diff --git a/nanosoc_tech b/nanosoc_tech
index a975485547e457621b7605d147b055833b5e67d5..e13c438900aad29d692c6b4201fee111326cb3a4 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit a975485547e457621b7605d147b055833b5e67d5
+Subproject commit e13c438900aad29d692c6b4201fee111326cb3a4
diff --git a/system/defines/pl230/pl230_defs.v b/system/defines/pl230/pl230_defs.v
deleted file mode 100644
index dcf4f1040e44f0b5ead58276a3367e5617e91c4a..0000000000000000000000000000000000000000
--- a/system/defines/pl230/pl230_defs.v
+++ /dev/null
@@ -1,189 +0,0 @@
-//-----------------------------------------------------------------------------
-// customised example Cortex-M0 controller DMA230 configuration
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright � 2021, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
-//
-// (C) COPYRIGHT 2006-2007 ARM Limited.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
-//
-// File Name : pl230_defs.v
-// Checked In : $Date: 2007-06-06 21:55:22 +0530 (Wed, 06 Jun 2007) $
-// Revision : $Revision: 13823 $
-// State : $state: PL230-DE-98007-r0p0-02rel0 $
-//
-//-----------------------------------------------------------------------------
-// Purpose : Peripheral specific macro definitions
-//
-//-----------------------------------------------------------------------------
-
-
-`ifdef ARM_TIMESCALE_DEFINED
- `timescale 1ns/1ps
-`endif
-
-// Set the number of channels implemented
-`define PL230_CHNLS 2
-`define PL230_CHNL_BITS 1
-//`define PL230_ONE_CHNL
-
-// Include Integration Test Logic
-`define PL230_INCLUDE_TEST
-
-
-// AHB Interface
-`define PL230_AHB_TRANS_IDLE 2'b00
-`define PL230_AHB_TRANS_NONSEQ 2'b10
-`define PL230_AHB_READ 1'b0
-`define PL230_AHB_WRITE 1'b1
-`define PL230_AHB_SIZE_BYTE 3'b000
-`define PL230_AHB_SIZE_HWORD 3'b001
-`define PL230_AHB_SIZE_WORD 3'b010
-
-// PrimeCell Configuration
-`define PL230_PERIPH_ID_0 8'h30
-`define PL230_PERIPH_ID_1 8'hB2
-`define PL230_PERIPH_ID_2 8'h0B
-`define PL230_PERIPH_ID_3 8'h00
-`define PL230_PERIPH_ID_4 8'h04
-`define PL230_PCELL_ID_0 8'h0D
-`define PL230_PCELL_ID_1 8'hF0
-`define PL230_PCELL_ID_2 8'h05
-`define PL230_PCELL_ID_3 8'hB1
-
-// Memory Mapped Registers
-// Controller Configuration Registers
-`define PL230_ADDR_DMA_STATUS 12'h000
-`define PL230_ADDR_DMA_CFG 12'h004
-`define PL230_ADDR_CTRL_BASE_PTR 12'h008
-`define PL230_ADDR_ALT_CTRL_BASE_PTR 12'h00C
-`define PL230_ADDR_DMA_WAITONREQ_STATUS 12'h010
-`define PL230_ADDR_CHNL_SW_REQUEST 12'h014
-`define PL230_ADDR_CHNL_USEBURST_SET 12'h018
-`define PL230_ADDR_CHNL_USEBURST_CLR 12'h01C
-`define PL230_ADDR_CHNL_REQ_MASK_SET 12'h020
-`define PL230_ADDR_CHNL_REQ_MASK_CLR 12'h024
-`define PL230_ADDR_CHNL_ENABLE_SET 12'h028
-`define PL230_ADDR_CHNL_ENABLE_CLR 12'h02C
-`define PL230_ADDR_CHNL_PRI_ALT_SET 12'h030
-`define PL230_ADDR_CHNL_PRI_ALT_CLR 12'h034
-`define PL230_ADDR_CHNL_PRIORITY_SET 12'h038
-`define PL230_ADDR_CHNL_PRIORITY_CLR 12'h03C
-// Reserved 12'h040
-// Reserved 12'h044
-// Reserved 12'h048
-`define PL230_ADDR_ERR_CLR 12'h04C
-// Integration Test Registers
-`define PL230_ADDR_INTEGRATION_CFG 12'hE00
-// Reserved 12'hE04
-`define PL230_ADDR_STALL_STATUS 12'hE08
-// Reserved 12'hE0C
-`define PL230_ADDR_DMA_REQ_STATUS 12'hE10
-// Reserved 12'hE14
-`define PL230_ADDR_DMA_SREQ_STATUS 12'hE18
-// Reserved 12'hE1C
-`define PL230_ADDR_DMA_DONE_SET 12'hE20
-`define PL230_ADDR_DMA_DONE_CLR 12'hE24
-`define PL230_ADDR_DMA_ACTIVE_SET 12'hE28
-`define PL230_ADDR_DMA_ACTIVE_CLR 12'hE2C
-// Reserved 12'hE30
-// Reserved 12'hE34
-// Reserved 12'hE38
-// Reserved 12'hE3C
-// Reserved 12'hE40
-// Reserved 12'hE44
-`define PL230_ADDR_ERR_SET 12'hE48
-// Reserved 12'hE4C
-// PrimeCell Configuration Registers
-`define PL230_ADDR_PERIPH_ID_4 12'hFD0
-// Reserved 12'hFD4
-// Reserved 12'hFD8
-// Reserved 12'hFDC
-`define PL230_ADDR_PERIPH_ID_0 12'hFE0
-`define PL230_ADDR_PERIPH_ID_1 12'hFE4
-`define PL230_ADDR_PERIPH_ID_2 12'hFE8
-`define PL230_ADDR_PERIPH_ID_3 12'hFEC
-`define PL230_ADDR_PCELL_ID_0 12'hFF0
-`define PL230_ADDR_PCELL_ID_1 12'hFF4
-`define PL230_ADDR_PCELL_ID_2 12'hFF8
-`define PL230_ADDR_PCELL_ID_3 12'hFFC
-
-
-// Bit vector definitions for channel_cfg
-`define PL230_CHANNEL_CFG_BITS 20
-// Destination address increment
-`define PL230_CHANNEL_CFG_DST_INC channel_cfg[19:18]
-`define PL230_HRDATA_DST_INC hrdata[31:30]
-// Destination transfer size
-// Source and destination sizes must match
-// so the same bits as the src_size are used
-`define PL230_CHANNEL_CFG_DST_SIZE channel_cfg[15:14]
-`define PL230_HRDATA_DST_SIZE hrdata[29:28]
-// Source address increment
-`define PL230_CHANNEL_CFG_SRC_INC channel_cfg[17:16]
-`define PL230_HRDATA_SRC_INC hrdata[27:26]
-// Source transfer size
-`define PL230_CHANNEL_CFG_SRC_SIZE channel_cfg[15:14]
-`define PL230_HRDATA_SRC_SIZE hrdata[25:24]
-// Destination AHB protection control
-`define PL230_CHANNEL_CFG_DST_PROT_CTRL channel_cfg[13:11]
-`define PL230_HRDATA_DST_PROT_CTRL hrdata[23:21]
-// Source AHB protection control
-`define PL230_CHANNEL_CFG_SRC_PROT_CTRL channel_cfg[10:8]
-`define PL230_HRDATA_SRC_PROT_CTRL hrdata[20:18]
-// Power of two transactions per request
-`define PL230_CHANNEL_CFG_R channel_cfg[7:4]
-`define PL230_HRDATA_R hrdata[17:14]
-// Number of bits in the N counter - hrdata[13:4]
-`define PL230_N_COUNT_BITS 10
-// Lsb bit offset for n_minus_1
-`define PL230_N_COUNT_OFFSET 4
-// Set chnl_useburst_status
-`define PL230_CHANNEL_CFG_NEXT_USEBURST channel_cfg[3]
-`define PL230_HRDATA_NEXT_USEBURST hrdata[3]
-// DMA cycle control
-`define PL230_CHANNEL_CFG_CYCLE_CTRL channel_cfg[2:0]
-`define PL230_HRDATA_CYCLE_CTRL hrdata[2:0]
-
-
-// Number of bits for the statemachine
-`define PL230_STATE_BITS 4
-// Statemachine state encoding
-`define PL230_ST_IDLE 4'h0
-`define PL230_ST_RD_CTRL 4'h1
-`define PL230_ST_RD_SPTR 4'h2
-`define PL230_ST_RD_DPTR 4'h3
-`define PL230_ST_RD_SDAT 4'h4
-`define PL230_ST_WR_DDAT 4'h5
-`define PL230_ST_WAIT 4'h6
-`define PL230_ST_WR_CTRL 4'h7
-`define PL230_ST_STALL 4'h8
-`define PL230_ST_DONE 4'h9
-`define PL230_ST_PSGP 4'hA
-`define PL230_ST_RESVD_0 4'hB
-`define PL230_ST_RESVD_1 4'hC
-`define PL230_ST_RESVD_2 4'hD
-`define PL230_ST_RESVD_3 4'hE
-`define PL230_ST_RESVD_4 4'hF
-
-`define PL230_SIZE_BYTE 2'b00
-`define PL230_SIZE_HWORD 2'b01
-`define PL230_SIZE_WORD 2'b10
-`define PL230_SIZE_RESVD 2'b11
-
-// pl230_defs.v end
diff --git a/system/defines/pl230/pl230_undefs.v b/system/defines/pl230/pl230_undefs.v
deleted file mode 100644
index 07223868feff9eff4930d29734b2b2e6292f6e38..0000000000000000000000000000000000000000
--- a/system/defines/pl230/pl230_undefs.v
+++ /dev/null
@@ -1,178 +0,0 @@
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from ARM Limited.
-//
-// (C) COPYRIGHT 2006-2007 ARM Limited.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from ARM Limited.
-//
-// File Name : pl230_undefs.v
-// Checked In : $Date: 2007-03-15 15:17:04 +0530 (Thu, 15 Mar 2007) $
-// Revision : $Revision: 10866 $
-// State : $state: PL230-DE-98007-r0p0-02rel0 $
-//
-//-----------------------------------------------------------------------------
-// Purpose : Undefine peripheral specific macro definitions
-//
-//-----------------------------------------------------------------------------
-
-
-
-
-
-
-// Set the number of channels implemented
-`undef PL230_CHNLS
-`undef PL230_CHNL_BITS
-`undef PL230_ONE_CHNL
-
-// Include Integration Test Logic
-`undef PL230_INCLUDE_TEST
-
-
-// AHB Interface
-`undef PL230_AHB_TRANS_IDLE
-`undef PL230_AHB_TRANS_NONSEQ
-`undef PL230_AHB_READ
-`undef PL230_AHB_WRITE
-`undef PL230_AHB_SIZE_BYTE
-`undef PL230_AHB_SIZE_HWORD
-`undef PL230_AHB_SIZE_WORD
-
-// PrimeCell Configuration
-`undef PL230_PERIPH_ID_0
-`undef PL230_PERIPH_ID_1
-`undef PL230_PERIPH_ID_2
-`undef PL230_PERIPH_ID_3
-`undef PL230_PERIPH_ID_4
-`undef PL230_PCELL_ID_0
-`undef PL230_PCELL_ID_1
-`undef PL230_PCELL_ID_2
-`undef PL230_PCELL_ID_3
-
-// Memory Mapped Registers
-// Controller Configuration Registers
-`undef PL230_ADDR_DMA_STATUS
-`undef PL230_ADDR_DMA_CFG
-`undef PL230_ADDR_CTRL_BASE_PTR
-`undef PL230_ADDR_ALT_CTRL_BASE_PTR
-`undef PL230_ADDR_DMA_WAITONREQ_STATUS
-`undef PL230_ADDR_CHNL_SW_REQUEST
-`undef PL230_ADDR_CHNL_USEBURST_SET
-`undef PL230_ADDR_CHNL_USEBURST_CLR
-`undef PL230_ADDR_CHNL_REQ_MASK_SET
-`undef PL230_ADDR_CHNL_REQ_MASK_CLR
-`undef PL230_ADDR_CHNL_ENABLE_SET
-`undef PL230_ADDR_CHNL_ENABLE_CLR
-`undef PL230_ADDR_CHNL_PRI_ALT_SET
-`undef PL230_ADDR_CHNL_PRI_ALT_CLR
-`undef PL230_ADDR_CHNL_PRIORITY_SET
-`undef PL230_ADDR_CHNL_PRIORITY_CLR
-// Reserved
-// Reserved
-// Reserved
-`undef PL230_ADDR_ERR_CLR
-// Integration Test Registers
-`undef PL230_ADDR_INTEGRATION_CFG
-// Reserved
-`undef PL230_ADDR_STALL_STATUS
-// Reserved
-`undef PL230_ADDR_DMA_REQ_STATUS
-// Reserved
-`undef PL230_ADDR_DMA_SREQ_STATUS
-// Reserved
-`undef PL230_ADDR_DMA_DONE_SET
-`undef PL230_ADDR_DMA_DONE_CLR
-`undef PL230_ADDR_DMA_ACTIVE_SET
-`undef PL230_ADDR_DMA_ACTIVE_CLR
-// Reserved
-// Reserved
-// Reserved
-// Reserved
-// Reserved
-// Reserved
-`undef PL230_ADDR_ERR_SET
-// Reserved
-// PrimeCell Configuration Registers
-`undef PL230_ADDR_PERIPH_ID_4
-// Reserved
-// Reserved
-// Reserved
-`undef PL230_ADDR_PERIPH_ID_0
-`undef PL230_ADDR_PERIPH_ID_1
-`undef PL230_ADDR_PERIPH_ID_2
-`undef PL230_ADDR_PERIPH_ID_3
-`undef PL230_ADDR_PCELL_ID_0
-`undef PL230_ADDR_PCELL_ID_1
-`undef PL230_ADDR_PCELL_ID_2
-`undef PL230_ADDR_PCELL_ID_3
-
-
-// Bit vector definitions for channel_cfg
-`undef PL230_CHANNEL_CFG_BITS
-// Destination address increment
-`undef PL230_CHANNEL_CFG_DST_INC
-`undef PL230_HRDATA_DST_INC
-// Destination transfer size
-// Source and destination sizes must match
-// so the same bits as the src_size are used
-`undef PL230_CHANNEL_CFG_DST_SIZE
-`undef PL230_HRDATA_DST_SIZE
-// Source address increment
-`undef PL230_CHANNEL_CFG_SRC_INC
-`undef PL230_HRDATA_SRC_INC
-// Source transfer size
-`undef PL230_CHANNEL_CFG_SRC_SIZE
-`undef PL230_HRDATA_SRC_SIZE
-// Destination AHB protection control
-`undef PL230_CHANNEL_CFG_DST_PROT_CTRL
-`undef PL230_HRDATA_DST_PROT_CTRL
-// Source AHB protection control
-`undef PL230_CHANNEL_CFG_SRC_PROT_CTRL
-`undef PL230_HRDATA_SRC_PROT_CTRL
-// Power of two transactions per request
-`undef PL230_CHANNEL_CFG_R
-`undef PL230_HRDATA_R
-// Number of bits in the N counter - hrdata[13:4]
-`undef PL230_N_COUNT_BITS
-// Lsb bit offset for n_minus_1
-`undef PL230_N_COUNT_OFFSET
-// Set chnl_useburst_status
-`undef PL230_CHANNEL_CFG_NEXT_USEBURST
-`undef PL230_HRDATA_NEXT_USEBURST
-// DMA cycle control
-`undef PL230_CHANNEL_CFG_CYCLE_CTRL
-`undef PL230_HRDATA_CYCLE_CTRL
-
-
-// Number of bits for the statemachine
-`undef PL230_STATE_BITS
-// Statemachine state encoding
-`undef PL230_ST_IDLE
-`undef PL230_ST_RD_CTRL
-`undef PL230_ST_RD_SPTR
-`undef PL230_ST_RD_DPTR
-`undef PL230_ST_RD_SDAT
-`undef PL230_ST_WR_DDAT
-`undef PL230_ST_WAIT
-`undef PL230_ST_WR_CTRL
-`undef PL230_ST_STALL
-`undef PL230_ST_DONE
-`undef PL230_ST_PSGP
-`undef PL230_ST_RESVD_0
-`undef PL230_ST_RESVD_1
-`undef PL230_ST_RESVD_2
-`undef PL230_ST_RESVD_3
-`undef PL230_ST_RESVD_4
-
-`undef PL230_SIZE_BYTE
-`undef PL230_SIZE_HWORD
-`undef PL230_SIZE_WORD
-`undef PL230_SIZE_RESVD
-
-// pl230_undefs.v end
diff --git a/wrapper/regs/cregs.csv b/wrapper/regs/cregs.csv
deleted file mode 100644
index c68d8e50d14cf0175dfaf88bbf9b0a18bee5b30f..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs.csv
+++ /dev/null
@@ -1,5 +0,0 @@
-name idx nbits start access test rval desc
-
-# Wrapper Control Register
-accelerator_en 0 32 0 rw 0 0x00000000 Accelerator Enable Register
-accelerator_channel_en 1 32 0 rw 0 0x00000000 Accelerator Channel Enable Register
\ No newline at end of file
diff --git a/wrapper/regs/cregs/CREGS.h b/wrapper/regs/cregs/CREGS.h
deleted file mode 100644
index 03b467eacbb96e4976e6acf1f83b6ca41610f727..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/CREGS.h
+++ /dev/null
@@ -1,16 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-#ifndef CREGS_H
-#define CREGS_H
-
-
-typedef struct
-{
- __IO uint32_t ACCELERATOR_EN; /* Offset: 0x0 (R/W) Accelerator Enable Register */
- __IO uint32_t ACCELERATOR_CHANNEL_EN; /* Offset: 0x4 (R/W) Accelerator Channel Enable Register */
-} CREGS_TypeDef;
-
-#endif
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.inst.sv b/wrapper/regs/cregs/cregs.inst.sv
deleted file mode 100644
index 1ad2ed0a83a321531c11248a382bfbff11e8a078..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.inst.sv
+++ /dev/null
@@ -1,24 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-// START
-logic [31:0] accelerator_en;
-logic [31:0] accelerator_channel_en;
-
-cregs u_cregs (
-
-// clocks and resets
-.clk(pclk),
-.rstn(presetn),
-
-// Synchronous register interface
-.regbus (cregs.sink),
-
-// reg file signals
-.accelerator_en(accelerator_en[31:0]) /* idx 0 */,
-.accelerator_channel_en(accelerator_channel_en[31:0]) /* idx 1 */
-
-);
-// END
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.md b/wrapper/regs/cregs/cregs.md
deleted file mode 100644
index 9e3b82cb35ffeb7efa4fc4aff652b15099b6c5a8..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.md
+++ /dev/null
@@ -1,15 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-# Programmers Model
-
-## Module: CREGS
-
-| Address Offset | Signal Name | Access | Bit width | Start bit | Description |
-| --- | --- | --- | --- | --- | --- |
-|
-| 0x0 | **ACCELERATOR_EN** | RW | 32 | 0 | Accelerator Enable Register |
-| 0x4 | **ACCELERATOR_CHANNEL_EN** | RW | 32 | 0 | Accelerator Channel Enable Register |
-
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.py b/wrapper/regs/cregs/cregs.py
deleted file mode 100644
index de7171d029c45a3c54f1d3bc642e94ae5c8eb5bd..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.py
+++ /dev/null
@@ -1,15 +0,0 @@
-# // VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-class Cregs(object):
-
- def __init__(self,base_offset):
- self.base_offset = base_offset
-
-
- self.ACCELERATOR_EN = self.base_offset + 0x0 # Accelerator Enable Register
- self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
- self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
-
-
-# // VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.sv b/wrapper/regs/cregs/cregs.sv
deleted file mode 100644
index 8c1d454e0d75f8fd4a6516ca743defa770529d2c..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.sv
+++ /dev/null
@@ -1,138 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-//-----------------------------------------------------------------------------
-// SoC Labs APB register Template
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// VGEN: HEADER
-// Register file contents:
-//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
-//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
-
-
-// VGEN: MODULE NAME
-module cregs (
-
-// clocks and resets
- input logic clk,
- input logic rstn,
-
-// APB inteface
- input logic psel,
- input logic [ADDRWIDTH:0] paddr,
- input logic penable,
- input logic pwrite,
- input logic [31:0] pwdata,
-
- output logic [31:0] prdata,
- output logic pready,
- output logic pslverr,
-
-// VGEN: INPUTS TO REGS
-
-
-// VGEN: OUTPUTS FROM REGS
- output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
- output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
-
-);
-
-//------------------------------------------------------------------------------
-// APB Interface
-//------------------------------------------------------------------------------
-
-logic [ADDRWIDTH-1:0] addr;
-logic read_en;
-logic write_en;
-logic [31:0] wdata;
-logic [31:0] rdata;
-
-// APB interface
-assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
-assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
-
-
-// register read and write signal
-assign addr = paddr;
-assign read_en = psel & (~pwrite); // assert for whole apb read transfer
-assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
- // It is also possible to change the design to perform the write in the 2nd
- // APB cycle. E.g.
- // assign write_en = psel & penable & pwrite;
- // However, if the design generate waitstate, this expression will result
- // in write_en being asserted for multiple cycles.
-assign wdata = pwdata;
-assign prdata = rdata;
-
-//------------------------------------------------------------------------------
-// Regsiter write
-//------------------------------------------------------------------------------
-
-// VGEN: REG WRITE
-// idx #0
-logic [31:0] accelerator_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_en[31:0] = accelerator_en_reg[31:0];
-
-// idx #1
-logic [31:0] accelerator_channel_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_channel_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
-
-
-
-//------------------------------------------------------------------------------
-// Regsiter read
-//------------------------------------------------------------------------------
-
-
-logic [31:0] rdata_o;
-
-always @*
-begin
- if (read_en)
- begin
- rdata_o[31:0] = 32'h00000000;
-
- // VGEN: REG READ
- if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
- if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
-
- end
- else
- begin
- rdata_o[31:0] = {32'h00000000};
- end
-end
-
-assign rdata[31:0] = rdata_o[31:0];
-
-
-//------------------------------------------------------------------------------
-//
-//------------------------------------------------------------------------------
-
-
-
-
-endmodule
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs.sv.bak b/wrapper/regs/cregs/cregs.sv.bak
deleted file mode 100644
index d0ca98a27542bd6c55bb388c49d4e712213edec3..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs.sv.bak
+++ /dev/null
@@ -1,139 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
-
-//-----------------------------------------------------------------------------
-// SoC Labs APB register Template
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// VGEN: HEADER
-// Register file contents:
-//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
-//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
-
-
-
-// VGEN: MODULE NAME
-module cregs (
-
-// clocks and resets
- input logic clk,
- input logic rstn,
-
-// APB inteface
- input logic psel,
- input logic [ADDRWIDTH:0] paddr,
- input logic penable,
- input logic pwrite,
- input logic [31:0] pwdata,
-
- output logic [31:0] prdata,
- output logic pready,
- output logic pslverr,
-
-// VGEN: INPUTS TO REGS
-
-
-// VGEN: OUTPUTS FROM REGS
- output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
- output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
-
-);
-
-//------------------------------------------------------------------------------
-// APB Interface
-//------------------------------------------------------------------------------
-
-logic [ADDRWIDTH-1:0] addr;
-logic read_en;
-logic write_en;
-logic [31:0] wdata;
-logic [31:0] rdata;
-
-// APB interface
-assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
-assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
-
-
-// register read and write signal
-assign addr = paddr;
-assign read_en = psel & (~pwrite); // assert for whole apb read transfer
-assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
- // It is also possible to change the design to perform the write in the 2nd
- // APB cycle. E.g.
- // assign write_en = psel & penable & pwrite;
- // However, if the design generate waitstate, this expression will result
- // in write_en being asserted for multiple cycles.
-assign wdata = pwdata;
-assign prdata = rdata;
-
-//------------------------------------------------------------------------------
-// Regsiter write
-//------------------------------------------------------------------------------
-
-// VGEN: REG WRITE
-// idx #0
-logic [31:0] accelerator_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_en[31:0] = accelerator_en_reg[31:0];
-
-// idx #1
-logic [31:0] accelerator_channel_en_reg;
-always@(posedge clk or negedge rstn) begin
- if(~rstn) begin
- accelerator_channel_en_reg[31:0] <= '0;
- end else begin
- if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
- end
-end
-assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
-
-
-
-//------------------------------------------------------------------------------
-// Regsiter read
-//------------------------------------------------------------------------------
-
-
-logic [31:0] rdata_o;
-
-always @*
-begin
- if (read_en)
- begin
- rdata_o[31:0] = 32'h00000000;
-
- // VGEN: REG READ
- if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
- if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
-
- end
- else
- begin
- rdata_o[31:0] = {32'h00000000};
- end
-end
-
-assign rdata[31:0] = rdata_o[31:0];
-
-
-//------------------------------------------------------------------------------
-//
-//------------------------------------------------------------------------------
-
-
-
-
-endmodule
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs_test.c b/wrapper/regs/cregs/cregs_test.c
deleted file mode 100644
index 1e1345d7773956524a5ba397ef41b8a52ff3f2ec..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs_test.c
+++ /dev/null
@@ -1,36 +0,0 @@
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-#include "cregs_test.h"
-
-// This test is intended to check initial (reset) values of registers
-int cregs_initial_value_test(void) {
- int num_errors=0;
-
- if (SM2_CREGS->ACCELERATOR_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");}
- if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");}
-
-
- return num_errors;
-
-}
-
-// This test is intended to check write read to registers
-int cregs_write_read_test(void) {
- int num_errors=0;
-
- SM2_CREGS->ACCELERATOR_EN = 0xFFFFFFFF; // write all-1s
- if (SM2_CREGS->ACCELERATOR_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-1s
- SM2_CREGS->ACCELERATOR_EN = 0x0; // clear field
- if (SM2_CREGS->ACCELERATOR_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-0s
- SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0xFFFFFFFF; // write all-1s
- if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-1s
- SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0x0; // clear field
- if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-0s
-
-
- return num_errors;
-
-}
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/regs/cregs/cregs_test.h b/wrapper/regs/cregs/cregs_test.h
deleted file mode 100644
index eaafa6d2e5aff0be80ce411ad90268044ae87081..0000000000000000000000000000000000000000
--- a/wrapper/regs/cregs/cregs_test.h
+++ /dev/null
@@ -1,18 +0,0 @@
-// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
-#ifndef CREGS_TEST_H
-#define CREGS_TEST_H
-
-
-#include "SM2_CM0.h"
-
-// This test is intended to check initial (reset) values of registers
-int cregs_initial_value_test(void);
-
-// This test is intended to check write and read to registers
-int cregs_write_read_test(void);
-
-#endif
-
-// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
-
diff --git a/wrapper/src/wrapper_accelerator.sv b/wrapper/src/wrapper_accelerator.sv
deleted file mode 100644
index e90ddf717e35f9f5cf256b24335a20a3f816a0b8..0000000000000000000000000000000000000000
--- a/wrapper/src/wrapper_accelerator.sv
+++ /dev/null
@@ -1,522 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Example Accelerator Wrapper
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module wrapper_accelerator #(
- parameter AHBADDRWIDTH=12,
- parameter INPACKETWIDTH=512,
- parameter CFGSIZEWIDTH=64,
- parameter CFGSCHEMEWIDTH=2,
- parameter OUTPACKETWIDTH=256
- ) (
- input logic HCLK, // Clock
- input logic HRESETn, // Reset
-
- // AHB connection to Initiator
- input logic HSELS,
- input logic [AHBADDRWIDTH-1:0] HADDRS,
- input logic [1:0] HTRANSS,
- input logic [2:0] HSIZES,
- input logic [3:0] HPROTS,
- input logic HWRITES,
- input logic HREADYS,
- input logic [31:0] HWDATAS,
-
- output logic HREADYOUTS,
- output logic HRESPS,
- output logic [31:0] HRDATAS,
-
- // Input Data Request Signal to DMAC
- output logic in_data_req,
-
- // Output Data Request Signal to DMAC
- output logic out_data_req
- );
-
-
- //**********************************************************
- // Internal AHB Parameters
- //**********************************************************
-
- // Input Port Parameters
- localparam [AHBADDRWIDTH-1:0] INPORTADDR = 'h000;
- localparam INPORTAHBADDRWIDTH = AHBADDRWIDTH - 2;
-
- // Output Port Parameters
- localparam [AHBADDRWIDTH-1:0] OUTPORTADDR = 'h400;
- localparam OUTPORTAHBADDRWIDTH = AHBADDRWIDTH - 2;
-
- localparam OUTPACKETBYTEWIDTH = $clog2(OUTPACKETWIDTH/8); // Number of Bytes in Packet
- localparam OUTPACKETSPACEWIDTH = OUTPORTAHBADDRWIDTH-OUTPACKETBYTEWIDTH; // Number of Bits to represent all Packets in Address Space
-
- // Control and Status Register Parameters
- localparam [AHBADDRWIDTH-1:0] CSRADDR = 'h800;
- localparam CSRADDRWIDTH = AHBADDRWIDTH - 2;
-
- //**********************************************************
- // Wrapper AHB Components
- //**********************************************************
-
- //----------------------------------------------------------
- // Internal AHB Decode Logic
- //----------------------------------------------------------
-
- // AHB Target 0 - Engine Input Port
- logic hsel0;
- logic hreadyout0;
- logic hresp0;
- logic [31:0] hrdata0;
-
- // AHB Target 1 - Engine Output Port
- logic hsel1;
- logic hreadyout1;
- logic hresp1;
- logic [31:0] hrdata1;
-
- // AHB Target 2 - CSRs
- logic hsel2;
- logic hreadyout2;
- logic hresp2;
- logic [31:0] hrdata2;
-
- // AHB Target 3 - Default Target
- logic hsel3;
- logic hreadyout3;
- logic hresp3;
- logic [31:0] hrdata3;
-
- // Internal AHB Address Assignment
- assign hsel0 = ((HADDRS < OUTPORTADDR) && (HADDRS >= INPORTADDR)) ? 1'b1:1'b0; // Input Port Select
- assign hsel1 = ((HADDRS < CSRADDR) && (HADDRS >= OUTPORTADDR)) ? 1'b1:1'b0; // Output Port Select
- assign hsel2 = (HADDRS >= CSRADDR) ? 1'b1:1'b0; // CSR Select
- assign hsel3 = (hsel0 | hsel1 | hsel2) ? 1'b0:1'b1; // Default Target Select
-
- // AHB Target Multiplexer
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (HREADYS),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (hsel2), // Input Port 2
- .HREADYOUT2 (hreadyout2),
- .HRESP2 (hresp2),
- .HRDATA2 (hrdata2),
- .HSEL3 (hsel3), // Input Port 3
- .HREADYOUT3 (hreadyout3),
- .HRESP3 (hresp3),
- .HRDATA3 (hrdata3),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (HREADYOUTS), // Outputs
- .HRESP (HRESPS),
- .HRDATA (HRDATAS)
- );
-
- //----------------------------------------------------------
- // Input Port Logic
- //----------------------------------------------------------
-
- // Engine Input Port Wire declarations
- logic [INPACKETWIDTH-1:0] in_packet;
- logic in_packet_last;
- logic in_packet_valid;
- logic in_packet_ready;
-
- // DMA
- logic in_dma_req_act;
-
- // Packet Constructor Instantiation
- wrapper_ahb_packet_constructor #(
- INPORTAHBADDRWIDTH,
- INPACKETWIDTH
- ) u_wrapper_data_input_port (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .hsels (hsel0),
- .haddrs (HADDRS[INPORTAHBADDRWIDTH-1:0]),
- .htranss (HTRANSS),
- .hsizes (HSIZES),
- .hwrites (HWRITES),
- .hreadys (HREADYS),
- .hwdatas (HWDATAS),
-
- .hreadyouts (hreadyout0),
- .hresps (hresp0),
- .hrdatas (hrdata0),
-
- // Valid/Ready Interface
- .packet_data (in_packet),
- .packet_data_last (in_packet_last),
- .packet_data_valid (in_packet_valid),
- .packet_data_ready (in_packet_ready),
-
- // Input Data Request
- .data_req (in_dma_req_act)
- );
-
- //----------------------------------------------------------
- // Configuration Port Logic
- //----------------------------------------------------------
-
- // Engine Configuration Port Wire declarations
- logic [CFGSIZEWIDTH-1:0] cfg_size;
- logic [CFGSCHEMEWIDTH-1:0] cfg_scheme;
- logic cfg_last;
- logic cfg_valid;
- logic cfg_ready;
-
- // Engine Configuration Port Tied-off to fixed values
- assign cfg_size = 64'd512;
- assign cfg_scheme = 2'd0;
- assign cfg_last = 1'b1;
- assign cfg_valid = 1'b1;
-
- //----------------------------------------------------------
- // Output Port Logic
- //----------------------------------------------------------
-
- // Engine Output Port Wire declarations
- logic [OUTPACKETWIDTH-1:0] out_hash;
- logic out_hash_last;
- logic [OUTPACKETSPACEWIDTH-1:0] out_hash_remain;
- logic out_hash_valid;
- logic out_hash_ready;
-
-
- // Relative Read Address for Start of Current Block
- logic [OUTPORTAHBADDRWIDTH-1:0] block_read_addr;
-
- // DMA Request Line
- logic out_dma_req_act;
-
- // Packet Deconstructor Instantiation
- wrapper_ahb_packet_deconstructor #(
- OUTPORTAHBADDRWIDTH,
- OUTPACKETWIDTH
- ) u_wrapper_data_output_port (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .hsels (hsel1),
- .haddrs (HADDRS[OUTPORTAHBADDRWIDTH-1:0]),
- .htranss (HTRANSS),
- .hsizes (HSIZES),
- .hwrites (HWRITES),
- .hreadys (HREADYS),
- .hwdatas (HWDATAS),
-
- .hreadyouts (hreadyout1),
- .hresps (hresp1),
- .hrdatas (hrdata1),
-
- // Valid/Ready Interface
- .packet_data (out_hash),
- .packet_data_last (out_hash_last),
- .packet_data_remain (out_hash_remain),
- .packet_data_valid (out_hash_valid),
- .packet_data_ready (out_hash_ready),
-
- // Input Data Request
- .data_req (out_dma_req_act),
-
- // Read Address Interface
- .block_read_addr (block_read_addr)
- );
-
- //----------------------------------------------------------
- // Wrapper Control and Staus Registers
- //----------------------------------------------------------
-
- // CSR APB wiring logic
- logic [CSRADDRWIDTH-1:0] CSRPADDR;
- logic CSRPENABLE;
- logic CSRPWRITE;
- logic [3:0] CSRPSTRB;
- logic [2:0] CSRPPROT;
- logic [31:0] CSRPWDATA;
- logic CSRPSEL;
-
- logic CSRAPBACTIVE;
- logic [31:0] CSRPRDATA;
- logic CSRPREADY;
- logic CSRPSLVERR;
-
- // CSR register wiring logic
- logic [CSRADDRWIDTH-1:0] csr_reg_addr;
- logic csr_reg_read_en;
- logic csr_reg_write_en;
- logic [31:0] csr_reg_wdata;
- logic [31:0] csr_reg_rdata;
-
- // AHB to APB Bridge
- cmsdk_ahb_to_apb #(
- CSRADDRWIDTH
- ) u_csr_ahb_apb_bridge (
- .HCLK (HCLK), // Clock
- .HRESETn (HRESETn), // Reset
- .PCLKEN (1'b1), // APB clock enable signal
-
- .HSEL (hsel2), // Device select
- .HADDR (HADDRS[CSRADDRWIDTH-1:0]), // Address
- .HTRANS (HTRANSS), // Transfer control
- .HSIZE (HSIZES), // Transfer size
- .HPROT (4'b1111), // Protection control
- .HWRITE (HWRITES), // Write control
- .HREADY (HREADYS), // Transfer phase done
- .HWDATA (HWDATAS), // Write data
-
- .HREADYOUT (hreadyout2), // Device ready
- .HRDATA (hrdata2), // Read data output
- .HRESP (hresp2), // Device response
-
- // APB Output
- .PADDR (CSRPADDR), // APB Address
- .PENABLE (CSRPENABLE), // APB Enable
- .PWRITE (CSRPWRITE), // APB Write
- .PSTRB (CSRPSTRB), // APB Byte Strobe
- .PPROT (CSRPPROT), // APB Prot
- .PWDATA (CSRPWDATA), // APB write data
- .PSEL (CSRPSEL), // APB Select
-
- .APBACTIVE (CSRAPBACTIVE), // APB bus is active, for clock gating
- // of APB bus
-
- // APB Input
- .PRDATA (CSRPRDATA), // Read data for each APB slave
- .PREADY (CSRPREADY), // Ready for each APB slave
- .PSLVERR (CSRPSLVERR) // Error state for each APB slave
- );
-
- // APB to Register Interface
- cmsdk_apb3_eg_slave_interface #(
- CSRADDRWIDTH
- ) u_csr_reg_inf (
-
- .pclk (HCLK), // pclk
- .presetn (HRESETn), // reset
-
- .psel (CSRPSEL), // apb interface inputs
- .paddr (CSRPADDR),
- .penable (CSRPENABLE),
- .pwrite (CSRPWRITE),
- .pwdata (CSRPWDATA),
-
- .prdata (CSRPRDATA), // apb interface outputs
- .pready (CSRPREADY),
- .pslverr (CSRPSLVERR),
-
- // Register interface
- .addr (csr_reg_addr),
- .read_en (csr_reg_read_en),
- .write_en (csr_reg_write_en),
- .wdata (csr_reg_wdata),
- .rdata (csr_reg_rdata)
- );
-
- logic ctrl_reg_write_en, ctrl_reg_read_en;
- assign ctrl_reg_write_en = csr_reg_write_en & (csr_reg_addr < 10'h100);
- assign ctrl_reg_read_en = csr_reg_read_en & (csr_reg_addr < 10'h100);
- // // Example Register Block
- // cmsdk_apb3_eg_slave_reg #(
- // CSRADDRWIDTH
- // ) u_csr_block (
- // .pclk (HCLK),
- // .presetn (HRESETn),
-
- // // Register interface
- // .addr (csr_reg_addr),
- // .read_en (csr_reg_read_en),
- // .write_en (csr_reg_write_en),
- // .wdata (csr_reg_wdata),
- // .ecorevnum (4'd0),
- // .rdata (csr_reg_rdata)
- // );
-
- //----------------------------------------------------------
- // Default AHB Target Logic
- //----------------------------------------------------------
-
- // AHB Default Target Instantiation
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel3),
- .HTRANS (HTRANSS),
- .HREADY (HREADYS),
- .HREADYOUT (hreadyout3),
- .HRESP (hresp3)
- );
-
- // Default Targets Data is tied off
- assign hrdata3 = {32{1'b0}};
-
- //**********************************************************
- // Wrapper Interrupt Generation
- //**********************************************************
-
- // TODO: Instantiate IRQ Generator
-
- //**********************************************************
- // Wrapper DMA Data Request Generation
- //**********************************************************
-
- wrapper_req_ctrl_reg #(
- CSRADDRWIDTH
- ) u_wrapper_req_ctrl_reg (
- .hclk (HCLK),
- .hresetn (HRESETn),
- .addr (csr_reg_addr),
- .read_en (ctrl_reg_read_en),
- .write_en (ctrl_reg_write_en),
- .wdata (csr_reg_wdata),
- .rdata (csr_reg_rdata),
-
- // Data Transfer Request Signaling
- .req_act_ch0 (in_dma_req_act),
- .req_act_ch1 (out_dma_req_act),
- .req_act_ch2 (1'b0),
- .req_act_ch3 (1'b0),
- .req_act_ch4 (1'b0),
-
- // DMA Request Output
- .drq_ch0 (in_data_req),
- .drq_ch1 (out_data_req),
- .drq_ch2 (),
- .drq_ch3 (),
- .drq_ch4 (),
-
- // Interrupt Request Output
- .irq_ch0 (),
- .irq_ch1 (),
- .irq_ch2 (),
- .irq_ch3 (),
- .irq_ch4 (),
- .irq_merged ()
- );
-
- //**********************************************************
- // Accelerator Engine
- //**********************************************************
-
- //----------------------------------------------------------
- // Accelerator Engine Logic
- //----------------------------------------------------------
-
- logic out_digest_valid;
-
- // Engine Output Port Wire declarations
- logic [OUTPACKETWIDTH-1:0] out_packet;
- logic out_packet_last;
- logic [OUTPACKETSPACEWIDTH-1:0] out_packet_remain;
- logic out_packet_valid;
- logic out_packet_ready;
-
- // Block Packets Remaining Tie-off (only ever one packet per block)
- assign out_packet_remain = {OUTPACKETSPACEWIDTH{1'b0}};
-
- // Hashing Accelerator Instatiation
- wrapper_valid_filter u_valid_filter (
- .clk (HCLK),
- .rst (~HRESETn),
-
- // Data in Channel
- .data_in_valid (in_packet_valid),
- .data_in_ready (in_packet_ready),
- .data_in_last (in_packet_last),
-
- // Data Out Channel
- .data_out_valid (out_digest_valid),
- .payload_out_valid (out_packet_valid)
- );
-
-
- // Hashing Accelerator Instatiation
- sha256_stream u_sha256_stream (
- .clk (HCLK),
- .rst (~HRESETn),
- .mode (1'b1),
-
- // Data in Channel
- .s_tdata_i (in_packet),
- .s_tvalid_i (in_packet_valid),
- .s_tready_o (in_packet_ready),
- .s_tlast_i (in_packet_last),
-
- // Data Out Channel
- .digest_o (out_packet),
- .digest_valid_o (out_digest_valid)
- );
-
- assign out_packet_last = 1'b1;
-
- // Output FIFO (Output has no handshaking)
- fifo_vr #(
- 4,
- 256
- ) u_output_fifo (
- .clk (HCLK),
- .nrst (HRESETn),
- .en (1'b1),
- .sync_rst (1'b0),
- .data_in (out_packet),
- .data_in_last (out_packet_last),
- .data_in_valid (out_packet_valid),
- .data_in_ready (),
- .data_out (out_hash),
- .data_out_valid (out_hash_valid),
- .data_out_ready (out_hash_ready),
- .data_out_last (out_hash_last),
- .status_ptr_dif ()
- );
-endmodule
diff --git a/wrapper/stimulus/ahb_input_hash_stim.fri b/wrapper/stimulus/ahb_input_hash_stim.fri
deleted file mode 100644
index a34d700c550156ba611e7d1773f8cddbf61c1392..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/ahb_input_hash_stim.fri
+++ /dev/null
@@ -1,273 +0,0 @@
-;#-----------------------------------------------------------------------------
-;# SoC Labs Basic Hashing Accelerator Wrapper Input Stimulus File
-;# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-;#
-;# Contributors
-;#
-;# David Mapstone (d.a.mapstone@soton.ac.uk)
-;#
-;# Copyright 2023, SoC Labs (www.soclabs.org)
-;#-----------------------------------------------------------------------------
-;Transaction Address Data Size
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-W 0x60010384 0x0e3109cc word
-W 0x60010388 0xc4411b41 word
-W 0x6001038c 0x5349fe99 word
-W 0x60010390 0xbc3bdfc1 word
-W 0x60010394 0xdeb5cb2a word
-W 0x60010398 0xa0052ca2 word
-W 0x6001039c 0x1761b000 word
-W 0x600103a0 0x1b5affff word
-W 0x600103a4 0xeab53b7e word
-W 0x600103a8 0x81152f06 word
-W 0x600103ac 0x7d60ab33 word
-W 0x600103b0 0x1ce3c906 word
-W 0x600103b4 0x707476fe word
-W 0x600103b8 0x923737f4 word
-W 0x600103bc 0x695b2443 word
-W 0x600103c0 0x00000200 word
-W 0x600103fc 0x80000000 word
-R 0x60010810 0x00000000 word
-R 0x600107e0 0xe06f1bef word
-R 0x600107e4 0xf498916a word
-R 0x600107e8 0x4686ebb1 word
-R 0x600107ec 0x0dc803e5 word
-R 0x600107f0 0x960ea091 word
-R 0x600107f4 0xeb558be4 word
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-R 0x600107fc 0xe1711626 word
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-W 0x600103b8 0xfe2518c8 word
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-W 0x600103fc 0x80000000 word
-R 0x600107e0 0x1f335cad word
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-W 0x60010384 0x6e6a3d49 word
-W 0x60010388 0xe7f1461f word
-W 0x6001038c 0xc6f4b35f word
-W 0x60010390 0xf82a46d6 word
-W 0x60010394 0x440244f5 word
-W 0x60010398 0x6bde0ef1 word
-W 0x6001039c 0xb0787487 word
-W 0x600103a0 0x1a96af96 word
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-W 0x600103a8 0xea97471c word
-W 0x600103ac 0x35bad402 word
-W 0x600103b0 0xb3733250 word
-W 0x600103b4 0x75028929 word
-W 0x600103b8 0x230c2b19 word
-W 0x600103bc 0x0bfe6ea9 word
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-W 0x600103fc 0x80000000 word
-R 0x600107e0 0x0b51e243 word
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-R 0x600107f0 0x7f6590f6 word
-R 0x600107f4 0x479570fd word
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-W 0x60010384 0x9193267a word
-W 0x60010388 0xc3f24d94 word
-W 0x6001038c 0xb295566e word
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-W 0x600103a0 0x45b0e216 word
-W 0x600103a4 0xdb750cbb word
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-W 0x600103ac 0xd67d1bbd word
-W 0x600103b0 0x24fdf316 word
-W 0x600103b4 0x0650c084 word
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-W 0x600103c0 0x00000200 word
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-R 0x600107e0 0x6d572f08 word
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-R 0x600107ec 0xa5ae48a8 word
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-R 0x600107f4 0xc555cde2 word
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-W 0x60010380 0x387dc590 word
-W 0x60010384 0x2966f6a3 word
-W 0x60010388 0xadd14662 word
-W 0x6001038c 0x0bc2175e word
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-W 0x60010394 0x335c30a8 word
-W 0x60010398 0x50e7e900 word
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-W 0x600103ac 0x48879677 word
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-W 0x600103bc 0xefdf5963 word
-W 0x600103c0 0x00000200 word
-W 0x600103fc 0x80000000 word
-R 0x600107e0 0x24eb65ee word
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-R 0x600107e8 0xaf5d19d2 word
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-W 0x60010380 0x2a22cd0b word
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-W 0x60010388 0xd3a5b873 word
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-W 0x60010394 0x59a1ee9a word
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-W 0x6001039c 0xedf99c9c word
-W 0x600103a0 0x47ab7368 word
-W 0x600103a4 0xa0eddacc word
-W 0x600103a8 0xe218002f word
-W 0x600103ac 0x1498319a word
-W 0x600103b0 0xb1f10e58 word
-W 0x600103b4 0x8d03ecb0 word
-W 0x600103b8 0x4408ab12 word
-W 0x600103bc 0xcabcc637 word
-W 0x600103c0 0x00000200 word
-W 0x600103fc 0x80000000 word
-R 0x600107e0 0x5951566a word
-R 0x600107e4 0xb8a4b430 word
-R 0x600107e8 0x9fe9980d word
-R 0x600107ec 0x80069d04 word
-R 0x600107f0 0x093d866f word
-R 0x600107f4 0x7af5e3f6 word
-R 0x600107f8 0xcc432473 word
-R 0x600107fc 0x090f1978 word
-Q
\ No newline at end of file
diff --git a/wrapper/stimulus/ahb_input_hash_stim.m2d b/wrapper/stimulus/ahb_input_hash_stim.m2d
deleted file mode 100644
index bd56970de251b776173764ea640dcbe5435e707d..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/ahb_input_hash_stim.m2d
+++ /dev/null
@@ -1,1468 +0,0 @@
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-00440001
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-10440001
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-00000000
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-10440001
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-10440001
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-10440001
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-00440001
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-00440001
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-00440001
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-00440001
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-00440001
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-00000200
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-00440001
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-10440001
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-10440001
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-1623b2c9
-00000000
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-00000000
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-10440001
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-9d3c0a90
-00000000
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-
-10440001
-600107ec
-ce34de30
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-FFFFFFFF
-00000000
-
-10440001
-600107f0
-00000000
-72fc05c5
-00000000
-FFFFFFFF
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-10440001
-600107f4
-cf65fdbb
-00000000
-FFFFFFFF
-00000000
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-10440001
-600107f8
-00000000
-ef598a6e
-00000000
-FFFFFFFF
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-10440001
-600107fc
-58d6d30f
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-FFFFFFFF
-00000000
-
-00440001
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-00000000
-28b3253a
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-00440001
-60010384
-96dbf9e5
-00000000
-
-00440001
-60010388
-00000000
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-00440001
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-6bbbc74a
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-00440001
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-00000000
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-00440001
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-00440001
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-00440001
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-00440001
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-80000000
-00000000
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-10440001
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-e4e3afb2
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-10440001
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diff --git a/wrapper/stimulus/input_block_32bit_stim.csv b/wrapper/stimulus/input_block_32bit_stim.csv
deleted file mode 100644
index 3d6bce9ce480ea51c66206dc67ec9a295b6af1a0..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/input_block_32bit_stim.csv
+++ /dev/null
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-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-80000000,1,1
-2a22cd0b,0,0
-f570eb78,0,0
-d3a5b873,0,0
-53d7f89b,0,0
-ebedc242,0,0
-59a1ee9a,0,0
-cea792f4,0,0
-edf99c9c,0,0
-47ab7368,0,0
-a0eddacc,0,0
-e218002f,0,0
-1498319a,0,0
-b1f10e58,0,0
-8d03ecb0,0,0
-4408ab12,0,0
-cabcc637,1,0
-00000200,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-00000000,0,1
-80000000,1,1
diff --git a/wrapper/stimulus/output_hash_32bit_ref.csv b/wrapper/stimulus/output_hash_32bit_ref.csv
deleted file mode 100644
index 76655dd804a388379f79c7d165575c0e54a31bb5..0000000000000000000000000000000000000000
--- a/wrapper/stimulus/output_hash_32bit_ref.csv
+++ /dev/null
@@ -1,80 +0,0 @@
-e06f1bef,0,1
-f498916a,0,1
-4686ebb1,0,1
-dc803e5 ,0,1
-960ea091,0,1
-eb558be4,0,1
-e14c46de,0,1
-e1711626,1,1
-d065f05e,0,1
-1623b2c9,0,1
-9d3c0a90,0,1
-ce34de30,0,1
-72fc05c5,0,1
-cf65fdbb,0,1
-ef598a6e,0,1
-58d6d30f,1,1
-e4e3afb2,0,1
-a3be45c9,0,1
-b43f0fa3,0,1
-56fcb65d,0,1
-bbf2982b,0,1
-15cd68c7,0,1
-cc9f9269,0,1
-ed646faf,1,1
-ad5d7f58,0,1
-c619f73f,0,1
-5a54de49,0,1
-38b0529 ,0,1
-92343513,0,1
-ea3cf2a9,0,1
-5a1b530b,0,1
-49393b4e,1,1
-105755f3,0,1
-1ca8459e,0,1
-8ffade5 ,0,1
-29a2e390,0,1
-c6905543,0,1
-5ed0766b,0,1
-9a63b562,0,1
-95262422,1,1
-1f335cad,0,1
-7d8c6b58,0,1
-cb265158,0,1
-ee44b230,0,1
-88e5f660,0,1
-96ee3bc5,0,1
-96cf9939,0,1
-38849fc2,1,1
-b51e243 ,0,1
-37b05a4b,0,1
-2497784 ,0,1
-aed161d2,0,1
-7f6590f6,0,1
-479570fd,0,1
-ae0cb755,0,1
-ee161bc2,1,1
-6d572f08,0,1
-e0c7b6dd,0,1
-88674260,0,1
-a5ae48a8,0,1
-a7112033,0,1
-c555cde2,0,1
-51c0db63,0,1
-60f9e31b,1,1
-24eb65ee,0,1
-309707c9,0,1
-af5d19d2,0,1
-d4e713d3,0,1
-5d160f7a,0,1
-400e3734,0,1
-b6a8cf6c,0,1
-3a012531,1,1
-5951566a,0,1
-b8a4b430,0,1
-9fe9980d,0,1
-80069d04,0,1
-93d866f ,0,1
-7af5e3f6,0,1
-cc432473,0,1
-90f1978 ,1,1
diff --git a/wrapper/verif/tb_wrapper_secworks_sha256.sv b/wrapper/verif/tb_wrapper_secworks_sha256.sv
deleted file mode 100644
index cbfce6e898aef9a1a5b06fa834391c259e2a901e..0000000000000000000000000000000000000000
--- a/wrapper/verif/tb_wrapper_secworks_sha256.sv
+++ /dev/null
@@ -1,263 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Top-level AHB Wrapper
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-// `include "wrapper_secworks_sha256.sv"
-
-`timescale 1ns/1ps
-
-import "DPI-C" function string getenv(input string env_name);
-
-module tb_wrapper_secworks_sha256;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-parameter InputFileName = ("/home/dam1n19/Design/secworks-sha256-project/wrapper/stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
- initial begin
- $write("env = %s\n", getenv("PWD"));
- end
-
-initial
- begin
- $dumpfile("wrapper_secworks_sha256.vcd");
- $dumpvars(0, tb_wrapper_secworks_sha256);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, two ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 0, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_secworks_sha256 #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0),
-
- // Input Data Request to DMAC
- .in_data_req (),
- .out_data_req ()
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file
diff --git a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv b/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
deleted file mode 100644
index 67579c7a6bb43ad57487c79dad7e6ae4995a8654..0000000000000000000000000000000000000000
--- a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
+++ /dev/null
@@ -1,256 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Top-level AHB Wrapper
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-`include "wrapper_sha256_hashing_stream.sv"
-
-`timescale 1ns/1ps
-
-module tb_wrapper_sha256_hashing_stream;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-parameter InputFileName = ("../../wrapper/stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
-initial
- begin
- $dumpfile("wrapper_sha256_hashing_stream.vcd");
- $dumpvars(0, tb_wrapper_sha256_hashing_stream);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, two ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 0, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_sha256_hashing_stream #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0),
-
- // Input Data Request to DMAC
- .in_data_req ()
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file
diff --git a/wrapper/verif/tb_wrapper_vr_loopback.sv b/wrapper/verif/tb_wrapper_vr_loopback.sv
deleted file mode 100644
index 5e25339e114b82463f362b5f946cc606b96feeec..0000000000000000000000000000000000000000
--- a/wrapper/verif/tb_wrapper_vr_loopback.sv
+++ /dev/null
@@ -1,260 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Testbench for Wrapper Valid-Ready Loopback Test
-// Modified from tb_frbm_example.v
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-------------------------------------------------------------------------
-// Abstract : Example for File Reader Bus Master
-// Testbench for the example AHB Lite slave.
-//=========================================================================--
-`include "cmsdk_ahb_filereadcore.v"
-`include "cmsdk_ahb_fileread_funnel.v"
-`include "cmsdk_ahb_fileread_master32.v"
-`include "cmsdk_ahb_default_slave.v"
-`include "cmsdk_ahb_slave_mux.v"
-`include "wrapper_vr_loopback.sv"
-
-`timescale 1ns/1ps
-
-module tb_wrapper_vr_loopback;
-
-parameter CLK_PERIOD = 10;
-parameter ADDRWIDTH = 12;
-
-// parameter InputFileName = "ahb_input_hash_stim.m2d";
-parameter InputFileName = ("../stimulus/ahb_input_hash_stim.m2d");
-parameter MessageTag = "FileReader:";
-parameter StimArraySize = 10000;
-
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// AHB Lite BUS SIGNALS
-wire hready;
-wire hresp;
-wire [31:0] hrdata;
-
-wire [1:0] htrans;
-wire [2:0] hburst;
-wire [3:0] hprot;
-wire [2:0] hsize;
-wire hwrite;
-wire hmastlock;
-wire [31:0] haddr;
-wire [31:0] hwdata;
-
-// Accelerator AHB Signals
-wire hsel0;
-wire hreadyout0;
-wire hresp0;
-wire [31:0] hrdata0;
-
-// Default Slave AHB Signals
-wire hsel1;
-wire hreadyout1;
-wire hresp1;
-wire [31:0] hrdata1;
-
-reg HCLK;
-reg HRESETn;
-
-//********************************************************************************
-// Clock and reset generation
-//********************************************************************************
-
-initial
- begin
- $dumpfile("wrapper_vr_loopback.vcd");
- $dumpvars(0, tb_wrapper_vr_loopback);
- HRESETn = 1'b0;
- HCLK = 1'b0;
- # (10*CLK_PERIOD);
- HRESETn = 1'b1;
- end
-
-always
- begin
- HCLK = #(CLK_PERIOD/2) ~HCLK;
- end
-
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default slave
-
- assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0;
- assign hsel1 = hsel0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// File read bus master:
-// generate AHB Master signal by reading a file which store the AHB Operations
-//********************************************************************************
-
-cmsdk_ahb_fileread_master32 #(InputFileName,
- MessageTag,
- StimArraySize
-) u_ahb_fileread_master32 (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- .HREADY (hready),
- .HRESP ({hresp}), //AHB Lite response to AHB response
- .HRDATA (hrdata),
- .EXRESP (1'b0), // Exclusive response (tie low if not used)
-
-
- .HTRANS (htrans),
- .HBURST (hburst),
- .HPROT (hprot),
- .EXREQ (), // Exclusive access request (not used)
- .MEMATTR (), // Memory attribute (not used)
- .HSIZE (hsize),
- .HWRITE (hwrite),
- .HMASTLOCK (hmastlock),
- .HADDR (haddr),
- .HWDATA (hwdata),
-
- .LINENUM ()
-
- );
-
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the slave signals to master, three ports are enabled
-//********************************************************************************
-
- cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (hready),
- .HSEL0 (hsel0), // Input Port 0
- .HREADYOUT0 (hreadyout0),
- .HRESP0 (hresp0),
- .HRDATA0 (hrdata0),
- .HSEL1 (hsel1), // Input Port 1
- .HREADYOUT1 (hreadyout1),
- .HRESP1 (hresp1),
- .HRDATA1 (hrdata1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (hready), // Outputs
- .HRESP (hresp),
- .HRDATA (hrdata)
- );
-
-
-//********************************************************************************
-// Slave module 1: example AHB slave module
-//********************************************************************************
- wrapper_vr_loopback #(ADDRWIDTH
- ) accelerator (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
-
- // Input slave port: 32 bit data bus interface
- .HSELS (hsel0),
- .HADDRS (haddr[ADDRWIDTH-1:0]),
- .HTRANSS (htrans),
- .HSIZES (hsize),
- .HWRITES (hwrite),
- .HREADYS (hready),
- .HWDATAS (hwdata),
-
- .HREADYOUTS (hreadyout0),
- .HRESPS (hresp0),
- .HRDATAS (hrdata0)
-
- );
-
-
-//********************************************************************************
-// Slave module 2: AHB default slave module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (hsel1),
- .HTRANS (htrans),
- .HREADY (hready),
- .HREADYOUT (hreadyout1),
- .HRESP (hresp1)
- );
-
- assign hrdata1 = {32{1'b0}}; // Default slave don't have data
-
- endmodule
\ No newline at end of file