From f78e13ae39205ea8d3dd23caf03fd074964768a8 Mon Sep 17 00:00:00 2001 From: Daniel Newbrook <dwn1c21@soton.ac.uk> Date: Tue, 29 Oct 2024 09:38:23 +0000 Subject: [PATCH] Seperate FPGA and behavioural flist --- flist/project/top_FPGA.flist | 32 ++++++++++++++++++++++++++++++++ nanosoc_tech | 2 +- 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 flist/project/top_FPGA.flist diff --git a/flist/project/top_FPGA.flist b/flist/project/top_FPGA.flist new file mode 100644 index 0000000..a836797 --- /dev/null +++ b/flist/project/top_FPGA.flist @@ -0,0 +1,32 @@ +//----------------------------------------------------------------------------- +// Project Top-level Filelist System Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Top-level Accelerator System +//----------------------------------------------------------------------------- + +// DESIGN_TOP nanosoc_chip + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= System Filelist ========================= +// - Defines RTL ++incdir+$(SOCLABS_PROJECT_DIR)/system/src/defines + +-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist + +// ============= Arm-IP Specific Filelists ========================= +// - NanoSoC Chip IP +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/nanosoc_FPGA.flist + +// - CMSDK IP +-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist +-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist diff --git a/nanosoc_tech b/nanosoc_tech index f0cbada..02f873a 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit f0cbada25183a36a0385084269c1c8a9bacf2ea1 +Subproject commit 02f873a7a1bc285f377543105602f35664c1d735 -- GitLab