diff --git a/sha-2-accelerator/.DS_Store b/sha-2-accelerator/.DS_Store
deleted file mode 100644
index 617ce0426920c16bba8d96c7d48c2a8973b5490f..0000000000000000000000000000000000000000
Binary files a/sha-2-accelerator/.DS_Store and /dev/null differ
diff --git a/sha-2-accelerator/.gitignore b/sha-2-accelerator/.gitignore
deleted file mode 100644
index 46915223154c67d6511fed7622842d30b6f67aba..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/.gitignore
+++ /dev/null
@@ -1,3 +0,0 @@
-*.vcd
-*.vvp
-*.DS_Store
\ No newline at end of file
diff --git a/sha-2-accelerator/.vscode/settings.json b/sha-2-accelerator/.vscode/settings.json
deleted file mode 100644
index 43e33e6ae2f2ebdefbefb5c5363f6bb2235a1b67..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/.vscode/settings.json
+++ /dev/null
@@ -1,7 +0,0 @@
-{
- "workbench.colorCustomizations": {
- "activityBar.background": "#00360F",
- "titleBar.activeBackground": "#004C16",
- "titleBar.activeForeground": "#EDFFF2"
- }
-}
\ No newline at end of file
diff --git a/sha-2-accelerator/README.md b/sha-2-accelerator/README.md
deleted file mode 100644
index 59bebfebd4daaa834e52b0d0a96d78f001495619..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/README.md
+++ /dev/null
@@ -1,55 +0,0 @@
-# SHA-2 Accelerator
-
-This project is an example accelerator which will be combined with the SoC Labs SoC infrastructure.
-TEST7
-## Repository Structure
-The respository is currently broken down into 2 main directories:
-- hdl
-- simulate
-
-HDL contains all the verilog files. This is seperated into:
-- src
-- verif
-
-src contains SystemVerilog design files and verif contains the SystemVerilog testbenches and verification resources.
-
-The simulate directory contains the socsim script, along with a directory called "simulators" which contains simulator-specific scripts and a "sim" directory which contains dumps and logs from simulation runs. The files in this directory should not be commited to the Git.
-
-## Setting Up Environment
-To be able to simulate in this repository, you will first need to source the sourceme:
-```
-% source sourceme
-```
-
-## Stimulus Generation
-Under `model/py`, there is `hash_model.py` which is a python model of the hashing accelerator. This produces numerous `.csv` files which can be fed in testbenches. These files are seperated into two types:
-- stimiulus
-- reference
-
-Stimulus files are used to stimulate the DUT by feeding into the inputs of the module. Reference files are used to compare to the output of the DUT to check whether it is behaving correctly.
-
-These files are present in the `simulate/stimulus/unit/` or `simulate/stimulus/system/` directories. Unit contains stimulus and reference files for unit tests - internal wrapper engine verification. System contains stimulus and reference files for System and Wrapper tests.
-
-The `simulate/stimulus/model/` directory contains a hand-written stimulus file which is used to seed and constrain the python model. There are `5` values in this file and are listed as follows:
-- Seed - random seed used to seed python model
-- Payload Number - Number of payloads to generate
-- Payload Size (Bits) - Number of bits a payload is comprised of. If set to 0, this is randomised each payload. If non-zero, each payload will have a size of this value.
-- Gap Limit - Maximum number of clock cycles to gap on the input (cycles to wait before asserting valid on the input data)
-- Stall Limit - Maximum number of clock cycles to stall on the output (cycles to wait before asseting ready on the output)
-
-To generate the stimulus and reference, ensure the `sourceme` in the root of this repo has been sourced and then run `python3 hash_model.py` within the `model/py` directory. This will populate the directories with the `.csv` files in the `simulate/stimulus` directory.
-
-## Simulation Setup
-This will set up the environment variables and will set the simulator used. Defaultly, this is set to ivlog - Icarus Verilog. This can be overloaded from the command line with the following command:
-```
-% SIMULATOR=yoursimulator
-```
-
-Once this is done, a simulation can be ran using the socsim command:
-```
-% socsim
-```
-This will generate simulation dumps in the following directory:
-```
-% $SHA_2_ACC_DIR/simulate/sim
-```
\ No newline at end of file
diff --git a/sha-2-accelerator/flist/sha-2-accelerator_src.flist b/sha-2-accelerator/flist/sha-2-accelerator_src.flist
deleted file mode 100644
index a9b8ef4c05f82773e00db0bfb9d6af21ddbfb0c0..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/flist/sha-2-accelerator_src.flist
+++ /dev/null
@@ -1,33 +0,0 @@
-//-----------------------------------------------------------------------------
-// SHA-2 Accelerator Filelist
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright � 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : Verilog Command File for SHA-2 Accelerator example
-//-----------------------------------------------------------------------------
-
-// ============= Verilog library extensions ===========
-+libext+.v+.vlib
-
-// ============= Accelerator Module search path =============
--y $DESIGN/sha-2-accelerator/hdl/src/
-+incdir+$DESIGN/sha-2-accelerator/hdl/src/
-
-$DESIGN/sha-2-accelerator/hdl/src/fifo_vr.sv
-$DESIGN/sha-2-accelerator/hdl/src/sha256_hash_compression.sv
-$DESIGN/sha-2-accelerator/hdl/src/sha256_hashing_stream.sv
-$DESIGN/sha-2-accelerator/hdl/src/sha256_message_build.sv
-
-// $DESIGN/sha-2-accelerator/hdl/src/sha256_1_3_arbitrator.sv
-// $DESIGN/sha-2-accelerator/hdl/src/sha256_config_sync.sv
-// $DESIGN/sha-2-accelerator/hdl/src/sha256_engine.sv
-// $DESIGN/sha-2-accelerator/hdl/src/sha256_id_buf.sv
-// $DESIGN/sha-2-accelerator/hdl/src/sha256_id_issue.sv
-// $DESIGN/sha-2-accelerator/hdl/src/sha256_id_validator.sv
-// $DESIGN/sha-2-accelerator/hdl/src/sha256_packet_manager.sv
diff --git a/sha-2-accelerator/flow/lint b/sha-2-accelerator/flow/lint
deleted file mode 100755
index b9a276ee8566076c6dfe85634fc15b06ee9974d5..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/flow/lint
+++ /dev/null
@@ -1,14 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs socsim script to run linting
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-verilator --lint-only $*
\ No newline at end of file
diff --git a/sha-2-accelerator/flow/simulators/ivlog_sim.sh b/sha-2-accelerator/flow/simulators/ivlog_sim.sh
deleted file mode 100755
index 674d71ecca3550cc0005a66fc2ef877bc747fa63..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/flow/simulators/ivlog_sim.sh
+++ /dev/null
@@ -1,16 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs icarus verilog simulation script for engine testbench
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-mkdir -p $SOC_TOP/simulate/sim/
-iverilog -I $SOC_TOP/hdl/verif/ -I $SOC_TOP/hdl/src/ -g2012 -o $SOC_TOP/simulate/sim/$1.vvp $SOC_TOP/hdl/verif/tb_$1.sv
-cd $SOC_TOP/simulate/sim/ && vvp $1.vvp $2
\ No newline at end of file
diff --git a/sha-2-accelerator/flow/socsim b/sha-2-accelerator/flow/socsim
deleted file mode 100755
index 42c6196bc101419a6a108eba4865be67a760d076..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/flow/socsim
+++ /dev/null
@@ -1,18 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs socsim script to run required simulation
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-DEFAULT_SIMULATOR="ivlog"
-if [[ -z "${SIMULATOR}" ]]; then
- SIMULATOR=$DEFAULT_SIMULATOR
-fi
-$SOC_TOP"/flow/simulators/"$SIMULATOR"_sim.sh" $@
diff --git a/sha-2-accelerator/flow/socsim_py b/sha-2-accelerator/flow/socsim_py
deleted file mode 100755
index 782aa6034bf43e15f10d347252b3faca14a9c664..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/flow/socsim_py
+++ /dev/null
@@ -1,14 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs socsim script to run required simulation
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-python3 $SHA_2_ACC_DIR"/flow/socsim_py.py" $@
\ No newline at end of file
diff --git a/sha-2-accelerator/flow/socsim_py.py b/sha-2-accelerator/flow/socsim_py.py
deleted file mode 100644
index a3246b77b4bad58895c926f3cdcdf8142203c2d3..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/flow/socsim_py.py
+++ /dev/null
@@ -1,17 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs socsim script to run required simulation
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-import argparse
-
-parser = argparse.ArgumentParser()
-parser.add_argument("-m", "--model", type=str, help="Python Model used to generate Sitmulus and Reference for design")
-parser.add_argument("-s", "--stimulus", type=str, help="Stimulus to pass to Python Model to generate Testbench Stimulus and Reference")
-parser.parse_args()
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/registers/config.yml b/sha-2-accelerator/hdl/registers/config.yml
deleted file mode 100644
index 446767e17c2cc28f41f6058c460768698a7c7a44..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/registers/config.yml
+++ /dev/null
@@ -1,3 +0,0 @@
-bus_width: 32
-address_width: 4
-protocol: apb
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/registers/out/status_regs.h b/sha-2-accelerator/hdl/registers/out/status_regs.h
deleted file mode 100644
index f16e7c6d7a4160a737ec5d648760acd10756b384..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/registers/out/status_regs.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef STATUS_REGS_H
-#define STATUS_REGS_H
-#include "stdint.h"
-#define STATUS_REGS_STATUS_0_STATUS_ID_BIT_WIDTH 6
-#define STATUS_REGS_STATUS_0_STATUS_ID_BIT_MASK 0x3f
-#define STATUS_REGS_STATUS_0_STATUS_ID_BIT_OFFSET 0
-#define STATUS_REGS_STATUS_0_STATUS_BUFFERED_IDS_BIT_WIDTH 3
-#define STATUS_REGS_STATUS_0_STATUS_BUFFERED_IDS_BIT_MASK 0x7
-#define STATUS_REGS_STATUS_0_STATUS_BUFFERED_IDS_BIT_OFFSET 6
-#define STATUS_REGS_STATUS_0_STATUS_ERR_BUFFER_BIT_WIDTH 1
-#define STATUS_REGS_STATUS_0_STATUS_ERR_BUFFER_BIT_MASK 0x1
-#define STATUS_REGS_STATUS_0_STATUS_ERR_BUFFER_BIT_OFFSET 9
-#define STATUS_REGS_STATUS_0_STATUS_ERR_PACKET_BIT_WIDTH 1
-#define STATUS_REGS_STATUS_0_STATUS_ERR_PACKET_BIT_MASK 0x1
-#define STATUS_REGS_STATUS_0_STATUS_ERR_PACKET_BIT_OFFSET 10
-#define STATUS_REGS_STATUS_0_STATUS_ERR_CLEAR_BIT_WIDTH 1
-#define STATUS_REGS_STATUS_0_STATUS_ERR_CLEAR_BIT_MASK 0x1
-#define STATUS_REGS_STATUS_0_STATUS_ERR_CLEAR_BIT_OFFSET 11
-#define STATUS_REGS_STATUS_0_STATUS_PACKET_COUNT_BIT_WIDTH 10
-#define STATUS_REGS_STATUS_0_STATUS_PACKET_COUNT_BIT_MASK 0x3ff
-#define STATUS_REGS_STATUS_0_STATUS_PACKET_COUNT_BIT_OFFSET 12
-#define STATUS_REGS_STATUS_0_BYTE_WIDTH 4
-#define STATUS_REGS_STATUS_0_BYTE_SIZE 4
-#define STATUS_REGS_STATUS_0_BYTE_OFFSET 0x0
-typedef struct {
- uint32_t status_0;
- uint32_t __reserved_0x4;
- uint32_t __reserved_0x8;
- uint32_t __reserved_0xc;
-} status_regs_t;
-#endif
diff --git a/sha-2-accelerator/hdl/registers/out/status_regs.md b/sha-2-accelerator/hdl/registers/out/status_regs.md
deleted file mode 100644
index 2b36b17f7ef19ce14de0b96030afe998b003b396..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/registers/out/status_regs.md
+++ /dev/null
@@ -1,24 +0,0 @@
-## status_regs
-
-* byte_size
- * 16
-
-|name|offset_address|
-|:--|:--|
-|[status_0](#status_regs-status_0)|0x0|
-
-### <div id="status_regs-status_0"></div>status_0
-
-* offset_address
- * 0x0
-* type
- * default
-
-|name|bit_assignments|type|initial_value|reference|labels|comment|
-|:--|:--|:--|:--|:--|:--|:--|
-|status_id|[5:0]|ro|0x00|||Contains last ID Value in ID Buffer|
-|status_buffered_ids|[8:6]|ro|0x0|||Number of IDs in ID Buffer|
-|status_err_buffer|[9]|ro|0x0|||ID Buffer Error|
-|status_err_packet|[10]|ro|0x0|||Dropped Packet Error|
-|status_err_clear|[11]|wo|0x0|||Clear Error Flags|
-|status_packet_count|[21:12]|ro|0x000|||Number of Packets Passed Through|
diff --git a/sha-2-accelerator/hdl/registers/out/status_regs.sv b/sha-2-accelerator/hdl/registers/out/status_regs.sv
deleted file mode 100644
index 006211faf39012606ee9fb7c51424cd1cdc98872..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/registers/out/status_regs.sv
+++ /dev/null
@@ -1,233 +0,0 @@
-`ifndef rggen_connect_bit_field_if
- `define rggen_connect_bit_field_if(RIF, FIF, LSB, WIDTH) \
- assign FIF.valid = RIF.valid; \
- assign FIF.read_mask = RIF.read_mask[LSB+:WIDTH]; \
- assign FIF.write_mask = RIF.write_mask[LSB+:WIDTH]; \
- assign FIF.write_data = RIF.write_data[LSB+:WIDTH]; \
- assign RIF.read_data[LSB+:WIDTH] = FIF.read_data; \
- assign RIF.value[LSB+:WIDTH] = FIF.value;
-`endif
-`ifndef rggen_tie_off_unused_signals
- `define rggen_tie_off_unused_signals(WIDTH, VALID_BITS, RIF) \
- if (1) begin : __g_tie_off \
- genvar __i; \
- for (__i = 0;__i < WIDTH;++__i) begin : g \
- if (!(((VALID_BITS) >> __i) & 1'b1)) begin : g \
- assign RIF.read_data[__i] = 1'b0; \
- assign RIF.value[__i] = 1'b0; \
- end \
- end \
- end
-`endif
-module status_regs
- import rggen_rtl_pkg::*;
-#(
- parameter int ADDRESS_WIDTH = 4,
- parameter bit PRE_DECODE = 0,
- parameter bit [ADDRESS_WIDTH-1:0] BASE_ADDRESS = '0,
- parameter bit ERROR_STATUS = 0,
- parameter bit [31:0] DEFAULT_READ_DATA = '0
-)(
- input logic i_clk,
- input logic i_rst_n,
- rggen_apb_if.slave apb_if,
- input logic [5:0] i_status_0_status_id,
- input logic [2:0] i_status_0_status_buffered_ids,
- input logic i_status_0_status_err_buffer,
- input logic i_status_0_status_err_packet,
- output logic o_status_0_status_err_clear,
- input logic [9:0] i_status_0_status_packet_count
-);
- rggen_register_if #(4, 32, 32) register_if[1]();
- rggen_apb_adapter #(
- .ADDRESS_WIDTH (ADDRESS_WIDTH),
- .LOCAL_ADDRESS_WIDTH (4),
- .BUS_WIDTH (32),
- .REGISTERS (1),
- .PRE_DECODE (PRE_DECODE),
- .BASE_ADDRESS (BASE_ADDRESS),
- .BYTE_SIZE (16),
- .ERROR_STATUS (ERROR_STATUS),
- .DEFAULT_READ_DATA (DEFAULT_READ_DATA)
- ) u_adapter (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .apb_if (apb_if),
- .register_if (register_if)
- );
- generate if (1) begin : g_status_0
- rggen_bit_field_if #(32) bit_field_if();
- `rggen_tie_off_unused_signals(32, 32'h003fffff, bit_field_if)
- rggen_default_register #(
- .READABLE (1),
- .WRITABLE (1),
- .ADDRESS_WIDTH (4),
- .OFFSET_ADDRESS (4'h0),
- .BUS_WIDTH (32),
- .DATA_WIDTH (32),
- .REGISTER_INDEX (0)
- ) u_register (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .register_if (register_if[0]),
- .bit_field_if (bit_field_if)
- );
- if (1) begin : g_status_id
- localparam bit [5:0] INITIAL_VALUE = 6'h00;
- rggen_bit_field_if #(6) bit_field_sub_if();
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 0, 6)
- rggen_bit_field #(
- .WIDTH (6),
- .STORAGE (0),
- .EXTERNAL_READ_DATA (1),
- .TRIGGER (0)
- ) u_bit_field (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .bit_field_if (bit_field_sub_if),
- .o_write_trigger (),
- .o_read_trigger (),
- .i_sw_write_enable ('0),
- .i_hw_write_enable ('0),
- .i_hw_write_data ('0),
- .i_hw_set ('0),
- .i_hw_clear ('0),
- .i_value (i_status_0_status_id),
- .i_mask ('1),
- .o_value (),
- .o_value_unmasked ()
- );
- end
- if (1) begin : g_status_buffered_ids
- localparam bit [2:0] INITIAL_VALUE = 3'h0;
- rggen_bit_field_if #(3) bit_field_sub_if();
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 6, 3)
- rggen_bit_field #(
- .WIDTH (3),
- .STORAGE (0),
- .EXTERNAL_READ_DATA (1),
- .TRIGGER (0)
- ) u_bit_field (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .bit_field_if (bit_field_sub_if),
- .o_write_trigger (),
- .o_read_trigger (),
- .i_sw_write_enable ('0),
- .i_hw_write_enable ('0),
- .i_hw_write_data ('0),
- .i_hw_set ('0),
- .i_hw_clear ('0),
- .i_value (i_status_0_status_buffered_ids),
- .i_mask ('1),
- .o_value (),
- .o_value_unmasked ()
- );
- end
- if (1) begin : g_status_err_buffer
- localparam bit INITIAL_VALUE = 1'h0;
- rggen_bit_field_if #(1) bit_field_sub_if();
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 9, 1)
- rggen_bit_field #(
- .WIDTH (1),
- .STORAGE (0),
- .EXTERNAL_READ_DATA (1),
- .TRIGGER (0)
- ) u_bit_field (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .bit_field_if (bit_field_sub_if),
- .o_write_trigger (),
- .o_read_trigger (),
- .i_sw_write_enable ('0),
- .i_hw_write_enable ('0),
- .i_hw_write_data ('0),
- .i_hw_set ('0),
- .i_hw_clear ('0),
- .i_value (i_status_0_status_err_buffer),
- .i_mask ('1),
- .o_value (),
- .o_value_unmasked ()
- );
- end
- if (1) begin : g_status_err_packet
- localparam bit INITIAL_VALUE = 1'h0;
- rggen_bit_field_if #(1) bit_field_sub_if();
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 10, 1)
- rggen_bit_field #(
- .WIDTH (1),
- .STORAGE (0),
- .EXTERNAL_READ_DATA (1),
- .TRIGGER (0)
- ) u_bit_field (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .bit_field_if (bit_field_sub_if),
- .o_write_trigger (),
- .o_read_trigger (),
- .i_sw_write_enable ('0),
- .i_hw_write_enable ('0),
- .i_hw_write_data ('0),
- .i_hw_set ('0),
- .i_hw_clear ('0),
- .i_value (i_status_0_status_err_packet),
- .i_mask ('1),
- .o_value (),
- .o_value_unmasked ()
- );
- end
- if (1) begin : g_status_err_clear
- localparam bit INITIAL_VALUE = 1'h0;
- rggen_bit_field_if #(1) bit_field_sub_if();
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 11, 1)
- rggen_bit_field #(
- .WIDTH (1),
- .INITIAL_VALUE (INITIAL_VALUE),
- .SW_READ_ACTION (RGGEN_READ_NONE),
- .SW_WRITE_ONCE (0),
- .TRIGGER (0)
- ) u_bit_field (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .bit_field_if (bit_field_sub_if),
- .o_write_trigger (),
- .o_read_trigger (),
- .i_sw_write_enable ('1),
- .i_hw_write_enable ('0),
- .i_hw_write_data ('0),
- .i_hw_set ('0),
- .i_hw_clear ('0),
- .i_value ('0),
- .i_mask ('1),
- .o_value (o_status_0_status_err_clear),
- .o_value_unmasked ()
- );
- end
- if (1) begin : g_status_packet_count
- localparam bit [9:0] INITIAL_VALUE = 10'h000;
- rggen_bit_field_if #(10) bit_field_sub_if();
- `rggen_connect_bit_field_if(bit_field_if, bit_field_sub_if, 12, 10)
- rggen_bit_field #(
- .WIDTH (10),
- .STORAGE (0),
- .EXTERNAL_READ_DATA (1),
- .TRIGGER (0)
- ) u_bit_field (
- .i_clk (i_clk),
- .i_rst_n (i_rst_n),
- .bit_field_if (bit_field_sub_if),
- .o_write_trigger (),
- .o_read_trigger (),
- .i_sw_write_enable ('0),
- .i_hw_write_enable ('0),
- .i_hw_write_data ('0),
- .i_hw_set ('0),
- .i_hw_clear ('0),
- .i_value (i_status_0_status_packet_count),
- .i_mask ('1),
- .o_value (),
- .o_value_unmasked ()
- );
- end
- end endgenerate
-endmodule
diff --git a/sha-2-accelerator/hdl/registers/out/status_regs_ral_pkg.sv b/sha-2-accelerator/hdl/registers/out/status_regs_ral_pkg.sv
deleted file mode 100644
index e9a85a7ab829d098a86b82637ad2c160394d6288..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/registers/out/status_regs_ral_pkg.sv
+++ /dev/null
@@ -1,34 +0,0 @@
-package status_regs_ral_pkg;
- import uvm_pkg::*;
- import rggen_ral_pkg::*;
- `include "uvm_macros.svh"
- `include "rggen_ral_macros.svh"
- class status_0_reg_model extends rggen_ral_reg;
- rand rggen_ral_field status_id;
- rand rggen_ral_field status_buffered_ids;
- rand rggen_ral_field status_err_buffer;
- rand rggen_ral_field status_err_packet;
- rand rggen_ral_field status_err_clear;
- rand rggen_ral_field status_packet_count;
- function new(string name);
- super.new(name, 32, 0);
- endfunction
- function void build();
- `rggen_ral_create_field(status_id, 0, 6, "RO", 1, 6'h00, 1, -1, "")
- `rggen_ral_create_field(status_buffered_ids, 6, 3, "RO", 1, 3'h0, 1, -1, "")
- `rggen_ral_create_field(status_err_buffer, 9, 1, "RO", 1, 1'h0, 1, -1, "")
- `rggen_ral_create_field(status_err_packet, 10, 1, "RO", 1, 1'h0, 1, -1, "")
- `rggen_ral_create_field(status_err_clear, 11, 1, "WO", 0, 1'h0, 1, -1, "")
- `rggen_ral_create_field(status_packet_count, 12, 10, "RO", 1, 10'h000, 1, -1, "")
- endfunction
- endclass
- class status_regs_block_model extends rggen_ral_block;
- rand status_0_reg_model status_0;
- function new(string name);
- super.new(name, 4, 0);
- endfunction
- function void build();
- `rggen_ral_create_reg(status_0, '{}, 4'h0, "RW", "g_status_0.u_register")
- endfunction
- endclass
-endpackage
diff --git a/sha-2-accelerator/hdl/registers/out/status_regs_rtl_pkg.sv b/sha-2-accelerator/hdl/registers/out/status_regs_rtl_pkg.sv
deleted file mode 100644
index e5b57358c2d4a85f1d396dc74bb03085991a59b7..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/registers/out/status_regs_rtl_pkg.sv
+++ /dev/null
@@ -1,23 +0,0 @@
-package status_regs_rtl_pkg;
- localparam int STATUS_0_BYTE_WIDTH = 4;
- localparam int STATUS_0_BYTE_SIZE = 4;
- localparam bit [3:0] STATUS_0_BYTE_OFFSET = 4'h0;
- localparam int STATUS_0_STATUS_ID_BIT_WIDTH = 6;
- localparam bit [5:0] STATUS_0_STATUS_ID_BIT_MASK = 6'h3f;
- localparam int STATUS_0_STATUS_ID_BIT_OFFSET = 0;
- localparam int STATUS_0_STATUS_BUFFERED_IDS_BIT_WIDTH = 3;
- localparam bit [2:0] STATUS_0_STATUS_BUFFERED_IDS_BIT_MASK = 3'h7;
- localparam int STATUS_0_STATUS_BUFFERED_IDS_BIT_OFFSET = 6;
- localparam int STATUS_0_STATUS_ERR_BUFFER_BIT_WIDTH = 1;
- localparam bit STATUS_0_STATUS_ERR_BUFFER_BIT_MASK = 1'h1;
- localparam int STATUS_0_STATUS_ERR_BUFFER_BIT_OFFSET = 9;
- localparam int STATUS_0_STATUS_ERR_PACKET_BIT_WIDTH = 1;
- localparam bit STATUS_0_STATUS_ERR_PACKET_BIT_MASK = 1'h1;
- localparam int STATUS_0_STATUS_ERR_PACKET_BIT_OFFSET = 10;
- localparam int STATUS_0_STATUS_ERR_CLEAR_BIT_WIDTH = 1;
- localparam bit STATUS_0_STATUS_ERR_CLEAR_BIT_MASK = 1'h1;
- localparam int STATUS_0_STATUS_ERR_CLEAR_BIT_OFFSET = 11;
- localparam int STATUS_0_STATUS_PACKET_COUNT_BIT_WIDTH = 10;
- localparam bit [9:0] STATUS_0_STATUS_PACKET_COUNT_BIT_MASK = 10'h3ff;
- localparam int STATUS_0_STATUS_PACKET_COUNT_BIT_OFFSET = 12;
-endpackage
diff --git a/sha-2-accelerator/hdl/registers/status_regs.yml b/sha-2-accelerator/hdl/registers/status_regs.yml
deleted file mode 100644
index 13a3ca47c9db4094d3dfc5d9f19b2d2d1c733528..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/registers/status_regs.yml
+++ /dev/null
@@ -1,12 +0,0 @@
-register_blocks:
- - name: status_regs
- byte_size: 16
- registers:
- - name: status_0
- bit_fields:
- - { name: status_id, bit_assignment: { width: 6 }, type: ro , initial_value: 0, comment: Contains last ID Value in ID Buffer }
- - { name: status_buffered_ids, bit_assignment: { width: 3 }, type: ro , initial_value: 0, comment: Number of IDs in ID Buffer }
- - { name: status_err_buffer, bit_assignment: { width: 1 }, type: ro , initial_value: 0, comment: ID Buffer Error }
- - { name: status_err_packet, bit_assignment: { width: 1 }, type: ro , initial_value: 0, comment: Dropped Packet Error }
- - { name: status_err_clear, bit_assignment: { width: 1 }, type: wo , initial_value: 0, comment: Clear Error Flags }
- - { name: status_packet_count, bit_assignment: { width: 10 }, type: ro , initial_value: 0, comment: Number of Packets Passed Through }
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/fifo_vr.sv b/sha-2-accelerator/hdl/src/fifo_vr.sv
deleted file mode 100644
index 4cce7dece0d700f882b3125e1fe31641c299e5e6..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/fifo_vr.sv
+++ /dev/null
@@ -1,162 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Parameterisable Valid-Ready FIFO
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-module fifo_vr #(
- parameter DEPTH = 4, // FIFO Row Depth
- parameter DATA_W = 32, // FIFO Row Width
- parameter PTR_W = $clog2(DEPTH) + 1 // Read/Write Pointer Width
-)(
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // In (Write) Control
- input logic [DATA_W-1:0] data_in,
- input logic data_in_last,
- input logic data_in_valid,
- output logic data_in_ready,
-
- // Out (Read) Control
- output logic [DATA_W-1:0] data_out,
- output logic data_out_last,
- input logic data_out_ready,
- output logic data_out_valid,
-
- // Status
- output logic [PTR_W-1:0] status_ptr_dif
-);
-
- logic data_in_shake; // Successful Write Handshake
- logic data_out_shake; // Successful Read Handshake
-
- assign data_in_shake = (data_in_valid == 1'b1) && (data_in_ready == 1'b1);
- assign data_out_shake = (data_out_valid == 1'b1) && (data_out_ready == 1'b1);
-
- logic [DATA_W:0] fifo [DEPTH-1:0]; // FIFO Memory Structure
- logic [PTR_W-1:0] write_ptr; // FIFO Write Pointer
- logic [PTR_W-1:0] read_ptr; // FIFO Read Pointer
- logic [PTR_W-1:0] ptr_dif; // Difference between Write and Read Pointers
-
- assign ptr_dif = write_ptr - read_ptr;
-
- assign status_ptr_dif = ptr_dif;
-
- // EXAMPLE: Conditions to write and read from FIFO's
- // Write Ptr | Read Ptr | Ptr_Dif | Valid Write | Valid Read
- // 000 - 000 = 000 | Y | N
- // 001 - 000 = 001 | Y | Y
- // 010 - 000 = 010 | Y | Y
- // 011 - 000 = 011 | Y | Y
- // 100 - 000 = 100 | N | Y
- // 101 - 000 = 101 | N | N
- // 110 - 000 = 110 | N | N
- // 111 - 000 = 111 | N | N
- // WriteValid: WritePtr - ReadPtr < 3'd4
- // ReadValid: WritePtr - ReadPtr - 1 < 3'd4
-
- assign {data_out,data_out_last} = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer
-
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) || sync_rst) begin
- // Under Reset
- // - Pointers reset to 0 (FIFO is empty without needing to reset the memories)
- // - Control taken low
- write_ptr <= 0;
- read_ptr <= 0;
- data_in_ready <= 1'b0;
- data_out_valid <= 1'b0;
- // Ensure FIFO Values are Known
- for (int i = 0; i < DEPTH; i++) begin
- fifo[i] <= 'b0;
- end
- end else if (en == 1'b1) begin
- // Enable signal is High
- // Write Logic
- if (ptr_dif < DEPTH) begin
- // Empty Rows in FIFO in FIFO
- if (data_in_shake) begin
- // Successful Handshake store data in FIFO and increment Write Pointer
- fifo [write_ptr[PTR_W-2:0]] <= {data_in,data_in_last};
- write_ptr <= write_ptr + 1;
- if ((ptr_dif + {{(PTR_W-1){1'b0}},(1'b1 - data_out_shake)}) < DEPTH) begin
- // Still space in FIFO after latest write
- // If theres a successful read on this clock cycle,
- // there will be an additional space in the FIFO next clock cycle
- // (number of pieces of data in the FIFO won't have changed)
- data_in_ready <= 1'b1;
- end else begin
- // FIFO is now full
- data_in_ready <= 1'b0;
- end
- end else begin
- // Unsuccessful handshake but space in FIFO
- // If there's write space now, next cc it will be the same or more
- // (more if a succesful read has been carried out in this cc)
- data_in_ready <= 1'b1;
- end
- end else begin
- if ((ptr_dif - {{(PTR_W-1){1'b0}}, data_out_shake}) < DEPTH) begin
- // If there is a successful read this clock cycle,
- // there will be space for another piece of data in the FIFO
- // (number of pieces of data in FIFO will have decremented by 1)
- data_in_ready <= 1'b1;
- end else begin
- // FIFO still Full
- data_in_ready <= 1'b0;
- end
- end
- // Read Logic
- if ((ptr_dif - 1) < DEPTH) begin
- // Data in FIFO - atleast one Piece of Data in FIFO
- // -> the "-1" causes dif of 0 to wrap where (dif - 1) becomes > DEPTH
- if (data_out_shake) begin
- // Successful Handshake Increment Read Pointer
- read_ptr <= read_ptr + 1;
- if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) - 1 < DEPTH) begin
- // Still Data in FIFO after latest Read
- // If there is a successful write this clock cycle,
- // there will be one more piece of data in the FIFO
- // (number of pieces of data in FIFO wont have changed)
- data_out_valid <= 1'b1;
- end else begin
- // FIFO empty after latest Read
- data_out_valid <= 1'b0;
- end
- end else begin
- // Unsuccessful handshake but Data in FIFO
- // If there's read data now, next cc it will be the same or more
- // (more if a succesful write has been carried out in this cc)
- data_out_valid <= 1'b1;
- end
- end else begin
- if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) < DEPTH) begin
- // If there is a successful write this clock cycle,
- // there will be one more piece of data in the FIFO
- // (number of pieces of data in FIFO will have incremented by 1)
- data_out_valid <= 1'b1;
- end else begin
- // FIFO still empty
- data_out_valid <= 1'b0;
- end
- end
- end else begin
- // If Enable is Low, set Control Low
- data_in_ready <= 1'b0;
- data_out_valid <= 1'b0;
- end
- end
-
- // Verif Notes to Check behaiour:
- // 1) Fill FIFO up with Data
- // 2) Read & Write in same clock cycle
-endmodule
diff --git a/sha-2-accelerator/hdl/src/sha256_1_3_arbitrator.sv b/sha-2-accelerator/hdl/src/sha256_1_3_arbitrator.sv
deleted file mode 100644
index f493aeb24beb08f367469965d4776411eb24ea69..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_1_3_arbitrator.sv
+++ /dev/null
@@ -1,163 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 1 to 3 Arbitrator
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-module sha256_1_to_3_arbitrator (
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // Data In data and Handshaking
- input logic [511:0] data_in,
- input logic data_in_last,
- input logic data_in_valid,
- output logic data_in_ready,
-
- // Data Out
- output logic [511:0] data_out,
- output logic data_out_last,
- output logic [4:0] data_out_packet_id,
-
- // Channel Enable - 1-hot
- input [2:0] channel_en,
-
- // Handshaking Channel 0
- output logic data_out_valid_0,
- input logic data_out_ready_0,
-
- // Handshaking Channel 1
- output logic data_out_valid_1,
- input logic data_out_ready_1,
-
- // Handshaking Channel 2
- output logic data_out_valid_2,
- input logic data_out_ready_2
-);
-
- logic [1:0] state, next_state;
- logic [1:0] channel_select, next_channel_select;
-
- logic [3:0] packet_id, next_packet_id;
-
- logic [511:0] next_data_out;
- logic [4:0] next_data_out_packet_id;
- logic next_data_out_last;
-
- logic [2:0] data_out_ready;
- logic [2:0] data_out_valid, next_data_out_valid;
-
- assign data_out_ready = {data_out_ready_0, data_out_ready_1, data_out_ready_2};
-
- assign data_out_valid_0 = data_out_valid[0];
- assign data_out_valid_1 = data_out_valid[1];
- assign data_out_valid_2 = data_out_valid[2];
-
- // State Machine Sequential Logic
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) | sync_rst) begin
- state <= 3'd0;
- data_in_ready <= 1'b0;
- data_out_valid_0 <= 1'b0;
- data_out_valid_1 <= 1'b0;
- data_out_valid_2 <= 1'b0;
- data_out_last <= 1'b0;
- data_out <= 256'd0;
- data_out_packet_id <= 4'd0;
- channel_select <= 2'd0;
- packet_id <= 4'd0;
- end else if (en == 1'b1) begin
- state <= next_state;
- data_out <= next_data_out;
- data_out_last <= next_data_out_last;
- data_out_packet_id <= next_data_out_packet_id;
- data_out_valid_0 <= next_data_out_valid_0;
- data_out_valid_1 <= next_data_out_valid_1;
- data_out_valid_2 <= next_data_out_valid_2;
- channel_select <= next_channel_select;
- packet_id <= next_packet_id;
- end else begin
- data_in_ready <= 1'b0;
- data_out_valid_0 <= 1'b0;
- data_out_valid_1 <= 1'b0;
- data_out_valid_2 <= 1'b0;
- end
- end
-
- always_comb begin
- // Default
- next_state = state;
- next_data_in_ready = data_in_ready;
- next_data_out_valid_0 = data_out_valid_0;
- next_data_out_valid_1 = data_out_valid_1;
- next_data_out_valid_2 = data_out_valid_2;
- next_data_out_last = data_out_last;
- next_data_out = data_out;
- next_channel_select = channel_select;
- next_packet_id = packet_id;
- next_data_out_packet_id = data_out_packet_id
-
- // Override
- case (state)
- 2'd0: begin
- if (!(data_out_valid[channel_select] && !data_out_ready[channel_select])) begin
- // If data out handshake has been seen, drop valid
- next_data_out_valid = 1'b0;
- end
- // Work out which Channel to use
- // - Check in order of value 0-2
- if (|data_out_ready) begin
- next_state = 2'd1;
- // If there is an avaliable channel, raise the ready signal on the input
- next_data_in_ready = 1'b1;
- if (data_out_ready[0] && channel_en[0]) next_channel_select = 2'd0;
- else if (data_out_ready[1] && channel_en[1]) next_channel_select = 2'd1;
- else if (data_out_ready[2] && channel_en[2]) next_channel_select = 2'd2;
- // De-assert Valid on all Channels
- next_data_out_valid = 3'd0;
- end else begin
- // No Channel is free, stay in this state
- next_state = 2'd0;
- end
- end
-
- 2'd1: begin
- // Check outputs can be written to
- if (data_out_valid[channel_select] && !data_out_ready[channel_select]) begin
- // If data out is valid and ready is low, there is already data waiting to be transferred
- next_data_in_ready = 1'b0;
- // If there is no Valid data at the output or there is a valid transfer happening on this clock cycle
- end else begin
- // These can be overloaded later if data is written to the outputs
- next_data_out_valid = 3'b0;
- next_data_in_ready = 1'b1;
- // Check Inputs have data
- if (data_in_valid && data_in_ready) begin
- // Valid Handshake and data can be processed
- // Data Processing Algorithm
- next_data_in_ready = 1'b0;
- // Write Input Data to Output
- next_data_out = data_in;
- next_data_out_packet_id = packet_id;
- next_data_out_last = data_in_last;
- next_data_out_valid = (3'b1 << next_channel_select);
- if (data_in_last) begin
- // Last Word of Packet - re-arbitrate
- // Increment Packet ID
- next_state = 2'd0;
- next_packet_id = packet_id + 4'd1;
- end
- end
- end
- end
- endcase
- end
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_config_sync.sv b/sha-2-accelerator/hdl/src/sha256_config_sync.sv
deleted file mode 100644
index 6f75f98ae86da5359655d8c0ba6ff360ccac2651..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_config_sync.sv
+++ /dev/null
@@ -1,204 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 Configuration Synchroniser
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-module sha256_config_sync (
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // ID In and Handshaking
- input logic [5:0] id_in,
- input logic id_in_last,
- input logic id_in_valid,
- output logic id_in_ready,
-
- // Config data and Handshaking
- input logic [63:0] cfg_in_size,
- input logic [1:0] cfg_in_scheme,
- input logic cfg_in_last,
- input logic cfg_in_valid,
- output logic cfg_in_ready,
-
- // Data Out data and Handshaking
- output logic [63:0] cfg_out_size,
- output logic [1:0] cfg_out_scheme,
- output logic [5:0] cfg_out_id,
- output logic cfg_out_last,
- output logic cfg_out_valid,
- input logic cfg_out_ready,
-
- // Status Out - Gets updated after every hash
- // - outputs size and then clears size to 0
- // - status regs are looking for non-zero size
- output logic [63:0] status_size
-);
-
- logic [1:0] state, next_state;
-
- logic next_cfg_in_ready;
- logic next_id_in_ready;
-
- logic [63:0] next_cfg_out_size;
- logic [1:0] next_cfg_out_scheme;
- logic [5:0] next_cfg_out_id;
- logic next_cfg_out_last;
- logic next_cfg_out_valid;
-
- logic [63:0] next_status_size;
-
- // State Machine Sequential Logic
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) | sync_rst) begin
- state <= 2'd0;
- cfg_out_size <= 64'd0;
- cfg_out_scheme <= 2'd0;
- cfg_out_id <= 6'd0;
- cfg_out_last <= 1'b0;
- cfg_out_valid <= 1'b0;
- cfg_in_ready <= 1'b0;
- id_in_ready <= 1'b0;
- status_size <= 64'd0;
- end else if (en == 1'b1) begin
- state <= next_state;
- cfg_out_size <= next_cfg_out_size;
- cfg_out_scheme <= next_cfg_out_scheme;
- cfg_out_id <= next_cfg_out_id;
- cfg_out_last <= next_cfg_out_last;
- cfg_out_valid <= next_cfg_out_valid;
- cfg_in_ready <= next_cfg_in_ready;
- id_in_ready <= next_id_in_ready;
- status_size <= next_status_size;
- end else begin
- cfg_out_valid <= 1'b0;
- cfg_in_ready <= 1'b0;
- id_in_ready <= 1'b0;
- status_size <= 64'd0;
- end
- end
-
- always_comb begin
- // Default
- next_state = state;
- next_cfg_out_size = cfg_out_size;
- next_cfg_out_scheme = cfg_out_scheme;
- next_cfg_out_id = cfg_out_id;
- next_cfg_out_last = cfg_out_last;
- next_cfg_out_valid = cfg_out_valid;
- next_cfg_in_ready = cfg_in_ready;
- next_id_in_ready = id_in_ready;
- next_status_size = status_size;
-
- // Override
- case (state)
- 2'd0: begin
- next_cfg_in_ready = 1'b1;
- next_id_in_ready = 1'b1;
- next_state = 2'd1;
- end
-
- 2'd1: begin
- // Handle Status Signals
- next_status_size = 64'd0;
- // Check outputs can be written to
- if (cfg_out_valid && !cfg_out_ready) begin
- // If data out is valid and ready is low, there is already data waiting to be transferred
- next_cfg_in_ready = 1'b0;
- next_id_in_ready = 1'b0;
- // If there is no Valid data at the output or there is a valid transfer happening on this clock cycle
- end else begin
- // These can be overloaded later if data is written to the outputs
- next_cfg_out_valid = 1'b0;
- next_cfg_in_ready = 1'b1;
- next_id_in_ready = 1'b1;
- next_cfg_out_last = 1'b0;
- // Check cfg input
- if (cfg_in_ready && cfg_in_valid) begin
- next_cfg_out_last = cfg_in_last;
- next_cfg_out_scheme = cfg_in_scheme;
- next_cfg_out_size = cfg_in_size;
- next_status_size = cfg_in_size;
- next_cfg_in_ready = 1'b0;
- next_state = 2'd2;
- end
- // Check Id input
- if (id_in_ready && id_in_valid) begin
- next_cfg_out_id = id_in;
- next_id_in_ready = 1'b0;
- next_state = 2'd3;
- end
- // Check if both inputs handshaked
- if ((id_in_ready && id_in_valid) && (cfg_in_ready && cfg_in_valid)) begin
- next_cfg_out_valid = 1'b1;
- if (!cfg_out_valid && cfg_out_ready) begin
- // In case where no valid data and ready is waiting for valid data
- // - (will be asserted next cc), guaranteed handshake next cycle
- next_cfg_in_ready = 1'b1;
- next_cfg_in_ready = 1'b1;
- end else begin
- next_cfg_in_ready = 1'b0;
- next_id_in_ready = 1'b0;
- end
- next_state = 2'd1;
- end
- end
- end
-
- 2'd2: begin // Cfg already handshaked - wait for ID handshake
- // Handle Status Signals
- next_status_size = 64'd0;
- // These can be overloaded later if data is written to the outputs
- next_cfg_out_valid = 1'b0;
- next_cfg_in_ready = 1'b0;
- next_id_in_ready = 1'b1;
- // Check Id input
- if (id_in_ready && id_in_valid) begin
- next_cfg_out_id = id_in;
- next_cfg_out_valid = 1'b1;
- if (cfg_out_ready) begin // Guaranteeded Handshake next clock cycle
- next_cfg_in_ready = 1'b1;
- next_id_in_ready = 1'b1;
- end else begin
- next_cfg_in_ready = 1'b0;
- next_id_in_ready = 1'b0;
- end
- next_state = 2'd1;
- end
- end
-
- 2'd3: begin // ID already handshaked - wait for config handshake
- // Handle Status Signals
- next_status_size = 64'd0;
- // These can be overloaded later if data is written to the outputs
- next_cfg_out_valid = 1'b0;
- next_cfg_in_ready = 1'b1;
- next_id_in_ready = 1'b0;
- // Check config input
- if (cfg_in_ready && cfg_in_valid) begin
- next_cfg_out_last = cfg_in_last;
- next_cfg_out_scheme = cfg_in_scheme;
- next_cfg_out_size = cfg_in_size;
- next_cfg_out_valid = 1'b1;
- next_status_size = cfg_in_size;
- if (cfg_out_ready) begin // Guaranteeded Handshake next clock cycle
- next_cfg_in_ready = 1'b1;
- next_id_in_ready = 1'b1;
- end else begin
- next_cfg_in_ready = 1'b0;
- next_id_in_ready = 1'b0;
- end
- next_state = 2'd1;
- end
- end
- endcase
- end
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_engine.sv b/sha-2-accelerator/hdl/src/sha256_engine.sv
deleted file mode 100644
index a5ff7736e324f1dfdaed36ba82d078da9d7835b2..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_engine.sv
+++ /dev/null
@@ -1,198 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 Engine Top-level
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`include "sha256_hash_compression.sv"
-`include "sha256_message_build.sv"
-`include "sha256_id_issue.sv"
-`include "fifo_vr.sv"
-
-module sha256_engine (
- // Clocking Signals
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // Data In data and Handshaking
- input logic [511:0] data_in,
- input logic data_in_last,
- input logic data_in_valid,
- output logic data_in_ready,
-
- // Config data and Handshaking
- input logic [63:0] cfg_size,
- input logic [1:0] cfg_scheme,
- input logic cfg_last,
- input logic cfg_valid,
- output logic cfg_ready,
-
- // Data Out data and Handshaking
- output logic [255:0] data_out,
- output logic data_out_last,
- output logic data_out_valid,
- input logic data_out_ready
-);
-
- logic [511:0] data_in_buffered;
- logic data_in_last_buffered;
- logic data_in_valid_buffered;
- logic data_in_ready_buffered;
-
- logic [63:0] cfg_size_buffered;
- logic [1:0] cfg_scheme_buffered;
- logic cfg_last_buffered;
- logic cfg_valid_buffered;
- logic cfg_ready_buffered;
-
- logic [5:0] id_val;
-
- logic [511:0] message_block;
- logic message_block_last;
- logic message_block_valid;
- logic message_block_ready;
-
- logic [511:0] message_block_buffered;
- logic message_block_last_buffered;
- logic message_block_valid_buffered;
- logic message_block_ready_buffered;
-
- logic [255:0] hash;
- logic hash_last;
- logic hash_valid;
- logic hash_ready;
-
- // Data-in FIFO
- fifo_vr #(16, // Depth
- 512 // Data Width
- ) data_in_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in),
- .data_in_valid (data_in_valid),
- .data_in_ready (data_in_ready),
- .data_in_last (data_in_last),
- .data_out (data_in_buffered),
- .data_out_last (data_in_last_buffered),
- .data_out_valid (data_in_valid_buffered),
- .data_out_ready (data_in_ready_buffered)
- );
-
- // Configuration FIFO
- fifo_vr #(8, // Depth
- 66 // Data Width
- ) cfg_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in ({cfg_size, cfg_scheme}),
- .data_in_valid (cfg_valid),
- .data_in_ready (cfg_ready),
- .data_in_last (cfg_last),
- .data_out ({cfg_size_buffered,cfg_scheme_buffered}),
- .data_out_last (cfg_last_buffered),
- .data_out_valid (cfg_valid_buffered),
- .data_out_ready (cfg_ready_buffered)
- );
-
- sha256_id_issue id_issue (
- .clk(clk),
- .nrst(nrst),
- .en(en),
- .sync_rst(sync_rst),
- .seed_in(6'd0),
- .seed_in_last(1'b1),
- .seed_in_valid(1'b0),
- .seed_in_ready(),
- .id_out(id_val),
- .id_out_last(),
- .id_out_valid(),
- .id_out_ready(1'b1)
- );
-
- // Message Build (Construct Message Blocks)
- sha256_message_build message_block_builder (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in_buffered),
- .data_in_valid (data_in_valid_buffered),
- .data_in_ready (data_in_ready_buffered),
- .data_in_last (data_in_last_buffered),
- .cfg_size (cfg_size_buffered),
- .cfg_scheme (cfg_scheme_buffered),
- .cfg_last (cfg_last_buffered),
- .cfg_valid (cfg_valid_buffered),
- .cfg_ready (cfg_ready_buffered),
- .data_out (message_block),
- .data_out_last (message_block_last),
- .data_out_valid (message_block_valid),
- .data_out_ready (message_block_ready)
- );
-
- // Intermediate FIFO
- fifo_vr #(16, // Depth
- 512 // Data Width
- ) message_block_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (message_block),
- .data_in_valid (message_block_valid),
- .data_in_ready (message_block_ready),
- .data_in_last (message_block_last),
- .data_out (message_block_buffered),
- .data_out_last (message_block_last_buffered),
- .data_out_valid (message_block_valid_buffered),
- .data_out_ready (message_block_ready_buffered)
- );
-
-
- // Hash Compression (Peform Hash Calculation)
- sha256_hash_compression hash_calculator (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (message_block_buffered),
- .data_in_valid (message_block_valid_buffered),
- .data_in_ready (message_block_ready_buffered),
- .data_in_last (message_block_last_buffered),
- .data_out (data_out),
- .data_out_last (data_out_last),
- .data_out_valid (data_out_valid),
- .data_out_ready (data_out_ready)
- );
-
- // // Data-out FIFO
- // fifo_vr #(4, // Depth
- // 256 // Data Width
- // ) data_out_buffer (
- // .clk (clk),
- // .nrst (nrst),
- // .en (en),
- // .sync_rst (sync_rst),
- // .data_in (hash),
- // .data_in_valid (hash_valid),
- // .data_in_ready (hash_ready),
- // .data_in_last (hash_last),
- // .data_out (data_out),
- // .data_out_last (data_out_last),
- // .data_out_valid (data_out_valid),
- // .data_out_ready (data_out_ready)
- // );
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_hash_compression.sv b/sha-2-accelerator/hdl/src/sha256_hash_compression.sv
deleted file mode 100644
index 942f241f57d2f0a78d7ef7e6056bc472feaf8729..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_hash_compression.sv
+++ /dev/null
@@ -1,370 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 Hash Processing Module
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`include "sha256_hashing_functions.svp"
-
-module sha256_hash_compression (
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // Data In data and Handshaking
- input logic [511:0] data_in,
- input logic [5:0] data_in_id,
- input logic data_in_last,
- input logic data_in_valid,
- output logic data_in_ready,
-
- // Data Out data and Handshaking
- output logic [255:0] data_out,
- output logic [5:0] data_out_id,
- output logic data_out_last,
- output logic data_out_valid,
- input logic data_out_ready
-);
-
- import sha256_hashing_functions::*;
-
- // Message Chunks
- logic [31:0] M [15:0];
-
- // Assign M Variables to 32 bit chunks of the input data
- genvar i;
- generate
- for (i = 0; i < 16; i++) begin
- assign M[i] = data_in[(32*((15-i)+1))-1:32*(15-i)];
- end
- endgenerate
-
- // Hash Value Registers
- logic [31:0] H [7:0];
- logic [31:0] next_H [7:0];
-
- // Message Schedule Registers
- logic [31:0] W [63:0];
- logic [31:0] next_W [63:0];
-
- // Working Registers
- logic [31:0] a,b,c,d,e,f,g,h;
- logic [31:0] next_a,next_b,next_c,next_d,next_e,next_f,next_g,next_h;
-
- // Working Combinatorial Words
- logic [31:0] T1, T2;
-
- // State Machine Registers
- logic [2:0] state, next_state;
- logic [255:0] next_data_out;
- logic [5:0] next_data_out_id;
- logic next_data_in_ready, next_data_out_valid, next_data_out_last;
- logic [5:0] hash_iter, next_hash_iter;
- logic last_block, next_last_block;
-
- logic [5:0] next_id, reg_id;
-
- // // SHA-2 Constants
- logic [31:0] K [63:0];
-
- assign K[0] = 32'h428a2f98;
- assign K[1] = 32'h71374491;
- assign K[2] = 32'hb5c0fbcf;
- assign K[3] = 32'he9b5dba5;
- assign K[4] = 32'h3956c25b;
- assign K[5] = 32'h59f111f1;
- assign K[6] = 32'h923f82a4;
- assign K[7] = 32'hab1c5ed5;
- assign K[8] = 32'hd807aa98;
- assign K[9] = 32'h12835b01;
- assign K[10] = 32'h243185be;
- assign K[11] = 32'h550c7dc3;
- assign K[12] = 32'h72be5d74;
- assign K[13] = 32'h80deb1fe;
- assign K[14] = 32'h9bdc06a7;
- assign K[15] = 32'hc19bf174;
- assign K[16] = 32'he49b69c1;
- assign K[17] = 32'hefbe4786;
- assign K[18] = 32'h0fc19dc6;
- assign K[19] = 32'h240ca1cc;
- assign K[20] = 32'h2de92c6f;
- assign K[21] = 32'h4a7484aa;
- assign K[22] = 32'h5cb0a9dc;
- assign K[23] = 32'h76f988da;
- assign K[24] = 32'h983e5152;
- assign K[25] = 32'ha831c66d;
- assign K[26] = 32'hb00327c8;
- assign K[27] = 32'hbf597fc7;
- assign K[28] = 32'hc6e00bf3;
- assign K[29] = 32'hd5a79147;
- assign K[30] = 32'h06ca6351;
- assign K[31] = 32'h14292967;
- assign K[32] = 32'h27b70a85;
- assign K[33] = 32'h2e1b2138;
- assign K[34] = 32'h4d2c6dfc;
- assign K[35] = 32'h53380d13;
- assign K[36] = 32'h650a7354;
- assign K[37] = 32'h766a0abb;
- assign K[38] = 32'h81c2c92e;
- assign K[39] = 32'h92722c85;
- assign K[40] = 32'ha2bfe8a1;
- assign K[41] = 32'ha81a664b;
- assign K[42] = 32'hc24b8b70;
- assign K[43] = 32'hc76c51a3;
- assign K[44] = 32'hd192e819;
- assign K[45] = 32'hd6990624;
- assign K[46] = 32'hf40e3585;
- assign K[47] = 32'h106aa070;
- assign K[48] = 32'h19a4c116;
- assign K[49] = 32'h1e376c08;
- assign K[50] = 32'h2748774c;
- assign K[51] = 32'h34b0bcb5;
- assign K[52] = 32'h391c0cb3;
- assign K[53] = 32'h4ed8aa4a;
- assign K[54] = 32'h5b9cca4f;
- assign K[55] = 32'h682e6ff3;
- assign K[56] = 32'h748f82ee;
- assign K[57] = 32'h78a5636f;
- assign K[58] = 32'h84c87814;
- assign K[59] = 32'h8cc70208;
- assign K[60] = 32'h90befffa;
- assign K[61] = 32'ha4506ceb;
- assign K[62] = 32'hbef9a3f7;
- assign K[63] = 32'hc67178f2;
-
- // ssig1 next_W assignments - issues using functions with arrayed objects in ivlog
- logic [31:0] ssig0_next_W [63:0];
- logic [31:0] ssig1_next_W [63:0];
-
- generate
- for (i=0; i < 64; i++) begin
- assign ssig0_next_W[i] = ((next_W[i] << 25) | (next_W[i] >> 7)) ^ ((next_W[i] << 14) | (next_W[i] >> 18)) ^ (next_W[i] >> 3);
- assign ssig1_next_W[i] = ((next_W[i] << 15) | (next_W[i] >> 17)) ^ ((next_W[i] << 13) | (next_W[i] >> 19)) ^ (next_W[i] >> 10);
- end
- endgenerate
-
- // State Machine Sequential Logic
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) | sync_rst) begin
- state <= 3'd0;
- hash_iter <= 6'd0;
- last_block <= 1'b0;
- data_in_ready <= 1'b0;
- data_out_valid <= 1'b0;
- data_out_last <= 1'b0;
- data_out <= 256'd0;
- data_out_id <= 6'd0;
- reg_id <= 6'd0;
- // Reset Working Registers
- a <= 32'd0;
- b <= 32'd0;
- c <= 32'd0;
- d <= 32'd0;
- e <= 32'd0;
- f <= 32'd0;
- g <= 32'd0;
- h <= 32'd0;
- // Reset H Registers
- for (int i=0; i < 8; i++) begin
- H[i] <= 32'd0;
- end
- // Reset W Registers
- for (int i=0; i < 64; i++) begin
- W[i] <= 32'd0;
- end
- end else if (en == 1'b1) begin
- state <= next_state;
- hash_iter <= next_hash_iter;
- last_block <= next_last_block;
- data_in_ready <= next_data_in_ready;
- data_out_valid <= next_data_out_valid;
- data_out_last <= next_data_out_last;
- data_out <= next_data_out;
- data_out_id <= next_data_out_id;
- reg_id <= next_id;
- // Set Working Registers
- a <= next_a;
- b <= next_b;
- c <= next_c;
- d <= next_d;
- e <= next_e;
- f <= next_f;
- g <= next_g;
- h <= next_h;
- // Set H Registers
- for (int i=0; i < 8; i++) begin
- H[i] <= next_H[i];
- end
- // Set W Registers
- for (int i=0; i < 64; i++) begin
- W[i] <= next_W[i];
- end
- end else begin
- data_in_ready <= 1'b0;
- data_out_valid <= 1'b0;
- end
- end
-
- // State Machine Combinatorial Logic
- always_comb begin
- // Default
- next_state = state;
- next_hash_iter = hash_iter;
- next_last_block = last_block;
- next_data_in_ready = data_in_ready;
- next_data_out_valid = data_out_valid;
- next_data_out_last = data_out_last;
- next_data_out = data_out;
- next_data_out_id = data_out_id;
- next_id = reg_id;
- // Set next Working Registers
- next_a = a;
- next_b = b;
- next_c = c;
- next_d = d;
- next_e = e;
- next_f = f;
- next_g = g;
- next_h = h;
- // Set next H Registers
- for (int i=0; i < 8; i++) begin
- next_H[i] = H[i];
- end
- // Set next W Registers
- for (int i=0; i < 64; i++) begin
- next_W[i] = W[i];
- end
- // Logic for Temporary Words
- T1 = h + bsig1(e) + ch(e,f,g) + K[hash_iter] + W[hash_iter];
- T2 = bsig0(a) + maj(a,b,c);
-
- // Override
- case (state)
- 3'd0: begin // Initialise Hash Registers
- if (!(data_out_valid && !data_out_ready)) begin
- // If data out handshake has been seen, drop valid
- next_data_out_valid = 1'b0;
- end
- // Initialise Hash Value Registers
- next_H[0] = 32'h6a09e667;
- next_H[1] = 32'hbb67ae85;
- next_H[2] = 32'h3c6ef372;
- next_H[3] = 32'ha54ff53a;
- next_H[4] = 32'h510e527f;
- next_H[5] = 32'h9b05688c;
- next_H[6] = 32'h1f83d9ab;
- next_H[7] = 32'h5be0cd19;
- next_data_in_ready = 1'b1;
- next_state = 3'd1;
- end
-
- 3'd1: begin // Perform Hash Initialisation
- if (!(data_out_valid && !data_out_ready)) begin
- // If data out handshake has been seen, drop valid
- next_data_out_valid = 1'b0;
- end
- if (data_in_valid && data_in_ready) begin
- // Valid Handshake and data can be processed
- // Use the Message chunks to populate the message schedule
- for (logic [31:0] t = 0; t < 64; t++) begin
- if (t < 16) begin
- next_W[t] = M[t];
- end else begin
- next_W[t] = ssig1_next_W[t-2] + next_W[t-32'd7] + ssig0_next_W[t-15] + next_W[t-32'd16];
- end
- end
- // Set Working Variables
- next_a = H[0];
- next_b = H[1];
- next_c = H[2];
- next_d = H[3];
- next_e = H[4];
- next_f = H[5];
- next_g = H[6];
- next_h = H[7];
- // Move to next state
- next_state = 3'd2;
- next_hash_iter = 6'd0;
- next_last_block = data_in_last;
- // Store ID Value
- next_id = data_in_id;
- // Drop Ready Signal to confirm handshake
- next_data_in_ready = 1'b0;
- end
- end
-
- 3'd2: begin // Perform the main hash computation
- if (!(data_out_valid && !data_out_ready)) begin
- // If data out handshake has been seen, drop valid
- next_data_out_valid = 1'b0;
- end
- // Perform Hash Function
- next_a = T1 + T2;
- next_b = a;
- next_c = b;
- next_d = c;
- next_e = d + T1;
- next_f = e;
- next_g = f;
- next_h = g;
- // Decrement Iteration Register
- next_hash_iter = hash_iter + 6'd1;
- if (hash_iter == 63) begin
- next_state = 3'd3;
- end
- end
-
- 3'd3: begin // Compute intermediate hash value
- if (!(data_out_valid && !data_out_ready)) begin
- // If data out handshake has been seen, drop valid
- next_data_out_valid = 1'b0;
- end
- if (last_block) begin
- if (!data_out_valid) begin // No Data waiting at output
- // Output updated H values
- next_data_out_id = reg_id;
- next_data_out = {a + H[0], b + H[1], c + H[2], d + H[3], e + H[4], f + H[5], g + H[6], h + H[7]};
- next_data_out_last = 1'b1;
- next_data_out_valid = 1'b1;
- // Next State Logic
- next_state = 3'd1;
- next_data_in_ready = 1'b1;
- // Initialise Hash Value Registers
- next_H[0] = 32'h6a09e667;
- next_H[1] = 32'hbb67ae85;
- next_H[2] = 32'h3c6ef372;
- next_H[3] = 32'ha54ff53a;
- next_H[4] = 32'h510e527f;
- next_H[5] = 32'h9b05688c;
- next_H[6] = 32'h1f83d9ab;
- next_H[7] = 32'h5be0cd19;
- end
- end else begin
- // Update H values for next message block
- next_H[0] = a + H[0];
- next_H[1] = b + H[1];
- next_H[2] = c + H[2];
- next_H[3] = d + H[3];
- next_H[4] = e + H[4];
- next_H[5] = f + H[5];
- next_H[6] = g + H[6];
- next_H[7] = h + H[7];
- // Next State Logic
- next_data_in_ready = 1'b1;
- next_state = 3'd1;
- end
- end
-
- default: begin
- next_state = 3'd0;
- end
- endcase
- end
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_hashing_functions.svp b/sha-2-accelerator/hdl/src/sha256_hashing_functions.svp
deleted file mode 100644
index 640d792cb2f1de4ad441f917ce11d7bd7c7316ec..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_hashing_functions.svp
+++ /dev/null
@@ -1,61 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 Engine function and constants SV Package
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-package sha256_hashing_functions;
- parameter data_width = 32;
-
- // SHA-2 Functions
- function logic [data_width-1:0] ssig0 (
- logic [data_width-1:0] x);
- logic [data_width-1:0] xrotr7, xrotr18, xshr3;
- xrotr7 = (x << 25) | (x >> 7);
- xrotr18 = (x << 14) | (x >> 18);
- xshr3 = x >> 3;
- ssig0 = xrotr7 ^ xrotr18 ^ xshr3;
- endfunction
-
- function logic [data_width-1:0] ssig1 (
- logic [data_width-1:0] x);
- logic [data_width-1:0] xrotr17, xrotr19, xshr10;
- xrotr17 = (x << 15) | (x >> 17);
- xrotr17 = (x << 13) | (x >> 19);
- xshr10 = x >> 10;
- ssig1 = xrotr17 ^ xrotr19 ^ xshr10;
- endfunction
-
- function logic [data_width-1:0] bsig0 (
- logic [data_width-1:0] x);
- logic [data_width-1:0] xrotr2, xrotr13, xrotr22;
- xrotr2 = (x << 30) | (x >> 2);
- xrotr13 = (x << 19) | (x >> 13);
- xrotr22 = (x << 10) | (x >> 22);
- bsig0 = xrotr2 ^ xrotr13 ^ xrotr22;
- endfunction
-
- function logic [data_width-1:0] bsig1 (
- logic [data_width-1:0] x);
- logic [data_width-1:0] xrotr6, xrotr11, xrotr25;
- xrotr6 = (x << 26) | (x >> 6);
- xrotr11 = (x << 21) | (x >> 11);
- xrotr25 = (x << 7) | (x >> 25);
- bsig1 = xrotr6 ^ xrotr11 ^ xrotr25;
- endfunction
-
- function logic [data_width-1:0] ch (
- logic [data_width-1:0] x, y, z);
- ch = (x & y) ^ ((~x) & z);
- endfunction
-
- function logic [data_width-1:0] maj (
- logic [data_width-1:0] x, y, z);
- maj = (x & y) ^ (x & z) ^ (y & z);
- endfunction
-endpackage
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_hashing_stream.sv b/sha-2-accelerator/hdl/src/sha256_hashing_stream.sv
deleted file mode 100644
index ae32bfe5a0efedf4e36b8242853aa2af24b31867..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_hashing_stream.sv
+++ /dev/null
@@ -1,191 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 Hashing Stream
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-// `include "sha256_hash_compression.sv"
-// `include "sha256_message_build.sv"
-// `include "sha256_id_issue.sv"
-// `include "fifo_vr.sv"
-
-module sha256_hashing_stream (
- // Clocking Signals
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // Data In data and Handshaking
- input logic [511:0] data_in,
- input logic data_in_last,
- input logic data_in_valid,
- output logic data_in_ready,
-
- // Config data and Handshaking
- input logic [63:0] cfg_size,
- input logic [1:0] cfg_scheme,
- input logic cfg_last,
- input logic cfg_valid,
- output logic cfg_ready,
-
- // Data Out data and Handshaking
- output logic [255:0] data_out,
- output logic data_out_last,
- output logic data_out_valid,
- input logic data_out_ready
-);
-
- logic [511:0] data_in_buffered;
- logic data_in_last_buffered;
- logic data_in_valid_buffered;
- logic data_in_ready_buffered;
-
- logic [63:0] cfg_size_buffered;
- logic [1:0] cfg_scheme_buffered;
- logic cfg_last_buffered;
- logic cfg_valid_buffered;
- logic cfg_ready_buffered;
-
- logic [5:0] id_val;
-
- logic [511:0] message_block;
- logic message_block_last;
- logic message_block_valid;
- logic message_block_ready;
-
- logic [511:0] message_block_buffered;
- logic message_block_last_buffered;
- logic message_block_valid_buffered;
- logic message_block_ready_buffered;
-
- logic [255:0] hash;
- logic hash_last;
- logic hash_valid;
- logic hash_ready;
-
- // Data-in FIFO
- fifo_vr #(16, // Depth
- 512 // Data Width
- ) data_in_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in),
- .data_in_valid (data_in_valid),
- .data_in_ready (data_in_ready),
- .data_in_last (data_in_last),
- .data_out (data_in_buffered),
- .data_out_last (data_in_last_buffered),
- .data_out_valid (data_in_valid_buffered),
- .data_out_ready (data_in_ready_buffered),
- .status_ptr_dif ()
- );
-
- // Configuration FIFO
- fifo_vr #(8, // Depth
- 66 // Data Width
- ) cfg_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in ({cfg_size, cfg_scheme}),
- .data_in_valid (cfg_valid),
- .data_in_ready (cfg_ready),
- .data_in_last (cfg_last),
- .data_out ({cfg_size_buffered,cfg_scheme_buffered}),
- .data_out_last (cfg_last_buffered),
- .data_out_valid (cfg_valid_buffered),
- .data_out_ready (cfg_ready_buffered),
- .status_ptr_dif ()
- );
-
- // Message Build (Construct Message Blocks)
- sha256_message_build message_block_builder (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in_buffered),
- .data_in_valid (data_in_valid_buffered),
- .data_in_ready (data_in_ready_buffered),
- .data_in_last (data_in_last_buffered),
- .cfg_size (cfg_size_buffered),
- .cfg_scheme (cfg_scheme_buffered),
- .cfg_last (cfg_last_buffered),
- .cfg_valid (cfg_valid_buffered),
- .cfg_ready (cfg_ready_buffered),
- .cfg_id (),
- .data_out (message_block),
- .data_out_last (message_block_last),
- .data_out_valid (message_block_valid),
- .data_out_ready (message_block_ready),
- .data_out_id ()
- );
-
- // Intermediate FIFO
- fifo_vr #(16, // Depth
- 512 // Data Width
- ) message_block_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (message_block),
- .data_in_valid (message_block_valid),
- .data_in_ready (message_block_ready),
- .data_in_last (message_block_last),
- .data_out (message_block_buffered),
- .data_out_last (message_block_last_buffered),
- .data_out_valid (message_block_valid_buffered),
- .data_out_ready (message_block_ready_buffered),
- .status_ptr_dif ()
- );
-
-
- // Hash Compression (Peform Hash Calculation)
- sha256_hash_compression hash_calculator (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (message_block_buffered),
- .data_in_valid (message_block_valid_buffered),
- .data_in_ready (message_block_ready_buffered),
- .data_in_last (message_block_last_buffered),
- .data_in_id (),
- .data_out (hash),
- .data_out_last (hash_last),
- .data_out_valid (hash_valid),
- .data_out_ready (hash_ready),
- .data_out_id ()
- );
-
- // Data-out FIFO
- fifo_vr #(4, // Depth
- 256 // Data Width
- ) data_out_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (hash),
- .data_in_valid (hash_valid),
- .data_in_ready (hash_ready),
- .data_in_last (hash_last),
- .data_out (data_out),
- .data_out_last (data_out_last),
- .data_out_valid (data_out_valid),
- .data_out_ready (data_out_ready),
- .status_ptr_dif ()
- );
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_id_buf.sv b/sha-2-accelerator/hdl/src/sha256_id_buf.sv
deleted file mode 100644
index 0af5f643f9c85eda02e542a2d63676831fc88604..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_id_buf.sv
+++ /dev/null
@@ -1,65 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 ID Buffer
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`include "fifo_vr.sv"
-
-module sha256_id_buf #(
- parameter DEPTH = 4,
- parameter ID_DATA_W = 6,
- parameter PTR_W = $clog2(DEPTH) // Read/Write Pointer Width
-)(
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // ID In
- input logic [ID_DATA_W-1:0] id_in,
- input logic id_in_last,
- input logic id_in_valid,
- output logic id_in_ready,
-
- // ID Out
- output logic [ID_DATA_W-1:0] id_out,
- output logic id_out_last,
- output logic id_out_valid,
- input logic id_out_ready,
-
- // Status Out
- output logic [ID_DATA_W-1:0] status_id, // ID being passed to Validator
- output logic [PTR_W:0] status_buffered_ids // Number of IDs in ID Validation Queue
-);
-
- logic [PTR_W:0] status_ptr_dif;
- fifo_vr #( DEPTH, // Depth
- ID_DATA_W // Data Width
- ) id_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (id_in),
- .data_in_last (id_in_last),
- .data_in_valid (id_in_valid),
- .data_in_ready (id_in_ready),
- .data_out (id_out),
- .data_out_last (id_out_last),
- .data_out_valid (id_out_valid),
- .data_out_ready (id_out_ready),
- .status_ptr_dif (status_ptr_dif)
- );
-
- // Status Signal Logic
- // - status ID is updated when id_out is updated
- assign status_buffered_ids = status_ptr_dif;
- assign status_id = id_out;
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_id_issue.sv b/sha-2-accelerator/hdl/src/sha256_id_issue.sv
deleted file mode 100644
index ac1d847be427da5b13fee9053a73cb6cd8d42a29..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_id_issue.sv
+++ /dev/null
@@ -1,103 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 ID Issuer
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-module sha256_id_issue (
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // Data Out - ID Out
- output logic [5:0] id_out,
- output logic id_out_last,
-
- // Concatenator Handshake
- output logic id_out_cfg_valid,
- input logic id_out_cfg_ready,
-
- // ID Buffer Handshake
- output logic id_out_buf_valid,
- input logic id_out_buf_ready
-);
-
- logic state, next_state;
-
- logic [5:0] next_id_out;
- logic next_id_out_last;
-
- logic next_id_out_cfg_valid;
- logic next_id_out_buf_valid;
-
-
- // State Machine Sequential Logic
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) | sync_rst) begin
- state <= 1'd0;
- id_out <= 6'd0;
- id_out_last <= 1'b0;
- id_out_cfg_valid <= 1'b0;
- id_out_buf_valid <= 1'b0;
- end else if (en == 1'b1) begin
- state <= next_state;
- id_out <= next_id_out;
- id_out_last <= next_id_out_last;
- id_out_cfg_valid <= next_id_out_cfg_valid;
- id_out_buf_valid <= next_id_out_buf_valid;
- end else begin
- id_out_cfg_valid <= 1'b0;
- id_out_buf_valid <= 1'b0;
- end
- end
-
- always_comb begin
- // Default
- next_state = state;
- next_id_out_cfg_valid = id_out_cfg_valid;
- next_id_out_buf_valid = id_out_buf_valid;
- next_id_out_last = id_out_last;
- next_id_out = id_out;
-
- // Override
- case (state)
- 1'd0: begin
- next_id_out_cfg_valid = 1'b1;
- next_id_out_buf_valid = 1'b1;
- next_state = 1'd1;
- end
-
- 1'd1: begin // Set Packet ID from Seed or Increment Value
- if (!(id_out_cfg_valid && !id_out_cfg_ready)) begin
- // If data out handshake has been seen, drop valid
- next_id_out_cfg_valid = 1'b0;
- end
- if (!(id_out_buf_valid && !id_out_buf_ready)) begin
- // If data out handshake has been seen, drop valid
- next_id_out_buf_valid = 1'b0;
- end
- // Always Last
- next_id_out_last = 1'b1;
- if ((!(id_out_cfg_valid && !id_out_cfg_ready)) && (!(id_out_buf_valid && !id_out_buf_ready))) begin
- // - if no data is seen on input, increment count
- // - if data is seen on input, count takes value of input
- // - there will always be valid data avaliable
- next_id_out_cfg_valid = 1'b1;
- next_id_out_buf_valid = 1'b1;
- next_id_out = id_out + 6'd1;
- end
- end
-
- default: begin
- next_state = 1'd0;
- end
- endcase
- end
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_id_validator.sv b/sha-2-accelerator/hdl/src/sha256_id_validator.sv
deleted file mode 100644
index 78c4b8ec5905d569cc67ebaf54004ecf58e32f00..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_id_validator.sv
+++ /dev/null
@@ -1,333 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 ID Validator
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-module sha256_id_validator (
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // ID Buffer IN
- input logic [5:0] id_in_buf,
- input logic id_in_buf_last,
- input logic id_in_buf_valid,
- output logic id_in_buf_ready,
-
- // Hash IN
- input logic [255:0] hash_in,
- input logic [5:0] hash_in_id,
- input logic hash_in_last,
- input logic hash_in_valid,
- output logic hash_in_ready,
-
- // Hash Out
- output logic [255:0] hash_out,
- output logic hash_out_err,
- output logic hash_out_last,
- output logic hash_out_valid,
- input logic hash_out_ready,
-
- // Status Out - Gets updated after every hash
- output logic [1:0] status_err,
- output logic [9:0] status_packet_count,
- input logic status_clear
-);
-
- logic [1:0] state, next_state;
-
- logic [255:0] next_hash_out;
- logic next_hash_out_err;
- logic next_hash_out_last, next_hash_out_valid;
- logic next_hash_in_ready, next_id_in_buf_ready;
-
- logic [255:0] hash_buf;
- logic [255:0] next_hash_buf;
-
- logic [5:0] hash_buf_id, id_buf;
- logic [5:0] next_hash_buf_id, next_id_buf;
-
- logic [5:0] hash_out_id, next_hash_out_id; //Debug
-
- // Status
- logic [1:0] next_status_err;
- logic [9:0] next_status_packet_count;
- // Status Error
- // bit 1 high - ID Buffer Error - Buffer has skipped and ID
- // bit 0 high - Hash ID Error - Packet has been dropped
-
- logic id_in_buf_msb;
- logic hash_in_id_msb;
-
- logic id_buf_msb;
- logic hash_buf_id_msb;
-
- assign id_in_buf_msb = id_in_buf[5];
- assign hash_in_id_msb = hash_in_id[5];
-
- assign id_buf_msb = id_buf[5];
- assign hash_buf_id_msb = hash_buf_id[5];
-
- // State Machine Sequential Logic
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) | sync_rst) begin
- state <= 2'd0;
- hash_out <= 256'd0;
- hash_out_err <= 1'b0;
- hash_out_last <= 1'b0;
- hash_out_valid <= 1'b0;
- hash_in_ready <= 1'b0;
- id_in_buf_ready <= 1'b0;
- hash_buf <= 256'd0;
- hash_buf_id <= 6'd0;
- id_buf <= 6'd0;
- hash_out_id <= 6'd0;
- status_err <= 2'b0;
- status_packet_count <= 10'd0;
- end else if (en == 1'b1) begin
- state <= next_state;
- hash_out <= next_hash_out;
- hash_out_err <= next_hash_out_err;
- hash_out_last <= next_hash_out_last;
- hash_out_valid <= next_hash_out_valid;
- hash_in_ready <= next_hash_in_ready;
- id_in_buf_ready <= next_id_in_buf_ready;
- hash_buf <= next_hash_buf;
- hash_buf_id <= next_hash_buf_id;
- id_buf <= next_id_buf;
- hash_out_id <= next_hash_out_id;
- status_packet_count <= next_status_packet_count;
- end else begin
- hash_out_valid <= 1'b0;
- hash_in_ready <= 1'b0;
- id_in_buf_ready <= 1'b0;
- end
- end
-
- always_comb begin
- // Default
- next_state = state;
- next_hash_out = hash_out;
- next_hash_out_err = hash_out_err;
- next_hash_out_last = hash_out_last;
- next_hash_out_valid = hash_out_valid;
- next_hash_in_ready = hash_in_ready;
- next_id_in_buf_ready = id_in_buf_ready;
- next_hash_buf = hash_buf;
- next_hash_buf_id = hash_buf_id;
- next_id_buf = id_buf;
- next_status_err = status_err;
- next_status_packet_count = status_packet_count;
- next_hash_out_id = hash_out_id;
-
- // Override
- case (state)
- 2'd0: begin
- next_hash_in_ready = 1'b1;
- next_id_in_buf_ready = 1'b1;
- next_state = 2'd1;
- end
-
- 2'd1: begin // Set Packet ID from Seed or Increment Value
- // Handle Status Signals
- if (status_clear) begin
- next_status_err = 2'b0;
- end
- // Check Whether Outputs Have Valid data waiting
- if (hash_out_valid && !hash_out_ready) begin
- // If data out handshake has not been seen, drop ready
- next_hash_in_ready = 1'b0;
- next_id_in_buf_ready = 1'b0;
- end else begin
- // Default Values
- next_hash_out_valid = 1'b0;
- next_hash_in_ready = 1'b1;
- next_id_in_buf_ready = 1'b1;
- // Check Hash Input Handshaked
- if (hash_in_ready && hash_in_valid) begin
- next_hash_in_ready = 1'b0;
- next_hash_buf = hash_in;
- next_hash_buf_id = hash_in_id;
- // Wait for ID Buffer State
- next_state = 2'd2;
- end
- // Check ID Buffer Input Handshaked
- if (id_in_buf_ready && id_in_buf_valid) begin
- next_id_in_buf_ready = 1'b0;
- next_id_buf = id_in_buf;
- // Wait for Hash Input State
- next_state = 2'd3;
- end
- // Check if Both Input Handshaked
- if ((hash_in_ready && hash_in_valid) && (id_in_buf_ready && id_in_buf_valid)) begin
- // Do ID's match?
- next_status_packet_count = status_packet_count + 1;
- next_hash_out = hash_in;
- next_hash_out_valid = 1'b1;
- next_hash_out_last = 1'b1;
- if (!hash_out_valid && hash_out_ready) begin
- // In case where no valid data and ready is waiting for valid data
- // - (will be asserted next cc), guaranteed handshake next cycle
- next_id_in_buf_ready = 1'b1;
- next_hash_in_ready = 1'b1;
- end else begin
- next_id_in_buf_ready = 1'b0;
- next_hash_in_ready = 1'b0;
- end
- // ID's don't match
- if ((id_in_buf > hash_in_id)||((~id_in_buf_msb & hash_in_id_msb) && (id_in_buf < 6'd10))) begin
- // If ID Buffer ID > Hash ID - ID Buffer Error
- // Pop an additional hash
- // Ensure another ID in Buf isn't popped
- next_hash_out_id = hash_in_id;
- next_id_in_buf_ready = 1'b0;
- next_state = 2'd3;
- next_hash_out_err = 1'b1;
- next_status_err = next_status_err | 2'b10;
- end else if ((id_in_buf < hash_in_id)||((id_in_buf_msb & ~hash_in_id_msb) && (hash_in_id < 6'd10))) begin
- // If ID Buffer ID < Hash ID - Lost Packet Error
- // Pop an additional value from the ID Buffer FIFO
- // Ensure another Hash isn't popped
- next_hash_out_id = id_in_buf;
- next_hash_in_ready = 1'b0;
- next_state = 2'd2;
- next_hash_out_err = 1'b1;
- next_status_err = next_status_err | 2'b01;
- end else begin
- next_hash_out_id = hash_in_id;
- next_hash_out_err = 1'b0;
- next_state = 2'd1;
- end
- end
- end
- end
-
- 2'd2: begin // Wait for ID Buffer Handshake
- // Handle Status Signal
- if (status_clear) begin
- next_status_err = 2'b0;
- end
- if (hash_out_valid && !hash_out_ready) begin
- // If data out handshake has not been seen, drop ready
- next_id_in_buf_ready = 1'b0;
- end else begin
- // Default Values
- next_id_in_buf_ready = 1'b1;
- next_hash_out_valid = 1'b0;
- // Has ID Buf Input Handshaked?
- if (id_in_buf_ready && id_in_buf_valid) begin
- // Put Hash On Output
- next_status_packet_count = status_packet_count + 1;
- next_hash_out = hash_buf;
- next_id_buf = id_in_buf;
- next_hash_out_last = 1'b1;
- next_hash_out_valid = 1'b1;
- if (!hash_out_valid && hash_out_ready) begin
- // In case where no valid data and ready is waiting for valid data
- // - (will be asserted next cc), guaranteed handshake next cycle
- next_id_in_buf_ready = 1'b1;
- next_hash_in_ready = 1'b1;
- end else begin
- next_id_in_buf_ready = 1'b0;
- next_hash_in_ready = 1'b0;
- end
- // ID's don't match
- if ((id_in_buf > hash_buf_id)||((~id_in_buf_msb & hash_buf_id_msb) && (id_in_buf < 6'd10))) begin
- // If ID Buffer ID > Hash ID - ID Buffer Error
- // Pop an additional hash
- // Ensure another ID in Buf isn't popped
- next_hash_out_id = hash_buf_id;
- next_id_in_buf_ready = 1'b0;
- next_state = 2'd3;
- next_hash_out_err = 1'b1;
- next_status_err = next_status_err | 2'b10;
- end else if ((id_in_buf < hash_buf_id)||((id_in_buf_msb & ~hash_buf_id_msb) && (6'd10 > hash_buf_id))) begin
- // If ID Buffer ID < Hash ID - Lost Packet Error
- // Pop an additional value from the ID Buffer FIFO
- // Ensure another Hash isn't popped
- next_hash_out_id = id_in_buf;
- next_hash_in_ready = 1'b0;
- next_state = 2'd2;
- next_hash_out_err = 1'b1;
- next_status_err = next_status_err | 2'b01;
- end else begin
- next_hash_out_id = hash_buf_id;
- next_hash_out_err = 1'b0;
- next_state = 2'd1;
- end
- end
- end
- end
-
- 2'd3: begin // Wait for Hash ID Handshake
- if (status_clear) begin
- next_status_err = 2'b0;
- end
- if (hash_out_valid && !hash_out_ready) begin
- // If data out handshake has not been seen, drop ready
- next_hash_in_ready = 1'b0;
- end else begin
- // Default Values
- next_hash_in_ready = 1'b1;
- next_hash_out_valid = 1'b0;
- // Has ID Buf Input Handshaked?
- if (hash_in_ready && hash_in_valid) begin
- // Put Hash On Output
- next_hash_buf = hash_in;
- next_hash_buf_id = hash_in_id;
- next_status_packet_count = status_packet_count + 1;
- next_hash_out = hash_in;
- next_hash_out_last = 1'b1;
- next_hash_out_valid = 1'b1;
- if (!hash_out_valid && hash_out_ready) begin
- // In case where no valid data and ready is waiting for valid data
- // - (will be asserted next cc), guaranteed handshake next cycle
- next_id_in_buf_ready = 1'b1;
- next_hash_in_ready = 1'b1;
- end else begin
- next_id_in_buf_ready = 1'b0;
- next_hash_in_ready = 1'b0;
- end
- // ID's don't match
- if ((id_buf > hash_in_id)||((~id_buf_msb & hash_in_id_msb) && (id_buf < 6'd10))) begin
- // If ID Buffer ID > Hash ID - ID Buffer Error
- // Pop an additional hash
- // Ensure another ID in Buf isn't popped
- next_hash_out_id = hash_in_id;
- next_id_in_buf_ready = 1'b0;
- next_state = 2'd3;
- next_hash_out_err = 1'b1;
- next_status_err = next_status_err | 2'b10;
- end else if ((id_buf < hash_in_id)||((id_buf_msb & ~hash_in_id_msb) && (6'd10 > hash_in_id))) begin
- // If ID Buffer ID < Hash ID - Lost Packet Error
- // Pop an additional value from the ID Buffer FIFO
- // Ensure another Hash isn't popped
- next_hash_out_id = id_buf;
- next_hash_in_ready = 1'b0;
- next_state = 2'd2;
- next_hash_out_err = 1'b1;
- next_status_err = next_status_err | 2'b01;
- end else begin
- // ID's Match
- next_hash_out_id = hash_in_id;
- next_state = 2'd1;
- next_hash_out_err = 1'b0;
- end
- end
- end
- end
-
- default: begin
- next_state = 2'd0;
- end
- endcase
- end
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_message_build.sv b/sha-2-accelerator/hdl/src/sha256_message_build.sv
deleted file mode 100644
index 836318b1935adefcca1a1e33e5753a6bf10363ca..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_message_build.sv
+++ /dev/null
@@ -1,253 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 Message Builder Module
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-module sha256_message_build (
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // Data In data and Handshaking
- input logic [511:0] data_in,
- input logic data_in_last,
- input logic data_in_valid,
- output logic data_in_ready,
-
- // Config data and Handshaking
- input logic [63:0] cfg_size,
- input logic [1:0] cfg_scheme,
- input logic [5:0] cfg_id,
- input logic cfg_last,
- input logic cfg_valid,
- output logic cfg_ready,
-
- // Data Out data and Handshaking
- output logic [511:0] data_out,
- output logic [5:0] data_out_id,
- output logic data_out_last,
- output logic data_out_valid,
- input logic data_out_ready
-);
-
- logic [8:0] data_word_rem, next_data_word_rem; // Remainder number of bits after 512 division
- logic [63:0] reg_cfg_size, next_cfg_size;
- logic [5:0] reg_cfg_id, next_cfg_id;
- logic [2:0] state, next_state; // State Machine State
- logic [54:0] data_word_count, next_data_word_count;
-
- logic next_data_in_ready, next_cfg_ready, next_data_out_valid, next_data_out_last;
- logic [511:0] next_data_out;
- logic [5:0] next_data_out_id;
-
- logic [511:0] last_word_mask;
- logic [511:0] end_marker;
- logic [511:0] last_data_word;
-
- // Create Mask for last Data Word
- // - If Muliple of 512, then no mask needed, else mask off valid data
- assign last_word_mask = |data_word_rem ? ((512'd1 << 512) - 1) << (512 - data_word_rem) : ((512'd1 << 512) - 1);
-
- // Create Position Marker to show end of data message (place a "1")
- // - only if not a multiple of 512
- assign end_marker = |data_word_rem ? 1 << (512 - data_word_rem - 1) : 512'd0; // BUG HERE!
-
- // Combine Last Data (after being masked) with end marker and size
- assign last_data_word = (data_in & last_word_mask) | end_marker;
-
- logic [54:0] word_extract;
- logic [8:0] rem_extract;
-
- logic extra_word, next_extra_word;
-
- assign word_extract = cfg_size[63:9];
- assign rem_extract = cfg_size[8:0];
-
- always_ff @(posedge clk, negedge nrst) begin
- if ((!nrst) | sync_rst) begin
- state <= 3'd0;
- data_in_ready <= 1'b0;
- cfg_ready <= 1'b1;
- reg_cfg_size <= 64'd0;
- reg_cfg_id <= 6'd0;
- data_word_rem <= 9'd0;
- data_out_valid <= 1'b0;
- data_out_last <= 1'b0;
- data_out <= 512'd0;
- data_out_id <= 6'd0;
- data_word_count <= 55'd0;
- extra_word <= 1'b0;
- end else if (en == 1'b1) begin
- state <= next_state;
- data_in_ready <= next_data_in_ready;
- cfg_ready <= next_cfg_ready;
- reg_cfg_size <= next_cfg_size;
- reg_cfg_id <= next_cfg_id;
- data_word_rem <= next_data_word_rem;
- data_out_valid <= next_data_out_valid;
- data_out_last <= next_data_out_last;
- data_out <= next_data_out;
- data_out_id <= next_data_out_id;
- data_word_count <= next_data_word_count;
- extra_word <= next_extra_word;
- end else begin
- data_in_ready <= 1'b0;
- data_out_valid <= 1'b0;
- end
- end
-
- always_comb begin
- // Default
- next_state = state;
- next_data_in_ready = data_in_ready;
- next_cfg_ready = cfg_ready;
- next_cfg_size = reg_cfg_size;
- next_cfg_id = reg_cfg_id;
- next_data_word_rem = data_word_rem;
- next_data_out_valid = data_out_valid;
- next_data_out_last = data_out_last;
- next_data_out = data_out;
- next_data_out_id = data_out_id;
- next_data_word_count = data_word_count;
- next_extra_word = extra_word;
-
- // Override
- case (state)
- 3'd0: begin // First time State
- next_cfg_ready = 1'b1;
- next_state = 3'd1;
- end
-
- 3'd1: begin // Initial Config Read
- if (!(data_out_valid && !data_out_ready)) begin
- // If data out handshake has been seen, drop valid
- next_data_out_valid = 1'b0;
- end
- // If there is no Valid data at the output or there is a valid transfer happening on this clock cycle
- if ((cfg_valid == 1'b1) && (cfg_ready == 1'b1)) begin
- // Check for already existing valid data at output
- if (data_out_valid && !data_out_ready) begin
- next_data_in_ready = 1'b0;
- end else begin
- next_data_in_ready = 1'b1;
- end
- // Handshake to Acknowledge Config Has been Read
- next_cfg_id = cfg_id;
- next_cfg_size = cfg_size;
- next_cfg_ready = 1'b0;
- next_data_word_count = word_extract + {53'd0, |rem_extract}; // Divide by 512 and round up
- next_data_word_rem = rem_extract;
- // Next State Logic
- if (next_data_word_count > 1) begin
- next_state = 3'd2;
- end else begin
- next_state = 3'd3;
- end
- end
- end
-
- 3'd2: begin // Pass through Data Blocks
- // Check outputs can be written to
- if (data_out_valid && !data_out_ready) begin
- // If data out is valid and ready is low, there is already data waiting to be transferred
- next_data_in_ready = 1'b0;
- // If there is no Valid data at the output or there is a valid transfer happening on this clock cycle
- end else begin
- // These can be overloaded later if data is written to the outputs
- next_data_out_valid = 1'b0;
- next_data_in_ready = 1'b1;
- next_data_out_last = 1'b0;
- // Check Inputs have data
- if (data_in_valid && data_in_ready) begin
- // Valid Handshake and data can be processed
- // Data Processing Algorithm
- next_data_in_ready = 1'b0;
- next_data_word_count = data_word_count - 1;
- // Write Input Data to Output
- next_data_out_id = reg_cfg_id;
- next_data_out = data_in;
- next_data_out_valid = 1'b1;
- next_data_out_last = 1'b0;
- if (next_data_word_count == 1) begin
- // Last Input Data Word
- next_state = 3'd3;
- end
- end
- end
- end
-
- 3'd3: begin // Process Last Read Word
- // Check outputs can be written to
- if (data_out_valid && !data_out_ready) begin
- // If data out is valid and ready is low, there is already data waiting to be transferred
- next_data_in_ready = 1'b0;
- // If there is no Valid data at the output or there is a valid transfer happening on this clock cycle
- end else begin
- // These can be overloaded later if data is written to the outputs
- next_data_out_valid = 1'b0;
- next_data_in_ready = 1'b1;
- // Check Inputs have data
- if (data_in_valid && data_in_ready) begin
- // Valid Handshake and data can be processed
- if ((data_word_rem - 1) > 9'd446) begin
- // If can't fit size in last word
- next_data_out_id = reg_cfg_id;
- next_data_out = last_data_word;
- next_data_out_valid = 1'b1;
- next_data_out_last = 1'b0;
- // NEXT STATE: Generate Additional Word
- next_state = 3'd4;
- next_data_in_ready = 1'b0;
- end else begin
- // Size can fit in last data word
- next_data_out_id = reg_cfg_id;
- next_data_out = last_data_word | {448'd0, reg_cfg_size};
- next_data_out_valid = 1'b1;
- next_data_out_last = 1'b1;
- next_data_word_count = data_word_count - 1;
- next_extra_word = 1'b1;
- // NEXT STATE: Read Next Config
- next_state = 3'd1;
- next_data_in_ready = 1'b0;
- next_cfg_ready = 1'b1;
- next_extra_word = 1'b0;
- end
- end
- end
- end
-
- 3'd4: begin // Generate Extra Word
- // Check outputs can be written to
- if (data_out_valid && !data_out_ready) begin
- // If data out is valid and ready is low, there is already data waiting to be transferred
- next_data_in_ready = 1'b0;
- // If there is no Valid data at the output or there is a valid transfer happening on this clock cycle
- end else begin
- // Size can fit in last data word
- next_data_out_id = reg_cfg_id;
- next_data_out = {~|data_word_rem, 447'd0, reg_cfg_size};
- next_data_out_valid = 1'b1;
- next_data_out_last = 1'b1;
- // NEXT STATE: Read Next Config
- next_state = 3'd1;
- next_data_in_ready = 1'b0;
- next_cfg_ready = 1'b1;
- next_extra_word = 1'b0;
- end
- end
-
- default: begin
- next_state = 3'd0;
- end
- endcase
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/src/sha256_packet_manager.sv b/sha-2-accelerator/hdl/src/sha256_packet_manager.sv
deleted file mode 100644
index be8170d8f6c37ac91af60dd6d700778fe2af2841..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/src/sha256_packet_manager.sv
+++ /dev/null
@@ -1,147 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-256 Packet Manager
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2023, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`include "sha256_id_buf.sv"
-`include "sha256_id_issue.sv"
-`include "sha256_id_validator.sv"
-`include "sha256_config_sync.sv"
-
-module sha256_packet_manager (
- // Clocking Signals
- input logic clk,
- input logic nrst,
- input logic en,
-
- // Synchronous, localised reset
- input logic sync_rst,
-
- // Config data and Handshaking
- input logic [63:0] cfg_in_size,
- input logic [1:0] cfg_in_scheme,
- input logic cfg_in_last,
- input logic cfg_in_valid,
- output logic cfg_in_ready,
-
- // Hash IN
- input logic [255:0] hash_in,
- input logic [5:0] hash_in_id,
- input logic hash_in_last,
- input logic hash_in_valid,
- output logic hash_in_ready,
-
- // Hash Out
- output logic [255:0] hash_out,
- output logic hash_out_err,
- output logic hash_out_last,
- output logic hash_out_valid,
- input logic hash_out_ready,
-
- // Status Signals
- output logic [5:0] status_id,
- output logic [1:0] status_err,
- output logic [9:0] status_packet_count,
- output logic [2:0] status_buffered_ids,
- output logic [63:0] status_size,
- input logic status_err_clear
-);
-
- logic [5:0] issue_id;
- logic issue_id_last;
- logic issue_id_buf_ready, issue_id_buf_valid;
- logic issue_id_cfg_ready, issue_id_cfg_valid;
-
- logic [5:0] id_buf_id;
- logic id_buf_id_last;
- logic id_buf_id_ready, id_buf_id_valid;
-
- logic [63:0] cfg_size;
- logic [1:0] cfg_scheme;
- logic [5:0] cfg_id;
- logic cfg_last;
- logic cfg_ready, cfg_valid;
-
- sha256_id_issue id_issuer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .id_out (issue_id),
- .id_out_last (issue_id_last),
- .id_out_cfg_valid (issue_id_cfg_valid),
- .id_out_cfg_ready (issue_id_cfg_ready),
- .id_out_buf_valid (issue_id_buf_valid),
- .id_out_buf_ready (issue_id_buf_ready)
- );
-
- sha256_config_sync config_synchroniser (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .id_in (issue_id),
- .id_in_last (issue_id_last),
- .id_in_valid (issue_id_cfg_valid),
- .id_in_ready (issue_id_cfg_ready),
- .cfg_in_size (cfg_in_size),
- .cfg_in_scheme (cfg_in_scheme),
- .cfg_in_last (cfg_in_last),
- .cfg_in_valid (cfg_in_valid),
- .cfg_in_ready (cfg_in_ready),
- .cfg_out_size (cfg_size),
- .cfg_out_scheme (cfg_scheme),
- .cfg_out_id (cfg_id),
- .cfg_out_last (cfg_last),
- .cfg_out_valid (cfg_valid),
- .cfg_out_ready (cfg_ready),
- .status_size (status_size)
- );
-
- sha256_id_buf id_buffer (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .id_in (issue_id),
- .id_in_last (issue_id_last),
- .id_in_valid (issue_id_buf_valid),
- .id_in_ready (issue_id_buf_ready),
- .id_out (id_buf_id),
- .id_out_last (id_buf_id_last),
- .id_out_valid (id_buf_id_valid),
- .id_out_ready (id_buf_id_ready),
- .status_id (status_id),
- .status_buffered_ids (status_buffered_ids)
- );
-
- sha256_id_validator id_validator (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .id_in_buf (id_buf_id),
- .id_in_buf_last (id_buf_id_last),
- .id_in_buf_valid (id_buf_id_valid),
- .id_in_buf_ready (id_buf_id_ready),
- .hash_in (hash_in),
- .hash_in_id (hash_in_id),
- .hash_in_last (hash_in_last),
- .hash_in_valid (hash_in_valid),
- .hash_in_ready (hash_in_ready),
- .hash_out (hash_out),
- .hash_out_err (hash_out_err),
- .hash_out_last (hash_out_last),
- .hash_out_valid (hash_out_valid),
- .hash_out_ready (hash_out_ready),
- .status_err (status_err),
- .status_packet_count (status_packet_count),
- .status_clear (status_err_clear)
- );
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_config_sync.sv b/sha-2-accelerator/hdl/verif/tb_sha256_config_sync.sv
deleted file mode 100644
index f8589bcf0e5af9ef53e16dba4284191d4f348473..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_config_sync.sv
+++ /dev/null
@@ -1,335 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 Config Synchroniser Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_config_sync.sv"
-
-module tb_sha256_config_sync;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
- // Data In data and Handshaking
- logic [5:0] id_in;
- logic id_in_last;
- logic id_in_valid;
- logic id_in_ready;
-
- // Config data and Handshaking
- logic [63:0] cfg_in_size;
- logic [1:0] cfg_in_scheme;
- logic cfg_in_last;
- logic cfg_in_valid;
- logic cfg_in_ready;
-
- // Data Out data and Handshaking
- logic [63:0] cfg_out_size;
- logic [1:0] cfg_out_scheme;
- logic [5:0] cfg_out_id;
- logic cfg_out_last;
- logic cfg_out_valid;
- logic cfg_out_ready;
-
-
- sha256_config_sync uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .id_in (id_in),
- .id_in_last (id_in_last),
- .id_in_valid (id_in_valid),
- .id_in_ready (id_in_ready),
- .cfg_in_size (cfg_in_size),
- .cfg_in_scheme (cfg_in_scheme),
- .cfg_in_last (cfg_in_last),
- .cfg_in_valid (cfg_in_valid),
- .cfg_in_ready (cfg_in_ready),
- .cfg_out_size (cfg_out_size),
- .cfg_out_scheme (cfg_out_scheme),
- .cfg_out_id (cfg_out_id),
- .cfg_out_last (cfg_out_last),
- .cfg_out_valid (cfg_out_valid),
- .cfg_out_ready (cfg_out_ready));
-
- logic id_in_drive_en;
- logic cfg_in_drive_en;
- logic cfg_out_drive_ready;
-
- logic [5:0] id_in_queue [$];
- logic id_in_last_queue [$];
- int id_in_gap_queue [$];
- logic id_in_wait_queue;
-
- logic [63:0] cfg_in_size_queue [$];
- logic [1:0] cfg_in_scheme_queue [$];
- logic cfg_in_last_queue [$];
- int cfg_in_gap_queue [$];
- logic cfg_in_wait_queue;
-
- logic [63:0] cfg_out_size_queue [$];
- logic [1:0] cfg_out_scheme_queue [$];
- logic [5:0] cfg_out_id_queue [$];
- logic cfg_out_last_queue [$];
- int cfg_out_stall_queue [$];
- logic cfg_out_wait_queue;
-
- // Handle Valid and Data for id_in
- always_ff @(posedge clk, negedge nrst) begin: id_in_valid_drive
- if (!nrst) begin
- id_in <= 512'd0;
- id_in_valid <= 1'b0;
- id_in_last <= 1'b0;
- id_in_gap <= 0;
- id_in_wait_queue <= 1'b1;
- end else if (id_in_drive_en) begin
- if (id_in_gap > 1) begin
- id_in_gap <= id_in_gap -1;
- id_in_valid <= 1'b0;
- end else begin
- id_in_valid <= 1'b1;
- end
- if (((id_in_valid == 1'b1) && (id_in_ready == 1'b1)) ||
- (id_in_wait_queue == 1'b1)) begin
- // Data transfer just completed or transfers already up to date
- if ((id_in_queue.size() > 0) && (id_in_last_queue.size() > 0) && (id_in_gap_queue.size() > 0)) begin
- id_in <= id_in_queue.pop_front();
- id_in_last <= id_in_last_queue.pop_front();
- if (id_in_gap_queue[0] == 0) begin
- id_in_valid <= 1'b1;
- end else begin
- id_in_valid <= 1'b0;
- end
- id_in_gap <= id_in_gap_queue.pop_front();
- id_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- id_in_wait_queue <= 1'b1;
- id_in_valid <= 1'b0;
- end
- end
- end
- end
-
- // Handle Valid and Data for cfg_in
- always_ff @(posedge clk, negedge nrst) begin: cfg_in_valid_drive
- if (!nrst) begin
- cfg_in_size <= 64'd0;
- cfg_in_scheme <= 2'd0;
- cfg_in_valid <= 1'b0;
- cfg_in_last <= 1'b0;
- cfg_in_gap <= 0;
- cfg_in_wait_queue <= 1'b1;
- end else if (cfg_in_drive_en) begin
- if (cfg_in_gap > 1) begin
- cfg_in_gap <= cfg_in_gap -1;
- cfg_in_valid <= 1'b0;
- end else begin
- cfg_in_valid <= 1'b1;
- end
- if (((cfg_in_valid == 1'b1) && (cfg_in_ready == 1'b1)) ||
- (cfg_in_wait_queue == 1'b1)) begin
- // cfg_in transfer just completed or transfers already up to date
- if ((cfg_in_size_queue.size() > 0) && (cfg_in_scheme_queue.size() > 0 ) && (cfg_in_last_queue.size() > 0) && (cfg_in_gap_queue.size() > 0)) begin
- cfg_in_size <= cfg_in_size_queue.pop_front();
- cfg_in_scheme <= cfg_in_scheme_queue.pop_front();
- cfg_in_last <= cfg_in_last_queue.pop_front();
- if (cfg_in_gap_queue[0] == 0) begin
- cfg_in_valid <= 1'b1;
- end else begin
- cfg_in_valid <= 1'b0;
- end
- cfg_in_gap <= cfg_in_gap_queue.pop_front();
- cfg_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- cfg_in_wait_queue <= 1'b1;
- cfg_in_valid <= 1'b0;
- end
- end
- end
- end
-
- logic [63:0] cfg_out_size_check;
- logic [1:0] cfg_out_scheme_check;
- logic [5:0] cfg_out_id_check;
- logic cfg_out_last_check;
-
- int id_in_gap;
- int cfg_in_gap;
- int cfg_out_stall;
-
- int packet_num;
-
- // Handle Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (cfg_out_drive_ready) begin
- // Count down to zero before enabling Ready
- if (cfg_out_stall > 1) begin
- cfg_out_stall <= cfg_out_stall - 1;
- cfg_out_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((cfg_out_valid == 1'b1) && (cfg_out_ready == 1'b1)) begin
- if (cfg_out_stall_queue.size() > 0) begin
- if (cfg_out_stall_queue[0] == 0) begin
- cfg_out_ready <= 1'b1;
- end else begin
- cfg_out_ready <= 1'b0;
- end
- cfg_out_stall <= cfg_out_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- cfg_out_ready <= 1'b1;
- end
- end
- end else begin
- cfg_out_ready <= 1'b0;
- end
- end
-
- // Handle Output Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((cfg_out_valid == 1'b1) && (cfg_out_ready == 1'b1)) begin
- // Check Size
- assert (cfg_out_size == cfg_out_size_check) else begin
- $error("cfg_out_size missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_size, cfg_out_size_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("cfg_out_size match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_size, cfg_out_size_check);
-
- // Check Scheme
- assert (cfg_out_scheme == cfg_out_scheme_check) else begin
- $error("cfg_out_scheme missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_scheme, cfg_out_scheme_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("cfg_out_scheme match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_scheme, cfg_out_scheme_check);
-
- // Check ID
- assert (cfg_out_id == cfg_out_id_check) else begin
- $error("cfg_out_id missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_id, cfg_out_id_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("cfg_out_id match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_id, cfg_out_id_check);
-
- // Check Last Flag
- assert (cfg_out_last == cfg_out_last_check) else begin
- $error("cfg_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, cfg_out_last, cfg_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("cfg_out_last match! packet %d | recieve: %x == check: %x", packet_num, cfg_out_last, cfg_out_last_check);
-
- // Pop new values
- if ((cfg_out_size_queue.size() > 0) && (cfg_out_scheme_queue.size() > 0) && (cfg_out_id_queue.size() > 0) && (cfg_out_last_queue.size() > 0)) begin
- cfg_out_size_check <= cfg_out_size_queue.pop_front();
- cfg_out_scheme_check <= cfg_out_scheme_queue.pop_front();
- cfg_out_id_check <= cfg_out_id_queue.pop_front();
- cfg_out_last_check <= cfg_out_last_queue.pop_front();
- if (cfg_out_last_check == 1'b1) begin
- packet_num <= packet_num + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [5:0] temp_id_in; // Temporary Input Data Storage
- logic temp_id_in_last; // Temporary Input Data Last
- int temp_id_in_gap; // Temporary Input Gap
-
- logic [63:0] temp_cfg_in_size; // Temporary cfg size
- logic [1:0] temp_cfg_in_scheme; // Temporary cfg scheme
- logic temp_cfg_in_last; // Temporary cfg last;
- int temp_cfg_in_gap; // Temporary cfg gap;
-
- logic [63:0] temp_cfg_out_size; // Temporary cfg size
- logic [1:0] temp_cfg_out_scheme; // Temporary cfg scheme
- logic [5:0] temp_cfg_out_id; // Temporary cfg id
- logic temp_cfg_out_last; // Temporary cfg last;
- int temp_cfg_out_stall; // Temporary cfg stall;
-
- initial begin
- $dumpfile("sha256_config_sync.vcd");
- $dumpvars(0, tb_sha256_config_sync);
- id_in_drive_en = 0;
- cfg_in_drive_en = 0;
- cfg_out_drive_ready = 0;
-
- // Read input data into Queue
- fd = $fopen("../stimulus/unit/input_id_stim.csv", "r");
- while ($fscanf (fd, "%d,%b,%d", temp_id_in, temp_id_in_last, temp_id_in_gap) == 3) begin
- id_in_queue.push_back(temp_id_in);
- id_in_last_queue.push_back(temp_id_in_last);
- id_in_gap_queue.push_back(temp_id_in_gap);
- end
- $fclose(fd);
-
- // Read input cfg into Queue
- fd = $fopen("../stimulus/unit/input_cfg_stim.csv", "r");
- while ($fscanf (fd, "%x,%x,%b,%d", temp_cfg_in_size, temp_cfg_in_scheme, temp_cfg_in_last, temp_cfg_in_gap) == 4) begin
- cfg_in_size_queue.push_back(temp_cfg_in_size);
- cfg_in_scheme_queue.push_back(temp_cfg_in_scheme);
- cfg_in_last_queue.push_back(temp_cfg_in_last);
- cfg_in_gap_queue.push_back(temp_cfg_in_gap);
- end
- $fclose(fd);
-
- // Read output data into Queue
- fd = $fopen("../stimulus/unit/output_cfg_sync_ref.csv", "r");
- while ($fscanf (fd, "%x,%x,%d,%b,%d", temp_cfg_out_size, temp_cfg_out_scheme, temp_cfg_out_id, temp_cfg_out_last, temp_cfg_out_stall) == 5) begin
- cfg_out_size_queue.push_back(temp_cfg_out_size);
- cfg_out_scheme_queue.push_back(temp_cfg_out_scheme);
- cfg_out_id_queue.push_back(temp_cfg_out_id);
- cfg_out_last_queue.push_back(temp_cfg_out_last);
- cfg_out_stall_queue.push_back(temp_cfg_out_stall);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- cfg_out_size_check = cfg_out_size_queue.pop_front();
- cfg_out_scheme_check = cfg_out_scheme_queue.pop_front();
- cfg_out_id_check = cfg_out_id_queue.pop_front();
- cfg_out_last_check = cfg_out_last_queue.pop_front();
- cfg_out_stall = cfg_out_stall_queue.pop_front();
-
- // Defaultly enable Message Builder
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
- #20 cfg_in_drive_en = 1;
-
- // Write some data into the config register
- # 30 id_in_drive_en = 1;
-
- # 30 cfg_out_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_engine.sv b/sha-2-accelerator/hdl/verif/tb_sha256_engine.sv
deleted file mode 100644
index 585a494c655587cc46e39a704464bb166780ce33..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_engine.sv
+++ /dev/null
@@ -1,366 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 Engine Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_engine.sv"
-
-module tb_sha256_engine;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
- // Data In data and Handshaking
- logic [511:0] data_in;
- logic data_in_last;
- logic data_in_valid;
- logic data_in_ready;
-
- // Config data and Handshaking
- logic [63:0] cfg_size;
- logic [1:0] cfg_scheme;
- logic cfg_last;
- logic cfg_valid;
- logic cfg_ready;
-
- // Data Out data and Handshaking
- logic [255:0] data_out;
- logic data_out_valid;
- logic data_out_ready;
- logic data_out_last;
-
- sha256_engine uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in),
- .data_in_valid (data_in_valid),
- .data_in_ready (data_in_ready),
- .data_in_last (data_in_last),
- .cfg_size (cfg_size),
- .cfg_scheme (cfg_scheme),
- .cfg_last (cfg_last),
- .cfg_valid (cfg_valid),
- .cfg_ready (cfg_ready),
- .data_out (data_out),
- .data_out_last (data_out_last),
- .data_out_valid (data_out_valid),
- .data_out_ready (data_out_ready)
- );
-
- logic data_in_drive_en;
- logic cfg_drive_en;
- logic data_out_drive_ready;
-
- logic [511:0] data_in_queue [$];
- logic data_in_last_queue [$];
- int data_in_gap_queue [$];
- logic data_in_wait_queue;
-
- logic [63:0] cfg_size_queue [$];
- logic [1:0] cfg_scheme_queue [$];
- logic cfg_last_queue [$];
- int cfg_gap_queue [$];
- logic cfg_wait_queue;
-
- logic [511:0] message_block_queue [$];
- logic message_block_last_queue [$];
- logic message_block_wait_queue;
-
- logic [255:0] data_out_queue [$];
- logic data_out_last_queue [$];
- int data_out_stall_queue [$];
- logic data_out_wait_queue;
-
- // Handle Valid and Data for data_in
- always_ff @(posedge clk, negedge nrst) begin: data_in_valid_drive
- if (!nrst) begin
- data_in <= 512'd0;
- data_in_valid <= 1'b0;
- data_in_last <= 1'b0;
- data_in_gap <= 0;
- data_in_wait_queue <= 1'b1;
- end else if (data_in_drive_en) begin
- if (data_in_gap > 1) begin
- data_in_gap <= data_in_gap -1;
- data_in_valid <= 1'b0;
- end else begin
- data_in_valid <= 1'b1;
- end
- if (((data_in_valid == 1'b1) && (data_in_ready == 1'b1)) ||
- (data_in_wait_queue == 1'b1)) begin
- // Data transfer just completed or transfers already up to date
- if ((data_in_queue.size() > 0) && (data_in_last_queue.size() > 0) && (data_in_gap_queue.size() > 0)) begin
- data_in <= data_in_queue.pop_front();
- data_in_last <= data_in_last_queue.pop_front();
- if (data_in_gap_queue[0] == 0) begin
- data_in_valid <= 1'b1;
- end else begin
- data_in_valid <= 1'b0;
- end
- data_in_gap <= data_in_gap_queue.pop_front();
- data_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- data_in_wait_queue <= 1'b1;
- data_in_valid <= 1'b0;
- end
- end
- end
- end
-
- // Handle Valid and Data for cfg
- always_ff @(posedge clk, negedge nrst) begin: cfg_valid_drive
- if (!nrst) begin
- cfg_size <= 64'd0;
- cfg_scheme <= 2'd0;
- cfg_valid <= 1'b0;
- cfg_last <= 1'b0;
- cfg_gap <= 0;
- cfg_wait_queue <= 1'b1;
- end else if (cfg_drive_en) begin
- if (cfg_gap > 1) begin
- cfg_gap <= cfg_gap -1;
- cfg_valid <= 1'b0;
- end else begin
- cfg_valid <= 1'b1;
- end
- if (((cfg_valid == 1'b1) && (cfg_ready == 1'b1)) ||
- (cfg_wait_queue == 1'b1)) begin
- // cfg transfer just completed or transfers already up to date
- if ((cfg_size_queue.size() > 0) && (cfg_scheme_queue.size() > 0 ) && (cfg_last_queue.size() > 0) && (cfg_gap_queue.size() > 0)) begin
- cfg_size <= cfg_size_queue.pop_front();
- cfg_scheme <= cfg_scheme_queue.pop_front();
- cfg_last <= cfg_last_queue.pop_front();
- if (cfg_gap_queue[0] == 0) begin
- cfg_valid <= 1'b1;
- end else begin
- cfg_valid <= 1'b0;
- end
- cfg_gap <= cfg_gap_queue.pop_front();
- cfg_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- cfg_wait_queue <= 1'b1;
- cfg_valid <= 1'b0;
- end
- end
- end
- end
-
- logic [511:0] message_block_data_out_check;
- logic message_block_data_out_last_check;
- int message_block_packet_num;
-
- logic [255:0] data_out_check;
- logic data_out_last_check;
- int data_in_gap;
- int cfg_gap;
- int data_out_stall;
-
- int packet_num;
-
- // Handle Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (data_out_drive_ready) begin
- // Count down to zero before enabling Ready
- if (data_out_stall > 1) begin
- data_out_stall <= data_out_stall - 1;
- data_out_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- if (data_out_stall_queue.size() > 0) begin
- if (data_out_stall_queue[0] == 0) begin
- data_out_ready <= 1'b1;
- end else begin
- data_out_ready <= 1'b0;
- end
- data_out_stall <= data_out_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- data_out_ready <= 1'b1;
- end
- end
- end else begin
- data_out_ready <= 1'b0;
- end
- end
-
- // Handle Output Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- assert (data_out == data_out_check) else begin
- $error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out match! packet %d | recieve: %x == check: %x", packet_num, data_out, data_out_check);
- assert (data_out_last == data_out_last_check) else begin
- $error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out_last match! packet %d | recieve: %x == check: %x", packet_num, data_out_last, data_out_last_check);
- if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
- data_out_check <= data_out_queue.pop_front();
- data_out_last_check <= data_out_last_queue.pop_front();
- if (data_out_last_check == 1'b1) begin
- packet_num <= packet_num + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
-
- // Check Message Block Handshake
- if ((message_builder_out_data_valid == 1'b1) && (message_builder_out_data_ready == 1'b1)) begin
- assert (message_builder_out_data == message_block_data_out_check) else begin
- $error("message block missmatch! packet %d | recieve: %x != check: %x", message_block_packet_num, data_out, message_block_data_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("message block match! packet %d | recieve: %x == check: %x", message_block_packet_num, message_builder_out_data, message_block_data_out_check);
- assert (message_builder_out_data_last == message_block_data_out_last_check) else begin
- $error("message block last missmatch! packet %d | recieve: %x != check: %x", message_block_packet_num, message_builder_out_data_last, message_block_data_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("message block last match! packet %d | recieve: %x == check: %x", message_block_packet_num, message_builder_out_data_last, message_block_data_out_last_check);
- if ((message_block_queue.size() > 0) && (message_block_last_queue.size() > 0)) begin
- message_block_data_out_check <= message_block_queue.pop_front();
- message_block_data_out_last_check <= message_block_last_queue.pop_front();
- if (message_block_data_out_last_check == 1'b1) begin
- message_block_packet_num <= message_block_packet_num + 1;
- end
- end
- end
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [511:0] input_data; // Temporary Input Data Storage
- logic input_data_last; // Temporary Input Data Last
- int input_data_gap; // Temporary Input Gap
-
- logic [63:0] input_cfg_size; // Temporary cfg size
- logic [1:0] input_cfg_scheme; // Temporary cfg scheme
- logic input_cfg_last; // Temporary cfg last;
- int input_cfg_gap; // Temporary cfg gap;
-
- logic [255:0] output_data; // Temporary Output Data Storage
- logic output_data_last; // Temporary Output Data Last
- int output_data_stall; // Temporary Output Stall
-
-
- logic [511:0] message_block_data; // Temporary Message Block Data Storage
- logic message_block_data_last; // Temporary Message Block Data Last
- int message_block_stall; // Dummy Variable to Read Stall Values into (goes unused other than file parsing)
-
- logic [511:0] message_builder_out_data;
- logic message_builder_out_data_last;
-
- assign message_builder_out_data = tb_sha256_engine.uut.message_block;
- assign message_builder_out_data_last = tb_sha256_engine.uut.message_block_last;
- assign message_builder_out_data_valid = tb_sha256_engine.uut.message_block_valid;
- assign message_builder_out_data_ready = tb_sha256_engine.uut.message_block_ready;
-
- initial begin
- $dumpfile("sha256_engine.vcd");
- $dumpvars(0, tb_sha256_engine);
- if ($test$plusargs ("DEBUG")) begin
- for (int i = 0; i < 16; i++) begin
- $dumpvars(0, tb_sha256_engine.uut.hash_calculator.M[i]);
- end
- for (int i = 0; i < 8; i++) begin
- $dumpvars(0, tb_sha256_engine.uut.hash_calculator.H[i]);
- $dumpvars(0, tb_sha256_engine.uut.hash_calculator.next_H[i]);
- end
- for (int i = 0; i < 64; i++) begin
- $dumpvars(0, tb_sha256_engine.uut.hash_calculator.W[i]);
- $dumpvars(0, tb_sha256_engine.uut.hash_calculator.next_W[i]);
- $dumpvars(0, tb_sha256_engine.uut.hash_calculator.ssig1_next_W[i]);
- end
- end
- data_in_drive_en = 0;
- cfg_drive_en = 0;
- data_out_drive_ready = 0;
-
- // Read input data into Queue
- fd = $fopen("../stimulus/unit/input_data_stim.csv", "r");
- while ($fscanf (fd, "%x,%b,%d", input_data, input_data_last, input_data_gap) == 3) begin
- data_in_queue.push_back(input_data);
- data_in_last_queue.push_back(input_data_last);
- data_in_gap_queue.push_back(input_data_gap);
- end
- $fclose(fd);
-
- // Read input cfg into Queue
- fd = $fopen("../stimulus/unit/input_cfg_stim.csv", "r");
- while ($fscanf (fd, "%x,%x,%b,%d", input_cfg_size, input_cfg_scheme, input_cfg_last, input_cfg_gap) == 4) begin
- cfg_size_queue.push_back(input_cfg_size);
- cfg_scheme_queue.push_back(input_cfg_scheme);
- cfg_last_queue.push_back(input_cfg_last);
- cfg_gap_queue.push_back(input_cfg_gap);
- end
- $fclose(fd);
-
- // Read output data into Queue
- fd = $fopen("../stimulus/unit/output_hash_ref.csv", "r");
- while ($fscanf (fd, "%x,%b,%d", output_data, output_data_last, output_data_stall) == 3) begin
- data_out_queue.push_back(output_data);
- data_out_last_queue.push_back(output_data_last);
- data_out_stall_queue.push_back(output_data_stall);
- end
- $fclose(fd);
-
- // Read Message Block data into Queue
- fd = $fopen("../stimulus/unit/output_message_block_ref.csv", "r");
- while ($fscanf (fd, "%x,%b,%d", message_block_data, message_block_data_last, message_block_stall) == 3) begin
- message_block_queue.push_back(message_block_data);
- message_block_last_queue.push_back(message_block_data_last);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- data_out_check = data_out_queue.pop_front();
- data_out_last_check = data_out_last_queue.pop_front();
- data_out_stall = data_out_stall_queue.pop_front();
-
- message_block_data_out_check = message_block_queue.pop_front();
- message_block_data_out_last_check = message_block_last_queue.pop_front();
-
- // Enable Hash Compression
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
- #20 data_in_drive_en = 1;
-
- // Write some data into the config register
- # 30 cfg_drive_en = 1;
-
- # 30 data_out_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_hash_compression.sv b/sha-2-accelerator/hdl/verif/tb_sha256_hash_compression.sv
deleted file mode 100644
index 7315a15f8567e7bb3c5bf98dfde6b872510d673d..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_hash_compression.sv
+++ /dev/null
@@ -1,253 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 Hash Compression Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_hash_compression.sv"
-
-module tb_sha256_hash_compression;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
- // Data In data and Handshaking
- logic [511:0] data_in;
- logic [5:0] data_in_id;
- logic data_in_last;
- logic data_in_valid;
- logic data_in_ready;
-
- // Data Out data and Handshaking
- logic [255:0] data_out;
- logic [5:0] data_out_id;
- logic data_out_valid;
- logic data_out_ready;
- logic data_out_last;
-
- sha256_hash_compression uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in),
- .data_in_id (data_in_id),
- .data_in_valid (data_in_valid),
- .data_in_ready (data_in_ready),
- .data_in_last (data_in_last),
- .data_out (data_out),
- .data_out_id (data_out_id),
- .data_out_last (data_out_last),
- .data_out_valid (data_out_valid),
- .data_out_ready (data_out_ready));
-
- logic data_in_drive_en;
- logic data_out_drive_ready;
-
- logic [511:0] data_in_queue [$];
- logic [5:0] data_in_id_queue [$];
- logic data_in_last_queue [$];
- int data_in_gap_queue [$];
- logic data_in_wait_queue;
-
-
- logic [255:0] data_out_queue [$];
- logic [5:0] data_out_id_queue [$];
- logic data_out_last_queue [$];
- int data_out_stall_queue [$];
- logic data_out_wait_queue;
-
- // Handle Valid and Data for data_in
- always_ff @(posedge clk, negedge nrst) begin: data_in_valid_drive
- if (!nrst) begin
- data_in <= 512'd0;
- data_in_id <= 6'd0;
- data_in_valid <= 1'b0;
- data_in_last <= 1'b0;
- data_in_gap <= 0;
- data_in_wait_queue <= 1'b1;
- end else if (data_in_drive_en) begin
- if (data_in_gap > 1) begin
- data_in_gap <= data_in_gap -1;
- data_in_valid <= 1'b0;
- end else begin
- data_in_valid <= 1'b1;
- end
- if (((data_in_valid == 1'b1) && (data_in_ready == 1'b1)) ||
- (data_in_wait_queue == 1'b1)) begin
- // Data transfer just completed or transfers already up to date
- if ((data_in_queue.size() > 0) && (data_in_id_queue.size() > 0) && (data_in_last_queue.size() > 0) && (data_in_gap_queue.size() > 0)) begin
- data_in <= data_in_queue.pop_front();
- data_in_id <= data_in_id_queue.pop_front();
- data_in_last <= data_in_last_queue.pop_front();
- if (data_in_gap_queue[0] == 0) begin
- data_in_valid <= 1'b1;
- end else begin
- data_in_valid <= 1'b0;
- end
- data_in_gap <= data_in_gap_queue.pop_front();
- data_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- data_in_wait_queue <= 1'b1;
- data_in_valid <= 1'b0;
- end
- end
- end
- end
-
-
- logic [255:0] data_out_check;
- logic [5:0] data_out_id_check;
- logic data_out_last_check;
-
- int data_in_gap;
- int data_out_stall;
-
- int packet_num;
-
- // Handle Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (data_out_drive_ready) begin
- // Count down to zero before enabling Ready
- if (data_out_stall > 1) begin
- data_out_stall <= data_out_stall - 1;
- data_out_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- if (data_out_stall_queue.size() > 0) begin
- if (data_out_stall_queue[0] == 0) begin
- data_out_ready <= 1'b1;
- end else begin
- data_out_ready <= 1'b0;
- end
- data_out_stall <= data_out_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- data_out_ready <= 1'b1;
- end
- end
- end else begin
- data_out_ready <= 1'b0;
- end
- end
-
- // Handle Output Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- assert (data_out == data_out_check) else begin
- $error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out match! packet %d | recieve: %x == check: %x", packet_num, data_out, data_out_check);
- assert (data_out_last == data_out_last_check) else begin
- $error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out_last match! packet %d | recieve: %x == check: %x", packet_num, data_out_last, data_out_last_check);
- if ((data_out_queue.size() > 0) && (data_out_id_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
- data_out_check <= data_out_queue.pop_front();
- data_out_id_check <= data_out_id_queue.pop_front();
- data_out_last_check <= data_out_last_queue.pop_front();
- if (data_out_last_check == 1'b1) begin
- packet_num <= packet_num + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [511:0] temp_data_in; // Temporary Input Data Storage
- logic [5:0] temp_data_in_id; // Temporary Input Data Storage
- logic temp_data_in_last; // Temporary Input Data Last
- int temp_data_in_gap; // Temporary Input Gap
-
-
- logic [255:0] temp_data_out; // Temporary Output Data Storage
- logic [5:0] temp_data_out_id; // Temporary Output Data Storage
- logic temp_data_out_last; // Temporary Output Data Last
- int temp_data_out_stall; // Temporary Output Stall
-
- initial begin
- $dumpfile("sha256_hash_compression.vcd");
- if ($test$plusargs ("DEBUG")) begin
- $dumpvars(0, tb_sha256_hash_compression);
- for (int i = 0; i < 16; i++) begin
- $dumpvars(0, tb_sha256_hash_compression.uut.M[i]);
- end
- for (int i = 0; i < 8; i++) begin
- $dumpvars(0, tb_sha256_hash_compression.uut.H[i]);
- $dumpvars(0, tb_sha256_hash_compression.uut.next_H[i]);
- end
- for (int i = 0; i < 64; i++) begin
- $dumpvars(0, tb_sha256_hash_compression.uut.W[i]);
- $dumpvars(0, tb_sha256_hash_compression.uut.next_W[i]);
- $dumpvars(0, tb_sha256_hash_compression.uut.ssig1_next_W[i]);
- end
- end
- data_in_drive_en = 0;
- data_out_drive_ready = 0;
-
- // Read input data into Queue
- fd = $fopen("../stimulus/unit/input_message_block_stim.csv", "r");
- while ($fscanf (fd, "%x,%d,%b,%d", temp_data_in, temp_data_in_id, temp_data_in_last, temp_data_in_gap) == 4) begin
- data_in_queue.push_back(temp_data_in);
- data_in_id_queue.push_back(temp_data_in_id);
- data_in_last_queue.push_back(temp_data_in_last);
- data_in_gap_queue.push_back(temp_data_in_gap);
- end
- $fclose(fd);
-
- // Read output data into Queue
- fd = $fopen("../stimulus/unit/output_hash_ref.csv", "r");
- while ($fscanf (fd, "%x,%d,%b,%d", temp_data_out, temp_data_out_id, temp_data_out_last, temp_data_out_stall) == 4) begin
- data_out_queue.push_back(temp_data_out);
- data_out_id_queue.push_back(temp_data_out_id);
- data_out_last_queue.push_back(temp_data_out_last);
- data_out_stall_queue.push_back(temp_data_out_stall);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- data_out_check = data_out_queue.pop_front();
- data_out_id_check = data_out_id_queue.pop_front();
- data_out_last_check = data_out_last_queue.pop_front();
- data_out_stall = data_out_stall_queue.pop_front();
-
- // Enable Hash Compression
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
- #20 data_in_drive_en = 1;
-
- # 30 data_out_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_hashing_stream.sv b/sha-2-accelerator/hdl/verif/tb_sha256_hashing_stream.sv
deleted file mode 100644
index 3aa7c57167d1d35f419ef82d87cf5e9cde9f6204..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_hashing_stream.sv
+++ /dev/null
@@ -1,331 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 Hashing Stream Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_hashing_stream.sv"
-
-module tb_sha256_hashing_stream;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
- // Data In data and Handshaking
- logic [511:0] data_in;
- logic data_in_last;
- logic data_in_valid;
- logic data_in_ready;
-
- // Config data and Handshaking
- logic [63:0] cfg_size;
- logic [1:0] cfg_scheme;
- logic cfg_last;
- logic cfg_valid;
- logic cfg_ready;
-
- // Data Out data and Handshaking
- logic [255:0] data_out;
- logic data_out_valid;
- logic data_out_ready;
- logic data_out_last;
-
- sha256_hashing_stream uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in),
- .data_in_valid (data_in_valid),
- .data_in_ready (data_in_ready),
- .data_in_last (data_in_last),
- .cfg_size (cfg_size),
- .cfg_scheme (cfg_scheme),
- .cfg_last (cfg_last),
- .cfg_valid (cfg_valid),
- .cfg_ready (cfg_ready),
- .data_out (data_out),
- .data_out_last (data_out_last),
- .data_out_valid (data_out_valid),
- .data_out_ready (data_out_ready)
- );
-
- logic data_in_drive_en;
- logic cfg_drive_en;
- logic data_out_drive_ready;
-
- logic [511:0] data_in_queue [$];
- logic data_in_last_queue [$];
- int data_in_gap_queue [$];
- logic data_in_wait_queue;
-
- logic [63:0] cfg_size_queue [$];
- logic [1:0] cfg_scheme_queue [$];
- logic cfg_last_queue [$];
- int cfg_gap_queue [$];
- logic cfg_wait_queue;
-
- logic [511:0] message_block_queue [$];
- logic message_block_last_queue [$];
- logic message_block_wait_queue;
-
- logic [255:0] data_out_queue [$];
- logic data_out_last_queue [$];
- int data_out_stall_queue [$];
- logic data_out_wait_queue;
-
- // Handle Valid and Data for data_in
- always_ff @(posedge clk, negedge nrst) begin: data_in_valid_drive
- if (!nrst) begin
- data_in <= 512'd0;
- data_in_valid <= 1'b0;
- data_in_last <= 1'b0;
- data_in_gap <= 0;
- data_in_wait_queue <= 1'b1;
- end else if (data_in_drive_en) begin
- if (data_in_gap > 1) begin
- data_in_gap <= data_in_gap -1;
- data_in_valid <= 1'b0;
- end else begin
- data_in_valid <= 1'b1;
- end
- if (((data_in_valid == 1'b1) && (data_in_ready == 1'b1)) ||
- (data_in_wait_queue == 1'b1)) begin
- // Data transfer just completed or transfers already up to date
- if ((data_in_queue.size() > 0) && (data_in_last_queue.size() > 0) && (data_in_gap_queue.size() > 0)) begin
- data_in <= data_in_queue.pop_front();
- data_in_last <= data_in_last_queue.pop_front();
- if (data_in_gap_queue[0] == 0) begin
- data_in_valid <= 1'b1;
- end else begin
- data_in_valid <= 1'b0;
- end
- data_in_gap <= data_in_gap_queue.pop_front();
- data_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- data_in_wait_queue <= 1'b1;
- data_in_valid <= 1'b0;
- end
- end
- end
- end
-
- // Handle Valid and Data for cfg
- always_ff @(posedge clk, negedge nrst) begin: cfg_valid_drive
- if (!nrst) begin
- cfg_size <= 64'd0;
- cfg_scheme <= 2'd0;
- cfg_valid <= 1'b0;
- cfg_last <= 1'b0;
- cfg_gap <= 0;
- cfg_wait_queue <= 1'b1;
- end else if (cfg_drive_en) begin
- if (cfg_gap > 1) begin
- cfg_gap <= cfg_gap -1;
- cfg_valid <= 1'b0;
- end else begin
- cfg_valid <= 1'b1;
- end
- if (((cfg_valid == 1'b1) && (cfg_ready == 1'b1)) ||
- (cfg_wait_queue == 1'b1)) begin
- // cfg transfer just completed or transfers already up to date
- if ((cfg_size_queue.size() > 0) && (cfg_scheme_queue.size() > 0 ) && (cfg_last_queue.size() > 0) && (cfg_gap_queue.size() > 0)) begin
- cfg_size <= cfg_size_queue.pop_front();
- cfg_scheme <= cfg_scheme_queue.pop_front();
- cfg_last <= cfg_last_queue.pop_front();
- if (cfg_gap_queue[0] == 0) begin
- cfg_valid <= 1'b1;
- end else begin
- cfg_valid <= 1'b0;
- end
- cfg_gap <= cfg_gap_queue.pop_front();
- cfg_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- cfg_wait_queue <= 1'b1;
- cfg_valid <= 1'b0;
- end
- end
- end
- end
-
- logic [511:0] message_block_data_out_check;
- logic message_block_data_out_last_check;
- int message_block_packet_num;
-
- logic [255:0] data_out_check;
- logic data_out_last_check;
- int data_in_gap;
- int cfg_gap;
- int data_out_stall;
-
- int packet_num;
-
- // Handle Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (data_out_drive_ready) begin
- // Count down to zero before enabling Ready
- if (data_out_stall > 1) begin
- data_out_stall <= data_out_stall - 1;
- data_out_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- if (data_out_stall_queue.size() > 0) begin
- if (data_out_stall_queue[0] == 0) begin
- data_out_ready <= 1'b1;
- end else begin
- data_out_ready <= 1'b0;
- end
- data_out_stall <= data_out_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- data_out_ready <= 1'b1;
- end
- end
- end else begin
- data_out_ready <= 1'b0;
- end
- end
-
- // Handle Output Data Verification
- always @(posedge clk) begin
- // Check Data In Handshake
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- assert (data_out == data_out_check) else begin
- $error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out match! packet %d | recieve: %x == check: %x", packet_num, data_out, data_out_check);
- assert (data_out_last == data_out_last_check) else begin
- $error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out_last match! packet %d | recieve: %x == check: %x", packet_num, data_out_last, data_out_last_check);
- if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
- data_out_check <= data_out_queue.pop_front();
- data_out_last_check <= data_out_last_queue.pop_front();
- if (data_out_last_check == 1'b1) begin
- packet_num <= packet_num + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
-
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [511:0] input_data; // Temporary Input Data Storage
- logic input_data_last; // Temporary Input Data Last
- int input_data_gap; // Temporary Input Gap
-
- logic [63:0] input_cfg_size; // Temporary cfg size
- logic [1:0] input_cfg_scheme; // Temporary cfg scheme
- logic input_cfg_last; // Temporary cfg last;
- int input_cfg_gap; // Temporary cfg gap;
-
- logic [255:0] output_data; // Temporary Output Data Storage
- logic [4:0] output_data_id; // Temporary Output Data ID
- logic output_data_last; // Temporary Output Data Last
- int output_data_stall; // Temporary Output Stall
-
-
- logic [511:0] message_block_data; // Temporary Message Block Data Storage
- logic message_block_data_last; // Temporary Message Block Data Last
- int message_block_stall; // Dummy Variable to Read Stall Values into (goes unused other than file parsing)
-
- logic [511:0] message_builder_out_data;
- logic message_builder_out_data_last;
-
- initial begin
- $dumpfile("sha256_hashing_stream.vcd");
- $dumpvars(0, tb_sha256_hashing_stream);
- if ($test$plusargs ("DEBUG")) begin
- for (int i = 0; i < 16; i++) begin
- $dumpvars(0, tb_sha256_hashing_stream.uut.hash_calculator.M[i]);
- end
- for (int i = 0; i < 8; i++) begin
- $dumpvars(0, tb_sha256_hashing_stream.uut.hash_calculator.H[i]);
- $dumpvars(0, tb_sha256_hashing_stream.uut.hash_calculator.next_H[i]);
- end
- for (int i = 0; i < 64; i++) begin
- $dumpvars(0, tb_sha256_hashing_stream.uut.hash_calculator.W[i]);
- $dumpvars(0, tb_sha256_hashing_stream.uut.hash_calculator.next_W[i]);
- $dumpvars(0, tb_sha256_hashing_stream.uut.hash_calculator.ssig1_next_W[i]);
- end
- end
- data_in_drive_en = 0;
- cfg_drive_en = 0;
- data_out_drive_ready = 0;
-
- // Read input data into Queue
- fd = $fopen("../stimulus/unit/input_data_stim.csv", "r");
- while ($fscanf (fd, "%x,%b,%d", input_data, input_data_last, input_data_gap) == 3) begin
- data_in_queue.push_back(input_data);
- data_in_last_queue.push_back(input_data_last);
- data_in_gap_queue.push_back(input_data_gap);
- end
- $fclose(fd);
-
- // Read input cfg into Queue
- fd = $fopen("../stimulus/unit/input_cfg_stim.csv", "r");
- while ($fscanf (fd, "%x,%x,%b,%d", input_cfg_size, input_cfg_scheme, input_cfg_last, input_cfg_gap) == 4) begin
- cfg_size_queue.push_back(input_cfg_size);
- cfg_scheme_queue.push_back(input_cfg_scheme);
- cfg_last_queue.push_back(input_cfg_last);
- cfg_gap_queue.push_back(input_cfg_gap);
- end
- $fclose(fd);
-
- // Read output data into Queue
- fd = $fopen("../stimulus/unit/output_hash_ref.csv", "r");
- while ($fscanf (fd, "%x, %d, %b, %d", output_data, output_data_id, output_data_last, output_data_stall) == 4) begin
- data_out_queue.push_back(output_data);
- data_out_last_queue.push_back(output_data_last);
- data_out_stall_queue.push_back(output_data_stall);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- data_out_check = data_out_queue.pop_front();
- data_out_last_check = data_out_last_queue.pop_front();
- data_out_stall = data_out_stall_queue.pop_front();
-
- // Enable Hash Compression
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
- #20 data_in_drive_en = 1;
-
- // Write some data into the config register
- # 30 cfg_drive_en = 1;
-
- # 30 data_out_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_id_buf.sv b/sha-2-accelerator/hdl/verif/tb_sha256_id_buf.sv
deleted file mode 100644
index 640b7aba2c343a22edbb04489fa83050a20ebb8e..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_id_buf.sv
+++ /dev/null
@@ -1,257 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 ID Buffer Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_id_buf.sv"
-
-module tb_sha256_id_buf;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
-
- // ID Buffer IN
- logic [5:0] id_in;
- logic id_in_last;
- logic id_in_valid;
- logic id_in_ready;
-
- // ID Out
- logic [5:0] id_out;
- logic id_out_last;
- logic id_out_valid;
- logic id_out_ready;
-
- // Status Out - Gets updated after every hash
- logic [5:0] status_id;
-
-
- sha256_id_buf uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
-
- // ID IN
- .id_in (id_in),
- .id_in_last (id_in_last),
- .id_in_valid (id_in_valid),
- .id_in_ready (id_in_ready),
-
- // ID Out
- .id_out (id_out),
- .id_out_last (id_out_last),
- .id_out_valid (id_out_valid),
- .id_out_ready (id_out_ready),
-
- // Status Out - Gets updated on every output Handshake
- .status_id (status_id)
- );
-
- logic id_in_drive_en;
-
- logic id_out_drive_ready;
-
- logic [5:0] id_in_queue [$];
- logic id_in_last_queue [$];
- int id_in_gap_queue [$];
- logic id_in_wait_queue;
-
- logic [5:0] id_out_queue [$];
- logic [5:0] status_id_out_queue [$];
- logic id_out_last_queue [$];
- int id_out_stall_queue [$];
- logic id_out_wait_queue;
-
- // TODO: Handle Status Checking
-
- // Handle Valid and Data for id_in
- always_ff @(posedge clk, negedge nrst) begin: id_in_valid_drive
- if (!nrst) begin
- id_in <= 6'd0;
- id_in_valid <= 1'b0;
- id_in_last <= 1'b0;
- id_in_gap <= 0;
- id_in_wait_queue <= 1'b1;
- end else if (id_in_drive_en) begin
- if (id_in_gap > 1) begin
- id_in_gap <= id_in_gap - 1;
- id_in_valid <= 1'b0;
- end else begin
- id_in_valid <= 1'b1;
- end
- if (((id_in_valid == 1'b1) && (id_in_ready == 1'b1)) ||
- (id_in_wait_queue == 1'b1)) begin
- // Data transfer just completed or transfers already up to date
- if ((id_in_queue.size() > 0) && (id_in_last_queue.size() > 0) && (id_in_gap_queue.size() > 0)) begin
- id_in <= id_in_queue.pop_front();
- id_in_last <= id_in_last_queue.pop_front();
- if (id_in_gap_queue[0] == 0) begin
- id_in_valid <= 1'b1;
- end else begin
- id_in_valid <= 1'b0;
- end
- id_in_gap <= id_in_gap_queue.pop_front();
- id_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- id_in_wait_queue <= 1'b1;
- id_in_valid <= 1'b0;
- end
- end
- end
- end
-
- logic [5:0] id_out_check;
- logic [5:0] status_id_out_check;
- logic id_out_last_check;
-
- int id_in_gap;
- int id_out_stall;
-
- int packet_num;
-
- // Handle Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (id_out_drive_ready) begin
- // Count down to zero before enabling Ready
- if (id_out_stall > 1) begin
- id_out_stall <= id_out_stall - 1;
- id_out_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((id_out_valid == 1'b1) && (id_out_ready == 1'b1)) begin
- if (id_out_stall_queue.size() > 0) begin
- if (id_out_stall_queue[0] == 0) begin
- id_out_ready <= 1'b1;
- end else begin
- id_out_ready <= 1'b0;
- end
- id_out_stall <= id_out_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- id_out_ready <= 1'b1;
- end
- end
- end else begin
- id_out_ready <= 1'b0;
- end
- end
-
- // Handle Output Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((id_out_valid == 1'b1) && (id_out_ready == 1'b1)) begin
- // Check Size
- assert (id_out == id_out_check) else begin
- $error("id_out missmatch! packet %d | recieve: %x != check: %x", packet_num, id_out, id_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("id_out match! packet %d | recieve: %x == check: %x", packet_num, id_out, id_out_check);
-
- // Check Last Flag
- assert (id_out_last == id_out_last_check) else begin
- $error("id_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, id_out_last, id_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("id_out_last match! packet %d | recieve: %x == check: %x", packet_num, id_out_last, id_out_last_check);
-
- // Check Status Value
- assert (status_id == status_id_out_check) else begin
- $error("id_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, status_id, status_id_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("status_id match! packet %d | recieve: %x == check: %x", packet_num, status_id, status_id_out_check);
-
- // Pop new values
- if ((id_out_queue.size() > 0) && (status_id_out_queue.size() > 0) && (id_out_last_queue.size() > 0)) begin
- id_out_check <= id_out_queue.pop_front();
- status_id_out_check <= status_id_out_queue.pop_front();
- id_out_last_check <= id_out_last_queue.pop_front();
- if (id_out_last_check == 1'b1) begin
- packet_num <= packet_num + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [5:0] temp_id_in; // Temporary Input Data Storage
- logic temp_id_in_last; // Temporary Input Data Last
- int temp_id_in_gap; // Temporary Input Gap
-
- logic [5:0] temp_id_out; // Temporary ID Value
- logic [5:0] temp_status_id_out; // Temporary Status ID Value
- logic temp_id_out_last; // Temporary ID last;
- int temp_id_out_stall; // Temporary ID stall;
-
- initial begin
- $dumpfile("sha256_id_buf.vcd");
- $dumpvars(0, tb_sha256_id_buf);
- id_in_drive_en = 0;
- id_out_drive_ready = 0;
-
- // Read input data into Queue in
- fd = $fopen("../stimulus/unit/input_buf_id_stim.csv", "r");
- while ($fscanf (fd, "%d,%b,%d", temp_id_in, temp_id_in_last, temp_id_in_gap) == 3) begin
- id_in_queue.push_back(temp_id_in);
- id_in_last_queue.push_back(temp_id_in_last);
- id_in_gap_queue.push_back(temp_id_in_gap);
- end
- $fclose(fd);
-
- // Read output data into Queue
- fd = $fopen("../stimulus/unit/output_buf_id_ref.csv", "r");
- while ($fscanf (fd, "%d,%b,%d,%d", temp_id_out, temp_id_out_last, temp_status_id_out, temp_id_out_stall) == 4) begin
- id_out_queue.push_back(temp_id_out);
- id_out_last_queue.push_back(temp_id_out_last);
- status_id_out_queue.push_back(temp_status_id_out);
- id_out_stall_queue.push_back(temp_id_out_stall);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- id_out_check = id_out_queue.pop_front();
- status_id_out_check = status_id_out_queue.pop_front();
- id_out_last_check = id_out_last_queue.pop_front();
- id_out_stall = id_out_stall_queue.pop_front();
-
- // Defaultly enable Message Builder
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
-
- // Write some data into the config register
- # 30 id_in_drive_en = 1;
-
- # 30 id_out_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_id_issue.sv b/sha-2-accelerator/hdl/verif/tb_sha256_id_issue.sv
deleted file mode 100644
index dfecfcfaa41376bc0fd547ef67fdfaf03ec5d7a5..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_id_issue.sv
+++ /dev/null
@@ -1,240 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 ID Issuer Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_id_issue.sv"
-
-module tb_sha256_id_issue;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
-
- // Data Out - ID Out
- logic [5:0] id_out;
- logic id_out_last;
-
- // Concatenator Handshake
- logic id_out_cfg_valid;
- logic id_out_cfg_ready;
-
- // ID Buffer Handshake
- logic id_out_buf_valid;
- logic id_out_buf_ready;
-
- sha256_id_issue uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .id_out (id_out),
- .id_out_last (id_out_last),
- .id_out_cfg_valid (id_out_cfg_valid),
- .id_out_cfg_ready (id_out_cfg_ready),
- .id_out_buf_valid (id_out_buf_valid),
- .id_out_buf_ready (id_out_buf_ready)
- );
-
- logic id_out_cfg_drive_ready;
- logic id_out_buf_drive_ready;
-
- logic [511:0] id_out_cfg_queue [$];
- logic id_out_cfg_last_queue [$];
- int id_out_cfg_stall_queue [$];
- logic id_out_cfg_wait_queue;
-
- logic [511:0] id_out_buf_queue [$];
- logic id_out_buf_last_queue [$];
- int id_out_buf_stall_queue [$];
- logic id_out_buf_wait_queue;
-
- logic [5:0] id_out_cfg_check, id_out_buf_check;
- logic id_out_cfg_last_check, id_out_buf_last_check;
- int id_out_cfg_stall, id_out_buf_stall;
-
- int packet_num_cfg, packet_num_buf ;
-
- // Handle Cfg Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (id_out_cfg_drive_ready) begin
- // Count down to zero before enabling Ready
- if (id_out_cfg_stall > 1) begin
- id_out_cfg_stall <= id_out_cfg_stall - 1;
- id_out_cfg_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((id_out_cfg_valid == 1'b1) && (id_out_cfg_ready == 1'b1)) begin
- if (id_out_cfg_stall_queue.size() > 0) begin
- if (id_out_cfg_stall_queue[0] == 0) begin
- id_out_cfg_ready <= 1'b1;
- end else begin
- id_out_cfg_ready <= 1'b0;
- end
- id_out_cfg_stall <= id_out_cfg_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- id_out_cfg_ready <= 1'b1;
- end
- end
- end else begin
- id_out_cfg_ready <= 1'b0;
- end
- end
-
- // Handle Output Cfg Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((id_out_cfg_valid == 1'b1) && (id_out_cfg_ready == 1'b1)) begin
- assert (id_out == id_out_cfg_check) else begin
- $error("id_out_cfg missmatch! packet %d | recieve: %d != check: %d", packet_num_cfg, id_out, id_out_cfg_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("id_out_cfg match! packet %d | recieve: %d == check: %d", packet_num_cfg, id_out, id_out_cfg_check);
- assert (id_out_last == id_out_cfg_last_check) else begin
- $error("id_out_cfg_last missmatch! packet %d | recieve: %d != check: %d", packet_num_cfg, id_out_last, id_out_cfg_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("id_out_cfg_last match! packet %d | recieve: %d != check: %d", packet_num_cfg, id_out_last, id_out_cfg_last_check);
- if ((id_out_cfg_queue.size() > 0) && (id_out_cfg_last_queue.size() > 0)) begin
- id_out_cfg_check <= id_out_cfg_queue.pop_front();
- id_out_cfg_last_check <= id_out_cfg_last_queue.pop_front();
- if (id_out_cfg_last_check == 1'b1) begin
- packet_num_cfg <= packet_num_cfg + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
- end
-
- // Handle buf Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (id_out_buf_drive_ready) begin
- // Count down to zero before enabling Ready
- if (id_out_buf_stall > 1) begin // Want to apply ready of the next clock cycle (stall will be 0 when ready is high)
- id_out_buf_stall <= id_out_buf_stall - 1;
- id_out_buf_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((id_out_buf_valid == 1'b1) && (id_out_buf_ready == 1'b1)) begin
- if (id_out_buf_stall_queue.size() > 0) begin
- if (id_out_buf_stall_queue[0] == 0) begin
- id_out_buf_ready <= 1'b1;
- end else begin
- id_out_buf_ready <= 1'b0;
- end
- id_out_buf_stall <= id_out_buf_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- id_out_buf_ready <= 1'b1;
- end
- end
- end else begin
- id_out_buf_ready <= 1'b0;
- end
- end
-
- // Handle Output buf Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((id_out_buf_valid == 1'b1) && (id_out_buf_ready == 1'b1)) begin
- assert (id_out == id_out_buf_check) else begin
- $error("id_out_buf missmatch! packet %d | recieve: %d != check: %d", packet_num_buf, id_out, id_out_buf_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("id_out_buf match! packet %d | recieve: %d == check: %d", packet_num_buf, id_out, id_out_buf_check);
- assert (id_out_last == id_out_buf_last_check) else begin
- $error("id_out_buf_last missmatch! packet %d | recieve: %d != check: %d", packet_num_buf, id_out_last, id_out_buf_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("id_out_buf_last match! packet %d | recieve: %d == check: %d", packet_num_buf, id_out_last, id_out_buf_last_check);
- if ((id_out_buf_queue.size() > 0) && (id_out_buf_last_queue.size() > 0)) begin
- id_out_buf_check <= id_out_buf_queue.pop_front();
- id_out_buf_last_check <= id_out_buf_last_queue.pop_front();
- if (id_out_buf_last_check == 1'b1) begin
- packet_num_buf <= packet_num_buf + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [5:0] id_cfg_data; // Temporary Output Cfg Data Storage
- logic id_cfg_last; // Temporary Output Cfg Data Last
- int id_cfg_stall; // Temporary Output Cfg Stall
-
- logic [5:0] id_buf_data; // Temporary Output buf Data Storage
- logic id_buf_last; // Temporary Output buf Data Last
- int id_buf_stall; // Temporary Output buf Stall
-
- initial begin
- $dumpfile("sha256_id_issue.vcd");
- $dumpvars(0, tb_sha256_id_issue);
- id_out_cfg_drive_ready = 0;
- id_out_buf_drive_ready = 0;
-
- // Read output cfg data into Queue
- fd = $fopen("../stimulus/unit/output_id_ref.csv", "r");
- while ($fscanf (fd, "%d,%b,%d", id_cfg_data, id_cfg_last, id_cfg_stall) == 3) begin
- id_out_cfg_queue.push_back(id_cfg_data);
- id_out_cfg_last_queue.push_back(id_cfg_last);
- id_out_cfg_stall_queue.push_back(id_cfg_stall);
- end
- $fclose(fd);
-
- // Read output buf data into Queue
- fd = $fopen("../stimulus/unit/output_id_ref.csv", "r");
- while ($fscanf (fd, "%d,%b,%d", id_buf_data, id_buf_last, id_buf_stall) == 3) begin
- id_out_buf_queue.push_back(id_buf_data);
- id_out_buf_last_queue.push_back(id_buf_last);
- id_out_buf_stall_queue.push_back(id_buf_stall);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- id_out_cfg_check = id_out_cfg_queue.pop_front();
- id_out_cfg_last_check = id_out_cfg_last_queue.pop_front();
- id_out_cfg_stall = id_out_cfg_stall_queue.pop_front();
- id_out_buf_check = id_out_buf_queue.pop_front();
- id_out_buf_last_check = id_out_buf_last_queue.pop_front();
- id_out_buf_stall = id_out_buf_stall_queue.pop_front();
-
- // Defaultly enable Message Builder
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
- id_out_cfg_drive_ready = 1;
- id_out_buf_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_id_validator.sv b/sha-2-accelerator/hdl/verif/tb_sha256_id_validator.sv
deleted file mode 100644
index 39e17390369eaf87117eff0bbfbe8855595e3555..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_id_validator.sv
+++ /dev/null
@@ -1,342 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 ID Validator Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_id_validator.sv"
-
-module tb_sha256_id_validator;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
-
- // ID Buffer IN
- logic [5:0] id_in_buf;
- logic id_in_buf_last;
- logic id_in_buf_valid;
- logic id_in_buf_ready;
-
- // Hash IN
- logic [255:0] hash_in;
- logic [5:0] hash_in_id;
- logic hash_in_last;
- logic hash_in_valid;
- logic hash_in_ready;
-
- // Hash Out
- logic [255:0] hash_out;
- logic hash_out_err;
- logic hash_out_last;
- logic hash_out_valid;
- logic hash_out_ready;
-
- // Status Out - Gets updated after every hash
- logic [1:0] status_err;
- logic [9:0] status_packet_count;
- logic status_clear;
-
- sha256_id_validator uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
-
- // ID Buffer IN
- .id_in_buf (id_in_buf),
- .id_in_buf_last (id_in_buf_last),
- .id_in_buf_valid (id_in_buf_valid),
- .id_in_buf_ready (id_in_buf_ready),
-
- // Hash IN
- .hash_in (hash_in),
- .hash_in_id (hash_in_id),
- .hash_in_last (hash_in_last),
- .hash_in_valid (hash_in_valid),
- .hash_in_ready (hash_in_ready),
-
- // Hash Out
- .hash_out (hash_out),
- .hash_out_err (hash_out_err),
- .hash_out_last (hash_out_last),
- .hash_out_valid (hash_out_valid),
- .hash_out_ready (hash_out_ready),
-
- // Status Out - Gets updated after every hash
- .status_err (status_err),
- .status_packet_count (status_packet_count),
- .status_clear (status_clear)
- );
-
- logic id_in_buf_drive_en;
- logic hash_in_drive_en;
-
- logic hash_out_drive_ready;
- // TODO: logic status_out_handle;
- // TODO: Test varying ID Values - not always same ID's
-
- logic [5:0] id_in_buf_queue [$];
- logic id_in_buf_last_queue [$];
- int id_in_buf_gap_queue [$];
- logic id_in_buf_wait_queue;
-
- logic [255:0] hash_in_queue [$];
- logic [5:0] hash_in_id_queue [$];
- logic hash_in_last_queue [$];
- int hash_in_gap_queue [$];
- logic hash_in_wait_queue;
-
- logic [255:0] hash_out_queue [$];
- logic hash_out_err_queue [$];
- logic hash_out_last_queue [$];
- int hash_out_stall_queue [$];
- logic hash_out_wait_queue;
-
- // TODO: Handle Status Checking
-
- // Handle Valid and Data for id_in_buf
- always_ff @(posedge clk, negedge nrst) begin: id_in_buf_valid_drive
- if (!nrst) begin
- id_in_buf <= 512'd0;
- id_in_buf_valid <= 1'b0;
- id_in_buf_last <= 1'b0;
- id_in_buf_gap <= 0;
- id_in_buf_wait_queue <= 1'b1;
- end else if (id_in_buf_drive_en) begin
- if (id_in_buf_gap > 1) begin
- id_in_buf_gap <= id_in_buf_gap - 1;
- id_in_buf_valid <= 1'b0;
- end else begin
- id_in_buf_valid <= 1'b1;
- end
- if (((id_in_buf_valid == 1'b1) && (id_in_buf_ready == 1'b1)) ||
- (id_in_buf_wait_queue == 1'b1)) begin
- // Data transfer just completed or transfers already up to date
- if ((id_in_buf_queue.size() > 0) && (id_in_buf_last_queue.size() > 0) && (id_in_buf_gap_queue.size() > 0)) begin
- id_in_buf <= id_in_buf_queue.pop_front();
- id_in_buf_last <= id_in_buf_last_queue.pop_front();
- if (id_in_buf_gap_queue[0] == 0) begin
- id_in_buf_valid <= 1'b1;
- end else begin
- id_in_buf_valid <= 1'b0;
- end
- id_in_buf_gap <= id_in_buf_gap_queue.pop_front();
- id_in_buf_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- id_in_buf_wait_queue <= 1'b1;
- id_in_buf_valid <= 1'b0;
- end
- end
- end
- end
-
- // Handle Valid and Data for hash_in
- always_ff @(posedge clk, negedge nrst) begin: hash_in_valid_drive
- if (!nrst) begin
- hash_in <= 256'd0;
- hash_in_id <= 6'd0;
- hash_in_valid <= 1'b0;
- hash_in_last <= 1'b0;
- hash_in_gap <= 0;
- hash_in_wait_queue <= 1'b1;
- end else if (hash_in_drive_en) begin
- if (hash_in_gap > 1) begin
- hash_in_gap <= hash_in_gap -1;
- hash_in_valid <= 1'b0;
- end else begin
- hash_in_valid <= 1'b1;
- end
- if (((hash_in_valid == 1'b1) && (hash_in_ready == 1'b1)) ||
- (hash_in_wait_queue == 1'b1)) begin
- // hash_in transfer just completed or transfers already up to date
- if ((hash_in_queue.size() > 0) && (hash_in_id_queue.size() > 0 ) && (hash_in_last_queue.size() > 0) && (hash_in_gap_queue.size() > 0)) begin
- hash_in <= hash_in_queue.pop_front();
- hash_in_id <= hash_in_id_queue.pop_front();
- hash_in_last <= hash_in_last_queue.pop_front();
- if (hash_in_gap_queue[0] == 0) begin
- hash_in_valid <= 1'b1;
- end else begin
- hash_in_valid <= 1'b0;
- end
- hash_in_gap <= hash_in_gap_queue.pop_front();
- hash_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- hash_in_wait_queue <= 1'b1;
- hash_in_valid <= 1'b0;
- end
- end
- end
- end
-
- logic [255:0] hash_out_check;
- logic hash_out_err_check;
- logic hash_out_last_check;
-
- int id_in_buf_gap;
- int hash_in_gap;
- int hash_out_stall;
-
- int packet_num;
-
- // Handle Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (hash_out_drive_ready) begin
- // Count down to zero before enabling Ready
- if (hash_out_stall > 1) begin
- hash_out_stall <= hash_out_stall - 1;
- hash_out_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((hash_out_valid == 1'b1) && (hash_out_ready == 1'b1)) begin
- if (hash_out_stall_queue.size() > 0) begin
- if (hash_out_stall_queue[0] == 0) begin
- hash_out_ready <= 1'b1;
- end else begin
- hash_out_ready <= 1'b0;
- end
- hash_out_stall <= hash_out_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- hash_out_ready <= 1'b1;
- end
- end
- end else begin
- hash_out_ready <= 1'b0;
- end
- end
-
- // Handle Output Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((hash_out_valid == 1'b1) && (hash_out_ready == 1'b1)) begin
- // Check Size
- assert (hash_out == hash_out_check) else begin
- $error("hash_out missmatch! packet %d | recieve: %x != check: %x", packet_num, hash_out, hash_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("hash_out match! packet %d | recieve: %x == check: %x", packet_num, hash_out, hash_out_check);
-
- // Check ID
- assert (hash_out_err == hash_out_err_check) else begin
- $error("hash_out_err missmatch! packet %d | recieve: %b != check: %b", packet_num, hash_out_err, hash_out_err_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("hash_out_err match! packet %d | recieve: %b == check: %b", packet_num, hash_out_err, hash_out_err_check);
-
- // Check Last Flag
- assert (hash_out_last == hash_out_last_check) else begin
- $error("hash_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, hash_out_last, hash_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("hash_out_last match! packet %d | recieve: %x == check: %x", packet_num, hash_out_last, hash_out_last_check);
-
- // Pop new values
- if ((hash_out_queue.size() > 0) && (hash_out_err_queue.size() > 0) && (hash_out_last_queue.size() > 0)) begin
- hash_out_check <= hash_out_queue.pop_front();
- hash_out_err_check <= hash_out_err_queue.pop_front();
- hash_out_last_check <= hash_out_last_queue.pop_front();
- if (hash_out_last_check == 1'b1) begin
- packet_num <= packet_num + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [5:0] temp_id_in_buf; // Temporary Input Data Storage
- logic temp_id_in_buf_last; // Temporary Input Data Last
- int temp_id_in_buf_gap; // Temporary Input Gap
-
- logic [255:0] temp_hash_in; // Temporary Hash Value
- logic [5:0] temp_hash_in_id; // Temporary Hash ID
- logic temp_hash_in_last; // Temporary Hash last;
- int temp_hash_in_gap; // Temporary Hash gap;
-
- logic [255:0] temp_hash_out; // Temporary Hash Value
- logic temp_hash_out_err; // Temporary Hash Error
- logic temp_hash_out_last; // Temporary Hash last;
- int temp_hash_out_stall; // Temporary Hash stall;
-
- initial begin
- $dumpfile("sha256_id_validator.vcd");
- $dumpvars(0, tb_sha256_id_validator);
- id_in_buf_drive_en = 0;
- hash_in_drive_en = 0;
- hash_out_drive_ready = 0;
-
- // Read input data into Queuein
- fd = $fopen("../stimulus/unit/input_validator_id_stim.csv", "r");
- while ($fscanf (fd, "%d,%b,%d", temp_id_in_buf, temp_id_in_buf_last, temp_id_in_buf_gap) == 3) begin
- id_in_buf_queue.push_back(temp_id_in_buf);
- id_in_buf_last_queue.push_back(temp_id_in_buf_last);
- id_in_buf_gap_queue.push_back(temp_id_in_buf_gap);
- end
- $fclose(fd);
-
- // Read input cfg into Queue
- fd = $fopen("../stimulus/unit/input_hash_in_stim.csv", "r");
- while ($fscanf (fd, "%x,%d,%b,%d", temp_hash_in, temp_hash_in_id, temp_hash_in_last, temp_hash_in_gap) == 4) begin
- hash_in_queue.push_back(temp_hash_in);
- hash_in_id_queue.push_back(temp_hash_in_id);
- hash_in_last_queue.push_back(temp_hash_in_last);
- hash_in_gap_queue.push_back(temp_hash_in_gap);
- end
- $fclose(fd);
-
- // Read output data into Queue
- fd = $fopen("../stimulus/unit/output_hash_out_ref.csv", "r");
- while ($fscanf (fd, "%x,%b,%b,%d", temp_hash_out, temp_hash_out_err, temp_hash_out_last, temp_hash_out_stall) == 4) begin
- hash_out_queue.push_back(temp_hash_out);
- hash_out_err_queue.push_back(temp_hash_out_err);
- hash_out_last_queue.push_back(temp_hash_out_last);
- hash_out_stall_queue.push_back(temp_hash_out_stall);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- hash_out_check = hash_out_queue.pop_front();
- hash_out_err_check = hash_out_err_queue.pop_front();
- hash_out_last_check = hash_out_last_queue.pop_front();
- hash_out_stall = hash_out_stall_queue.pop_front();
-
- // Defaultly enable Message Builder
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
- #20 hash_in_drive_en = 1;
-
- // Write some data into the config register
- # 30 id_in_buf_drive_en = 1;
-
- # 30 hash_out_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/hdl/verif/tb_sha256_message_build.sv b/sha-2-accelerator/hdl/verif/tb_sha256_message_build.sv
deleted file mode 100644
index b6d66c2d180fadd723e00f2821c63217ed137f35..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/hdl/verif/tb_sha256_message_build.sv
+++ /dev/null
@@ -1,325 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic SHA-2 Message Builder Testbench
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2022, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`timescale 1ns/1ns
-`include "sha256_message_build.sv"
-
-module tb_sha256_message_build;
-
- logic clk;
- logic nrst;
- logic en;
- logic sync_rst;
- // Data In data and Handshaking
- logic [511:0] data_in;
- logic data_in_last;
- logic data_in_valid;
- logic data_in_ready;
-
- // Config data and Handshaking
- logic [63:0] cfg_size;
- logic [1:0] cfg_scheme;
- logic [5:0] cfg_id;
- logic cfg_last;
- logic cfg_valid;
- logic cfg_ready;
-
- // Data Out data and Handshaking
- logic [511:0] data_out;
- logic [5:0] data_out_id;
- logic data_out_valid;
- logic data_out_ready;
- logic data_out_last;
-
- sha256_message_build uut (
- .clk (clk),
- .nrst (nrst),
- .en (en),
- .sync_rst (sync_rst),
- .data_in (data_in),
- .data_in_valid (data_in_valid),
- .data_in_ready (data_in_ready),
- .data_in_last (data_in_last),
- .cfg_size (cfg_size),
- .cfg_scheme (cfg_scheme),
- .cfg_id (cfg_id),
- .cfg_last (cfg_last),
- .cfg_valid (cfg_valid),
- .cfg_ready (cfg_ready),
- .data_out (data_out),
- .data_out_id (data_out_id),
- .data_out_last (data_out_last),
- .data_out_valid (data_out_valid),
- .data_out_ready (data_out_ready));
-
- logic data_in_drive_en;
- logic cfg_drive_en;
- logic data_out_drive_ready;
-
- logic [511:0] data_in_queue [$];
- logic data_in_last_queue [$];
- int data_in_gap_queue [$];
- logic data_in_wait_queue;
-
- logic [63:0] cfg_size_queue [$];
- logic [1:0] cfg_scheme_queue [$];
- logic [5:0] cfg_id_queue [$];
- logic cfg_last_queue [$];
- int cfg_gap_queue [$];
- logic cfg_wait_queue;
-
- logic [511:0] data_out_queue [$];
- logic [5:0] data_out_id_queue [$];
- logic data_out_last_queue [$];
- int data_out_stall_queue [$];
- logic data_out_wait_queue;
-
- // Handle Valid and Data for data_in
- always_ff @(posedge clk, negedge nrst) begin: data_in_valid_drive
- if (!nrst) begin
- data_in <= 512'd0;
- data_in_valid <= 1'b0;
- data_in_last <= 1'b0;
- data_in_gap <= 0;
- data_in_wait_queue <= 1'b1;
- end else if (data_in_drive_en) begin
- if (data_in_gap > 1) begin
- data_in_gap <= data_in_gap -1;
- data_in_valid <= 1'b0;
- end else begin
- data_in_valid <= 1'b1;
- end
- if (((data_in_valid == 1'b1) && (data_in_ready == 1'b1)) ||
- (data_in_wait_queue == 1'b1)) begin
- // Data transfer just completed or transfers already up to date
- if ((data_in_queue.size() > 0) && (data_in_last_queue.size() > 0) && (data_in_gap_queue.size() > 0)) begin
- data_in <= data_in_queue.pop_front();
- data_in_last <= data_in_last_queue.pop_front();
- if (data_in_gap_queue[0] == 0) begin
- data_in_valid <= 1'b1;
- end else begin
- data_in_valid <= 1'b0;
- end
- data_in_gap <= data_in_gap_queue.pop_front();
- data_in_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- data_in_wait_queue <= 1'b1;
- data_in_valid <= 1'b0;
- end
- end
- end
- end
-
- // Handle Valid and Data for cfg
- always_ff @(posedge clk, negedge nrst) begin: cfg_valid_drive
- if (!nrst) begin
- cfg_size <= 64'd0;
- cfg_scheme <= 2'd0;
- cfg_id <= 6'd0;
- cfg_valid <= 1'b0;
- cfg_last <= 1'b0;
- cfg_gap <= 0;
- cfg_wait_queue <= 1'b1;
- end else if (cfg_drive_en) begin
- if (cfg_gap > 1) begin
- cfg_gap <= cfg_gap -1;
- cfg_valid <= 1'b0;
- end else begin
- cfg_valid <= 1'b1;
- end
- if (((cfg_valid == 1'b1) && (cfg_ready == 1'b1)) ||
- (cfg_wait_queue == 1'b1)) begin
- // cfg transfer just completed or transfers already up to date
- if ((cfg_size_queue.size() > 0) && (cfg_scheme_queue.size() > 0) && (cfg_id_queue.size() > 0) && (cfg_last_queue.size() > 0) && (cfg_gap_queue.size() > 0)) begin
- cfg_size <= cfg_size_queue.pop_front();
- cfg_scheme <= cfg_scheme_queue.pop_front();
- cfg_id <= cfg_id_queue.pop_front();
- cfg_last <= cfg_last_queue.pop_front();
- if (cfg_gap_queue[0] == 0) begin
- cfg_valid <= 1'b1;
- end else begin
- cfg_valid <= 1'b0;
- end
- cfg_gap <= cfg_gap_queue.pop_front();
- cfg_wait_queue <= 1'b0;
- end else begin
- // No data currently avaiable in queue to write but transfers up to date
- cfg_wait_queue <= 1'b1;
- cfg_valid <= 1'b0;
- end
- end
- end
- end
-
- logic [511:0] data_out_check;
- logic [5:0] data_out_id_check;
- logic data_out_last_check;
-
- int data_in_gap;
- int cfg_gap;
-
- int data_out_stall;
-
- int packet_num;
-
- // Handle Output Ready Signal Verification
- always @(posedge clk) begin
- // Check Override Control on Ready
- if (data_out_drive_ready) begin
- // Count down to zero before enabling Ready
- if (data_out_stall > 1) begin
- data_out_stall <= data_out_stall - 1;
- data_out_ready <= 1'b0;
- end else begin
- // Wait for handshake before updating stall value
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- if (data_out_stall_queue.size() > 0) begin
- if (data_out_stall_queue[0] == 0) begin
- data_out_ready <= 1'b1;
- end else begin
- data_out_ready <= 1'b0;
- end
- data_out_stall <= data_out_stall_queue.pop_front();
- end
- // Keep Ready Asserted until handshake seen
- end else begin
- data_out_ready <= 1'b1;
- end
- end
- end else begin
- data_out_ready <= 1'b0;
- end
- end
-
- // Handle Output Data Verification
- always @(posedge clk) begin
- // Check Data on Handshake
- if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
- // Check Data Out Data
- assert (data_out == data_out_check) else begin
- $error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out match! packet %d | recieve: %x == check: %x", packet_num, data_out, data_out_check);
-
- // Check Data Out ID
- assert (data_out_id == data_out_id_check) else begin
- $error("data_out_id missmatch! packet %d | recieve: %d != check: %d", packet_num, data_out_id, data_out_id_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out_id match! packet %d | recieve: %d == check: %d", packet_num, data_out_id, data_out_id_check);
-
- // Check Data Out Last
- assert (data_out_last == data_out_last_check) else begin
- $error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
- $finish;
- end
- if ($test$plusargs ("DEBUG")) $display("data_out_last match! packet %d | recieve: %x == check: %x", packet_num, data_out_last, data_out_last_check);
- if ((data_out_queue.size() > 0) && (data_out_id_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
- data_out_check <= data_out_queue.pop_front();
- data_out_id_check <= data_out_id_queue.pop_front();
- data_out_last_check <= data_out_last_queue.pop_front();
- if (data_out_last_check == 1'b1) begin
- packet_num <= packet_num + 1;
- end
- end else begin
- $display("Test Passes");
- $finish;
- end
- end
- end
-
- // File Reading Variables
- int fd; // File descriptor Handle
-
- logic [511:0] temp_data_in; // Temporary Input Data Storage
- logic temp_data_in_last; // Temporary Input Data Last
- int temp_data_in_gap; // Temporary Input Gap
-
- logic [63:0] temp_cfg_in_size; // Temporary cfg size
- logic [1:0] temp_cfg_in_scheme; // Temporary cfg scheme
- logic [5:0] temp_cfg_in_id; // Temporary cfg ID
- logic temp_cfg_in_last; // Temporary cfg last;
- int temp_cfg_in_gap; // Temporary cfg gap;
-
- logic [511:0] temp_data_out; // Temporary Output Data Storage
- logic [5:0] temp_data_out_id; // Temporary Output Data ID
- logic temp_data_out_last; // Temporary Output Data Last
- int temp_data_out_stall; // Temporary Output Stall
-
- initial begin
- $dumpfile("sha256_message_build.vcd");
- $dumpvars(0, tb_sha256_message_build);
- data_in_drive_en = 0;
- cfg_drive_en = 0;
- data_out_drive_ready = 0;
-
- // Read input data into Queue
- fd = $fopen("../stimulus/unit/input_data_stim.csv", "r");
- while ($fscanf (fd, "%x,%b,%d", temp_data_in, temp_data_in_last, temp_data_in_gap) == 3) begin
- data_in_queue.push_back(temp_data_in);
- data_in_last_queue.push_back(temp_data_in_last);
- data_in_gap_queue.push_back(temp_data_in_gap);
- end
- $fclose(fd);
-
- // Read input cfg into Queue
- fd = $fopen("../stimulus/unit/input_cfg_sync_stim.csv", "r");
- while ($fscanf (fd, "%x,%x,%d,%b,%d", temp_cfg_in_size, temp_cfg_in_scheme, temp_cfg_in_id, temp_cfg_in_last, temp_cfg_in_gap) == 5) begin
- cfg_size_queue.push_back(temp_cfg_in_size);
- cfg_scheme_queue.push_back(temp_cfg_in_scheme);
- cfg_id_queue.push_back(temp_cfg_in_id);
- cfg_last_queue.push_back(temp_cfg_in_last);
- cfg_gap_queue.push_back(temp_cfg_in_gap);
- end
- $fclose(fd);
-
- // Read output data into Queue
- fd = $fopen("../stimulus/unit/output_message_block_ref.csv", "r");
- while ($fscanf (fd, "%x,%d,%b,%d", temp_data_out, temp_data_out_id, temp_data_out_last, temp_data_out_stall) == 4) begin
- data_out_queue.push_back(temp_data_out);
- data_out_id_queue.push_back(temp_data_out_id);
- data_out_last_queue.push_back(temp_data_out_last);
- data_out_stall_queue.push_back(temp_data_out_stall);
- end
- $fclose(fd);
-
- // Initialise First Checking Values
- data_out_check = data_out_queue.pop_front();
- data_out_id_check = data_out_id_queue.pop_front();
- data_out_last_check = data_out_last_queue.pop_front();
- data_out_stall = data_out_stall_queue.pop_front();
-
- // Defaultly enable Message Builder
- en = 1;
-
- // Defaultly set Sync Reset Low
- sync_rst = 0;
-
- #20 nrst = 1;
- #20 nrst = 0;
- #20 nrst = 1;
- #20 data_in_drive_en = 1;
-
- // Write some data into the config register
- # 30 cfg_drive_en = 1;
-
- # 30 data_out_drive_ready = 1;
- end
-
- initial begin
- forever begin
- #10 clk = 0;
- #10 clk = 1;
- end
- end
-
-endmodule
\ No newline at end of file
diff --git a/sha-2-accelerator/model/py/hash_model.py b/sha-2-accelerator/model/py/hash_model.py
deleted file mode 100644
index 20087d6a2f443016fc1fb6c2405f9cfb78f618cc..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/model/py/hash_model.py
+++ /dev/null
@@ -1,393 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs Basic SHA-2 Hashing Model Python Reference
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-import os, random, math, csv
-import binascii
-import hashlib
-
-def main():
- # Check Environment Variables set
- if not "SHA_2_ACC_DIR" in os.environ:
- print("Sourceme file at root of repository has not been sourced. Please source this file and try again.")
- quit()
- # Read in Descriptor File
- # - contains number of payloads of data to generate and random seed
- stim_file = os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/model/" + "model_stim.csv"
- with open(stim_file, "r") as stim:
- csvreader = csv.reader(stim, delimiter=",")
- stim_list = list(csvreader)
-
- seed = int(stim_list[0][0])
- payloads = int(stim_list[0][1])
- payload_size_bits = int(stim_list[0][2])
- gap_limit = int(stim_list[0][3])
- stall_limit = int(stim_list[0][4])
- random.seed(seed)
-
- print(f"Generating {payloads} payloads using seed: {seed}")
- in_cfg_words_list = []
- in_cfg_words_gap_list = []
- sync_cfg_size_list = []
- sync_cfg_id_list = []
- sync_cfg_stall_list = []
- in_data_words_list = []
- in_data_words_last_list = []
- in_data_words_gap_list = []
- message_block_list = []
- message_block_id_list = []
- message_block_last_list = []
- message_block_gap_list = []
- message_block_stall_list = []
-
- # Hash Output List Initialisation
- hash_val = 0
- hash_list = []
- hash_id_list = []
- hash_gap_list = []
- hash_stall_list = []
- hash_err_list = []
-
- # ID Lists
- id_gap_list = []
- expected_id_list = []
- expected_id_stall_list = []
- id_buf_id_list = []
-
- id_value = 0
- id_validator_buf_value = 0
- id_validator_hash_value = 0
- id_validator_buf_no_wrap_value = 0
- id_validator_hash_no_wrap_value = 0
-
- id_validator_buf_list = []
- id_validator_hash_list = []
- id_validator_buf_no_wrap_list = []
- id_validator_hash_no_wrap_list = []
- id_validator_hash_stall_list = []
- val_hash_list = []
-
- prev_payload_hash_err = False
-
- for i in range(payloads):
- # Generate Gapping and Stalling Values
- # Gapping - Period to wait before taking Input Valid High
- # Stalling - Period to wait before taking Output Read High
- if gap_limit > 0:
- id_gap_list.append(random.randrange(0,gap_limit))
- in_cfg_words_gap_list.append(random.randrange(0,gap_limit))
- hash_gap_list.append(random.randrange(0,gap_limit))
- else:
- id_gap_list.append(0)
- in_cfg_words_gap_list.append(0)
-
- if stall_limit > 0:
- hash_stall_list.append(random.randrange(0,stall_limit))
- sync_cfg_stall_list.append(random.randrange(0,stall_limit))
- else:
- hash_stall_list.append(0)
- sync_cfg_stall_list.append(0)
-
- # Generate expected output in 512 bit chunks
- if payload_size_bits == 0:
- cfg_size = math.ceil(random.randint(0,pow(2,14))/8)*8
- else:
- cfg_size = payload_size_bits
- cfg_size_bin = "{0:b}".format(cfg_size)
- # Pad Size to 64 bits
- cfg_size_str = "0"*(64-len(cfg_size_bin)) + str(cfg_size_bin)
-
- # Generate Random Data using Size
- data = "{0:b}".format(random.getrandbits(cfg_size))
- data = "0"*(cfg_size - len(data)) + data # Pad Data to length of config (Python like to concatenate values)
-
- if stall_limit > 0:
- id_stall_value = random.randrange(0,stall_limit)
- else:
- id_stall_value = 0
-
- expected_id_list.append(id_value)
- sync_cfg_id_list.append(id_value)
- hash_id_list.append(id_value)
- old_id_value = id_value
- id_validator_buf_list.append(id_validator_buf_value)
- id_validator_hash_list.append(id_validator_hash_value)
- id_validator_buf_no_wrap_list.append(id_validator_buf_no_wrap_value)
- id_validator_hash_no_wrap_list.append(id_validator_hash_no_wrap_value)
-
- # Reference Values
- id_value += 1
-
- if id_value >= 64:
- id_value = id_value - 64
-
- expected_id_stall_list.append(id_stall_value)
-
- id_buf_id_list.append(random.randrange(0,63))
-
-
- chunked_data_words = chunkstring(str(data),512)
- in_data_words = chunked_data_words.copy()
- in_data_words[-1] = in_data_words[-1] + "0"*(512-len(in_data_words[-1]))
- in_data_words_last = []
- in_data_words_gap = []
- message_block = chunked_data_words.copy()
- message_block_id = []
- message_block_last = []
- message_block_stall = []
- message_block_gap = []
- last_len = len(chunked_data_words[-1])
- # print(f"{chunked_data_words[-1]} {last_len}")
- if (last_len == 512):
- message_block.append("1" + "0"*447 + cfg_size_str)
- else:
- message_block[-1] = message_block[-1] + "1"
- if last_len > 447: # Size can't fit in last word
- # Pad last word to 512 bits
- message_block[-1] = message_block[-1] + "0"*(512 - len(message_block[-1]))
- # Create New word with Size at the end
- message_block.append("0"*448 + cfg_size_str)
- else:
- message_block[-1] = message_block[-1] + "0"*(512 - 64- len(message_block[-1])) + cfg_size_str
-
- for i in range(len(in_data_words)):
- in_data_words_last.append("0")
- if gap_limit > 0:
- in_data_words_gap.append(random.randrange(0,gap_limit))
- else:
- in_data_words_gap.append(0)
- in_data_words_last[-1] = "1"
-
- for i in range(len(message_block)):
- message_block_last.append("0")
- message_block_id.append(old_id_value)
- if stall_limit > 0:
- message_block_stall.append(random.randrange(0,stall_limit))
- else:
- message_block_stall.append(0)
- if gap_limit > 0:
- message_block_gap.append(random.randrange(0,gap_limit))
- else:
- message_block_gap.append(0)
- message_block_last[-1] = "1"
-
- in_cfg_words_list.append(cfg_size_str)
- sync_cfg_size_list.append(cfg_size_str)
- in_data_words_list += in_data_words
- in_data_words_last_list += in_data_words_last
- in_data_words_gap_list += in_data_words_gap
- message_block_list += message_block
- message_block_id_list += message_block_id
- message_block_last_list += message_block_last
- message_block_gap_list += message_block_gap
- message_block_stall_list += message_block_stall
- intval = int(data, 2)
- old_hash_val = hash_val
- h=int(data, 2).to_bytes((len(data) + 7) // 8, byteorder='big')
- hash_val = binascii.hexlify(hashlib.sha256(h).digest()).decode()
- hash_list.append(hash_val)
-
- # while (id_validator_buf_value != id_validator_hash_value):
- # print(f"{id_validator_buf_value}, {id_validator_hash_value}")
- # hash_err_list.append("1")
- # if id_validator_buf_value > id_validator_hash_value:
- # # Pop another hash
- # # - Hash ID increases by 1 while buf ID stays the same
- # id_validator_hash_value += 1
- # id_validator_hash_list.append(id_validator_hash_value)
- # hash_gap_list.append(hash_gap_list[-1])
- # else:
- # # Pop another ID Buf ID
- # # - ID increases by extra 1 BUT hash remains the same
- # id_validator_buf_value += 1
- # val_hash_list.append(hash_val)
- # hash_stall_list.append(hash_stall_list[-1])
- # id_validator_buf_list.append(id_validator_buf_value)
- # id_gap_list.append(id_gap_list[-1])
- # print(f"{id_validator_buf_value}, {id_validator_hash_value}")
- # hash_err_list.append("0")
- id_validator_buf_value += 1
- id_validator_hash_value += 1
- id_validator_buf_no_wrap_value += 1
- id_validator_hash_no_wrap_value += 1
- # val_hash_list.append(hash_val)
-
- if random.randrange(0,100) < 20:
- id_validator_buf_value += 1
- id_validator_buf_no_wrap_value += 1
-
- if random.randrange(0,100) < 20:
- id_validator_hash_value += 1
- id_validator_hash_no_wrap_value += 1
-
- if id_validator_buf_value >= 64:
- id_validator_buf_value = id_validator_buf_value - 64
-
- if id_validator_hash_value >= 64:
- id_validator_hash_value = id_validator_hash_value - 64
-
- # Generate val_hash_list
- id_validator_buf_offset = 0
- id_validator_hash_offset = 0
- for idx, hash in enumerate(hash_list):
- if id_validator_buf_no_wrap_list[idx + id_validator_buf_offset] == id_validator_hash_no_wrap_list[idx + id_validator_hash_offset]:
- hash_err_list.append("0")
- val_hash_list.append(hash_list[idx + id_validator_hash_offset])
- else:
- if id_validator_buf_no_wrap_list[idx + id_validator_buf_offset] > id_validator_hash_no_wrap_list[idx + id_validator_hash_offset]:
- # Pop another hash
- # - Hash ID increases by 1 while buf ID stays the same
- hash_err_list.append("1")
- val_hash_list.append(hash_list[idx + id_validator_hash_offset])
- id_validator_buf_offset -= 1
- else:
- # Pop another ID Buf ID
- # - ID increases by extra 1 BUT hash remains the same
- hash_err_list.append("1")
- val_hash_list.append(hash_list[idx + id_validator_hash_offset])
- id_validator_hash_offset -= 1
-
- # Write out Input ID Seed to Text File
- input_header = ["id_value", "last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_id_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(expected_id_list):
- writer.writerow([expected_id_list[idx], "1", id_gap_list[idx]])
-
- # Write out Buffer Input ID to Text File
- input_header = ["id_value", "last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_buf_id_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(id_buf_id_list):
- writer.writerow([id_buf_id_list[idx], "1", id_gap_list[idx]])
-
- # Write out Input Validator ID Seed to Text File
- input_header = ["id_value", "last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_validator_id_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(id_validator_buf_list):
- writer.writerow([id_validator_buf_list[idx], "1", id_gap_list[idx]])
-
- # Write out Output ID Values to Text File
- input_header = ["expected_id_value, id_last, stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_id_ref.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(expected_id_list):
- writer.writerow([word, "1", expected_id_stall_list[idx]])
-
- # Write out Output ID Values to Text File
- input_header = ["expected_id_value, id_last, status_id, stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_buf_id_ref.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(id_buf_id_list):
- writer.writerow([word, "1", word, expected_id_stall_list[idx]])
-
- # Write out Input Data Stimulus to Text File
- input_header = ["input_data", "input_data_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_data_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(in_data_words_list):
- writer.writerow(["{0:x}".format(int(word, 2)), in_data_words_last_list[idx], in_data_words_gap_list[idx]])
-
- # Write out Input Data 32bit AHB Stimulus to Text File
- input_header = ["input_data_32word", "input_data_32word_last", "input_data_last"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "input_data_32bit_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(in_data_words_list):
- sub_word_count = 0
- while sub_word_count < 16:
- sub_word = int(word, 2) >> (32 * (sub_word_count)) & 0xFFFF_FFFF
- sub_word_last = 0
- if sub_word_count == 15:
- sub_word_last = 1
- writer.writerow(["{0:x}".format(sub_word), sub_word_last, in_data_words_last_list[idx]])
- sub_word_count += 1
-
- # Write out Cfg Stimulus to Text File
- input_header = ["input_cfg_size", "input_cfg_scheme", "input_cfg_last"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_cfg_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(in_cfg_words_list):
- writer.writerow(["{0:x}".format(int(word, 2)), "0", "1", in_cfg_words_gap_list[idx]])
-
- # Write out Cfg Stimulus to Text File
- input_header = ["input_cfg_size", "input_cfg_scheme", "input_cfg_id", "input_cfg_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_cfg_sync_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(in_cfg_words_list):
- writer.writerow(["{0:x}".format(int(word, 2)), "0", expected_id_list[idx] ,"1", in_cfg_words_gap_list[idx]])
-
- # Write out Cfg sync reference to Text File
- input_header = ["output_cfg_size", "output_cfg_scheme", "output_cfg_id", "output_cfg_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_cfg_sync_ref.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(sync_cfg_size_list):
- writer.writerow(["{0:x}".format(int(word, 2)), "0", sync_cfg_id_list[idx], "1", sync_cfg_stall_list[idx]])
-
- # Write out Expected output to text file
- output_header = ["output_data", "output_data_id", "output_data_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_message_block_ref.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(message_block_list):
- writer.writerow(["{0:x}".format(int(word, 2)), message_block_id_list[idx], message_block_last_list[idx], message_block_stall_list[idx]])
-
- # Write out Message Block (Input) to text file
- output_header = ["message_block_data", "message_block_id", "message_block_data_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_message_block_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(message_block_list):
- writer.writerow(["{0:x}".format(int(word, 2)), message_block_id_list[idx], message_block_last_list[idx], message_block_gap_list[idx]])
-
- # Write out hash value to text file
- output_header = ["output_data", "output_id", "output_data_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_hash_ref.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(hash_list):
- writer.writerow([word, expected_id_list[idx], "1", hash_stall_list[idx]])
-
- # Write out hash value to text file
- output_header = ["output_data", "output_sub_word_last", "output_data_last"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/system/" + "output_hash_32bit_ref.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(hash_list):
- sub_word_count = 0
- while sub_word_count < 8:
- sub_word = int(word, 16) >> (32 * sub_word_count) & 0xFFFF_FFFF
- sub_word_last = 0
- if sub_word_count == 7:
- sub_word_last = 1
- writer.writerow(["{0:x}".format(sub_word), sub_word_last, "1"])
- sub_word_count += 1
-
- # Write out Validator Hash Input to text file
- output_header = ["hash_in", "hash_in_id", "hash_last", "gap_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "input_hash_in_stim.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(hash_list):
- writer.writerow([word, id_validator_hash_list[idx], "1", hash_gap_list[idx]])
-
- # Write out hash out (include error) value to text file
- output_header = ["hash", "hash_err", "hash_last", "stall_value"]
- with open(os.environ["SHA_2_ACC_DIR"] + "/simulate/stimulus/unit/" + "output_hash_out_ref.csv", "w", encoding="UTF8", newline='') as f:
- writer = csv.writer(f)
- for idx, word in enumerate(val_hash_list):
- writer.writerow([word, hash_err_list[idx], "1", hash_stall_list[idx]])
-
-
-
-def chunkstring(string, length):
- array_len = math.ceil(len(string)/length)
- array = []
- for i in range(array_len):
- array.append(string[i*length:i*length + length])
- return array
-
-if __name__ == "__main__":
- main()
diff --git a/sha-2-accelerator/simulate/.DS_Store b/sha-2-accelerator/simulate/.DS_Store
deleted file mode 100644
index a3ba0506f91bf270f44efbde52d7826d3cc52172..0000000000000000000000000000000000000000
Binary files a/sha-2-accelerator/simulate/.DS_Store and /dev/null differ
diff --git a/sha-2-accelerator/simulate/sim/.DS_Store b/sha-2-accelerator/simulate/sim/.DS_Store
deleted file mode 100644
index 9fdb14b4b0f5892a63e2bbe07d8809e48be05fec..0000000000000000000000000000000000000000
Binary files a/sha-2-accelerator/simulate/sim/.DS_Store and /dev/null differ
diff --git a/sha-2-accelerator/simulate/stimulus/README.md b/sha-2-accelerator/simulate/stimulus/README.md
deleted file mode 100644
index 0215fcf496b4b86b9a1d9a0e46e882d357b8d344..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/README.md
+++ /dev/null
@@ -1,7 +0,0 @@
-The csv files in this directory are used for verifcation of systemverilog modules.
-
-The model directory contains a hand written stimulus to be used by python models to generate the testbench stimulus.
-The first value is the random seed followed by the number of packets:
- seed,packets
-
-The testbench directory contains stimulus for the SV testbenches. Input stimulus is fed into the testbench to drive the design and the output is used to verify the outputs of the design.
\ No newline at end of file
diff --git a/sha-2-accelerator/simulate/stimulus/model/model_stim.csv b/sha-2-accelerator/simulate/stimulus/model/model_stim.csv
deleted file mode 100644
index 3ad8ed8b7612f2b9ad71807903cef756c83755e7..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/model/model_stim.csv
+++ /dev/null
@@ -1 +0,0 @@
-4048473887,10,512,3,3
\ No newline at end of file
diff --git a/sha-2-accelerator/simulate/stimulus/system/input_data_32bit_stim.csv b/sha-2-accelerator/simulate/stimulus/system/input_data_32bit_stim.csv
deleted file mode 100644
index 78ad4d0f34d72ba649b0185eb545e848ea8033cb..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/system/input_data_32bit_stim.csv
+++ /dev/null
@@ -1,160 +0,0 @@
-94748770,0,1
-e3109cc ,0,1
-c4411b41,0,1
-5349fe99,0,1
-bc3bdfc1,0,1
-deb5cb2a,0,1
-a0052ca2,0,1
-1761b000,0,1
-1b5affff,0,1
-eab53b7e,0,1
-81152f06,0,1
-7d60ab33,0,1
-1ce3c906,0,1
-707476fe,0,1
-923737f4,0,1
-695b2443,1,1
-f7079da3,0,1
-a0c46731,0,1
-c51f9e09,0,1
-8d8993e6,0,1
-fd33039d,0,1
-e8675d4a,0,1
-c0e513a1,0,1
-858c0663,0,1
-a1fb693e,0,1
-d5ebd6d4,0,1
-26f7441f,0,1
-907554b5,0,1
-9db705fd,0,1
-47a57bf5,0,1
-fe2518c8,0,1
-4c5b82c1,1,1
-28b3253a,0,1
-96dbf9e5,0,1
-55e5ab02,0,1
-6bbbc74a,0,1
-ed5fbca6,0,1
-73ece6c4,0,1
-832fa959,0,1
-7a0d31bf,0,1
-aa1320aa,0,1
-9fcb8eb3,0,1
-6bf549d9,0,1
-49bd3de ,0,1
-dd09fb8d,0,1
-1285908a,0,1
-3eb37ea8,0,1
-68eb3a8c,1,1
-bfcceaa6,0,1
-a2264db5,0,1
-4ba05e93,0,1
-b60ac4cb,0,1
-9edcb672,0,1
-637780 ,0,1
-860e62d9,0,1
-8a983052,0,1
-35e38f6f,0,1
-d2e8b382,0,1
-3482b173,0,1
-9d76f455,0,1
-5b623fda,0,1
-b08ab5bf,0,1
-332433a7,0,1
-17aced3b,1,1
-2319760c,0,1
-c25e8486,0,1
-e2be9c44,0,1
-28e4aeaf,0,1
-ae725608,0,1
-d394d5f8,0,1
-f6768cc7,0,1
-7f51d709,0,1
-4c99a726,0,1
-2586fbc4,0,1
-d2f30b37,0,1
-8c71f0c5,0,1
-4acf0b2d,0,1
-d0d8e335,0,1
-88af1d5f,0,1
-e69dad36,1,1
-2a17c8e9,0,1
-63931b41,0,1
-d191bfc8,0,1
-40d7f3fc,0,1
-60754253,0,1
-d5f6ef4c,0,1
-a49ff89d,0,1
-b3f9bc39,0,1
-7ba3ec2e,0,1
-f100cac2,0,1
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diff --git a/sha-2-accelerator/simulate/stimulus/system/output_hash_32bit_ref.csv b/sha-2-accelerator/simulate/stimulus/system/output_hash_32bit_ref.csv
deleted file mode 100644
index 76655dd804a388379f79c7d165575c0e54a31bb5..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/system/output_hash_32bit_ref.csv
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/input_buf_id_stim.csv b/sha-2-accelerator/simulate/stimulus/unit/input_buf_id_stim.csv
deleted file mode 100644
index 99b9722ce61e1f07bc04f292c3c21b27f57de54b..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/input_buf_id_stim.csv
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/input_cfg_stim.csv b/sha-2-accelerator/simulate/stimulus/unit/input_cfg_stim.csv
deleted file mode 100644
index f13e931de23068774a02106284f6a5812b87f19d..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/input_cfg_stim.csv
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/input_cfg_sync_stim.csv b/sha-2-accelerator/simulate/stimulus/unit/input_cfg_sync_stim.csv
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index 672ecf82e46da05bd6f44c0e2f4880143269fa02..0000000000000000000000000000000000000000
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/input_data_stim.csv b/sha-2-accelerator/simulate/stimulus/unit/input_data_stim.csv
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deleted file mode 100644
index 04962ea4bdf3cea5edb3b80b5c2389bbb8eb41e2..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/input_hash_in_stim.csv
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deleted file mode 100644
index 5b41598d2a41805c930912c19559de278c4b78ad..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/input_id_stim.csv
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/input_message_block_stim.csv b/sha-2-accelerator/simulate/stimulus/unit/input_message_block_stim.csv
deleted file mode 100644
index d693581624461549fd4cd9ee569c912bf04855fd..0000000000000000000000000000000000000000
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/input_validator_id_stim.csv b/sha-2-accelerator/simulate/stimulus/unit/input_validator_id_stim.csv
deleted file mode 100644
index 99938c49eae2246bbdb917ec81f62fbab84e7900..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/input_validator_id_stim.csv
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/output_buf_id_ref.csv b/sha-2-accelerator/simulate/stimulus/unit/output_buf_id_ref.csv
deleted file mode 100644
index f1b55d9ffb3c7122d97f367cae3fce841c19cfb7..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/output_buf_id_ref.csv
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/output_cfg_sync_ref.csv b/sha-2-accelerator/simulate/stimulus/unit/output_cfg_sync_ref.csv
deleted file mode 100644
index 278204cd107ee978eef0e0d491b7282608e00871..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/output_cfg_sync_ref.csv
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/output_hash_out_ref.csv b/sha-2-accelerator/simulate/stimulus/unit/output_hash_out_ref.csv
deleted file mode 100644
index 54dca0fc65ccd8e53c96120459e96924d9aef294..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/simulate/stimulus/unit/output_hash_out_ref.csv
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deleted file mode 100644
index 1f32b447ed8129a16251b5b0f8880897d5f6aeda..0000000000000000000000000000000000000000
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deleted file mode 100644
index 6a737de7ac5a5f204e7dd8b46bd8c2046a19517c..0000000000000000000000000000000000000000
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diff --git a/sha-2-accelerator/simulate/stimulus/unit/output_message_block_ref.csv b/sha-2-accelerator/simulate/stimulus/unit/output_message_block_ref.csv
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diff --git a/sha-2-accelerator/sourceme b/sha-2-accelerator/sourceme
deleted file mode 100755
index febef30dcc12f5c0ed02e22352ff1d3162e2ac20..0000000000000000000000000000000000000000
--- a/sha-2-accelerator/sourceme
+++ /dev/null
@@ -1,44 +0,0 @@
-#-----------------------------------------------------------------------------
-# SoC Labs Environment Setup Script
-# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-#
-# Contributors
-#
-# David Mapstone (d.a.mapstone@soton.ac.uk)
-#
-# Copyright 2022, SoC Labs (www.soclabs.org)
-#-----------------------------------------------------------------------------
-
-#!/usr/bin/env bash
-
-if [ -z "$SHA_2_ACC_DIR" ]; then
- # Set environment Variables for Repository
- export SHA_2_ACC_DIR="$( cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P )"
-
- if [ -z "$SOC_ENV_SET" ]; then
- # Add flow directory to Path
- export PATH=$PATH:$SHA_2_ACC_DIR/flow
-
- # Set Default Simulator
- export SIMULATOR="ivlog"
-
- # Set Top-level Directory
- export SOC_TOP=$SHA_2_ACC_DIR
-
- # Set flag to say this is top level repo
- export SOC_ENV_SET="True"
-
- # Source Top-level sourceme
- for d in $WRAP_ACC_DIR/../* ; do
- if [ -d "$d" ]; then
- if test -f "$d/sourceme"; then
- source $d/sourceme
- fi
- fi
- done
-
- # Clear SOC_ENV_SET Variable
- unset SOC_ENV_SET
- fi
-fi
-