From e6b5b7f8ecaf9c29b4fb92809a502d39b2aab4c4 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Thu, 29 Jun 2023 20:56:24 +0100
Subject: [PATCH] Updated accelerator subsystem instantiation
---
nanosoc_tech | 2 +-
system/src/accelerator_subsystem.v | 8 ++++----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/nanosoc_tech b/nanosoc_tech
index 9408699..8b5ab2e 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 9408699b35a7fe343821afdb8cb164754ed80dda
+Subproject commit 8b5ab2e812b773bfee88ccf57d0437a43c74393b
diff --git a/system/src/accelerator_subsystem.v b/system/src/accelerator_subsystem.v
index a6e5690..c07da89 100644
--- a/system/src/accelerator_subsystem.v
+++ b/system/src/accelerator_subsystem.v
@@ -25,17 +25,17 @@ module accelerator_subsystem #(
// AHB connection to Initiator
input wire HSEL,
- input wire [AHBADDRWIDTH-1:0] HADDR,
+ input wire [SYS_ADDR_W-1:0] HADDR,
input wire [1:0] HTRANS,
input wire [2:0] HSIZE,
input wire [3:0] HPROT,
input wire HWRITE,
input wire HREADY,
- input wire [31:0] HWDATA,
+ input wire [SYS_DATA_W-1:0] HWDATA,
output wire HREADYOUT,
output wire HRESP,
- output wire [31:0] HRDATA,
+ output wire [SYS_DATA_W-1:0] HRDATA,
// Data Request Signal to DMAC
output wire [1:0] EXP_DRQ,
@@ -50,7 +50,7 @@ module accelerator_subsystem #(
.ahb_hclk (HCLK),
.ahb_hresetn (HRESETn),
.ahb_hsel (HSEL),
- .ahb_haddr16 (HADDR[15:0]),
+ .ahb_haddr16 (HADDR[AHBADDRWIDTH-1:0]),
.ahb_htrans (HTRANS),
.ahb_hwrite (HWRITE),
.ahb_hsize (HSIZE),
--
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