From cfef7ffdcd0c963cf8c37e05adcaa1cdc67f08cd Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Thu, 22 Jun 2023 12:27:47 +0100 Subject: [PATCH] Changed Incdir syntax in filelists and started writing lint waivers --- .gitignore | 1 + flist/mem/fpga_mem.flist | 2 +- flist/nanosoc/nanosoc_tb.flist | 2 +- nanosoc_tech | 2 +- soctools_flow | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/.gitignore b/.gitignore index 842fc71..fca9ac0 100644 --- a/.gitignore +++ b/.gitignore @@ -1,6 +1,7 @@ *.vcd *.vvp simulate/sim/* +lint/* .socinit accelerator/html/* wrapper/html/* diff --git a/flist/mem/fpga_mem.flist b/flist/mem/fpga_mem.flist index 2df4506..7d33d33 100644 --- a/flist/mem/fpga_mem.flist +++ b/flist/mem/fpga_mem.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= -+incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ +-incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ // - Top-level testbench $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v \ No newline at end of file diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist index 4c7b31c..043c564 100644 --- a/flist/nanosoc/nanosoc_tb.flist +++ b/flist/nanosoc/nanosoc_tb.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= -+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ +-incdir $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/ // - Top-level testbench $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb.v diff --git a/nanosoc_tech b/nanosoc_tech index d0ddcf0..cb7b26a 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit d0ddcf03185befc43936756573f3bc4aa7d496b1 +Subproject commit cb7b26aa5a553766cc90e513d146f6cfd7ac9142 diff --git a/soctools_flow b/soctools_flow index e5b63d6..ce9edaa 160000 --- a/soctools_flow +++ b/soctools_flow @@ -1 +1 @@ -Subproject commit e5b63d6e283f277a79947bcd4a616e4bf3ebadd9 +Subproject commit ce9edaa78fac0d09ad9466e4bc159e999483fd12 -- GitLab