diff --git a/.gitignore b/.gitignore
index 842fc71a62a4b6fdbfad7ff5b7d5f6818694d117..fca9ac03099591647bde2016acddc37017b89d33 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,6 +1,7 @@
 *.vcd
 *.vvp
 simulate/sim/*
+lint/*
 .socinit
 accelerator/html/*
 wrapper/html/*
diff --git a/flist/mem/fpga_mem.flist b/flist/mem/fpga_mem.flist
index 2df450680b160600f0c86f11fb48e61a60bdef5e..7d33d33da563e9e6310a10dad7805712419e45cd 100644
--- a/flist/mem/fpga_mem.flist
+++ b/flist/mem/fpga_mem.flist
@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Testbench search path    =============
-+incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/
+-incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/
 
 // - Top-level testbench
 $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist
index 4c7b31c13ccc093e4bce684453d2a6e62eb54192..043c56417e7613c29301186fedbd00fdf4aa9695 100644
--- a/flist/nanosoc/nanosoc_tb.flist
+++ b/flist/nanosoc/nanosoc_tb.flist
@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Testbench search path    =============
-+incdir+$(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
+-incdir $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/
 
 // - Top-level testbench
 $(SOCLABS_NANOSOC_TECH_DIR)/verif/verilog/nanosoc_tb.v
diff --git a/nanosoc_tech b/nanosoc_tech
index d0ddcf03185befc43936756573f3bc4aa7d496b1..cb7b26aa5a553766cc90e513d146f6cfd7ac9142 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit d0ddcf03185befc43936756573f3bc4aa7d496b1
+Subproject commit cb7b26aa5a553766cc90e513d146f6cfd7ac9142
diff --git a/soctools_flow b/soctools_flow
index e5b63d6e283f277a79947bcd4a616e4bf3ebadd9..ce9edaa78fac0d09ad9466e4bc159e999483fd12 160000
--- a/soctools_flow
+++ b/soctools_flow
@@ -1 +1 @@
-Subproject commit e5b63d6e283f277a79947bcd4a616e4bf3ebadd9
+Subproject commit ce9edaa78fac0d09ad9466e4bc159e999483fd12