From 9c7fb45a00fb0ecba486fbee814eb0b91bd3db0c Mon Sep 17 00:00:00 2001
From: dwf1m12 <d.w.flynn@soton.ac.uk>
Date: Wed, 4 Oct 2023 21:15:54 +0100
Subject: [PATCH] DM230 default to allow AES128 project to work

---
 flist/project/accelerator.flist | 6 +++---
 flist/project/system.flist      | 6 +++++-
 nanosoc_tech                    | 2 +-
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/flist/project/accelerator.flist b/flist/project/accelerator.flist
index 2166f19..b531759 100644
--- a/flist/project/accelerator.flist
+++ b/flist/project/accelerator.flist
@@ -14,10 +14,10 @@
 // =============    Accelerator Module search path    =============
 
 // ! Point this to your Accelerator RTL
-//+incdir+$(ACCELERATOR_DIR)/src/rtl
++incdir+$(ACCELERATOR_DIR)/src/rtl
 
 // ! Point this to your Wrapper RTL
-///$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
 
 // ! Point this to your Subsystem RTL
-///$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
diff --git a/flist/project/system.flist b/flist/project/system.flist
index d5a2331..baa34e1 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -32,4 +32,8 @@
 -f $(SOCLABS_WRAPPER_TECH_DIR)/flist/accelerator_wrapper_ip.flist
 
 // - Bootrom Code RTL
-$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
+
+// the chosen DMA controller
+//-f $(SOCLABS_SLDMA350_TECH_DIR)/flist/sldma350_ahb.flist
+-f $(SOCLABS_SLDMA230_TECH_DIR)/flist/sldma230_ip.flist
diff --git a/nanosoc_tech b/nanosoc_tech
index 872cd26..5a0f5c8 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 872cd269323ed2cf442aff3830cb46ab25846ad8
+Subproject commit 5a0f5c8b88fc323c52701c75f7665bf948d7b16a
-- 
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