From 8f9dd46ee9824193d516cc443743d780e5f3d526 Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Wed, 5 Apr 2023 17:00:02 +0100 Subject: [PATCH] SOC1-164: Added Stimulus to run on secworks accelerator (requires padding to be done before hand) and added additional hardware modules and simulation scripts to get succesful simulation --- .gitignore | 3 +- accelerator-wrapper | 2 +- flist/ahb_ip.flist | 2 +- flist/primatives.flist | 22 + flist/wrapper.flist | 4 +- primatives/src/fifo_vr.sv | 162 ++++++++ secworks-sha256 | 2 +- simulate/socsim/wrapper_secworks_sha256.sh | 39 ++ system/stimulus/adp_hash_stim.cmd | 360 +++++++++-------- wrapper/src/wrapper_digest_filter.sv | 59 +++ wrapper/src/wrapper_secworks_sha256.sv | 77 +++- wrapper/stimulus/ahb_input_hash_stim.fri | 340 ++++++++-------- wrapper/stimulus/ahb_input_hash_stim.m2d | 420 ++++++++++++-------- wrapper/stimulus/input_block_32bit_stim.csv | 320 +++++++++++++++ wrapper/stimulus/output_hash_32bit_ref.csv | 80 ++++ wrapper/verif/tb_wrapper_secworks_sha256.sv | 263 ++++++++++++ 16 files changed, 1654 insertions(+), 501 deletions(-) create mode 100644 flist/primatives.flist create mode 100644 primatives/src/fifo_vr.sv create mode 100755 simulate/socsim/wrapper_secworks_sha256.sh create mode 100644 wrapper/src/wrapper_digest_filter.sv create mode 100644 wrapper/stimulus/input_block_32bit_stim.csv create mode 100644 wrapper/stimulus/output_hash_32bit_ref.csv create mode 100644 wrapper/verif/tb_wrapper_secworks_sha256.sv diff --git a/.gitignore b/.gitignore index 1ec1bff..1043bb3 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ *.vcd -*.vvp \ No newline at end of file +*.vvp +simulate/sim/* \ No newline at end of file diff --git a/accelerator-wrapper b/accelerator-wrapper index 5b9023d..1c77ddd 160000 --- a/accelerator-wrapper +++ b/accelerator-wrapper @@ -1 +1 @@ -Subproject commit 5b9023da96fb288ce3d7e71e66afac48ed67c2d3 +Subproject commit 1c77ddd15197427f23676985d3f1df5754094b26 diff --git a/flist/ahb_ip.flist b/flist/ahb_ip.flist index 2896de6..65441c5 100644 --- a/flist/ahb_ip.flist +++ b/flist/ahb_ip.flist @@ -21,4 +21,4 @@ $(SOC_TOP_DIR)/cmsdk/ip/cmsdk_ahb_default_slave.v $(SOC_TOP_DIR)/cmsdk/ip/cmsdk_ahb_slave_mux.v -$(SOC_TOP_DIR)/cmsdk/ip/cmsdk_ahb_ram_beh.v \ No newline at end of file +// $(SOC_TOP_DIR)/cmsdk/ip/cmsdk_ahb_ram_beh.v \ No newline at end of file diff --git a/flist/primatives.flist b/flist/primatives.flist new file mode 100644 index 0000000..f97049b --- /dev/null +++ b/flist/primatives.flist @@ -0,0 +1,22 @@ +//----------------------------------------------------------------------------- +// PrimativesFilelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for RTL Primatives +//----------------------------------------------------------------------------- + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= Accelerator Module search path ============= +-y $(SOC_TOP_DIR)/primatives/src/ ++incdir+$(SOC_TOP_DIR)/primatives/src/ + +$(SOC_TOP_DIR)/primatives/src/fifo_vr.sv diff --git a/flist/wrapper.flist b/flist/wrapper.flist index e078838..7a73878 100644 --- a/flist/wrapper.flist +++ b/flist/wrapper.flist @@ -19,5 +19,5 @@ -y $(SOC_TOP_DIR)/wrapper/src/ +incdir+$(SOC_TOP_DIR)/wrapper/src/ -$(SOC_TOP_DIR)/wrapper/src/wrapper_vr_loopback.sv -$(SOC_TOP_DIR)/hdl/wrapper/wrapper_sha256_hashing_stream.sv \ No newline at end of file +$(SOC_TOP_DIR)/wrapper/src/wrapper_secworks_sha256.sv +$(SOC_TOP_DIR)/wrapper/src/wrapper_digest_filter.sv diff --git a/primatives/src/fifo_vr.sv b/primatives/src/fifo_vr.sv new file mode 100644 index 0000000..b86b9d4 --- /dev/null +++ b/primatives/src/fifo_vr.sv @@ -0,0 +1,162 @@ +//----------------------------------------------------------------------------- +// SoC Labs Basic Parameterisable Valid-Ready FIFO +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright 2022, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +module fifo_vr #( + parameter DEPTH = 4, // FIFO Row Depth + parameter DATA_W = 32, // FIFO Row Width + localparam PTR_W = $clog2(DEPTH) + 1 // Read/Write Pointer Width +)( + input logic clk, + input logic nrst, + input logic en, + + // Synchronous, localised reset + input logic sync_rst, + + // In (Write) Control + input logic [DATA_W-1:0] data_in, + input logic data_in_last, + input logic data_in_valid, + output logic data_in_ready, + + // Out (Read) Control + output logic [DATA_W-1:0] data_out, + output logic data_out_last, + input logic data_out_ready, + output logic data_out_valid, + + // Status + output logic [PTR_W-1:0] status_ptr_dif +); + + logic data_in_shake; // Successful Write Handshake + logic data_out_shake; // Successful Read Handshake + + assign data_in_shake = (data_in_valid == 1'b1) && (data_in_ready == 1'b1); + assign data_out_shake = (data_out_valid == 1'b1) && (data_out_ready == 1'b1); + + logic [DATA_W:0] fifo [DEPTH-1:0]; // FIFO Memory Structure + logic [PTR_W-1:0] write_ptr; // FIFO Write Pointer + logic [PTR_W-1:0] read_ptr; // FIFO Read Pointer + logic [PTR_W-1:0] ptr_dif; // Difference between Write and Read Pointers + + assign ptr_dif = write_ptr - read_ptr; + + assign status_ptr_dif = ptr_dif; + + // EXAMPLE: Conditions to write and read from FIFO's + // Write Ptr | Read Ptr | Ptr_Dif | Valid Write | Valid Read + // 000 - 000 = 000 | Y | N + // 001 - 000 = 001 | Y | Y + // 010 - 000 = 010 | Y | Y + // 011 - 000 = 011 | Y | Y + // 100 - 000 = 100 | N | Y + // 101 - 000 = 101 | N | N + // 110 - 000 = 110 | N | N + // 111 - 000 = 111 | N | N + // WriteValid: WritePtr - ReadPtr < 3'd4 + // ReadValid: WritePtr - ReadPtr - 1 < 3'd4 + + assign {data_out,data_out_last} = fifo [read_ptr[PTR_W-2:0]]; // Output Data is dereferenced value of the Read Pointer + + always_ff @(posedge clk, negedge nrst) begin + if ((!nrst) || sync_rst) begin + // Under Reset + // - Pointers reset to 0 (FIFO is empty without needing to reset the memories) + // - Control taken low + write_ptr <= 0; + read_ptr <= 0; + data_in_ready <= 1'b0; + data_out_valid <= 1'b0; + // Ensure FIFO Values are Known + for (int i = 0; i < DEPTH; i++) begin + fifo[i] <= 'b0; + end + end else if (en == 1'b1) begin + // Enable signal is High + // Write Logic + if (ptr_dif < DEPTH) begin + // Empty Rows in FIFO in FIFO + if (data_in_shake) begin + // Successful Handshake store data in FIFO and increment Write Pointer + fifo [write_ptr[PTR_W-2:0]] <= {data_in,data_in_last}; + write_ptr <= write_ptr + 1; + if ((ptr_dif + {{(PTR_W-1){1'b0}},(1'b1 - data_out_shake)}) < DEPTH) begin + // Still space in FIFO after latest write + // If theres a successful read on this clock cycle, + // there will be an additional space in the FIFO next clock cycle + // (number of pieces of data in the FIFO won't have changed) + data_in_ready <= 1'b1; + end else begin + // FIFO is now full + data_in_ready <= 1'b0; + end + end else begin + // Unsuccessful handshake but space in FIFO + // If there's write space now, next cc it will be the same or more + // (more if a succesful read has been carried out in this cc) + data_in_ready <= 1'b1; + end + end else begin + if ((ptr_dif - {{(PTR_W-1){1'b0}}, data_out_shake}) < DEPTH) begin + // If there is a successful read this clock cycle, + // there will be space for another piece of data in the FIFO + // (number of pieces of data in FIFO will have decremented by 1) + data_in_ready <= 1'b1; + end else begin + // FIFO still Full + data_in_ready <= 1'b0; + end + end + // Read Logic + if ((ptr_dif - 1) < DEPTH) begin + // Data in FIFO - atleast one Piece of Data in FIFO + // -> the "-1" causes dif of 0 to wrap where (dif - 1) becomes > DEPTH + if (data_out_shake) begin + // Successful Handshake Increment Read Pointer + read_ptr <= read_ptr + 1; + if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) - 1 < DEPTH) begin + // Still Data in FIFO after latest Read + // If there is a successful write this clock cycle, + // there will be one more piece of data in the FIFO + // (number of pieces of data in FIFO wont have changed) + data_out_valid <= 1'b1; + end else begin + // FIFO empty after latest Read + data_out_valid <= 1'b0; + end + end else begin + // Unsuccessful handshake but Data in FIFO + // If there's read data now, next cc it will be the same or more + // (more if a succesful write has been carried out in this cc) + data_out_valid <= 1'b1; + end + end else begin + if (((ptr_dif - 1) + {{(PTR_W-1){1'b0}},data_in_shake}) < DEPTH) begin + // If there is a successful write this clock cycle, + // there will be one more piece of data in the FIFO + // (number of pieces of data in FIFO will have incremented by 1) + data_out_valid <= 1'b1; + end else begin + // FIFO still empty + data_out_valid <= 1'b0; + end + end + end else begin + // If Enable is Low, set Control Low + data_in_ready <= 1'b0; + data_out_valid <= 1'b0; + end + end + + // Verif Notes to Check behaiour: + // 1) Fill FIFO up with Data + // 2) Read & Write in same clock cycle +endmodule diff --git a/secworks-sha256 b/secworks-sha256 index 20ab187..edec92f 160000 --- a/secworks-sha256 +++ b/secworks-sha256 @@ -1 +1 @@ -Subproject commit 20ab187e1c653f1ccdf726553fde14c4b792b07d +Subproject commit edec92f3167b358d58f65a2fad4b7f929d78aeb0 diff --git a/simulate/socsim/wrapper_secworks_sha256.sh b/simulate/socsim/wrapper_secworks_sha256.sh new file mode 100755 index 0000000..64ecee6 --- /dev/null +++ b/simulate/socsim/wrapper_secworks_sha256.sh @@ -0,0 +1,39 @@ +#----------------------------------------------------------------------------- +# SoC Labs icarus verilog simulation script for engine testbench +# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +# +# Contributors +# +# David Mapstone (d.a.mapstone@soton.ac.uk) +# +# Copyright 2022, SoC Labs (www.soclabs.org) +#----------------------------------------------------------------------------- + +#!/usr/bin/env bash + +# Generate Stimulus from stimulus generation Script +# python3 $ACC_SEC_SHA2_DIR/flow/stimgen.py +# Create Simulatiom Directory to Run in +mkdir -p $SOC_TOP_DIR/simulate/sim/ +mkdir -p $SOC_TOP_DIR/simulate/sim/wrapper_secworks_sha256 + +cd $SOC_TOP_DIR/simulate/sim/wrapper_secworks_sha256 +# Compile Simulation +xrun \ + -64bit \ + -sv \ + -timescale 1ps/1ps \ + +access+r \ + -f $SOC_TOP_DIR/flist/wrapper.flist \ + -f $SOC_TOP_DIR/flist/primatives.flist \ + -f $SOC_TOP_DIR/flist/ahb_ip.flist \ + -f $SOC_TOP_DIR/flist/ahb_vip.flist \ + -f $ACC_SEC_SHA2_DIR/flist/*.flist \ + -f $ACC_WRAPPER_DIR/flist/wrapper_ip.flist \ + -xmlibdirname $SOC_TOP_DIR/simulate/sim/wrapper_secworks_sha256 \ + $SOC_TOP_DIR/wrapper/verif/tb_wrapper_secworks_sha256.sv \ + -gui \ + -top tb_wrapper_secworks_sha256 + +# Run Simulation +# cd $SOC_TOP_DIR/simulate/sim/ && vvp wrapper_sha256_hashing_stream.vvp \ No newline at end of file diff --git a/system/stimulus/adp_hash_stim.cmd b/system/stimulus/adp_hash_stim.cmd index e4c6f50..bf7c416 100644 --- a/system/stimulus/adp_hash_stim.cmd +++ b/system/stimulus/adp_hash_stim.cmd @@ -1,36 +1,40 @@ A -a 0x600107c0 +a 0x60010780 w 0x94748770 -a 0x600107c4 +a 0x60010784 w 0x0e3109cc -a 0x600107c8 +a 0x60010788 w 0xc4411b41 -a 0x600107cc +a 0x6001078c w 0x5349fe99 -a 0x600107d0 +a 0x60010790 w 0xbc3bdfc1 -a 0x600107d4 +a 0x60010794 w 0xdeb5cb2a -a 0x600107d8 +a 0x60010798 w 0xa0052ca2 -a 0x600107dc +a 0x6001079c w 0x1761b000 -a 0x600107e0 +a 0x600107a0 w 0x1b5affff -a 0x600107e4 +a 0x600107a4 w 0xeab53b7e -a 0x600107e8 +a 0x600107a8 w 0x81152f06 -a 0x600107ec +a 0x600107ac w 0x7d60ab33 -a 0x600107f0 +a 0x600107b0 w 0x1ce3c906 -a 0x600107f4 +a 0x600107b4 w 0x707476fe -a 0x600107f8 +a 0x600107b8 w 0x923737f4 -a 0x600107fc +a 0x600107bc w 0x695b2443 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0xe06f1bef a 0x60010fe4 @@ -47,38 +51,42 @@ a 0x60010ff8 r 0xe14c46de a 0x60010ffc r 0xe1711626 -a 0x600107c0 +a 0x60010780 w 0xf7079da3 -a 0x600107c4 +a 0x60010784 w 0xa0c46731 -a 0x600107c8 +a 0x60010788 w 0xc51f9e09 -a 0x600107cc +a 0x6001078c w 0x8d8993e6 -a 0x600107d0 +a 0x60010790 w 0xfd33039d -a 0x600107d4 +a 0x60010794 w 0xe8675d4a -a 0x600107d8 +a 0x60010798 w 0xc0e513a1 -a 0x600107dc +a 0x6001079c w 0x858c0663 -a 0x600107e0 +a 0x600107a0 w 0xa1fb693e -a 0x600107e4 +a 0x600107a4 w 0xd5ebd6d4 -a 0x600107e8 +a 0x600107a8 w 0x26f7441f -a 0x600107ec +a 0x600107ac w 0x907554b5 -a 0x600107f0 +a 0x600107b0 w 0x9db705fd -a 0x600107f4 +a 0x600107b4 w 0x47a57bf5 -a 0x600107f8 +a 0x600107b8 w 0xfe2518c8 -a 0x600107fc +a 0x600107bc w 0x4c5b82c1 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0xd065f05e a 0x60010fe4 @@ -95,38 +103,42 @@ a 0x60010ff8 r 0xef598a6e a 0x60010ffc r 0x58d6d30f -a 0x600107c0 +a 0x60010780 w 0x28b3253a -a 0x600107c4 +a 0x60010784 w 0x96dbf9e5 -a 0x600107c8 +a 0x60010788 w 0x55e5ab02 -a 0x600107cc +a 0x6001078c w 0x6bbbc74a -a 0x600107d0 +a 0x60010790 w 0xed5fbca6 -a 0x600107d4 +a 0x60010794 w 0x73ece6c4 -a 0x600107d8 +a 0x60010798 w 0x832fa959 -a 0x600107dc +a 0x6001079c w 0x7a0d31bf -a 0x600107e0 +a 0x600107a0 w 0xaa1320aa -a 0x600107e4 +a 0x600107a4 w 0x9fcb8eb3 -a 0x600107e8 +a 0x600107a8 w 0x6bf549d9 -a 0x600107ec +a 0x600107ac w 0x049bd3de -a 0x600107f0 +a 0x600107b0 w 0xdd09fb8d -a 0x600107f4 +a 0x600107b4 w 0x1285908a -a 0x600107f8 +a 0x600107b8 w 0x3eb37ea8 -a 0x600107fc +a 0x600107bc w 0x68eb3a8c +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0xe4e3afb2 a 0x60010fe4 @@ -143,38 +155,42 @@ a 0x60010ff8 r 0xcc9f9269 a 0x60010ffc r 0xed646faf -a 0x600107c0 +a 0x60010780 w 0xbfcceaa6 -a 0x600107c4 +a 0x60010784 w 0xa2264db5 -a 0x600107c8 +a 0x60010788 w 0x4ba05e93 -a 0x600107cc +a 0x6001078c w 0xb60ac4cb -a 0x600107d0 +a 0x60010790 w 0x9edcb672 -a 0x600107d4 +a 0x60010794 w 0x00637780 -a 0x600107d8 +a 0x60010798 w 0x860e62d9 -a 0x600107dc +a 0x6001079c w 0x8a983052 -a 0x600107e0 +a 0x600107a0 w 0x35e38f6f -a 0x600107e4 +a 0x600107a4 w 0xd2e8b382 -a 0x600107e8 +a 0x600107a8 w 0x3482b173 -a 0x600107ec +a 0x600107ac w 0x9d76f455 -a 0x600107f0 +a 0x600107b0 w 0x5b623fda -a 0x600107f4 +a 0x600107b4 w 0xb08ab5bf -a 0x600107f8 +a 0x600107b8 w 0x332433a7 -a 0x600107fc +a 0x600107bc w 0x17aced3b +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0xad5d7f58 a 0x60010fe4 @@ -191,38 +207,42 @@ a 0x60010ff8 r 0x5a1b530b a 0x60010ffc r 0x49393b4e -a 0x600107c0 +a 0x60010780 w 0x2319760c -a 0x600107c4 +a 0x60010784 w 0xc25e8486 -a 0x600107c8 +a 0x60010788 w 0xe2be9c44 -a 0x600107cc +a 0x6001078c w 0x28e4aeaf -a 0x600107d0 +a 0x60010790 w 0xae725608 -a 0x600107d4 +a 0x60010794 w 0xd394d5f8 -a 0x600107d8 +a 0x60010798 w 0xf6768cc7 -a 0x600107dc +a 0x6001079c w 0x7f51d709 -a 0x600107e0 +a 0x600107a0 w 0x4c99a726 -a 0x600107e4 +a 0x600107a4 w 0x2586fbc4 -a 0x600107e8 +a 0x600107a8 w 0xd2f30b37 -a 0x600107ec +a 0x600107ac w 0x8c71f0c5 -a 0x600107f0 +a 0x600107b0 w 0x4acf0b2d -a 0x600107f4 +a 0x600107b4 w 0xd0d8e335 -a 0x600107f8 +a 0x600107b8 w 0x88af1d5f -a 0x600107fc +a 0x600107bc w 0xe69dad36 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0x105755f3 a 0x60010fe4 @@ -239,38 +259,42 @@ a 0x60010ff8 r 0x9a63b562 a 0x60010ffc r 0x95262422 -a 0x600107c0 +a 0x60010780 w 0x2a17c8e9 -a 0x600107c4 +a 0x60010784 w 0x63931b41 -a 0x600107c8 +a 0x60010788 w 0xd191bfc8 -a 0x600107cc +a 0x6001078c w 0x40d7f3fc -a 0x600107d0 +a 0x60010790 w 0x60754253 -a 0x600107d4 +a 0x60010794 w 0xd5f6ef4c -a 0x600107d8 +a 0x60010798 w 0xa49ff89d -a 0x600107dc +a 0x6001079c w 0xb3f9bc39 -a 0x600107e0 +a 0x600107a0 w 0x7ba3ec2e -a 0x600107e4 +a 0x600107a4 w 0xf100cac2 -a 0x600107e8 +a 0x600107a8 w 0x552ac1d3 -a 0x600107ec +a 0x600107ac w 0x657744db -a 0x600107f0 +a 0x600107b0 w 0xfa2402f8 -a 0x600107f4 +a 0x600107b4 w 0x5e2ea772 -a 0x600107f8 +a 0x600107b8 w 0x572c2bf0 -a 0x600107fc +a 0x600107bc w 0x372eb887 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0x1f335cad a 0x60010fe4 @@ -287,38 +311,42 @@ a 0x60010ff8 r 0x96cf9939 a 0x60010ffc r 0x38849fc2 -a 0x600107c0 +a 0x60010780 w 0xac465530 -a 0x600107c4 +a 0x60010784 w 0x6e6a3d49 -a 0x600107c8 +a 0x60010788 w 0xe7f1461f -a 0x600107cc +a 0x6001078c w 0xc6f4b35f -a 0x600107d0 +a 0x60010790 w 0xf82a46d6 -a 0x600107d4 +a 0x60010794 w 0x440244f5 -a 0x600107d8 +a 0x60010798 w 0x6bde0ef1 -a 0x600107dc +a 0x6001079c w 0xb0787487 -a 0x600107e0 +a 0x600107a0 w 0x1a96af96 -a 0x600107e4 +a 0x600107a4 w 0xa55fef07 -a 0x600107e8 +a 0x600107a8 w 0xea97471c -a 0x600107ec +a 0x600107ac w 0x35bad402 -a 0x600107f0 +a 0x600107b0 w 0xb3733250 -a 0x600107f4 +a 0x600107b4 w 0x75028929 -a 0x600107f8 +a 0x600107b8 w 0x230c2b19 -a 0x600107fc +a 0x600107bc w 0x0bfe6ea9 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0x0b51e243 a 0x60010fe4 @@ -335,38 +363,42 @@ a 0x60010ff8 r 0xae0cb755 a 0x60010ffc r 0xee161bc2 -a 0x600107c0 +a 0x60010780 w 0xec8225d7 -a 0x600107c4 +a 0x60010784 w 0x9193267a -a 0x600107c8 +a 0x60010788 w 0xc3f24d94 -a 0x600107cc +a 0x6001078c w 0xb295566e -a 0x600107d0 +a 0x60010790 w 0x034a0bc0 -a 0x600107d4 +a 0x60010794 w 0x1a4d2e6b -a 0x600107d8 +a 0x60010798 w 0xa6ed70c9 -a 0x600107dc +a 0x6001079c w 0x4d573f76 -a 0x600107e0 +a 0x600107a0 w 0x45b0e216 -a 0x600107e4 +a 0x600107a4 w 0xdb750cbb -a 0x600107e8 +a 0x600107a8 w 0x4138b929 -a 0x600107ec +a 0x600107ac w 0xd67d1bbd -a 0x600107f0 +a 0x600107b0 w 0x24fdf316 -a 0x600107f4 +a 0x600107b4 w 0x0650c084 -a 0x600107f8 +a 0x600107b8 w 0xf95e6e9c -a 0x600107fc +a 0x600107bc w 0x877e2642 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0x6d572f08 a 0x60010fe4 @@ -383,38 +415,42 @@ a 0x60010ff8 r 0x51c0db63 a 0x60010ffc r 0x60f9e31b -a 0x600107c0 +a 0x60010780 w 0x387dc590 -a 0x600107c4 +a 0x60010784 w 0x2966f6a3 -a 0x600107c8 +a 0x60010788 w 0xadd14662 -a 0x600107cc +a 0x6001078c w 0x0bc2175e -a 0x600107d0 +a 0x60010790 w 0x3d2556a0 -a 0x600107d4 +a 0x60010794 w 0x335c30a8 -a 0x600107d8 +a 0x60010798 w 0x50e7e900 -a 0x600107dc +a 0x6001079c w 0xb1b72206 -a 0x600107e0 +a 0x600107a0 w 0xc6f526b0 -a 0x600107e4 +a 0x600107a4 w 0x15a4177f -a 0x600107e8 +a 0x600107a8 w 0xf0d718a4 -a 0x600107ec +a 0x600107ac w 0x48879677 -a 0x600107f0 +a 0x600107b0 w 0x8934d6c4 -a 0x600107f4 +a 0x600107b4 w 0x50ab7c39 -a 0x600107f8 +a 0x600107b8 w 0x3360bbd7 -a 0x600107fc +a 0x600107bc w 0xefdf5963 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0x24eb65ee a 0x60010fe4 @@ -431,38 +467,42 @@ a 0x60010ff8 r 0xb6a8cf6c a 0x60010ffc r 0x3a012531 -a 0x600107c0 +a 0x60010780 w 0x2a22cd0b -a 0x600107c4 +a 0x60010784 w 0xf570eb78 -a 0x600107c8 +a 0x60010788 w 0xd3a5b873 -a 0x600107cc +a 0x6001078c w 0x53d7f89b -a 0x600107d0 +a 0x60010790 w 0xebedc242 -a 0x600107d4 +a 0x60010794 w 0x59a1ee9a -a 0x600107d8 +a 0x60010798 w 0xcea792f4 -a 0x600107dc +a 0x6001079c w 0xedf99c9c -a 0x600107e0 +a 0x600107a0 w 0x47ab7368 -a 0x600107e4 +a 0x600107a4 w 0xa0eddacc -a 0x600107e8 +a 0x600107a8 w 0xe218002f -a 0x600107ec +a 0x600107ac w 0x1498319a -a 0x600107f0 +a 0x600107b0 w 0xb1f10e58 -a 0x600107f4 +a 0x600107b4 w 0x8d03ecb0 -a 0x600107f8 +a 0x600107b8 w 0x4408ab12 -a 0x600107fc +a 0x600107bc w 0xcabcc637 +a 0x600107c0 +w 0x00000200 +a 0x600107fc +w 0x80000000 a 0x60010fe0 r 0x5951566a a 0x60010fe4 diff --git a/wrapper/src/wrapper_digest_filter.sv b/wrapper/src/wrapper_digest_filter.sv new file mode 100644 index 0000000..498b48f --- /dev/null +++ b/wrapper/src/wrapper_digest_filter.sv @@ -0,0 +1,59 @@ +//----------------------------------------------------------------------------- +// SoC Labs Digest Valid Signal Filter Module +// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright 2023; SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- + +module wrapper_digest_filter( + input logic clk, + input logic rst, + input logic s_tlast_i, + input logic s_tvalid_i, + input logic s_tready_o, + input logic digest_valid_o, + output logic hash_valid_o +); + +logic [63:0] block_count, count_check, digest_count; +logic prev_last; +logic prev_digest_valid_o; + +always_ff @(posedge clk, posedge rst) begin + if (rst) begin + block_count <= 'd0; + count_check <= 'd0; + digest_count <= 'd0; + prev_digest_valid_o <= 'd0; + // hash_valid_o <= 1'd0; + prev_last <= 1'd0; + end else begin + prev_digest_valid_o <= digest_valid_o; + if (s_tvalid_i && s_tready_o) begin + prev_last <= s_tlast_i; + if (s_tlast_i) begin + block_count <= 'd0; + count_check <= block_count + 1'd1; + end else begin + block_count <= block_count + 64'd1; + end + end + // hash_valid_o <= 1'b0; + if (digest_valid_o == 1'd0 && prev_digest_valid_o == 1'd1) begin + if (digest_count == (count_check - 64'd1)) begin + digest_count <= 'd0; + // hash_valid_o <= 1'b1; + end else begin + digest_count <= digest_count + 'd1; + end + end + end +end + +// Only takes Valid High for 1 Clock Cycle (Requires Change) and only takes valid high on when correct number of output packets seen +assign hash_valid_o = (digest_count == (count_check - 64'd1)) && ~prev_digest_valid_o ? digest_valid_o : 1'b0; +endmodule \ No newline at end of file diff --git a/wrapper/src/wrapper_secworks_sha256.sv b/wrapper/src/wrapper_secworks_sha256.sv index aaf27cb..b271dd0 100644 --- a/wrapper/src/wrapper_secworks_sha256.sv +++ b/wrapper/src/wrapper_secworks_sha256.sv @@ -213,17 +213,17 @@ module wrapper_secworks_sha256 #( //---------------------------------------------------------- // Engine Output Port Wire declarations - logic [OUTPACKETWIDTH-1:0] out_packet; - logic out_packet_last; - logic [OUTPACKETSPACEWIDTH-1:0] out_packet_remain; - logic out_packet_valid; - logic out_packet_ready; + logic [OUTPACKETWIDTH-1:0] out_hash; + logic out_hash_last; + logic [OUTPACKETSPACEWIDTH-1:0] out_hash_remain; + logic out_hash_valid; + logic out_hash_ready; + // Relative Read Address for Start of Current Block logic [OUTPORTAHBADDRWIDTH-1:0] block_read_addr; - // Block Packets Remaining Tie-off (only ever one packet per block) - assign out_packet_remain = {OUTPACKETSPACEWIDTH{1'b0}}; + // Packet Deconstructor Instantiation wrapper_ahb_packet_deconstructor #( @@ -247,11 +247,11 @@ module wrapper_secworks_sha256 #( .hrdatas (hrdata1), // Valid/Ready Interface - .packet_data (out_packet), - .packet_data_last (out_packet_last), - .packet_data_remain (out_packet_remain), - .packet_data_valid (out_packet_valid), - .packet_data_ready (out_packet_ready), + .packet_data (out_hash), + .packet_data_last (out_hash_last), + .packet_data_remain (out_hash_remain), + .packet_data_valid (out_hash_valid), + .packet_data_ready (out_hash_ready), // Input Data Request .data_req (out_data_req), @@ -308,11 +308,39 @@ module wrapper_secworks_sha256 #( // Accelerator Engine Logic //---------------------------------------------------------- + logic out_digest_valid; + + // Engine Output Port Wire declarations + logic [OUTPACKETWIDTH-1:0] out_packet; + logic out_packet_last; + logic [OUTPACKETSPACEWIDTH-1:0] out_packet_remain; + logic out_packet_valid; + logic out_packet_ready; + + // Block Packets Remaining Tie-off (only ever one packet per block) + assign out_packet_remain = {OUTPACKETSPACEWIDTH{1'b0}}; + + // Hashing Accelerator Instatiation + wrapper_digest_filter u_digest_filter ( + .clk (HCLK), + .rst (~HRESETn), + + // Data in Channel + .s_tvalid_i (in_packet_valid), + .s_tready_o (in_packet_ready), + .s_tlast_i (in_packet_last), + + // Data Out Channel + .digest_valid_o (out_digest_valid), + .hash_valid_o (out_packet_valid) + ); + + // Hashing Accelerator Instatiation sha256_stream u_sha256_stream ( .clk (HCLK), - .nrst (HRESETn), - .mode (1'b1) + .rst (~HRESETn), + .mode (1'b1), // Data in Channel .s_tdata_i (in_packet), @@ -322,9 +350,28 @@ module wrapper_secworks_sha256 #( // Data Out Channel .digest_o (out_packet), - .digest_valid_o (out_packet_valid) + .digest_valid_o (out_digest_valid) ); assign out_packet_last = 1'b1; + // Output FIFO (Output has no handshaking) + fifo_vr #( + 4, + 256 + ) u_output_fifo ( + .clk (HCLK), + .nrst (HRESETn), + .en (1'b1), + .sync_rst (1'b0), + .data_in (out_packet), + .data_in_last (out_packet_last), + .data_in_valid (out_packet_valid), + .data_in_ready (), + .data_out (out_hash), + .data_out_valid (out_hash_valid), + .data_out_ready (out_hash_ready), + .data_out_last (out_hash_last), + .status_ptr_dif () + ); endmodule \ No newline at end of file diff --git a/wrapper/stimulus/ahb_input_hash_stim.fri b/wrapper/stimulus/ahb_input_hash_stim.fri index 0958904..5a70a66 100644 --- a/wrapper/stimulus/ahb_input_hash_stim.fri +++ b/wrapper/stimulus/ahb_input_hash_stim.fri @@ -9,22 +9,24 @@ ;# Copyright 2023, SoC Labs (www.soclabs.org) ;#----------------------------------------------------------------------------- ;Transaction Address Data Size -W 0x600107c0 0x94748770 word -W 0x600107c4 0x0e3109cc word -W 0x600107c8 0xc4411b41 word -W 0x600107cc 0x5349fe99 word -W 0x600107d0 0xbc3bdfc1 word -W 0x600107d4 0xdeb5cb2a word -W 0x600107d8 0xa0052ca2 word -W 0x600107dc 0x1761b000 word -W 0x600107e0 0x1b5affff word -W 0x600107e4 0xeab53b7e word -W 0x600107e8 0x81152f06 word -W 0x600107ec 0x7d60ab33 word -W 0x600107f0 0x1ce3c906 word -W 0x600107f4 0x707476fe word -W 0x600107f8 0x923737f4 word -W 0x600107fc 0x695b2443 word +W 0x60010780 0x94748770 word +W 0x60010784 0x0e3109cc word +W 0x60010788 0xc4411b41 word +W 0x6001078c 0x5349fe99 word +W 0x60010790 0xbc3bdfc1 word +W 0x60010794 0xdeb5cb2a word +W 0x60010798 0xa0052ca2 word +W 0x6001079c 0x1761b000 word +W 0x600107a0 0x1b5affff word +W 0x600107a4 0xeab53b7e word +W 0x600107a8 0x81152f06 word +W 0x600107ac 0x7d60ab33 word +W 0x600107b0 0x1ce3c906 word +W 0x600107b4 0x707476fe word +W 0x600107b8 0x923737f4 word +W 0x600107bc 0x695b2443 word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0xe06f1bef word R 0x60010fe4 0xf498916a word R 0x60010fe8 0x4686ebb1 word @@ -33,22 +35,24 @@ R 0x60010ff0 0x960ea091 word R 0x60010ff4 0xeb558be4 word R 0x60010ff8 0xe14c46de word R 0x60010ffc 0xe1711626 word -W 0x600107c0 0xf7079da3 word -W 0x600107c4 0xa0c46731 word -W 0x600107c8 0xc51f9e09 word -W 0x600107cc 0x8d8993e6 word -W 0x600107d0 0xfd33039d word -W 0x600107d4 0xe8675d4a word -W 0x600107d8 0xc0e513a1 word -W 0x600107dc 0x858c0663 word -W 0x600107e0 0xa1fb693e word -W 0x600107e4 0xd5ebd6d4 word -W 0x600107e8 0x26f7441f word -W 0x600107ec 0x907554b5 word -W 0x600107f0 0x9db705fd word -W 0x600107f4 0x47a57bf5 word -W 0x600107f8 0xfe2518c8 word -W 0x600107fc 0x4c5b82c1 word +W 0x60010780 0xf7079da3 word +W 0x60010784 0xa0c46731 word +W 0x60010788 0xc51f9e09 word +W 0x6001078c 0x8d8993e6 word +W 0x60010790 0xfd33039d word +W 0x60010794 0xe8675d4a word +W 0x60010798 0xc0e513a1 word +W 0x6001079c 0x858c0663 word +W 0x600107a0 0xa1fb693e word +W 0x600107a4 0xd5ebd6d4 word +W 0x600107a8 0x26f7441f word +W 0x600107ac 0x907554b5 word +W 0x600107b0 0x9db705fd word +W 0x600107b4 0x47a57bf5 word +W 0x600107b8 0xfe2518c8 word +W 0x600107bc 0x4c5b82c1 word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0xd065f05e word R 0x60010fe4 0x1623b2c9 word R 0x60010fe8 0x9d3c0a90 word @@ -57,22 +61,24 @@ R 0x60010ff0 0x72fc05c5 word R 0x60010ff4 0xcf65fdbb word R 0x60010ff8 0xef598a6e word R 0x60010ffc 0x58d6d30f word -W 0x600107c0 0x28b3253a word -W 0x600107c4 0x96dbf9e5 word -W 0x600107c8 0x55e5ab02 word -W 0x600107cc 0x6bbbc74a word -W 0x600107d0 0xed5fbca6 word -W 0x600107d4 0x73ece6c4 word -W 0x600107d8 0x832fa959 word -W 0x600107dc 0x7a0d31bf word -W 0x600107e0 0xaa1320aa word -W 0x600107e4 0x9fcb8eb3 word -W 0x600107e8 0x6bf549d9 word -W 0x600107ec 0x049bd3de word -W 0x600107f0 0xdd09fb8d word -W 0x600107f4 0x1285908a word -W 0x600107f8 0x3eb37ea8 word -W 0x600107fc 0x68eb3a8c word +W 0x60010780 0x28b3253a word +W 0x60010784 0x96dbf9e5 word +W 0x60010788 0x55e5ab02 word +W 0x6001078c 0x6bbbc74a word +W 0x60010790 0xed5fbca6 word +W 0x60010794 0x73ece6c4 word +W 0x60010798 0x832fa959 word +W 0x6001079c 0x7a0d31bf word +W 0x600107a0 0xaa1320aa word +W 0x600107a4 0x9fcb8eb3 word +W 0x600107a8 0x6bf549d9 word +W 0x600107ac 0x049bd3de word +W 0x600107b0 0xdd09fb8d word +W 0x600107b4 0x1285908a word +W 0x600107b8 0x3eb37ea8 word +W 0x600107bc 0x68eb3a8c word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0xe4e3afb2 word R 0x60010fe4 0xa3be45c9 word R 0x60010fe8 0xb43f0fa3 word @@ -81,22 +87,24 @@ R 0x60010ff0 0xbbf2982b word R 0x60010ff4 0x15cd68c7 word R 0x60010ff8 0xcc9f9269 word R 0x60010ffc 0xed646faf word -W 0x600107c0 0xbfcceaa6 word -W 0x600107c4 0xa2264db5 word -W 0x600107c8 0x4ba05e93 word -W 0x600107cc 0xb60ac4cb word -W 0x600107d0 0x9edcb672 word -W 0x600107d4 0x00637780 word -W 0x600107d8 0x860e62d9 word -W 0x600107dc 0x8a983052 word -W 0x600107e0 0x35e38f6f word -W 0x600107e4 0xd2e8b382 word -W 0x600107e8 0x3482b173 word -W 0x600107ec 0x9d76f455 word -W 0x600107f0 0x5b623fda word -W 0x600107f4 0xb08ab5bf word -W 0x600107f8 0x332433a7 word -W 0x600107fc 0x17aced3b word +W 0x60010780 0xbfcceaa6 word +W 0x60010784 0xa2264db5 word +W 0x60010788 0x4ba05e93 word +W 0x6001078c 0xb60ac4cb word +W 0x60010790 0x9edcb672 word +W 0x60010794 0x00637780 word +W 0x60010798 0x860e62d9 word +W 0x6001079c 0x8a983052 word +W 0x600107a0 0x35e38f6f word +W 0x600107a4 0xd2e8b382 word +W 0x600107a8 0x3482b173 word +W 0x600107ac 0x9d76f455 word +W 0x600107b0 0x5b623fda word +W 0x600107b4 0xb08ab5bf word +W 0x600107b8 0x332433a7 word +W 0x600107bc 0x17aced3b word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0xad5d7f58 word R 0x60010fe4 0xc619f73f word R 0x60010fe8 0x5a54de49 word @@ -105,22 +113,24 @@ R 0x60010ff0 0x92343513 word R 0x60010ff4 0xea3cf2a9 word R 0x60010ff8 0x5a1b530b word R 0x60010ffc 0x49393b4e word -W 0x600107c0 0x2319760c word -W 0x600107c4 0xc25e8486 word -W 0x600107c8 0xe2be9c44 word -W 0x600107cc 0x28e4aeaf word -W 0x600107d0 0xae725608 word -W 0x600107d4 0xd394d5f8 word -W 0x600107d8 0xf6768cc7 word -W 0x600107dc 0x7f51d709 word -W 0x600107e0 0x4c99a726 word -W 0x600107e4 0x2586fbc4 word -W 0x600107e8 0xd2f30b37 word -W 0x600107ec 0x8c71f0c5 word -W 0x600107f0 0x4acf0b2d word -W 0x600107f4 0xd0d8e335 word -W 0x600107f8 0x88af1d5f word -W 0x600107fc 0xe69dad36 word +W 0x60010780 0x2319760c word +W 0x60010784 0xc25e8486 word +W 0x60010788 0xe2be9c44 word +W 0x6001078c 0x28e4aeaf word +W 0x60010790 0xae725608 word +W 0x60010794 0xd394d5f8 word +W 0x60010798 0xf6768cc7 word +W 0x6001079c 0x7f51d709 word +W 0x600107a0 0x4c99a726 word +W 0x600107a4 0x2586fbc4 word +W 0x600107a8 0xd2f30b37 word +W 0x600107ac 0x8c71f0c5 word +W 0x600107b0 0x4acf0b2d word +W 0x600107b4 0xd0d8e335 word +W 0x600107b8 0x88af1d5f word +W 0x600107bc 0xe69dad36 word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0x105755f3 word R 0x60010fe4 0x1ca8459e word R 0x60010fe8 0x08ffade5 word @@ -129,22 +139,24 @@ R 0x60010ff0 0xc6905543 word R 0x60010ff4 0x5ed0766b word R 0x60010ff8 0x9a63b562 word R 0x60010ffc 0x95262422 word -W 0x600107c0 0x2a17c8e9 word -W 0x600107c4 0x63931b41 word -W 0x600107c8 0xd191bfc8 word -W 0x600107cc 0x40d7f3fc word -W 0x600107d0 0x60754253 word -W 0x600107d4 0xd5f6ef4c word -W 0x600107d8 0xa49ff89d word -W 0x600107dc 0xb3f9bc39 word -W 0x600107e0 0x7ba3ec2e word -W 0x600107e4 0xf100cac2 word -W 0x600107e8 0x552ac1d3 word -W 0x600107ec 0x657744db word -W 0x600107f0 0xfa2402f8 word -W 0x600107f4 0x5e2ea772 word -W 0x600107f8 0x572c2bf0 word -W 0x600107fc 0x372eb887 word +W 0x60010780 0x2a17c8e9 word +W 0x60010784 0x63931b41 word +W 0x60010788 0xd191bfc8 word +W 0x6001078c 0x40d7f3fc word +W 0x60010790 0x60754253 word +W 0x60010794 0xd5f6ef4c word +W 0x60010798 0xa49ff89d word +W 0x6001079c 0xb3f9bc39 word +W 0x600107a0 0x7ba3ec2e word +W 0x600107a4 0xf100cac2 word +W 0x600107a8 0x552ac1d3 word +W 0x600107ac 0x657744db word +W 0x600107b0 0xfa2402f8 word +W 0x600107b4 0x5e2ea772 word +W 0x600107b8 0x572c2bf0 word +W 0x600107bc 0x372eb887 word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0x1f335cad word R 0x60010fe4 0x7d8c6b58 word R 0x60010fe8 0xcb265158 word @@ -153,22 +165,24 @@ R 0x60010ff0 0x88e5f660 word R 0x60010ff4 0x96ee3bc5 word R 0x60010ff8 0x96cf9939 word R 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0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0x0b51e243 word R 0x60010fe4 0x37b05a4b word R 0x60010fe8 0x02497784 word @@ -177,22 +191,24 @@ R 0x60010ff0 0x7f6590f6 word R 0x60010ff4 0x479570fd word R 0x60010ff8 0xae0cb755 word R 0x60010ffc 0xee161bc2 word -W 0x600107c0 0xec8225d7 word -W 0x600107c4 0x9193267a word -W 0x600107c8 0xc3f24d94 word -W 0x600107cc 0xb295566e word -W 0x600107d0 0x034a0bc0 word -W 0x600107d4 0x1a4d2e6b word -W 0x600107d8 0xa6ed70c9 word -W 0x600107dc 0x4d573f76 word -W 0x600107e0 0x45b0e216 word -W 0x600107e4 0xdb750cbb word -W 0x600107e8 0x4138b929 word -W 0x600107ec 0xd67d1bbd word -W 0x600107f0 0x24fdf316 word -W 0x600107f4 0x0650c084 word -W 0x600107f8 0xf95e6e9c word -W 0x600107fc 0x877e2642 word +W 0x60010780 0xec8225d7 word +W 0x60010784 0x9193267a word +W 0x60010788 0xc3f24d94 word +W 0x6001078c 0xb295566e word +W 0x60010790 0x034a0bc0 word +W 0x60010794 0x1a4d2e6b word +W 0x60010798 0xa6ed70c9 word +W 0x6001079c 0x4d573f76 word +W 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word +W 0x60010780 0x387dc590 word +W 0x60010784 0x2966f6a3 word +W 0x60010788 0xadd14662 word +W 0x6001078c 0x0bc2175e word +W 0x60010790 0x3d2556a0 word +W 0x60010794 0x335c30a8 word +W 0x60010798 0x50e7e900 word +W 0x6001079c 0xb1b72206 word +W 0x600107a0 0xc6f526b0 word +W 0x600107a4 0x15a4177f word +W 0x600107a8 0xf0d718a4 word +W 0x600107ac 0x48879677 word +W 0x600107b0 0x8934d6c4 word +W 0x600107b4 0x50ab7c39 word +W 0x600107b8 0x3360bbd7 word +W 0x600107bc 0xefdf5963 word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0x24eb65ee word R 0x60010fe4 0x309707c9 word R 0x60010fe8 0xaf5d19d2 word @@ -225,22 +243,24 @@ R 0x60010ff0 0x5d160f7a word R 0x60010ff4 0x400e3734 word R 0x60010ff8 0xb6a8cf6c word R 0x60010ffc 0x3a012531 word -W 0x600107c0 0x2a22cd0b word -W 0x600107c4 0xf570eb78 word -W 0x600107c8 0xd3a5b873 word -W 0x600107cc 0x53d7f89b word -W 0x600107d0 0xebedc242 word -W 0x600107d4 0x59a1ee9a word -W 0x600107d8 0xcea792f4 word -W 0x600107dc 0xedf99c9c word -W 0x600107e0 0x47ab7368 word -W 0x600107e4 0xa0eddacc word -W 0x600107e8 0xe218002f word -W 0x600107ec 0x1498319a word -W 0x600107f0 0xb1f10e58 word -W 0x600107f4 0x8d03ecb0 word -W 0x600107f8 0x4408ab12 word -W 0x600107fc 0xcabcc637 word +W 0x60010780 0x2a22cd0b word +W 0x60010784 0xf570eb78 word +W 0x60010788 0xd3a5b873 word +W 0x6001078c 0x53d7f89b word +W 0x60010790 0xebedc242 word +W 0x60010794 0x59a1ee9a word +W 0x60010798 0xcea792f4 word +W 0x6001079c 0xedf99c9c word +W 0x600107a0 0x47ab7368 word +W 0x600107a4 0xa0eddacc word +W 0x600107a8 0xe218002f word +W 0x600107ac 0x1498319a word +W 0x600107b0 0xb1f10e58 word +W 0x600107b4 0x8d03ecb0 word +W 0x600107b8 0x4408ab12 word +W 0x600107bc 0xcabcc637 word +W 0x600107c0 0x00000200 word +W 0x600107fc 0x80000000 word R 0x60010fe0 0x5951566a word R 0x60010fe4 0xb8a4b430 word R 0x60010fe8 0x9fe9980d word diff --git a/wrapper/stimulus/ahb_input_hash_stim.m2d b/wrapper/stimulus/ahb_input_hash_stim.m2d index 9d782b3..0a4fb32 100644 --- a/wrapper/stimulus/ahb_input_hash_stim.m2d +++ b/wrapper/stimulus/ahb_input_hash_stim.m2d @@ -1,83 +1,93 @@ 0044000c -600107c0 +60010780 00000000 94748770 00440001 -600107c4 +60010784 0e3109cc 00000000 00440001 -600107c8 +60010788 00000000 c4411b41 00440001 -600107cc +6001078c 5349fe99 00000000 00440001 -600107d0 +60010790 00000000 bc3bdfc1 00440001 -600107d4 +60010794 deb5cb2a 00000000 00440001 -600107d8 +60010798 00000000 a0052ca2 00440001 -600107dc +6001079c 1761b000 00000000 00440001 -600107e0 +600107a0 00000000 1b5affff 00440001 -600107e4 +600107a4 eab53b7e 00000000 00440001 -600107e8 +600107a8 00000000 81152f06 00440001 -600107ec +600107ac 7d60ab33 00000000 00440001 -600107f0 +600107b0 00000000 1ce3c906 00440001 -600107f4 +600107b4 707476fe 00000000 00440001 -600107f8 +600107b8 00000000 923737f4 00440001 -600107fc +600107bc 695b2443 00000000 +00440001 +600107c0 +00000000 +00000200 + +00440001 +600107fc +80000000 +00000000 + 10440001 60010fe0 00000000 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-600107fc +600107bc cabcc637 00000000 +00440001 +600107c0 +00000000 +00000200 + +00440001 +600107fc +80000000 +00000000 + 10440001 60010fe0 00000000 diff --git a/wrapper/stimulus/input_block_32bit_stim.csv b/wrapper/stimulus/input_block_32bit_stim.csv new file mode 100644 index 0000000..3d6bce9 --- /dev/null +++ b/wrapper/stimulus/input_block_32bit_stim.csv @@ -0,0 +1,320 @@ +94748770,0,0 +0e3109cc,0,0 +c4411b41,0,0 +5349fe99,0,0 +bc3bdfc1,0,0 +deb5cb2a,0,0 +a0052ca2,0,0 +1761b000,0,0 +1b5affff,0,0 +eab53b7e,0,0 +81152f06,0,0 +7d60ab33,0,0 +1ce3c906,0,0 +707476fe,0,0 +923737f4,0,0 +695b2443,1,0 +00000200,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +00000000,0,1 +80000000,1,1 +f7079da3,0,0 +a0c46731,0,0 +c51f9e09,0,0 +8d8993e6,0,0 +fd33039d,0,0 +e8675d4a,0,0 +c0e513a1,0,0 +858c0663,0,0 +a1fb693e,0,0 +d5ebd6d4,0,0 +26f7441f,0,0 +907554b5,0,0 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+60f9e31b,1,1 +24eb65ee,0,1 +309707c9,0,1 +af5d19d2,0,1 +d4e713d3,0,1 +5d160f7a,0,1 +400e3734,0,1 +b6a8cf6c,0,1 +3a012531,1,1 +5951566a,0,1 +b8a4b430,0,1 +9fe9980d,0,1 +80069d04,0,1 +93d866f ,0,1 +7af5e3f6,0,1 +cc432473,0,1 +90f1978 ,1,1 diff --git a/wrapper/verif/tb_wrapper_secworks_sha256.sv b/wrapper/verif/tb_wrapper_secworks_sha256.sv new file mode 100644 index 0000000..37d7343 --- /dev/null +++ b/wrapper/verif/tb_wrapper_secworks_sha256.sv @@ -0,0 +1,263 @@ +//----------------------------------------------------------------------------- +// SoC Labs Basic Testbench for Top-level AHB Wrapper +// Modified from tb_frbm_example.v +// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright 2023; SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from Arm Limited or its affiliates. +// +// (C) COPYRIGHT 2010-2011,2017 Arm Limited or its affiliates. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from Arm Limited or its affiliates. +// +// SVN Information +// +// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $ +// +// Revision : $Revision: 371321 $ +// +// Release Information : Cortex-M System Design Kit-r1p1-00rel0 +// +//----------------------------------------------------------------------------- +//------------------------------------------------------------------------- +// Abstract : Example for File Reader Bus Master +// Testbench for the example AHB Lite slave. +//=========================================================================-- +// `include "wrapper_secworks_sha256.sv" + +`timescale 1ns/1ps + +import "DPI-C" function string getenv(input string env_name); + +module tb_wrapper_secworks_sha256; + +parameter CLK_PERIOD = 10; +parameter ADDRWIDTH = 12; + +parameter InputFileName = ("/home/dam1n19/Design/secworks-sha-256-system-top/wrapper/stimulus/ahb_input_hash_stim.m2d"); +parameter MessageTag = "FileReader:"; +parameter StimArraySize = 10000; + + +//******************************************************************************** +// Internal Wires +//******************************************************************************** + +// AHB Lite BUS SIGNALS +wire hready; +wire hresp; +wire [31:0] hrdata; + +wire [1:0] htrans; +wire [2:0] hburst; +wire [3:0] hprot; +wire [2:0] hsize; +wire hwrite; +wire hmastlock; +wire [31:0] haddr; +wire [31:0] hwdata; + +// Accelerator AHB Signals +wire hsel0; +wire hreadyout0; +wire hresp0; +wire [31:0] hrdata0; + +// Default Slave AHB Signals +wire hsel1; +wire hreadyout1; +wire hresp1; +wire [31:0] hrdata1; + +reg HCLK; +reg HRESETn; + +//******************************************************************************** +// Clock and reset generation +//******************************************************************************** + + initial begin + $write("env = %s\n", getenv("PWD")); + end + +initial + begin + $dumpfile("wrapper_secworks_sha256.vcd"); + $dumpvars(0, tb_wrapper_secworks_sha256); + HRESETn = 1'b0; + HCLK = 1'b0; + # (10*CLK_PERIOD); + HRESETn = 1'b1; + end + +always + begin + HCLK = #(CLK_PERIOD/2) ~HCLK; + end + + +//******************************************************************************** +// Address decoder, need to be changed for other configuration +//******************************************************************************** +// 0x60010000 - 0x60010FFF : HSEL #0 - Hash Accelerator +// Other addresses : HSEL #1 - Default slave + + assign hsel0 = (haddr[31:12] == 20'h60010)? 1'b1:1'b0; + assign hsel1 = hsel0 ? 1'b0:1'b1; + +//******************************************************************************** +// File read bus master: +// generate AHB Master signal by reading a file which store the AHB Operations +//******************************************************************************** + +cmsdk_ahb_fileread_master32 #(InputFileName, + MessageTag, + StimArraySize +) u_ahb_fileread_master32 ( + .HCLK (HCLK), + .HRESETn (HRESETn), + + .HREADY (hready), + .HRESP ({hresp}), //AHB Lite response to AHB response + .HRDATA (hrdata), + .EXRESP (1'b0), // Exclusive response (tie low if not used) + + + .HTRANS (htrans), + .HBURST (hburst), + .HPROT (hprot), + .EXREQ (), // Exclusive access request (not used) + .MEMATTR (), // Memory attribute (not used) + .HSIZE (hsize), + .HWRITE (hwrite), + .HMASTLOCK (hmastlock), + .HADDR (haddr), + .HWDATA (hwdata), + + .LINENUM () + + ); + + +//******************************************************************************** +// Slave multiplexer module: +// multiplex the slave signals to master, two ports are enabled +//******************************************************************************** + + cmsdk_ahb_slave_mux #( + 1, //PORT0_ENABLE + 1, //PORT1_ENABLE + 0, //PORT2_ENABLE + 0, //PORT3_ENABLE + 0, //PORT4_ENABLE + 0, //PORT5_ENABLE + 0, //PORT6_ENABLE + 0, //PORT7_ENABLE + 0, //PORT8_ENABLE + 0 //PORT9_ENABLE + ) u_ahb_slave_mux ( + .HCLK (HCLK), + .HRESETn (HRESETn), + .HREADY (hready), + .HSEL0 (hsel0), // Input Port 0 + .HREADYOUT0 (hreadyout0), + .HRESP0 (hresp0), + .HRDATA0 (hrdata0), + .HSEL1 (hsel1), // Input Port 1 + .HREADYOUT1 (hreadyout1), + .HRESP1 (hresp1), + .HRDATA1 (hrdata1), + .HSEL2 (1'b0), // Input Port 2 + .HREADYOUT2 (), + .HRESP2 (), + .HRDATA2 (), + .HSEL3 (1'b0), // Input Port 3 + .HREADYOUT3 (), + .HRESP3 (), + .HRDATA3 (), + .HSEL4 (1'b0), // Input Port 4 + .HREADYOUT4 (), + .HRESP4 (), + .HRDATA4 (), + .HSEL5 (1'b0), // Input Port 5 + .HREADYOUT5 (), + .HRESP5 (), + .HRDATA5 (), + .HSEL6 (1'b0), // Input Port 6 + .HREADYOUT6 (), + .HRESP6 (), + .HRDATA6 (), + .HSEL7 (1'b0), // Input Port 7 + .HREADYOUT7 (), + .HRESP7 (), + .HRDATA7 (), + .HSEL8 (1'b0), // Input Port 8 + .HREADYOUT8 (), + .HRESP8 (), + .HRDATA8 (), + .HSEL9 (1'b0), // Input Port 9 + .HREADYOUT9 (), + .HRESP9 (), + .HRDATA9 (), + + .HREADYOUT (hready), // Outputs + .HRESP (hresp), + .HRDATA (hrdata) + ); + + +//******************************************************************************** +// Slave module 1: example AHB slave module +//******************************************************************************** + wrapper_secworks_sha256 #(ADDRWIDTH + ) accelerator ( + .HCLK (HCLK), + .HRESETn (HRESETn), + + // Input slave port: 32 bit data bus interface + .HSELS (hsel0), + .HADDRS (haddr[ADDRWIDTH-1:0]), + .HTRANSS (htrans), + .HSIZES (hsize), + .HWRITES (hwrite), + .HREADYS (hready), + .HWDATAS (hwdata), + + .HREADYOUTS (hreadyout0), + .HRESPS (hresp0), + .HRDATAS (hrdata0), + + // Input Data Request to DMAC + .in_data_req (), + .out_data_req () + ); + + +//******************************************************************************** +// Slave module 2: AHB default slave module +//******************************************************************************** + cmsdk_ahb_default_slave u_ahb_default_slave( + .HCLK (HCLK), + .HRESETn (HRESETn), + .HSEL (hsel1), + .HTRANS (htrans), + .HREADY (hready), + .HREADYOUT (hreadyout1), + .HRESP (hresp1) + ); + + assign hrdata1 = {32{1'b0}}; // Default slave don't have data + + endmodule \ No newline at end of file -- GitLab