diff --git a/flist/mem/fpga_mem.flist b/flist/mem/fpga_mem.flist
index 75aeb75736b7372825f3b4e7dbc86806ef6b14d0..d45130c518c4050b7ab01fb0285d61256a24fef9 100644
--- a/flist/mem/fpga_mem.flist
+++ b/flist/mem/fpga_mem.flist
@@ -19,4 +19,5 @@
// +incdir+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/
// - Top-level testbench
-$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
\ No newline at end of file
+$(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v
+$(SOCLABS_FPGA_LIB_TECH_DIR)/rom/verilog/sl_ahb_rom.v
\ No newline at end of file
diff --git a/flist/project/accelerator.flist b/flist/project/accelerator.flist
index a9d3db2dc3a46ea5ef527b4cfe2415f01681e1a4..1b868a80e535823f92187eab3ca9dd3f2703a216 100644
--- a/flist/project/accelerator.flist
+++ b/flist/project/accelerator.flist
@@ -12,3 +12,6 @@
+libext+.v+.vlib
// ============= Accelerator Module search path =============
++incdir+$(ACCELERATOR_DIR)/src/rtl
+$(SOCLABS_PROJECT_DIR)/system/src/accelerator_subsystem.v
+$(SOCLABS_PROJECT_DIR)/wrapper/src/soclabs_ahb_aes128_ctrl.v
\ No newline at end of file
diff --git a/flist/project/system.flist b/flist/project/system.flist
index c70ea933b3b331539fb21e89c5ae7e94e41c2231..c03340d6a1fa03cb3f6974698638ed375537ace4 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -14,7 +14,7 @@
// ============= Accelerator Module search path =============
// ! Point this to your accelerator filelist
-// -f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
// ============= Wrapper Filelist =========================
-f $(SOCLABS_PROJECT_DIR)/flist/project/wrapper.flist
diff --git a/nanosoc_tech b/nanosoc_tech
index a2e3324d42d4cad8725c3ea746119cccc094dbcf..9408699b35a7fe343821afdb8cb164754ed80dda 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit a2e3324d42d4cad8725c3ea746119cccc094dbcf
+Subproject commit 9408699b35a7fe343821afdb8cb164754ed80dda
diff --git a/proj-branch b/proj-branch
index ca916d0be495c2ed26cf397ab50d4bd826ae27b0..4c11f8f514ed0921118dff6ef3303e15165059de 100644
--- a/proj-branch
+++ b/proj-branch
@@ -11,7 +11,8 @@
# Each Repo needs to have its branch set manually in here - they will defaultly be checked out to main
# Project Repository Subrepository Branch Index
# Add your Accelerator Repository here
-# accelerator_repo: main
+secworks-aes: master
+
nanosoc_tech: feat_nanosoc_regions
nanosoc_tech/system/slcorem0_tech: main
nanosoc_tech/system/sldma230_tech: main
@@ -21,5 +22,4 @@ fpga_lib_tech: main
generic_lib_tech: main
rtl_primitives_tech: main
soctools_flow: main
-soctools_flow/tools/chipkit_flow: main
-secworks-aes: master
\ No newline at end of file
+soctools_flow/tools/chipkit_flow: main
\ No newline at end of file
diff --git a/simulate/socsim/system_secworks_aes128.sh b/simulate/socsim/system_secworks_aes128.sh
index 9819cb1df85ada4cb5d8a1a6e08e8f5d3171807a..1bfacd413d1a7326dee7254953312d535c2a755a 100755
--- a/simulate/socsim/system_secworks_aes128.sh
+++ b/simulate/socsim/system_secworks_aes128.sh
@@ -24,7 +24,8 @@ cd $SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
# Compile Simulation
# Call makefile in NanoSoC Repo with options
echo ${2}
-make -C $SOCLABS_NANOSOC_TECH_DIR run_xm \
+make -C $SOCLABS_NANOSOC_TECH_DIR run_mti \
SIM_DIR=$SIM_DIR \
+ ACCELERATOR=yes \
${@:2}
diff --git a/system/src/accelerator_subsystem.v b/system/src/accelerator_subsystem.v
new file mode 100644
index 0000000000000000000000000000000000000000..a6e56906f67f942a378fafa80508e19e3fcb6730
--- /dev/null
+++ b/system/src/accelerator_subsystem.v
@@ -0,0 +1,74 @@
+//-----------------------------------------------------------------------------
+// SoC Labs Basic Example Accelerator Wrapper
+// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2023; SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module accelerator_subsystem #(
+ parameter SYS_ADDR_W=32,
+ parameter SYS_DATA_W=32,
+ parameter AHBADDRWIDTH=16,
+ parameter INPACKETWIDTH=128,
+ parameter CFGSIZEWIDTH=64,
+ parameter CFGSCHEMEWIDTH=2,
+ parameter OUTPACKETWIDTH=128,
+ parameter CFGNUMIRQ=4
+ ) (
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+
+ // AHB connection to Initiator
+ input wire HSEL,
+ input wire [AHBADDRWIDTH-1:0] HADDR,
+ input wire [1:0] HTRANS,
+ input wire [2:0] HSIZE,
+ input wire [3:0] HPROT,
+ input wire HWRITE,
+ input wire HREADY,
+ input wire [31:0] HWDATA,
+
+ output wire HREADYOUT,
+ output wire HRESP,
+ output wire [31:0] HRDATA,
+
+ // Data Request Signal to DMAC
+ output wire [1:0] EXP_DRQ,
+ input wire [1:0] EXP_DLAST,
+
+ // Interrupts
+ output wire [CFGNUMIRQ-1:0] EXP_IRQ
+
+ );
+
+ soclabs_ahb_aes128_ctrl u_exp_aes128 (
+ .ahb_hclk (HCLK),
+ .ahb_hresetn (HRESETn),
+ .ahb_hsel (HSEL),
+ .ahb_haddr16 (HADDR[15:0]),
+ .ahb_htrans (HTRANS),
+ .ahb_hwrite (HWRITE),
+ .ahb_hsize (HSIZE),
+ .ahb_hprot (HPROT),
+ .ahb_hwdata (HWDATA),
+ .ahb_hready (HREADY),
+ .ahb_hrdata (HRDATA),
+ .ahb_hreadyout (HREADYOUT),
+ .ahb_hresp (HRESP),
+ .drq_ipdma128 (EXP_DRQ[0]),
+ .dlast_ipdma128 (1'b0),
+ .drq_opdma128 (EXP_DRQ[1]),
+ .dlast_opdma128 (1'b0),
+ .irq_key128 (EXP_IRQ[0]),
+ .irq_ip128 (EXP_IRQ[1]),
+ .irq_op128 (EXP_IRQ[2]),
+ .irq_error (EXP_IRQ[3]),
+ .irq_merged ( )
+ );
+
+endmodule
diff --git a/system/src/nanosoc_acc_wrapper.v b/system/src/nanosoc_acc_wrapper.v
deleted file mode 100644
index 860ed3b9b9df1b9ca93f9cfea8f453fe2d0ce561..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_acc_wrapper.v
+++ /dev/null
@@ -1,76 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Example Accelerator Wrapper
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright (C) 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module nanosoc_exp_wrapper #(
- parameter AHBADDRWIDTH=16,
- parameter INPACKETWIDTH=128,
- parameter CFGSIZEWIDTH=64,
- parameter CFGSCHEMEWIDTH=2,
- parameter OUTPACKETWIDTH=128,
- parameter CFGNUMIRQ=4
- ) (
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
-
- // AHB connection to Initiator
- input wire HSEL_i,
- input wire [AHBADDRWIDTH-1:0] HADDR_i,
- input wire [1:0] HTRANS_i,
- input wire [2:0] HSIZE_i,
- input wire [3:0] HPROT_i,
- input wire HWRITE_i,
- input wire HREADY_i,
- input wire [31:0] HWDATA_i,
-
- output wire HREADYOUT_o,
- output wire HRESP_o,
- output wire [31:0] HRDATA_o,
-
- // Input Data Request Signal to DMAC
- output wire exp_drq_ip_o,
- input wire exp_dlast_ip_i,
-
- // Output Data Request Signal to DMAC
- output wire exp_drq_op_o,
- input wire exp_dlast_op_i,
-
- // Interrupts
- output wire [CFGNUMIRQ-1:0] exp_irq_o
-
- );
-
- soclabs_ahb_aes128_ctrl u_exp_aes128 (
- .ahb_hclk (HCLK),
- .ahb_hresetn (HRESETn),
- .ahb_hsel (HSEL_i),
- .ahb_haddr16 (HADDR_i[15:0]),
- .ahb_htrans (HTRANS_i),
- .ahb_hwrite (HWRITE_i),
- .ahb_hsize (HSIZE_i),
- .ahb_hprot (HPROT_i),
- .ahb_hwdata (HWDATA_i),
- .ahb_hready (HREADY_i),
- .ahb_hrdata (HRDATA_o),
- .ahb_hreadyout (HREADYOUT_o),
- .ahb_hresp (HRESP_o),
- .drq_ipdma128 (exp_drq_ip_o),
- .dlast_ipdma128 (1'b0),
- .drq_opdma128 (exp_drq_op_o),
- .dlast_opdma128 (1'b0),
- .irq_key128 (exp_irq_o[0]),
- .irq_ip128 (exp_irq_o[1]),
- .irq_op128 (exp_irq_o[2]),
- .irq_error (exp_irq_o[3]),
- .irq_merged ( )
- );
-
-endmodule
diff --git a/system/src/nanosoc_exp.v b/system/src/nanosoc_exp.v
deleted file mode 100644
index b8794b4d226d02c414918bbd9a26d0b4bd5d108b..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_exp.v
+++ /dev/null
@@ -1,152 +0,0 @@
-//-----------------------------------------------------------------------------
-// Nanosoc Expansion Region AHB Address Region
-// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-//
-// Copyright 2021-3, SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-`include "cmsdk_ahb_default_slave.v"
-`include "cmsdk_ahb_slave_mux.v"
-
-module nanosoc_exp #(
- parameter ADDRWIDTH=29, // Region Address Width
- parameter ACCEL_ADDRWIDTH=12 // Region Address Width
- )(
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
-
- // AHB connection to Initiator
- input wire HSELS,
- input wire [ADDRWIDTH-1:0] HADDRS,
- input wire [1:0] HTRANSS,
- input wire [2:0] HSIZES,
- input wire [3:0] HPROTS,
- input wire HWRITES,
- input wire HREADYS,
- input wire [31:0] HWDATAS,
-
- output wire HREADYOUTS,
- output wire HRESPS,
- output wire [31:0] HRDATAS,
-
- output wire ip_data_req,
- output wire op_data_req
- );
-
-//********************************************************************************
-// Internal Wires
-//********************************************************************************
-
-// Accelerator AHB Signals
-wire HSEL0;
-wire HREADYOUT0;
-wire HRESP0;
-wire [31:0] HRDATA0;
-
-// Default Slave AHB Signals
-wire HSEL1;
-wire HREADYOUT1;
-wire HRESP1;
-wire [31:0] HRDATA1;
-
-//********************************************************************************
-// Address decoder, need to be changed for other configuration
-//********************************************************************************
-// 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
-// Other addresses : HSEL #1 - Default target
-
- assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
- assign HSEL1 = HSEL0 ? 1'b0:1'b1;
-
-//********************************************************************************
-// Slave multiplexer module:
-// multiplex the target signals to master, three ports are enabled
-//********************************************************************************
-
-cmsdk_ahb_slave_mux #(
- 1, //PORT0_ENABLE
- 1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
- 0, //PORT3_ENABLE
- 0, //PORT4_ENABLE
- 0, //PORT5_ENABLE
- 0, //PORT6_ENABLE
- 0, //PORT7_ENABLE
- 0, //PORT8_ENABLE
- 0 //PORT9_ENABLE
- ) u_ahb_slave_mux (
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HREADY (HREADYS),
- .HSEL0 (HSEL0), // Input Port 0
- .HREADYOUT0 (HREADYOUT0),
- .HRESP0 (HRESP0),
- .HRDATA0 (HRDATA0),
- .HSEL1 (HSEL1), // Input Port 1
- .HREADYOUT1 (HREADYOUT1),
- .HRESP1 (HRESP1),
- .HRDATA1 (HRDATA1),
- .HSEL2 (1'b0), // Input Port 2
- .HREADYOUT2 (),
- .HRESP2 (),
- .HRDATA2 (),
- .HSEL3 (1'b0), // Input Port 3
- .HREADYOUT3 (),
- .HRESP3 (),
- .HRDATA3 (),
- .HSEL4 (1'b0), // Input Port 4
- .HREADYOUT4 (),
- .HRESP4 (),
- .HRDATA4 (),
- .HSEL5 (1'b0), // Input Port 5
- .HREADYOUT5 (),
- .HRESP5 (),
- .HRDATA5 (),
- .HSEL6 (1'b0), // Input Port 6
- .HREADYOUT6 (),
- .HRESP6 (),
- .HRDATA6 (),
- .HSEL7 (1'b0), // Input Port 7
- .HREADYOUT7 (),
- .HRESP7 (),
- .HRDATA7 (),
- .HSEL8 (1'b0), // Input Port 8
- .HREADYOUT8 (),
- .HRESP8 (),
- .HRDATA8 (),
- .HSEL9 (1'b0), // Input Port 9
- .HREADYOUT9 (),
- .HRESP9 (),
- .HRDATA9 (),
-
- .HREADYOUT (HREADYOUTS), // Outputs
- .HRESP (HRESPS),
- .HRDATA (HRDATAS)
- );
-
-
-//********************************************************************************
-// Slave module 1: Accelerator AHB target module
-//********************************************************************************
-
-// Instantiate your accelerator wrapper HERE
-
-//********************************************************************************
-// Slave module 2: AHB default target module
-//********************************************************************************
- cmsdk_ahb_default_slave u_ahb_default_slave(
- .HCLK (HCLK),
- .HRESETn (HRESETn),
- .HSEL (HSEL1),
- .HTRANS (HTRANSS),
- .HREADY (HREADYS),
- .HREADYOUT (HREADYOUT1),
- .HRESP (HRESP1)
- );
-
- assign HRDATA1 = {32{1'b0}}; // Default target don't have data
-
-endmodule
diff --git a/system/src/nanosoc_exp_wrapper.v b/system/src/nanosoc_exp_wrapper.v
deleted file mode 100644
index 860ed3b9b9df1b9ca93f9cfea8f453fe2d0ce561..0000000000000000000000000000000000000000
--- a/system/src/nanosoc_exp_wrapper.v
+++ /dev/null
@@ -1,76 +0,0 @@
-//-----------------------------------------------------------------------------
-// SoC Labs Basic Example Accelerator Wrapper
-// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
-//
-// Contributors
-//
-// David Mapstone (d.a.mapstone@soton.ac.uk)
-// David Flynn (d.w.flynn@soton.ac.uk)
-//
-// Copyright (C) 2023; SoC Labs (www.soclabs.org)
-//-----------------------------------------------------------------------------
-
-module nanosoc_exp_wrapper #(
- parameter AHBADDRWIDTH=16,
- parameter INPACKETWIDTH=128,
- parameter CFGSIZEWIDTH=64,
- parameter CFGSCHEMEWIDTH=2,
- parameter OUTPACKETWIDTH=128,
- parameter CFGNUMIRQ=4
- ) (
- input wire HCLK, // Clock
- input wire HRESETn, // Reset
-
- // AHB connection to Initiator
- input wire HSEL_i,
- input wire [AHBADDRWIDTH-1:0] HADDR_i,
- input wire [1:0] HTRANS_i,
- input wire [2:0] HSIZE_i,
- input wire [3:0] HPROT_i,
- input wire HWRITE_i,
- input wire HREADY_i,
- input wire [31:0] HWDATA_i,
-
- output wire HREADYOUT_o,
- output wire HRESP_o,
- output wire [31:0] HRDATA_o,
-
- // Input Data Request Signal to DMAC
- output wire exp_drq_ip_o,
- input wire exp_dlast_ip_i,
-
- // Output Data Request Signal to DMAC
- output wire exp_drq_op_o,
- input wire exp_dlast_op_i,
-
- // Interrupts
- output wire [CFGNUMIRQ-1:0] exp_irq_o
-
- );
-
- soclabs_ahb_aes128_ctrl u_exp_aes128 (
- .ahb_hclk (HCLK),
- .ahb_hresetn (HRESETn),
- .ahb_hsel (HSEL_i),
- .ahb_haddr16 (HADDR_i[15:0]),
- .ahb_htrans (HTRANS_i),
- .ahb_hwrite (HWRITE_i),
- .ahb_hsize (HSIZE_i),
- .ahb_hprot (HPROT_i),
- .ahb_hwdata (HWDATA_i),
- .ahb_hready (HREADY_i),
- .ahb_hrdata (HRDATA_o),
- .ahb_hreadyout (HREADYOUT_o),
- .ahb_hresp (HRESP_o),
- .drq_ipdma128 (exp_drq_ip_o),
- .dlast_ipdma128 (1'b0),
- .drq_opdma128 (exp_drq_op_o),
- .dlast_opdma128 (1'b0),
- .irq_key128 (exp_irq_o[0]),
- .irq_ip128 (exp_irq_o[1]),
- .irq_op128 (exp_irq_o[2]),
- .irq_error (exp_irq_o[3]),
- .irq_merged ( )
- );
-
-endmodule