diff --git a/.gitmodules b/.gitmodules
index 13b71911fb8c3c24c823283f1f5ced0ef868b54d..85fb57afa1284abf83b913add0ae9423289d5dda 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -10,3 +10,6 @@
[submodule "socsim"]
path = socsim
url = git@git.soton.ac.uk:soclabs/socsim.git
+[submodule "CHIPKIT"]
+ path = CHIPKIT
+ url = git@git.soton.ac.uk:soclabs/CHIPKIT.git
diff --git a/CHIPKIT b/CHIPKIT
new file mode 160000
index 0000000000000000000000000000000000000000..2435cd9df8ff8a7e7d2e289b4e646eed10882e27
--- /dev/null
+++ b/CHIPKIT
@@ -0,0 +1 @@
+Subproject commit 2435cd9df8ff8a7e7d2e289b4e646eed10882e27
diff --git a/accelerator-wrapper b/accelerator-wrapper
index 031c516e3aded99b3fe63311f1500bb751705c27..b29111dad3d10ea9499f63f39ba8536b21f51355 160000
--- a/accelerator-wrapper
+++ b/accelerator-wrapper
@@ -1 +1 @@
-Subproject commit 031c516e3aded99b3fe63311f1500bb751705c27
+Subproject commit b29111dad3d10ea9499f63f39ba8536b21f51355
diff --git a/flist/system.flist b/flist/system.flist
new file mode 100644
index 0000000000000000000000000000000000000000..968aee3c957bdd2acf3394f73a04ee9ae760824b
--- /dev/null
+++ b/flist/system.flist
@@ -0,0 +1,22 @@
+//-----------------------------------------------------------------------------
+// Accelerator System Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for Top-level Accelerator System
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= Accelerator Module search path =============
+-y $(SOC_TOP_DIR)/system/src/
++incdir+$(SOC_TOP_DIR)/system/src/
+
+$(SOC_TOP_DIR)/system/src/nanosoc_exp.v
\ No newline at end of file
diff --git a/flow/adp_verify.py b/flow/adp_verify.py
new file mode 100644
index 0000000000000000000000000000000000000000..f2122bae70d9187cba8be3ad501657860cc2e868
--- /dev/null
+++ b/flow/adp_verify.py
@@ -0,0 +1,95 @@
+#-----------------------------------------------------------------------------
+# ADP Command File Verification Script
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright � 2021-3, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+class address_region():
+ def __init__(self, base, size):
+ self.base = base
+ self.size = size
+ self.end = base + size - 4
+
+class read_word():
+ def __init__(self, index, region, address, read_data = 0,exp_data = 0):
+ self.index = index
+ self.region = region
+ self.address = int(str(address), 16)
+ self.read_data = int(str(read_data), 16)
+ self.exp_data = int(str(exp_data), 16)
+
+ def validate(self):
+ if (self.address >= self.region.base and self.address <= self.region.end):
+ return True
+ else:
+ return False
+
+ def check_address(self, address):
+ # print(f"self: {hex(self.address)} test: {address}")
+ if (self.address == int(str(address), 16)):
+ return True
+ else:
+ return False
+
+ def set_read_data(self, read_data):
+ self.read_data = int(read_data, 16)
+
+ def set_exp_data(self, exp_data):
+ self.exp_data = int(exp_data, 16)
+
+ def verify(self):
+ assert (self.read_data == self.exp_data)
+
+def adp_verify(adp_input, adp_output, out_log):
+ # Create Input Region for Accelerator
+ accel_input_port = address_region(base = 0x6001_0000, size = 0x0000_0800)
+ accel_output_port = address_region(base = 0x6001_0800, size = 0x0000_0800)
+
+ word_list = []
+ temp_address_buf = 0x0
+
+ # Read in adp input
+ adp_input_lines = open(adp_input, "r").readlines()
+ idx = 0
+ for line in adp_input_lines:
+ line_split = str(line).split()
+ if len(line_split) > 1:
+ if line_split[0].lower() == "a":
+ # Capture Address
+ temp_address_buf = line_split[1]
+ if line_split[0].lower() == "r":
+ temp_read_word = read_word(idx, accel_output_port, temp_address_buf, exp_data = line_split[1])
+ if temp_read_word.validate():
+ word_list.append(temp_read_word)
+ idx += 1
+
+ # Read in adp output
+ adp_output_lines = open(adp_output, "r").readlines()
+ idx = 0
+ temp_address_buf = 0x0
+ for line in adp_output_lines:
+ line_split = str(line).split()
+ if len(line_split) > 1:
+ if line_split[0] == "]A":
+ # Capture Address
+ temp_address_buf = line_split[1]
+ if line_split[0] == "]R":
+ if word_list[idx].check_address(temp_address_buf):
+ word_list[idx].set_read_data(line_split[1])
+ idx += 1
+
+ # Perform Verification
+ for word in word_list:
+ word.verify()
+ print(f"Tests Passed on {len(word_list)} reads")
+
+if __name__ == "__main__":
+ adp_input = "ft1248_ip.log"
+ adp_output = "ft1248_op.log"
+ output_log = "verify.log"
+ adp_verify(adp_input,adp_output,output_log)
diff --git a/nanosoc b/nanosoc
index 5843789d5155903a0868741a33cf016875831b27..20e2a3d1520f66949bee7efad07e4b61aa3741a0 160000
--- a/nanosoc
+++ b/nanosoc
@@ -1 +1 @@
-Subproject commit 5843789d5155903a0868741a33cf016875831b27
+Subproject commit 20e2a3d1520f66949bee7efad07e4b61aa3741a0
diff --git a/set_env.sh b/set_env.sh
index 8d0c2c3100aed43376ccc385b87d5b5234a798a1..6fa88ed6111e5803651a93d9966076f0300982f9 100755
--- a/set_env.sh
+++ b/set_env.sh
@@ -36,7 +36,7 @@ else
# Source environment variables for all submodules
for d in $SOC_TOP_DIR/* ; do
- if [ -f "$d/.git" ]; then
+ if [ -e "$d/.git" ]; then
if [ -f "$d/set_env.sh" ]; then
# If .git file exists - submodule
source $d/set_env.sh
diff --git a/sha-2-accelerator b/sha-2-accelerator
index 1dd9a82ce6170d363933240053894e8f84928e55..bbd478b94f719df99ade719c546cfad52dd24e40 160000
--- a/sha-2-accelerator
+++ b/sha-2-accelerator
@@ -1 +1 @@
-Subproject commit 1dd9a82ce6170d363933240053894e8f84928e55
+Subproject commit bbd478b94f719df99ade719c546cfad52dd24e40
diff --git a/simulate/socsim/nanosoc_sha256_hashing_stream.sh b/simulate/socsim/nanosoc_sha256_hashing_stream.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c3ce45fef5fd542ff13c83ddeca293bae2836f13
--- /dev/null
+++ b/simulate/socsim/nanosoc_sha256_hashing_stream.sh
@@ -0,0 +1,19 @@
+#-----------------------------------------------------------------------------
+# SoC Labs Cadence Xcelium simulation script for engine testbench
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2022, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+mkdir -p $SOC_TOP_DIR/simulate/sim/
+make run_xm \
+ TESTNAME=hello \
+ ACCELERATOR_VC="-sv -f $ACC_ENGINE_DIR/flist/sha-2-accelerator_src.flist -f $ACC_WRAPPER_DIR/flist/wrapper_ip.flist" \
+ ADP_FILE="$SOC_TOP_DIR/system/stimulus/adp_hash_stim.cmd" \
+ -C $NANOSOC_DIR/Cortex-M0/nanosoc/systems/mcu/rtl_sim
\ No newline at end of file
diff --git a/system/src/nanosoc_exp.v b/system/src/nanosoc_exp.v
new file mode 100644
index 0000000000000000000000000000000000000000..229f7565fe9dd5468a5fc8e3ffd584fe0a033095
--- /dev/null
+++ b/system/src/nanosoc_exp.v
@@ -0,0 +1,166 @@
+//-----------------------------------------------------------------------------
+// Nanosoc Expansion Region AHB Address Region
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+`include "cmsdk_ahb_default_slave.v"
+`include "cmsdk_ahb_slave_mux.v"
+
+module nanosoc_exp #(
+ parameter ADDRWIDTH=29, // Region Address Width
+ parameter ACCEL_ADDRWIDTH=12 // Region Address Width
+ )(
+ input wire HCLK, // Clock
+ input wire HRESETn, // Reset
+
+ // AHB connection to Initiator
+ input wire HSELS,
+ input wire [ADDRWIDTH-1:0] HADDRS,
+ input wire [1:0] HTRANSS,
+ input wire [2:0] HSIZES,
+ input wire HWRITES,
+ input wire HREADYS,
+ input wire [31:0] HWDATAS,
+
+ output wire HREADYOUTS,
+ output wire HRESPS,
+ output wire [31:0] HRDATAS
+ );
+
+//********************************************************************************
+// Internal Wires
+//********************************************************************************
+
+// Accelerator AHB Signals
+wire HSEL0;
+wire HREADYOUT0;
+wire HRESP0;
+wire [31:0] HRDATA0;
+
+// Default Slave AHB Signals
+wire HSEL1;
+wire HREADYOUT1;
+wire HRESP1;
+wire [31:0] HRDATA1;
+
+//********************************************************************************
+// Address decoder, need to be changed for other configuration
+//********************************************************************************
+// 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
+// Other addresses : HSEL #1 - Default target
+
+ assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0;
+ assign HSEL1 = HSEL0 ? 1'b0:1'b1;
+
+//********************************************************************************
+// Slave multiplexer module:
+// multiplex the target signals to master, three ports are enabled
+//********************************************************************************
+
+cmsdk_ahb_slave_mux #(
+ 1, //PORT0_ENABLE
+ 1, //PORT1_ENABLE
+ 1, //PORT2_ENABLE
+ 0, //PORT3_ENABLE
+ 0, //PORT4_ENABLE
+ 0, //PORT5_ENABLE
+ 0, //PORT6_ENABLE
+ 0, //PORT7_ENABLE
+ 0, //PORT8_ENABLE
+ 0 //PORT9_ENABLE
+ ) u_ahb_slave_mux (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HREADY (HREADYS),
+ .HSEL0 (HSEL0), // Input Port 0
+ .HREADYOUT0 (HREADYOUT0),
+ .HRESP0 (HRESP0),
+ .HRDATA0 (HRDATA0),
+ .HSEL1 (HSEL1), // Input Port 1
+ .HREADYOUT1 (HREADYOUT1),
+ .HRESP1 (HRESP1),
+ .HRDATA1 (HRDATA1),
+ .HSEL2 (1'b0), // Input Port 2
+ .HREADYOUT2 (),
+ .HRESP2 (),
+ .HRDATA2 (),
+ .HSEL3 (1'b0), // Input Port 3
+ .HREADYOUT3 (),
+ .HRESP3 (),
+ .HRDATA3 (),
+ .HSEL4 (1'b0), // Input Port 4
+ .HREADYOUT4 (),
+ .HRESP4 (),
+ .HRDATA4 (),
+ .HSEL5 (1'b0), // Input Port 5
+ .HREADYOUT5 (),
+ .HRESP5 (),
+ .HRDATA5 (),
+ .HSEL6 (1'b0), // Input Port 6
+ .HREADYOUT6 (),
+ .HRESP6 (),
+ .HRDATA6 (),
+ .HSEL7 (1'b0), // Input Port 7
+ .HREADYOUT7 (),
+ .HRESP7 (),
+ .HRDATA7 (),
+ .HSEL8 (1'b0), // Input Port 8
+ .HREADYOUT8 (),
+ .HRESP8 (),
+ .HRDATA8 (),
+ .HSEL9 (1'b0), // Input Port 9
+ .HREADYOUT9 (),
+ .HRESP9 (),
+ .HRDATA9 (),
+
+ .HREADYOUT (HREADYOUTS), // Outputs
+ .HRESP (HRESPS),
+ .HRDATA (HRDATAS)
+ );
+
+
+//********************************************************************************
+// Slave module 1: Accelerator AHB target module
+//********************************************************************************
+ wrapper_sha256_hashing_stream #(ACCEL_ADDRWIDTH
+ ) accelerator (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+
+ // Input target port: 32 bit data bus interface
+ .HSELS (HSEL0),
+ .HADDRS (HADDRS[ACCEL_ADDRWIDTH-1:0]),
+ .HTRANSS (HTRANSS),
+ .HSIZES (HSIZES),
+ .HWRITES (HWRITES),
+ .HREADYS (HREADYS),
+ .HWDATAS (HWDATAS),
+
+ .HREADYOUTS (HREADYOUT0),
+ .HRESPS (HRESP0),
+ .HRDATAS (HRDATA0)
+
+ );
+
+
+//********************************************************************************
+// Slave module 2: AHB default target module
+//********************************************************************************
+ cmsdk_ahb_default_slave u_ahb_default_slave(
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (HSEL1),
+ .HTRANS (HTRANSS),
+ .HREADY (HREADYS),
+ .HREADYOUT (HREADYOUT1),
+ .HRESP (HRESPS)
+ );
+
+ assign HRDATA1 = {32{1'b0}}; // Default target don't have data
+
+endmodule
diff --git a/wrapper/regs/cregs.csv b/wrapper/regs/cregs.csv
new file mode 100644
index 0000000000000000000000000000000000000000..c68d8e50d14cf0175dfaf88bbf9b0a18bee5b30f
--- /dev/null
+++ b/wrapper/regs/cregs.csv
@@ -0,0 +1,5 @@
+name idx nbits start access test rval desc
+
+# Wrapper Control Register
+accelerator_en 0 32 0 rw 0 0x00000000 Accelerator Enable Register
+accelerator_channel_en 1 32 0 rw 0 0x00000000 Accelerator Channel Enable Register
\ No newline at end of file
diff --git a/wrapper/regs/cregs/CREGS.h b/wrapper/regs/cregs/CREGS.h
new file mode 100644
index 0000000000000000000000000000000000000000..03b467eacbb96e4976e6acf1f83b6ca41610f727
--- /dev/null
+++ b/wrapper/regs/cregs/CREGS.h
@@ -0,0 +1,16 @@
+// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
+#ifndef CREGS_H
+#define CREGS_H
+
+
+typedef struct
+{
+ __IO uint32_t ACCELERATOR_EN; /* Offset: 0x0 (R/W) Accelerator Enable Register */
+ __IO uint32_t ACCELERATOR_CHANNEL_EN; /* Offset: 0x4 (R/W) Accelerator Channel Enable Register */
+} CREGS_TypeDef;
+
+#endif
+
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
diff --git a/wrapper/regs/cregs/cregs.inst.sv b/wrapper/regs/cregs/cregs.inst.sv
new file mode 100644
index 0000000000000000000000000000000000000000..1ad2ed0a83a321531c11248a382bfbff11e8a078
--- /dev/null
+++ b/wrapper/regs/cregs/cregs.inst.sv
@@ -0,0 +1,24 @@
+// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
+// START
+logic [31:0] accelerator_en;
+logic [31:0] accelerator_channel_en;
+
+cregs u_cregs (
+
+// clocks and resets
+.clk(pclk),
+.rstn(presetn),
+
+// Synchronous register interface
+.regbus (cregs.sink),
+
+// reg file signals
+.accelerator_en(accelerator_en[31:0]) /* idx 0 */,
+.accelerator_channel_en(accelerator_channel_en[31:0]) /* idx 1 */
+
+);
+// END
+
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
diff --git a/wrapper/regs/cregs/cregs.md b/wrapper/regs/cregs/cregs.md
new file mode 100644
index 0000000000000000000000000000000000000000..9e3b82cb35ffeb7efa4fc4aff652b15099b6c5a8
--- /dev/null
+++ b/wrapper/regs/cregs/cregs.md
@@ -0,0 +1,15 @@
+// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
+# Programmers Model
+
+## Module: CREGS
+
+| Address Offset | Signal Name | Access | Bit width | Start bit | Description |
+| --- | --- | --- | --- | --- | --- |
+|
+| 0x0 | **ACCELERATOR_EN** | RW | 32 | 0 | Accelerator Enable Register |
+| 0x4 | **ACCELERATOR_CHANNEL_EN** | RW | 32 | 0 | Accelerator Channel Enable Register |
+
+
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
diff --git a/wrapper/regs/cregs/cregs.py b/wrapper/regs/cregs/cregs.py
new file mode 100644
index 0000000000000000000000000000000000000000..de7171d029c45a3c54f1d3bc642e94ae5c8eb5bd
--- /dev/null
+++ b/wrapper/regs/cregs/cregs.py
@@ -0,0 +1,15 @@
+# // VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
+class Cregs(object):
+
+ def __init__(self,base_offset):
+ self.base_offset = base_offset
+
+
+ self.ACCELERATOR_EN = self.base_offset + 0x0 # Accelerator Enable Register
+ self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
+ self.ACCELERATOR_CHANNEL_EN = self.base_offset + 0x4 # Accelerator Channel Enable Register
+
+
+# // VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
diff --git a/wrapper/regs/cregs/cregs.sv b/wrapper/regs/cregs/cregs.sv
new file mode 100644
index 0000000000000000000000000000000000000000..8c1d454e0d75f8fd4a6516ca743defa770529d2c
--- /dev/null
+++ b/wrapper/regs/cregs/cregs.sv
@@ -0,0 +1,138 @@
+// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
+//-----------------------------------------------------------------------------
+// SoC Labs APB register Template
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// VGEN: HEADER
+// Register file contents:
+//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
+//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
+
+
+// VGEN: MODULE NAME
+module cregs (
+
+// clocks and resets
+ input logic clk,
+ input logic rstn,
+
+// APB inteface
+ input logic psel,
+ input logic [ADDRWIDTH:0] paddr,
+ input logic penable,
+ input logic pwrite,
+ input logic [31:0] pwdata,
+
+ output logic [31:0] prdata,
+ output logic pready,
+ output logic pslverr,
+
+// VGEN: INPUTS TO REGS
+
+
+// VGEN: OUTPUTS FROM REGS
+ output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
+ output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
+
+);
+
+//------------------------------------------------------------------------------
+// APB Interface
+//------------------------------------------------------------------------------
+
+logic [ADDRWIDTH-1:0] addr;
+logic read_en;
+logic write_en;
+logic [31:0] wdata;
+logic [31:0] rdata;
+
+// APB interface
+assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
+assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
+
+
+// register read and write signal
+assign addr = paddr;
+assign read_en = psel & (~pwrite); // assert for whole apb read transfer
+assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
+ // It is also possible to change the design to perform the write in the 2nd
+ // APB cycle. E.g.
+ // assign write_en = psel & penable & pwrite;
+ // However, if the design generate waitstate, this expression will result
+ // in write_en being asserted for multiple cycles.
+assign wdata = pwdata;
+assign prdata = rdata;
+
+//------------------------------------------------------------------------------
+// Regsiter write
+//------------------------------------------------------------------------------
+
+// VGEN: REG WRITE
+// idx #0
+logic [31:0] accelerator_en_reg;
+always@(posedge clk or negedge rstn) begin
+ if(~rstn) begin
+ accelerator_en_reg[31:0] <= '0;
+ end else begin
+ if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
+ end
+end
+assign accelerator_en[31:0] = accelerator_en_reg[31:0];
+
+// idx #1
+logic [31:0] accelerator_channel_en_reg;
+always@(posedge clk or negedge rstn) begin
+ if(~rstn) begin
+ accelerator_channel_en_reg[31:0] <= '0;
+ end else begin
+ if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
+ end
+end
+assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
+
+
+
+//------------------------------------------------------------------------------
+// Regsiter read
+//------------------------------------------------------------------------------
+
+
+logic [31:0] rdata_o;
+
+always @*
+begin
+ if (read_en)
+ begin
+ rdata_o[31:0] = 32'h00000000;
+
+ // VGEN: REG READ
+ if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
+ if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
+
+ end
+ else
+ begin
+ rdata_o[31:0] = {32'h00000000};
+ end
+end
+
+assign rdata[31:0] = rdata_o[31:0];
+
+
+//------------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+
+
+
+
+endmodule
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
diff --git a/wrapper/regs/cregs/cregs.sv.bak b/wrapper/regs/cregs/cregs.sv.bak
new file mode 100644
index 0000000000000000000000000000000000000000..d0ca98a27542bd6c55bb388c49d4e712213edec3
--- /dev/null
+++ b/wrapper/regs/cregs/cregs.sv.bak
@@ -0,0 +1,139 @@
+// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
+
+//-----------------------------------------------------------------------------
+// SoC Labs APB register Template
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2023, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+// VGEN: HEADER
+// Register file contents:
+//{'name': 'accelerator_en', 'idx': '0', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Enable Register'}
+//{'name': 'accelerator_channel_en', 'idx': '1', 'nbits': '32', 'start': '0', 'access': 'rw', 'test': '0', 'rval': '0x00000000', 'desc': 'Accelerator Channel Enable Register'}
+
+
+
+// VGEN: MODULE NAME
+module cregs (
+
+// clocks and resets
+ input logic clk,
+ input logic rstn,
+
+// APB inteface
+ input logic psel,
+ input logic [ADDRWIDTH:0] paddr,
+ input logic penable,
+ input logic pwrite,
+ input logic [31:0] pwdata,
+
+ output logic [31:0] prdata,
+ output logic pready,
+ output logic pslverr,
+
+// VGEN: INPUTS TO REGS
+
+
+// VGEN: OUTPUTS FROM REGS
+ output logic [31:0] accelerator_en /* idx #0: Accelerator Enable Register */,
+ output logic [31:0] accelerator_channel_en /* idx #1: Accelerator Channel Enable Register */
+
+);
+
+//------------------------------------------------------------------------------
+// APB Interface
+//------------------------------------------------------------------------------
+
+logic [ADDRWIDTH-1:0] addr;
+logic read_en;
+logic write_en;
+logic [31:0] wdata;
+logic [31:0] rdata;
+
+// APB interface
+assign pready = 1'b1; //always ready. Can be customized to support waitstate if required.
+assign pslverr = 1'b0; //alwyas OKAY. Can be customized to support error response if required.
+
+
+// register read and write signal
+assign addr = paddr;
+assign read_en = psel & (~pwrite); // assert for whole apb read transfer
+assign write_en = psel & (~penable) & pwrite; // assert for 1st cycle of write transfer
+ // It is also possible to change the design to perform the write in the 2nd
+ // APB cycle. E.g.
+ // assign write_en = psel & penable & pwrite;
+ // However, if the design generate waitstate, this expression will result
+ // in write_en being asserted for multiple cycles.
+assign wdata = pwdata;
+assign prdata = rdata;
+
+//------------------------------------------------------------------------------
+// Regsiter write
+//------------------------------------------------------------------------------
+
+// VGEN: REG WRITE
+// idx #0
+logic [31:0] accelerator_en_reg;
+always@(posedge clk or negedge rstn) begin
+ if(~rstn) begin
+ accelerator_en_reg[31:0] <= '0;
+ end else begin
+ if(write_en & (addr[9:2]==8'h0)) accelerator_en_reg[31:0] <= wdata[31:0];
+ end
+end
+assign accelerator_en[31:0] = accelerator_en_reg[31:0];
+
+// idx #1
+logic [31:0] accelerator_channel_en_reg;
+always@(posedge clk or negedge rstn) begin
+ if(~rstn) begin
+ accelerator_channel_en_reg[31:0] <= '0;
+ end else begin
+ if(write_en & (addr[9:2]==8'h1)) accelerator_channel_en_reg[31:0] <= wdata[31:0];
+ end
+end
+assign accelerator_channel_en[31:0] = accelerator_channel_en_reg[31:0];
+
+
+
+//------------------------------------------------------------------------------
+// Regsiter read
+//------------------------------------------------------------------------------
+
+
+logic [31:0] rdata_o;
+
+always @*
+begin
+ if (read_en)
+ begin
+ rdata_o[31:0] = 32'h00000000;
+
+ // VGEN: REG READ
+ if(addr[9:2]==8'h0) if(addr[9:2]==8'h0) rdata_o[31:0] = accelerator_en[31:0]; // idx #0
+ if(addr[9:2]==8'h1) if(addr[9:2]==8'h1) rdata_o[31:0] = accelerator_channel_en[31:0]; // idx #1
+
+ end
+ else
+ begin
+ rdata_o[31:0] = {32'h00000000};
+ end
+end
+
+assign rdata[31:0] = rdata_o[31:0];
+
+
+//------------------------------------------------------------------------------
+//
+//------------------------------------------------------------------------------
+
+
+
+
+endmodule
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:58:58 24/03/2023
+
diff --git a/wrapper/regs/cregs/cregs_test.c b/wrapper/regs/cregs/cregs_test.c
new file mode 100644
index 0000000000000000000000000000000000000000..1e1345d7773956524a5ba397ef41b8a52ff3f2ec
--- /dev/null
+++ b/wrapper/regs/cregs/cregs_test.c
@@ -0,0 +1,36 @@
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
+#include "cregs_test.h"
+
+// This test is intended to check initial (reset) values of registers
+int cregs_initial_value_test(void) {
+ int num_errors=0;
+
+ if (SM2_CREGS->ACCELERATOR_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");}
+ if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");}
+
+
+ return num_errors;
+
+}
+
+// This test is intended to check write read to registers
+int cregs_write_read_test(void) {
+ int num_errors=0;
+
+ SM2_CREGS->ACCELERATOR_EN = 0xFFFFFFFF; // write all-1s
+ if (SM2_CREGS->ACCELERATOR_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-1s
+ SM2_CREGS->ACCELERATOR_EN = 0x0; // clear field
+ if (SM2_CREGS->ACCELERATOR_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_EN");} // check field is all-0s
+ SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0xFFFFFFFF; // write all-1s
+ if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != (0xFFFFFFFF >> (32-32))) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-1s
+ SM2_CREGS->ACCELERATOR_CHANNEL_EN = 0x0; // clear field
+ if (SM2_CREGS->ACCELERATOR_CHANNEL_EN != 0x0) {num_errors += 1; puts("ERROR: ACCELERATOR_CHANNEL_EN");} // check field is all-0s
+
+
+ return num_errors;
+
+}
+
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
diff --git a/wrapper/regs/cregs/cregs_test.h b/wrapper/regs/cregs/cregs_test.h
new file mode 100644
index 0000000000000000000000000000000000000000..eaafa6d2e5aff0be80ce411ad90268044ae87081
--- /dev/null
+++ b/wrapper/regs/cregs/cregs_test.h
@@ -0,0 +1,18 @@
+// VGEN START: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
+#ifndef CREGS_TEST_H
+#define CREGS_TEST_H
+
+
+#include "SM2_CM0.h"
+
+// This test is intended to check initial (reset) values of registers
+int cregs_initial_value_test(void);
+
+// This test is intended to check write and read to registers
+int cregs_write_read_test(void);
+
+#endif
+
+// VGEN END: Autogenerated by /Users/davidmapstone/Documents/SoCLabs/RTL/accelerator-system-top/CHIPKIT/tools/vgen/bin/vgen.py on 10:59:11 24/03/2023
+
diff --git a/wrapper/src/wrapper_sha256_hashing_stream.sv b/wrapper/src/wrapper_sha256_hashing_stream.sv
index 89dd2976a273518111327fbcf63d121def088af0..781e02827c1433af79b4d59f0f968637e25b645d 100644
--- a/wrapper/src/wrapper_sha256_hashing_stream.sv
+++ b/wrapper/src/wrapper_sha256_hashing_stream.sv
@@ -1,5 +1,5 @@
//-----------------------------------------------------------------------------
-// SoC Labs Basic Accelerator Wrapper for Hashing Stream
+// SoC Labs Basic Example Accelerator Wrapper
// A joint work commissioned on behalf of SoC Labs; under Arm Academic Access license.
//
// Contributors
@@ -8,180 +8,307 @@
//
// Copyright 2023; SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// The confidential and proprietary information contained in this file may
-// only be used by a person authorised under and to the extent permitted
-// by a subsisting licensing agreement from Arm Limited or its affiliates.
-//
-// (C) COPYRIGHT 2010-2011 Arm Limited or its affiliates.
-// ALL RIGHTS RESERVED
-//
-// This entire notice must be reproduced on all copies of this file
-// and copies of this file may only be made by a person if such person is
-// permitted to do so under the terms of a subsisting license agreement
-// from Arm Limited or its affiliates.
-//
-// SVN Information
-//
-// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
-//
-// Revision : $Revision: 371321 $
-//
-// Release Information : Cortex-M System Design Kit-r1p1-00rel0
-//
-//-----------------------------------------------------------------------------
-//-----------------------------------------------------------------------------
-// Abstract : AHB-lite example slave, support 4 32-bit register read and write,
-// each register can be accessed by byte, half word or word.
-// The example slave always output ready and OKAY response to the master
-//-----------------------------------------------------------------------------
module wrapper_sha256_hashing_stream #(
- parameter ADDRWIDTH=12
+ parameter AHBADDRWIDTH=12,
+ parameter INPACKETWIDTH=512,
+ parameter CFGSIZEWIDTH=64,
+ parameter CFGSCHEMEWIDTH=2,
+ parameter OUTPACKETWIDTH=256
) (
input logic HCLK, // Clock
input logic HRESETn, // Reset
- // AHB connection to Initiator
- input logic HSELS,
- input logic [ADDRWIDTH-1:0] HADDRS,
- input logic [1:0] HTRANSS,
- input logic [2:0] HSIZES,
- input logic HWRITES,
- input logic HREADYS,
- input logic [31:0] HWDATAS,
-
- output logic HREADYOUTS,
- output logic HRESPS,
- output logic [31:0] HRDATAS
+ // AHB connection to Initiator
+ input logic HSELS,
+ input logic [AHBADDRWIDTH-1:0] HADDRS,
+ input logic [1:0] HTRANSS,
+ input logic [2:0] HSIZES,
+ input logic HWRITES,
+ input logic HREADYS,
+ input logic [31:0] HWDATAS,
+
+ output logic HREADYOUTS,
+ output logic HRESPS,
+ output logic [31:0] HRDATAS,
+
+ //TODO: Add APB Interface
+
+ // Input Data Request Signal to DMAC
+ output logic in_data_req,
+
+ // Output Data Request Signal to DMAC
+ output logic out_data_req
);
- // ----------------------------------------
- // Internal wires declarations
-
- // Register module interface signals
- logic [ADDRWIDTH-1:0] in_buf_addr;
- logic in_buf_read_en;
- logic in_buf_write_en;
- logic [3:0] in_buf_byte_strobe;
- logic [31:0] in_buf_wdata;
- logic [31:0] in_buf_rdata;
-
- // Input Port Wire Declarations
- logic [ADDRWIDTH-2:0] input_addr;
- logic input_read_en;
- logic input_write_en;
- logic [3:0] input_byte_strobe;
- logic [31:0] input_wdata;
- logic [31:0] input_rdata;
- logic input_wready;
- logic input_rready;
-
- // Output Port Wire Declarations
- logic [ADDRWIDTH-2:0] output_addr;
- logic output_read_en;
- logic output_write_en;
- logic [3:0] output_byte_strobe;
- logic [31:0] output_wdata;
- logic [31:0] output_rdata;
- logic output_wready;
- logic output_rready;
-
- // Internal Wiring
- // Input Packet Wires
- logic [511:0] in_packet;
- logic in_packet_last;
- logic in_packet_valid;
- logic in_packet_ready;
-
- // Output Packet Wires
- logic [255:0] out_packet;
- logic out_packet_last;
- logic out_packet_valid;
- logic out_packet_ready;
-
- // Configuration Tie Off
- logic [63:0] cfg_size;
- logic [1:0] cfg_scheme;
- logic cfg_last;
- logic cfg_valid;
- logic cfg_ready;
- assign cfg_size = 64'd512;
- assign cfg_scheme = 2'd0;
- assign cfg_last = 1'b1;
- assign cfg_valid = 1'b1;
+ //**********************************************************
+ // Internal AHB Parameters
+ //**********************************************************
+
+ // Input Port Parameters
+ localparam [AHBADDRWIDTH-1:0] INPORTADDR = 'h000;
+ localparam INPORTAHBADDRWIDTH = AHBADDRWIDTH - 1;
+
+ // Output Port Parameters
+ localparam [AHBADDRWIDTH-1:0] OUTPORTADDR = 'h800;
+ localparam OUTPORTAHBADDRWIDTH = AHBADDRWIDTH - 1;
+
+ localparam OUTPACKETBYTEWIDTH = $clog2(OUTPACKETWIDTH/8); // Number of Bytes in Packet
+ localparam OUTPACKETSPACEWIDTH = OUTPORTAHBADDRWIDTH-OUTPACKETBYTEWIDTH; // Number of Bits to represent all Packets in Address Space
+
+ //**********************************************************
+ // Wrapper AHB Components
+ //**********************************************************
- //-----------------------------------------------------------
- // Module logic start
//----------------------------------------------------------
+ // Internal AHB Decode Logic
+ //----------------------------------------------------------
+
+ // AHB Target 0 - Engine Input Port
+ logic hsel0;
+ logic hreadyout0;
+ logic hresp0;
+ logic [31:0] hrdata0;
+
+ // AHB Target 1 - Engine Output Port
+ logic hsel1;
+ logic hreadyout1;
+ logic hresp1;
+ logic [31:0] hrdata1;
+
+ // AHB Target 2 - Default Target
+ logic hsel2;
+ logic hreadyout2;
+ logic hresp2;
+ logic [31:0] hrdata2;
+
+ // Internal AHB Address Assignment
+ assign hsel0 = ((HADDRS < OUTPORTADDR) && (HADDRS >= INPORTADDR)) ? 1'b1:1'b0; // Input Port Select
+ assign hsel1 = (HADDRS >= OUTPORTADDR) ? 1'b1:1'b0; // Output Port Select
+ assign hsel2 = (hsel0 | hsel1) ? 1'b0:1'b1; // Default Target Select
+
+ // AHB Target Multiplexer
+ cmsdk_ahb_slave_mux #(
+ 1, //PORT0_ENABLE
+ 1, //PORT1_ENABLE
+ 1, //PORT2_ENABLE
+ 0, //PORT3_ENABLE
+ 0, //PORT4_ENABLE
+ 0, //PORT5_ENABLE
+ 0, //PORT6_ENABLE
+ 0, //PORT7_ENABLE
+ 0, //PORT8_ENABLE
+ 0 //PORT9_ENABLE
+ ) u_ahb_slave_mux (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HREADY (HREADYS),
+ .HSEL0 (hsel0), // Input Port 0
+ .HREADYOUT0 (hreadyout0),
+ .HRESP0 (hresp0),
+ .HRDATA0 (hrdata0),
+ .HSEL1 (hsel1), // Input Port 1
+ .HREADYOUT1 (hreadyout1),
+ .HRESP1 (hresp1),
+ .HRDATA1 (hrdata1),
+ .HSEL2 (hsel2), // Input Port 2
+ .HREADYOUT2 (hreadyout2),
+ .HRESP2 (hresp2),
+ .HRDATA2 (hrdata2),
+ .HSEL3 (1'b0), // Input Port 3
+ .HREADYOUT3 (),
+ .HRESP3 (),
+ .HRDATA3 (),
+ .HSEL4 (1'b0), // Input Port 4
+ .HREADYOUT4 (),
+ .HRESP4 (),
+ .HRDATA4 (),
+ .HSEL5 (1'b0), // Input Port 5
+ .HREADYOUT5 (),
+ .HRESP5 (),
+ .HRDATA5 (),
+ .HSEL6 (1'b0), // Input Port 6
+ .HREADYOUT6 (),
+ .HRESP6 (),
+ .HRDATA6 (),
+ .HSEL7 (1'b0), // Input Port 7
+ .HREADYOUT7 (),
+ .HRESP7 (),
+ .HRDATA7 (),
+ .HSEL8 (1'b0), // Input Port 8
+ .HREADYOUT8 (),
+ .HRESP8 (),
+ .HRDATA8 (),
+ .HSEL9 (1'b0), // Input Port 9
+ .HREADYOUT9 (),
+ .HRESP9 (),
+ .HRDATA9 (),
+
+ .HREADYOUT (HREADYOUTS), // Outputs
+ .HRESP (HRESPS),
+ .HRDATA (HRDATAS)
+ );
+
+ //----------------------------------------------------------
+ // Input Port Logic
+ //----------------------------------------------------------
+
+ // Engine Input Port Wire declarations
+ logic [INPACKETWIDTH-1:0] in_packet;
+ logic in_packet_last;
+ logic in_packet_valid;
+ logic in_packet_ready;
- // Interface block to convert AHB transfers to Register transfers to engine input/output channels
- // engine Input/Output Channels
- wrapper_ahb_vr_interface #(
- ADDRWIDTH
- ) u_wrapper_ahb_interface (
+ // Packet Constructor Instantiation
+ wrapper_ahb_packet_constructor #(
+ INPORTAHBADDRWIDTH,
+ INPACKETWIDTH
+ ) u_wrapper_data_input_port (
.hclk (HCLK),
.hresetn (HRESETn),
// Input slave port: 32 bit data bus interface
- .hsels (HSELS),
- .haddrs (HADDRS),
+ .hsels (hsel0),
+ .haddrs (HADDRS[AHBADDRWIDTH-2:0]),
.htranss (HTRANSS),
.hsizes (HSIZES),
.hwrites (HWRITES),
.hreadys (HREADYS),
.hwdatas (HWDATAS),
- .hreadyouts (HREADYOUTS),
- .hresps (HRESPS),
- .hrdatas (HRDATAS),
-
- // Register interface - Accelerator Engine Input
- .input_addr (input_addr),
- .input_read_en (input_read_en),
- .input_write_en (input_write_en),
- .input_byte_strobe (input_byte_strobe),
- .input_wdata (input_wdata),
- .input_rdata (input_rdata),
- .input_wready (input_wready),
- .input_rready (input_rready),
-
- // Register interface - Accelerator Engine Output
- .output_addr (output_addr),
- .output_read_en (output_read_en),
- .output_write_en (output_write_en),
- .output_byte_strobe (output_byte_strobe),
- .output_wdata (output_wdata),
- .output_rdata (output_rdata),
- .output_wready (output_wready),
- .output_rready (output_rready)
+ .hreadyouts (hreadyout0),
+ .hresps (hresp0),
+ .hrdatas (hrdata0),
+
+ // Valid/Ready Interface
+ .packet_data (in_packet),
+ .packet_data_last (in_packet_last),
+ .packet_data_valid (in_packet_valid),
+ .packet_data_ready (in_packet_ready),
+
+ // Input Data Request
+ .data_req (in_data_req)
);
- wrapper_packet_construct #(
- (ADDRWIDTH - 1), // Only half address map allocated to this device
- 512 // Packet Width
- ) u_wrapper_packet_construct (
+ //----------------------------------------------------------
+ // Configuration Port Logic
+ //----------------------------------------------------------
+
+ // Engine Configuration Port Wire declarations
+ logic [CFGSIZEWIDTH-1:0] cfg_size;
+ logic [CFGSCHEMEWIDTH-1:0] cfg_scheme;
+ logic cfg_last;
+ logic cfg_valid;
+ logic cfg_ready;
+
+ // Engine Configuration Port Tied-off to fixed values
+ assign cfg_size = 64'd512;
+ assign cfg_scheme = 2'd0;
+ assign cfg_last = 1'b1;
+ assign cfg_valid = 1'b1;
+
+ //----------------------------------------------------------
+ // Output Port Logic
+ //----------------------------------------------------------
+
+ // Engine Output Port Wire declarations
+ logic [OUTPACKETWIDTH-1:0] out_packet;
+ logic out_packet_last;
+ logic [OUTPACKETSPACEWIDTH-1:0] out_packet_remain;
+ logic out_packet_valid;
+ logic out_packet_ready;
+
+ // Relative Read Address for Start of Current Block
+ logic [OUTPORTAHBADDRWIDTH-1:0] block_read_addr;
+
+ // Block Packets Remaining Tie-off (only ever one packet per block)
+ assign out_packet_remain = {OUTPACKETSPACEWIDTH{1'b0}};
+
+ // Packet Deconstructor Instantiation
+ wrapper_ahb_packet_deconstructor #(
+ OUTPORTAHBADDRWIDTH,
+ OUTPACKETWIDTH
+ ) u_wrapper_data_output_port (
.hclk (HCLK),
.hresetn (HRESETn),
- // Register interface
- .addr (input_addr),
- .read_en (input_read_en),
- .write_en (input_write_en),
- .byte_strobe (input_byte_strobe),
- .wdata (input_wdata),
- .rdata (input_rdata),
- .wready (input_wready),
- .rready (input_rready),
+ // Input slave port: 32 bit data bus interface
+ .hsels (hsel1),
+ .haddrs (HADDRS[AHBADDRWIDTH-2:0]),
+ .htranss (HTRANSS),
+ .hsizes (HSIZES),
+ .hwrites (HWRITES),
+ .hreadys (HREADYS),
+ .hwdatas (HWDATAS),
+
+ .hreadyouts (hreadyout1),
+ .hresps (hresp1),
+ .hrdatas (hrdata1),
// Valid/Ready Interface
- .packet_data (in_packet),
- .packet_data_last (in_packet_last),
- .packet_data_valid (in_packet_valid),
- .packet_data_ready (in_packet_ready)
+ .packet_data (out_packet),
+ .packet_data_last (out_packet_last),
+ .packet_data_remain (out_packet_remain),
+ .packet_data_valid (out_packet_valid),
+ .packet_data_ready (out_packet_ready),
+
+ // Input Data Request
+ .data_req (out_data_req),
+
+ // Read Address Interface
+ .block_read_addr (block_read_addr)
+ );
+
+ //----------------------------------------------------------
+ // Default AHB Target Logic
+ //----------------------------------------------------------
+
+ // AHB Default Target Instantiation
+ cmsdk_ahb_default_slave u_ahb_default_slave(
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (hsel2),
+ .HTRANS (HTRANSS),
+ .HREADY (HREADYS),
+ .HREADYOUT (hreadyout2),
+ .HRESP (hresp2)
);
+ // Default Targets Data is tied off
+ assign hrdata2 = {32{1'b0}};
+
+ //**********************************************************
+ // Wrapper APB Components
+ //**********************************************************
+
+ // TODO: Instantiate APB Mux
+
+ // TODO: Instantiate APB Default Target
+
+ // TODO: Wrapper Register Blocks
+
+ //**********************************************************
+ // Wrapper Interrupt Generation
+ //**********************************************************
+
+ // TODO: Instantiate IRQ Generator
+
+ //**********************************************************
+ // Wrapper DMA Data Request Generation
+ //**********************************************************
+
+ // TODO: Write up data request logic through registers
+
+ //**********************************************************
+ // Accelerator Engine
+ //**********************************************************
+
+ //----------------------------------------------------------
+ // Accelerator Engine Logic
+ //----------------------------------------------------------
+
+ // Hashing Accelerator Instatiation
sha256_hashing_stream u_sha256_hashing_stream (
.clk (HCLK),
.nrst (HRESETn),
@@ -208,28 +335,5 @@ module wrapper_sha256_hashing_stream #(
.data_out_ready (out_packet_ready)
);
- wrapper_packet_deconstruct #(
- (ADDRWIDTH - 1), // Only half address map allocated to this device
- 256 // Ouptut Packet WIdth
- ) u_wrapper_packet_deconstruct (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Register interface
- .addr (output_addr),
- .read_en (output_read_en),
- .write_en (output_write_en),
- .byte_strobe (output_byte_strobe),
- .wdata (output_wdata),
- .rdata (output_rdata),
- .wready (output_wready),
- .rready (output_rready),
-
- // Valid/Ready Interface
- .packet_data (out_packet),
- .packet_data_last (out_packet_last),
- .packet_data_valid (out_packet_valid),
- .packet_data_ready (out_packet_ready)
- );
endmodule
\ No newline at end of file
diff --git a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv b/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
index 36def961336aa07a44f82d4d3e466b997be39689..67579c7a6bb43ad57487c79dad7e6ae4995a8654 100644
--- a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
+++ b/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
@@ -147,13 +147,13 @@ cmsdk_ahb_fileread_master32 #(InputFileName,
//********************************************************************************
// Slave multiplexer module:
-// multiplex the slave signals to master, three ports are enabled
+// multiplex the slave signals to master, two ports are enabled
//********************************************************************************
cmsdk_ahb_slave_mux #(
1, //PORT0_ENABLE
1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
+ 0, //PORT2_ENABLE
0, //PORT3_ENABLE
0, //PORT4_ENABLE
0, //PORT5_ENABLE
@@ -231,8 +231,10 @@ cmsdk_ahb_fileread_master32 #(InputFileName,
.HREADYOUTS (hreadyout0),
.HRESPS (hresp0),
- .HRDATAS (hrdata0)
+ .HRDATAS (hrdata0),
+ // Input Data Request to DMAC
+ .in_data_req ()
);