From 697e268e685ecfe0c48b5e74127c965f249fffc0 Mon Sep 17 00:00:00 2001
From: David Mapstone <david@mapstone.me>
Date: Mon, 20 Mar 2023 15:22:58 +0000
Subject: [PATCH] SOC1-141: Updated top-level wrapper to use AHB packet
constructor for input port
---
accelerator-wrapper | 2 +-
nanosoc | 2 +-
wrapper/src/wrapper_sha256_hashing_stream.sv | 228 ++++++++++++++----
.../verif/tb_wrapper_sha256_hashing_stream.sv | 4 +-
4 files changed, 190 insertions(+), 46 deletions(-)
diff --git a/accelerator-wrapper b/accelerator-wrapper
index 031c516..34fab01 160000
--- a/accelerator-wrapper
+++ b/accelerator-wrapper
@@ -1 +1 @@
-Subproject commit 031c516e3aded99b3fe63311f1500bb751705c27
+Subproject commit 34fab012317556651f1de4debf369a8f3db6330b
diff --git a/nanosoc b/nanosoc
index 5843789..6138eb0 160000
--- a/nanosoc
+++ b/nanosoc
@@ -1 +1 @@
-Subproject commit 5843789d5155903a0868741a33cf016875831b27
+Subproject commit 6138eb07a20f6394b39ea5f53f553a4300d8b6e4
diff --git a/wrapper/src/wrapper_sha256_hashing_stream.sv b/wrapper/src/wrapper_sha256_hashing_stream.sv
index 89dd297..05135e7 100644
--- a/wrapper/src/wrapper_sha256_hashing_stream.sv
+++ b/wrapper/src/wrapper_sha256_hashing_stream.sv
@@ -37,7 +37,9 @@
//-----------------------------------------------------------------------------
module wrapper_sha256_hashing_stream #(
- parameter ADDRWIDTH=12
+ parameter ADDRWIDTH=12,
+ parameter INPACKETWIDTH=512,
+ parameter OUTPACKETWIDTH=256
) (
input logic HCLK, // Clock
input logic HRESETn, // Reset
@@ -94,6 +96,9 @@ module wrapper_sha256_hashing_stream #(
logic in_packet_valid;
logic in_packet_ready;
+ // Input Data Request
+ logic in_data_req;
+
// Output Packet Wires
logic [255:0] out_packet;
logic out_packet_last;
@@ -112,10 +117,131 @@ module wrapper_sha256_hashing_stream #(
assign cfg_last = 1'b1;
assign cfg_valid = 1'b1;
+ // Engine Input AHB Signals
+ logic hsel0;
+ logic hreadyout0;
+ logic hresp0;
+ logic [31:0] hrdata0;
+
+ // Engine Output AHB Signals
+ logic hsel1;
+ logic hreadyout1;
+ logic hresp1;
+ logic [31:0] hrdata1;
+
+ // Default Target AHB Signals
+ logic hsel2;
+ logic hreadyout2;
+ logic hresp2;
+ logic [31:0] hrdata2;
+
+ // Address Decoder
+ assign hsel0 = (~HADDRS[ADDRWIDTH-1]) ? 1'b1:1'b0; // Input Port Select
+ assign hsel1 = (HADDRS[ADDRWIDTH-1]) ? 1'b1:1'b0; // Output Port Select
+ assign hsel2 = (hsel0 | hsel1) ? 1'b0:1'b1; // Default Target Select
+
//-----------------------------------------------------------
// Module logic start
//----------------------------------------------------------
+ cmsdk_ahb_slave_mux #(
+ 1, //PORT0_ENABLE
+ 1, //PORT1_ENABLE
+ 1, //PORT2_ENABLE
+ 0, //PORT3_ENABLE
+ 0, //PORT4_ENABLE
+ 0, //PORT5_ENABLE
+ 0, //PORT6_ENABLE
+ 0, //PORT7_ENABLE
+ 0, //PORT8_ENABLE
+ 0 //PORT9_ENABLE
+ ) u_ahb_slave_mux (
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HREADY (HREADYS),
+ .HSEL0 (hsel0), // Input Port 0
+ .HREADYOUT0 (hreadyout0),
+ .HRESP0 (hresp0),
+ .HRDATA0 (hrdata0),
+ .HSEL1 (hsel1), // Input Port 1
+ .HREADYOUT1 (hreadyout1),
+ .HRESP1 (hresp1),
+ .HRDATA1 (hrdata1),
+ .HSEL2 (hsel2), // Input Port 2
+ .HREADYOUT2 (hreadyout2),
+ .HRESP2 (hresp2),
+ .HRDATA2 (hrdata2),
+ .HSEL3 (1'b0), // Input Port 3
+ .HREADYOUT3 (),
+ .HRESP3 (),
+ .HRDATA3 (),
+ .HSEL4 (1'b0), // Input Port 4
+ .HREADYOUT4 (),
+ .HRESP4 (),
+ .HRDATA4 (),
+ .HSEL5 (1'b0), // Input Port 5
+ .HREADYOUT5 (),
+ .HRESP5 (),
+ .HRDATA5 (),
+ .HSEL6 (1'b0), // Input Port 6
+ .HREADYOUT6 (),
+ .HRESP6 (),
+ .HRDATA6 (),
+ .HSEL7 (1'b0), // Input Port 7
+ .HREADYOUT7 (),
+ .HRESP7 (),
+ .HRDATA7 (),
+ .HSEL8 (1'b0), // Input Port 8
+ .HREADYOUT8 (),
+ .HRESP8 (),
+ .HRDATA8 (),
+ .HSEL9 (1'b0), // Input Port 9
+ .HREADYOUT9 (),
+ .HRESP9 (),
+ .HRDATA9 (),
+
+ .HREADYOUT (HREADYOUTS), // Outputs
+ .HRESP (HRESPS),
+ .HRDATA (HRDATAS)
+ );
+
+ //----------------------------
+ // Input Port
+ //----------------------------
+ wrapper_ahb_packet_constructor #(
+ ADDRWIDTH-1,
+ INPACKETWIDTH
+ ) u_wrapper_data_input_port (
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+
+ // Input slave port: 32 bit data bus interface
+ .hsels (hsel0),
+ .haddrs (HADDRS[ADDRWIDTH-2:0]),
+ .htranss (HTRANSS),
+ .hsizes (HSIZES),
+ .hwrites (HWRITES),
+ .hreadys (HREADYS),
+ .hwdatas (HWDATAS),
+
+ .hreadyouts (hreadyout0),
+ .hresps (hresp0),
+ .hrdatas (hrdata0),
+ // Valid/Ready Interface
+ .packet_data (in_packet),
+ .packet_data_last (in_packet_last),
+ .packet_data_valid (in_packet_valid),
+ .packet_data_ready (in_packet_ready),
+
+ // Input Data Request
+ .data_req (in_data_req)
+ );
+
+
+
+ //----------------------------
+ // Output Port
+ //----------------------------
// Interface block to convert AHB transfers to Register transfers to engine input/output channels
// engine Input/Output Channels
wrapper_ahb_vr_interface #(
@@ -125,7 +251,7 @@ module wrapper_sha256_hashing_stream #(
.hresetn (HRESETn),
// Input slave port: 32 bit data bus interface
- .hsels (HSELS),
+ .hsels (hsel1),
.haddrs (HADDRS),
.htranss (HTRANSS),
.hsizes (HSIZES),
@@ -133,9 +259,9 @@ module wrapper_sha256_hashing_stream #(
.hreadys (HREADYS),
.hwdatas (HWDATAS),
- .hreadyouts (HREADYOUTS),
- .hresps (HRESPS),
- .hrdatas (HRDATAS),
+ .hreadyouts (hreadyout1),
+ .hresps (hresp1),
+ .hrdatas (hrdata1),
// Register interface - Accelerator Engine Input
.input_addr (input_addr),
@@ -158,30 +284,59 @@ module wrapper_sha256_hashing_stream #(
.output_rready (output_rready)
);
- wrapper_packet_construct #(
+ wrapper_packet_deconstruct #(
(ADDRWIDTH - 1), // Only half address map allocated to this device
- 512 // Packet Width
- ) u_wrapper_packet_construct (
+ 256 // Ouptut Packet WIdth
+ ) u_wrapper_packet_deconstruct (
.hclk (HCLK),
.hresetn (HRESETn),
// Register interface
- .addr (input_addr),
- .read_en (input_read_en),
- .write_en (input_write_en),
- .byte_strobe (input_byte_strobe),
- .wdata (input_wdata),
- .rdata (input_rdata),
- .wready (input_wready),
- .rready (input_rready),
+ .addr (output_addr),
+ .read_en (output_read_en),
+ .write_en (output_write_en),
+ .byte_strobe (output_byte_strobe),
+ .wdata (output_wdata),
+ .rdata (output_rdata),
+ .wready (output_wready),
+ .rready (output_rready),
// Valid/Ready Interface
- .packet_data (in_packet),
- .packet_data_last (in_packet_last),
- .packet_data_valid (in_packet_valid),
- .packet_data_ready (in_packet_ready)
+ .packet_data (out_packet),
+ .packet_data_last (out_packet_last),
+ .packet_data_valid (out_packet_valid),
+ .packet_data_ready (out_packet_ready)
);
+ // wrapper_packet_construct #(
+ // (ADDRWIDTH - 1), // Only half address map allocated to this device
+ // 512 // Packet Width
+ // ) u_wrapper_packet_construct (
+ // .hclk (HCLK),
+ // .hresetn (HRESETn),
+
+ // // Register interface
+ // .addr (input_addr),
+ // .read_en (input_read_en),
+ // .write_en (input_write_en),
+ // .byte_strobe (input_byte_strobe),
+ // .wdata (input_wdata),
+ // .rdata (input_rdata),
+ // .wready (input_wready),
+ // .rready (input_rready),
+
+ // // Valid/Ready Interface
+ // .packet_data (in_packet),
+ // .packet_data_last (in_packet_last),
+ // .packet_data_valid (in_packet_valid),
+ // .packet_data_ready (in_packet_ready),
+
+ // .engine_ready()
+ // );
+
+ //------------------------
+ // Accelerator Engine
+ //------------------------
sha256_hashing_stream u_sha256_hashing_stream (
.clk (HCLK),
.nrst (HRESETn),
@@ -208,28 +363,17 @@ module wrapper_sha256_hashing_stream #(
.data_out_ready (out_packet_ready)
);
- wrapper_packet_deconstruct #(
- (ADDRWIDTH - 1), // Only half address map allocated to this device
- 256 // Ouptut Packet WIdth
- ) u_wrapper_packet_deconstruct (
- .hclk (HCLK),
- .hresetn (HRESETn),
-
- // Register interface
- .addr (output_addr),
- .read_en (output_read_en),
- .write_en (output_write_en),
- .byte_strobe (output_byte_strobe),
- .wdata (output_wdata),
- .rdata (output_rdata),
- .wready (output_wready),
- .rready (output_rready),
-
- // Valid/Ready Interface
- .packet_data (out_packet),
- .packet_data_last (out_packet_last),
- .packet_data_valid (out_packet_valid),
- .packet_data_ready (out_packet_ready)
+ // Default Target
+ cmsdk_ahb_default_slave u_ahb_default_slave(
+ .HCLK (HCLK),
+ .HRESETn (HRESETn),
+ .HSEL (hsel2),
+ .HTRANS (HTRANSS),
+ .HREADY (HREADYS),
+ .HREADYOUT (hreadyout2),
+ .HRESP (hresp2)
);
+ assign hrdata2 = {32{1'b0}}; // Default target doesn't have data
+
endmodule
\ No newline at end of file
diff --git a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv b/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
index 36def96..dae3183 100644
--- a/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
+++ b/wrapper/verif/tb_wrapper_sha256_hashing_stream.sv
@@ -147,13 +147,13 @@ cmsdk_ahb_fileread_master32 #(InputFileName,
//********************************************************************************
// Slave multiplexer module:
-// multiplex the slave signals to master, three ports are enabled
+// multiplex the slave signals to master, two ports are enabled
//********************************************************************************
cmsdk_ahb_slave_mux #(
1, //PORT0_ENABLE
1, //PORT1_ENABLE
- 1, //PORT2_ENABLE
+ 0, //PORT2_ENABLE
0, //PORT3_ENABLE
0, //PORT4_ENABLE
0, //PORT5_ENABLE
--
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