From 613c76a5540a9d9028355f523a5fb59e3d9d1fbf Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 30 Jun 2023 11:23:28 +0100
Subject: [PATCH] Moved AES Test to project level
---
.gitignore | 11 +-
nanosoc_tech | 2 +-
system/cpu_software/software_list.txt | 0
system/testcodes/aes128_tests/aes128.h | 71 ++
system/testcodes/aes128_tests/aes128_tests.c | 688 ++++++++++++++++++
.../testcodes/aes128_tests/dma_pl230_driver.c | 163 +++++
.../testcodes/aes128_tests/dma_pl230_driver.h | 198 +++++
system/testcodes/aes128_tests/makefile | 258 +++++++
system/testcodes/software_list.txt | 1 +
9 files changed, 1390 insertions(+), 2 deletions(-)
delete mode 100644 system/cpu_software/software_list.txt
create mode 100644 system/testcodes/aes128_tests/aes128.h
create mode 100644 system/testcodes/aes128_tests/aes128_tests.c
create mode 100644 system/testcodes/aes128_tests/dma_pl230_driver.c
create mode 100644 system/testcodes/aes128_tests/dma_pl230_driver.h
create mode 100644 system/testcodes/aes128_tests/makefile
create mode 100644 system/testcodes/software_list.txt
diff --git a/.gitignore b/.gitignore
index fca9ac0..2059d90 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,4 @@
+# Simulation Related File Removal
*.vcd
*.vvp
simulate/sim/*
@@ -7,4 +8,12 @@ accelerator/html/*
wrapper/html/*
system/src/bootrom
system/html/*
-flist/tmp
\ No newline at end of file
+flist/tmp
+
+# Compile Test Code Removal
+/system/testcodes/*/*.elf
+/system/testcodes/*/*.ELF
+/system/testcodes/*/*.hex
+/system/testcodes/*/*.lst
+/system/testcodes/*/*.o
+/system/testcodes/*/*.bin
\ No newline at end of file
diff --git a/nanosoc_tech b/nanosoc_tech
index a012b7b..8d33ead 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit a012b7b8cdd7ff9deb9bb78fcf7738a588ae1ad5
+Subproject commit 8d33eadfa943359fa5b7612283272892669be999
diff --git a/system/cpu_software/software_list.txt b/system/cpu_software/software_list.txt
deleted file mode 100644
index e69de29..0000000
diff --git a/system/testcodes/aes128_tests/aes128.h b/system/testcodes/aes128_tests/aes128.h
new file mode 100644
index 0000000..202adf4
--- /dev/null
+++ b/system/testcodes/aes128_tests/aes128.h
@@ -0,0 +1,71 @@
+#ifndef _AES128_H_
+#define _AES128_H_
+
+#include <stdint.h>
+
+// define the API addresses here.
+
+#define AES128_BASE (0x60000000)
+
+// byte address I/O buffers
+#define AES128_BUF_SIZE (0x4000)
+
+typedef struct {
+ __I uint32_t CORE_NAME[2]; /* 0x0000-0007 */
+ __I uint32_t CORE_VERSION; /* 0x0008-000B */
+ uint32_t RESRV0C; /* 0x000C */
+ __IO uint32_t CTRL; /* 0x0010 */
+ __O uint32_t CTRL_SET; /* 0x0014 */
+ __O uint32_t CTRLL_CLR; /* 0x0018 */
+ __I uint32_t STATUS; /* 0x001c */
+ __IO uint32_t QUAL; /* 0x0020 */
+ uint32_t RESRV24[3]; /* 0x0024 - 2F*/
+ __IO uint32_t DRQ_MSK; /* 0x0030 */
+ __O uint32_t DRQ_MSK_SET; /* 0x0034 */
+ __O uint32_t DRQ_MSK_CLR; /* 0x0038 */
+ __I uint32_t DRQ_STATUS; /* 0x003C */
+ __IO uint32_t IRQ_MSK; /* 0x0040 */
+ __O uint32_t IRQ_MSK_SET; /* 0x0044 */
+ __O uint32_t IRQ_MSK_CLR; /* 0x0048 */
+ __I uint32_t IRQ_STATUS; /* 0x004C */
+ uint8_t RESRV50[AES128_BUF_SIZE - 0x50];/* 0x0050-0x3FFC (4096-20 words) */
+ __IO uint8_t KEY128[AES128_BUF_SIZE]; /* 0x4000-7FFF (0x3FFF is last alias) */
+ __IO uint8_t TXTIP128[AES128_BUF_SIZE]; /* 0x8000-BFFF (0x3FFF is last alias) */
+ __I uint8_t TXTOP128[AES128_BUF_SIZE]; /* 0xC000-FFFF (0x3FFF is last alias) */
+} AES128_TypeDef;
+
+#define AES128 ((AES128_TypeDef *) AES128_BASE )
+
+#define AES_BLOCK_SIZE 16
+
+#define AES_KEY_LEN_128 16
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+#define AES128_CTRL_REG_WIDTH ( 8)
+#define AES128_CTRL_BIT_MAX ( (CTRL_REG_WIDTH-1)
+#define AES128_CTRL_KEY_REQ_BIT (1<<0)
+#define AES128_CTRL_IP_REQ_BIT (1<<1)
+#define AES128_CTRL_OP_REQ_BIT (1<<2)
+#define AES128_CTRL_ERR_REQ_BIT (1<<3)
+#define AES128_CTRL_BYPASS_BIT (1<<6)
+#define AES128_CTRL_ENCODE_BIT (1<<7)
+#define AES128_STAT_REG_WIDTH ( 8)
+#define AES128_STAT_KEY_REQ_BIT (1<<0)
+#define AES128_STAT_IP_REQ_BIT (1<<1)
+#define AES128_STAT_OP_REQ_BIT (1<<2)
+#define AES128_STAT_ERR_REQ_BIT (1<<3)
+#define AES128_STAT_KEYOK_BIT (1<<4)
+#define AES128_STAT_VALID_BIT (1<<5)
+#define AES128_STAT_BYPASS_BIT (1<<6)
+#define AES128_STAT_ENCODE_BIT (1<<7)
+#define AES128_KEY_REQ_BIT (1<<0)
+#define AES128_IP_REQ_BIT (1<<1)
+#define AES128_OP_REQ_BIT (1<<2)
+#define AES128_ERR_REQ_BIT (1<<3)
+#define AES128_KEYOK_BIT (1<<4)
+#define AES128_VALID_BIT (1<<5)
+#define AES128_BYPASS_BIT (1<<6)
+#define AES128_ENCODE_BIT (1<<7)
+
+#endif // _AES128_H_
diff --git a/system/testcodes/aes128_tests/aes128_tests.c b/system/testcodes/aes128_tests/aes128_tests.c
new file mode 100644
index 0000000..36bc549
--- /dev/null
+++ b/system/testcodes/aes128_tests/aes128_tests.c
@@ -0,0 +1,688 @@
+#include "CMSDK_CM0.h"
+#include "aes128.h"
+#include <string.h>
+#include "uart_stdout.h"
+#include <stdio.h>
+// memcopy implememtation
+#define os_memcpy memcpy
+#define os_memset memset
+// PL230DMA implementation
+#include "dma_pl230_driver.h"
+
+
+static volatile dma_pl230_channel_data aes_ip_chain[2];
+static volatile dma_pl230_channel_data aes_op_chain[2];
+
+// associate DMA channel numbers
+#define DMA_CHAN_AES128_IP (0)
+#define DMA_CHAN_AES128_OP (1)
+
+volatile int dma_done_irq_occurred;
+volatile int dma_done_irq_expected;
+volatile int dma_error_irq_occurred;
+volatile int dma_error_irq_expected;
+volatile int aes_key_irq_occurred;
+volatile int aes_key_irq_expected;
+volatile int aes_ip_irq_occurred;
+volatile int aes_ip_irq_expected;
+volatile int aes_op_irq_occurred;
+volatile int aes_op_irq_expected;
+volatile int aes_err_irq_occurred;
+volatile int aes_err_irq_expected;
+
+ uint8_t _test_key128[AES_KEY_LEN_128] = {
+ 0x75, 0x46, 0x20, 0x67,
+ 0x6e, 0x75, 0x4b, 0x20,
+ 0x79, 0x6d, 0x20, 0x73,
+ 0x74, 0x61, 0x68, 0x54 };
+
+ uint8_t test_key128[AES_KEY_LEN_128] = {
+ 0x54, 0x68, 0x61, 0x74,
+ 0x73, 0x20, 0x6d, 0x79,
+ 0x20, 0x4b, 0x75, 0x6e,
+ 0x67, 0x20, 0x46, 0x75 };
+
+ uint8_t buf128[AES_BLOCK_SIZE] = {
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00 };
+
+ uint8_t _test_text128[AES_BLOCK_SIZE] = {
+ 0x6f, 0x77, 0x54, 0x20,
+ 0x65, 0x6e, 0x69, 0x4e,
+ 0x20, 0x65, 0x6e, 0x4f,
+ 0x20, 0x6f, 0x77, 0x54 };
+
+ uint8_t test_text128[AES_BLOCK_SIZE] = {
+ 0x54, 0x77, 0x6f, 0x20,
+ 0x4f, 0x6e, 0x65, 0x20,
+ 0x4e, 0x69, 0x6e, 0x65,
+ 0x20, 0x54, 0x77, 0x6f };
+
+ uint8_t test_exp128[AES_BLOCK_SIZE] = {
+ 0x29, 0xc3, 0x50, 0x5f,
+ 0x57, 0x14, 0x20, 0xf6,
+ 0x40, 0x22, 0x99, 0xb3,
+ 0x1a, 0x02, 0xd7, 0x3a };
+
+// add extra block[128] with all zeros to toggle bits low
+ uint8_t shift_patt[129*16] = {
+ 0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x80,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xc0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xe0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf0,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xf8,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfc,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xfe,
+ 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,//127
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,//128
+ };
+
+ uint8_t shift_buf1[sizeof(shift_patt)];
+ uint8_t shift_buf2[sizeof(shift_patt)];
+
+
+/* Note: Hardware supports byte, half-word or word accesses
+ So memcpy() can be used to load/save data
+ And memset() can be used to pad out data-in to 128-bits
+ mode =0 (bypass), =1 (encode) or =2 (decode)
+*/
+void aes128_driver_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT | AES128_CTRL_ERR_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+
+ // Program Key
+ os_memcpy((uint8_t *)AES128->KEY128, key, AES_KEY_LEN_128);
+ while (!(AES128->STATUS & AES128_KEYOK_BIT))
+ ;
+
+ /* payload */
+ while(nbytes) {
+ uint8_t len = (nbytes > AES_BLOCK_SIZE) ? AES_BLOCK_SIZE : nbytes;
+ /* Align/pad input and load into hardware */
+ os_memcpy((uint8_t *)AES128->TXTIP128, input, len);
+ //patch up any zero-padding
+ if (len < AES_BLOCK_SIZE)
+ os_memset((uint8_t *)&(AES128->TXTIP128[len]), 0, AES_BLOCK_SIZE-len);
+ /* Auto-started! - no need for manual start */
+ /* Poll until completed */
+ while (!(AES128->STATUS & AES128_VALID_BIT))
+ ;
+ os_memcpy(result, (uint8_t *)AES128->TXTOP128, AES_BLOCK_SIZE);
+ /* Accounting */
+ input += len;
+ result += len;
+ nbytes -= len;
+ AES128->IRQ_MSK_SET = (AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ }
+ AES128->CTRL = 0;
+}
+
+// wrapper functions
+
+void aes128_bypass_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 0); }
+
+void aes128_encrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 1); }
+
+void aes128_decrypt_memcpy(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_driver_memcpy(key, nbytes, input, result, 2); }
+
+
+int aes128_buffer_verify(uint32_t buflen, uint8_t *buf_A, uint8_t *buf_B)
+{
+ int i, j, fail = 0;
+ for (i=0 ; i < buflen; i++) {
+ if (buf_A[i] != buf_B[i]){
+ fail = 1;
+ break;
+ }
+ }
+ if (fail) {
+ j=i; // print offending block
+ for (i=(j - (j%16)) ; i < (j-(j%16)+16); i++) {
+ if (i%16==0)
+ printf(" //%03d\n", (i>>4));
+ printf("0x%02x,", buf_A[i]);
+ }
+ }
+ if (fail){
+ i=j;
+ printf("Verify compare FAIL\n EXPECTED_RESULT[%2d]= 0x%02x, ACTUAL_RESULT= 0x%02x \n",i, buf_B[i], buf_A[i]);
+ return(-1);
+ }
+ return(0);
+}
+
+void aes128_driver_aligned_dma32(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ int c;
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ dma_pl230_data_struct_init(); // initialize
+
+ // program DMA transfers in multiples of 4 words (nbytes scaled >>2 for words)
+ aes_ip_chain[0].SrcEndPointer = DMA_PL230_PTR_END(key,PL230_XFER_W,4);
+ aes_ip_chain[0].DstEndPointer = DMA_PL230_PTR_END(&(AES128->KEY128[AES128_BUF_SIZE-16]),PL230_XFER_W,4);
+ aes_ip_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_DEV_CHAIN_ALT,PL230_XFER_W,4,PL230_CTRL_RPWR_4);
+
+ aes_ip_chain[1].SrcEndPointer = DMA_PL230_PTR_END(input,PL230_XFER_W,(nbytes>>2));
+ aes_ip_chain[1].DstEndPointer = DMA_PL230_PTR_END(&(AES128->TXTIP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_W,(nbytes>>2));
+ aes_ip_chain[1].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_W,(nbytes>>2),PL230_CTRL_RPWR_4);
+
+ c=DMA_CHAN_AES128_IP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_ip_chain[0].SrcEndPointer), PL230_XFER_W,(2*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(2*4),PL230_CTRL_RPWR_4);
+
+ aes_op_chain[0].SrcEndPointer = DMA_PL230_PTR_END(&(AES128->TXTOP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_W,(nbytes>>2));
+ aes_op_chain[0].DstEndPointer = DMA_PL230_PTR_END(result,PL230_XFER_W,(nbytes>>2));
+ aes_op_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_W,(nbytes>>2),PL230_CTRL_RPWR_4);
+
+ c=DMA_CHAN_AES128_OP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_op_chain[0].SrcEndPointer), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(1*4),PL230_CTRL_RPWR_4);
+
+ // enable DMA controller channels
+ dma_pl230_init((1<<DMA_CHAN_AES128_OP) | (1<<DMA_CHAN_AES128_IP)); // two active
+
+ // and enable DMA requests
+ AES128->DRQ_MSK_SET = (AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ // test to ensure output DMA has started
+ while (!(dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP))))
+ ;
+ while (dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP)))
+ ;
+ while (dma_pl230_channel_active((1<<DMA_CHAN_AES128_OP)))
+ ;
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ dma_pl230_init(0); // none active
+ return;
+}
+
+void aes128_driver_dma8(uint8_t *key, uint32_t nbytes, uint8_t *input,
+ uint8_t *result, uint8_t mode)
+{
+ int c;
+ // Reset engine
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ AES128->QUAL = 0;
+ AES128->CTRL = AES128_CTRL_KEY_REQ_BIT | AES128_CTRL_IP_REQ_BIT | AES128_CTRL_OP_REQ_BIT;
+
+ // Set up parameters
+ if (mode == 1)
+ AES128->CTRL_SET = AES128_ENCODE_BIT; // ENCODE mode
+ if (mode == 0)
+ AES128->CTRL_SET = AES128_BYPASS_BIT; // BYPASS mode
+
+ dma_pl230_data_struct_init(); // initialize
+
+ // program DMA transfers in multiples of 16 bytes
+ aes_ip_chain[0].SrcEndPointer = DMA_PL230_PTR_END(key,PL230_XFER_B,16);
+ aes_ip_chain[0].DstEndPointer = DMA_PL230_PTR_END(&(AES128->KEY128[AES128_BUF_SIZE-16]),PL230_XFER_B,16);
+ aes_ip_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_DEV_CHAIN_ALT,PL230_XFER_B,16,PL230_CTRL_RPWR_16);
+
+ aes_ip_chain[1].SrcEndPointer = DMA_PL230_PTR_END(input,PL230_XFER_B,(nbytes));
+ aes_ip_chain[1].DstEndPointer = DMA_PL230_PTR_END(&(AES128->TXTIP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_B,(nbytes));
+ aes_ip_chain[1].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_B,(nbytes),PL230_CTRL_RPWR_16);
+
+ c=DMA_CHAN_AES128_IP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_ip_chain[0].SrcEndPointer), PL230_XFER_W, (2*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W, (1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(2*4),PL230_CTRL_RPWR_4);
+
+ aes_op_chain[0].SrcEndPointer = DMA_PL230_PTR_END(&(AES128->TXTOP128[AES128_BUF_SIZE-nbytes]),PL230_XFER_B,(nbytes));
+ aes_op_chain[0].DstEndPointer = DMA_PL230_PTR_END(result,PL230_XFER_B,(nbytes));
+ aes_op_chain[0].Control = DMA_PL230_CTRL(PL230_CTRL_CYCLE_BASIC,PL230_XFER_B,(nbytes),PL230_CTRL_RPWR_16);
+
+ c=DMA_CHAN_AES128_OP;
+ dma_pl230_table->Primary[c].SrcEndPointer = DMA_PL230_PTR_END(&(aes_op_chain[0].SrcEndPointer), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].DstEndPointer = DMA_PL230_PTR_END(&(dma_pl230_table->Alternate[c]), PL230_XFER_W,(1*4));
+ dma_pl230_table->Primary[c].Control= DMA_PL230_CTRL_DSTFIX(PL230_CTRL_CYCLE_DEV_CHAIN_PRI,PL230_XFER_W,(1*4),PL230_CTRL_RPWR_4);
+
+ // enable DMA controller channels
+ dma_pl230_init((1<<DMA_CHAN_AES128_OP) | (1<<DMA_CHAN_AES128_IP)); // two active
+
+ // and enable DMA requests
+ AES128->DRQ_MSK_SET = (AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ AES128->IRQ_MSK_SET = (AES128_ERR_REQ_BIT | AES128_KEY_REQ_BIT | AES128_IP_REQ_BIT | AES128_OP_REQ_BIT);
+ // test to ensure output DMA has started
+ while (!(dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP)))
+ ;
+ while (dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP))
+ ;
+ while (dma_pl230_channel_active(1<<DMA_CHAN_AES128_OP))
+ ;
+ AES128->DRQ_MSK = 0;
+ AES128->IRQ_MSK = 0;
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ dma_pl230_init(0); // none active
+ return;
+}
+
+// wrapper functions
+
+void aes128_alignchk_block_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result, uint8_t mode)
+ { uint32_t dma_max = DMA_PL230_MAX_XFERS; // default to 1 K bytes
+ if (((((long)key) & 3)==0) && ((((long)input) & 3)==0) && ((((long)result) & 3)==0)) dma_max=(DMA_PL230_MAX_XFERS<<2);
+ while (nbytes >dma_max) {
+ if (dma_max == DMA_PL230_MAX_XFERS) // 1K bytes DMA
+ aes128_driver_dma8(key, dma_max, input, result, mode);
+ else // 1K words DMA
+ aes128_driver_aligned_dma32(key, dma_max, input, result, mode);
+ nbytes -= dma_max; input += dma_max; result += dma_max;
+ }
+ if (dma_max == DMA_PL230_MAX_XFERS) // up to 1K bytes remaining
+ aes128_driver_dma8(key, nbytes, input, result, mode);
+ else // up to 1K words remaining
+ aes128_driver_aligned_dma32(key, nbytes, input, result, mode);
+ }
+
+void aes128_bypass_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 0); }
+
+void aes128_encrypt_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 1); }
+
+void aes128_decrypt_dma(uint8_t *key, uint32_t nbytes, uint8_t *input, uint8_t *result)
+ { aes128_alignchk_block_dma (key, nbytes, input, result, 2); }
+
+
+int main(void) {
+ char rx_char [256] = "SoCLabs AES128v1"; // init to 0
+ unsigned char id_string [16] = {0};
+ int i, fail=0;
+ unsigned char * p;
+
+ UartStdOutInit();
+ printf("%s\n",rx_char);
+ printf("AES128 test program\n");
+ printf(" AES128 ID: ");
+ // iterate over 3 32-bit fields
+ p = (unsigned char *)AES128->CORE_NAME;
+ for (i = 0; i < 12; i++) {
+ id_string[i^3]=*p; // fix byte ordering per word
+ p+=1;
+ }
+ id_string[12] = 0;
+ printf("%s\n",id_string);
+
+ aes_key_irq_occurred = 0;
+ aes_key_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP0_IRQn);
+ NVIC_EnableIRQ(EXP0_IRQn);
+ aes_ip_irq_occurred = 0;
+ aes_ip_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP1_IRQn);
+ NVIC_EnableIRQ(EXP1_IRQn);
+ aes_op_irq_occurred = 0;
+ aes_op_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP2_IRQn);
+ NVIC_EnableIRQ(EXP2_IRQn);
+ aes_err_irq_occurred = 0;
+ aes_err_irq_expected = 1;
+ NVIC_ClearPendingIRQ(EXP3_IRQn);
+ NVIC_EnableIRQ(EXP3_IRQn);
+
+ printf("AES128 SW (memcpy) tests...\n");
+ printf(" AES128 reference pattern test\n");
+
+ printf(" AES128 input/output bypass test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 2){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 1){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
+
+ printf(" AES128 decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(buf128), buf128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+
+ printf(" AES128 logic toggle test\n");
+ printf(" AES128 input/output pattern test\n");
+ aes128_bypass_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+
+ if (aes_key_irq_occurred != 1){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != (129+1)){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 129){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ printf(" AES128 pattern encrypt test\n");
+ aes128_encrypt_memcpy(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ printf(" AES128 pattern decrypt test\n");
+ aes128_decrypt_memcpy(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+
+ printf("AES128 DMA tests...\n");
+
+ aes_key_irq_occurred = 0;
+ aes_ip_irq_occurred = 0;
+ aes_op_irq_occurred = 0;
+ aes_err_irq_occurred = 0;
+ dma_error_irq_expected = 0;
+ dma_error_irq_occurred = 0;
+ dma_done_irq_expected = 1;
+ dma_done_irq_occurred = 0;
+ NVIC_ClearPendingIRQ(DMA_IRQn);
+ NVIC_EnableIRQ(DMA_IRQn);
+
+ printf(" AES128 dma input/output bypass test\n");
+ aes128_bypass_dma(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (dma_done_irq_occurred < 2){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ printf(" AES128 dma encrypt test\n");
+ aes128_encrypt_dma(test_key128, sizeof(test_text128), test_text128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_exp128);
+
+ printf(" AES128 dma decrypt test\n");
+ aes128_decrypt_dma(test_key128, sizeof(buf128), buf128, buf128);
+ fail += aes128_buffer_verify(AES_BLOCK_SIZE, buf128, test_text128);
+
+ if (dma_done_irq_occurred < 6){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ printf(" AES128 dma unaligned pattern test\n");
+ aes128_bypass_dma(test_key128,(16*63), shift_patt, shift_buf1+3);
+ fail += aes128_buffer_verify((16*63), shift_buf1+3, shift_patt);
+
+ printf(" AES128 dma input/output pattern test\n");
+ aes128_bypass_dma(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf1, shift_patt);
+ printf(" AES128 dma pattern encrypt test\n");
+ aes128_encrypt_dma(test_key128, sizeof(shift_patt), shift_patt, shift_buf1);
+ printf(" AES128 dma pattern decrypt test\n");
+ aes128_decrypt_dma(test_key128, sizeof(shift_patt), shift_buf1, shift_buf2);
+ fail += aes128_buffer_verify(sizeof(shift_patt), shift_buf2, shift_patt);
+
+ if (dma_done_irq_occurred < (2*7)){
+ puts ("ERROR: DMA err IRQ missing");
+ fail++;
+ } else
+ printf(" ++ DMA_DONE IRQ count = %d\n", dma_done_irq_occurred);
+
+ // check IRQ masked by DRQs - except when Iinput buffer empty after DMA done
+ if (aes_key_irq_occurred != 0){ fail++;
+ printf(" ++ AES key request IRQ count = %d\n", aes_key_irq_occurred); }
+ if (aes_ip_irq_occurred != 7){ fail++;
+ printf(" ++ AES inp request missing: IRQ count = %d\n", aes_ip_irq_occurred); }
+ if (aes_op_irq_occurred != 0){ fail++;
+ printf(" ++ AES out request missing: IRQ count = %d\n", aes_op_irq_occurred); }
+ if (aes_err_irq_occurred != 0){ fail++;
+ printf(" ++ AES err request missing: IRQ count = %d\n", aes_err_irq_occurred); }
+
+ NVIC_DisableIRQ(DMA_IRQn);
+ NVIC_DisableIRQ(EXP0_IRQn);
+ NVIC_DisableIRQ(EXP1_IRQn);
+ NVIC_DisableIRQ(EXP2_IRQn);
+ NVIC_DisableIRQ(EXP3_IRQn);
+
+ printf ("Data retrieved from the AES is: %s\n", id_string);
+ printf ("Data expected from the AES is: %s\n", rx_char);
+ if (fail >0)
+ printf("** AES TESTS FAILED (%d) **\n", fail);
+ else
+ printf("** AES TEST PASSED **\n");
+ // End simulation
+
+
+ UartEndSimulation();
+
+ return 0;
+
+}
+
+/* --------------------------------------------------------------- */
+/* Interrupt handlers */
+/* --------------------------------------------------------------- */
+
+void DMA_Handler(void)
+{
+if ((DMA_PL230_DMAC->ERR_CLR & 1) != 0) {
+ /* DMA interrupt is caused by DMA error */
+ dma_error_irq_occurred ++;
+ DMA_PL230_DMAC->ERR_CLR = 1; /* Clear dma_err */
+ if (dma_error_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+else {
+ // DMA interrupt is caused by DMA done
+ dma_done_irq_occurred ++;
+ if (dma_done_irq_expected==0) {
+ puts ("ERROR : Unexpected DMA done interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+ }
+}
+
+void EXP0_Handler(void)
+{
+ // AES128 interrupt is caused by Key buffer empty IRQ
+ aes_key_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_KEY_REQ_BIT;
+ if (aes_key_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Key buffer empty request interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP1_Handler(void)
+{
+ // AES128 interrupt is caused by Input buffer empty IRQ
+ aes_ip_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_IP_REQ_BIT;
+ if (aes_ip_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Input buffer empty reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP2_Handler(void)
+{
+ // AES128 interrupt is caused by Output buffer full IRQ
+ aes_op_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_OP_REQ_BIT;
+ if (aes_op_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Output buffer full reqest interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
+void EXP3_Handler(void)
+{
+ // AES128 interrupt is caused by Error IRQ
+ aes_err_irq_occurred ++;
+ AES128->IRQ_MSK_CLR = AES128_ERR_REQ_BIT;
+ if (aes_err_irq_expected==0) {
+ puts ("ERROR : Unexpected AES128 Error interrupt occurred.\n");
+ UartEndSimulation();
+ while (1);
+ }
+}
+
diff --git a/system/testcodes/aes128_tests/dma_pl230_driver.c b/system/testcodes/aes128_tests/dma_pl230_driver.c
new file mode 100644
index 0000000..8781465
--- /dev/null
+++ b/system/testcodes/aes128_tests/dma_pl230_driver.c
@@ -0,0 +1,163 @@
+#include <stdio.h>
+#include <string.h>
+#include "dma_pl230_driver.h"
+
+#define DEBUG_PRINTF(...) do {} while(0);
+//#define cpu_to_be32(__x) __x
+//#define be32_to_cpu(__x) __x
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static int g_dma_pl230_initialised = 0;
+
+static dma_pl230_data_structure priv_dma __attribute__((aligned(256)));
+//
+dma_pl230_data_structure *dma_pl230_table = &priv_dma;
+
+/* --------------------------------------------------------------- */
+/* Initialize DMA data structure */
+/* --------------------------------------------------------------- */
+void dma_pl230_data_struct_init(void)
+{
+ int i; /* loop counter */
+
+// printf ("dma structure block address = %x\n", dma_pl230_table);
+ for (i=0; i<MAX_NUM_OF_DMA_CHANNELS; i++) {
+ dma_pl230_table->Primary[i].SrcEndPointer = 0;
+ dma_pl230_table->Primary[i].DstEndPointer = 0;
+ dma_pl230_table->Primary[i].Control = 0;
+ dma_pl230_table->Alternate[i].SrcEndPointer = 0;
+ dma_pl230_table->Alternate[i].DstEndPointer = 0;
+ dma_pl230_table->Alternate[i].Control = 0;
+ }
+ g_dma_pl230_initialised = 1;
+ return;
+}
+
+void dma_pl230_data_struct_init_dbg(void)
+{
+ int i; /* loop counter */
+ unsigned int ptr;
+
+ int ch_num; /* number of channels */
+ unsigned int blksize; /* Size of DMA data structure in bytes */
+ unsigned int blkmask; /* address mask */
+
+
+ ch_num = (((DMA_PL230_DMAC->DMA_STATUS) >> 16) & 0x1F)+1;
+ blksize = ch_num * 32;
+ if (ch_num > 16) blkmask = 0x3FF; /* 17 to 32 */
+ else if (ch_num > 8) blkmask = 0x1FF; /* 9 to 16 */
+ else if (ch_num > 4) blkmask = 0x0FF; /* 5 to 8 */
+ else if (ch_num > 2) blkmask = 0x07F; /* 3 to 4 */
+ else if (ch_num > 1) blkmask = 0x03F; /* 2 */
+ else blkmask = 0x01F; /* 1 */
+
+
+ /* Create DMA data structure in RAM after stack
+ In the linker script, a 1KB memory stack above stack is reserved
+ so we can use this space for putting the DMA data structure.
+ */
+
+// ptr = HW32_REG(0); /* Read Top of Stack */
+ ptr = (0x80000000); // force for now as no reserved RAM available
+
+ /* the DMA data structure must be aligned to the size of the data structure */
+ if ((ptr & blkmask) != 0x0)
+ ptr = (ptr + blksize) & ~blkmask;
+
+/// if ((ptr + blksize) > (RAM_ADDRESS_MAX + 1)) {
+/// puts ("ERROR : Not enough RAM space for DMA data structure.");
+/// UartEndSimulation();
+/// }
+
+ /* Set pointer to the reserved space */
+ dma_pl230_table = (dma_pl230_data_structure *) ptr;
+ ptr = (unsigned long) &(dma_pl230_table->Primary[0].SrcEndPointer);
+
+ printf ("dma structure block address = %x\n", ptr);
+
+ for (i=0; i<MAX_NUM_OF_DMA_CHANNELS; i++) {
+ dma_pl230_table->Primary[i].SrcEndPointer = 0;
+ dma_pl230_table->Primary[i].DstEndPointer = 0;
+ dma_pl230_table->Primary[i].Control = 0;
+ dma_pl230_table->Alternate[i].SrcEndPointer = 0;
+ dma_pl230_table->Alternate[i].DstEndPointer = 0;
+ dma_pl230_table->Alternate[i].Control = 0;
+ }
+ g_dma_pl230_initialised = 1;
+ return;
+}
+/* --------------------------------------------------------------- */
+/* Initialize DMA PL230 */
+/* --------------------------------------------------------------- */
+void dma_pl230_init_dbg(unsigned int chan_mask)
+{
+ unsigned int current_state;
+ puts ("Initialize PL230");
+ current_state = DMA_PL230_DMAC->DMA_STATUS;
+ printf ("- # of channels allowed : %d\n",(((current_state) >> 16) & 0x1F)+1);
+ /* Debugging printfs: */
+ printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
+ printf ("- Current master enable : %x\n",(((current_state) >> 0) & 0x1));
+
+ /* Wait until current DMA complete */
+ current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
+ if (!((current_state==0) || (current_state==0x8) || (current_state==0x9))) {
+ puts ("- wait for DMA IDLE/STALLED/DONE");
+ current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
+ printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
+
+ }
+ while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
+ /* Wait if not IDLE/STALLED/DONE */
+ current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
+ printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
+ }
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ DMA_PL230_DMAC->CTRL_BASE_PTR = (unsigned long) &(dma_pl230_table->Primary->SrcEndPointer);
+ /* Set DMA data structure address */
+ DMA_PL230_DMAC->CHNL_ENABLE_CLR = 0xFFFFFFFF; /* Disable all channels */
+ DMA_PL230_DMAC->CHNL_PRI_ALT_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all alt channels */
+ DMA_PL230_DMAC->CHNL_ENABLE_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable channel */
+ DMA_PL230_DMAC->CHNL_USEBURST_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable bursts */
+ if (chan_mask)
+ DMA_PL230_DMAC->DMA_CFG = 1; /* Enable DMA controller if enabled channel*/
+ return;
+}
+
+void dma_pl230_init(unsigned int chan_mask)
+{
+ unsigned int current_state;
+ if (g_dma_pl230_initialised ==0)
+ dma_pl230_data_struct_init();
+ /* Wait until current DMA complete */
+ current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
+ while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
+ /* Wait if not IDLE/STALLED/DONE */
+ puts ("- wait for DMA IDLE/STALLED/DONE");
+ current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
+ }
+ DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
+ DMA_PL230_DMAC->CTRL_BASE_PTR = (unsigned long) &(dma_pl230_table->Primary->SrcEndPointer);
+ /* Set DMA data structure address */
+ DMA_PL230_DMAC->CHNL_ENABLE_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all channels */
+ DMA_PL230_DMAC->CHNL_PRI_ALT_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all alt channels */
+ DMA_PL230_DMAC->CHNL_ENABLE_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable channel */
+ DMA_PL230_DMAC->CHNL_USEBURST_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable bursts */
+ g_dma_pl230_initialised = 2;
+ if (chan_mask)
+ DMA_PL230_DMAC->DMA_CFG = 1; /* Enable DMA controller if enabled channel*/
+ return;
+}
+
+unsigned int dma_pl230_channel_active(unsigned int chan_mask)
+{
+ return(DMA_PL230_DMAC->CHNL_ENABLE_SET & chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enabled channels */
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/system/testcodes/aes128_tests/dma_pl230_driver.h b/system/testcodes/aes128_tests/dma_pl230_driver.h
new file mode 100644
index 0000000..082b196
--- /dev/null
+++ b/system/testcodes/aes128_tests/dma_pl230_driver.h
@@ -0,0 +1,198 @@
+#ifndef __DMA_PL230_MCU_H
+#define __DMA_PL230_MCU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "CMSDK_CM0.h"
+
+#define DMA_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
+
+#define MAX_NUM_OF_DMA_CHANNELS 2
+
+/*------------- PL230 uDMA (PL230) --------------------------------------*/
+/** @addtogroup DMA_PL230 CMSDK uDMA controller
+ @{
+*/
+typedef struct
+{
+ __I uint32_t DMA_STATUS; /*!< Offset: 0x000 DMA status Register (R/W) */
+ __O uint32_t DMA_CFG; /*!< Offset: 0x004 DMA configuration Register ( /W) */
+ __IO uint32_t CTRL_BASE_PTR; /*!< Offset: 0x008 Channel Control Data Base Pointer Register (R/W) */
+ __I uint32_t ALT_CTRL_BASE_PTR; /*!< Offset: 0x00C Channel Alternate Control Data Base Pointer Register (R/ ) */
+ __I uint32_t DMA_WAITONREQ_STATUS; /*!< Offset: 0x010 Channel Wait On Request Status Register (R/ ) */
+ __O uint32_t CHNL_SW_REQUEST; /*!< Offset: 0x014 Channel Software Request Register ( /W) */
+ __IO uint32_t CHNL_USEBURST_SET; /*!< Offset: 0x018 Channel UseBurst Set Register (R/W) */
+ __O uint32_t CHNL_USEBURST_CLR; /*!< Offset: 0x01C Channel UseBurst Clear Register ( /W) */
+ __IO uint32_t CHNL_REQ_MASK_SET; /*!< Offset: 0x020 Channel Request Mask Set Register (R/W) */
+ __O uint32_t CHNL_REQ_MASK_CLR; /*!< Offset: 0x024 Channel Request Mask Clear Register ( /W) */
+ __IO uint32_t CHNL_ENABLE_SET; /*!< Offset: 0x028 Channel Enable Set Register (R/W) */
+ __O uint32_t CHNL_ENABLE_CLR; /*!< Offset: 0x02C Channel Enable Clear Register ( /W) */
+ __IO uint32_t CHNL_PRI_ALT_SET; /*!< Offset: 0x030 Channel Primary-Alterante Set Register (R/W) */
+ __O uint32_t CHNL_PRI_ALT_CLR; /*!< Offset: 0x034 Channel Primary-Alterante Clear Register ( /W) */
+ __IO uint32_t CHNL_PRIORITY_SET; /*!< Offset: 0x038 Channel Priority Set Register (R/W) */
+ __O uint32_t CHNL_PRIORITY_CLR; /*!< Offset: 0x03C Channel Priority Clear Register ( /W) */
+ uint32_t RESERVED0[3];
+ __IO uint32_t ERR_CLR; /*!< Offset: 0x04C Bus Error Clear Register (R/W) */
+
+} DMA_PL230_TypeDef;
+
+#define PL230_DMA_CHNL_BITS 0
+
+#define DMA_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< DMA_PL230 DMA STATUS: MSTREN Position */
+#define DMA_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << DMA_PL230_DMA_STATUS_MSTREN_Pos) /*!< DMA_PL230 DMA STATUS: MSTREN Mask */
+
+#define DMA_PL230_DMA_STATUS_STATE_Pos 0 /*!< DMA_PL230 DMA STATUS: STATE Position */
+#define DMA_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << DMA_PL230_DMA_STATUS_STATE_Pos) /*!< DMA_PL230 DMA STATUS: STATE Mask */
+
+#define DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< DMA_PL230 DMA STATUS: CHNLS_MINUS1 Position */
+#define DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< DMA_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
+
+#define DMA_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< DMA_PL230 DMA STATUS: TEST_STATUS Position */
+#define DMA_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << DMA_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< DMA_PL230 DMA STATUS: TEST_STATUS Mask */
+
+#define DMA_PL230_DMA_CFG_MSTREN_Pos 0 /*!< DMA_PL230 DMA CFG: MSTREN Position */
+#define DMA_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << DMA_PL230_DMA_CFG_MSTREN_Pos) /*!< DMA_PL230 DMA CFG: MSTREN Mask */
+
+#define DMA_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< DMA_PL230 DMA CFG: CPCCACHE Position */
+#define DMA_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCCACHE_Pos) /*!< DMA_PL230 DMA CFG: CPCCACHE Mask */
+
+#define DMA_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< DMA_PL230 DMA CFG: CPCBUF Position */
+#define DMA_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCBUF_Pos) /*!< DMA_PL230 DMA CFG: CPCBUF Mask */
+
+#define DMA_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< DMA_PL230 DMA CFG: CPCPRIV Position */
+#define DMA_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCPRIV_Pos) /*!< DMA_PL230 DMA CFG: CPCPRIV Mask */
+
+#define DMA_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< DMA_PL230 STATUS: BASE_PTR Position */
+#define DMA_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << DMA_PL230_CTRL_BASE_PTR_Pos) /*!< DMA_PL230 STATUS: BASE_PTR Mask */
+
+#define DMA_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< DMA_PL230 STATUS: MSTREN Position */
+#define DMA_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << DMA_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< DMA_PL230 STATUS: MSTREN Mask */
+
+#define DMA_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< DMA_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
+#define DMA_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << DMA_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< DMA_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
+
+#define DMA_PL230_CHNL_SW_REQUEST_Pos 0 /*!< DMA_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
+#define DMA_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_SW_REQUEST_Pos) /*!< DMA_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
+
+#define DMA_PL230_CHNL_USEBURST_SET_Pos 0 /*!< DMA_PL230 CHNL_USEBURST: SET Position */
+#define DMA_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_USEBURST_SET_Pos) /*!< DMA_PL230 CHNL_USEBURST: SET Mask */
+
+#define DMA_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< DMA_PL230 CHNL_USEBURST: CLR Position */
+#define DMA_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_USEBURST_CLR_Pos) /*!< DMA_PL230 CHNL_USEBURST: CLR Mask */
+
+#define DMA_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< DMA_PL230 CHNL_REQ_MASK: SET Position */
+#define DMA_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_REQ_MASK_SET_Pos) /*!< DMA_PL230 CHNL_REQ_MASK: SET Mask */
+
+#define DMA_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< DMA_PL230 CHNL_REQ_MASK: CLR Position */
+#define DMA_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< DMA_PL230 CHNL_REQ_MASK: CLR Mask */
+
+#define DMA_PL230_CHNL_ENABLE_SET_Pos 0 /*!< DMA_PL230 CHNL_ENABLE: SET Position */
+#define DMA_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_ENABLE_SET_Pos) /*!< DMA_PL230 CHNL_ENABLE: SET Mask */
+
+#define DMA_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< DMA_PL230 CHNL_ENABLE: CLR Position */
+#define DMA_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_ENABLE_CLR_Pos) /*!< DMA_PL230 CHNL_ENABLE: CLR Mask */
+
+#define DMA_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< DMA_PL230 CHNL_PRI_ALT: SET Position */
+#define DMA_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRI_ALT_SET_Pos) /*!< DMA_PL230 CHNL_PRI_ALT: SET Mask */
+
+#define DMA_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< DMA_PL230 CHNL_PRI_ALT: CLR Position */
+#define DMA_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< DMA_PL230 CHNL_PRI_ALT: CLR Mask */
+
+#define DMA_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< DMA_PL230 CHNL_PRIORITY: SET Position */
+#define DMA_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRIORITY_SET_Pos) /*!< DMA_PL230 CHNL_PRIORITY: SET Mask */
+
+#define DMA_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< DMA_PL230 CHNL_PRIORITY: CLR Position */
+#define DMA_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRIORITY_CLR_Pos) /*!< DMA_PL230 CHNL_PRIORITY: CLR Mask */
+
+#define DMA_PL230_ERR_CLR_Pos 0 /*!< DMA_PL230 ERR: CLR Position */
+#define DMA_PL230_ERR_CLR_Msk (0x00000001ul << DMA_PL230_ERR_CLR_Pos) /*!< DMA_PL230 ERR: CLR Mask */
+
+
+#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
+
+ /* Maximum to 32 DMA channel */
+ /* SRAM in example system is 64K bytes */
+#define RAM_ADDRESS_MAX 0x80001fff
+
+typedef struct /* 4 words */
+{
+ volatile unsigned char* SrcEndPointer;
+ volatile unsigned char* DstEndPointer;
+ volatile unsigned long Control;
+ volatile unsigned long unused;
+} dma_pl230_channel_data;
+
+
+typedef struct /* 8 words per channel */
+{ /* was one channel in the example uDMA setup */
+ volatile dma_pl230_channel_data Primary[MAX_NUM_OF_DMA_CHANNELS];
+ volatile dma_pl230_channel_data Alternate[MAX_NUM_OF_DMA_CHANNELS];
+} dma_pl230_data_structure;
+
+
+extern dma_pl230_data_structure *dma_pl230_table;
+
+#define DMA_PL230_DMAC ((DMA_PL230_TypeDef *) DMA_PL230_BASE)
+
+#define DMA_PL230_PTR_END(__ptr, __siz, __num) \
+ ((unsigned char *) __ptr + ((1<<__siz)*(__num-1)))
+
+#define DMA_PL230_CTRL(__cyc, __siz, __num, __rpwr) \
+ (((unsigned long) __siz << 30)|(__siz << 28)|(__siz << 26)|(__siz << 24)| \
+ (1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
+ (1 << 3)|(__cyc << 0) )
+
+#define DMA_PL230_CTRL_SRCFIX(__cyc, __siz, __num, __rpwr) \
+ (((unsigned long) __siz << 30)|(__siz << 28)|(0x0c000000UL)|(__siz << 24)| \
+ (1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
+ (1 << 3)|(__cyc << 0) )
+
+#define DMA_PL230_CTRL_DSTFIX(__cyc, __siz, __num, __rpwr) \
+ ((0xc0000000UL)|(__siz << 28)|(__siz << 26)|(__siz << 24)| \
+ (1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
+ (1 << 3)|(__cyc << 0) )
+
+#define DMA_PL230_MAX_XFERS (0x400)
+
+#define PL230_CTRL_CYCLE_STOP 0
+#define PL230_CTRL_CYCLE_BASIC 1
+#define PL230_CTRL_CYCLE_AUTO 2
+#define PL230_CTRL_CYCLE_PPONG 3
+#define PL230_CTRL_CYCLE_MEM_CHAIN_PRI 4
+#define PL230_CTRL_CYCLE_MEM_CHAIN_ALT 5
+#define PL230_CTRL_CYCLE_DEV_CHAIN_PRI 6
+#define PL230_CTRL_CYCLE_DEV_CHAIN_ALT 7
+
+#define PL230_CTRL_RPWR_1 0
+#define PL230_CTRL_RPWR_2 1
+#define PL230_CTRL_RPWR_4 2
+#define PL230_CTRL_RPWR_8 3
+#define PL230_CTRL_RPWR_16 4
+
+#define PL230_XFER_B 0
+#define PL230_XFER_H 1
+#define PL230_XFER_W 2
+
+/* --------------------------------------------------------------- */
+/* Initialize DMA data structure */
+/* --------------------------------------------------------------- */
+void dma_pl230_data_struct_init(void);
+
+/* --------------------------------------------------------------- */
+/* Initialize DMA PL230 */
+/* --------------------------------------------------------------- */
+void dma_pl230_init_dbg(unsigned int chan_mask);
+void dma_pl230_init(unsigned int chan_mask);
+
+/* --------------------------------------------------------------- */
+/* Check DMA PL230 DMA channel(s) active (return 0 when finishes) */
+/* --------------------------------------------------------------- */
+unsigned int dma_pl230_channel_active(unsigned int chan_mask);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __DMA_PL230_MCU_H */
+
diff --git a/system/testcodes/aes128_tests/makefile b/system/testcodes/aes128_tests/makefile
new file mode 100644
index 0000000..70938b9
--- /dev/null
+++ b/system/testcodes/aes128_tests/makefile
@@ -0,0 +1,258 @@
+#-----------------------------------------------------------------------------
+# The confidential and proprietary information contained in this file may
+# only be used by a person authorised under and to the extent permitted
+# by a subsisting licensing agreement from Arm Limited or its affiliates.
+#
+# (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
+# ALL RIGHTS RESERVED
+#
+# This entire notice must be reproduced on all copies of this file
+# and copies of this file may only be made by a person if such person is
+# permitted to do so under the terms of a subsisting license agreement
+# from Arm Limited or its affiliates.
+#
+# SVN Information
+#
+# Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
+#
+# Revision : $Revision: 371321 $
+#
+# Release Information : Cortex-M System Design Kit-r1p1-00rel0
+#-----------------------------------------------------------------------------
+#
+# Cortex-M System Design Kit software compilation make file
+#
+#-----------------------------------------------------------------------------
+#
+# Configurations
+#
+# Choose the core instantiated, can be
+# - CORTEX_M0
+# - CORTEX_M0PLUS
+CPU_PRODUCT = CORTEX_M0
+
+# Shared software directory
+SOFTWARE_DIR = $(SOCLABS_NANOSOC_TECH_DIR)/software
+CMSIS_DIR = $(SOFTWARE_DIR)/cmsis
+CORE_DIR = $(CMSIS_DIR)/CMSIS/Include
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0plus
+else
+ DEVICE_DIR = $(CMSIS_DIR)/Device/ARM/CMSDK_CM0
+endif
+
+# Program file
+TESTNAME = aes128_tests
+
+# Endian Option
+COMPILE_BIGEND = 0
+
+# Configuration
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ USER_DEFINE = -DCORTEX_M0PLUS
+else
+ USER_DEFINE = -DCORTEX_M0
+endif
+
+DEPS_LIST = makefile
+
+# Tool chain : ds5 / gcc / keil
+TOOL_CHAIN = ds5
+
+ifeq ($(TOOL_CHAIN),ds5)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = --cpu Cortex-M0plus
+ else
+ CPU_TYPE = --cpu Cortex-M0
+ endif
+endif
+
+ifeq ($(TOOL_CHAIN),gcc)
+ ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ CPU_TYPE = -mcpu=cortex-m0plus
+ else
+ CPU_TYPE = -mcpu=cortex-m0
+ endif
+endif
+
+# Startup code directory for DS-5
+ifeq ($(TOOL_CHAIN),ds5)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/ARM
+endif
+
+# Startup code directory for gcc
+ifeq ($(TOOL_CHAIN),gcc)
+ STARTUP_DIR = $(DEVICE_DIR)/Source/GCC
+endif
+
+ifeq ($(CPU_PRODUCT),CORTEX_M0PLUS)
+ STARTUP_FILE = startup_CMSDK_CM0plus
+ SYSTEM_FILE = system_CMSDK_CM0plus
+else
+ STARTUP_FILE = startup_CMSDK_CM0
+ SYSTEM_FILE = system_CMSDK_CM0
+endif
+
+# ---------------------------------------------------------------------------------------
+# DS-5 options
+
+# MicroLIB option
+COMPILE_MICROLIB = 0
+
+# Small Multiply (Cortex-M0/M0+ has small multiplier option)
+COMPILE_SMALLMUL = 0
+
+#ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+# -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+#ARM_ASM_OPTIONS = -g
+#ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+# --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
+
+ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ARM_ASM_OPTIONS =
+ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
+ --no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ ARM_CC_OPTIONS += --bigend
+ ARM_ASM_OPTIONS += --bigend
+ ARM_LINK_OPTIONS += --be8
+endif
+
+ifeq ($(COMPILE_MICROLIB),1)
+ # MicroLIB
+ ARM_CC_OPTIONS += --library_type=microlib
+ ARM_ASM_OPTIONS += --library_type=microlib --pd "__MICROLIB SETA 1"
+ ARM_LINK_OPTIONS += --library_type=microlib
+endif
+
+ifeq ($(COMPILE_SMALLMUL),1)
+ # In Cortex-M0, small multiply takes 32 cycles
+ ARM_CC_OPTIONS += --multiply_latency=32
+endif
+
+# ---------------------------------------------------------------------------------------
+# gcc options
+
+GNG_CC = arm-none-eabi-gcc
+GNU_OBJDUMP = arm-none-eabi-objdump
+GNU_OBJCOPY = arm-none-eabi-objcopy
+
+LINKER_SCRIPT_PATH = $(SOFTWARE_DIR)/common/scripts
+LINKER_SCRIPT = $(LINKER_SCRIPT_PATH)/cmsdk_cm0.ld
+
+GNU_CC_FLAGS = -g -O3 -mthumb $(CPU_TYPE)
+
+ifeq ($(COMPILE_BIGEND),1)
+ # Big Endian
+ GNU_CC_FLAGS += -mbig-endian
+endif
+
+# ---------------------------------------------------------------------------------------
+all: all_$(TOOL_CHAIN)
+
+# ---------------------------------------------------------------------------------------
+# DS-5
+all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
+
+$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+dma_pl230_driver.o : dma_pl230_driver.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+retarget.o : $(SOFTWARE_DIR)/common/retarget/retarget.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+uart_stdout.o : $(SOFTWARE_DIR)/common/retarget/uart_stdout.c $(DEPS_LIST)
+ armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(STARTUP_FILE).o : $(STARTUP_DIR)/$(STARTUP_FILE).s $(DEPS_LIST)
+ armasm $(ARM_ASM_OPTIONS) $(CPU_TYPE) $< -o $@
+
+$(TESTNAME).ELF : $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+ armlink $(ARM_LINK_OPTIONS) -o $@ $(TESTNAME).o dma_pl230_driver.o $(SYSTEM_FILE).o $(STARTUP_FILE).o retarget.o uart_stdout.o
+
+$(TESTNAME).hex : $(TESTNAME).ELF
+ fromelf --vhx --8x1 $< --output $@
+
+$(TESTNAME).lst : $(TESTNAME).ELF
+ fromelf -c -d -e -s -z -v $< --output $@
+
+# ---------------------------------------------------------------------------------------
+# gcc
+all_gcc:
+ $(GNG_CC) $(GNU_CC_FLAGS) $(STARTUP_DIR)/$(STARTUP_FILE).s \
+ $(TESTNAME).c \
+ $(SOFTWARE_DIR)/common/retarget/retarget.c \
+ $(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
+ $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
+ -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -L $(LINKER_SCRIPT_PATH) \
+ -D__STACK_SIZE=0x200 \
+ -D__HEAP_SIZE=0x1000 \
+ $(USER_DEFINE) -T $(LINKER_SCRIPT) -o $(TESTNAME).o
+ # Generate disassembly code
+ $(GNU_OBJDUMP) -S $(TESTNAME).o > $(TESTNAME).lst
+ # Generate binary file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O binary $(TESTNAME).bin
+ # Generate hex file
+ $(GNU_OBJCOPY) -S $(TESTNAME).o -O verilog $(TESTNAME).hex
+
+# Note:
+# If the version of object copy you are using does not support verilog hex file output,
+# you can generate the hex file from binary file using the following command
+# od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+
+# ---------------------------------------------------------------------------------------
+# Keil MDK
+
+all_keil:
+ @echo "Please compile your project code and press ENTER when ready"
+ @read dummy
+
+# ---------------------------------------------------------------------------------------
+# Binary
+
+all_bin: $(TESTNAME).bin
+ # Generate hex file from binary
+ od -v -A n -t x1 --width=1 $(TESTNAME).bin > $(TESTNAME).hex
+
+# ---------------------------------------------------------------------------------------
+# Clean
+clean :
+ @rm -rf *.o
+ @if [ -e $(TESTNAME).hex ] ; then \
+ rm -rf $(TESTNAME).hex ; \
+ fi
+ @if [ -e $(TESTNAME).lst ] ; then \
+ rm -rf $(TESTNAME).lst ; \
+ fi
+ @if [ -e $(TESTNAME).ELF ] ; then \
+ rm -rf $(TESTNAME).ELF ; \
+ fi
+ @if [ -e $(TESTNAME).bin ] ; then \
+ rm -rf $(TESTNAME).bin ; \
+ fi
+ @rm -rf *.crf
+ @rm -rf *.plg
+ @rm -rf *.tra
+ @rm -rf *.htm
+ @rm -rf *.map
+ @rm -rf *.dep
+ @rm -rf *.d
+ @rm -rf *.lnp
+ @rm -rf *.bak
+ @rm -rf *.lst
+ @rm -rf *.axf
+ @rm -rf *.sct
+ @rm -rf *.__i
+ @rm -rf *._ia
diff --git a/system/testcodes/software_list.txt b/system/testcodes/software_list.txt
new file mode 100644
index 0000000..c5f79c4
--- /dev/null
+++ b/system/testcodes/software_list.txt
@@ -0,0 +1 @@
+aes128_tests
\ No newline at end of file
--
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