diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 147e2a5fe2aa6c42e2b16e303f08976d6d7bddd7..1850a7a3616273fc8bac18eaac7350225b07ff65 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -17,6 +17,7 @@ # https://gitlab.com/gitlab-org/gitlab/-/blob/master/lib/gitlab/ci/templates/Getting-Started.gitlab-ci.yml stages: # List of stages for jobs, and their order of execution + - compile - simulate - build - deploy @@ -25,6 +26,20 @@ variables: GIT_SUBMODULE_STRATEGY: recursive GIT_SUBMODULE_FORCE_HTTPS: "true" +compile-software: + stage: compile + script: + - echo "Compilation phase started" + - git submodule foreach --recursive git submodule init + - git fetch --recurse-submodules + - source set_env.sh + - cd $SOCLABS_NANOSOC_TECH_DIR + - make compile_all_code + artifacts: + paths: + - ./simulate/sim/*/*.hex + tags: + - ds5 simulate-hello: stage: simulate @@ -52,9 +67,9 @@ build-job-Z2: # This job runs in the build stage, which runs first. - git submodule foreach --recursive git submodule init - git fetch --recurse-submodules - source set_env.sh - - cd ./nanosoc_tech/fpga/ + - cd $SOCLABS_NANOSOC_TECH_DIR/fpga/ - make build_fpga FPGA=z2 - - FILE=../../imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit + - FILE=$SOCLABS_DESIGN_ROOT/imp/fpga/output/pynq_z2/overlays/nanosoc_design.bit - if test -f "$FILE"; then - echo "Build successful" - else @@ -76,9 +91,9 @@ build-job-ZCU104: # This job runs in the build stage, which runs first. - git submodule foreach --recursive git submodule init - git fetch --recurse-submodules - source set_env.sh - - cd ./nanosoc_tech/fpga + - cd $SOCLABS_NANOSOC_TECH_DIR/fpga - make build_fpga FPGA=zcu104 - - FILE=../../imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit + - FILE=$SOCLABS_DESIGN_ROOT/imp/fpga/output/pynq_zcu104/overlays/nanosoc_design.bit - if test -f "$FILE"; then - echo "Build successful" - else @@ -199,7 +214,7 @@ deploy-job-ZCU104: # This job runs in the deploy stage. - screen -r zynq -X stuff "deactivate \n" - screen -r zynq -X stuff "exit \n" # test the screenlog for "Overlay Loaded" - - cp ./nanosoc/fpga_imp/CI_verification/test_bitfile_ZCU104.sh ./ + - cp ./nanosoc_tech/fpga/ci_tools/test_bitfile_ZCU104.sh ./ - chmod +x test_bitfile_ZCU104.sh - ./test_bitfile_ZCU104.sh diff --git a/nanosoc_tech b/nanosoc_tech index 5c65b9856a4025b2ddc57fffaf76297ce9d19b67..b36f7041c7c96e7af7ed10647a667ee319f440ce 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit 5c65b9856a4025b2ddc57fffaf76297ce9d19b67 +Subproject commit b36f7041c7c96e7af7ed10647a667ee319f440ce