From 38572d40f85b06c31ff765ece254fb38352b9e3f Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Fri, 26 May 2023 10:59:16 +0100
Subject: [PATCH] SOC1-223: Update enviroment variable names

---
 README.md                                  |  2 +-
 env/dependency_env.sh                      | 16 ++++-----
 flist/dma-230/pl230_ip.flist               |  2 +-
 flist/generic_lib/generic_lib_ip.flist     | 14 ++++----
 flist/nanosoc/nanosoc_chip_ip.flist        | 26 +++++++--------
 flist/nanosoc/nanosoc_matrix_ip.flist      |  4 +--
 flist/nanosoc/nanosoc_tb.flist             | 20 ++++++------
 flist/nanosoc/nanosoc_test_io_ip.flist     |  6 ++--
 flist/primitives/primitives.flist          |  6 ++--
 flist/project/system.flist                 | 32 +++++++++---------
 flist/project/wrapper.flist                |  8 ++---
 flist/wrapper/wrapper_ip.flist             | 24 +++++++-------
 flow/stimgen.py                            | 10 +++---
 nanosoc_tech                               |  2 +-
 set_env.sh                                 | 38 +++++++++++-----------
 simulate/socsim/bootrom.sh                 |  6 ++--
 simulate/socsim/system_secworks_sha256.sh  |  8 ++---
 simulate/socsim/wrapper_secworks_sha256.sh | 24 +++++++-------
 soctools_flow                              |  2 +-
 19 files changed, 125 insertions(+), 125 deletions(-)

diff --git a/README.md b/README.md
index babc4e8..adaf8ae 100644
--- a/README.md
+++ b/README.md
@@ -34,7 +34,7 @@ This checks out all the repositories to the `main` branch. You are then able to
 
 After setting up your workarea, you now need to add your accelerator design repository as a subrepo.
 
-From `$DESIGN_ROOT`, you are able to run:
+From `$SOCLABS_DESIGN_ROOT`, you are able to run:
 
 `git submodule status` 
 
diff --git a/env/dependency_env.sh b/env/dependency_env.sh
index bcde818..f76f37f 100755
--- a/env/dependency_env.sh
+++ b/env/dependency_env.sh
@@ -15,29 +15,29 @@
 #-----------------------------------------------------------------------------
 
 # Accelerator Engine -- Add Your Accelerator Environment Variable HERE!
-# export YOUR_ACCELERATOR_DIR="$PROJECT_DIR/your_accelerator"
+# export YOUR_ACCELERATOR_DIR="$SOCLABS_PROJECT_DIR/your_accelerator"
 
 # Accelerator Wrapper
-export WRAPPER_TECH_DIR="$PROJECT_DIR/accelerator_wrapper_tech"
+export SOCLABS_WRAPPER_TECH_DIR="$SOCLABS_PROJECT_DIR/accelerator_wrapper_tech"
 
 # NanoSoC
-export NANOSOC_TECH_DIR="$PROJECT_DIR/nanosoc_tech"
+export SOCLABS_NANOSOC_TECH_DIR="$SOCLABS_PROJECT_DIR/nanosoc_tech"
 
 # Primtives
-export PRIMITIVES_TECH_DIR="$PROJECT_DIR/rtl_primitives_tech"
+export SOCLABS_PRIMITIVES_TECH_DIR="$SOCLABS_PROJECT_DIR/rtl_primitives_tech"
 
 # FPGA Libraries
-export FPGA_LIB_TECH_DIR="$PROJECT_DIR/fpga_lib_tech"
+export SOCLABS_FPGA_LIB_TECH_DIR="$SOCLABS_PROJECT_DIR/fpga_lib_tech"
 
 # Generic Libraries
-export GENERIC_LIB_TECH_DIR="$PROJECT_DIR/generic_lib_tech"
+export SOCLABS_GENERIC_LIB_TECH_DIR="$SOCLABS_PROJECT_DIR/generic_lib_tech"
 
 #-----------------------------------------------------------------------------
 # Flows
 #-----------------------------------------------------------------------------
 
 # SoCTools - Toolkit of scripts related to SoCLabs projects
-export SOCTOOLS_FLOW_DIR="$PROJECT_DIR/soctools_flow"
+export SOCLABS_SOCTOOLS_FLOW_DIR="$SOCLABS_PROJECT_DIR/soctools_flow"
 
 # CHIPKIT - Register Generation
-export CHIPKIT_FLOW_DIR="$SOCTOOLS_FLOW_DIR/tools/chipkit_flow"
+export SOCLABS_CHIPKIT_FLOW_DIR="$SOCLABS_SOCTOOLS_FLOW_DIR/tools/chipkit_flow"
diff --git a/flist/dma-230/pl230_ip.flist b/flist/dma-230/pl230_ip.flist
index 978f427..8c862a5 100644
--- a/flist/dma-230/pl230_ip.flist
+++ b/flist/dma-230/pl230_ip.flist
@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    DMA-230 search path    =============
-+incdir+$(PROJECT_DIR)/system/defines/pl230
++incdir+$(SOCLABS_PROJECT_DIR)/system/defines/pl230
 
 $(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_ahb_ctrl.v
 $(ARM_IP_LIBRARY_PATH)/latest/DMA-230/logical/pl230_apb_regs.v
diff --git a/flist/generic_lib/generic_lib_ip.flist b/flist/generic_lib/generic_lib_ip.flist
index 0ff3038..3995db3 100644
--- a/flist/generic_lib/generic_lib_ip.flist
+++ b/flist/generic_lib/generic_lib_ip.flist
@@ -16,10 +16,10 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
-$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
-$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
-$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
-$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
-$(GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
-$(GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v
-$(GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_INOUT8MA_NOE.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDIO.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSSIO.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VDDSOC.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/pads/verilog/PAD_VSS.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/mem/verilog/SROM_Ax32.v
+$(SOCLABS_GENERIC_LIB_TECH_DIR)/sync/verilog/SYNCHRONIZER_EDGES.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_chip_ip.flist b/flist/nanosoc/nanosoc_chip_ip.flist
index c7b49e1..fc7bb4a 100644
--- a/flist/nanosoc/nanosoc_chip_ip.flist
+++ b/flist/nanosoc/nanosoc_chip_ip.flist
@@ -16,19 +16,19 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_chip_pads.v
 
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_subsystem.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_cpu.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sysio.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_sys_ahb_decode.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_subsystem.v
 
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_cs_rom_table.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_pin_mux.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_stclkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
 
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_matrix_ip.flist b/flist/nanosoc/nanosoc_matrix_ip.flist
index a9bbcb2..00a82ce 100644
--- a/flist/nanosoc/nanosoc_matrix_ip.flist
+++ b/flist/nanosoc/nanosoc_matrix_ip.flist
@@ -16,6 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Bus Matrix IP search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix
 
--y $(NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix
\ No newline at end of file
+-y $(SOCLABS_NANOSOC_TECH_DIR)/system/src/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist
index e5438e8..893b1b2 100644
--- a/flist/nanosoc/nanosoc_tb.flist
+++ b/flist/nanosoc/nanosoc_tb.flist
@@ -16,18 +16,18 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Testbench search path    =============
-+incdir+$(NANOSOC_TECH_DIR)/system/verif/verilog/
++incdir+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/
 
 // - Top-level testbench
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_tb.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_tb.v
 
 // - Testbench components
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
 
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_test_io_ip.flist b/flist/nanosoc/nanosoc_test_io_ip.flist
index d0094ed..5df3c3d 100644
--- a/flist/nanosoc/nanosoc_test_io_ip.flist
+++ b/flist/nanosoc/nanosoc_test_io_ip.flist
@@ -16,6 +16,6 @@
 +libext+.v+.vlib
 
 // =============    NanoSoC Chip Test Interface IP Filelists   =============
-$(NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_control_v1_0.v
-$(NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_manager.v
-$(NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
\ No newline at end of file
+$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_control_v1_0.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_adp_manager.v
+$(SOCLABS_NANOSOC_TECH_DIR)/system/test_io/verilog/nanosoc_ft1248_stream_io_v1_0.v
\ No newline at end of file
diff --git a/flist/primitives/primitives.flist b/flist/primitives/primitives.flist
index 807360c..bb0e871 100644
--- a/flist/primitives/primitives.flist
+++ b/flist/primitives/primitives.flist
@@ -16,7 +16,7 @@
 +libext+.v+.vlib
 
 // =============    RTL Primitives search path    =============
--y $(PRIMITIVES_TECH_DIR)/src/sv/
-+incdir+$(PRIMITIVES_TECH_DIR)/src/sv/
+-y $(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
++incdir+$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/
 
-$(PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv
+$(SOCLABS_PRIMITIVES_TECH_DIR)/src/sv/fifo_vr.sv
diff --git a/flist/project/system.flist b/flist/project/system.flist
index c8bf33e..2262842 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -19,49 +19,49 @@
 
 // =============    Accelerator Module search path    =============
 // ! Point this to your accelerator filelist
-// -f $(PROJECT_DIR)/flist/project/accelerator.flist
+// -f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
 
 // =============    Wrapper Filelist      =========================
--f $(PROJECT_DIR)/flist/project/wrapper.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/wrapper.flist
 
 // =============    System Component Filelist      ================
 
 // - Primitives IP
--f $(PROJECT_DIR)/flist/primitives/primitives.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/primitives/primitives.flist
 
 // - CMSDK IP
--f $(PROJECT_DIR)/flist/ahb/ahb_ip.flist
--f $(PROJECT_DIR)/flist/apb/apb_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/ahb/ahb_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/apb/apb_ip.flist
 
 // - NanoSoC Chip IP
--f $(PROJECT_DIR)/flist/nanosoc/nanosoc_chip_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_chip_ip.flist
 
 // - NanoSoC Bus Matrix
--f $(PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist
 
 // - NanoSoc Test Interface IP
--f $(PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_test_io_ip.flist
 
 // - Generic Pad Library
--f $(PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
 
 // - CMSDK VIP
--f $(PROJECT_DIR)/flist/corstone-101/corstone-101_vip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_vip.flist
 
 // - Corstone-101 System components
--f $(PROJECT_DIR)/flist/corstone-101/corstone-101_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/corstone-101/corstone-101_ip.flist
 
 // - DMA controller
--f $(PROJECT_DIR)/flist/dma-230/pl230_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/dma-230/pl230_ip.flist
 
 // - Cortex-M0 IP
--f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
 
 // - NanoSoC Custom Expansion Region
-$(PROJECT_DIR)/system/src/nanosoc_exp.v
+$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v
 
 // - Top level
--f $(PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
 
 // =============    Bootrom Filelist      ================
-$(PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
diff --git a/flist/project/wrapper.flist b/flist/project/wrapper.flist
index 2122cf0..f553705 100644
--- a/flist/project/wrapper.flist
+++ b/flist/project/wrapper.flist
@@ -18,11 +18,11 @@
 +libext+.v+.vlib
 
 // =============    Wrapper IP Filelist    ========================
--f $(PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
 
 // =============    Accelerator Module search path    =============
--y $(PROJECT_DIR)/wrapper/src/
-+incdir+$(PROJECT_DIR)/wrapper/src/
+-y $(SOCLABS_PROJECT_DIR)/wrapper/src/
++incdir+$(SOCLABS_PROJECT_DIR)/wrapper/src/
 
 // Add the source files related to your custom wrapper
-// $(PROJECT_DIR)/wrapper/src/your_wrapper.v
+// $(SOCLABS_PROJECT_DIR)/wrapper/src/your_wrapper.v
diff --git a/flist/wrapper/wrapper_ip.flist b/flist/wrapper/wrapper_ip.flist
index 3304718..1e406b8 100644
--- a/flist/wrapper/wrapper_ip.flist
+++ b/flist/wrapper/wrapper_ip.flist
@@ -16,17 +16,17 @@
 +libext+.v+.vlib
 
 // =============    Accelerator Module search path    =============
--y $(WRAPPER_TECH_DIR)/hdl/src/
-+incdir+$(WRAPPER_TECH_DIR)/hdl/src/
+-y $(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/
++incdir+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/
 
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_constructor.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_packet_deconstructor.sv
 
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv
-$(WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_addr_calc.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_data_req.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv
+$(SOCLABS_WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv
diff --git a/flow/stimgen.py b/flow/stimgen.py
index 1039895..996b738 100755
--- a/flow/stimgen.py
+++ b/flow/stimgen.py
@@ -107,7 +107,7 @@ def stimulus_generation(stim_file, ref_file, input_start_address, input_size, ou
     calculates write addresses for each word and generates a .fri file which
     can be used to stimulate an AHB testbench
     """
-    fri_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.fri"
+    fri_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.fri"
 
     if gen_fri:
         # Calculate End Address
@@ -193,14 +193,14 @@ def stimulus_generation(stim_file, ref_file, input_start_address, input_size, ou
 
 
         # Generate ADP Command File with Write Transactions
-        adp_file = os.environ["PROJECT_DIR"] + "/system/stimulus/" + "adp_hash_stim.cmd"
+        adp_file = os.environ["SOCLABS_PROJECT_DIR"] + "/system/stimulus/" + "adp_hash_stim.cmd"
         adp_output(adp_file, output_word_list)
 
         # Generate FRI File with Write Transactions
         fri_output(fri_file, output_word_list)
 
     # Call fm2conv.pl script
-    m2d_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.m2d"
+    m2d_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.m2d"
     os.system(f"fm2conv.pl -busWidth=32 -infile={fri_file} -outfile={m2d_file}")
 
 
@@ -209,6 +209,6 @@ if __name__ == "__main__":
     accelerator_input_size =     0x0000_0400
     accelerator_output_address = 0x6001_0400
     accelerator_output_size =    0x0000_0400
-    stim_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "input_block_32bit_stim.csv"
-    ref_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "output_hash_32bit_ref.csv"
+    stim_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "input_block_32bit_stim.csv"
+    ref_file = os.environ["SOCLABS_PROJECT_DIR"] + "/wrapper/stimulus/" + "output_hash_32bit_ref.csv"
     stimulus_generation(stim_file, ref_file, accelerator_input_address, accelerator_input_size, accelerator_output_address, accelerator_output_size, gen_fri=False)
\ No newline at end of file
diff --git a/nanosoc_tech b/nanosoc_tech
index 263c129..91ce5d7 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 263c129eee99942b27c5c6199ec91b81c85021c3
+Subproject commit 91ce5d7d85e099cdaf3194a97795c439c27fdd1c
diff --git a/set_env.sh b/set_env.sh
index e7025e8..8304f5c 100755
--- a/set_env.sh
+++ b/set_env.sh
@@ -11,33 +11,33 @@
 #!/bin/bash
 
 # Get Root Location of Design Structure
-if [ -z $DESIGN_ROOT ]; then
-    # If $DESIGN_ROOT hasn't been set yet
-    DESIGN_ROOT=`git rev-parse --show-superproject-working-tree`
+if [ -z $SOCLABS_DESIGN_ROOT ]; then
+    # If $SOCLABS_DESIGN_ROOT hasn't been set yet
+    SOCLABS_DESIGN_ROOT=`git rev-parse --show-superproject-working-tree`
 
-    if [ -z $DESIGN_ROOT ]; then
+    if [ -z $SOCLABS_DESIGN_ROOT ]; then
         # If not in a submodule - at root
-        DESIGN_ROOT=`git rev-parse --show-toplevel`
+        SOCLABS_DESIGN_ROOT=`git rev-parse --show-toplevel`
     fi
 
     # Source Top-Level Sourceme
-    source $DESIGN_ROOT/set_env.sh
+    source $SOCLABS_DESIGN_ROOT/set_env.sh
 else
     # Set Environment Variable for this Repository
-    export PROJECT_DIR="$(cd -P "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
+    export SOCLABS_PROJECT_DIR="$(cd -P "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
 
     # If this Repo is root of workspace
-    if [ $PROJECT_DIR = $DESIGN_ROOT ]; then
-        echo "Design Workspace: $DESIGN_ROOT" 
-        export DESIGN_ROOT
+    if [ $SOCLABS_PROJECT_DIR = $SOCLABS_DESIGN_ROOT ]; then
+        echo "Design Workspace: $SOCLABS_DESIGN_ROOT" 
+        export SOCLABS_DESIGN_ROOT
     fi
 
     # Add in location for socsim scripts
-    export SOCSIM_PATH=$PROJECT_DIR/simulate/socsim
+    export SOCLABS_SOCSIM_PATH=$SOCLABS_PROJECT_DIR/simulate/socsim
     
 
     # Source dependency environment variable script
-    source $PROJECT_DIR/env/dependency_env.sh
+    source $SOCLABS_PROJECT_DIR/env/dependency_env.sh
 
     # Add Scripts to Path
     # "TECH_DIR"
@@ -50,23 +50,23 @@ else
         eval PATH="$PATH:\$${line}/tools"
     done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep FLOW_DIR)"
 
-    # "PROJECT_DIR"
+    # "SOCLABS_PROJECT_DIR"
     while read line; do 
         eval PATH="$PATH:\$${line}/flow"
-    done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep PROJECT_DIR)"
+    done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep SOCLABS_PROJECT_DIR)"
 
     export PATH
 fi
 
 # Check cloned repository has been initialised
-if [ ! -f $PROJECT_DIR/.socinit ]; then
+if [ ! -f $SOCLABS_PROJECT_DIR/.socinit ]; then
     echo "Running First Time Repository Initialisation"
     # Source environment variables for all submodules
-    cd $DESIGN_ROOT
+    cd $SOCLABS_DESIGN_ROOT
     git submodule update --remote --recursive
     git submodule foreach --recursive git checkout main
     # Read proj-branch file to find out which branch each subrepo needs to be on
-    git config --file .gitmodules --get-regexp path | awk '{ print $2 }' | while read line; do cd $PROJECT_DIR/$line && git checkout `grep $line $PROJECT_DIR/proj-branch | awk '{ print $2 }'` && git pull; done
-    git restore $DESIGN_ROOT/.gitmodules
-    touch $PROJECT_DIR/.socinit
+    git config --file .gitmodules --get-regexp path | awk '{ print $2 }' | while read line; do cd $SOCLABS_PROJECT_DIR/$line && git checkout `grep $line $SOCLABS_PROJECT_DIR/proj-branch | awk '{ print $2 }'` && git pull; done
+    git restore $SOCLABS_DESIGN_ROOT/.gitmodules
+    touch $SOCLABS_PROJECT_DIR/.socinit
 fi
\ No newline at end of file
diff --git a/simulate/socsim/bootrom.sh b/simulate/socsim/bootrom.sh
index bf938b9..f2357a6 100755
--- a/simulate/socsim/bootrom.sh
+++ b/simulate/socsim/bootrom.sh
@@ -15,15 +15,15 @@
 SIM_NAME=`basename -s .sh "$0"`
 
 # Directory to put simulation files
-SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
+SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
 
 # Create Directory to put simulation files
 mkdir -p $SIM_DIR
-cd $PROJECT_DIR/simulate/sim/system_secworks_sha256
+cd $SOCLABS_PROJECT_DIR/simulate/sim/system_secworks_sha256
 
 # Compile Simulation
 # Call makefile in NanoSoC Repo with options
 echo ${2}
-make -C $NANOSOC_TECH_DIR/system bootrom \
+make -C $SOCLABS_NANOSOC_TECH_DIR/system bootrom \
     SIM_DIR=$SIM_DIR \
 
diff --git a/simulate/socsim/system_secworks_sha256.sh b/simulate/socsim/system_secworks_sha256.sh
index 339422a..e7a53ab 100755
--- a/simulate/socsim/system_secworks_sha256.sh
+++ b/simulate/socsim/system_secworks_sha256.sh
@@ -15,17 +15,17 @@
 SIM_NAME=`basename -s .sh "$0"`
 
 # Directory to put simulation files
-SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
+SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
 
 # Create Directory to put simulation files
 mkdir -p $SIM_DIR
-cd $PROJECT_DIR/simulate/sim/system_secworks_sha256
+cd $SOCLABS_PROJECT_DIR/simulate/sim/system_secworks_sha256
 
 # Compile Simulation
 # Call makefile in NanoSoC Repo with options
 echo ${2}
-make -C $NANOSOC_TECH_DIR/system run_xm \
+make -C $SOCLABS_NANOSOC_TECH_DIR/system run_xm \
     SIM_DIR=$SIM_DIR \
-    ADP_FILE=$PROJECT_DIR/system/stimulus/adp_hash_stim.cmd \
+    ADP_FILE=$SOCLABS_PROJECT_DIR/system/stimulus/adp_hash_stim.cmd \
     ${@:2}
 
diff --git a/simulate/socsim/wrapper_secworks_sha256.sh b/simulate/socsim/wrapper_secworks_sha256.sh
index 0007d9c..2ac6f86 100755
--- a/simulate/socsim/wrapper_secworks_sha256.sh
+++ b/simulate/socsim/wrapper_secworks_sha256.sh
@@ -14,24 +14,24 @@
 # Generate Stimulus from stimulus generation Script
 # python3 $SECWORKS_SHA2_TECH_DIR/flow/stimgen.py
 # Create Simulatiom Directory to Run in
-mkdir -p $PROJECT_DIR/simulate/sim/ 
-mkdir -p $PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
+mkdir -p $SOCLABS_PROJECT_DIR/simulate/sim/ 
+mkdir -p $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
 
-cd $PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
+cd $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256
 # Compile Simulation
 xrun \
     -64bit \
     -sv \
     -timescale 1ps/1ps \
     +access+r \
-    -f $PROJECT_DIR/flist/primatives.flist \
-    -f $PROJECT_DIR/flist/wrapper_ip.flist \
-    -f $PROJECT_DIR/flist/ahb_ip.flist \
-    -f $PROJECT_DIR/flist/apb_ip.flist \
-    -f $PROJECT_DIR/flist/wrapper.flist \
-    -f $PROJECT_DIR/flist/ahb_vip.flist \
-    -f $PROJECT_DIR/flist/secworks_sha25_stream.flist \
-    -xmlibdirname $PROJECT_DIR/simulate/sim/wrapper_secworks_sha256 \
-    $PROJECT_DIR/wrapper/verif/tb_wrapper_secworks_sha256.sv \
+    -f $SOCLABS_PROJECT_DIR/flist/primatives.flist \
+    -f $SOCLABS_PROJECT_DIR/flist/wrapper_ip.flist \
+    -f $SOCLABS_PROJECT_DIR/flist/ahb_ip.flist \
+    -f $SOCLABS_PROJECT_DIR/flist/apb_ip.flist \
+    -f $SOCLABS_PROJECT_DIR/flist/wrapper.flist \
+    -f $SOCLABS_PROJECT_DIR/flist/ahb_vip.flist \
+    -f $SOCLABS_PROJECT_DIR/flist/secworks_sha25_stream.flist \
+    -xmlibdirname $SOCLABS_PROJECT_DIR/simulate/sim/wrapper_secworks_sha256 \
+    $SOCLABS_PROJECT_DIR/wrapper/verif/tb_wrapper_secworks_sha256.sv \
     -gui \
     -top tb_wrapper_secworks_sha256
\ No newline at end of file
diff --git a/soctools_flow b/soctools_flow
index 93edf21..e5b63d6 160000
--- a/soctools_flow
+++ b/soctools_flow
@@ -1 +1 @@
-Subproject commit 93edf21c102f6267d34c0ff6b5175104b3354902
+Subproject commit e5b63d6e283f277a79947bcd4a616e4bf3ebadd9
-- 
GitLab