From 19dcbeaa74274870fef4d2400dd11e7961354ce5 Mon Sep 17 00:00:00 2001 From: dam1n19 <dam1n19@soton.ac.uk> Date: Fri, 23 Jun 2023 16:53:06 +0100 Subject: [PATCH] Updated branch reference for nanosoc --- flist/mem/fpga_mem.flist | 2 +- flist/project/system.flist | 6 ------ flist/project/system_tb.flist | 30 ++++++++++++++++++++++++++++++ fpga_lib_tech | 2 +- nanosoc_tech | 2 +- proj-branch | 2 +- soctools_flow | 2 +- 7 files changed, 35 insertions(+), 11 deletions(-) create mode 100644 flist/project/system_tb.flist diff --git a/flist/mem/fpga_mem.flist b/flist/mem/fpga_mem.flist index 7d33d33..c59cc67 100644 --- a/flist/mem/fpga_mem.flist +++ b/flist/mem/fpga_mem.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= --incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ +// -incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ // - Top-level testbench $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v \ No newline at end of file diff --git a/flist/project/system.flist b/flist/project/system.flist index 5c53c0f..bc981cd 100644 --- a/flist/project/system.flist +++ b/flist/project/system.flist @@ -42,15 +42,9 @@ // - Generic Pad Library -f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist -// - CMSDK VIP --f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist - // - NanoSoC Custom Expansion Region //$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v -// - Top level --f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist - // - FPGA sram -f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist diff --git a/flist/project/system_tb.flist b/flist/project/system_tb.flist new file mode 100644 index 0000000..f715788 --- /dev/null +++ b/flist/project/system_tb.flist @@ -0,0 +1,30 @@ +//----------------------------------------------------------------------------- +// Accelerator System Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Top-level Accelerator System +//----------------------------------------------------------------------------- + +// DESIGN_TOP nanosoc_tb + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= System Component Filelist ================ + +// - CMSDK VIP +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist + +// - Design +-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist + +// - Top level +-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist + diff --git a/fpga_lib_tech b/fpga_lib_tech index 3e6eea8..4344fb7 160000 --- a/fpga_lib_tech +++ b/fpga_lib_tech @@ -1 +1 @@ -Subproject commit 3e6eea8f70104378841ddb7032399cebcf43686f +Subproject commit 4344fb7198daaae6d40f95b58587af5f869263a2 diff --git a/nanosoc_tech b/nanosoc_tech index cb7b26a..6baa3fc 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit cb7b26aa5a553766cc90e513d146f6cfd7ac9142 +Subproject commit 6baa3fcaed83d29214b97c74d5c92627e152a41a diff --git a/proj-branch b/proj-branch index c8662e9..d004de0 100644 --- a/proj-branch +++ b/proj-branch @@ -12,7 +12,7 @@ # Project Repository Subrepository Branch Index # Add your Accelerator Repository here # accelerator_repo: main -nanosoc_tech: main +nanosoc_tech: feat_nanosoc_regions accelerator_wrapper_tech: main fpga_lib_tech: main generic_lib_tech: main diff --git a/soctools_flow b/soctools_flow index ce9edaa..1c70675 160000 --- a/soctools_flow +++ b/soctools_flow @@ -1 +1 @@ -Subproject commit ce9edaa78fac0d09ad9466e4bc159e999483fd12 +Subproject commit 1c706759aebfbd539a9f035e94737975e00dd5dd -- GitLab