diff --git a/flist/mem/fpga_mem.flist b/flist/mem/fpga_mem.flist index 7d33d33da563e9e6310a10dad7805712419e45cd..c59cc67ad8c2aef5623aad61fe35ae814b1379f1 100644 --- a/flist/mem/fpga_mem.flist +++ b/flist/mem/fpga_mem.flist @@ -16,7 +16,7 @@ +libext+.v+.vlib // ============= NanoSoC Testbench search path ============= --incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ +// -incdir $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/ // - Top-level testbench $(SOCLABS_FPGA_LIB_TECH_DIR)/sram/verilog/sl_ahb_sram.v \ No newline at end of file diff --git a/flist/project/system.flist b/flist/project/system.flist index 5c53c0fe11ee3ae1d2f7053cb75f13214e7ee632..bc981cd7ad0918b1c599adcc92d41a25c836e60e 100644 --- a/flist/project/system.flist +++ b/flist/project/system.flist @@ -42,15 +42,9 @@ // - Generic Pad Library -f $(SOCLABS_PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist -// - CMSDK VIP --f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist - // - NanoSoC Custom Expansion Region //$(SOCLABS_PROJECT_DIR)/system/src/nanosoc_exp.v -// - Top level --f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist - // - FPGA sram -f $(SOCLABS_PROJECT_DIR)/flist/mem/fpga_mem.flist diff --git a/flist/project/system_tb.flist b/flist/project/system_tb.flist new file mode 100644 index 0000000000000000000000000000000000000000..f71578841f31e570cfe807088ecff6fa907d70ab --- /dev/null +++ b/flist/project/system_tb.flist @@ -0,0 +1,30 @@ +//----------------------------------------------------------------------------- +// Accelerator System Filelist +// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license. +// +// Contributors +// +// David Mapstone (d.a.mapstone@soton.ac.uk) +// +// Copyright � 2021-3, SoC Labs (www.soclabs.org) +//----------------------------------------------------------------------------- +//----------------------------------------------------------------------------- +// Abstract : Verilog Command File for Top-level Accelerator System +//----------------------------------------------------------------------------- + +// DESIGN_TOP nanosoc_tb + +// ============= Verilog library extensions =========== ++libext+.v+.vlib + +// ============= System Component Filelist ================ + +// - CMSDK VIP +-f $(SOCLABS_NANOSOC_TECH_DIR)/flist/corstone101_vip.flist + +// - Design +-f $(SOCLABS_PROJECT_DIR)/flist/project/system.flist + +// - Top level +-f $(SOCLABS_PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist + diff --git a/fpga_lib_tech b/fpga_lib_tech index 3e6eea8f70104378841ddb7032399cebcf43686f..4344fb7198daaae6d40f95b58587af5f869263a2 160000 --- a/fpga_lib_tech +++ b/fpga_lib_tech @@ -1 +1 @@ -Subproject commit 3e6eea8f70104378841ddb7032399cebcf43686f +Subproject commit 4344fb7198daaae6d40f95b58587af5f869263a2 diff --git a/nanosoc_tech b/nanosoc_tech index cb7b26aa5a553766cc90e513d146f6cfd7ac9142..6baa3fcaed83d29214b97c74d5c92627e152a41a 160000 --- a/nanosoc_tech +++ b/nanosoc_tech @@ -1 +1 @@ -Subproject commit cb7b26aa5a553766cc90e513d146f6cfd7ac9142 +Subproject commit 6baa3fcaed83d29214b97c74d5c92627e152a41a diff --git a/proj-branch b/proj-branch index c8662e937f4d3be543ec54963a5166f6176f746a..d004de05b26fb96b51721b15900d36c666fb80c3 100644 --- a/proj-branch +++ b/proj-branch @@ -12,7 +12,7 @@ # Project Repository Subrepository Branch Index # Add your Accelerator Repository here # accelerator_repo: main -nanosoc_tech: main +nanosoc_tech: feat_nanosoc_regions accelerator_wrapper_tech: main fpga_lib_tech: main generic_lib_tech: main diff --git a/soctools_flow b/soctools_flow index ce9edaa78fac0d09ad9466e4bc159e999483fd12..1c706759aebfbd539a9f035e94737975e00dd5dd 160000 --- a/soctools_flow +++ b/soctools_flow @@ -1 +1 @@ -Subproject commit ce9edaa78fac0d09ad9466e4bc159e999483fd12 +Subproject commit 1c706759aebfbd539a9f035e94737975e00dd5dd