From 18e275e10dd9e880b03ae8ac1275c5a8864c5976 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Wed, 26 Apr 2023 17:06:00 +0100
Subject: [PATCH] SOC1-167: Moved soc-init into set env script and added
additional filelist to get nanosoc simulation to run
---
.gitignore | 3 ++-
flist/nanosoc/nanosoc_chip_ip.flist | 33 +++++++++++++++++++++++++++
flist/nanosoc/nanosoc_matrix_ip.flist | 4 ++--
flist/nanosoc/nanosoc_tb.flist | 12 ++++++++++
flist/project/system.flist | 13 +++++++----
flist/project/wrapper.flist | 3 +++
nanosoc | 2 +-
set_env.sh | 20 ++++++++++++++++
system/src/nanosoc_exp.v | 2 +-
9 files changed, 83 insertions(+), 9 deletions(-)
create mode 100644 flist/nanosoc/nanosoc_chip_ip.flist
diff --git a/.gitignore b/.gitignore
index 1043bb3..b04674f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,4 @@
*.vcd
*.vvp
-simulate/sim/*
\ No newline at end of file
+simulate/sim/*
+.socinit
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_chip_ip.flist b/flist/nanosoc/nanosoc_chip_ip.flist
new file mode 100644
index 0000000..3d40778
--- /dev/null
+++ b/flist/nanosoc/nanosoc_chip_ip.flist
@@ -0,0 +1,33 @@
+//-----------------------------------------------------------------------------
+// NanoSoC Chip Related IP Filelist
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright � 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Verilog Command File for NanoSoC Bus Matrix IP
+//-----------------------------------------------------------------------------
+
+// ============= Verilog library extensions ===========
++libext+.v+.vlib
+
+// ============= NanoSoC Bus Matrix IP search path =============
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_chip_pads.v
+
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_cpu.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sysio.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/nanosoc_sys_ahb_decode.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_ahb_cs_rom_table.v
+
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_pin_mux.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_stclkctrl.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_clkctrl.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_mcu_sysctrl.v
+
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/bootrom.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ahb_bootrom.v
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_matrix_ip.flist b/flist/nanosoc/nanosoc_matrix_ip.flist
index b03107a..d8883e0 100644
--- a/flist/nanosoc/nanosoc_matrix_ip.flist
+++ b/flist/nanosoc/nanosoc_matrix_ip.flist
@@ -16,6 +16,6 @@
+libext+.v+.vlib
// ============= NanoSoC Bus Matrix IP search path =============
-+incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built
++incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
--y $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built
\ No newline at end of file
+-y $(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix
\ No newline at end of file
diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist
index 54a1236..22c1310 100644
--- a/flist/nanosoc/nanosoc_tb.flist
+++ b/flist/nanosoc/nanosoc_tb.flist
@@ -18,4 +18,16 @@
// ============= DMA-230 search path =============
+incdir+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/
+// - Top-level testbench
$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/tb_nanosoc.v
+
+// - Testbench components
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_clkreset.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/cmsdk_uart_capture.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/axi_streamio8_txd_from_file.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ft1248x1_to_axi_streamio_v1_0.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/axi_streamio8_rxd_to_file.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/track_tb_iostream.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/ft1248x1_track.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/dma_log_to_file.v
+$(NANOSOC_TECH_DIR)/Cortex-M0/nanosoc/systems/mcu/verilog/aes128_log_to_file.v
\ No newline at end of file
diff --git a/flist/project/system.flist b/flist/project/system.flist
index 7bc4c5e..e4871a5 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -23,12 +23,15 @@
// ============= System Component Filelist ================
+// - Primatives IP
+-f $(PROJECT_DIR)/flist/primatives/primatives.flist
+
// - CMSDK IP
-f $(PROJECT_DIR)/flist/ahb/ahb_ip.flist
-f $(PROJECT_DIR)/flist/apb/apb_ip.flist
-// - Top level
--f $(PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
+// - NanoSoC Chip IP
+-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_chip_ip.flist
// - NanoSoC Bus Matrix
-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_matrix_ip.flist
@@ -36,7 +39,6 @@
// - Generic Pad Library
-f $(PROJECT_DIR)/flist/generic_lib/generic_lib_ip.flist
-
// - CMSDK VIP
-f $(PROJECT_DIR)/flist/corstone-101/corstone-101_vip.flist
@@ -55,4 +57,7 @@
-f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
// - NanoSoC Custom Expansion Region
-$(PROJECT_DIR)/system/src/nanosoc_exp.v
\ No newline at end of file
+$(PROJECT_DIR)/system/src/nanosoc_exp.v
+
+// - Top level
+-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
\ No newline at end of file
diff --git a/flist/project/wrapper.flist b/flist/project/wrapper.flist
index 3724f23..ed4e319 100644
--- a/flist/project/wrapper.flist
+++ b/flist/project/wrapper.flist
@@ -15,6 +15,9 @@
// ============= Verilog library extensions ===========
+libext+.v+.vlib
+// ============= Wrapper IP Filelist ========================
+-f $(PROJECT_DIR)/flist/wrapper/wrapper_ip.flist
+
// ============= Accelerator Module search path =============
-y $(PROJECT_DIR)/wrapper/src/
+incdir+$(PROJECT_DIR)/wrapper/src/
diff --git a/nanosoc b/nanosoc
index 0dd2050..983484f 160000
--- a/nanosoc
+++ b/nanosoc
@@ -1 +1 @@
-Subproject commit 0dd2050946f895436ac9af62a23054b0584f8d7f
+Subproject commit 983484f9c10a516ffb43db4c922b597435c4be4c
diff --git a/set_env.sh b/set_env.sh
index fea648b..65400a5 100755
--- a/set_env.sh
+++ b/set_env.sh
@@ -54,4 +54,24 @@ else
done <<< "$(awk 'BEGIN{for(v in ENVIRON) print v}' | grep PROJECT_DIR)"
export PATH
+fi
+
+# Check cloned repository has been initialised
+if [ ! -f $PROJECT_DIR/.socinit ]; then
+ echo "Running First Time Repository Initialisation"
+ # Source environment variables for all submodules
+ cd $DESIGN_ROOT
+ for d in $PROJECT_DIR/* ; do
+ if [ -e "$d/.git" ]; then
+ if [ -f "$d/set_env.sh" ]; then
+ # If .git file exists - submodule
+ # git config -f .gitmodules submodule.$d.branch main
+ git submodule set-branch --branch main $d
+ fi
+ fi
+ done
+ git submodule update --remote --recursive
+ git submodule foreach --recursive git checkout main
+ git restore $DESIGN_ROOT/.gitmodules
+ touch $PROJECT_DIR/.socinit
fi
\ No newline at end of file
diff --git a/system/src/nanosoc_exp.v b/system/src/nanosoc_exp.v
index 9558e5e..e095259 100644
--- a/system/src/nanosoc_exp.v
+++ b/system/src/nanosoc_exp.v
@@ -131,7 +131,7 @@ cmsdk_ahb_slave_mux #(
//********************************************************************************
// Slave module 1: Accelerator AHB target module
//********************************************************************************
- wrapper_sha256_secworks_sha256 #(ACCEL_ADDRWIDTH
+ wrapper_secworks_sha256 #(ACCEL_ADDRWIDTH
) u_accelerator (
.HCLK (HCLK),
.HRESETn (HRESETn),
--
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