From 0e274a81858ab403bf27abfe8e86f67c0d680d78 Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Wed, 12 Apr 2023 16:52:23 +0100
Subject: [PATCH] SOC1-163: Moved Stimgen file to project repo added request
ctrl register module to wrapper repo
---
accelerator-wrapper | 2 +-
...ream.flist => secworks_sha25_stream.flist} | 0
flist/wrapper.flist | 1 -
flist/wrapper_ip.flist | 3 +
flow/stimgen.py | 214 +++++++
simulate/socsim/wrapper_secworks_sha256.sh | 1 +
system/stimulus/adp_hash_stim.cmd | 520 ++++++++---------
wrapper/src/wrapper_secworks_sha256.sv | 91 ++-
wrapper/stimulus/ahb_input_hash_stim.fri | 521 ++++++++---------
wrapper/stimulus/ahb_input_hash_stim.m2d | 527 +++++++++---------
wrapper/verif/tb_wrapper_secworks_sha256.sv | 2 +-
11 files changed, 1072 insertions(+), 810 deletions(-)
rename flist/{secwork_sha25_stream.flist => secworks_sha25_stream.flist} (100%)
create mode 100755 flow/stimgen.py
diff --git a/accelerator-wrapper b/accelerator-wrapper
index 7a5fe70..e93c1e9 160000
--- a/accelerator-wrapper
+++ b/accelerator-wrapper
@@ -1 +1 @@
-Subproject commit 7a5fe7024c3d2be951242c81f15aa743fca5faa8
+Subproject commit e93c1e93794237c72d62bdf71985cf89ca091e2d
diff --git a/flist/secwork_sha25_stream.flist b/flist/secworks_sha25_stream.flist
similarity index 100%
rename from flist/secwork_sha25_stream.flist
rename to flist/secworks_sha25_stream.flist
diff --git a/flist/wrapper.flist b/flist/wrapper.flist
index 7aa139a..3724f23 100644
--- a/flist/wrapper.flist
+++ b/flist/wrapper.flist
@@ -20,4 +20,3 @@
+incdir+$(PROJECT_DIR)/wrapper/src/
$(PROJECT_DIR)/wrapper/src/wrapper_secworks_sha256.sv
-$(PROJECT_DIR)/wrapper/src/wrapper_digest_filter.sv
diff --git a/flist/wrapper_ip.flist b/flist/wrapper_ip.flist
index 046c08f..373f79d 100644
--- a/flist/wrapper_ip.flist
+++ b/flist/wrapper_ip.flist
@@ -28,3 +28,6 @@ $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_reg_interface.sv
// $(WRAPPER_TECH_DIR)/hdl/src/wrapper_ahb_vr_interface.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_construct.sv
$(WRAPPER_TECH_DIR)/hdl/src/wrapper_packet_deconstruct.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_req_ctrl_reg.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_dmac_req.sv
+$(WRAPPER_TECH_DIR)/hdl/src/wrapper_valid_filter.sv
diff --git a/flow/stimgen.py b/flow/stimgen.py
new file mode 100755
index 0000000..1039895
--- /dev/null
+++ b/flow/stimgen.py
@@ -0,0 +1,214 @@
+#!/usr/bin/env python
+
+import csv, os, tabulate
+from enum import Enum
+
+soclabs_header = """;#-----------------------------------------------------------------------------
+;# SoC Labs Basic Hashing Accelerator Wrapper Input Stimulus File
+;# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+;#
+;# Contributors
+;#
+;# David Mapstone (d.a.mapstone@soton.ac.uk)
+;#
+;# Copyright 2023, SoC Labs (www.soclabs.org)
+;#-----------------------------------------------------------------------------"""
+
+class TransactionType(Enum):
+ """ Enumerated Types for Transaction Types for ASCII Debug """
+ READ = 1
+ WRITE = 2
+ def __str__(self):
+ if (self == TransactionType.READ):
+ return "R"
+ elif (self == TransactionType.WRITE):
+ return "W"
+
+class TransactionSize(Enum):
+ """ Enumerated Types for Transaction Types for ASCII Debug """
+ WORD = 1
+ HALFWORD = 2
+ def __str__(self):
+ if (self == TransactionSize.WORD):
+ return "word"
+ elif (self == TransactionSize.HALFWORD):
+ return "halfword"
+
+class InputBlockStruct:
+ def __init__(self):
+ self.word_list = []
+
+ def word_append(self, word):
+ self.word_list.append(word)
+
+class InputPacketStruct:
+ def __init__(self):
+ self.block_list = []
+
+ def block_append(self, block):
+ self.block_list.append(block)
+
+class WordStruct:
+ def __init__(self, data, addr, trans, packet_num = 0, block_num = 0, size = TransactionSize.WORD):
+ self.data = data
+ self.addr = addr
+ self.trans = trans
+ self.packet_num = packet_num
+ self.block_num = block_num
+ self.size = size
+
+def adp_output(out_file, word_list):
+ """
+ This function takes a list of 32 bit words and addresses and formats
+ the data into .cmd format for the ADP module
+ testbench
+ """
+
+ data = []
+ for word in word_list:
+ if (word.data > 0):
+ data.append(["a", "{0:#0{1}x}".format(word.addr,10)])
+ data.append([str(word.trans).lower(), "{0:#0{1}x}".format(word.data,10)])
+
+ table_str = tabulate.tabulate(data, tablefmt="plain")
+
+ with open(out_file, "w", encoding="UTF8", newline='') as f:
+ f.write("A\n")
+ f.write(table_str)
+ f.write("\n A")
+ f.write("\nX")
+ f.write("\n!")
+
+def fri_output(out_file, word_list):
+ """
+ This function takes a list of 32 bit words and addresses and formats
+ the data into .fri format to be fed into fml2conv.pl script to stimulate
+ testbench
+ """
+
+ # Column Names
+ col_names = ["Transaction", "Address", "Data", "Size"]
+
+ data = []
+ for word in word_list:
+ if (word.data > 0):
+ data.append([str(word.trans), "{0:#0{1}x}".format(word.addr,10), "{0:#0{1}x}".format(word.data,10), str(word.size)])
+
+ table_str = tabulate.tabulate(data, headers=col_names, tablefmt="plain")
+
+ with open(out_file, "w", encoding="UTF8", newline='') as f:
+ f.write(soclabs_header + "\n;")
+ f.write(table_str)
+ f.write("\nQ") # Add End of Simulation Flag
+
+def stimulus_generation(stim_file, ref_file, input_start_address, input_size, output_start_address, output_size, gen_fri=True):
+ """
+ This function takes 32 bit input stimulus file from accelerator model,
+ calculates write addresses for each word and generates a .fri file which
+ can be used to stimulate an AHB testbench
+ """
+ fri_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.fri"
+
+ if gen_fri:
+ # Calculate End Address
+ input_end_address = input_start_address + input_size - 0x4
+ # print(f"End Address is {hex(end_address)}")
+
+ # Open Files
+ with open(stim_file, "r") as stim:
+ csvreader = csv.reader(stim, delimiter=",")
+ stim_list = list(csvreader)
+
+ with open(ref_file, "r") as ref:
+ csvreader = csv.reader(ref, delimiter=",")
+ ref_list = list(csvreader)
+
+ # Initialise Packet Lists
+ write_packet_list = []
+ read_packet_list = []
+
+ # Initialise Temporary Structures
+ temppacketstruct = InputPacketStruct()
+ tempblockstruct = InputBlockStruct()
+
+ # Put Write Data into Structs
+ for i in stim_list:
+ tempblockstruct.word_append(int(i[0],16))
+ # If Last Word in Block, Append to Packet and Reset Temporary block structure
+ if (int(i[1])):
+ temppacketstruct.block_append(tempblockstruct)
+ tempblockstruct = InputBlockStruct()
+ # If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
+ if (int(i[2])):
+ write_packet_list.append(temppacketstruct)
+ temppacketstruct = InputPacketStruct()
+
+ # Put Read Data into Structs
+ for i in ref_list:
+ tempblockstruct.word_append(int(i[0],16))
+ # If Last Word in Block, Append to Packet and Reset Temporary block structure
+ if (int(i[1])):
+ temppacketstruct.block_append(tempblockstruct)
+ tempblockstruct = InputBlockStruct()
+ # If Last Block in Packet , Append Packet to Packet List and Reset Temp Packet
+ if (int(i[2])):
+ read_packet_list.append(temppacketstruct)
+ temppacketstruct = InputPacketStruct()
+
+
+ # List of Ouptut Transactions
+ output_word_list = []
+
+ # Generate Address for Packet
+ for packet_num, write_packet in enumerate(write_packet_list):
+ # Calculate Number of Blocks in First Packet
+ num_blocks = len(write_packet.block_list)
+ # Each Write Block Can Contain 16 32-bit Words (512 bits) (0x4 * 16 = 0x40)
+ # - Work Out Required Size = (0x40 * NumBlocks)
+ # - Work Out Beginning Address = (end_address + 0x4) - Size
+ req_write_size = 0x40 * num_blocks
+ start_write_addr = input_start_address + input_size - req_write_size
+ # Each Read Block Contains 8 32-bit Words (256 bits) (0x4 * 8 = 0x20)
+ req_read_size = 0x20
+ start_read_addr = output_start_address + output_size - req_read_size
+ # print(f"Packet: {int(packet_num)} | Start Address: {hex(start_write_addr)}")
+ write_addr = start_write_addr
+ read_addr = start_read_addr
+ # Write out Packet containing multiple 512 bit Blocks to Input Port
+ for block_num, block in enumerate(write_packet.block_list):
+ for word in block.word_list:
+ word_data = WordStruct(word, write_addr, TransactionType.WRITE, packet_num, block_num)
+ output_word_list.append(word_data)
+ # Increment Address
+ write_addr += 0x4
+ # Set Read Packet
+ read_packet = read_packet_list[packet_num]
+ # Read Back 256 Bit Packet from Output Port
+ for block_num, block in enumerate(read_packet.block_list):
+ for word in block.word_list:
+ word_data = WordStruct(word, read_addr, TransactionType.READ, packet_num, 0)
+ output_word_list.append(word_data)
+ # Increment Address
+ read_addr += 0x4
+
+
+ # Generate ADP Command File with Write Transactions
+ adp_file = os.environ["PROJECT_DIR"] + "/system/stimulus/" + "adp_hash_stim.cmd"
+ adp_output(adp_file, output_word_list)
+
+ # Generate FRI File with Write Transactions
+ fri_output(fri_file, output_word_list)
+
+ # Call fm2conv.pl script
+ m2d_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "ahb_input_hash_stim.m2d"
+ os.system(f"fm2conv.pl -busWidth=32 -infile={fri_file} -outfile={m2d_file}")
+
+
+if __name__ == "__main__":
+ accelerator_input_address = 0x6001_0000
+ accelerator_input_size = 0x0000_0400
+ accelerator_output_address = 0x6001_0400
+ accelerator_output_size = 0x0000_0400
+ stim_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "input_block_32bit_stim.csv"
+ ref_file = os.environ["PROJECT_DIR"] + "/wrapper/stimulus/" + "output_hash_32bit_ref.csv"
+ stimulus_generation(stim_file, ref_file, accelerator_input_address, accelerator_input_size, accelerator_output_address, accelerator_output_size, gen_fri=False)
\ No newline at end of file
diff --git a/simulate/socsim/wrapper_secworks_sha256.sh b/simulate/socsim/wrapper_secworks_sha256.sh
index a36666d..4f7780a 100755
--- a/simulate/socsim/wrapper_secworks_sha256.sh
+++ b/simulate/socsim/wrapper_secworks_sha256.sh
@@ -27,6 +27,7 @@ xrun \
-f $PROJECT_DIR/flist/primatives.flist \
-f $PROJECT_DIR/flist/wrapper_ip.flist \
-f $PROJECT_DIR/flist/ahb_ip.flist \
+ -f $PROJECT_DIR/flist/apb_ip.flist \
-f $PROJECT_DIR/flist/wrapper.flist \
-f $PROJECT_DIR/flist/ahb_vip.flist \
-f $PROJECT_DIR/flist/secworks_sha25_stream.flist \
diff --git a/system/stimulus/adp_hash_stim.cmd b/system/stimulus/adp_hash_stim.cmd
index bf7c416..d65e2c1 100644
--- a/system/stimulus/adp_hash_stim.cmd
+++ b/system/stimulus/adp_hash_stim.cmd
@@ -1,523 +1,523 @@
A
-a 0x60010780
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r 0x1f335cad
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w 0x00000200
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r 0x0b51e243
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w 0x4138b929
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w 0x877e2642
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w 0x00000200
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r 0x6d572f08
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r 0x24eb65ee
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A
X
diff --git a/wrapper/src/wrapper_secworks_sha256.sv b/wrapper/src/wrapper_secworks_sha256.sv
index b6fc0ed..70d5c7f 100644
--- a/wrapper/src/wrapper_secworks_sha256.sv
+++ b/wrapper/src/wrapper_secworks_sha256.sv
@@ -16,8 +16,8 @@ module wrapper_secworks_sha256 #(
parameter CFGSCHEMEWIDTH=2,
parameter OUTPACKETWIDTH=256
) (
- input logic HCLK, // Clock
- input logic HRESETn, // Reset
+ input logic HCLK, // Clock
+ input logic HRESETn, // Reset
// AHB connection to Initiator
input logic HSELS,
@@ -32,8 +32,6 @@ module wrapper_secworks_sha256 #(
output logic HRESPS,
output logic [31:0] HRDATAS,
- //TODO: Add APB Interface
-
// Input Data Request Signal to DMAC
output logic in_data_req,
@@ -54,7 +52,7 @@ module wrapper_secworks_sha256 #(
localparam [AHBADDRWIDTH-1:0] OUTPORTADDR = 'h400;
localparam OUTPORTAHBADDRWIDTH = AHBADDRWIDTH - 2;
- localparam OUTPACKETBYTEWIDTH = $clog2(OUTPACKETWIDTH/8); // Number of Bytes in Packet
+ localparam OUTPACKETBYTEWIDTH = $clog2(OUTPACKETWIDTH/8); // Number of Bytes in Packet
localparam OUTPACKETSPACEWIDTH = OUTPORTAHBADDRWIDTH-OUTPACKETBYTEWIDTH; // Number of Bits to represent all Packets in Address Space
// Control and Status Register Parameters
@@ -171,6 +169,9 @@ module wrapper_secworks_sha256 #(
logic in_packet_valid;
logic in_packet_ready;
+ // DMA
+ logic in_dma_req_act;
+
// Packet Constructor Instantiation
wrapper_ahb_packet_constructor #(
INPORTAHBADDRWIDTH,
@@ -199,7 +200,7 @@ module wrapper_secworks_sha256 #(
.packet_data_ready (in_packet_ready),
// Input Data Request
- .data_req (in_data_req)
+ .data_req (in_dma_req_act)
);
//----------------------------------------------------------
@@ -234,7 +235,8 @@ module wrapper_secworks_sha256 #(
// Relative Read Address for Start of Current Block
logic [OUTPORTAHBADDRWIDTH-1:0] block_read_addr;
-
+ // DMA Request Line
+ logic out_dma_req_act;
// Packet Deconstructor Instantiation
wrapper_ahb_packet_deconstructor #(
@@ -265,10 +267,10 @@ module wrapper_secworks_sha256 #(
.packet_data_ready (out_hash_ready),
// Input Data Request
- .data_req (out_data_req),
+ .data_req (out_dma_req_act),
// Read Address Interface
- .block_read_addr (block_read_addr)
+ .block_read_addr (block_read_addr)
);
//----------------------------------------------------------
@@ -305,12 +307,12 @@ module wrapper_secworks_sha256 #(
.PCLKEN (1'b1), // APB clock enable signal
.HSEL (hsel2), // Device select
- .HADDR, (HADDRS[CSRADDRWIDTH-1:0]) // Address
+ .HADDR (HADDRS[CSRADDRWIDTH-1:0]), // Address
.HTRANS (HTRANSS), // Transfer control
.HSIZE (HSIZES), // Transfer size
.HPROT (4'b1111), // Protection control
.HWRITE (HWRITES), // Write control
- .HREADY, (HREADYS) // Transfer phase done
+ .HREADY (HREADYS), // Transfer phase done
.HWDATA (HWDATAS), // Write data
.HREADYOUT (hreadyout2), // Device ready
@@ -361,21 +363,24 @@ module wrapper_secworks_sha256 #(
.rdata (csr_reg_rdata)
);
- // Example Register Block
- cmsdk_apb3_eg_slave_reg #(
- CSRADDRWIDTH
- ) u_csr_block (
- .pclk (HCLK),
- .presetn (HRESETn),
-
- // Register interface
- .addr (csr_reg_addr),
- .read_en (csr_reg_read_en),
- .write_en (csr_reg_write_en),
- .wdata (csr_reg_wdata),
- .ecorevnum (4'd0),
- .rdata (csr_reg_rdata)
- );
+ logic ctrl_reg_write_en, ctrl_reg_read_en;
+ assign ctrl_reg_write_en = csr_reg_write_en & (csr_reg_addr < 10'h100);
+ assign ctrl_reg_read_en = csr_reg_read_en & (csr_reg_addr < 10'h100);
+ // // Example Register Block
+ // cmsdk_apb3_eg_slave_reg #(
+ // CSRADDRWIDTH
+ // ) u_csr_block (
+ // .pclk (HCLK),
+ // .presetn (HRESETn),
+
+ // // Register interface
+ // .addr (csr_reg_addr),
+ // .read_en (csr_reg_read_en),
+ // .write_en (csr_reg_write_en),
+ // .wdata (csr_reg_wdata),
+ // .ecorevnum (4'd0),
+ // .rdata (csr_reg_rdata)
+ // );
//----------------------------------------------------------
// Default AHB Target Logic
@@ -405,7 +410,39 @@ module wrapper_secworks_sha256 #(
// Wrapper DMA Data Request Generation
//**********************************************************
- // TODO: Write up data request logic through registers
+ wrapper_req_ctrl_reg #(
+ CSRADDRWIDTH
+ ) u_wrapper_req_ctrl_reg (
+ .hclk (HCLK),
+ .hresetn (HRESETn),
+ .addr (csr_reg_addr),
+ .read_en (ctrl_reg_read_en),
+ .write_en (ctrl_reg_write_en),
+ .wdata (csr_reg_wdata),
+ .rdata (csr_reg_rdata),
+
+ // Data Transfer Request Signaling
+ .req_act_ch0 (in_dma_req_act),
+ .req_act_ch1 (out_dma_req_act),
+ .req_act_ch2 (1'b0),
+ .req_act_ch3 (1'b0),
+ .req_act_ch4 (1'b0),
+
+ // DMA Request Output
+ .drq_ch0 (in_data_req),
+ .drq_ch1 (out_data_req),
+ .drq_ch2 (),
+ .drq_ch3 (),
+ .drq_ch4 (),
+
+ // Interrupt Request Output
+ .irq_ch0 (),
+ .irq_ch1 (),
+ .irq_ch2 (),
+ .irq_ch3 (),
+ .irq_ch4 (),
+ .irq_merged ()
+ );
//**********************************************************
// Accelerator Engine
diff --git a/wrapper/stimulus/ahb_input_hash_stim.fri b/wrapper/stimulus/ahb_input_hash_stim.fri
index 5a70a66..a34d700 100644
--- a/wrapper/stimulus/ahb_input_hash_stim.fri
+++ b/wrapper/stimulus/ahb_input_hash_stim.fri
@@ -9,264 +9,265 @@
;# Copyright 2023, SoC Labs (www.soclabs.org)
;#-----------------------------------------------------------------------------
;Transaction Address Data Size
-W 0x60010780 0x94748770 word
-W 0x60010784 0x0e3109cc word
-W 0x60010788 0xc4411b41 word
-W 0x6001078c 0x5349fe99 word
-W 0x60010790 0xbc3bdfc1 word
-W 0x60010794 0xdeb5cb2a word
-W 0x60010798 0xa0052ca2 word
-W 0x6001079c 0x1761b000 word
-W 0x600107a0 0x1b5affff word
-W 0x600107a4 0xeab53b7e word
-W 0x600107a8 0x81152f06 word
-W 0x600107ac 0x7d60ab33 word
-W 0x600107b0 0x1ce3c906 word
-W 0x600107b4 0x707476fe word
-W 0x600107b8 0x923737f4 word
-W 0x600107bc 0x695b2443 word
-W 0x600107c0 0x00000200 word
-W 0x600107fc 0x80000000 word
-R 0x60010fe0 0xe06f1bef word
-R 0x60010fe4 0xf498916a word
-R 0x60010fe8 0x4686ebb1 word
-R 0x60010fec 0x0dc803e5 word
-R 0x60010ff0 0x960ea091 word
-R 0x60010ff4 0xeb558be4 word
-R 0x60010ff8 0xe14c46de word
-R 0x60010ffc 0xe1711626 word
-W 0x60010780 0xf7079da3 word
-W 0x60010784 0xa0c46731 word
-W 0x60010788 0xc51f9e09 word
-W 0x6001078c 0x8d8993e6 word
-W 0x60010790 0xfd33039d word
-W 0x60010794 0xe8675d4a word
-W 0x60010798 0xc0e513a1 word
-W 0x6001079c 0x858c0663 word
-W 0x600107a0 0xa1fb693e word
-W 0x600107a4 0xd5ebd6d4 word
-W 0x600107a8 0x26f7441f word
-W 0x600107ac 0x907554b5 word
-W 0x600107b0 0x9db705fd word
-W 0x600107b4 0x47a57bf5 word
-W 0x600107b8 0xfe2518c8 word
-W 0x600107bc 0x4c5b82c1 word
-W 0x600107c0 0x00000200 word
-W 0x600107fc 0x80000000 word
-R 0x60010fe0 0xd065f05e word
-R 0x60010fe4 0x1623b2c9 word
-R 0x60010fe8 0x9d3c0a90 word
-R 0x60010fec 0xce34de30 word
-R 0x60010ff0 0x72fc05c5 word
-R 0x60010ff4 0xcf65fdbb word
-R 0x60010ff8 0xef598a6e word
-R 0x60010ffc 0x58d6d30f word
-W 0x60010780 0x28b3253a word
-W 0x60010784 0x96dbf9e5 word
-W 0x60010788 0x55e5ab02 word
-W 0x6001078c 0x6bbbc74a word
-W 0x60010790 0xed5fbca6 word
-W 0x60010794 0x73ece6c4 word
-W 0x60010798 0x832fa959 word
-W 0x6001079c 0x7a0d31bf word
-W 0x600107a0 0xaa1320aa word
-W 0x600107a4 0x9fcb8eb3 word
-W 0x600107a8 0x6bf549d9 word
-W 0x600107ac 0x049bd3de word
-W 0x600107b0 0xdd09fb8d word
-W 0x600107b4 0x1285908a word
-W 0x600107b8 0x3eb37ea8 word
-W 0x600107bc 0x68eb3a8c word
-W 0x600107c0 0x00000200 word
-W 0x600107fc 0x80000000 word
-R 0x60010fe0 0xe4e3afb2 word
-R 0x60010fe4 0xa3be45c9 word
-R 0x60010fe8 0xb43f0fa3 word
-R 0x60010fec 0x56fcb65d word
-R 0x60010ff0 0xbbf2982b word
-R 0x60010ff4 0x15cd68c7 word
-R 0x60010ff8 0xcc9f9269 word
-R 0x60010ffc 0xed646faf word
-W 0x60010780 0xbfcceaa6 word
-W 0x60010784 0xa2264db5 word
-W 0x60010788 0x4ba05e93 word
-W 0x6001078c 0xb60ac4cb word
-W 0x60010790 0x9edcb672 word
-W 0x60010794 0x00637780 word
-W 0x60010798 0x860e62d9 word
-W 0x6001079c 0x8a983052 word
-W 0x600107a0 0x35e38f6f word
-W 0x600107a4 0xd2e8b382 word
-W 0x600107a8 0x3482b173 word
-W 0x600107ac 0x9d76f455 word
-W 0x600107b0 0x5b623fda word
-W 0x600107b4 0xb08ab5bf word
-W 0x600107b8 0x332433a7 word
-W 0x600107bc 0x17aced3b word
-W 0x600107c0 0x00000200 word
-W 0x600107fc 0x80000000 word
-R 0x60010fe0 0xad5d7f58 word
-R 0x60010fe4 0xc619f73f word
-R 0x60010fe8 0x5a54de49 word
-R 0x60010fec 0x038b0529 word
-R 0x60010ff0 0x92343513 word
-R 0x60010ff4 0xea3cf2a9 word
-R 0x60010ff8 0x5a1b530b word
-R 0x60010ffc 0x49393b4e word
-W 0x60010780 0x2319760c word
-W 0x60010784 0xc25e8486 word
-W 0x60010788 0xe2be9c44 word
-W 0x6001078c 0x28e4aeaf word
-W 0x60010790 0xae725608 word
-W 0x60010794 0xd394d5f8 word
-W 0x60010798 0xf6768cc7 word
-W 0x6001079c 0x7f51d709 word
-W 0x600107a0 0x4c99a726 word
-W 0x600107a4 0x2586fbc4 word
-W 0x600107a8 0xd2f30b37 word
-W 0x600107ac 0x8c71f0c5 word
-W 0x600107b0 0x4acf0b2d word
-W 0x600107b4 0xd0d8e335 word
-W 0x600107b8 0x88af1d5f word
-W 0x600107bc 0xe69dad36 word
-W 0x600107c0 0x00000200 word
-W 0x600107fc 0x80000000 word
-R 0x60010fe0 0x105755f3 word
-R 0x60010fe4 0x1ca8459e word
-R 0x60010fe8 0x08ffade5 word
-R 0x60010fec 0x29a2e390 word
-R 0x60010ff0 0xc6905543 word
-R 0x60010ff4 0x5ed0766b word
-R 0x60010ff8 0x9a63b562 word
-R 0x60010ffc 0x95262422 word
-W 0x60010780 0x2a17c8e9 word
-W 0x60010784 0x63931b41 word
-W 0x60010788 0xd191bfc8 word
-W 0x6001078c 0x40d7f3fc word
-W 0x60010790 0x60754253 word
-W 0x60010794 0xd5f6ef4c word
-W 0x60010798 0xa49ff89d word
-W 0x6001079c 0xb3f9bc39 word
-W 0x600107a0 0x7ba3ec2e word
-W 0x600107a4 0xf100cac2 word
-W 0x600107a8 0x552ac1d3 word
-W 0x600107ac 0x657744db word
-W 0x600107b0 0xfa2402f8 word
-W 0x600107b4 0x5e2ea772 word
-W 0x600107b8 0x572c2bf0 word
-W 0x600107bc 0x372eb887 word
-W 0x600107c0 0x00000200 word
-W 0x600107fc 0x80000000 word
-R 0x60010fe0 0x1f335cad word
-R 0x60010fe4 0x7d8c6b58 word
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\ No newline at end of file
diff --git a/wrapper/stimulus/ahb_input_hash_stim.m2d b/wrapper/stimulus/ahb_input_hash_stim.m2d
index 0a4fb32..bd56970 100644
--- a/wrapper/stimulus/ahb_input_hash_stim.m2d
+++ b/wrapper/stimulus/ahb_input_hash_stim.m2d
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diff --git a/wrapper/verif/tb_wrapper_secworks_sha256.sv b/wrapper/verif/tb_wrapper_secworks_sha256.sv
index 37d7343..cbfce6e 100644
--- a/wrapper/verif/tb_wrapper_secworks_sha256.sv
+++ b/wrapper/verif/tb_wrapper_secworks_sha256.sv
@@ -46,7 +46,7 @@ module tb_wrapper_secworks_sha256;
parameter CLK_PERIOD = 10;
parameter ADDRWIDTH = 12;
-parameter InputFileName = ("/home/dam1n19/Design/secworks-sha-256-system-top/wrapper/stimulus/ahb_input_hash_stim.m2d");
+parameter InputFileName = ("/home/dam1n19/Design/secworks-sha256-project/wrapper/stimulus/ahb_input_hash_stim.m2d");
parameter MessageTag = "FileReader:";
parameter StimArraySize = 10000;
--
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