diff --git a/flist/nanosoc/nanosoc_chip_ip.flist b/flist/nanosoc/nanosoc_chip_ip.flist
index c7b49e1f711620a60d1490706fb2d8dfd61a27d1..659ebf01103ac0e34260b06a25cb12ea047fdcbf 100644
--- a/flist/nanosoc/nanosoc_chip_ip.flist
+++ b/flist/nanosoc/nanosoc_chip_ip.flist
@@ -31,4 +31,9 @@ $(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_clkctrl.v
$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
-$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
+$(NANOSOC_TECH_DIR)/system/src/bootrom/verilog/bootrom.v
+
+$(NANOSOC_TECH_DIR)/system/aes/src/nanosoc_acc_wrapper.v
++incdir+$(PROJECT_DIR)/secworks-aes/src/rtl
+$(NANOSOC_TECH_DIR)/system/aes/src/soclabs_ahb_aes128_ctrl.v
diff --git a/flist/nanosoc/nanosoc_tb.flist b/flist/nanosoc/nanosoc_tb.flist
index e5438e8832b81056cb5f1dde561df2d779c8ce8e..7c0ec8e7ae791b8d0141e322ea8a69c96f2fc453 100644
--- a/flist/nanosoc/nanosoc_tb.flist
+++ b/flist/nanosoc/nanosoc_tb.flist
@@ -30,4 +30,5 @@ $(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
-$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
\ No newline at end of file
+$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
+$(NANOSOC_TECH_DIR)/system/aes/verif/aes128_log_to_file.v
diff --git a/flist/project/system.flist b/flist/project/system.flist
index 070cb146b9f56b99be3423bb712717a44506cdfc..a067906f4396f5b9a67f9de9e061ffabed512ef0 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -62,4 +62,4 @@ $(PROJECT_DIR)/system/src/nanosoc_exp.v
-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist
// ============= Bootrom Filelist ================
-$(PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
+//src/bootrom/verilog/bootrom.v
diff --git a/generic_lib_tech b/generic_lib_tech
index 69e79bf881a73af0b3ee04e25835450ed2635718..53dca95d66a93333a7e6e8bbbda0696a348da0b5 160000
--- a/generic_lib_tech
+++ b/generic_lib_tech
@@ -1 +1 @@
-Subproject commit 69e79bf881a73af0b3ee04e25835450ed2635718
+Subproject commit 53dca95d66a93333a7e6e8bbbda0696a348da0b5
diff --git a/nanosoc_tech b/nanosoc_tech
index 9e4a4da0a9dd45c84a787c4cf73294e7a412aff4..f68c3e62bd2dd914b49e7000fb0f226fcb01a8a7 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 9e4a4da0a9dd45c84a787c4cf73294e7a412aff4
+Subproject commit f68c3e62bd2dd914b49e7000fb0f226fcb01a8a7
diff --git a/simulate/socsim/bootrom.sh b/simulate/socsim/bootrom.sh
index bf938b97f485bfaf622ef748afcf25d4cdf6ac8a..fc9a69adbaa23540c6e37ece3f90b503aa6fc782 100755
--- a/simulate/socsim/bootrom.sh
+++ b/simulate/socsim/bootrom.sh
@@ -19,7 +19,7 @@ SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
# Create Directory to put simulation files
mkdir -p $SIM_DIR
-cd $PROJECT_DIR/simulate/sim/system_secworks_sha256
+cd $PROJECT_DIR/simulate/sim/$PROJECT_DIR
# Compile Simulation
# Call makefile in NanoSoC Repo with options
diff --git a/simulate/socsim/system_secworks_aes128.sh b/simulate/socsim/system_secworks_aes128.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c2ccf343ae1d45a12a32ae5f17f68bbce864c65a
--- /dev/null
+++ b/simulate/socsim/system_secworks_aes128.sh
@@ -0,0 +1,30 @@
+#-----------------------------------------------------------------------------
+# SoC Labs Simulation script for system level verification
+# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+#
+# Contributors
+#
+# David Mapstone (d.a.mapstone@soton.ac.uk)
+#
+# Copyright 2023, SoC Labs (www.soclabs.org)
+#-----------------------------------------------------------------------------
+
+#!/usr/bin/env bash
+
+# Get simulation name from name of script
+SIM_NAME=`basename -s .sh "$0"`
+
+# Directory to put simulation files
+SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
+
+# Create Directory to put simulation files
+mkdir -p $SIM_DIR
+cd $PROJECT_DIR/simulate/sim/$PROJECT_DIR
+
+# Compile Simulation
+# Call makefile in NanoSoC Repo with options
+echo ${2}
+make -C $NANOSOC_TECH_DIR/system run_mti \
+ SIM_DIR=$SIM_DIR \
+ ${@:2}
+
diff --git a/wrapper/src/wrapper_accelerator.sv b/wrapper/src/wrapper_accelerator.sv
index e90ddf717e35f9f5cf256b24335a20a3f816a0b8..e0ff2fcb1ea42684c8d751538540fc06f10adfb3 100644
--- a/wrapper/src/wrapper_accelerator.sv
+++ b/wrapper/src/wrapper_accelerator.sv
@@ -14,7 +14,8 @@ module wrapper_accelerator #(
parameter INPACKETWIDTH=512,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
- parameter OUTPACKETWIDTH=256
+ parameter OUTPACKETWIDTH=256,
+ parameter CFGNUMIRQ=4
) (
input logic HCLK, // Clock
input logic HRESETn, // Reset
@@ -34,10 +35,15 @@ module wrapper_accelerator #(
output logic [31:0] HRDATAS,
// Input Data Request Signal to DMAC
- output logic in_data_req,
+ output logic in_data_drq,
+ input logic in_data_dlast,
// Output Data Request Signal to DMAC
- output logic out_data_req
+ output logic out_data_drq,
+ input logic out_data_dlast,
+
+ output logic [CFGNUMIRQ-1:0] int_irq
+
);
@@ -430,17 +436,17 @@ module wrapper_accelerator #(
.req_act_ch4 (1'b0),
// DMA Request Output
- .drq_ch0 (in_data_req),
- .drq_ch1 (out_data_req),
+ .drq_ch0 (in_data_drq),
+ .drq_ch1 (out_data_drq),
.drq_ch2 (),
.drq_ch3 (),
.drq_ch4 (),
// Interrupt Request Output
- .irq_ch0 (),
- .irq_ch1 (),
- .irq_ch2 (),
- .irq_ch3 (),
+ .irq_ch0 (int_irq[0]),
+ .irq_ch1 (int_irq[1]),
+ .irq_ch2 (int_irq[2]),
+ .irq_ch3 (int_irq[3]),
.irq_ch4 (),
.irq_merged ()
);