diff --git a/nanosoc_tech b/nanosoc_tech
index 2435337b99835700f043c394f110cf245b113ac5..da0e6c8fdffb3ae05dc39c2f5022aa90483b85c8 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 2435337b99835700f043c394f110cf245b113ac5
+Subproject commit da0e6c8fdffb3ae05dc39c2f5022aa90483b85c8
diff --git a/system/testcodes/aes128_tests_dma230/dma_pl230_driver.c b/system/testcodes/aes128_tests_dma230/dma_pl230_driver.c
deleted file mode 100644
index 878146502e4b9f1d44f686d3f9f0df121ffcfe74..0000000000000000000000000000000000000000
--- a/system/testcodes/aes128_tests_dma230/dma_pl230_driver.c
+++ /dev/null
@@ -1,163 +0,0 @@
-#include <stdio.h>
-#include <string.h>
-#include "dma_pl230_driver.h"
-
-#define DEBUG_PRINTF(...) do {} while(0);
-//#define cpu_to_be32(__x) __x
-//#define be32_to_cpu(__x) __x
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-static int g_dma_pl230_initialised = 0;
-
-static dma_pl230_data_structure priv_dma __attribute__((aligned(256)));
-//
-dma_pl230_data_structure *dma_pl230_table = &priv_dma;
-
-/* --------------------------------------------------------------- */
-/* Initialize DMA data structure */
-/* --------------------------------------------------------------- */
-void dma_pl230_data_struct_init(void)
-{
- int i; /* loop counter */
-
-// printf ("dma structure block address = %x\n", dma_pl230_table);
- for (i=0; i<MAX_NUM_OF_DMA_CHANNELS; i++) {
- dma_pl230_table->Primary[i].SrcEndPointer = 0;
- dma_pl230_table->Primary[i].DstEndPointer = 0;
- dma_pl230_table->Primary[i].Control = 0;
- dma_pl230_table->Alternate[i].SrcEndPointer = 0;
- dma_pl230_table->Alternate[i].DstEndPointer = 0;
- dma_pl230_table->Alternate[i].Control = 0;
- }
- g_dma_pl230_initialised = 1;
- return;
-}
-
-void dma_pl230_data_struct_init_dbg(void)
-{
- int i; /* loop counter */
- unsigned int ptr;
-
- int ch_num; /* number of channels */
- unsigned int blksize; /* Size of DMA data structure in bytes */
- unsigned int blkmask; /* address mask */
-
-
- ch_num = (((DMA_PL230_DMAC->DMA_STATUS) >> 16) & 0x1F)+1;
- blksize = ch_num * 32;
- if (ch_num > 16) blkmask = 0x3FF; /* 17 to 32 */
- else if (ch_num > 8) blkmask = 0x1FF; /* 9 to 16 */
- else if (ch_num > 4) blkmask = 0x0FF; /* 5 to 8 */
- else if (ch_num > 2) blkmask = 0x07F; /* 3 to 4 */
- else if (ch_num > 1) blkmask = 0x03F; /* 2 */
- else blkmask = 0x01F; /* 1 */
-
-
- /* Create DMA data structure in RAM after stack
- In the linker script, a 1KB memory stack above stack is reserved
- so we can use this space for putting the DMA data structure.
- */
-
-// ptr = HW32_REG(0); /* Read Top of Stack */
- ptr = (0x80000000); // force for now as no reserved RAM available
-
- /* the DMA data structure must be aligned to the size of the data structure */
- if ((ptr & blkmask) != 0x0)
- ptr = (ptr + blksize) & ~blkmask;
-
-/// if ((ptr + blksize) > (RAM_ADDRESS_MAX + 1)) {
-/// puts ("ERROR : Not enough RAM space for DMA data structure.");
-/// UartEndSimulation();
-/// }
-
- /* Set pointer to the reserved space */
- dma_pl230_table = (dma_pl230_data_structure *) ptr;
- ptr = (unsigned long) &(dma_pl230_table->Primary[0].SrcEndPointer);
-
- printf ("dma structure block address = %x\n", ptr);
-
- for (i=0; i<MAX_NUM_OF_DMA_CHANNELS; i++) {
- dma_pl230_table->Primary[i].SrcEndPointer = 0;
- dma_pl230_table->Primary[i].DstEndPointer = 0;
- dma_pl230_table->Primary[i].Control = 0;
- dma_pl230_table->Alternate[i].SrcEndPointer = 0;
- dma_pl230_table->Alternate[i].DstEndPointer = 0;
- dma_pl230_table->Alternate[i].Control = 0;
- }
- g_dma_pl230_initialised = 1;
- return;
-}
-/* --------------------------------------------------------------- */
-/* Initialize DMA PL230 */
-/* --------------------------------------------------------------- */
-void dma_pl230_init_dbg(unsigned int chan_mask)
-{
- unsigned int current_state;
- puts ("Initialize PL230");
- current_state = DMA_PL230_DMAC->DMA_STATUS;
- printf ("- # of channels allowed : %d\n",(((current_state) >> 16) & 0x1F)+1);
- /* Debugging printfs: */
- printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
- printf ("- Current master enable : %x\n",(((current_state) >> 0) & 0x1));
-
- /* Wait until current DMA complete */
- current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
- if (!((current_state==0) || (current_state==0x8) || (current_state==0x9))) {
- puts ("- wait for DMA IDLE/STALLED/DONE");
- current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
- printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
-
- }
- while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
- /* Wait if not IDLE/STALLED/DONE */
- current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
- printf ("- Current status : %x\n",(((current_state) >> 4) & 0xF));
- }
- DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
- DMA_PL230_DMAC->CTRL_BASE_PTR = (unsigned long) &(dma_pl230_table->Primary->SrcEndPointer);
- /* Set DMA data structure address */
- DMA_PL230_DMAC->CHNL_ENABLE_CLR = 0xFFFFFFFF; /* Disable all channels */
- DMA_PL230_DMAC->CHNL_PRI_ALT_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all alt channels */
- DMA_PL230_DMAC->CHNL_ENABLE_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable channel */
- DMA_PL230_DMAC->CHNL_USEBURST_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable bursts */
- if (chan_mask)
- DMA_PL230_DMAC->DMA_CFG = 1; /* Enable DMA controller if enabled channel*/
- return;
-}
-
-void dma_pl230_init(unsigned int chan_mask)
-{
- unsigned int current_state;
- if (g_dma_pl230_initialised ==0)
- dma_pl230_data_struct_init();
- /* Wait until current DMA complete */
- current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
- while (!((current_state==0) || (current_state==0x8) || (current_state==0x9))){
- /* Wait if not IDLE/STALLED/DONE */
- puts ("- wait for DMA IDLE/STALLED/DONE");
- current_state = (DMA_PL230_DMAC->DMA_STATUS >> 4) & 0xF;
- }
- DMA_PL230_DMAC->DMA_CFG = 0; /* Disable DMA controller for initialization */
- DMA_PL230_DMAC->CTRL_BASE_PTR = (unsigned long) &(dma_pl230_table->Primary->SrcEndPointer);
- /* Set DMA data structure address */
- DMA_PL230_DMAC->CHNL_ENABLE_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all channels */
- DMA_PL230_DMAC->CHNL_PRI_ALT_CLR = ((1<<MAX_NUM_OF_DMA_CHANNELS)-1); /* Disable all alt channels */
- DMA_PL230_DMAC->CHNL_ENABLE_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable channel */
- DMA_PL230_DMAC->CHNL_USEBURST_SET = (chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enable bursts */
- g_dma_pl230_initialised = 2;
- if (chan_mask)
- DMA_PL230_DMAC->DMA_CFG = 1; /* Enable DMA controller if enabled channel*/
- return;
-}
-
-unsigned int dma_pl230_channel_active(unsigned int chan_mask)
-{
- return(DMA_PL230_DMAC->CHNL_ENABLE_SET & chan_mask & ((1<<MAX_NUM_OF_DMA_CHANNELS)-1)); /* Enabled channels */
-}
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/system/testcodes/aes128_tests_dma230/dma_pl230_driver.h b/system/testcodes/aes128_tests_dma230/dma_pl230_driver.h
deleted file mode 100644
index 082b196ab13b993867815b4ff5f91ff5cf1588a0..0000000000000000000000000000000000000000
--- a/system/testcodes/aes128_tests_dma230/dma_pl230_driver.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef __DMA_PL230_MCU_H
-#define __DMA_PL230_MCU_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include "CMSDK_CM0.h"
-
-#define DMA_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
-
-#define MAX_NUM_OF_DMA_CHANNELS 2
-
-/*------------- PL230 uDMA (PL230) --------------------------------------*/
-/** @addtogroup DMA_PL230 CMSDK uDMA controller
- @{
-*/
-typedef struct
-{
- __I uint32_t DMA_STATUS; /*!< Offset: 0x000 DMA status Register (R/W) */
- __O uint32_t DMA_CFG; /*!< Offset: 0x004 DMA configuration Register ( /W) */
- __IO uint32_t CTRL_BASE_PTR; /*!< Offset: 0x008 Channel Control Data Base Pointer Register (R/W) */
- __I uint32_t ALT_CTRL_BASE_PTR; /*!< Offset: 0x00C Channel Alternate Control Data Base Pointer Register (R/ ) */
- __I uint32_t DMA_WAITONREQ_STATUS; /*!< Offset: 0x010 Channel Wait On Request Status Register (R/ ) */
- __O uint32_t CHNL_SW_REQUEST; /*!< Offset: 0x014 Channel Software Request Register ( /W) */
- __IO uint32_t CHNL_USEBURST_SET; /*!< Offset: 0x018 Channel UseBurst Set Register (R/W) */
- __O uint32_t CHNL_USEBURST_CLR; /*!< Offset: 0x01C Channel UseBurst Clear Register ( /W) */
- __IO uint32_t CHNL_REQ_MASK_SET; /*!< Offset: 0x020 Channel Request Mask Set Register (R/W) */
- __O uint32_t CHNL_REQ_MASK_CLR; /*!< Offset: 0x024 Channel Request Mask Clear Register ( /W) */
- __IO uint32_t CHNL_ENABLE_SET; /*!< Offset: 0x028 Channel Enable Set Register (R/W) */
- __O uint32_t CHNL_ENABLE_CLR; /*!< Offset: 0x02C Channel Enable Clear Register ( /W) */
- __IO uint32_t CHNL_PRI_ALT_SET; /*!< Offset: 0x030 Channel Primary-Alterante Set Register (R/W) */
- __O uint32_t CHNL_PRI_ALT_CLR; /*!< Offset: 0x034 Channel Primary-Alterante Clear Register ( /W) */
- __IO uint32_t CHNL_PRIORITY_SET; /*!< Offset: 0x038 Channel Priority Set Register (R/W) */
- __O uint32_t CHNL_PRIORITY_CLR; /*!< Offset: 0x03C Channel Priority Clear Register ( /W) */
- uint32_t RESERVED0[3];
- __IO uint32_t ERR_CLR; /*!< Offset: 0x04C Bus Error Clear Register (R/W) */
-
-} DMA_PL230_TypeDef;
-
-#define PL230_DMA_CHNL_BITS 0
-
-#define DMA_PL230_DMA_STATUS_MSTREN_Pos 0 /*!< DMA_PL230 DMA STATUS: MSTREN Position */
-#define DMA_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << DMA_PL230_DMA_STATUS_MSTREN_Pos) /*!< DMA_PL230 DMA STATUS: MSTREN Mask */
-
-#define DMA_PL230_DMA_STATUS_STATE_Pos 0 /*!< DMA_PL230 DMA STATUS: STATE Position */
-#define DMA_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << DMA_PL230_DMA_STATUS_STATE_Pos) /*!< DMA_PL230 DMA STATUS: STATE Mask */
-
-#define DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /*!< DMA_PL230 DMA STATUS: CHNLS_MINUS1 Position */
-#define DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << DMA_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /*!< DMA_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
-
-#define DMA_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /*!< DMA_PL230 DMA STATUS: TEST_STATUS Position */
-#define DMA_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << DMA_PL230_DMA_STATUS_TEST_STATUS_Pos) /*!< DMA_PL230 DMA STATUS: TEST_STATUS Mask */
-
-#define DMA_PL230_DMA_CFG_MSTREN_Pos 0 /*!< DMA_PL230 DMA CFG: MSTREN Position */
-#define DMA_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << DMA_PL230_DMA_CFG_MSTREN_Pos) /*!< DMA_PL230 DMA CFG: MSTREN Mask */
-
-#define DMA_PL230_DMA_CFG_CPCCACHE_Pos 2 /*!< DMA_PL230 DMA CFG: CPCCACHE Position */
-#define DMA_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCCACHE_Pos) /*!< DMA_PL230 DMA CFG: CPCCACHE Mask */
-
-#define DMA_PL230_DMA_CFG_CPCBUF_Pos 1 /*!< DMA_PL230 DMA CFG: CPCBUF Position */
-#define DMA_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCBUF_Pos) /*!< DMA_PL230 DMA CFG: CPCBUF Mask */
-
-#define DMA_PL230_DMA_CFG_CPCPRIV_Pos 0 /*!< DMA_PL230 DMA CFG: CPCPRIV Position */
-#define DMA_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << DMA_PL230_DMA_CFG_CPCPRIV_Pos) /*!< DMA_PL230 DMA CFG: CPCPRIV Mask */
-
-#define DMA_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /*!< DMA_PL230 STATUS: BASE_PTR Position */
-#define DMA_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << DMA_PL230_CTRL_BASE_PTR_Pos) /*!< DMA_PL230 STATUS: BASE_PTR Mask */
-
-#define DMA_PL230_ALT_CTRL_BASE_PTR_Pos 0 /*!< DMA_PL230 STATUS: MSTREN Position */
-#define DMA_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << DMA_PL230_ALT_CTRL_BASE_PTR_Pos) /*!< DMA_PL230 STATUS: MSTREN Mask */
-
-#define DMA_PL230_DMA_WAITONREQ_STATUS_Pos 0 /*!< DMA_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
-#define DMA_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << DMA_PL230_DMA_WAITONREQ_STATUS_Pos) /*!< DMA_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
-
-#define DMA_PL230_CHNL_SW_REQUEST_Pos 0 /*!< DMA_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
-#define DMA_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_SW_REQUEST_Pos) /*!< DMA_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
-
-#define DMA_PL230_CHNL_USEBURST_SET_Pos 0 /*!< DMA_PL230 CHNL_USEBURST: SET Position */
-#define DMA_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_USEBURST_SET_Pos) /*!< DMA_PL230 CHNL_USEBURST: SET Mask */
-
-#define DMA_PL230_CHNL_USEBURST_CLR_Pos 0 /*!< DMA_PL230 CHNL_USEBURST: CLR Position */
-#define DMA_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_USEBURST_CLR_Pos) /*!< DMA_PL230 CHNL_USEBURST: CLR Mask */
-
-#define DMA_PL230_CHNL_REQ_MASK_SET_Pos 0 /*!< DMA_PL230 CHNL_REQ_MASK: SET Position */
-#define DMA_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_REQ_MASK_SET_Pos) /*!< DMA_PL230 CHNL_REQ_MASK: SET Mask */
-
-#define DMA_PL230_CHNL_REQ_MASK_CLR_Pos 0 /*!< DMA_PL230 CHNL_REQ_MASK: CLR Position */
-#define DMA_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_REQ_MASK_CLR_Pos) /*!< DMA_PL230 CHNL_REQ_MASK: CLR Mask */
-
-#define DMA_PL230_CHNL_ENABLE_SET_Pos 0 /*!< DMA_PL230 CHNL_ENABLE: SET Position */
-#define DMA_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_ENABLE_SET_Pos) /*!< DMA_PL230 CHNL_ENABLE: SET Mask */
-
-#define DMA_PL230_CHNL_ENABLE_CLR_Pos 0 /*!< DMA_PL230 CHNL_ENABLE: CLR Position */
-#define DMA_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_ENABLE_CLR_Pos) /*!< DMA_PL230 CHNL_ENABLE: CLR Mask */
-
-#define DMA_PL230_CHNL_PRI_ALT_SET_Pos 0 /*!< DMA_PL230 CHNL_PRI_ALT: SET Position */
-#define DMA_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRI_ALT_SET_Pos) /*!< DMA_PL230 CHNL_PRI_ALT: SET Mask */
-
-#define DMA_PL230_CHNL_PRI_ALT_CLR_Pos 0 /*!< DMA_PL230 CHNL_PRI_ALT: CLR Position */
-#define DMA_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRI_ALT_CLR_Pos) /*!< DMA_PL230 CHNL_PRI_ALT: CLR Mask */
-
-#define DMA_PL230_CHNL_PRIORITY_SET_Pos 0 /*!< DMA_PL230 CHNL_PRIORITY: SET Position */
-#define DMA_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRIORITY_SET_Pos) /*!< DMA_PL230 CHNL_PRIORITY: SET Mask */
-
-#define DMA_PL230_CHNL_PRIORITY_CLR_Pos 0 /*!< DMA_PL230 CHNL_PRIORITY: CLR Position */
-#define DMA_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << DMA_PL230_CHNL_PRIORITY_CLR_Pos) /*!< DMA_PL230 CHNL_PRIORITY: CLR Mask */
-
-#define DMA_PL230_ERR_CLR_Pos 0 /*!< DMA_PL230 ERR: CLR Position */
-#define DMA_PL230_ERR_CLR_Msk (0x00000001ul << DMA_PL230_ERR_CLR_Pos) /*!< DMA_PL230 ERR: CLR Mask */
-
-
-#define HW32_REG(ADDRESS) (*((volatile unsigned long *)(ADDRESS)))
-
- /* Maximum to 32 DMA channel */
- /* SRAM in example system is 64K bytes */
-#define RAM_ADDRESS_MAX 0x80001fff
-
-typedef struct /* 4 words */
-{
- volatile unsigned char* SrcEndPointer;
- volatile unsigned char* DstEndPointer;
- volatile unsigned long Control;
- volatile unsigned long unused;
-} dma_pl230_channel_data;
-
-
-typedef struct /* 8 words per channel */
-{ /* was one channel in the example uDMA setup */
- volatile dma_pl230_channel_data Primary[MAX_NUM_OF_DMA_CHANNELS];
- volatile dma_pl230_channel_data Alternate[MAX_NUM_OF_DMA_CHANNELS];
-} dma_pl230_data_structure;
-
-
-extern dma_pl230_data_structure *dma_pl230_table;
-
-#define DMA_PL230_DMAC ((DMA_PL230_TypeDef *) DMA_PL230_BASE)
-
-#define DMA_PL230_PTR_END(__ptr, __siz, __num) \
- ((unsigned char *) __ptr + ((1<<__siz)*(__num-1)))
-
-#define DMA_PL230_CTRL(__cyc, __siz, __num, __rpwr) \
- (((unsigned long) __siz << 30)|(__siz << 28)|(__siz << 26)|(__siz << 24)| \
- (1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
- (1 << 3)|(__cyc << 0) )
-
-#define DMA_PL230_CTRL_SRCFIX(__cyc, __siz, __num, __rpwr) \
- (((unsigned long) __siz << 30)|(__siz << 28)|(0x0c000000UL)|(__siz << 24)| \
- (1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
- (1 << 3)|(__cyc << 0) )
-
-#define DMA_PL230_CTRL_DSTFIX(__cyc, __siz, __num, __rpwr) \
- ((0xc0000000UL)|(__siz << 28)|(__siz << 26)|(__siz << 24)| \
- (1 << 21)|(1 << 18)|(__rpwr << 14)|(((__num-1)&0x3ff)<<4)| \
- (1 << 3)|(__cyc << 0) )
-
-#define DMA_PL230_MAX_XFERS (0x400)
-
-#define PL230_CTRL_CYCLE_STOP 0
-#define PL230_CTRL_CYCLE_BASIC 1
-#define PL230_CTRL_CYCLE_AUTO 2
-#define PL230_CTRL_CYCLE_PPONG 3
-#define PL230_CTRL_CYCLE_MEM_CHAIN_PRI 4
-#define PL230_CTRL_CYCLE_MEM_CHAIN_ALT 5
-#define PL230_CTRL_CYCLE_DEV_CHAIN_PRI 6
-#define PL230_CTRL_CYCLE_DEV_CHAIN_ALT 7
-
-#define PL230_CTRL_RPWR_1 0
-#define PL230_CTRL_RPWR_2 1
-#define PL230_CTRL_RPWR_4 2
-#define PL230_CTRL_RPWR_8 3
-#define PL230_CTRL_RPWR_16 4
-
-#define PL230_XFER_B 0
-#define PL230_XFER_H 1
-#define PL230_XFER_W 2
-
-/* --------------------------------------------------------------- */
-/* Initialize DMA data structure */
-/* --------------------------------------------------------------- */
-void dma_pl230_data_struct_init(void);
-
-/* --------------------------------------------------------------- */
-/* Initialize DMA PL230 */
-/* --------------------------------------------------------------- */
-void dma_pl230_init_dbg(unsigned int chan_mask);
-void dma_pl230_init(unsigned int chan_mask);
-
-/* --------------------------------------------------------------- */
-/* Check DMA PL230 DMA channel(s) active (return 0 when finishes) */
-/* --------------------------------------------------------------- */
-unsigned int dma_pl230_channel_active(unsigned int chan_mask);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __DMA_PL230_MCU_H */
-
diff --git a/system/testcodes/aes128_tests_dma230/makefile b/system/testcodes/aes128_tests_dma230/makefile
index 31f4b947940c08e8de6ddefd8919152be98019ed..3f41cf935611a5a40a401b3830b1a433c216f8b1 100644
--- a/system/testcodes/aes128_tests_dma230/makefile
+++ b/system/testcodes/aes128_tests_dma230/makefile
@@ -103,14 +103,8 @@ COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
-#ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-# -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
-#ARM_ASM_OPTIONS = -g
-#ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
-# --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
-
ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
- -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
ARM_ASM_OPTIONS =
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
--no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
@@ -161,7 +155,7 @@ all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
-dma_pl230_driver.o : dma_pl230_driver.c $(DEPS_LIST)
+dma_pl230_driver.o : $(SOFTWARE_DIR)/drivers/dma_pl230_driver.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
@@ -194,7 +188,8 @@ all_gcc:
$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
- -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/drivers \
-L $(LINKER_SCRIPT_PATH) \
-D__STACK_SIZE=0x200 \
-D__HEAP_SIZE=0x1000 \
diff --git a/system/testcodes/aes128_tests_memcpy/makefile b/system/testcodes/aes128_tests_memcpy/makefile
index 0fb504209ef0b133e577f83408838a27d9dfd12e..ef85d4e64d70bf3df1b5cc4963a54aa7f3debddc 100644
--- a/system/testcodes/aes128_tests_memcpy/makefile
+++ b/system/testcodes/aes128_tests_memcpy/makefile
@@ -103,14 +103,8 @@ COMPILE_MICROLIB = 0
# Small Multiply (Cortex-M0/M0+ has small multiplier option)
COMPILE_SMALLMUL = 0
-#ARM_CC_OPTIONS = -c -O3 -g -Otime -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
-# -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
-#ARM_ASM_OPTIONS = -g
-#ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
-# --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
-
ARM_CC_OPTIONS = -c -O3 -Ospace -I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
- -I $(SOFTWARE_DIR)/common/retarget $(USER_DEFINE)
+ -I $(SOFTWARE_DIR)/common/retarget -I $(SOFTWARE_DIR)/drivers $(USER_DEFINE)
ARM_ASM_OPTIONS =
ARM_LINK_OPTIONS = "--keep=$(STARTUP_FILE).o(RESET)" "--first=$(STARTUP_FILE).o(RESET)" \
--no_debug --rw_base 0x30000000 --ro_base 0x00000000 --map --info sizes
@@ -161,7 +155,7 @@ all_ds5 : $(TESTNAME).hex $(TESTNAME).lst
$(TESTNAME).o : $(TESTNAME).c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
-dma_pl230_driver.o : dma_pl230_driver.c $(DEPS_LIST)
+dma_pl230_driver.o : $(SOFTWARE_DIR)/drivers/dma_pl230_driver.c $(DEPS_LIST)
armcc $(ARM_CC_OPTIONS) $(CPU_TYPE) $< -o $@
$(SYSTEM_FILE).o : $(DEVICE_DIR)/Source/$(SYSTEM_FILE).c $(DEPS_LIST)
@@ -194,7 +188,8 @@ all_gcc:
$(SOFTWARE_DIR)/common/retarget/uart_stdout.c \
$(DEVICE_DIR)/Source/$(SYSTEM_FILE).c \
-I $(DEVICE_DIR)/Include -I $(CORE_DIR) \
- -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/common/retarget \
+ -I $(SOFTWARE_DIR)/drivers \
-L $(LINKER_SCRIPT_PATH) \
-D__STACK_SIZE=0x200 \
-D__HEAP_SIZE=0x1000 \