From fc020358b65ca887383a4606b68736eda05faaea Mon Sep 17 00:00:00 2001
From: dam1n19 <dam1n19@soton.ac.uk>
Date: Wed, 28 Jun 2023 16:47:00 +0100
Subject: [PATCH] Updated aes project to now simulate

---
 .gitmodules                               | 3 +++
 flist/nanosoc/nanosoc_chip_ip.flist       | 1 -
 flist/project/system.flist                | 4 ++--
 fpga_lib_tech                             | 2 +-
 nanosoc_tech                              | 2 +-
 simulate/socsim/system_secworks_aes128.sh | 6 +++---
 soctools_flow                             | 2 +-
 7 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/.gitmodules b/.gitmodules
index f5c1b16..e264757 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -16,3 +16,6 @@ url = https://git.soton.ac.uk/soclabs/nanosoc_tech.git
 [submodule "rtl_primitives_tech"]
 	path = rtl_primitives_tech
 	url = https://git.soton.ac.uk/soclabs/rtl_primitives_tech.git
+[submodule "secworks-aes"]
+	path = secworks-aes
+	url = https://github.com/secworks/aes.git
diff --git a/flist/nanosoc/nanosoc_chip_ip.flist b/flist/nanosoc/nanosoc_chip_ip.flist
index dc66fdb..0999af9 100644
--- a/flist/nanosoc/nanosoc_chip_ip.flist
+++ b/flist/nanosoc/nanosoc_chip_ip.flist
@@ -32,7 +32,6 @@ $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_mcu_sysctrl.v
 
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_apb_usrt.v
 $(SOCLABS_NANOSOC_TECH_DIR)/system/src/verilog/nanosoc_ahb_bootrom.v
-$(SOCLABS_NANOSOC_TECH_DIR)/system/src/bootrom/verilog/bootrom.v
 
 //$(SOCLABS_NANOSOC_TECH_DIR)/system/aes/src/nanosoc_exp_wrapper.v
 //+incdir+$(SOCLABS_PROJECT_DIR)/secworks-aes/src/rtl
diff --git a/flist/project/system.flist b/flist/project/system.flist
index b81c92f..431b2e8 100644
--- a/flist/project/system.flist
+++ b/flist/project/system.flist
@@ -19,7 +19,7 @@
 
 // =============    Accelerator Module search path    =============
 // ! Point this to your accelerator filelist
- f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
+-f $(SOCLABS_PROJECT_DIR)/flist/project/accelerator.flist
 
 // =============    Wrapper Filelist      =========================
 -f $(SOCLABS_PROJECT_DIR)/flist/project/wrapper.flist
@@ -64,4 +64,4 @@
 -f $(SOCLABS_PROJECT_DIR)/flist/project/system_tb.flist
 
 // =============    Bootrom Filelist      ================
-//$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
+$(SOCLABS_PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
diff --git a/fpga_lib_tech b/fpga_lib_tech
index c51fa19..4344fb7 160000
--- a/fpga_lib_tech
+++ b/fpga_lib_tech
@@ -1 +1 @@
-Subproject commit c51fa197a1d89ed556653fd7743c4aba20383b39
+Subproject commit 4344fb7198daaae6d40f95b58587af5f869263a2
diff --git a/nanosoc_tech b/nanosoc_tech
index 23d548a..be3bdf3 160000
--- a/nanosoc_tech
+++ b/nanosoc_tech
@@ -1 +1 @@
-Subproject commit 23d548a2cbe9c61a8ec90096c6f269ba692534e1
+Subproject commit be3bdf3202c87063c7bf38bf3cd3c6db6307a286
diff --git a/simulate/socsim/system_secworks_aes128.sh b/simulate/socsim/system_secworks_aes128.sh
index 9cfe3ee..9066517 100755
--- a/simulate/socsim/system_secworks_aes128.sh
+++ b/simulate/socsim/system_secworks_aes128.sh
@@ -15,16 +15,16 @@
 SIM_NAME=`basename -s .sh "$0"`
 
 # Directory to put simulation files
-SIM_DIR=$PROJECT_DIR/simulate/sim/$SIM_NAME
+SIM_DIR=$SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
 
 # Create Directory to put simulation files
 mkdir -p $SIM_DIR
-cd $PROJECT_DIR/simulate/sim/$PROJECT_DIR
+cd $SOCLABS_PROJECT_DIR/simulate/sim/$SIM_NAME
 
 # Compile Simulation
 # Call makefile in NanoSoC Repo with options
 echo ${2}
-make -C $NANOSOC_TECH_DIR/system run_xm \
+make -C $SOCLABS_NANOSOC_TECH_DIR/system run_xm \
     SIM_DIR=$SIM_DIR \
     ${@:2}
 
diff --git a/soctools_flow b/soctools_flow
index e5b63d6..1c70675 160000
--- a/soctools_flow
+++ b/soctools_flow
@@ -1 +1 @@
-Subproject commit e5b63d6e283f277a79947bcd4a616e4bf3ebadd9
+Subproject commit 1c706759aebfbd539a9f035e94737975e00dd5dd
-- 
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