From 7e14ebac333a81371e4b11b1d1c54d12cef3bed5 Mon Sep 17 00:00:00 2001
From: dam1n19 <d.a.mapstone@soton.ac.uk>
Date: Fri, 6 Jan 2023 09:37:41 +0000
Subject: [PATCH] fixed message_build testbench file descriptor paths and added
testbench name passing to socsim
---
.DS_Store | Bin 6148 -> 6148 bytes
flow/simulators/ivlog_sim.sh | 4 +-
flow/socsim | 2 +-
hdl/src/hash_process.sv | 42 ++++++++
hdl/verif/tb_hash_process.sv | 196 ++++++++++++++++++++++++++++++++++
hdl/verif/tb_message_build.sv | 8 +-
simulate/.DS_Store | Bin 0 -> 6148 bytes
simulate/sim/.DS_Store | Bin 0 -> 6148 bytes
8 files changed, 245 insertions(+), 7 deletions(-)
create mode 100644 hdl/src/hash_process.sv
create mode 100644 hdl/verif/tb_hash_process.sv
create mode 100644 simulate/.DS_Store
create mode 100644 simulate/sim/.DS_Store
diff --git a/.DS_Store b/.DS_Store
index 4913f199765e3dd77811dac5cc334c9a0ef2e635..ed5a1627a0488f9e875d5407c85d5a08a9c4e8bb 100644
GIT binary patch
delta 71
zcmZoMXfc=|#>B!ku~2NHo+2aX#(>?7i&&T#IXCk#tzev-!gPG|V&)#k&Fmcf984@+
cn?EvtXP(S2;>f|sz`(@7z`(FMLSzjy0JlOB`Tzg`
delta 68
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Z@640=MI1R87#J8B85meLM~JLp1^{Sah~
diff --git a/flow/simulators/ivlog_sim.sh b/flow/simulators/ivlog_sim.sh
index 97571d6..8b62d62 100755
--- a/flow/simulators/ivlog_sim.sh
+++ b/flow/simulators/ivlog_sim.sh
@@ -12,5 +12,5 @@
#!/usr/bin/env bash
mkdir -p $SHA_2_ACC_DIR/simulate/sim/
-iverilog -I $SHA_2_ACC_DIR/hdl/verif/ -I $SHA_2_ACC_DIR/hdl/src/ -g2012 -o $SHA_2_ACC_DIR/simulate/sim/message_build.vvp $SHA_2_ACC_DIR/hdl/verif/tb_message_build.sv
-cd $SHA_2_ACC_DIR/simulate/sim/ && vvp message_build.vvp
\ No newline at end of file
+iverilog -I $SHA_2_ACC_DIR/hdl/verif/ -I $SHA_2_ACC_DIR/hdl/src/ -g2012 -o $SHA_2_ACC_DIR/simulate/sim/$1.vvp $SHA_2_ACC_DIR/hdl/verif/tb_$1.sv
+cd $SHA_2_ACC_DIR/simulate/sim/ && vvp $1.vvp
\ No newline at end of file
diff --git a/flow/socsim b/flow/socsim
index 0d96be3..23dadfc 100755
--- a/flow/socsim
+++ b/flow/socsim
@@ -15,4 +15,4 @@ DEFAULT_SIMULATOR="ivlog"
if [[ -z "${SIMULATOR}" ]]; then
SIMULATOR=$DEFAULT_SIMULATOR
fi
-$SHA_2_ACC_DIR"/flow/simulators/"$SIMULATOR"_sim.sh"
+$SHA_2_ACC_DIR"/flow/simulators/"$SIMULATOR"_sim.sh" $1
diff --git a/hdl/src/hash_process.sv b/hdl/src/hash_process.sv
new file mode 100644
index 0000000..96dd49f
--- /dev/null
+++ b/hdl/src/hash_process.sv
@@ -0,0 +1,42 @@
+//-----------------------------------------------------------------------------
+// SoC Labs Basic SHA-2 Hash Processing Module
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+module hash_process (
+ input logic clk,
+ input logic nrst,
+ input logic en,
+
+ // Synchronous, localised reset
+ input logic sync_rst,
+
+ // Data In data and Handshaking
+ input logic [511:0] data_in,
+ input logic data_in_last,
+ input logic data_in_valid,
+ output logic data_in_ready,
+
+ // Data Out data and Handshaking
+ output logic [511:0] data_out,
+ output logic data_out_last,
+ output logic data_out_valid,
+ input logic data_out_ready
+);
+
+// Message Chunks
+logic [31:0] M [15:0];
+
+genvar i;
+generate
+ for (i=0; i < 16; i++) begin
+ assign M[i] = data_in[(16*i)-1:16*(i-1)];
+ end
+endgenerate
+
+endmodule
\ No newline at end of file
diff --git a/hdl/verif/tb_hash_process.sv b/hdl/verif/tb_hash_process.sv
new file mode 100644
index 0000000..158a4ad
--- /dev/null
+++ b/hdl/verif/tb_hash_process.sv
@@ -0,0 +1,196 @@
+//-----------------------------------------------------------------------------
+// SoC Labs Basic SHA-2 Message Builder Testbench
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Mapstone (d.a.mapstone@soton.ac.uk)
+//
+// Copyright 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+`timescale 1ns/1ns
+`include "message_build.sv"
+
+module tb_message_build;
+
+ logic clk;
+ logic nrst;
+ // Data In data and Handshaking
+ logic [511:0] data_in;
+ logic data_in_last;
+ logic data_in_valid;
+ logic data_in_ready;
+
+ // Config data and Handshaking
+ logic [63:0] cfg_size;
+ logic [1:0] cfg_scheme;
+ logic cfg_last;
+ logic cfg_valid;
+ logic cfg_ready;
+
+ // Data Out data and Handshaking
+ logic [511:0] data_out;
+ logic data_out_valid;
+ logic data_out_ready;
+ logic data_out_last;
+
+ hash_process uut (
+ .clk (clk),
+ .nrst(nrst),
+ .data_in(data_in),
+ .data_in_valid(data_in_valid),
+ .data_in_ready(data_in_ready),
+ .data_in_last(data_in_last),
+ .data_out(data_out),
+ .data_out_last(data_out_last),
+ .data_out_valid(data_out_valid),
+ .data_out_ready(data_out_ready));
+
+ logic data_in_drive_en;
+ logic cfg_drive_en;
+ logic data_out_drive_ready;
+
+ logic [511:0] data_in_queue [$];
+ logic data_in_last_queue [$];
+ logic data_in_wait_queue;
+
+ logic [63:0] cfg_size_queue [$];
+ logic [1:0] cfg_scheme_queue [$];
+ logic cfg_last_queue [$];
+ logic cfg_wait_queue;
+
+ logic [511:0] data_out_queue [$];
+ logic data_out_last_queue [$];
+ logic data_out_wait_queue;
+
+ // Handle Valid and Data for data_in
+ always_ff @(posedge clk, negedge nrst) begin: data_in_valid_drive
+ if (!nrst) begin
+ data_in <= 512'd0;
+ data_in_valid <= 1'b0;
+ data_in_last <= 1'b0;
+ data_in_wait_queue <= 1'b1;
+ end else if (data_in_drive_en) begin
+ if (((data_in_valid == 1'b1) && (data_in_ready == 1'b1)) ||
+ (data_in_wait_queue == 1'b1)) begin
+ // Data transfer just completed or transfers already up to date
+ if ((data_in_queue.size() > 0) && (data_in_last_queue.size() > 0)) begin
+ data_in <= data_in_queue.pop_front();
+ data_in_last <= data_in_last_queue.pop_front();
+ data_in_valid <= 1'b1;
+ data_in_wait_queue <= 1'b0;
+ end else begin
+ // No data currently avaiable in queue to write but transfers up to date
+ data_in_wait_queue <= 1'b1;
+ data_in_valid <= 1'b0;
+ end
+ end
+ end
+ end
+
+ logic [511:0] data_out_check;
+ logic data_out_last_check;
+ logic check_output;
+ logic test_end;
+ int packet_num;
+
+ // Handle Output Ready Driving
+ always_ff @(posedge clk, negedge nrst) begin: data_out_recieve
+ if (!nrst) begin
+ data_out_ready <= 1'b0;
+ check_output <= 1'b0;
+ test_end <= 1'b0;
+ end else begin
+ // Synchronise Ready to Clock
+ if (data_out_drive_ready) begin
+ data_out_ready <= 1'b1;
+ end else begin
+ data_out_ready <= 1'b0;
+ end
+ end
+ end
+
+ // Handle Output Data Verification
+ always @(posedge clk) begin
+ // Check Data on Handshake
+ if ((data_out_valid == 1'b1) && (data_out_ready == 1'b1)) begin
+ if ((data_out_queue.size() > 0) && (data_out_last_queue.size() > 0)) begin
+ data_out_check <= data_out_queue.pop_front();
+ data_out_last_check <= data_out_last_queue.pop_front();
+ assert (data_out == data_out_check) else begin
+ $error("data_out missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out, data_out_check);
+ $finish;
+ end
+ assert (data_out_last == data_out_last_check) else begin
+ $error("data_out_last missmatch! packet %d | recieve: %x != check: %x", packet_num, data_out_last, data_out_last_check);
+ $finish;
+ end
+ if (data_out_last_check == 1'b1) begin
+ packet_num <= packet_num + 1;
+ end
+ end else begin
+ $display("Test Passes");
+ $finish;
+ end
+ end
+ end
+
+ // File Reading Variables
+ int fd; // File descriptor Handle
+
+ logic [511:0] input_data; // Temporary Input Data Storage
+ logic input_data_last; // Temporary Input Data Last
+
+ logic [63:0] input_cfg_size; // Temporary cfg size
+ logic [1:0] input_cfg_scheme; // Temporary cfg scheme
+ logic input_cfg_last; // Temporary cfg last;
+
+ logic [511:0] output_data; // Temporary Output Data Storage
+ logic output_data_last; // Temporary Output Data Last
+
+ initial begin
+ $dumpfile("engine_sim.vcd");
+ $dumpvars(0, tb_message_build);
+ data_in_drive_en = 0;
+ cfg_drive_en = 0;
+ data_out_drive_ready = 0;
+
+ // Read input data into Queue
+ fd = $fopen("../stimulus/input_data_builder_stim.csv", "r");
+ while ($fscanf (fd, "%x,%b", input_data, input_data_last) == 2) begin
+ data_in_queue.push_back(input_data);
+ data_in_last_queue.push_back(input_data_last);
+ end
+ $fclose(fd);
+
+ // Read output data into Queue
+ fd = $fopen("../stimulus/output_data_builder_stim.csv", "r");
+ while ($fscanf (fd, "%x,%b", output_data, output_data_last) == 2) begin
+ data_out_queue.push_back(output_data);
+ data_out_last_queue.push_back(output_data_last);
+ end
+ $fclose(fd);
+
+ // Initialise First Checking Values
+ data_out_check = data_out_queue.pop_front();
+ data_out_last_check = data_out_last_queue.pop_front();
+
+ #20 nrst = 1;
+ #20 nrst = 0;
+ #20 nrst = 1;
+ #20 data_in_drive_en = 1;
+
+ // Write some data into the config register
+ # 30 cfg_drive_en = 1;
+
+ # 30 data_out_drive_ready = 1;
+ end
+
+ initial begin
+ forever begin
+ #10 clk = 0;
+ #10 clk = 1;
+ end
+ end
+
+endmodule
\ No newline at end of file
diff --git a/hdl/verif/tb_message_build.sv b/hdl/verif/tb_message_build.sv
index 37d5496..5cd7a29 100644
--- a/hdl/verif/tb_message_build.sv
+++ b/hdl/verif/tb_message_build.sv
@@ -181,14 +181,14 @@ module tb_message_build;
logic output_data_last; // Temporary Output Data Last
initial begin
- $dumpfile("engine_sim.vcd");
+ $dumpfile("message_build.vcd");
$dumpvars(0, tb_message_build);
data_in_drive_en = 0;
cfg_drive_en = 0;
data_out_drive_ready = 0;
// Read input data into Queue
- fd = $fopen("../stimulus/input_data_builder_stim.csv", "r");
+ fd = $fopen("../stimulus/testbench/input_data_builder_stim.csv", "r");
while ($fscanf (fd, "%x,%b", input_data, input_data_last) == 2) begin
data_in_queue.push_back(input_data);
data_in_last_queue.push_back(input_data_last);
@@ -196,7 +196,7 @@ module tb_message_build;
$fclose(fd);
// Read input cfg into Queue
- fd = $fopen("../stimulus/input_cfg_builder_stim.csv", "r");
+ fd = $fopen("../stimulus/testbench/input_cfg_builder_stim.csv", "r");
while ($fscanf (fd, "%x,%x,%b", input_cfg_size, input_cfg_scheme, input_cfg_last) == 3) begin
cfg_size_queue.push_back(input_cfg_size);
cfg_scheme_queue.push_back(input_cfg_scheme);
@@ -205,7 +205,7 @@ module tb_message_build;
$fclose(fd);
// Read output data into Queue
- fd = $fopen("../stimulus/output_data_builder_stim.csv", "r");
+ fd = $fopen("../stimulus/testbench/output_data_builder_stim.csv", "r");
while ($fscanf (fd, "%x,%b", output_data, output_data_last) == 2) begin
data_out_queue.push_back(output_data);
data_out_last_queue.push_back(output_data_last);
diff --git a/simulate/.DS_Store b/simulate/.DS_Store
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diff --git a/simulate/sim/.DS_Store b/simulate/sim/.DS_Store
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--
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