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Commit 09673ca2 authored by dwf1m12's avatar dwf1m12
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add project-level testbench support for aes128 example

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flist/project/system.flist
+ 4
− 4
View file @ 09673ca2
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
// ============= Accelerator Module search path ============= // ============= Accelerator Module search path =============
// ! Point this to your accelerator filelist // ! Point this to your accelerator filelist
// -f $(PROJECT_DIR)/flist/project/accelerator.flist -f $(PROJECT_DIR)/flist/project/accelerator.flist
// ============= Wrapper Filelist ========================= // ============= Wrapper Filelist =========================
-f $(PROJECT_DIR)/flist/project/wrapper.flist -f $(PROJECT_DIR)/flist/project/wrapper.flist
...@@ -58,10 +58,10 @@ ...@@ -58,10 +58,10 @@
-f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist -f $(PROJECT_DIR)/flist/cortex-m0/cortex-m0_ip.flist
// - NanoSoC Custom Expansion Region // - NanoSoC Custom Expansion Region
$(PROJECT_DIR)/system/src/nanosoc_exp.v //$(PROJECT_DIR)/system/src/nanosoc_exp_wrapper.v
// - Top level // - Top level
-f $(PROJECT_DIR)/flist/nanosoc/nanosoc_tb.flist -f $(PROJECT_DIR)/flist/project/system_tb.flist
// ============= Bootrom Filelist ================ // ============= Bootrom Filelist ================
$(PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v //$(PROJECT_DIR)/system/src/bootrom/verilog/bootrom.v
\ No newline at end of file
flist/project/system_tb.flist 0 → 100644
+ 35
− 0
View file @ 09673ca2
//-----------------------------------------------------------------------------
// NanoSoC Testbench Filelist
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Mapstone (d.a.mapstone@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Verilog Command File for NanoSoC Testbench
//-----------------------------------------------------------------------------
// ============= Verilog library extensions ===========
+libext+.v+.vlib
// ============= NanoSoC Testbench search path =============
+incdir+$(NANOSOC_TECH_DIR)/system/verif/verilog/
// - Top-level project-specific testbench
$(PROJECT_DIR)/system/verif/verilog/nanosoc_tb.v
$(PROJECT_DIR)/system/verif/verilog/aes128_log_to_file.v
// - Testbench components
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_clkreset.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_uart_capture.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_txd_from_file.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_to_axi_streamio_v1_0.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_axi_stream_io_8_rxd_to_file.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_track_tb_iostream.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_ft1248x1_track.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_dma_log_to_file.v
$(NANOSOC_TECH_DIR)/system/verif/verilog/nanosoc_acc_log_to_file.v
system/src/nanosoc_acc_wrapper.v
+ 24
− 23
View file @ 09673ca2
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
// Copyright (C) 2023; SoC Labs (www.soclabs.org) // Copyright (C) 2023; SoC Labs (www.soclabs.org)
//----------------------------------------------------------------------------- //-----------------------------------------------------------------------------
module nanosoc_acc_wrapper #( module nanosoc_exp_wrapper #(
parameter AHBADDRWIDTH=16, parameter AHBADDRWIDTH=16,
parameter INPACKETWIDTH=128, parameter INPACKETWIDTH=128,
parameter CFGSIZEWIDTH=64, parameter CFGSIZEWIDTH=64,
...@@ -22,18 +22,18 @@ module nanosoc_acc_wrapper #( ...@@ -22,18 +22,18 @@ module nanosoc_acc_wrapper #(
input wire HRESETn, // Reset input wire HRESETn, // Reset
// AHB connection to Initiator // AHB connection to Initiator
input wire HSELS, input wire HSEL_i,
input wire [AHBADDRWIDTH-1:0] HADDRS, input wire [AHBADDRWIDTH-1:0] HADDR_i,
input wire [1:0] HTRANSS, input wire [1:0] HTRANS_i,
input wire [2:0] HSIZES, input wire [2:0] HSIZE_i,
input wire [3:0] HPROTS, input wire [3:0] HPROT_i,
input wire HWRITES, input wire HWRITE_i,
input wire HREADYS, input wire HREADY_i,
input wire [31:0] HWDATAS, input wire [31:0] HWDATA_i,
output wire HREADYOUTS, output wire HREADYOUT_o,
output wire HRESPS, output wire HRESP_o,
output wire [31:0] HRDATAS, output wire [31:0] HRDATA_o,
// Input Data Request Signal to DMAC // Input Data Request Signal to DMAC
output wire exp_drq_ip_o, output wire exp_drq_ip_o,
...@@ -45,22 +45,23 @@ module nanosoc_acc_wrapper #( ...@@ -45,22 +45,23 @@ module nanosoc_acc_wrapper #(
// Interrupts // Interrupts
output wire [CFGNUMIRQ-1:0] exp_irq_o output wire [CFGNUMIRQ-1:0] exp_irq_o
); );
soclabs_ahb_aes128_ctrl u_exp_aes128 ( soclabs_ahb_aes128_ctrl u_exp_aes128 (
.ahb_hclk (HCLK), .ahb_hclk (HCLK),
.ahb_hresetn (HRESETn), .ahb_hresetn (HRESETn),
.ahb_hsel (HSELS), .ahb_hsel (HSEL_i),
.ahb_haddr16 (HADDRS[15:0]), .ahb_haddr16 (HADDR_i[15:0]),
.ahb_htrans (HTRANSS), .ahb_htrans (HTRANS_i),
.ahb_hwrite (HWRITES), .ahb_hwrite (HWRITE_i),
.ahb_hsize (HSIZES), .ahb_hsize (HSIZE_i),
.ahb_hprot (HPROTS), .ahb_hprot (HPROT_i),
.ahb_hwdata (HWDATAS), .ahb_hwdata (HWDATA_i),
.ahb_hready (HREADYS), .ahb_hready (HREADY_i),
.ahb_hrdata (HRDATAS), .ahb_hrdata (HRDATA_o),
.ahb_hreadyout (HREADYOUTS), .ahb_hreadyout (HREADYOUT_o),
.ahb_hresp (HRESPS), .ahb_hresp (HRESP_o),
.drq_ipdma128 (exp_drq_ip_o), .drq_ipdma128 (exp_drq_ip_o),
.dlast_ipdma128 (1'b0), .dlast_ipdma128 (1'b0),
.drq_opdma128 (exp_drq_op_o), .drq_opdma128 (exp_drq_op_o),
......
system/src/nanosoc_exp.v
+ 40
− 26
View file @ 09673ca2
...@@ -12,28 +12,42 @@ ...@@ -12,28 +12,42 @@
`include "cmsdk_ahb_slave_mux.v" `include "cmsdk_ahb_slave_mux.v"
module nanosoc_exp #( module nanosoc_exp #(
parameter ADDRWIDTH=29, // Region Address Width parameter ADDRWIDTH=29, // Region Decode Address Width
parameter ACCEL_ADDRWIDTH=12 // Region Address Width parameter ACCEL_ADDRWIDTH=12, // Region Address Width
parameter INPACKETWIDTH=128,
parameter CFGSIZEWIDTH=64,
parameter CFGSCHEMEWIDTH=2,
parameter OUTPACKETWIDTH=128,
parameter CFGNUMIRQ=4
)( )(
input wire HCLK, // Clock input wire HCLK, // Clock
input wire HRESETn, // Reset input wire HRESETn, // Reset
// AHB connection to Initiator // AHB connection to Initiator
input wire HSELS, input wire HSEL_i,
input wire [ADDRWIDTH-1:0] HADDRS, input wire [ADDRWIDTH-1:0] HADDR_i,
input wire [1:0] HTRANSS, input wire [1:0] HTRANS_i,
input wire [2:0] HSIZES, input wire [2:0] HSIZE_i,
input wire [3:0] HPROTS, input wire [3:0] HPROT_i,
input wire HWRITES, input wire HWRITE_i,
input wire HREADYS, input wire HREADY_i,
input wire [31:0] HWDATAS, input wire [31:0] HWDATA_i,
output wire HREADYOUTS, output wire HREADYOUT_o,
output wire HRESPS, output wire HRESP_o,
output wire [31:0] HRDATAS, output wire [31:0] HRDATA_o,
output wire ip_data_req, // Input Data Request Signal to DMAC
output wire op_data_req output wire exp_drq_ip_o,
input wire exp_dlast_ip_i,
// Output Data Request Signal to DMAC
output wire exp_drq_op_o,
input wire exp_dlast_op_i,
// Interrupts
output wire [CFGNUMIRQ-1:0] exp_irq_o
); );
//******************************************************************************** //********************************************************************************
...@@ -58,8 +72,8 @@ wire [31:0] HRDATA1; ...@@ -58,8 +72,8 @@ wire [31:0] HRDATA1;
// 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator // 0x00010000 - 0x00010FFF : HSEL #0 - Hash Accelerator
// Other addresses : HSEL #1 - Default target // Other addresses : HSEL #1 - Default target
assign HSEL0 = (HADDRS[ADDRWIDTH-1:12] == 'h00010) ? 1'b1:1'b0; assign HSEL0 = (HSEL_i & (HADDR_i[ADDRWIDTH-1:12] == 'h00010)) ? 1'b1:1'b0;
assign HSEL1 = HSEL0 ? 1'b0:1'b1; assign HSEL1 = HSEL0 ? 1'b0:HSEL_i;
//******************************************************************************** //********************************************************************************
// Slave multiplexer module: // Slave multiplexer module:
...@@ -80,7 +94,7 @@ cmsdk_ahb_slave_mux #( ...@@ -80,7 +94,7 @@ cmsdk_ahb_slave_mux #(
) u_ahb_slave_mux ( ) u_ahb_slave_mux (
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
.HREADY (HREADYS), .HREADY (HREADY_i),
.HSEL0 (HSEL0), // Input Port 0 .HSEL0 (HSEL0), // Input Port 0
.HREADYOUT0 (HREADYOUT0), .HREADYOUT0 (HREADYOUT0),
.HRESP0 (HRESP0), .HRESP0 (HRESP0),
...@@ -122,9 +136,9 @@ cmsdk_ahb_slave_mux #( ...@@ -122,9 +136,9 @@ cmsdk_ahb_slave_mux #(
.HRESP9 (), .HRESP9 (),
.HRDATA9 (), .HRDATA9 (),
.HREADYOUT (HREADYOUTS), // Outputs .HREADYOUT (HREADYOUT_o), // Outputs
.HRESP (HRESPS), .HRESP (HRESP_o),
.HRDATA (HRDATAS) .HRDATA (HRDATA_o)
); );
...@@ -141,10 +155,10 @@ cmsdk_ahb_slave_mux #( ...@@ -141,10 +155,10 @@ cmsdk_ahb_slave_mux #(
.HCLK (HCLK), .HCLK (HCLK),
.HRESETn (HRESETn), .HRESETn (HRESETn),
.HSEL (HSEL1), .HSEL (HSEL1),
.HTRANS (HTRANSS), .HTRANS (HTRANS_i),
.HREADY (HREADYS), .HREADY (HREADY_i),
.HREADYOUT (HREADYOUT1), .HREADYOUT (HREADYOUT1),
.HRESP (HRESPS) .HRESP (HRESP1)
); );
assign HRDATA1 = {32{1'b0}}; // Default target don't have data assign HRDATA1 = {32{1'b0}}; // Default target don't have data
......
system/verif/verilog/aes128_log_to_file.v 0 → 100644
+ 308
− 0
View file @ 09673ca2
//-----------------------------------------------------------------------------
// AHB transaction logger, developed for DMA integration testing
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright (C) 2023, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
module aes128_log_to_file
#(parameter FILENAME = "aes128.log",
parameter TIMESTAMP = 1)
(
input wire ahb_hclk, // Clock
input wire ahb_hresetn, // Reset
input wire ahb_hsel, // Device select
input wire [15:0] ahb_haddr16, // Address for byte select
input wire [1:0] ahb_htrans, // Transfer control
input wire [2:0] ahb_hsize, // Transfer size
input wire [3:0] ahb_hprot, // Protection control
input wire ahb_hwrite, // Write control
input wire ahb_hready, // Transfer phase done
input wire [31:0] ahb_hwdata, // Write data
input wire ahb_hreadyout, // Device ready
input wire [31:0] ahb_hrdata, // Read data output
input wire ahb_hresp, // Device response
// stream data
input wire drq_ipdma128, // (to) DMAC input burst request
input wire dlast_ipdma128,// (from) DMAC input burst end (last transfer)
input wire drq_opdma128, // (to) DMAC output dma burst request
input wire dlast_opdma128,// (from) DMAC output burst end (last transfer)
input wire irq_key128,
input wire irq_ip128,
input wire irq_op128,
input wire irq_error,
input wire irq_merged // combined interrrupt request (to CPU)
);
// CORE ID
localparam ADDR_CORE_NAME0 = 16'h0000;
localparam ADDR_CORE_NAME1 = 16'h0004;
localparam ADDR_CORE_VERSION= 16'h0008;
localparam CORE_NAME0 = 32'h61657331; // "aes1"
localparam CORE_NAME1 = 32'h32382020; // "28 "
localparam CORE_VERSION = 32'h302e3031; // "0.01"
// CTRL control register with bit-set/bit-clear options
localparam ADDR_CTRL = 16'h0010;
localparam ADDR_CTRL_SET = 16'h0014;
localparam ADDR_CTRL_CLR = 16'h0018;
localparam CTRL_REG_WIDTH = 8;
localparam CTRL_BIT_MAX = (CTRL_REG_WIDTH-1);
localparam CTRL_KEY_REQ_BIT = 0;
localparam CTRL_IP_REQ_BIT = 1;
localparam CTRL_OP_REQ_BIT = 2;
localparam CTRL_ERR_REQ_BIT = 3;
localparam CTRL_KEYOK_BIT = 4;
localparam CTRL_VALID_BIT = 5;
localparam CTRL_BYPASS_BIT = 6;
localparam CTRL_ENCODE_BIT = 7;
// STAT status regisyer
localparam ADDR_STAT = 16'h001c;
localparam STAT_REG_WIDTH = 8;
localparam STAT_BIT_MAX = (STAT_REG_WIDTH-1);
localparam STAT_KEYREQ_BIT = 0;
localparam STAT_INPREQ_BIT = 1;
localparam STAT_OUTREQ_BIT = 2;
localparam STAT_ERROR_BIT = 3;
localparam STAT_KEYOK_BIT = 4;
localparam STAT_VALID_BIT = 5;
// QUAL qualifier field
localparam ADDR_QUAL = 16'h0020;
localparam QUAL_REG_WIDTH = 32;
localparam QUAL_BIT_MAX = (QUAL_REG_WIDTH-1);
// DREQ DMAC request control with bit-set/bit-clear options
localparam ADDR_DREQ = 16'h0030;
localparam ADDR_DREQ_SET = 16'h0034;
localparam ADDR_DREQ_CLR = 16'h0038;
localparam ADDR_DREQ_ACT = 16'h003c;
localparam DREQ_REG_WIDTH = 3;
localparam DREQ_BIT_MAX = (DREQ_REG_WIDTH-1);
localparam REQ_KEYBUF_BIT = 0;
localparam REQ_IP_BUF_BIT = 1;
localparam REQ_OP_BUF_BIT = 2;
// IREQ CPU interrupt request control with bit-set/bit-clear options
localparam ADDR_IREQ = 16'h0040;
localparam ADDR_IREQ_SET = 16'h0044;
localparam ADDR_IREQ_CLR = 16'h0048;
localparam ADDR_IREQ_ACT = 16'h004c;
localparam IREQ_REG_WIDTH = 4;
localparam IREQ_BIT_MAX = (IREQ_REG_WIDTH-1);
localparam REQ_ERROR_BIT = 3;
localparam ADDR_KEY_BASE = 16'h4000;
localparam ADDR_KEY0 = 16'h4000;
localparam ADDR_KEY3 = 16'h400c;
localparam ADDR_KEY7 = 16'h401c;
localparam ADDR_IBUF_BASE = 16'h8000;
localparam ADDR_IBUF_0 = 16'h8000;
localparam ADDR_IBUF_3 = 16'h800c;
localparam ADDR_OBUF_BASE = 16'hc000;
localparam ADDR_OBUF_3 = 16'hc00c;
// AHB transction de-pipelining
// --------------------------------------------------------------------------
// Internal regs/wires
// --------------------------------------------------------------------------
reg sel_r;
reg [15:0] addr16_r;
reg wcyc_r;
reg rcyc_r;
reg [3:0] byte4_r;
reg [3:0] dma_ctrl_state_r;
// --------------------------------------------------------------------------
// AHB slave byte buffer interface, support for unaligned data transfers
// --------------------------------------------------------------------------
wire [1:0] byte_addr = ahb_haddr16[1:0];
// generate next byte enable decodes for Word/Half/Byte CPU/DMA accesses
wire [3:0] byte_nxt;
assign byte_nxt[0] = (ahb_hsize[1])|((ahb_hsize[0])&(!byte_addr[1]))|(byte_addr[1:0]==2'b00);
assign byte_nxt[1] = (ahb_hsize[1])|((ahb_hsize[0])&(!byte_addr[1]))|(byte_addr[1:0]==2'b01);
assign byte_nxt[2] = (ahb_hsize[1])|((ahb_hsize[0])&( byte_addr[1]))|(byte_addr[1:0]==2'b10);
assign byte_nxt[3] = (ahb_hsize[1])|((ahb_hsize[0])&( byte_addr[1]))|(byte_addr[1:0]==2'b11);
// de-pipelined registered access signals
always @(posedge ahb_hclk or negedge ahb_hresetn)
if (!ahb_hresetn)
begin
addr16_r <= 16'h0000;
sel_r <= 1'b0;
wcyc_r <= 1'b0;
rcyc_r <= 1'b0;
byte4_r <= 4'b0000;
end else if (ahb_hready)
begin
addr16_r <= (ahb_hsel & ahb_htrans[1]) ? ahb_haddr16 : addr16_r;
sel_r <= (ahb_hsel & ahb_htrans[1]);
wcyc_r <= (ahb_hsel & ahb_htrans[1] & ahb_hwrite);
rcyc_r <= (ahb_hsel & ahb_htrans[1] & !ahb_hwrite);
byte4_r <= (ahb_hsel & ahb_htrans[1]) ? byte_nxt[3:0] : 4'b0000;
end
wire [31:0] ahb_hdata = (wcyc_r)? ahb_hwdata : ahb_hrdata;
//----------------------------------------------
//-- File I/O
//----------------------------------------------
integer fd; // channel descriptor for cmd file input
integer ch;
reg drq_ipdma128_prev;
reg dlast_ipdma128_prev;
reg drq_opdma128_prev;
reg dlast_opdma128_prev;
reg irq_key128_prev;
reg irq_ip128_prev;
reg irq_op128_prev;
reg irq_error_prev;
reg irq_merged_prev;
wire drq_ipdma128_change;
wire dlast_ipdma128_change;
wire drq_opdma128_change;
wire dlast_opdma128_change;
wire irq_key128_change;
wire irq_ip128_change;
wire irq_op128_change;
wire irq_error_change;
wire irq_merged_change;
wire irq_change;
wire drq_change;
wire any_change;
reg [31:0] cyc_count;
`define EOF -1
reg [7:0] ctrl_reg;
reg [2:0] dreq_reg;
reg [2:0] ireq_reg;
always @(posedge ahb_hclk or negedge ahb_hresetn)
if (!ahb_hresetn)
begin
drq_ipdma128_prev <= 1'b0;
dlast_ipdma128_prev <= 1'b0;
drq_opdma128_prev <= 1'b0;
dlast_opdma128_prev <= 1'b0;
irq_key128_prev <= 1'b0;
irq_ip128_prev <= 1'b0;
irq_op128_prev <= 1'b0;
irq_error_prev <= 1'b0;
irq_merged_prev <= 1'b0;
end else if (ahb_hready)
begin
drq_ipdma128_prev <= drq_ipdma128 ;
dlast_ipdma128_prev <= dlast_ipdma128;
drq_opdma128_prev <= drq_opdma128 ;
dlast_opdma128_prev <= dlast_opdma128;
irq_key128_prev <= irq_key128 ;
irq_ip128_prev <= irq_ip128 ;
irq_op128_prev <= irq_op128 ;
irq_error_prev <= irq_error ;
irq_merged_prev <= irq_merged ;
end
assign drq_ipdma128_change = (drq_ipdma128_prev ^ drq_ipdma128 );
assign dlast_ipdma128_change = (dlast_ipdma128_prev ^ dlast_ipdma128);
assign drq_opdma128_change = (drq_opdma128_prev ^ drq_opdma128 );
assign dlast_opdma128_change = (dlast_opdma128_prev ^ dlast_opdma128);
assign drq_change = drq_ipdma128_change | drq_opdma128_change
| dlast_ipdma128_change | dlast_opdma128_change;
assign irq_key128_change = (irq_key128_prev ^ irq_key128 );
assign irq_ip128_change = (irq_ip128_prev ^ irq_ip128 );
assign irq_op128_change = (irq_op128_prev ^ irq_op128 );
assign irq_error_change = (irq_error_prev ^ irq_error );
assign irq_change = irq_key128_change | irq_ip128_change
| irq_op128_change | irq_error_change;
assign any_change = drq_ipdma128_change
| dlast_ipdma128_change
| drq_opdma128_change
| dlast_opdma128_change
| irq_key128_change
| irq_ip128_change
| irq_op128_change
| irq_error_change
| irq_merged_change
;
initial
begin
fd= $fopen(FILENAME,"w");
cyc_count <= 0;
if (fd == 0)
$write("** %m : output log file failed to open **\n");
else begin
@(posedge ahb_hresetn);
while (1) begin
@(posedge ahb_hclk);
cyc_count <= cyc_count +1;
if (sel_r & ahb_hready) begin
$fwrite(fd, "AES-C: ");
case ({addr16_r[15:2],2'b00})
ADDR_CORE_NAME0 : begin $fwrite(fd, "CORE_NAME0 "); end
ADDR_CORE_NAME1 : begin $fwrite(fd, "CORE_NAME1 "); end
ADDR_CORE_VERSION : begin $fwrite(fd, "CORE_VERSION"); end
ADDR_CTRL : begin $fwrite(fd, "CTRL "); if (wcyc_r) ctrl_reg <= ahb_hwdata[7:0]; end
ADDR_CTRL_SET : begin $fwrite(fd, "CTRL_SET "); if (wcyc_r) ctrl_reg <= ctrl_reg | ahb_hwdata[7:0]; end
ADDR_CTRL_CLR : begin $fwrite(fd, "CTRL_CLR "); if (wcyc_r) ctrl_reg <= ctrl_reg &~ahb_hwdata[7:0]; end
ADDR_STAT : begin $fwrite(fd, "STAT "); end
ADDR_QUAL : begin $fwrite(fd, "QUAL "); end
ADDR_DREQ : begin $fwrite(fd, "DREQ "); if (wcyc_r) dreq_reg <= ahb_hwdata[2:0]; end
ADDR_DREQ_SET : begin $fwrite(fd, "DREQ_SET "); if (wcyc_r) dreq_reg <= dreq_reg | ahb_hwdata[2:0]; end
ADDR_DREQ_CLR : begin $fwrite(fd, "DREQ_CLR "); if (wcyc_r) dreq_reg <= dreq_reg &~ahb_hwdata[2:0]; end
ADDR_DREQ_ACT : begin $fwrite(fd, "DREQ_ACT "); end
ADDR_IREQ : begin $fwrite(fd, "IREQ "); end
ADDR_IREQ_SET : begin $fwrite(fd, "IREQ_SET "); if (wcyc_r) ireq_reg <= ahb_hwdata[3:0]; end
ADDR_IREQ_CLR : begin $fwrite(fd, "IREQ_CLR "); if (wcyc_r) ireq_reg <= ireq_reg | ahb_hwdata[3:0]; end
ADDR_IREQ_ACT : begin $fwrite(fd, "IREQ_ACT "); if (wcyc_r) ireq_reg <= ireq_reg &~ahb_hwdata[3:0]; end
default:
if (addr16_r[15:14] == 2'b01) $fwrite(fd, "KEYBUF128 ");
else if (addr16_r[15:14] == 2'b10) $fwrite(fd, "IPBUF128 ");
else if (addr16_r[15:14] == 2'b11) $fwrite(fd, "OPBUF128 ");
endcase
$fwrite(fd, " A+0x%04x, %s, D=0x", addr16_r, (wcyc_r) ? "W" : "R");
if (byte4_r[3]) $fwrite(fd, "%02x", ahb_hdata[31:24]); else $fwrite(fd, "--");
if (byte4_r[2]) $fwrite(fd, "%02x", ahb_hdata[23:16]); else $fwrite(fd, "--");
if (byte4_r[1]) $fwrite(fd, "%02x", ahb_hdata[15: 8]); else $fwrite(fd, "--");
if (byte4_r[0]) $fwrite(fd, "%02x", ahb_hdata[ 7: 0]); else $fwrite(fd, "--");
if (TIMESTAMP) $fwrite(fd, ", CYC=%8d (@%t)\n", cyc_count, $time); else $fwrite(fd, "\n");
end
if (any_change) begin
$fwrite(fd, "AESRQ: ");
if (drq_change) begin
$fwrite(fd, " drq_ipdma128=%b,",drq_ipdma128);
$fwrite(fd, " dlast_ipdma128=%b,",dlast_ipdma128);
$fwrite(fd, " drq_opdma128=%b,",drq_opdma128);
$fwrite(fd, " dlast_opdma128=%b",dlast_opdma128);
end
if (irq_change) begin
if (drq_change) $fwrite(fd, ",");
$fwrite(fd, " irq_merged=%b,",irq_merged);
$fwrite(fd, "irq_key128=%b,",irq_key128);
$fwrite(fd, "irq_ip128=%b,",irq_ip128);
$fwrite(fd, "irq_op128=%b,",irq_op128);
$fwrite(fd, "irq_error=%b",irq_error);
end
if (TIMESTAMP) $fwrite(fd, ", CYC=%8d (@%t)\n",cyc_count, $time); else $fwrite(fd, "\n");
end
end
$fclose(fd);
end
end
endmodule
system/verif/verilog/nanosoc_tb.v 0 → 100644
+ 766
− 0
View file @ 09673ca2
//-----------------------------------------------------------------------------
// NanoSoC Testbench adpated from example Cortex-M0 controller testbench
// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
//
// Contributors
//
// David Flynn (d.w.flynn@soton.ac.uk)
//
// Copyright � 2021-3, SoC Labs (www.soclabs.org)
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from Arm Limited or its affiliates.
//
// (C) COPYRIGHT 2010-2013 Arm Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from Arm Limited or its affiliates.
//
// SVN Information
//
// Checked In : $Date: 2017-10-10 15:55:38 +0100 (Tue, 10 Oct 2017) $
//
// Revision : $Revision: 371321 $
//
// Release Information : Cortex-M System Design Kit-r1p1-00rel0
//
//-----------------------------------------------------------------------------
//-----------------------------------------------------------------------------
// Abstract : Testbench for the Cortex-M0 example system
//-----------------------------------------------------------------------------
//
`timescale 1ns/1ps
`define CORTEX_M0
module nanosoc_tb;
wire XTAL1; // crystal pin 1
wire XTAL2; // crystal pin 2
wire NRST; // active low reset
wire [15:0] P0; // Port 0
wire [15:0] P1; // Port 1
wire VDDIO;
wire VSSIO;
wire VDD;
wire VSS;
//Debug tester signals
wire nTRST;
wire TDI;
wire SWDIOTMS;
wire SWCLKTCK;
wire TDO;
wire PCLK; // Clock for UART capture device
wire [5:0] debug_command; // used to drive debug tester
wire debug_running; // indicate debug test is running
wire debug_err; // indicate debug test has error
wire debug_test_en1;
wire debug_test_en2;
wire debug_test_en; // To enable the debug tester connection to MCU GPIO P0
// This signal is controlled by software,
// Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
// the command, use "UartPutc((char) 0x11)" to send debug test
// enable command, use "UartPutc((char) 0x12)" to send debug test
// disable command. Refer to tb_uart_capture.v file for detail
assign debug_test_en = debug_test_en1 | debug_test_en2; // FT1248 or UART2 control
//-----------------------------------------
// System options
`define MEM_INIT 1;
localparam BE=0;
`define ARM_CMSDK_INCLUDE_DEBUG_TESTER 1
`ifdef ADP_FILE
localparam ADP_FILENAME=`ADP_FILE;
`else
localparam ADP_FILENAME="adp.cmd";
`endif
SROM_Ax32
#(.ADDRWIDTH (8),
.filename ("bootrom/hex/bootloader.hex"),
.romgen (1)
)
u_BOOTROM (
.CLK(XTAL1),
.ADDR(8'h0),
.SEL(1'b0),
.RDATA( )
);
// --------------------------------------------------------------------------------
// Cortex-M0/Cortex-M0+ Microcontroller
// --------------------------------------------------------------------------------
nanosoc_chip_pads
u_nanosoc_chip_pads (
`ifdef POWER_PINS
.VDDIO (VDDIO),
.VSSIO (VSSIO),
.VDD (VDD),
.VSS (VSS),
`endif
.XTAL1 (XTAL1), // input
.XTAL2 (XTAL2), // output
.NRST (NRST), // active low reset
.P0 (P0),
.P1 (P1),
.SWDIOTMS (SWDIOTMS),
.SWCLKTCK (SWCLKTCK)
);
// --------------------------------------------------------------------------------
// Source for clock and reset
// --------------------------------------------------------------------------------
nanosoc_clkreset u_nanosoc_clkreset(
.CLK (XTAL1),
.NRST (NRST)
);
// Pullup to suppress X-inputs
pullup(P0[ 0]);
pullup(P0[ 1]);
pullup(P0[ 2]);
pullup(P0[ 3]);
pullup(P0[ 4]);
pullup(P0[ 5]);
pullup(P0[ 6]);
pullup(P0[ 7]);
pullup(P0[ 8]);
pullup(P0[ 9]);
pullup(P0[10]);
pullup(P0[11]);
pullup(P0[12]);
pullup(P0[13]);
pullup(P0[14]);
pullup(P0[15]);
pullup(P1[ 0]);
pullup(P1[ 1]);
pullup(P1[ 2]);
pullup(P1[ 3]);
pullup(P1[ 4]);
pullup(P1[ 5]);
pullup(P1[ 6]);
pullup(P1[ 7]);
pullup(P1[ 8]);
pullup(P1[ 9]);
pullup(P1[10]);
pullup(P1[11]);
pullup(P1[12]);
pullup(P1[13]);
pullup(P1[14]);
pullup(P1[15]);
// --------------------------------------------------------------------------------
// UART output capture
// --------------------------------------------------------------------------------
`ifdef ARM_CMSDK_SLOWSPEED_PCLK
// If PCLK is running at slower speed, the UART output will also be slower
assign PCLK = u_cmsdk_mcu.u_cmsdk_mcu.PCLK;
`else
assign PCLK = XTAL1;
`endif
// --------------------------------------------------------------------------------
// external UART phase lock to (known) baud rate
// seem unable to use the following (due to generate instance naming?)
// wire baudx16_clk = u_cmsdk_mcu.u_cmsdk_mcu.u_cmsdk_mcu_system.u_apb_subsystem.u_apb_uart_2.BAUDTICK;
// 2000000/208 = 9615 baud (+0.16%)
// 208 / 16
`define BAUDPROG 130
reg [7:0] bauddiv;
wire baudclken = (bauddiv == 8'b00000000);
always @(negedge NRST or posedge PCLK)
if (!NRST)
bauddiv <=0;
else
bauddiv <= (baudclken) ? (`BAUDPROG-1) : (bauddiv -1) ; // count down of BAUDPROG
wire baudx16_clk = bauddiv[7]; //prefer:// !baudclken;
wire UARTXD = P1[5];
reg UARTXD_del;
always @(negedge NRST or posedge baudx16_clk)
if (!NRST)
UARTXD_del <= 1'b0;
else
UARTXD_del <= UARTXD; // delay one BAUD_TICK-time
wire UARTXD_edge = UARTXD_del ^ UARTXD; // edge detect
reg [3:0] pllq;
always @(negedge NRST or posedge baudx16_clk)
if (!NRST)
pllq[3:0] <= 4'b0000; // phase lock ready for Q[3] to go high
else
if (UARTXD_edge)
pllq[3:0] <= 4'b0110; // sync to mid bit-time
else
pllq[3:0] <= pllq[3:0] - 1; // count down divide-by-16
wire baud_clk = pllq[3];
reg baud_clk_del;
always @(negedge NRST or posedge PCLK)
if (!NRST)
baud_clk_del <= 1'b1;
else
baud_clk_del <= baud_clk;
// --------------------------------------------------------------------------------
// set FASTMODE true if UART simulation mode is programmed
wire FASTMODE = 1'b0;
wire uart_clk = (FASTMODE) ? PCLK : baud_clk; //(baud_clk & !baud_clk_del);
nanosoc_uart_capture #(.LOGFILENAME("logs/uart2.log"))
u_nanosoc_uart_capture(
.RESETn (NRST),
.CLK (uart_clk), //PCLK),
.RXD (UARTXD), // UART 2 use for StdOut
.DEBUG_TESTER_ENABLE (debug_test_en2),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
// --------------------------------------------------------------------------------
// FTDI IO capture
// --------------------------------------------------------------------------------
// UART connection cross over for UART test
// assign P1[0] = P1[3]; // UART 0 RXD = UART 1 TXD
// assign P1[2] = P1[1]; // UART 1 RXD = UART 0 TXD
assign P1[4] = P1[5]; // loopback UART2
wire ft_clk_out = P1[1];
wire ft_miso_in;
assign P1[0] = ft_miso_in;
wire ft_ssn_out = P1[3];
//
// AXI stream io testing
//
wire txd8_ready;
wire txd8_valid;
wire [7:0] txd8_data ;
wire rxd8_ready;
wire rxd8_valid;
wire [7:0] rxd8_data ;
nanosoc_axi_stream_io_8_txd_from_file
#(.TXDFILENAME(ADP_FILENAME))
u_nanosoc_axi_stream_io_8_txd_from_file
(
.aclk (XTAL1),
.aresetn (NRST),
.txd8_ready (txd8_ready),
.txd8_valid (txd8_valid),
.txd8_data (txd8_data)
);
/*
axi_stream_io_8_buffer
u_axi_stream_io_8_buffer
(
.aclk (XTAL1),
.aresetn (NRST),
.rxd8_ready (txd8_ready),
.rxd8_valid (txd8_valid),
.rxd8_data (txd8_data),
.txd8_ready (rxd8_ready),
.txd8_valid (rxd8_valid),
.txd8_data (rxd8_data)
);
*/
wire ft_miosio_o;
wire ft_miosio_z;
wire ft_miosio_i = P1[2]; // & ft_miosio_z;
assign P1[2] = (ft_miosio_z) ? 1'bz : ft_miosio_o;
nanosoc_ft1248x1_to_axi_streamio_v1_0
u_nanosoc_ft1248x1_to_axi_streamio_v1_0
(
.ft_clk_i (ft_clk_out),
.ft_ssn_i (ft_ssn_out),
.ft_miso_o (ft_miso_in),
.ft_miosio_i (ft_miosio_i),
.ft_miosio_o (ft_miosio_o),
.ft_miosio_z (ft_miosio_z),
.aclk (XTAL1),
.aresetn (NRST),
.rxd_tready_o (txd8_ready),
.rxd_tvalid_i (txd8_valid),
.rxd_tdata8_i (txd8_data),
.txd_tready_i (rxd8_ready),
.txd_tvalid_o (rxd8_valid),
.txd_tdata8_o (rxd8_data)
);
nanosoc_axi_stream_io_8_rxd_to_file
#(.RXDFILENAME("logs/ft1248_out.log"))
u_nanosoc_axi_stream_io_8_rxd_to_file
(
.aclk (XTAL1),
.aresetn (NRST),
.rxd8_ready (rxd8_ready),
.rxd8_valid (rxd8_valid),
.rxd8_data (rxd8_data)
);
nanosoc_track_tb_iostream
u_nanosoc_track_tb_iostream
(
.aclk (XTAL1),
.aresetn (NRST),
.rxd8_ready (rxd8_ready),
.rxd8_valid (rxd8_valid),
.rxd8_data (rxd8_data),
.DEBUG_TESTER_ENABLE (debug_test_en1),
.AUXCTRL ( ),
.SIMULATIONEND( )
);
wire ft_clk2uart;
wire ft_rxd2uart;
wire ft_txd2uart;
nanosoc_ft1248x1_track
u_nanosoc_ft1248x1_track
(
.ft_clk_i (ft_clk_out),
.ft_ssn_i (ft_ssn_out),
.ft_miso_i (ft_miso_in),
.ft_miosio_i (ft_miosio_i),
.aclk (XTAL1),
.aresetn (NRST),
.FTDI_CLK2UART_o (ft_clk2uart), // Clock (baud rate)
.FTDI_OP2UART_o (ft_rxd2uart), // Received data to UART capture
.FTDI_IP2UART_o (ft_txd2uart) // Transmitted data to UART capture
);
nanosoc_uart_capture #(.LOGFILENAME("logs/ft1248_op.log"))
u_nanosoc_uart_capture1(
.RESETn (NRST),
.CLK (ft_clk2uart),
.RXD (ft_rxd2uart),
.DEBUG_TESTER_ENABLE (debug_test_en1),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
nanosoc_uart_capture #(.LOGFILENAME("logs/ft1248_ip.log"))
u_nanosoc_uart_capture2(
.RESETn (NRST),
.CLK (ft_clk2uart),
.RXD (ft_txd2uart),
.DEBUG_TESTER_ENABLE ( ),
.SIMULATIONEND (), // This signal set to 1 at the end of simulation.
.AUXCTRL ()
);
// --------------------------------------------------------------------------------
// Tracking CPU with Tarmac trace support
// --------------------------------------------------------------------------------
`ifdef CORTEX_M0
`ifdef USE_TARMAC
`define ARM_CM0IK_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_cpu.u_cortex_m0_integration.u_cortexm0
CORTEXM0
#(.ACG(1), .AHBSLV(0), .BE(0), .BKPT(4),
.DBG(1), .NUMIRQ(32), .RAR(1), .SMUL(0),
.SYST(1), .WIC(1), .WICLINES(34), .WPT(2))
u_cortexm0_track
(
// Outputs
.HADDR ( ),
.HBURST ( ),
.HMASTLOCK ( ),
.HPROT ( ),
.HSIZE ( ),
.HTRANS ( ),
.HWDATA ( ),
.HWRITE ( ),
.HMASTER ( ),
.SLVRDATA ( ),
.SLVREADY ( ),
.SLVRESP ( ),
.DBGRESTARTED ( ),
.HALTED ( ),
.TXEV ( ),
.LOCKUP ( ),
.SYSRESETREQ ( ),
.CODENSEQ ( ),
.CODEHINTDE ( ),
.SPECHTRANS ( ),
.SLEEPING ( ),
.SLEEPDEEP ( ),
.SLEEPHOLDACKn ( ),
.WICDSACKn ( ),
.WICMASKISR ( ),
.WICMASKNMI ( ),
.WICMASKRXEV ( ),
.WICLOAD ( ),
.WICCLEAR ( ),
// Inputs
.SCLK (`ARM_CM0IK_PATH.SCLK),
.HCLK (`ARM_CM0IK_PATH.HCLK),
.DCLK (`ARM_CM0IK_PATH.DCLK),
.DBGRESETn (`ARM_CM0IK_PATH.DBGRESETn),
.HRESETn (`ARM_CM0IK_PATH.HRESETn),
.HRDATA (`ARM_CM0IK_PATH.HRDATA[31:0]),
.HREADY (`ARM_CM0IK_PATH.HREADY),
.HRESP (`ARM_CM0IK_PATH.HRESP),
.SLVADDR (`ARM_CM0IK_PATH.SLVADDR[31:0]),
.SLVSIZE (`ARM_CM0IK_PATH.SLVSIZE[1:0]),
.SLVTRANS (`ARM_CM0IK_PATH.SLVTRANS[1:0]),
.SLVWDATA (`ARM_CM0IK_PATH.SLVWDATA[31:0]),
.SLVWRITE (`ARM_CM0IK_PATH.SLVWRITE),
.DBGRESTART (`ARM_CM0IK_PATH.DBGRESTART),
.EDBGRQ (`ARM_CM0IK_PATH.EDBGRQ),
.NMI (`ARM_CM0IK_PATH.NMI),
.IRQ (`ARM_CM0IK_PATH.IRQ[31:0]),
.RXEV (`ARM_CM0IK_PATH.RXEV),
.STCALIB (`ARM_CM0IK_PATH.STCALIB[25:0]),
.STCLKEN (`ARM_CM0IK_PATH.STCLKEN),
.IRQLATENCY (`ARM_CM0IK_PATH.IRQLATENCY[7:0]),
.ECOREVNUM (`ARM_CM0IK_PATH.ECOREVNUM[19:0]),
.SLEEPHOLDREQn (`ARM_CM0IK_PATH.SLEEPHOLDREQn),
.WICDSREQn (`ARM_CM0IK_PATH.WICDSREQn),
.SE (`ARM_CM0IK_PATH.SE));
`define ARM_CM0IK_TRACK u_cortexm0_track
cm0_tarmac #(.LOGFILENAME("logs/tarmac0.log"))
u_tarmac_track
(.enable_i (1'b1),
.hclk_i (`ARM_CM0IK_TRACK.HCLK),
.hready_i (`ARM_CM0IK_TRACK.HREADY),
.haddr_i (`ARM_CM0IK_TRACK.HADDR[31:0]),
.hprot_i (`ARM_CM0IK_TRACK.HPROT[3:0]),
.hsize_i (`ARM_CM0IK_TRACK.HSIZE[2:0]),
.hwrite_i (`ARM_CM0IK_TRACK.HWRITE),
.htrans_i (`ARM_CM0IK_TRACK.HTRANS[1:0]),
.hresetn_i (`ARM_CM0IK_TRACK.HRESETn),
.hresp_i (`ARM_CM0IK_TRACK.HRESP),
.hrdata_i (`ARM_CM0IK_TRACK.HRDATA[31:0]),
.hwdata_i (`ARM_CM0IK_TRACK.HWDATA[31:0]),
.lockup_i (`ARM_CM0IK_TRACK.LOCKUP),
.halted_i (`ARM_CM0IK_TRACK.HALTED),
.codehintde_i (`ARM_CM0IK_TRACK.CODEHINTDE[2:0]),
.codenseq_i (`ARM_CM0IK_TRACK.CODENSEQ),
.hdf_req_i (`ARM_CM0IK_TRACK.u_top.u_sys.ctl_hdf_request),
.int_taken_i (`ARM_CM0IK_TRACK.u_top.u_sys.dec_int_taken_o),
.int_return_i (`ARM_CM0IK_TRACK.u_top.u_sys.dec_int_return_o),
.int_pend_i (`ARM_CM0IK_TRACK.u_top.u_sys.nvm_int_pend),
.pend_num_i (`ARM_CM0IK_TRACK.u_top.u_sys.nvm_int_pend_num[5:0]),
.ipsr_i (`ARM_CM0IK_TRACK.u_top.u_sys.psr_ipsr[5:0]),
.ex_last_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_ex_last),
.iaex_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_iaex_en),
.reg_waddr_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_wr_addr[3:0]),
.reg_write_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_wr_en),
.xpsr_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.ctl_xpsr_en),
.fe_addr_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_fe_addr[30:0]),
.int_delay_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_int_delay),
.special_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_op_special),
.opcode_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.pfu_opcode[15:0]),
.reg_wdata_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.psr_gpr_wdata[31:0]),
.atomic_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.atomic),
.atomic_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.atomic_nxt),
.dabort_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.data_abort),
.ex_last_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.ex_last_nxt),
.int_preempt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_ctl.int_preempt),
.psp_sel_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_gpr.psp_sel),
.xpsr_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_gpr.xpsr[31:0]),
.iaex_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.iaex[30:0]),
.iaex_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.iaex_nxt[30:0]),
.opcode_nxt_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.ibuf_de_nxt[15:0]),
.delay_count_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.ibuf_lo[13:6]),
.tbit_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_pfu.tbit_en),
.cflag_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.cflag_ena),
.ipsr_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.ipsr_ena),
.nzflag_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.nzflag_ena),
.vflag_en_i (`ARM_CM0IK_TRACK.u_top.u_sys.u_core.u_psr.vflag_ena)
);
`endif // USE_TARMAC
`endif // CORTEX_M0
// --------------------------------------------------------------------------------
// Tracking DMA logging support
// - Track inputs to on-chip PL230 DMAC and replicate state and outputs in testbench
// - log the RTL Inuts/outputs/internal-state of this traccking DMAC
// --------------------------------------------------------------------------------
`define DMAC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_pl230_udma
pl230_udma u_track_pl230_udma (
// Clock and Reset
.hclk (`DMAC_PATH.hclk),
.hresetn (`DMAC_PATH.hresetn),
// DMA Control
.dma_req (`DMAC_PATH.dma_req),
.dma_sreq (`DMAC_PATH.dma_sreq),
.dma_waitonreq (`DMAC_PATH.dma_waitonreq),
.dma_stall (`DMAC_PATH.dma_stall),
.dma_active ( ),
.dma_done ( ),
.dma_err ( ),
// AHB-Lite Master Interface
.hready (`DMAC_PATH.hready),
.hresp (`DMAC_PATH.hresp),
.hrdata (`DMAC_PATH.hrdata),
.htrans ( ),
.hwrite ( ),
.haddr ( ),
.hsize ( ),
.hburst ( ),
.hmastlock ( ),
.hprot ( ),
.hwdata ( ),
// APB Slave Interface
.pclken (`DMAC_PATH.pclken),
.psel (`DMAC_PATH.psel),
.pen (`DMAC_PATH.pen),
.pwrite (`DMAC_PATH.pwrite),
.paddr (`DMAC_PATH.paddr),
.pwdata (`DMAC_PATH.pwdata),
.prdata ( )
);
`define DMAC_TRACK_PATH u_track_pl230_udma
nanosoc_dma_log_to_file #(.FILENAME("logs/dma230.log"),.NUM_CHNLS(2),.NUM_CHNL_BITS(1),.TIMESTAMP(1))
u_nanosoc_dma_log_to_file (
.hclk (`DMAC_TRACK_PATH.hclk),
.hresetn (`DMAC_TRACK_PATH.hresetn),
// AHB-Lite Master Interface
.hready (`DMAC_TRACK_PATH.hready),
.hresp (`DMAC_TRACK_PATH.hresp),
.hrdata (`DMAC_TRACK_PATH.hrdata),
.htrans (`DMAC_TRACK_PATH.htrans),
.hwrite (`DMAC_TRACK_PATH.hwrite),
.haddr (`DMAC_TRACK_PATH.haddr),
.hsize (`DMAC_TRACK_PATH.hsize),
.hburst (`DMAC_TRACK_PATH.hburst),
.hprot (`DMAC_TRACK_PATH.hprot),
.hwdata (`DMAC_TRACK_PATH.hwdata),
// APB control interface
.pclken (`DMAC_TRACK_PATH.pclken),
.psel (`DMAC_TRACK_PATH.psel),
.pen (`DMAC_TRACK_PATH.pen),
.pwrite (`DMAC_TRACK_PATH.pwrite),
.paddr (`DMAC_TRACK_PATH.paddr),
.pwdata (`DMAC_TRACK_PATH.pwdata),
.prdata (`DMAC_TRACK_PATH.prdata),
// DMA Control
.dma_req (`DMAC_TRACK_PATH.dma_req),
.dma_active (`DMAC_TRACK_PATH.dma_active),
.dma_done (`DMAC_TRACK_PATH.dma_done),
// DMA state from tracking RTL model
.dma_chnl (`DMAC_TRACK_PATH.u_pl230_ahb_ctrl.current_chnl),
.dma_ctrl_state(`DMAC_TRACK_PATH.u_pl230_ahb_ctrl.ctrl_state)
);
// --------------------------------------------------------------------------------
// Tracking Accelerator logging support
// --------------------------------------------------------------------------------
`define ACC_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper
nanosoc_acc_log_to_file #(.FILENAME("logs/acc_exp.log"),.CFGNUMIRQ(4),.TIMESTAMP(1))
u_nanosoc_acc_log_to_file (
.HCLK (`ACC_PATH.HCLK ),
.HRESETn (`ACC_PATH.HRESETn ),
.HSEL_i (`ACC_PATH.HSEL_i ),
.HADDR_i (`ACC_PATH.HADDR_i ),
.HTRANS_i (`ACC_PATH.HTRANS_i ),
.HWRITE_i (`ACC_PATH.HWRITE_i ),
.HSIZE_i (`ACC_PATH.HSIZE_i ),
.HPROT_i (`ACC_PATH.HPROT_i ),
.HWDATA_i (`ACC_PATH.HWDATA_i ),
.HREADY_i (`ACC_PATH.HREADY_i ),
.HRDATA_o (`ACC_PATH.HRDATA_o ),
.HREADYOUT_o (`ACC_PATH.HREADYOUT_o ),
.HRESP_o (`ACC_PATH.HRESP_o ),
.exp_drq_ip_o (`ACC_PATH.exp_drq_ip_o ),
.exp_dlast_ip_i (`ACC_PATH.exp_dlast_ip_i),
.exp_drq_op_o (`ACC_PATH.exp_drq_op_o ),
.exp_dlast_op_i (`ACC_PATH.exp_dlast_op_i),
.exp_irq_o (`ACC_PATH.exp_irq_o )
);
`define AES_PATH u_nanosoc_chip_pads.u_nanosoc_chip.u_nanosoc_exp_wrapper.u_exp_aes128
aes128_log_to_file #(.FILENAME("logs/aes128.log"),.TIMESTAMP(1))
u_aes_log_to_file (
.ahb_hclk (`AES_PATH.ahb_hclk ),
.ahb_hresetn (`AES_PATH.ahb_hresetn ),
.ahb_hsel (`AES_PATH.ahb_hsel ),
.ahb_haddr16 (`AES_PATH.ahb_haddr16 ),
.ahb_htrans (`AES_PATH.ahb_htrans ),
.ahb_hwrite (`AES_PATH.ahb_hwrite ),
.ahb_hsize (`AES_PATH.ahb_hsize ),
.ahb_hprot (`AES_PATH.ahb_hprot ),
.ahb_hwdata (`AES_PATH.ahb_hwdata ),
.ahb_hready (`AES_PATH.ahb_hready ),
.ahb_hrdata (`AES_PATH.ahb_hrdata ),
.ahb_hreadyout (`AES_PATH.ahb_hreadyout ),
.ahb_hresp (`AES_PATH.ahb_hresp ),
.drq_ipdma128 (`AES_PATH.drq_ipdma128 ),
.dlast_ipdma128 (`AES_PATH.dlast_ipdma128),
.drq_opdma128 (`AES_PATH.drq_opdma128 ),
.dlast_opdma128 (`AES_PATH.dlast_opdma128),
.irq_key128 (`AES_PATH.irq_key128 ),
.irq_ip128 (`AES_PATH.irq_ip128 ),
.irq_op128 (`AES_PATH.irq_op128 ),
.irq_error (`AES_PATH.irq_error ),
.irq_merged (`AES_PATH.irq_merged )
);
// --------------------------------------------------------------------------------
// Debug tester connection -
// --------------------------------------------------------------------------------
`ifdef ARM_CMSDK_INCLUDE_DEBUG_TESTER
// Add pullups and pulldowns on Debug Interface
pullup (nTRST);
pullup (TDI);
pullup (TDO);
pullup (SWDIOTMS);
pulldown (SWCLKTCK);
//connect to P0 for debug command and status pin
//add pulldown to debug command and debug status signals
// to give default value 0;
pulldown(debug_command[5]);
pulldown(debug_command[4]);
pulldown(debug_command[3]);
pulldown(debug_command[2]);
pulldown(debug_command[1]);
pulldown(debug_command[0]);
pulldown(debug_running);
pulldown(debug_err);
//Tristate logic for GPIO connection
bufif1 (debug_command[5], P0[29-16], debug_test_en);
bufif1 (debug_command[4], P0[28-16], debug_test_en);
bufif1 (debug_command[3], P0[27-16], debug_test_en);
bufif1 (debug_command[2], P0[26-16], debug_test_en);
bufif1 (debug_command[1], P0[25-16], debug_test_en);
bufif1 (debug_command[0], P0[24-16], debug_test_en);
bufif1 (P0[31-16], debug_running, debug_test_en);
bufif1 (P0[30-16], debug_err, debug_test_en);
cmsdk_debug_tester #(.ROM_MEMFILE((BE==1) ? "debugtester_be.hex" : "debugtester_le.hex"))
u_cmsdk_debug_tester
(
// Clock and Reset
.CLK (XTAL1),
.PORESETn (NRST),
// Command Interface
.DBGCMD (debug_command[5:0]),
.DBGRUNNING (debug_running),
.DBGERROR (debug_err),
// Trace Interface
.TRACECLK (1'b0),
.TRACEDATA (4'h0),
.SWV (1'b0),
// Debug Interface
.TDO (TDO),
.nTRST (nTRST),
.SWCLKTCK (SWCLKTCK),
.TDI (TDI),
.SWDIOTMS (SWDIOTMS)
);
`endif
// --------------------------------------------------------------------------------
// Misc
// --------------------------------------------------------------------------------
// Format for time reporting
initial $timeformat(-9, 0, " ns", 0);
// Configuration checks
initial begin
`ifdef CORTEX_M0DESIGNSTART
`ifdef CORTEX_M0
$display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0 are set. Please use only one.");
$stop;
`endif
`endif
`ifdef CORTEX_M0DESIGNSTART
`ifdef CORTEX_M0PLUS
$display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : Both CORTEX_M0DESIGNSTART and CORTEX_M0PLUS are set. Please use only one.");
$stop;
`endif
`endif
`ifdef CORTEX_M0
`ifdef CORTEX_M0PLUS
$display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : Both CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
$stop;
`endif
`endif
`ifdef CORTEX_M0DESIGNSTART
`ifdef CORTEX_M0
`ifdef CORTEX_M0PLUS
$display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : All of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please use only one.");
$stop;
`endif
`endif
`endif
`ifdef CORTEX_M0
`else
`ifdef CORTEX_M0PLUS
`else
`ifdef CORTEX_M0DESIGNSTART
`else
$display("ERROR (nanosoc_tb.v) in CPU preprocessing directive : None of CORTEX_M0DESIGNSTART, CORTEX_M0 and CORTEX_M0PLUS are set. Please select one.");
$stop;
`endif
`endif
`endif
end
endmodule
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