diff --git a/implement/fpga/imp/.git_ignore b/implement/fpga/imp/.git_ignore
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/implement/fpga/xilinx_vivado/CI_verification/.gitkeep b/implement/fpga/xilinx_vivado/CI_verification/.gitkeep
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/implement/fpga/xilinx_vivado/CI_verification/load_bitfile.py b/implement/fpga/xilinx_vivado/CI_verification/load_bitfile.py
new file mode 100644
index 0000000000000000000000000000000000000000..2e4c01a48344380b10f20a087b6af8f293a00971
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/CI_verification/load_bitfile.py
@@ -0,0 +1,17 @@
+import os, warnings
+from pynq import PL
+from pynq import Overlay
+
+ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design_1.bit")
+
+if not os.path.exists(PL.bitfile_name):
+ warnings.warn('There is no overlay loaded after boot.', UserWarning)
+
+ol = Overlay(PL.bitfile_name)
+
+ol.download()
+
+if ol.is_loaded():
+ print("Overlay Loaded")
+else:
+ print("Overlay failed to load")
diff --git a/implement/fpga/xilinx_vivado/CI_verification/load_file_output b/implement/fpga/xilinx_vivado/CI_verification/load_file_output
new file mode 100644
index 0000000000000000000000000000000000000000..1a433d8cf732503b1ccd02d28f4c408aba763f7b
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/CI_verification/load_file_output
@@ -0,0 +1 @@
+Overlay Loaded
diff --git a/implement/fpga/xilinx_vivado/CI_verification/run_ADP_verification.py b/implement/fpga/xilinx_vivado/CI_verification/run_ADP_verification.py
new file mode 100644
index 0000000000000000000000000000000000000000..270290af9c83a29931667b58c30f09efaf5a0905
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/CI_verification/run_ADP_verification.py
@@ -0,0 +1,128 @@
+import os, warnings
+from pynq import PL
+from pynq import Overlay
+
+from pynq import Overlay
+from pynq import MMIO
+import time
+from time import sleep, time
+
+# HARDWARE CONSTANTS
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+# Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+
+# Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class ADPIO:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address, 0x10000, debug=False)
+ self.address = address
+
+ def setupCtrlReg(self):
+# # Reset FIFOs, disable interrupts
+# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)
+# sleep(1)
+ self.uart.write(CTRL_REG, 0)
+ sleep(1)
+
+ def monitorModeEnter(self):
+ self.uart.write(TX_FIFO, 0x1b)
+
+ def monitorModeExit(self):
+ self.uart.write(TX_FIFO, 0x04)
+
+ def read(self, count, timeout=1):
+ # status = currentStatus(uart) bad idea
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, stop waiting if timeoutpasses
+ while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):
+ pass
+ if time() >= stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout=1):
+ # Write bytes via UART
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ # Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):
+ pass
+ # Check timeout
+ if time() > stop_time:
+ wr_count = -1
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+
+
+ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design.bit")
+ol = Overlay(PL.bitfile_name)
+ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']
+print("ADPIO stream interface: ",hex(ADP_address))
+
+adp = ADPIO(ADP_address)
+# Setup AXI UART register
+adp.setupCtrlReg()
+print(adp.read(100))
+
+adp.monitorModeEnter()
+print(adp.read(4))
+
+adp.write('A\n')
+print(adp.read(100))
+
+adp.write('A 0x10000000\nR 4\n')
+print(adp.read(100))
+
+adp.write('A 0x30000000\nR\nR \n')
+print(adp.read(100))
+
+adp.write('A 0x30000000\nW 0x11111111\nW22222222\n')
+print(adp.read(100))
+
+adp.write('A 0x30000000\nR 3\n')
+print(adp.read(100))
+
+adp.write('A 0x50000000\nW 0x11111111\nW22222222\n')
+print(adp.read(100))
+
+adp.write('A 0x50000000\nR 2\n')
+print(adp.read(100))
+
+adp.write('A 10000000\nM 0xF0000000\nV 0\nP 4000\n')
+print(adp.read(100))
+adp.write('A 10000000\nM\nV 30000000\nP 2000\n')
+print(adp.read(100))
+
+adp.write('A 90000000\nV 0x87654321\nF 400\nA\nW FFFFFFFF\n')
+print(adp.read(100))
+
+adp.write('A 0x90000000\nR 3\n')
+print(adp.read(100))
+adp.write('A 0x90000FFC\nr 0003\n\nA\n')
+print(adp.read(100))
+
+adp.write('S 0x31\n\n')
+print(adp.read(100))
+
+adp.monitorModeExit()
+print(adp.read(100))
diff --git a/implement/fpga/xilinx_vivado/CI_verification/test_bitfile_ZCU104.sh b/implement/fpga/xilinx_vivado/CI_verification/test_bitfile_ZCU104.sh
new file mode 100644
index 0000000000000000000000000000000000000000..d7076bdbcc3e96225ff51e41265ecd7c27314bc9
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/CI_verification/test_bitfile_ZCU104.sh
@@ -0,0 +1,9 @@
+#!/bin/bash
+
+if (grep -r "Overlay Loaded" ./screenlog)
+then
+ echo "Bit file loaded successfully"
+else
+ echo "Bit file load failed"
+ exit 1
+fi
diff --git a/implement/fpga/xilinx_vivado/build_fpga_arm_MPS3.scr b/implement/fpga/xilinx_vivado/build_fpga_arm_MPS3.scr
new file mode 100755
index 0000000000000000000000000000000000000000..4ce70edaf44334115d4c044d3a65307efbedaced
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/build_fpga_arm_MPS3.scr
@@ -0,0 +1 @@
+vivado -mode batch -source scripts/build_mcu_fpga_arm_mps3.tcl
diff --git a/implement/fpga/xilinx_vivado/build_fpga_pynq_z2.scr b/implement/fpga/xilinx_vivado/build_fpga_pynq_z2.scr
new file mode 100755
index 0000000000000000000000000000000000000000..091e8c59fa646d48406bd548b678b371f27bb16a
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/build_fpga_pynq_z2.scr
@@ -0,0 +1,4 @@
+cd $SOCLABS_FPGA_IMP_PATH/../imp/
+mkdir build_nanosoc_fpga_pynq_z2
+cd build_nanosoc_fpga_pynq_z2
+vivado -mode tcl -source $SOCLABS_FPGA_IMP_PATH/scripts/build_mcu_fpga_pynq_z2.tcl
diff --git a/implement/fpga/xilinx_vivado/build_fpga_pynq_zcu104.scr b/implement/fpga/xilinx_vivado/build_fpga_pynq_zcu104.scr
new file mode 100755
index 0000000000000000000000000000000000000000..14f78259dd084448dfbc7231390a5b8a945f4391
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/build_fpga_pynq_zcu104.scr
@@ -0,0 +1,4 @@
+cd $SOCLABS_FPGA_IMP_PATH/../imp/
+mkdir build_nanosoc_fpga_pynq_zcu104
+cd build_nanosoc_fpga_pynq_zcu104
+vivado -mode batch -source $SOCLABS_FPGA_IMP_PATH/scripts/build_mcu_fpga_pynq_zcu104.tcl
diff --git a/implement/fpga/xilinx_vivado/clean_fpga.scr b/implement/fpga/xilinx_vivado/clean_fpga.scr
new file mode 100755
index 0000000000000000000000000000000000000000..cf4b0fa112dd2ffa1a1ffa37cdbbd9370d5a772b
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/clean_fpga.scr
@@ -0,0 +1,8 @@
+rm -f ./pynq_export/pz2/pynq/overlays/soclabs/*
+rm -f ./pynq_export/pz104/pynq/overlays/soclabs/*
+rm -Rf ./project_pynq_z2
+rm -Rf ./project_pynq_zcu104
+rm -Rf ./vivado*
+rm -Rf ./.gen
+rm -Rf ./.srcs
+rm -Rf ./.Xil
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/bd/bd.tcl b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/bd/bd.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..690e4e124478e7a541fa5bd5469dc6447e9f893f
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/component.xml b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/component.xml
new file mode 100755
index 0000000000000000000000000000000000000000..8b1054692e746f6c07edeebdb9718ef729fa8d6f
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/component.xml
@@ -0,0 +1,1425 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>ADPcontrol</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>com_rx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_rx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_rx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_rx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.COM_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>com_tx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_tx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_tx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>com_tx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.COM_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>stdio_rx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_rx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_rx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_rx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.STDIO_RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>stdio_tx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_tx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_tx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>stdio_tx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.STDIO_TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ahb</spirit:name>
+ <spirit:displayName>AHB_M</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ahblite" spirit:version="2.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="ahblite_rtl" spirit:version="2.0"/>
+ <spirit:master>
+ <spirit:addressSpaceRef spirit:addressSpaceRef="ahb"/>
+ </spirit:master>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HTRANS</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_htrans</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hprot</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HSIZE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hsize</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hrdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWRITE</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hwrite</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_haddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HMASTLOCK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hmastlock</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HBURST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hburst</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>HWDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hwdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ahb_hclk</spirit:name>
+ <spirit:displayName>hclk</spirit:displayName>
+ <spirit:description>rising-edge clock</spirit:description>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:description>100000000</spirit:description>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.FREQ_HZ"/>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.ASSOCIATED_BUSIF">com_rx:com_tx:stdio_rx:stdio_tx:ahb</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.ASSOCIATED_RESET">ahb_hresetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HCLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ahb_hresetn</spirit:name>
+ <spirit:displayName>hresetn</spirit:displayName>
+ <spirit:description>active low reset</spirit:description>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>ahb_hresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.AHB_HRESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:addressSpaces>
+ <spirit:addressSpace>
+ <spirit:name>ahb</spirit:name>
+ <spirit:range spirit:format="bitString" spirit:resolve="user">0x100000000</spirit:range>
+ <spirit:width spirit:format="long" spirit:resolve="user">32</spirit:width>
+ <spirit:vendorExtensions>
+ <xilinx:addressSpaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="user" xilinx:id="ADDRSPACE_ENABLEMENT.ahb">true</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:addressSpaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:addressSpace>
+ </spirit:addressSpaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesis</spirit:name>
+ <spirit:displayName>Verilog Synthesis</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>ADPcontrol_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>e4d9de63</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+ <spirit:displayName>Verilog Simulation</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>ADPcontrol_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>e4d9de63</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>936ced64</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>bd_tcl</spirit:name>
+ <spirit:displayName>Block Diagram</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>bd_tcl_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>16328387</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>ahb_hclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hresetn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_rx_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_rx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_rx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_tx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_tx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>com_tx_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_rx_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_rx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_rx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_tx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_tx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>stdio_tx_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>gpo8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>gpi8</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_haddr</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hburst</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hmastlock</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hprot</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hsize</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_htrans</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hwdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hwrite</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hrdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ahb_hresp</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ <spirit:modelParameters>
+ <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="string">
+ <spirit:name>PROMPT_CHAR</spirit:name>
+ <spirit:displayName>Prompt Char</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.PROMPT_CHAR">]</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_6fc15197</spirit:name>
+ <spirit:enumeration>32</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_9d8b0d81</spirit:name>
+ <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>src/ADPmanager.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>src/ADPcontrol_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_4c40ce83</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>src/ADPmanager.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>src/ADPcontrol_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>xgui/ADPcontrol_v1_0.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_936ced64</spirit:userFileType>
+ <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>bd_tcl_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>bd/bd.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>ADP AHB controller</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ADPcontrol_v1_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PROMPT_CHAR</spirit:name>
+ <spirit:displayName>Prompt Char</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PROMPT_CHAR">]</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:supportedFamilies>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
+ </xilinx:supportedFamilies>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>ADPcontrol_v1.0</xilinx:displayName>
+ <xilinx:autoFamilySupportLevel>level_1</xilinx:autoFamilySupportLevel>
+ <xilinx:coreRevision>28</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2023-03-17T11:11:19Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1d457846_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@37c19d7d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4d9c63f5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3486ae33_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@16991627_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@21280f5b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2a6297f7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@d359ebf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@585c5d69_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13554121_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5cc15ddd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@47f5cea9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2797f52a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2d4db012_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4d5ff66d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@160f397b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@9eedd13_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@383df36f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5b29af4a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6a844f8f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@dd3613f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@465ab221_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2c2a723e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7769a864_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2b6e7c2b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@348806c9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@543e517b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23a5fd27_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5acc4197_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1b0672e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1fcd885_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3b8348bf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7a2cf9c9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@266167bd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@75fc528d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@571f957b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@205b72be_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@18af816d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@76808038_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@12b6bb23_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@571354b0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@49208c72_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@96cf3b7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@160b7175_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@733792a3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6741cc7c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@21688aa5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@15d88077_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3dedcd2d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@109e8ade_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@66efa591_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@33406c6a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1295e34_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23a10fd2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@46b3edc3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@79223f91_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@25bf4cbd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3bf95837_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2d5a6e80_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23cef462_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7701c845_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@d900de2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1b614769_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2a1ab09c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5a71cfc7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7737ed39_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3417e460_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5dcd78cc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@87e31dd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5878b3d1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@414f7e53_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@448f5b33_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5f4942b4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@68082003_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@67b73b35_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@63825d52_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@59bce76e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@511d4c77_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1c74144d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4e4c1934_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@378bcf30_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4e795a88_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ad7045c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ae82c3f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4ac8e1b1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@72e7dc1b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@36456a91_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3994cf09_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c751ad6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@44a8e456_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@58f80386_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@60462d25_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@19c41859_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3a040f48_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7d1e622a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5592457_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7aa4d1b7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5b291a28_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1cad021e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7376878e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4870a6f7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2fc3ca30_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77cf444c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a9a0814_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1424fd5e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3453af13_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27e0072f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@f46a21a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@18d268d4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5c1b0b80_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2973e675_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@604ab08f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3ba14fe4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@223f211e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@15bffbbe_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@dc2fd1e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@54866dfc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@49d29cb3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6317da2d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2dea1246_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@22205824_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@71fb215a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3f69f943_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@10598249_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@69cc5be9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@30744b50_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77c27106_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@17c7c0e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b1dc1ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13c92119_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@433c97e8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@dfaa30_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@498e3871_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@68ef63bf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@cabff58_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6329d1ac_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3d41686b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@17b94c6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@73c60546_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1efb46d6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1c3fd36_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@94a143_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27fa8005_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@62074f67_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3c35c7f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23404941_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1ca68904_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3bf56a5a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1af8595a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7883ae7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3a942794_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@148bd7e5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@73d73a56_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3a2205ee_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1349a24a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d4275c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@657d1d9b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77dc74cf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7b2335ea_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@60cfbf2f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3b5bc7f8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3952de2e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4ea52573_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@58fdb158_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6a3ec25b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@38e01d1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@41312d17_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4960f858_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4fc1a608_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@50a7b242_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3ba5a927_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4577effb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@24950516_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3f566912_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@ce5ccb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1868af0c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1e5676a1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@482c6c08_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@439d1ccd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4d18b880_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1cb34d37_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@35956167_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@edc52ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ca21f6a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@30cea3b8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@72dd0545_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3385e4b5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a7f120d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@64e52226_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3642d1a2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2f597e54_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@51e8ab9d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@72b9d5e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7a4741c0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4bb7f6f8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@634fe21a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4aa4e91b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@30ad75d5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4911c113_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4080a163_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77494d4e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1bdef9f8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4385cd7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@64412115_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6f2eee8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3c61cfc8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@21768440_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4b355e7a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@65d604b5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1d52befe_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7cf526e5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@551c331c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@646f2bcc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6d01a5a8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d95b5ff_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27b779c7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1434a4fe_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5e7326d8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2fd42eaf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2a035f8e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@761ebb79_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2edf9f01_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@c5189a6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11b06564_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@f5f8ce8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@751af23d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@57380db3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@f3d75f1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@626de2e1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@65166b70_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1b007a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3f3b6415_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@444d9f3b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@58fe3b2b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@22c722fb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@143ea435_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5a42ad29_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@c5b8ec0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a4e16b4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@42ffb207_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@714e55e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@46a7eaba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@17b1cd6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@43ddb8ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@46813502_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@20ebdb6c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3b2bcf03_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@573cb596_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@67a1e45e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@e85625c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b0d7ccd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2f5cda36_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@51ba8691_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@782de323_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@570b95ae_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5b826b52_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@37cc7d57_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1fead495_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@395f4c4c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77419e7a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5b4eb32d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@50a26523_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2129e8aa_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4c1b9123_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2bd2e4a6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@441d0859_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7f39f4dd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@179c6e39_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1de9114f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@50d3b1e8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@129ac90_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a081ede_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@46ad3f41_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6a67c8c3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77c6b087_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6941d063_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@31d57680_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ad3812d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5053bd97_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4950b18d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@71973c4b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@f73ae96_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@aa60d05_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4b98b40c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@767f6dd3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3d62773e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4932ca24_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@499b78e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@570037c0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c5b2a33_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@72a04750_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5c95f5d6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13e93f4b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@26f6a801_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@69443224_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3df62b6f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@67368a6e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7cc83605_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1507eb2e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@135a41e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@64e63246_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4f49185c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5593e965_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@225ff805_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4beed390_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@106a0c22_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@384214bd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@593ef9fb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@37cdc023_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13a1d788_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@524f74f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4bf9a62b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@55a122c7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7c2fdaa9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@518b1cda_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@51e91952_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1278d0d9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@33a9e1f0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5761a78_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@57c6694d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6f6e2a4c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@651527ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@20634131_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4a5fc5ae_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1ea744d8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@41ac8c35_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@544fed3e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@352cd72_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@25a30a08_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3a049463_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@50f12b6f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@598f48b2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6449a017_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4fc6d831_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b83cae5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3ceb3464_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a761ed2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@25804f95_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@47f1862a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@551336b0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2943bdfb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4a3f2f83_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@52f9db4e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@66396587_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4382e037_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@41949965_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a8a1eeb_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5189684d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@76bfc522_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4c88cfbd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2cbbaeda_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77ee719d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d7b2699_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@73ba8e8b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1f047a95_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@22689605_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b1c0e75_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3c70f3ac_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3d414ec0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@30a4d75_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@52a783ab_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6706deea_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6124d7d8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@59e9e696_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@202e94c8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@b6ee7ad_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11bbdbd2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@53acccb5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1bcb5b05_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c1a5b1c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4fa63c3e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@64e4590_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@43599237_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@784e427e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@251afaad_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@326b33d4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2b2571dc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2fed8cc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@509a0566_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@193895f6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@725ff575_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6f25ab56_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1e921ec3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@ac8c699_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@53f24856_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1724f6e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@610a3da7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3b846fd8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@645d5f2e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@14d3680_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@75fea7b9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@49e97fec_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6cbcafe8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@e9f64d3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b46d36f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7ed1f96b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27f5c251_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@472752f8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@17bc87a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@31dc304_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@352d492d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6e8cf4c8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3f9ad2c5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@32f89c42_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3778bb78_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@510d9d71_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5634a7b8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@8cbb07a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2bd39894_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@49f0884e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@47766a99_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@72bfa014_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6ceae5a1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@f97815f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2ab1af41_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@736d5c8f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@28ad60d2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@280a47e1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3f6f7e0d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@73674571_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2bc75aea_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4648f64d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@44e851d7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3596d0fb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@25a1a065_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3a73112f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6ff5037d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3b679be2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@343f5854_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1f0e5159_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@672205c4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5eaf4a2f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4294b19b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4a77deab_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@48460505_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@186d05f2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77227d65_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@bf3434b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@70fe8b50_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6ea74e9c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@94baf8f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2c237466_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7477dd9e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@59c3564f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@230c6865_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@73dd3fa0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@38c0e7a6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@361aa0bf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@693cd002_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@90cf9bd_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@56759d72_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@76489f89_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@23cddfea_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@61951253_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2ef492f8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@11384e6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@43229f8c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@560889a6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7b9e8239_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77274317_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7fede95d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7adf648c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6f2d3a75_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6b8943f6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@46de7d7d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1064cd98_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@55fee084_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4f4a40b1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@246290e0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4c03aa24_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6a5175be_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@243298c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4d32cec8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@26e6b9dc_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@71f2c9c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@766d3322_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@53d9d8f3_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1bc31527_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@a7d1a87_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@554e8355_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@f387ef1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2d26d3c1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4a493133_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2ed57f64_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@33917459_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@256b8cbb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@ef978f7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@854b85c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@15a5cb4c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5e7bf60a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@75ba979_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2550dd2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5bb22db_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6a777a31_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@13fd8c0e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5ab5d13a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@a6d43c7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2de47456_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1fd6a6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@41e4b0cb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@70b02a59_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@366f8d4f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@76029335_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@70b9dabf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@49a7f7e5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5d4805a4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@11351177_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5bfb7bd1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@18e46c62_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2cc869b1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@33f4180_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3afeb273_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@9c5e63_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4a35a7c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@cd72db6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@28cdf041_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@eb4cd13_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5f536198_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@59f8726d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3a228f4c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ADPcontrol_1.0</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="cf8749a1"/>
+ <xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="2ed9224a"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="6203a1ee"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="2212c402"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cd165264"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="35656c35"/>
+ <xilinx:targetDRCs>
+ <xilinx:targetDRC xilinx:tool="ipi">
+ <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
+ </xilinx:targetDRC>
+ </xilinx:targetDRCs>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
new file mode 100755
index 0000000000000000000000000000000000000000..7b8967c18e34a77bb98084ede844e99853f3e47c
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0.v
@@ -0,0 +1,103 @@
+//-----------------------------------------------------------------------------
+// top-level soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+
+ module ADPcontrol_v1_0 #
+ (
+ // Users to add parameters here
+ parameter PROMPT_CHAR = "]"
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Ports of Axi Slave Bus Interface com_rx
+ input wire ahb_hclk,
+ input wire ahb_hresetn,
+
+ output wire com_rx_tready,
+ input wire [7 : 0] com_rx_tdata,
+ input wire com_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface com_tx
+ output wire com_tx_tvalid,
+ output wire [7 : 0] com_tx_tdata,
+ input wire com_tx_tready,
+
+ // Ports of Axi Slave Bus Interface stdio_rx
+ output wire stdio_rx_tready,
+ input wire [7 : 0] stdio_rx_tdata,
+ input wire stdio_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface stdio_tx
+ output wire stdio_tx_tvalid,
+ output wire [7 : 0] stdio_tx_tdata,
+ input wire stdio_tx_tready,
+
+ output wire [7 : 0] gpo8,
+ input wire [7 : 0] gpi8,
+
+ output wire [31:0] ahb_haddr ,
+ output wire [ 2:0] ahb_hburst ,
+ output wire ahb_hmastlock,
+ output wire [ 3:0] ahb_hprot ,
+ output wire [ 2:0] ahb_hsize ,
+ output wire [ 1:0] ahb_htrans ,
+ output wire [31:0] ahb_hwdata ,
+ output wire ahb_hwrite ,
+ input wire [31:0] ahb_hrdata ,
+ input wire ahb_hready ,
+ input wire ahb_hresp
+ );
+
+ // Add user logic here
+
+ADPmanager
+ #(.PROMPT_CHAR (PROMPT_CHAR))
+ ADPmanager(
+ .HCLK (ahb_hclk ),
+ .HRESETn (ahb_hresetn ),
+ .HADDR32_o (ahb_haddr ),
+ .HBURST3_o (ahb_hburst ),
+ .HMASTLOCK_o (ahb_hmastlock ),
+ .HPROT4_o (ahb_hprot ),
+ .HSIZE3_o (ahb_hsize ),
+ .HTRANS2_o (ahb_htrans ),
+ .HWDATA32_o (ahb_hwdata ),
+ .HWRITE_o (ahb_hwrite ),
+ .HRDATA32_i (ahb_hrdata ),
+ .HREADY_i (ahb_hready ),
+ .HRESP_i (ahb_hresp ),
+ .GPO8_o (gpo8 ),
+ .GPI8_i (gpi8 ),
+ .COMRX_TREADY_o(com_rx_tready),
+ .COMRX_TDATA_i(com_rx_tdata),
+ .COMRX_TVALID_i(com_rx_tvalid),
+ .STDRX_TREADY_o(stdio_rx_tready),
+ .STDRX_TDATA_i(stdio_rx_tdata),
+ .STDRX_TVALID_i(stdio_rx_tvalid),
+ .COMTX_TVALID_o(com_tx_tvalid),
+ .COMTX_TDATA_o(com_tx_tdata),
+ .COMTX_TREADY_i(com_tx_tready),
+ .STDTX_TVALID_o(stdio_tx_tvalid),
+ .STDTX_TDATA_o(stdio_tx_tdata),
+ .STDTX_TREADY_i(stdio_tx_tready)
+
+ );
+
+
+endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
new file mode 100755
index 0000000000000000000000000000000000000000..0e980d36757f551bd13414b0bf8f135a4e6bcafc
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_rx.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_com_rx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
new file mode 100755
index 0000000000000000000000000000000000000000..ba5f03594fc0075bdc58c0535948374580237a28
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_com_tx.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_com_tx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
new file mode 100755
index 0000000000000000000000000000000000000000..30f30e3895ada561f258535ea88f9b012142f738
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_rx.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_stdio_rx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
new file mode 100755
index 0000000000000000000000000000000000000000..8f4af08975c515e65431d6d12dfe5484ac0cac69
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/hdl/ADPcontrol_v1_0_stdio_tx.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ADPcontrol_v1_0_stdio_tx #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..3abb2fcb7d874d62c253813441c291e06284c7ab
Binary files /dev/null and b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/soclabs.org_user_ADPcontrol_1.0.zip differ
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
new file mode 100755
index 0000000000000000000000000000000000000000..07c4c8aeabd268a31f2de71e26a8d0f0c2038df9
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/src/ADPcontrol_v1_0.v
@@ -0,0 +1,102 @@
+//-----------------------------------------------------------------------------
+// top-level soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2021-2, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+ module ADPcontrol_v1_0 #
+ (
+ // Users to add parameters here
+ parameter PROMPT_CHAR = "]"
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Ports of Axi Slave Bus Interface com_rx
+ input wire ahb_hclk,
+ input wire ahb_hresetn,
+
+ output wire com_rx_tready,
+ input wire [7 : 0] com_rx_tdata,
+ input wire com_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface com_tx
+ output wire com_tx_tvalid,
+ output wire [7 : 0] com_tx_tdata,
+ input wire com_tx_tready,
+
+ // Ports of Axi Slave Bus Interface stdio_rx
+ output wire stdio_rx_tready,
+ input wire [7 : 0] stdio_rx_tdata,
+ input wire stdio_rx_tvalid,
+
+ // Ports of Axi Master Bus Interface stdio_tx
+ output wire stdio_tx_tvalid,
+ output wire [7 : 0] stdio_tx_tdata,
+ input wire stdio_tx_tready,
+
+ output wire [7 : 0] gpo8,
+ input wire [7 : 0] gpi8,
+
+ output wire [31:0] ahb_haddr ,
+ output wire [ 2:0] ahb_hburst ,
+ output wire ahb_hmastlock,
+ output wire [ 3:0] ahb_hprot ,
+ output wire [ 2:0] ahb_hsize ,
+ output wire [ 1:0] ahb_htrans ,
+ output wire [31:0] ahb_hwdata ,
+ output wire ahb_hwrite ,
+ input wire [31:0] ahb_hrdata ,
+ input wire ahb_hready ,
+ input wire ahb_hresp
+ );
+
+ // Add user logic here
+
+ADPmanager
+ #(.PROMPT_CHAR (PROMPT_CHAR))
+ ADPmanager(
+ .HCLK (ahb_hclk ),
+ .HRESETn (ahb_hresetn ),
+ .HADDR32_o (ahb_haddr ),
+ .HBURST3_o (ahb_hburst ),
+ .HMASTLOCK_o (ahb_hmastlock ),
+ .HPROT4_o (ahb_hprot ),
+ .HSIZE3_o (ahb_hsize ),
+ .HTRANS2_o (ahb_htrans ),
+ .HWDATA32_o (ahb_hwdata ),
+ .HWRITE_o (ahb_hwrite ),
+ .HRDATA32_i (ahb_hrdata ),
+ .HREADY_i (ahb_hready ),
+ .HRESP_i (ahb_hresp ),
+ .GPO8_o (gpo8 ),
+ .GPI8_i (gpi8 ),
+ .COMRX_TREADY_o(com_rx_tready),
+ .COMRX_TDATA_i(com_rx_tdata),
+ .COMRX_TVALID_i(com_rx_tvalid),
+ .STDRX_TREADY_o(stdio_rx_tready),
+ .STDRX_TDATA_i(stdio_rx_tdata),
+ .STDRX_TVALID_i(stdio_rx_tvalid),
+ .COMTX_TVALID_o(com_tx_tvalid),
+ .COMTX_TDATA_o(com_tx_tdata),
+ .COMTX_TREADY_i(com_tx_tready),
+ .STDTX_TVALID_o(stdio_tx_tvalid),
+ .STDTX_TDATA_o(stdio_tx_tdata),
+ .STDTX_TREADY_i(stdio_tx_tready)
+
+ );
+
+
+endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/src/ADPmanager.v b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/src/ADPmanager.v
new file mode 100755
index 0000000000000000000000000000000000000000..5c6ec0be32e8ca76a5537aa727ae65a67208560c
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/src/ADPmanager.v
@@ -0,0 +1,800 @@
+//-----------------------------------------------------------------------------
+// soclabs ASCII Debug Protocol controller
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2021-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//`define ADPBASIC 1
+
+module ADPmanager // AHB initiator interface
+ #(parameter PROMPT_CHAR = "]"
+ )
+ ( input wire HCLK,
+ input wire HRESETn,
+ output wire [31:0] HADDR32_o,
+ output wire [ 2:0] HBURST3_o,
+ output wire HMASTLOCK_o,
+ output wire [ 3:0] HPROT4_o,
+ output wire [ 2:0] HSIZE3_o,
+ output wire [ 1:0] HTRANS2_o,
+ output wire [31:0] HWDATA32_o,
+ output wire HWRITE_o,
+ input wire [31:0] HRDATA32_i,
+ input wire HREADY_i,
+ input wire HRESP_i,
+// COMIO interface
+ output wire [ 7:0] GPO8_o,
+ input wire [ 7:0] GPI8_i,
+// input wire COM_RXE_i,
+ input wire [ 7:0] COMRX_TDATA_i,
+ input wire COMRX_TVALID_i,
+ output wire COMRX_TREADY_o,
+// input wire COM_TXF_i,
+ output wire [ 7:0] COMTX_TDATA_o,
+ output wire COMTX_TVALID_o,
+ input wire COMTX_TREADY_i,
+// STDIO interface
+// input wire STDOUT_RXE_i,
+ input wire [ 7:0] STDRX_TDATA_i,
+ input wire STDRX_TVALID_i,
+ output wire STDRX_TREADY_o,
+// input wire STDIN_TXF_i
+ output wire [ 7:0] STDTX_TDATA_o,
+ output wire STDTX_TVALID_o,
+ input wire STDTX_TREADY_i
+);
+
+wire COM_RXE_i = !COMRX_TVALID_i;
+wire COM_TXF_i = !COMTX_TREADY_i;
+
+//wire adp_rx_req = COMRX_TVALID_i & COMRX_TREADY_o;
+//wire std_rx_req = STDRX_TVALID_i & STDRX_TREADY_o;
+
+
+wire STD_TXF_i = !STDTX_TREADY_i;
+wire STD_RXE_i = !STDRX_TVALID_i;
+
+`ifdef ADPBASIC
+ localparam BANNERHEX = 32'h50c1ab01;
+`else
+ localparam BANNERHEX = 32'h50c1ab03;
+`endif
+
+localparam CMD_bad = 4'b0000;
+localparam CMD_A = 4'b0001; // set Address
+localparam CMD_C = 4'b0010; // Control
+localparam CMD_R = 4'b0011; // Read word, addr++
+localparam CMD_S = 4'b0100; // Status/STDIN
+localparam CMD_W = 4'b0100; // Write word, addr++
+localparam CMD_X = 4'b0101; // eXit
+`ifndef ADPBASIC
+localparam CMD_F = 4'b1000; // Fill (wordocunt) from addr++
+localparam CMD_M = 4'b1001; // set read Mask
+localparam CMD_P = 4'b1010; // Poll hardware (count)
+localparam CMD_U = 4'b1011; // (Binary) Upload (wordocunt) from addr++
+localparam CMD_V = 4'b1100; // match Value
+`endif
+
+
+function FNvalid_adp_entry; // Escape char
+input [7:0] char8;
+ FNvalid_adp_entry = (char8[7:0] == 8'h1b);
+endfunction
+
+function [3:0] FNvalid_cmd;
+input [7:0] char8;
+case (char8[7:0])
+"A": FNvalid_cmd = CMD_A;
+"a": FNvalid_cmd = CMD_A;
+"C": FNvalid_cmd = CMD_C;
+"c": FNvalid_cmd = CMD_C;
+"R": FNvalid_cmd = CMD_R;
+"r": FNvalid_cmd = CMD_R;
+"S": FNvalid_cmd = CMD_S;
+"s": FNvalid_cmd = CMD_S;
+"W": FNvalid_cmd = CMD_W;
+"w": FNvalid_cmd = CMD_W;
+"X": FNvalid_cmd = CMD_X;
+"x": FNvalid_cmd = CMD_X;
+`ifndef ADPBASIC
+"F": FNvalid_cmd = CMD_F;
+"f": FNvalid_cmd = CMD_F;
+"M": FNvalid_cmd = CMD_M;
+"m": FNvalid_cmd = CMD_M;
+"P": FNvalid_cmd = CMD_P;
+"p": FNvalid_cmd = CMD_P;
+"U": FNvalid_cmd = CMD_U;
+"u": FNvalid_cmd = CMD_U;
+"V": FNvalid_cmd = CMD_V;
+"v": FNvalid_cmd = CMD_V;
+`endif
+default:
+ FNvalid_cmd = 0;
+endcase
+endfunction
+
+function FNvalid_space; // space or tab char
+input [7:0] char8;
+ FNvalid_space = ((char8[7:0] == 8'h20) || (char8[7:0] == 8'h09));
+endfunction
+
+function FNnull; // space or tab char
+input [7:0] char8;
+ FNnull = (char8[7:0] == 8'h00);
+endfunction
+
+function FNexit; // EOF
+input [7:0] char8;
+ FNexit = ((char8[7:0] == 8'h04) || (char8[7:0] == 8'h00));
+endfunction
+
+function FNvalid_EOL; // CR or LF
+input [7:0] char8;
+ FNvalid_EOL = ((char8[7:0] == 8'h0a) || (char8[7:0] == 8'h0d));
+endfunction
+
+function FNuppercase;
+input [7:0] char8;
+ FNuppercase = (char8[6]) ? (char8 & 8'h5f) : (char8);
+endfunction
+
+function [63:0] FNBuild_param64_hexdigit;
+input [63:0] param64;
+input [7:0] char8;
+case (char8[7:0])
+"\t":FNBuild_param64_hexdigit = 64'b0; // tab starts new (zeroed) param64
+" ": FNBuild_param64_hexdigit = 64'b0; // space starts new (zeroed) param64
+"x": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64
+"X": FNBuild_param64_hexdigit = 64'b0; // hex prefix starts new (zeroed) param64
+"0": FNBuild_param64_hexdigit = {param64[59:0],4'b0000};
+"1": FNBuild_param64_hexdigit = {param64[59:0],4'b0001};
+"2": FNBuild_param64_hexdigit = {param64[59:0],4'b0010};
+"3": FNBuild_param64_hexdigit = {param64[59:0],4'b0011};
+"4": FNBuild_param64_hexdigit = {param64[59:0],4'b0100};
+"5": FNBuild_param64_hexdigit = {param64[59:0],4'b0101};
+"6": FNBuild_param64_hexdigit = {param64[59:0],4'b0110};
+"7": FNBuild_param64_hexdigit = {param64[59:0],4'b0111};
+"8": FNBuild_param64_hexdigit = {param64[59:0],4'b1000};
+"9": FNBuild_param64_hexdigit = {param64[59:0],4'b1001};
+"A": FNBuild_param64_hexdigit = {param64[59:0],4'b1010};
+"B": FNBuild_param64_hexdigit = {param64[59:0],4'b1011};
+"C": FNBuild_param64_hexdigit = {param64[59:0],4'b1100};
+"D": FNBuild_param64_hexdigit = {param64[59:0],4'b1101};
+"E": FNBuild_param64_hexdigit = {param64[59:0],4'b1110};
+"F": FNBuild_param64_hexdigit = {param64[59:0],4'b1111};
+"a": FNBuild_param64_hexdigit = {param64[59:0],4'b1010};
+"b": FNBuild_param64_hexdigit = {param64[59:0],4'b1011};
+"c": FNBuild_param64_hexdigit = {param64[59:0],4'b1100};
+"d": FNBuild_param64_hexdigit = {param64[59:0],4'b1101};
+"e": FNBuild_param64_hexdigit = {param64[59:0],4'b1110};
+"f": FNBuild_param64_hexdigit = {param64[59:0],4'b1111};
+default: FNBuild_param64_hexdigit = param64; // EOL etc returns param64 unchanged
+endcase
+endfunction
+
+function [63:0] FNBuild_param64_byte;
+input [63:0] param64;
+input [7:0] byte;
+ FNBuild_param64_byte = {byte[7:0], param64[63:08]};
+endfunction
+
+function [31:0] FNBuild_param32_hexdigit;
+input [31:0] param32;
+input [7:0] char8;
+case (char8[7:0])
+"\t":FNBuild_param32_hexdigit = 32'b0; // tab starts new (zeroed) param32
+" ": FNBuild_param32_hexdigit = 32'b0; // space starts new (zeroed) param32
+"x": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32
+"X": FNBuild_param32_hexdigit = 32'b0; // hex prefix starts new (zeroed) param32
+"0": FNBuild_param32_hexdigit = {param32[27:0],4'b0000};
+"1": FNBuild_param32_hexdigit = {param32[27:0],4'b0001};
+"2": FNBuild_param32_hexdigit = {param32[27:0],4'b0010};
+"3": FNBuild_param32_hexdigit = {param32[27:0],4'b0011};
+"4": FNBuild_param32_hexdigit = {param32[27:0],4'b0100};
+"5": FNBuild_param32_hexdigit = {param32[27:0],4'b0101};
+"6": FNBuild_param32_hexdigit = {param32[27:0],4'b0110};
+"7": FNBuild_param32_hexdigit = {param32[27:0],4'b0111};
+"8": FNBuild_param32_hexdigit = {param32[27:0],4'b1000};
+"9": FNBuild_param32_hexdigit = {param32[27:0],4'b1001};
+"A": FNBuild_param32_hexdigit = {param32[27:0],4'b1010};
+"B": FNBuild_param32_hexdigit = {param32[27:0],4'b1011};
+"C": FNBuild_param32_hexdigit = {param32[27:0],4'b1100};
+"D": FNBuild_param32_hexdigit = {param32[27:0],4'b1101};
+"E": FNBuild_param32_hexdigit = {param32[27:0],4'b1110};
+"F": FNBuild_param32_hexdigit = {param32[27:0],4'b1111};
+"a": FNBuild_param32_hexdigit = {param32[27:0],4'b1010};
+"b": FNBuild_param32_hexdigit = {param32[27:0],4'b1011};
+"c": FNBuild_param32_hexdigit = {param32[27:0],4'b1100};
+"d": FNBuild_param32_hexdigit = {param32[27:0],4'b1101};
+"e": FNBuild_param32_hexdigit = {param32[27:0],4'b1110};
+"f": FNBuild_param32_hexdigit = {param32[27:0],4'b1111};
+default: FNBuild_param32_hexdigit = param32; // EOL etc returns param32 unchanged
+endcase
+endfunction
+
+function [31:0] FNBuild_param32_byte;
+input [31:0] param32;
+input [7:0] byte;
+ FNBuild_param32_byte = {byte[7:0], param32[31:08]};
+endfunction
+
+
+
+function [7:0] FNmap_hex_digit;
+input [3:0] nibble;
+case (nibble[3:0])
+4'b0000: FNmap_hex_digit = "0";
+4'b0001: FNmap_hex_digit = "1";
+4'b0010: FNmap_hex_digit = "2";
+4'b0011: FNmap_hex_digit = "3";
+4'b0100: FNmap_hex_digit = "4";
+4'b0101: FNmap_hex_digit = "5";
+4'b0110: FNmap_hex_digit = "6";
+4'b0111: FNmap_hex_digit = "7";
+4'b1000: FNmap_hex_digit = "8";
+4'b1001: FNmap_hex_digit = "9";
+4'b1010: FNmap_hex_digit = "a";
+4'b1011: FNmap_hex_digit = "b";
+4'b1100: FNmap_hex_digit = "c";
+4'b1101: FNmap_hex_digit = "d";
+4'b1110: FNmap_hex_digit = "e";
+4'b1111: FNmap_hex_digit = "f";
+default: FNmap_hex_digit = "0";
+endcase
+endfunction
+
+
+// as per Vivado synthesis mapping
+`ifdef ADPFSMDESIGN
+localparam ADP_WRITEHEX = 6'b000000 ;
+localparam ADP_WRITEHEXS = 6'b000001 ;
+localparam ADP_WRITEHEX9 = 6'b000010 ;
+localparam ADP_WRITEHEX8 = 6'b000011 ;
+localparam ADP_WRITEHEX7 = 6'b000100 ;
+localparam ADP_WRITEHEX6 = 6'b000101 ;
+localparam ADP_WRITEHEX5 = 6'b000110 ;
+localparam ADP_WRITEHEX4 = 6'b000111 ;
+localparam ADP_WRITEHEX3 = 6'b001000 ;
+localparam ADP_WRITEHEX2 = 6'b001001 ;
+localparam ADP_WRITEHEX1 = 6'b001010 ;
+localparam ADP_WRITEHEX0 = 6'b001011 ;
+localparam ADP_LINEACK = 6'b001100 ;
+localparam ADP_LINEACK2 = 6'b001101 ;
+localparam ADP_PROMPT = 6'b001110 ;
+localparam ADP_IOCHK = 6'b001111 ;
+localparam ADP_STDOUT = 6'b010000 ;
+localparam ADP_STDOUT1 = 6'b010001 ;
+localparam ADP_STDOUT2 = 6'b010010 ;
+localparam ADP_STDOUT3 = 6'b010011 ;
+localparam ADP_RXCMD = 6'b010100 ;
+localparam ADP_RXPARAM = 6'b010101 ;
+localparam ADP_ACTION = 6'b010110 ;
+localparam ADP_SYSCTL = 6'b010111 ;
+localparam ADP_READ = 6'b011000 ;
+localparam ADP_SYSCHK = 6'b011001 ;
+localparam ADP_STDIN = 6'b011010 ;
+localparam ADP_WRITE = 6'b011011 ;
+localparam ADP_EXIT = 6'b011100 ;
+localparam STD_IOCHK = 6'b011101 ;
+localparam STD_RXD1 = 6'b011110 ;
+localparam STD_RXD2 = 6'b011111 ;
+localparam STD_TXD1 = 6'b100000 ;
+localparam STD_TXD2 = 6'b100001 ;
+localparam ADP_UCTRL = 6'b100010 ;
+localparam ADP_UREADB0 = 6'b100011 ;
+localparam ADP_UREADB1 = 6'b100100 ;
+localparam ADP_UREADB2 = 6'b100101 ;
+localparam ADP_UREADB3 = 6'b100110 ;
+localparam ADP_UWRITE = 6'b100111 ;
+localparam ADP_POLL = 6'b101000 ;
+localparam ADP_POLL1 = 6'b101001 ;
+localparam ADP_POLL2 = 6'b101010 ;
+localparam ADP_FCTRL = 6'b101011 ;
+localparam ADP_FWRITE = 6'b101100 ;
+localparam ADP_ECHOCMD = 6'b101101 ;
+localparam ADP_ECHOBUS = 6'b101110 ;
+localparam ADP_UNKNOWN = 6'b101111 ;
+reg [5:0] adp_state ;
+`else
+// one-hot encoded explicitly
+localparam ADP_WRITEHEX = 48'b000000000000000000000000000000000000000000000001 ; // = 6'b000000
+localparam ADP_WRITEHEXS = 48'b000000000000000000000000000000000000000000000010 ; // = 6'b000001
+localparam ADP_WRITEHEX9 = 48'b000000000000000000000000000000000000000000000100 ; // = 6'b000010
+localparam ADP_WRITEHEX8 = 48'b000000000000000000000000000000000000000000001000 ; // = 6'b000011
+localparam ADP_WRITEHEX7 = 48'b000000000000000000000000000000000000000000010000 ; // = 6'b000100
+localparam ADP_WRITEHEX6 = 48'b000000000000000000000000000000000000000000100000 ; // = 6'b000101
+localparam ADP_WRITEHEX5 = 48'b000000000000000000000000000000000000000001000000 ; // = 6'b000110
+localparam ADP_WRITEHEX4 = 48'b000000000000000000000000000000000000000010000000 ; // = 6'b000111
+localparam ADP_WRITEHEX3 = 48'b000000000000000000000000000000000000000100000000 ; // = 6'b001000
+localparam ADP_WRITEHEX2 = 48'b000000000000000000000000000000000000001000000000 ; // = 6'b001001
+localparam ADP_WRITEHEX1 = 48'b000000000000000000000000000000000000010000000000 ; // = 6'b001010
+localparam ADP_WRITEHEX0 = 48'b000000000000000000000000000000000000100000000000 ; // = 6'b001011
+localparam ADP_LINEACK = 48'b000000000000000000000000000000000001000000000000 ; // = 6'b001100
+localparam ADP_LINEACK2 = 48'b000000000000000000000000000000000010000000000000 ; // = 6'b001101
+localparam ADP_PROMPT = 48'b000000000000000000000000000000000100000000000000 ; // = 6'b001110
+localparam ADP_IOCHK = 48'b000000000000000000000000000000001000000000000000 ; // = 6'b001111
+localparam ADP_STDOUT = 48'b000000000000000000000000000000010000000000000000 ; // = 6'b010000
+localparam ADP_STDOUT1 = 48'b000000000000000000000000000000100000000000000000 ; // = 6'b010001
+localparam ADP_STDOUT2 = 48'b000000000000000000000000000001000000000000000000 ; // = 6'b010010
+localparam ADP_STDOUT3 = 48'b000000000000000000000000000010000000000000000000 ; // = 6'b010011
+localparam ADP_RXCMD = 48'b000000000000000000000000000100000000000000000000 ; // = 6'b010100
+localparam ADP_RXPARAM = 48'b000000000000000000000000001000000000000000000000 ; // = 6'b010101
+localparam ADP_ACTION = 48'b000000000000000000000000010000000000000000000000 ; // = 6'b010110
+localparam ADP_SYSCTL = 48'b000000000000000000000000100000000000000000000000 ; // = 6'b010111
+localparam ADP_READ = 48'b000000000000000000000001000000000000000000000000 ; // = 6'b011000
+localparam ADP_SYSCHK = 48'b000000000000000000000010000000000000000000000000 ; // = 6'b011001
+localparam ADP_STDIN = 48'b000000000000000000000100000000000000000000000000 ; // = 6'b011010
+localparam ADP_WRITE = 48'b000000000000000000001000000000000000000000000000 ; // = 6'b011011
+localparam ADP_EXIT = 48'b000000000000000000010000000000000000000000000000 ; // = 6'b011100
+localparam STD_IOCHK = 48'b000000000000000000100000000000000000000000000000 ; // = 6'b011101
+localparam STD_RXD1 = 48'b000000000000000001000000000000000000000000000000 ; // = 6'b011110
+localparam STD_RXD2 = 48'b000000000000000010000000000000000000000000000000 ; // = 6'b011111
+localparam STD_TXD1 = 48'b000000000000000100000000000000000000000000000000 ; // = 6'b100000
+localparam STD_TXD2 = 48'b000000000000001000000000000000000000000000000000 ; // = 6'b100001
+localparam ADP_UCTRL = 48'b000000000000010000000000000000000000000000000000 ; // = 6'b100010
+localparam ADP_UREADB0 = 48'b000000000000100000000000000000000000000000000000 ; // = 6'b100011
+localparam ADP_UREADB1 = 48'b000000000001000000000000000000000000000000000000 ; // = 6'b100100
+localparam ADP_UREADB2 = 48'b000000000010000000000000000000000000000000000000 ; // = 6'b100101
+localparam ADP_UREADB3 = 48'b000000000100000000000000000000000000000000000000 ; // = 6'b100110
+localparam ADP_UWRITE = 48'b000000001000000000000000000000000000000000000000 ; // = 6'b100111
+localparam ADP_POLL = 48'b000000010000000000000000000000000000000000000000 ; // = 6'b101000
+localparam ADP_POLL1 = 48'b000000100000000000000000000000000000000000000000 ; // = 6'b101001
+localparam ADP_POLL2 = 48'b000001000000000000000000000000000000000000000000 ; // = 6'b101010
+localparam ADP_FCTRL = 48'b000010000000000000000000000000000000000000000000 ; // = 6'b101011
+localparam ADP_FWRITE = 48'b000100000000000000000000000000000000000000000000 ; // = 6'b101100
+localparam ADP_ECHOCMD = 48'b001000000000000000000000000000000000000000000000 ; // = 6'b101101
+localparam ADP_ECHOBUS = 48'b010000000000000000000000000000000000000000000000 ; // = 6'b101110
+localparam ADP_UNKNOWN = 48'b100000000000000000000000000000000000000000000000 ; // = 6'b101111
+reg [47:0] adp_state ;
+`endif
+
+reg [31:0] adp_bus_data;
+reg banner ;
+reg com_tx_req ;
+reg [7:0] com_tx_byte ;
+reg com_rx_ack ;
+reg std_tx_req ;
+reg [ 7:0] std_tx_byte;
+reg std_rx_ack ;
+reg adp_bus_req ;
+reg adp_bus_write ;
+reg adp_bus_err ;
+reg [7:0] adp_cmd ;
+reg [32:0] adp_param ;
+reg [31:0] adp_addr ;
+reg adp_addr_inc;
+reg [31:0] adp_sys ;
+
+assign GPO8_o = adp_sys[7:0];
+
+// ADP RX stream
+wire com_rx_req = COMRX_TVALID_i;
+wire [ 7:0] com_rx_byte = COMRX_TDATA_i;
+assign COMRX_TREADY_o = com_rx_ack;
+// ADP TX stream
+wire com_tx_ack = COMTX_TREADY_i;
+assign COMTX_TDATA_o = com_tx_byte;
+assign COMTX_TVALID_o = com_tx_req;
+// STD RX stream (from STDOUT)
+wire std_rx_req = STDRX_TVALID_i;
+wire [ 7:0] std_rx_byte = STDRX_TDATA_i;
+assign STDRX_TREADY_o = std_rx_ack;
+// STD TX stream (to STDIN)
+wire std_tx_ack = STDTX_TREADY_i;
+assign STDTX_TDATA_o = std_tx_byte;
+assign STDTX_TVALID_o = std_tx_req;
+
+//AMBA AHB master as "stream" interface
+reg ahb_dphase;
+wire ahb_aphase = adp_bus_req & !ahb_dphase;
+wire adp_bus_ack = ahb_dphase & HREADY_i;
+// control pipe
+always @(posedge HCLK or negedge HRESETn)
+ if(!HRESETn)
+ ahb_dphase <= 0;
+ else if (HREADY_i)
+ ahb_dphase <= (ahb_aphase);
+
+assign HADDR32_o = adp_addr;
+assign HBURST3_o = 3'b001; // "INCR" burst signalled whenever transfer;
+assign HMASTLOCK_o = 1'b0;
+assign HPROT4_o[3:0] = {1'b0, 1'b0, 1'b1, 1'b1};
+assign HSIZE3_o[2:0] = {1'b0, 2'b10};
+assign HTRANS2_o = {ahb_aphase,1'b0}; // non-seq
+assign HWDATA32_o = adp_bus_data;
+assign HWRITE_o = adp_bus_write;
+
+
+`ifndef ADPBASIC
+reg [31:0] adp_val;
+reg [31:0] adp_mask;
+reg [31:0] adp_poll;
+reg [31:0] adp_count;
+reg adp_count_dec ;
+wire adp_delay_done;
+wire poll2_loop_next;
+`endif
+
+// ADP_control flags in the 'C' control field
+wire adp_disable;
+wire adp_stdin_wait;
+
+// commnon interface handshake terms
+wire com_rx_done = COMRX_TVALID_i & COMRX_TREADY_o;
+wire com_tx_done = COMTX_TVALID_o & COMTX_TREADY_i;
+wire std_rx_done = STDRX_TVALID_i & STDRX_TREADY_o;
+wire std_tx_done = STDTX_TVALID_o & STDTX_TREADY_i;
+wire adp_bus_done = (adp_bus_req & adp_bus_ack);
+
+// common task to set up for next state
+task ADP_LINEACK_next; // prepare newline TX (and cancel any startup banner)
+// begin com_tx_req <= 1; com_tx_byte <= 8'h0A; banner <= 0; adp_state <= ADP_LINEACK; end
+ begin com_tx_req <= 1; com_tx_byte <= 8'h0A; adp_state <= ADP_LINEACK; end
+endtask
+task ADP_PROMPT_next; // prepare prompt TX
+ begin com_tx_req <= 1; com_tx_byte <= PROMPT_CHAR; adp_state <= ADP_PROMPT; end
+endtask
+task ADP_BUSWRITEINC_next; // prepare bus write and addr++ on completion
+ begin adp_bus_req <=1; adp_bus_write <=1; adp_addr_inc <=1; end
+endtask
+task ADP_BUSREADINC_next; // prepare bus read and addr++ on completion
+ begin adp_bus_req <=1; adp_bus_write <=0; adp_addr_inc <=1; end
+endtask
+
+task ADP_hexdigit_next; // output nibble
+input [3:0] nibble;
+ begin com_tx_req <= 1; com_tx_byte <= FNmap_hex_digit(nibble[3:0]); end
+endtask
+task ADP_txchar_next; // output char
+input [7:0] byte;
+ begin com_tx_req<= 1; com_tx_byte <= byte; end
+endtask
+
+task com_rx_nxt; com_rx_ack <=1; endtask
+
+function FNcount_down_zero_next; // param about to be zero
+input [31:0] counter;
+ FNcount_down_zero_next = !(|counter[31:1]);
+endfunction
+
+always @(posedge HCLK or negedge HRESETn)
+ if(!HRESETn) begin
+ adp_state <= ADP_WRITEHEX ;
+ adp_bus_data <= BANNERHEX;
+ banner <= 1; // start-up HEX message
+ com_tx_req <= 0; // default no TX req
+ com_rx_ack <= 0; // default no RX ack
+ std_tx_req <= 0; // default no TX req
+ std_rx_ack <= 0; // default no RX ack
+ adp_bus_req <= 0; // default no bus transaction
+ adp_bus_err <= 0; // default no bus error
+ adp_cmd <= 0;
+ adp_param <= 0;
+ adp_addr <= 0;
+ adp_addr_inc <= 0;
+ adp_bus_write<= 0;
+`ifndef ADPBASIC
+ adp_count <= 0;
+ adp_count_dec<= 0;
+ adp_val <= 0;
+ adp_mask <= 0;
+ adp_sys <= 0;
+`endif
+ end else begin // default states
+ adp_state <= adp_state; // default to hold current state
+ com_tx_req <= 0; // default no TX req
+ com_rx_ack <= 0; // default no RX ack
+ std_tx_req <= 0; // default no TX req
+ std_rx_ack <= 0; // default no RX ack
+ adp_bus_req <= 0; // default no bus transaction
+ adp_addr <= (adp_addr_inc & adp_bus_done) ? adp_addr + 4 : adp_addr; // address++
+ adp_addr_inc <= 0;
+`ifndef ADPBASIC
+ adp_count <= (adp_count_dec & adp_bus_done & |adp_count) ? adp_count - 1 : adp_count; // param--
+ adp_count_dec<= 0;
+`endif
+ case (adp_state)
+// >>>>>>>>>>>>>>>> STDIO BYPASS >>>>>>>>>>>>>>>>>>>>>>
+ STD_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
+ if (com_rx_req) begin com_rx_ack <= 1; adp_state <= STD_RXD1; end // input char pending for STDIN
+// else if (com_tx_ack & std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending and not busy
+ else if (std_rx_req) begin std_rx_ack <= 1; adp_state <= STD_TXD1; end // STDOUT char pending
+ STD_TXD1: // get STD out char
+ if (std_rx_done)
+ begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= STD_TXD2; end
+ else std_rx_ack <= 1; // extend
+ STD_TXD2: // output char to ADP channel
+ if (com_tx_done) begin adp_state <= STD_IOCHK; end
+ else com_tx_req <= 1; // extend
+ STD_RXD1: // read rx char and check for ADP entry else STDIN **
+ if (com_rx_done) begin
+ if (FNvalid_adp_entry(com_rx_byte))
+ begin ADP_txchar_next(8'h0A); adp_state <= ADP_LINEACK; end // ADP prompt
+ else if (std_tx_ack)
+ begin std_tx_byte <= com_rx_byte; std_tx_req <= 1; adp_state <= STD_RXD2; end
+ else adp_state <= STD_IOCHK; // otherwise discard STDIN char and process OP data if blocked
+ end else com_rx_ack <= 1; // extend
+ STD_RXD2: // get STD in char
+ if (std_tx_done) begin adp_state <= STD_IOCHK; end
+ else std_tx_req <= 1; // extend
+
+// >>>>>>>>>>>>>>>> ADP Monitor >>>>>>>>>>>>>>>>>>>>>>
+ ADP_PROMPT: // transition after reset deassertion
+ if (com_tx_done) begin adp_state <= ADP_IOCHK; end
+ else com_tx_req <= 1; // extend
+
+ ADP_IOCHK: // check for commsrx or STDOUT and not busy service, else loop back
+ if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+ else if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end
+
+// if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end
+// else if (com_tx_ack & std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+//// else if (std_rx_req) begin com_tx_byte <= "<"; com_tx_req <= 1; adp_state <= ADP_STDOUT; end
+
+// >>>>>>>>>>>>>>>> ADP <STDOUT> >>>>>>>>>>>>>>>>>>>>>>
+ ADP_STDOUT: // output "<"
+ if (com_tx_done) begin std_rx_ack <= 1; adp_state <= ADP_STDOUT1; end
+ else com_tx_req <= 1; // extend stream request if not ready
+ ADP_STDOUT1: // get STD out char
+ if (std_rx_done) begin com_tx_byte <= std_rx_byte; com_tx_req <= 1; adp_state <= ADP_STDOUT2; end
+ else std_rx_ack <= 1; // else extend
+ ADP_STDOUT2: // output char
+ if (com_tx_done) begin com_tx_byte <= ">"; com_tx_req <= 1; adp_state <= ADP_STDOUT3; end
+ else com_tx_req <= 1; // else extend
+ ADP_STDOUT3: // output ">"
+ if (com_tx_done) begin if (com_rx_req) begin com_rx_ack <= 1; adp_state <= ADP_RXCMD; end else adp_state <= ADP_IOCHK; end
+ else com_tx_req <= 1; // else extend
+
+// >>>>>>>>>>>>>>>> ADP COMMAND PARSING >>>>>>>>>>>>>>>>>>>>>>
+ ADP_RXCMD: // read and save ADP command
+ if (com_rx_done) begin
+ if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // immediate exit
+ else if (FNvalid_space(com_rx_byte)) com_rx_ack <= 1; // retry for a command
+ else if (FNvalid_EOL(com_rx_byte)) begin adp_cmd <= "?"; adp_state <= ADP_ACTION; end // no command, skip param
+ else begin adp_cmd <= com_rx_byte; adp_param <= 33'h1_00000000; com_rx_ack <= 1; adp_state <= ADP_RXPARAM; end // get optional parameter
+ end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_RXPARAM: // read and build hex parameter
+ if (com_rx_done) begin // RX byte
+ if (FNexit(com_rx_byte)) adp_state <= STD_IOCHK; // exit
+ else if (FNvalid_EOL(com_rx_byte))
+`ifndef ADPBASIC
+ begin adp_count <= adp_param[31:0]; adp_state <= ADP_ACTION; end // parameter complete on EOL
+`else
+ begin adp_state <= ADP_ACTION; end // parameter complete on EOL
+`endif
+ else
+ begin adp_param <= {1'b0,FNBuild_param32_hexdigit(adp_param[31:0], com_rx_byte)}; com_rx_ack <= 1; end // build parameter
+ end
+ else com_rx_ack <= 1;
+
+ ADP_ACTION: // parse command and action with parameter
+ if (FNexit(com_rx_byte))
+ adp_state <= STD_IOCHK;
+ else if (FNvalid_cmd(adp_cmd) == CMD_A)
+ begin if (adp_param[32] == 1'b1) adp_param <= {1'b0, adp_addr}; else adp_addr <= adp_param[31:0];
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_C) begin
+ if (adp_param[32]) // report GPO
+ begin adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 1) // clear selected bits in GPO
+ begin adp_sys[7:0] <= adp_sys[7:0] & ~adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 2) // set selected bits in GPO
+ begin adp_sys[7:0] <= adp_sys[7:0] | adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else if (adp_param[31:8] == 3) // overwrite bits in GPO
+ begin adp_sys[7:0] <= adp_param[7:0]; adp_state <= ADP_SYSCTL; end
+ else // 4 etc, report GPO
+ begin adp_state <= ADP_SYSCTL; end
+ end
+ else if (FNvalid_cmd(adp_cmd) == CMD_R)
+ begin ADP_BUSREADINC_next(); adp_state <= ADP_READ;
+`ifndef ADPBASIC
+ adp_count_dec <= 1'b1; // optional loop param
+`endif
+ end // no param required
+ else if (FNvalid_cmd(adp_cmd) == CMD_S)
+ begin adp_state <= ADP_SYSCHK; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_W)
+ begin adp_bus_data <= adp_param[31:0]; ADP_BUSWRITEINC_next(); adp_state <= ADP_WRITE; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_X)
+ begin com_tx_byte <= 8'h0a; com_tx_req <= 1; adp_state <= ADP_EXIT; end
+`ifndef ADPBASIC
+ else if (FNvalid_cmd(adp_cmd) == CMD_U)
+ if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_UCTRL; // non-zero count
+ else if (FNvalid_cmd(adp_cmd) == CMD_M)
+ begin if (adp_param[32] == 1'b1) adp_param <= {1'b0,adp_mask}; else adp_mask <= adp_param[31:0];
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_P)
+ if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_POLL; // non-zero count
+ else if (FNvalid_cmd(adp_cmd) == CMD_V)
+ begin if (adp_param[32] == 1'b1) adp_param <= {1'b0,adp_val}; else adp_val <= adp_param[31:0];
+ adp_state <= ADP_ECHOCMD; end
+ else if (FNvalid_cmd(adp_cmd) == CMD_F)
+ if (FNcount_down_zero_next(adp_param[31:0])) adp_state <= ADP_ECHOCMD; else adp_state <= ADP_FCTRL; // non-zero count
+`endif
+ else
+ begin ADP_txchar_next("?"); adp_state <= ADP_UNKNOWN; end // unrecognised/invald
+
+// >>>>>>>>>>>>>>>> ADP BUS WRITE and READ >>>>>>>>>>>>>>>>>>>>>>
+
+ ADP_WRITE: // perform bus write at current address pointer (and auto increment)
+ if (adp_bus_done) begin adp_state <= ADP_ECHOCMD; adp_bus_err <= HRESP_i; end
+ else begin ADP_BUSWRITEINC_next(); end // extend request
+
+ ADP_READ: // perform bus read at current adp address (and auto increment) - and report in hex
+ if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_bus_err <= HRESP_i; ADP_txchar_next("R"); adp_state <= ADP_ECHOBUS; end
+ else begin
+ ADP_BUSREADINC_next();
+`ifndef ADPBASIC
+ adp_count_dec<= 1'b1;
+`endif
+ end // extend request
+
+`ifndef ADPBASIC
+
+// >>>>>>>>>>>>>>>> ADP BINARY UPLOAD >>>>>>>>>>>>>>>>>>>>>>
+ ADP_UCTRL: // set control value
+ begin com_rx_ack <= 1; adp_state <= ADP_UREADB0; end // read next 4 bytes
+ ADP_UREADB0: // read raw binary byte
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[31:24] <= com_rx_byte; adp_state <= ADP_UREADB1; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UREADB1: // read raw binary byte
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[23:16] <= com_rx_byte; adp_state <= ADP_UREADB2; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UREADB2: // read raw binary byte 0
+ if (com_rx_done) begin com_rx_ack <= 1; adp_bus_data[15: 8] <= com_rx_byte; adp_state <= ADP_UREADB3; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UREADB3: // read raw binary byte 0
+ if (com_rx_done)
+ begin adp_bus_data[ 7: 0] <= com_rx_byte; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_UWRITE; end
+ else com_rx_ack <= 1; // extend stream request if not ready
+ ADP_UWRITE: // Write word to Addr++
+ if (adp_bus_done) begin // auto address++, count--
+ if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_UREADB0; adp_bus_err <= adp_bus_err | HRESP_i; end
+ end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request
+
+// >>>>>>>>>>>>>>>> ADP BUS READ LOOP >>>>>>>>>>>>>>>>>>>>>>
+ ADP_POLL: // set poll value
+ begin adp_bus_req <= 1; adp_bus_write <= 0; adp_state <= ADP_POLL1; end
+ ADP_POLL1: // wait for read data, no addr++
+ if (adp_bus_done) begin adp_bus_data <= HRDATA32_i; adp_count_dec <=1; adp_state <= ADP_POLL2; adp_bus_err <= adp_bus_err | HRESP_i; end
+ else begin adp_bus_req <= 1; adp_count_dec <=1; end
+ ADP_POLL2:
+ if (FNcount_down_zero_next(adp_count)) begin adp_state <= ADP_ECHOCMD; adp_bus_err <= 1'b1; end // timeout
+ else if (((adp_bus_data & adp_mask) ^ adp_val) == 0) begin adp_state <= ADP_ECHOCMD; adp_param <= {1'b0, (adp_param[31:0] - adp_count)}; end // exact match
+ else adp_state <= ADP_POLL;
+
+// >>>>>>>>>>>>>>>> ADP (ZERO) FILL MEMORY >>>>>>>>>>>>>>>>>>>>>>
+ ADP_FCTRL: // set control value
+ begin adp_bus_data <= adp_val; ADP_BUSWRITEINC_next(); adp_count_dec <= 1; adp_state <= ADP_FWRITE; end
+ ADP_FWRITE: // Write word to Addr++
+ if (adp_bus_done) begin // auto address++, count--
+ if (FNcount_down_zero_next(adp_count)) adp_state <= ADP_ECHOCMD; else begin adp_state <= ADP_FCTRL; adp_bus_err <= adp_bus_err | HRESP_i; end
+ end else begin ADP_BUSWRITEINC_next(); adp_count_dec <= 1; end // extend request
+`endif
+
+ // >>>>>>>>>>>>>>>> ADP MISC >>>>>>>>>>>>>>>>>>>>>>
+
+ ADP_UNKNOWN: // output "?"
+ if (com_tx_done) begin ADP_LINEACK_next(); end
+ else com_tx_req <= 1; // extend stream request if not ready
+
+ ADP_EXIT: // exit ADP mode
+ if (com_tx_done) adp_state <= STD_IOCHK;
+ else com_tx_req <= 1; // extend stream request if not ready
+
+ ADP_SYSCHK: // check STDIN fifo
+ begin // no upper flags so STDIN char
+ if (std_tx_ack) begin std_tx_req <=1; std_tx_byte <= adp_param[7:0]; adp_state <= ADP_STDIN; end
+ else begin adp_bus_err <= 1'b1; adp_state <= ADP_ECHOCMD; end // signal error then echo comand
+ end
+ ADP_STDIN: // push char into STDIN
+ if (std_tx_done) begin adp_bus_data <= {24'b0,adp_param[7:0]}; ADP_txchar_next("S"); adp_state <= ADP_ECHOBUS; end
+ else std_tx_req <= 1; // extend
+
+ ADP_SYSCTL: // read current status - and report in hex
+ begin adp_bus_data <= {GPI8_i[7:0],adp_sys[7:0],adp_param[15:0]}; ADP_txchar_next("C"); adp_state <= ADP_ECHOBUS; end
+
+ ADP_ECHOCMD: // output command and (param) data
+ begin ADP_txchar_next(adp_cmd & 8'h5f); adp_bus_data <= adp_param[31:0]; adp_state <= ADP_ECHOBUS; end // output command char
+ ADP_ECHOBUS: // output command space and (bus) data
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
+ else com_tx_req <= 1; // extend
+
+ ADP_WRITEHEX: // output hex word with prefix
+ begin adp_state <= ADP_WRITEHEXS; ADP_txchar_next(adp_bus_err ? "!" : " "); end // output space char, or "!" on bus error
+
+ ADP_WRITEHEXS:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX9; ADP_txchar_next("0"); end // output "0" hex prefix
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX9:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX8; ADP_txchar_next("x"); end // output "x" hex prefix
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX8:
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX7; ADP_hexdigit_next(adp_bus_data[31:28]); end // hex nibble 7
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX7: // output hex nibble 7
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX6; ADP_hexdigit_next(adp_bus_data[27:24]); end // hex nibble 6
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX6: // output hex nibble 6
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX5; ADP_hexdigit_next(adp_bus_data[23:20]); end // hex nibble 5
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX5: // output hex nibble 5
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX4; ADP_hexdigit_next(adp_bus_data[19:16]); end // hex nibble 4
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX4: // output hex nibble 4
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX3; ADP_hexdigit_next(adp_bus_data[15:12]); end // hex nibble 3
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX3: // output hex nibble 3
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX2; ADP_hexdigit_next(adp_bus_data[11: 8]); end // hex nibble 2
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX2: // output hex nibble 2
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX1; ADP_hexdigit_next(adp_bus_data[ 7: 4]); end // hex nibble 1
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX1: // output hex nibble 1
+ if (com_tx_done) begin adp_state <= ADP_WRITEHEX0; ADP_hexdigit_next(adp_bus_data[ 3: 0]); end // hex nibble 0
+ else com_tx_req <= 1; // extend
+ ADP_WRITEHEX0: // output hex nibble 0 (if not startup banner then scan to end of line before lineack
+ if (com_tx_done) begin
+ adp_bus_err <= 1'b0; // clear sticky bus error flag
+ if (banner) begin ADP_LINEACK_next(); end
+ else begin ADP_txchar_next(8'h0A); com_tx_req <= 1; adp_state <= ADP_LINEACK; end // newline and prompt
+ end else com_tx_req <= 1; // extend
+
+ ADP_LINEACK: // write EOLN
+ if (com_tx_done) begin
+ begin ADP_txchar_next(8'h0D); adp_state <= ADP_LINEACK2; end
+ end else com_tx_req <= 1; // extend
+ ADP_LINEACK2: // CR
+ if (com_tx_done) begin
+ if (banner) begin banner <= 0; adp_state <= STD_IOCHK; end
+`ifndef ADPBASIC
+ else if ((FNvalid_cmd(adp_cmd) == CMD_R) & |adp_count) //// non-zero count
+ begin ADP_BUSREADINC_next(); adp_count_dec <= 1'b1; adp_state <= ADP_READ; end //
+`endif
+ else begin ADP_txchar_next(PROMPT_CHAR); adp_state <= ADP_PROMPT; end
+ end else com_tx_req <= 1; // extend
+ default:
+ begin ADP_txchar_next("#"); adp_state <= ADP_UNKNOWN; end // default error
+ endcase
+ end
+
+endmodule
+
+////AHBLITE_ADPMASTER instancing
+//ADPmaster
+// #(.PROMPT_CHAR ("]"))
+// ADPmaster(
+// .HCLK (ahb_hclk ),
+// .HRESETn (ahb_hrestn ),
+// .HADDR32_o (ahb_haddr ),
+// .HBURST3_o (ahb_hburst ),
+// .HMASTLOCK_o (ahb_hmastlock ),
+// .HPROT4_o (ahb_hprot ),
+// .HSIZE3_o (ahb_hsize ),
+// .HTRANS2_o (ahb_htrans ),
+// .HWDATA32_o (ahb_hwdata ),
+// .HWRITE_o (ahb_hwrite ),
+// .HRDATA32_i (ahb_hrdata ),
+// .HREADY_i (ahb_hready ),
+// .HRESP_i (ahb_hresp ),
+
+// .COMRX_TREADY_o(com_rx_tready),
+// .COMRX_TDATA_i(com_rx_tdata),
+// .COMRX_TVALID_i(com_rx_tvalid),
+// .STDRX_TREADY_o(std_rx_tready),
+// .STDRX_TDATA_i(std_rx_tdata),
+// .STDRX_TVALID_i(std_rx_tvalid),
+// .COMTX_TVALID_o(com_tx_tvalid),
+// .COMTX_TDATA_o(com_tx_tdata),
+// .COMTX_TREADY_i(com_tx_tready),
+// .STDTX_TVALID_o(std_tx_tvalid),
+// .STDTX_TDATA_o(std_tx_tdata),
+// .STDTX_TREADY_i(std_tx_tready)
+
+// );
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7b1f3777d50c30180f5ec02a105f6d4280b0d604
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ADPcontrol_1.0/xgui/ADPcontrol_v1_0.tcl
@@ -0,0 +1,24 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+proc update_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } {
+ # Procedure called to update PROMPT_CHAR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.PROMPT_CHAR { PARAM_VALUE.PROMPT_CHAR } {
+ # Procedure called to validate PROMPT_CHAR
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.PROMPT_CHAR { MODELPARAM_VALUE.PROMPT_CHAR PARAM_VALUE.PROMPT_CHAR } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.PROMPT_CHAR}] ${MODELPARAM_VALUE.PROMPT_CHAR}
+}
+
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/bd/bd.tcl b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/bd/bd.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..690e4e124478e7a541fa5bd5469dc6447e9f893f
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/component.xml b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/component.xml
new file mode 100755
index 0000000000000000000000000000000000000000..5696e415cb8e30efb4743373a5ca6747614422b3
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/component.xml
@@ -0,0 +1,1482 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>axi_stream_io</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>S_AXI</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave>
+ <spirit:memoryMapRef spirit:memoryMapRef="S_AXI"/>
+ </spirit:slave>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWPROT</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WDATA</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RRESP</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARPROT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARPROT</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_AWADDR</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WREADY</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARVALID</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_WSTRB</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_BRESP</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_RDATA</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WIZ_NUM_REG</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI.WIZ_NUM_REG" spirit:minimum="4" spirit:maximum="512" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choice_pairs_ce1226b1">0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.RX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>tx</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>tx_tvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>tx_tdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>tx_tready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>WIZ_DATA_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.TX.WIZ_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197">32</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>interrupt</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="interrupt_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>INTERRUPT</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>interrupt</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>SENSITIVITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.INTERRUPT.SENSITIVITY" spirit:choiceRef="choice_list_99a1d2b9">LEVEL_HIGH</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S_AXI_ACLK</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ACLK</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">S_AXI_ARESETN</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">rx:tx:S_AXI</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>S_AXI_ARESETN</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>S_AXI_ARESETN</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:memoryMaps>
+ <spirit:memoryMap>
+ <spirit:name>S_AXI</spirit:name>
+ <spirit:addressBlock>
+ <spirit:name>Reg</spirit:name>
+ <spirit:baseAddress spirit:format="long">0</spirit:baseAddress>
+ <spirit:range spirit:format="long">4096</spirit:range>
+ <spirit:width spirit:format="long">0</spirit:width>
+ <spirit:register>
+ <spirit:name>RX_FIFO</spirit:name>
+ <spirit:displayName>RX FIFO</spirit:displayName>
+ <spirit:description>Data RX FIFO</spirit:description>
+ <spirit:addressOffset>0x00</spirit:addressOffset>
+ <spirit:size spirit:format="long">1</spirit:size>
+ </spirit:register>
+ <spirit:register>
+ <spirit:name>TX_FIFO</spirit:name>
+ <spirit:displayName>TX_FIFO</spirit:displayName>
+ <spirit:description>Data TX FIFO</spirit:description>
+ <spirit:addressOffset>0x04</spirit:addressOffset>
+ <spirit:size spirit:format="long">1</spirit:size>
+ </spirit:register>
+ <spirit:register>
+ <spirit:name>STAT_REG</spirit:name>
+ <spirit:displayName>STAT_REG</spirit:displayName>
+ <spirit:description>Status register</spirit:description>
+ <spirit:addressOffset>0x08</spirit:addressOffset>
+ <spirit:size spirit:format="long">1</spirit:size>
+ </spirit:register>
+ <spirit:register>
+ <spirit:name>CTRL_REG</spirit:name>
+ <spirit:displayName>CTRL_REG</spirit:displayName>
+ <spirit:description>Control register</spirit:description>
+ <spirit:addressOffset>0x0c</spirit:addressOffset>
+ <spirit:size spirit:format="long">1</spirit:size>
+ </spirit:register>
+ </spirit:addressBlock>
+ </spirit:memoryMap>
+ </spirit:memoryMaps>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesis</spirit:name>
+ <spirit:displayName>Verilog Synthesis</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>iostream_v1_0_axi</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>4d515fed</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+ <spirit:displayName>Verilog Simulation</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>iostream_v1_0_axi</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>4d515fed</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_softwaredriver</spirit:name>
+ <spirit:displayName>Software Driver</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>ec44730d</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>1b3a39eb</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>bd_tcl</spirit:name>
+ <spirit:displayName>Block Diagram</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>bd_tcl_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>16328387</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>interrupt</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>tx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>tx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>tx_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_tready</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_tdata</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rx_tvalid</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_ACLK</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_ARESETN</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_AWADDR</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_AWPROT</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_AWVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_AWREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_WDATA</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_WSTRB</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_WVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_WREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_BRESP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_BVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_BREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_ARADDR</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH')) - 1)">3</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_ARPROT</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">2</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_ARVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_ARREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_RDATA</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_RRESP</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">1</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_RVALID</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>S_AXI_RREADY</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ <spirit:modelParameters>
+ <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_6fc15197</spirit:name>
+ <spirit:enumeration>32</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_99a1d2b9</spirit:name>
+ <spirit:enumeration>LEVEL_HIGH</spirit:enumeration>
+ <spirit:enumeration>LEVEL_LOW</spirit:enumeration>
+ <spirit:enumeration>EDGE_RISING</spirit:enumeration>
+ <spirit:enumeration>EDGE_FALLING</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_9d8b0d81</spirit:name>
+ <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_ce1226b1</spirit:name>
+ <spirit:enumeration spirit:text="true">1</spirit:enumeration>
+ <spirit:enumeration spirit:text="false">0</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>src/axi_stream_io_v1_0_axi_s.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_4d515fed</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>src/axi_stream_io_v1_0_axi_s.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd</spirit:name>
+ <spirit:userFileType>mdd</spirit:userFileType>
+ <spirit:userFileType>driver_mdd</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>driver_tcl</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/axi_stream_io_v1_0/src/Makefile</spirit:name>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/axi_stream_io_v1_0/src/axi_stream_io.h</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/axi_stream_io_v1_0/src/axi_stream_io.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c</spirit:name>
+ <spirit:fileType>cSource</spirit:fileType>
+ <spirit:userFileType>driver_src</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>xgui/axi_stream_io_v1_0.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_1b3a39eb</spirit:userFileType>
+ <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>bd_tcl_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>bd/bd.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>AXI mapped TX and RX byte stream interface</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>C_axi_s_BASEADDR</spirit:name>
+ <spirit:displayName>C axi s BASEADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_axi_s_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_axi_s_BASEADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_axi_s_HIGHADDR</spirit:name>
+ <spirit:displayName>C axi s HIGHADDR</spirit:displayName>
+ <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_axi_s_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_axi_s_HIGHADDR">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">axi_stream_io_v1_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S_AXI_ADDR_WIDTH">4</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:supportedFamilies>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">zynquplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">artix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">artix7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">kintex7l</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">kintexu</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">kintexuplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">spartan7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">virtexuplus</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">virtexuplusHBM</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">aartix7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">aspartan7</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">azynq</xilinx:family>
+ </xilinx:supportedFamilies>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>axi_stream_io_v1.0</xilinx:displayName>
+ <xilinx:vendorDisplayName>SoC Labs</xilinx:vendorDisplayName>
+ <xilinx:vendorURL>http://www.soclabs.org</xilinx:vendorURL>
+ <xilinx:coreRevision>18</xilinx:coreRevision>
+ <xilinx:upgrades>
+ <xilinx:canUpgradeFrom>xilinx.com:user:axi_stream_io:1.0</xilinx:canUpgradeFrom>
+ </xilinx:upgrades>
+ <xilinx:coreCreationDateTime>2023-02-19T21:07:14Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@16fed581_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2ec9608d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@793f5b3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7322b269_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6e248e43_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@b4e9ef3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@426bcb85_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2e53d487_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@61dade0b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4eafa00f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@53e3a875_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@162982df_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@75f72ee4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@18aeac53_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@606d36b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@38c0eb40_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@57696f2a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@510901ec_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@60d2f4d6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3a2da1b3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@cd54b6e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@693cb83d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@ef28d1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5a59314d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@29767284_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@29f27e63_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13dc2895_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5e36f1df_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@709fc708_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@8bba7d9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@21d8e4a5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@37415f14_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@66dc3d40_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4fba07d0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@eb3af51_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4c66ef79_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@45185362_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@53225cb8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1cf08902_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4b15fae5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@17a6be36_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3301516d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3be10ef6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6a177ab9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@20e4e579_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@f741122_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@df275a0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4ac8a5fd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ae71cdc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2c59353f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2325ca04_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@498ea243_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4b8c707a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@52cdfb1d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2a0d6185_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4bac3167_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@19a83bf5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@562798bd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@123cc7f3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7062c158_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@778708cf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3a452e27_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@ece9f0f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4b895821_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3dc1927b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3e4d1f1c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@22bc955c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4c436144_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23f15bc2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2414d94e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@63ae6b17_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1f88dbb1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7517e1ec_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@668022b8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3177ce96_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@71f152fd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@30ad2c46_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5aae29a7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@292165c8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@334d7f4a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3479b8c2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13d09377_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@315680f2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ba41a48_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@d66c81a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2a99c6a5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4530b54d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@699d5142_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@17559350_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@18f15cc5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@482d154b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@9b0867a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2835d2db_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3070b16_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7616d28e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6f3420ae_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@59ca939e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3c36ad44_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1e50ae02_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@22ebfa5c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@465f09ec_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1bdbdf15_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@9060620_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@65357e50_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4e4f99_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7b82dd23_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7a9b0492_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4851d668_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ee66680_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@18058a64_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@cfe93ee_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@53c2b650_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11a6efc0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@18afa642_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@12652ecf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@e72e52b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2861fd1c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@24001396_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4454325e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3d14ded5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6a45a760_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@75c51952_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1d040cfa_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@c27bbbf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7158e610_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@499392b5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@e8df7e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11aa003e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4273f844_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5fadd8f7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c93a7db_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27ee561_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4a52c607_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11760a9c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4115d1f1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7d41ca58_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4899dc31_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13b9216c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2e05852a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@384bceec_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4ed8c48f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@200621c6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ac073d7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@18632943_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1c0d8bb2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@50809788_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7fdbc98a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3142de19_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2b3fb5f1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4faf4338_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@eb7476f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1d508d99_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@53d85a46_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@30a744ac_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@238f4e8e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2081d690_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7eee799d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2c95d02_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4e1ddea2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@21e860f8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3660b171_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3ef639f7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@16ba015e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3642a664_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@159c8828_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@14e878fa_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7f0733b2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@10cb371d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3553a1c7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3fc60b7d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@551cc009_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@752a2e44_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@63f8237c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3ca7d308_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@556a2759_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5f380808_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@651a74cf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1ecd1477_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@9b65a49_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@35b2d11e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3536a2cc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1cd68297_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1692283f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@ecc2ee6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@747cc728_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3ec1998a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6fb41197_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2c33db6f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@42060eaa_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@62342897_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@36eef4b6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@19ecf3b7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d580cef_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4f729cff_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23321c1e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@539a0d0d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@9a208b1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@38bee981_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@13576b9a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6455b470_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23aa217a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@25e0ca99_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5787a96e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@43773246_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4d61f0c5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@123ec803_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@441ed6b1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@40743552_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@575fe9d1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@760563e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@d20fcca_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4486a217_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@61023d9d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7ba954b1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@35c3b2bc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@42fe08ca_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2c2cdfab_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@14ff32f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7ec2d566_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1f0c382e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@10ce9ce2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1d3487ea_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@69af9ff5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@a3f99a9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5d79a274_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2940bbec_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3c331f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@346dc4a8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ee2a2b9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@76248ced_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5a67ad90_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3f211e20_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@31809d90_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@585e4f98_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@42ec0b0a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@85dcc7d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@782407fa_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4693fec4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@206ba19e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@65d9e06_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4115aaf6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7a3e8df0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5a0dab9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@16462cdd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@25040671_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3cc02f38_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6b7d8e4b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1450c3b3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@112dcc8a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@570107d2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2a4c82ba_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@59d6fbcc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1b1ef5d9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7bd35be_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4a26fb6f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7742ea34_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@100b085b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@66ebb4d6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@78ccb7c6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@59569c0f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@16028751_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4b46cdee_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3638e993_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5fc9a2e7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7cd279dc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2476846e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@789eb25_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7ebb6bc1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5b807ab4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@58bb111d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4dd4eede_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2030ea86_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@262d6dbc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@9879ce_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@544f9318_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@783ccf68_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@74b5dbd6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7b1a5399_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4e59d89b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1ebfb7d3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@28806a0b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4f1fac1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@193f5497_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@98f5ccf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ea19ca3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5c57bfe8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@474ef512_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1c3d233f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@561f98f3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4156e62d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7fcfc34d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4275157_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2004e159_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@f268144_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@c10c0e6_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7557e11f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@b8141f0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@63cfb8ab_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3d394ce0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@50390780_ARCHIVE_LOCATION">C:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3dbeacb1_ARCHIVE_LOCATION">C:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4f3f661b_ARCHIVE_LOCATION">C:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@716ccc45_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3278c6a2_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@398d4fdc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@384c540d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@145b9325_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5e420b14_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@720a061a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7019edbc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@32cec7a3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5b9ea533_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4ba41145_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7a1c3bc8_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3f98c05d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@85ece3f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@64329cf3_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6098b91e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@658c8c87_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5e029802_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@46a555e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@66159ec1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@78addf86_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3d48e636_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@45209cb7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3841593c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7fecffde_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@33c9e638_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@538ac29d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6c1cb496_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6e783269_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@703c8061_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1a7552e4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@71a8b655_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@393dae6f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@26792732_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@56b72513_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@50b98a45_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@75004655_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27616936_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3a54ec8f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@23e0933_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@21d6563f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7e96eb79_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@fbb747e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5a959611_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3d67b840_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1ececc3c_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2c3729d0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@753686b7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4bc158bd_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7553bd98_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@686c9917_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@15e3e3fc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@17c20476_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2890ad0d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2502d801_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@615193fc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@10d0b0e1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@1c009a65_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@77fd9a52_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@423f07dc_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@589a99d0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@b813605_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@a38b321_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@355431d9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@d146dd7_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@3bf71b0b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@27b3813d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5ef70193_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@24d7fb4d_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@11d6e696_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@43384aaf_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5dcbf251_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@33084c7e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@4c5a8f4b_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@38125fe9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@14f39b23_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@71113478_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@36296867_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@511868d0_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6f3ba609_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@78a4bc24_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@32825895_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ea7679a_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@600011e1_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@766beed_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@5f381aa9_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@300820b4_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7058d4f_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@6ec12ea5_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@2b23043_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@51253581_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.dd@7aa26a8e_ARCHIVE_LOCATION">c:/Users/dflynn/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@b23f618_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77b30d22_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4cde9694_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@120ff5dc_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@24113226_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@44aea720_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2ee819b6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4818d5b2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@38e9bfee_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1c951027_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@348407d1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@111f073e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@16159ba0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@21bb058_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@28bf5ef8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@a1c64f7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@74feff94_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4f3615f1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs/fpga/vivado/pynq/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@519e5f78_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7528fe9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@140ccca_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@19984aed_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@29788adb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@fd26a57_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@297fa2f6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@47ec066a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@377a7bfc_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6b725b5d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3eeb33d6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@30630a09_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4bfe4edb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@29cc3150_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4a07c44b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4b170789_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@398d3842_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@19987ff9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@54481846_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77667cfb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@47d2390f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7337b6ef_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1d4cfc6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6d178b5c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@33a003ad_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6e2ec915_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/axi_stream_io_1.0</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="5562313f"/>
+ <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="d6592117"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f0ec23b4"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="7c2aad6e"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="cd9ec9b5"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="6cced3b9"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
new file mode 100755
index 0000000000000000000000000000000000000000..d7af75e2819376e5c2c39a5f2e0ae96d14f52b63
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.mdd
@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER axi_stream_io
+ OPTION supported_peripherals = (axi_stream_io);
+ OPTION copyfiles = all;
+ OPTION VERSION = 1.0;
+ OPTION NAME = axi_stream_io;
+END DRIVER
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..c3a9cd03e1863921dd4ab5cbc6e020d40ae2757b
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/data/axi_stream_io.tcl
@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+ xdefine_include_file $drv_handle "xparameters.h" "axi_stream_io" "NUM_INSTANCES" "DEVICE_ID" "C_axi_s_BASEADDR" "C_axi_s_HIGHADDR"
+}
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
new file mode 100755
index 0000000000000000000000000000000000000000..21453f41a1f9f82d13b20509b772556244d9f08d
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/Makefile
@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+ echo "Compiling axi_stream_io..."
+ $(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+ $(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+ make clean
+
+include:
+ ${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+ rm -rf ${OUTS}
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
new file mode 100755
index 0000000000000000000000000000000000000000..c552cbf0e917a961b599672e2ffd4327293d004c
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.c
@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "axi_stream_io.h"
+
+/************************** Function Definitions ***************************/
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
new file mode 100755
index 0000000000000000000000000000000000000000..294e8516087a45c4aa2229806fe30eb93e47c9b9
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io.h
@@ -0,0 +1,79 @@
+
+#ifndef AXI_STREAM_IO_H
+#define AXI_STREAM_IO_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AXI_STREAM_IO_axi_s_SLV_REG0_OFFSET 0
+#define AXI_STREAM_IO_axi_s_SLV_REG1_OFFSET 4
+#define AXI_STREAM_IO_axi_s_SLV_REG2_OFFSET 8
+#define AXI_STREAM_IO_axi_s_SLV_REG3_OFFSET 12
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AXI_STREAM_IO register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param BaseAddress is the base address of the AXI_STREAM_IOdevice.
+ * @param RegOffset is the register offset from the base to write to.
+ * @param Data is the data written to the register.
+ *
+ * @return None.
+ *
+ * @note
+ * C-style signature:
+ * void AXI_STREAM_IO_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AXI_STREAM_IO_mWriteReg(BaseAddress, RegOffset, Data) \
+ Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AXI_STREAM_IO register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param BaseAddress is the base address of the AXI_STREAM_IO device.
+ * @param RegOffset is the register offset from the base to write to.
+ *
+ * @return Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * u32 AXI_STREAM_IO_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AXI_STREAM_IO_mReadReg(BaseAddress, RegOffset) \
+ Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the AXI_STREAM_IO instance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXI_STREAM_IO_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AXI_STREAM_IO_H
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
new file mode 100755
index 0000000000000000000000000000000000000000..26bea4d0c70f3d34776b08b13b6c877f2034dea1
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/drivers/axi_stream_io_v1_0/src/axi_stream_io_selftest.c
@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "axi_stream_io.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param baseaddr_p is the base address of the AXI_STREAM_IOinstance to be worked on.
+ *
+ * @return
+ *
+ * - XST_SUCCESS if all self-test code passed
+ * - XST_FAILURE if any self-test code failed
+ *
+ * @note Caching must be turned off for this function to work.
+ * @note Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AXI_STREAM_IO_Reg_SelfTest(void * baseaddr_p)
+{
+ u32 baseaddr;
+ int write_loop_index;
+ int read_loop_index;
+ int Index;
+
+ baseaddr = (u32) baseaddr_p;
+
+ xil_printf("******************************\n\r");
+ xil_printf("* User Peripheral Self Test\n\r");
+ xil_printf("******************************\n\n\r");
+
+ /*
+ * Write to user logic slave module register(s) and read back
+ */
+ xil_printf("User logic slave module test...\n\r");
+
+ for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+ AXI_STREAM_IO_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+ for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+ if ( AXI_STREAM_IO_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+ xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+ return XST_FAILURE;
+ }
+
+ xil_printf(" - slave register write/read passed\n\n\r");
+
+ return XST_SUCCESS;
+}
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..6427293a7e3a842cbc0c6c8b2efec11dd4817b08
Binary files /dev/null and b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/soclabs.org_user_axi_stream_io_1.0.zip differ
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
new file mode 100755
index 0000000000000000000000000000000000000000..1d30f66be79c030e3aedc8b1e2e5c5095e974158
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/src/axi_stream_io_v1_0_axi_s.v
@@ -0,0 +1,418 @@
+
+`timescale 1 ns / 1 ps
+
+ module iostream_v1_0_axi #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXI data bus
+ parameter integer C_S_AXI_DATA_WIDTH = 32,
+ // Width of S_AXI address bus
+ parameter integer C_S_AXI_ADDR_WIDTH = 4
+ )
+ (
+ // Users to add ports here
+ output wire interrupt,
+
+ // Ports of Axi Master Bus Interface tx
+// input wire tx_aclk,
+// input wire tx_aresetn,
+ output wire tx_tvalid,
+ output wire [7 : 0] tx_tdata,
+// output wire [0 : 0] tx_tstrb,
+// output wire tx_tlast,
+ input wire tx_tready,
+
+ // Ports of Axi Slave Bus Interface rx
+// input wire rx_aclk,
+// input wire rx_aresetn,
+ output wire rx_tready,
+ input wire [7 : 0] rx_tdata,
+// input wire [0 : 0] rx_tstrb,
+// input wire rx_tlast,
+ input wire rx_tvalid,
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global Clock Signal
+ input wire S_AXI_ACLK,
+ // Global Reset Signal. This Signal is Active LOW
+ input wire S_AXI_ARESETN,
+ // Write address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_AWADDR,
+ // Write channel Protection type. This signal indicates the
+ // privilege and security level of the transaction, and whether
+ // the transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_AWPROT,
+ // Write address valid. This signal indicates that the master signaling
+ // valid write address and control information.
+ input wire S_AXI_AWVALID,
+ // Write address ready. This signal indicates that the slave is ready
+ // to accept an address and associated control signals.
+ output wire S_AXI_AWREADY,
+ // Write data (issued by master, acceped by Slave)
+ input wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_WDATA,
+ // Write strobes. This signal indicates which byte lanes hold
+ // valid data. There is one write strobe bit for each eight
+ // bits of the write data bus.
+ input wire [(C_S_AXI_DATA_WIDTH/8)-1 : 0] S_AXI_WSTRB,
+ // Write valid. This signal indicates that valid write
+ // data and strobes are available.
+ input wire S_AXI_WVALID,
+ // Write ready. This signal indicates that the slave
+ // can accept the write data.
+ output wire S_AXI_WREADY,
+ // Write response. This signal indicates the status
+ // of the write transaction.
+ output wire [1 : 0] S_AXI_BRESP,
+ // Write response valid. This signal indicates that the channel
+ // is signaling a valid write response.
+ output wire S_AXI_BVALID,
+ // Response ready. This signal indicates that the master
+ // can accept a write response.
+ input wire S_AXI_BREADY,
+ // Read address (issued by master, acceped by Slave)
+ input wire [C_S_AXI_ADDR_WIDTH-1 : 0] S_AXI_ARADDR,
+ // Protection type. This signal indicates the privilege
+ // and security level of the transaction, and whether the
+ // transaction is a data access or an instruction access.
+ input wire [2 : 0] S_AXI_ARPROT,
+ // Read address valid. This signal indicates that the channel
+ // is signaling valid read address and control information.
+ input wire S_AXI_ARVALID,
+ // Read address ready. This signal indicates that the slave is
+ // ready to accept an address and associated control signals.
+ output wire S_AXI_ARREADY,
+ // Read data (issued by slave)
+ output wire [C_S_AXI_DATA_WIDTH-1 : 0] S_AXI_RDATA,
+ // Read response. This signal indicates the status of the
+ // read transfer.
+ output wire [1 : 0] S_AXI_RRESP,
+ // Read valid. This signal indicates that the channel is
+ // signaling the required read data.
+ output wire S_AXI_RVALID,
+ // Read ready. This signal indicates that the master can
+ // accept the read data and response information.
+ input wire S_AXI_RREADY
+ );
+
+ // AXI4LITE signals
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_awaddr;
+ reg axi_awready;
+ reg axi_wready;
+ reg [1 : 0] axi_bresp;
+ reg axi_bvalid;
+ reg [C_S_AXI_ADDR_WIDTH-1 : 0] axi_araddr;
+ reg axi_arready;
+ reg [C_S_AXI_DATA_WIDTH-1 : 0] axi_rdata;
+ reg [1 : 0] axi_rresp;
+ reg axi_rvalid;
+
+ // Example-specific design signals
+ // local parameter for addressing 32 bit / 64 bit C_S_AXI_DATA_WIDTH
+ // ADDR_LSB is used for addressing 32/64 bit registers/memories
+ // ADDR_LSB = 2 for 32 bits (n downto 2)
+ // ADDR_LSB = 3 for 64 bits (n downto 3)
+ localparam integer ADDR_LSB = (C_S_AXI_DATA_WIDTH/32) + 1;
+ localparam integer OPT_MEM_ADDR_BITS = 1;
+
+ //----------------------------------------------
+ //-- Signals for user logic register space example
+ //------------------------------------------------
+ //-- Number of Slave Registers 4
+ reg [8:0] tx_reg; // TX data
+ reg [8:0] rx_reg; // RX data
+ reg [7:0] ctrl_reg; // ctrl
+ wire slv_reg_rden;
+ wire slv_reg_wren;
+ reg [7:0] reg_data_out;
+ integer byte_index;
+ reg aw_en;
+
+ wire tx_empty = !tx_reg[8]; // request to transmit
+ wire rx_full = rx_reg[8];
+
+ // I/O Connections assignments
+
+ assign interrupt = ctrl_reg[4] & (tx_empty | rx_full);
+
+ // TX stream interface
+ assign tx_tdata = tx_reg[7:0];
+ assign tx_tvalid = tx_reg[8];
+
+ // RX stream interface
+ assign rx_tready = !rx_reg[8];
+
+ //AXI Slave
+ assign S_AXI_AWREADY = axi_awready;
+ assign S_AXI_WREADY = axi_wready;
+ assign S_AXI_BRESP = axi_bresp;
+ assign S_AXI_BVALID = axi_bvalid;
+ assign S_AXI_ARREADY = axi_arready;
+ assign S_AXI_RDATA = axi_rdata;
+ assign S_AXI_RRESP = axi_rresp;
+ assign S_AXI_RVALID = axi_rvalid;
+ // Implement axi_awready generation
+ // axi_awready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_awready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awready <= 1'b0;
+ aw_en <= 1'b1;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // slave is ready to accept write address when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_awready <= 1'b1;
+ aw_en <= 1'b0;
+ end
+ else if (S_AXI_BREADY && axi_bvalid)
+ begin
+ aw_en <= 1'b1;
+ axi_awready <= 1'b0;
+ end
+ else
+ begin
+ axi_awready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_awaddr latching
+ // This process is used to latch the address when both
+ // S_AXI_AWVALID and S_AXI_WVALID are valid.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_awaddr <= 0;
+ end
+ else
+ begin
+ if (~axi_awready && S_AXI_AWVALID && S_AXI_WVALID && aw_en)
+ begin
+ // Write Address latching
+ axi_awaddr <= S_AXI_AWADDR;
+ end
+ end
+ end
+
+ // Implement axi_wready generation
+ // axi_wready is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_AWVALID and S_AXI_WVALID are asserted. axi_wready is
+ // de-asserted when reset is low.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_wready <= 1'b0;
+ end
+ else
+ begin
+ if (~axi_wready && S_AXI_WVALID && S_AXI_AWVALID && aw_en )
+ begin
+ // slave is ready to accept write data when
+ // there is a valid write address and write data
+ // on the write address and data bus. This design
+ // expects no outstanding transactions.
+ axi_wready <= 1'b1;
+ end
+ else
+ begin
+ axi_wready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and write logic generation
+ // The write data is accepted and written to memory mapped registers when
+ // axi_awready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted. Write strobes are used to
+ // select byte enables of slave registers while writing.
+ // These registers are cleared when reset (active low) is applied.
+ // Slave register write enable is asserted when valid address and data are available
+ // and the slave is ready to accept the write address and write data.
+ assign slv_reg_wren = axi_wready && S_AXI_WVALID && axi_awready && S_AXI_AWVALID;
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ rx_reg <= 0;
+ else if ((ctrl_reg[1] == 1'b1)) // RX flush
+ rx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // SW test write
+ rx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (slv_reg_rden && (axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h0)) // Read and clear RX valid pending
+ rx_reg[8] <= 1'b0;
+ else if (rx_tvalid & rx_tready) //(!rx_reg[8]) // new RX data
+ rx_reg[8:0] <= {1'b1, rx_tdata[7:0]}; // valid rx data (= clear rx_tready inverted bit[8])
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ tx_reg <= 0;
+ else if ((ctrl_reg[0] == 1'b1)) // TX flush
+ tx_reg <= 0;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h1)) // Write and set valid pending
+ tx_reg[8:0] <= {1'b1, S_AXI_WDATA[7:0]};
+ else if (tx_tready & tx_tvalid) //& tx_reg[8]) // clear TX valid pending when req and ack
+ tx_reg[8] <= 1'b0; // clear valid when TX data acknowledged
+ end
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ ctrl_reg <= 8'b00000100;
+ else if (slv_reg_wren && (axi_awaddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] == 2'h3))
+ ctrl_reg[7:0] <= S_AXI_WDATA[7:0];
+ end
+
+ // Implement write response logic generation
+ // The write response and response valid signals are asserted by the slave
+ // when axi_wready, S_AXI_WVALID, axi_wready and S_AXI_WVALID are asserted.
+ // This marks the acceptance of address and indicates the status of
+ // write transaction.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_bvalid <= 0;
+ axi_bresp <= 2'b0;
+ end
+ else
+ begin
+ if (axi_awready && S_AXI_AWVALID && ~axi_bvalid && axi_wready && S_AXI_WVALID)
+ begin
+ // indicates a valid write response is available
+ axi_bvalid <= 1'b1;
+ axi_bresp <= 2'b0; // 'OKAY' response
+ end // work error responses in future
+ else
+ begin
+ if (S_AXI_BREADY && axi_bvalid)
+ //check if bready is asserted while bvalid is high)
+ //(there is a possibility that bready is always asserted high)
+ begin
+ axi_bvalid <= 1'b0;
+ end
+ end
+ end
+ end
+
+ // Implement axi_arready generation
+ // axi_arready is asserted for one S_AXI_ACLK clock cycle when
+ // S_AXI_ARVALID is asserted. axi_awready is
+ // de-asserted when reset (active low) is asserted.
+ // The read address is also latched when S_AXI_ARVALID is
+ // asserted. axi_araddr is reset to zero on reset assertion.
+
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_arready <= 1'b0;
+ axi_araddr <= 32'b0;
+ end
+ else
+ begin
+ if (~axi_arready && S_AXI_ARVALID)
+ begin
+ // indicates that the slave has acceped the valid read address
+ axi_arready <= 1'b1;
+ // Read address latching
+ axi_araddr <= S_AXI_ARADDR;
+ end
+ else
+ begin
+ axi_arready <= 1'b0;
+ end
+ end
+ end
+
+ // Implement axi_arvalid generation
+ // axi_rvalid is asserted for one S_AXI_ACLK clock cycle when both
+ // S_AXI_ARVALID and axi_arready are asserted. The slave registers
+ // data are available on the axi_rdata bus at this instance. The
+ // assertion of axi_rvalid marks the validity of read data on the
+ // bus and axi_rresp indicates the status of read transaction.axi_rvalid
+ // is deasserted on reset (active low). axi_rresp and axi_rdata are
+ // cleared to zero on reset (active low).
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rvalid <= 0;
+ axi_rresp <= 0;
+ end
+ else
+ begin
+ if (axi_arready && S_AXI_ARVALID && ~axi_rvalid)
+ begin
+ // Valid read data is available at the read data bus
+ axi_rvalid <= 1'b1;
+ axi_rresp <= 2'b0; // 'OKAY' response
+ end
+ else if (axi_rvalid && S_AXI_RREADY)
+ begin
+ // Read data is accepted by the master
+ axi_rvalid <= 1'b0;
+ end
+ end
+ end
+
+ // Implement memory mapped register select and read logic generation
+ // Slave register read enable is asserted when valid address is available
+ // and the slave is ready to accept the read address.
+ assign slv_reg_rden = axi_arready & S_AXI_ARVALID & ~axi_rvalid;
+ always @(*)
+ begin
+ // Address decoding for reading registers
+ case ( axi_araddr[ADDR_LSB+OPT_MEM_ADDR_BITS:ADDR_LSB] )
+ 2'h0 : reg_data_out <= rx_reg[7:0];
+ 2'h1 : reg_data_out <= tx_reg[7:0];
+ 2'h2 : reg_data_out <= {3'b000, ctrl_reg[4], !tx_empty, tx_empty, rx_full, rx_full};
+ 2'h3 : reg_data_out <= ctrl_reg;
+ default : reg_data_out <= 0;
+ endcase
+ end
+
+ // Output register or memory read data
+ always @( posedge S_AXI_ACLK )
+ begin
+ if ( S_AXI_ARESETN == 1'b0 )
+ begin
+ axi_rdata <= 0;
+ end
+ else
+ begin
+ // When there is a valid read address (S_AXI_ARVALID) with
+ // acceptance of read address by the slave (axi_arready),
+ // output the read dada
+ if (slv_reg_rden)
+ begin
+ axi_rdata <= {24'h000000, reg_data_out}; // register read data
+ end
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
new file mode 100755
index 0000000000000000000000000000000000000000..fcf8a063ad02ac8d5e1c0cefd2eaf6c6e8339a41
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/axi_stream_io_1.0/xgui/axi_stream_io_v1_0.tcl
@@ -0,0 +1,58 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
+ ipgui::add_param $IPINST -name "C_axi_s_BASEADDR" -parent ${Page_0}
+ ipgui::add_param $IPINST -name "C_axi_s_HIGHADDR" -parent ${Page_0}
+
+
+}
+
+proc update_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to update C_S_AXI_ADDR_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_ADDR_WIDTH { PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to validate C_S_AXI_ADDR_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to update C_S_AXI_DATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_S_AXI_DATA_WIDTH { PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to validate C_S_AXI_DATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_axi_s_BASEADDR { PARAM_VALUE.C_axi_s_BASEADDR } {
+ # Procedure called to update C_axi_s_BASEADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_axi_s_BASEADDR { PARAM_VALUE.C_axi_s_BASEADDR } {
+ # Procedure called to validate C_axi_s_BASEADDR
+ return true
+}
+
+proc update_PARAM_VALUE.C_axi_s_HIGHADDR { PARAM_VALUE.C_axi_s_HIGHADDR } {
+ # Procedure called to update C_axi_s_HIGHADDR when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_axi_s_HIGHADDR { PARAM_VALUE.C_axi_s_HIGHADDR } {
+ # Procedure called to validate C_axi_s_HIGHADDR
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH { MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH PARAM_VALUE.C_S_AXI_DATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S_AXI_DATA_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH { MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH PARAM_VALUE.C_S_AXI_ADDR_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_S_AXI_ADDR_WIDTH}] ${MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH}
+}
+
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4804aeba807dc4c53516378f9a0796c29f028d13
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..e23a30e81b561171df7772e99abecd3adb5a18ae
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/component.xml
@@ -0,0 +1,634 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>user</spirit:library>
+ <spirit:name>ft1248x1_to_axi_streamio</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>aresetn</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>aresetn</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>POLARITY</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ARESETN.POLARITY" spirit:choiceRef="choice_list_9d8b0d81">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>aclk</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_RESET">aresetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.ASSOCIATED_BUSIF">txd8:rxd8</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.ACLK.FREQ_TOLERANCE_HZ">-1</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>txd8</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:master/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>txd_tdata8_o</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>txd_tvalid_o</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>txd_tready_i</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>rxd8</spirit:name>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="axis_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rxd_tdata8_i</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rxd_tvalid_i</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>TREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>rxd_tready_o</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ </spirit:busInterface>
+ </spirit:busInterfaces>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_verilogsynthesis</spirit:name>
+ <spirit:displayName>Verilog Synthesis</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>ft1248x1_to_axi_streamio_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>07d8b26e</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
+ <spirit:displayName>Verilog Simulation</spirit:displayName>
+ <spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>verilog</spirit:language>
+ <spirit:modelName>ft1248x1_to_axi_streamio_v1_0</spirit:modelName>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>07d8b26e</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_xpgui</spirit:name>
+ <spirit:displayName>UI Layout</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>6f142aff</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>bd_tcl</spirit:name>
+ <spirit:displayName>Block Diagram</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
+ <spirit:fileSetRef>
+ <spirit:localName>bd_tcl_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>45a2f450</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ <spirit:ports>
+ <spirit:port>
+ <spirit:name>ft_clk_i</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ft_ssn_i</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ft_miso_o</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ft_miosio_i</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ft_miosio_o</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>ft_miosio_z</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>aclk</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>aresetn</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>txd_tvalid_o</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>txd_tdata8_o</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>txd_tready_i</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">1</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rxd_tready_o</spirit:name>
+ <spirit:wire>
+ <spirit:direction>out</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rxd_tdata8_i</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:vector>
+ <spirit:left spirit:format="long">7</spirit:left>
+ <spirit:right spirit:format="long">0</spirit:right>
+ </spirit:vector>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ <spirit:driver>
+ <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+ </spirit:driver>
+ </spirit:wire>
+ </spirit:port>
+ <spirit:port>
+ <spirit:name>rxd_tvalid_i</spirit:name>
+ <spirit:wire>
+ <spirit:direction>in</spirit:direction>
+ <spirit:wireTypeDefs>
+ <spirit:wireTypeDef>
+ <spirit:typeName>wire</spirit:typeName>
+ <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+ <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+ </spirit:wireTypeDef>
+ </spirit:wireTypeDefs>
+ </spirit:wire>
+ </spirit:port>
+ </spirit:ports>
+ <spirit:modelParameters>
+ <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+ <spirit:name>C_rxd8_TDATA_WIDTH</spirit:name>
+ <spirit:displayName>C rxd8 TDATA WIDTH</spirit:displayName>
+ <spirit:description>AXI4Stream sink: Data Width</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH" spirit:order="3" spirit:rangeType="long">8</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="integer">
+ <spirit:name>C_txd8_TDATA_WIDTH</spirit:name>
+ <spirit:displayName>C txd8 TDATA WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_txd8_TDATA_WIDTH" spirit:order="4" spirit:rangeType="long">8</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_9d8b0d81</spirit:name>
+ <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_d8920bdd</spirit:name>
+ <spirit:enumeration>8</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/SYNCHRONIZER_EDGES.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/ft1248x1_to_axi_streamio_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_1d919ea1</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>hdl/SYNCHRONIZER_EDGES.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>hdl/ft1248x1_to_axi_streamio_v1_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>xgui/ft1248x1_to_axi_streamio_v1_0.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_6f142aff</spirit:userFileType>
+ <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>bd_tcl_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>bd/bd.tcl</spirit:name>
+ <spirit:fileType>tclSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>FTDI FT1248 single bit serial to AXI 8-bit stream IO</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>C_rxd8_TDATA_WIDTH</spirit:name>
+ <spirit:displayName>C rxd8 TDATA WIDTH</spirit:displayName>
+ <spirit:description>AXI4Stream sink: Data Width</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_rxd8_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd" spirit:order="3">8</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_rxd8_TDATA_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>C_txd8_TDATA_WIDTH</spirit:name>
+ <spirit:displayName>C txd8 TDATA WIDTH</spirit:displayName>
+ <spirit:description>Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.</spirit:description>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_txd8_TDATA_WIDTH" spirit:choiceRef="choice_list_d8920bdd" spirit:order="4">8</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_txd8_TDATA_WIDTH">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ft1248x1_to_axi_streamio_v1_0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:supportedFamilies>
+ <xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
+ <xilinx:family xilinx:lifeCycle="Beta">zynquplus</xilinx:family>
+ </xilinx:supportedFamilies>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>ft1248x1_to_axi_streamio_v1.0</xilinx:displayName>
+ <xilinx:coreRevision>8</xilinx:coreRevision>
+ <xilinx:coreCreationDateTime>2023-02-26T14:27:06Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@428bf478_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77d2a63f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@401fae27_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@799f76c6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@543230e4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@860c575_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@13b2b016_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1b16e880_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@b115448_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@35f4f12f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@96c629_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@289d8498_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5e6ca2b9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@34c6c438_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2f1c92e2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6bc27418_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6470d1df_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@666070f1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4795032_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@214e5d0f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@72c6aa50_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@310b0085_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7057424_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6cf947f0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2241eee6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@64c33679_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@f32e78b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@524b62d8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@25a5c540_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5b694545_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1756c2fa_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5e55a1f4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6e825144_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@29f61c2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5d96e1e9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@608fee64_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@12bb2394_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@319424cf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3aac7e77_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@511ec980_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@330b1dd3_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@529e8eab_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@dd60893_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@c8742b2_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7621d7af_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@24f3db95_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@22c484f4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1866e24c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5571345d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@46ac3e68_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@56b1d9f1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@529ff48f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@757ac0cc_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1fcd0999_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@90370b5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@28c4e1ce_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@a3c2c51_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@33cb581b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@36560694_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5a029744_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@649708f3_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@40b4275d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2c2b1fd9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2c951206_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@60f53ba_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@62ce2736_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4869df7e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@366d857f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3143c41e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@a3a24e5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@f50a86e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@16f76b78_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@784ca772_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@266cf8b0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5985e9a7_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5b0f2afb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@261184f5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1ff5947b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@439de9f5_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3103f8a1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@43ce0b7f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@63f6aeb9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@654e1a72_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@428ff7a8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2747214_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@165165da_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@14b2bd29_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@11bb99fa_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@45d547c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@992911c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6f68f972_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@33ec70d0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77c4c6ca_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@3eaae7a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7e143239_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1ddc7b40_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@302a1c3e_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4fa27fd6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1117ca64_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@35cb4ee9_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4a5d8467_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4c4463a4_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@56eee029_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@333fc4de_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@6e8d2e2a_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@70ab23aa_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@203963e1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@509005d0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4916ee78_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@9b5c2aa_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@58902ddb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@5744b6c1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@51d00cf6_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4910d90c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@52ca7ed0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7a2f2ef_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@13049cbf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2c4fe533_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@19907224_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git_new/nanosoc/Cortex-M0/nanosoc/systems/mcu/fpga_imp/ip_repo/ft1248x1_to_axi_streamio_1.0</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="90504787"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="5194cd85"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="95a87e81"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="1be3ccaa"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="6bebc0ed"/>
+ <xilinx:targetDRCs>
+ <xilinx:targetDRC xilinx:tool="ipi">
+ <xilinx:targetDRCOption xilinx:name="ignore_freq_hz" xilinx:value="true"/>
+ </xilinx:targetDRC>
+ </xilinx:targetDRCs>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix
new file mode 100644
index 0000000000000000000000000000000000000000..e82fe55bd07f5b2021117a733d5ad768f20a16cc
Binary files /dev/null and b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/ft1248x1_to_axi_streamio_0_2.xcix differ
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
new file mode 100644
index 0000000000000000000000000000000000000000..c669ec19a796217b231dd0575337608f84445beb
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/SYNCHRONIZER_EDGES.v
@@ -0,0 +1,42 @@
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright © 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SYNCHRONIZER_EDGES (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ ,output wire syn_del_o
+ ,output wire posedge_o
+ ,output wire negedge_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+reg sync_stage3;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ sync_stage3 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ sync_stage3 <= sync_stage2;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+assign syn_del_o = (testmode_i) ? asyn_i : sync_stage3;
+assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
+assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
+
+endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..a089edf83efd967f56efb3ce3e55ed1d93a63d19
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0.v
@@ -0,0 +1,212 @@
+//-----------------------------------------------------------------------------
+// FT1248 1-bit-data to 8-bit AXI-Stream IO
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright (C) 2022-3, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
+//-----------------------------------------------------------------------------
+
+ module ft1248x1_to_axi_streamio_v1_0 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Stream Bus Interface rxd8
+ parameter integer C_rxd8_TDATA_WIDTH = 8,
+
+ // Parameters of Axi Stream Bus Interface txd8
+ parameter integer C_txd8_TDATA_WIDTH = 8
+ )
+ (
+ input wire ft_clk_i, // SCLK
+ input wire ft_ssn_i, // SS_N
+ output wire ft_miso_o, // MISO
+// inout wire ft_miosio_io, // MIOSIO tristate output control
+ input wire ft_miosio_i,
+ output wire ft_miosio_o,
+ output wire ft_miosio_z,
+
+ input wire aclk, // external primary clock
+ input wire aresetn, // external reset (active low)
+
+ // Ports of Axi stream Bus Interface TXD
+ output wire txd_tvalid_o,
+ output wire [7 : 0] txd_tdata8_o,
+ input wire txd_tready_i,
+
+ // Ports of Axi stream Bus Interface RXD
+ output wire rxd_tready_o,
+ input wire [7 : 0] rxd_tdata8_i,
+ input wire rxd_tvalid_i
+
+ );
+
+//wire ft_clk;
+wire ft_clk_rising;
+wire ft_clk_falling;
+
+wire ft_ssn;
+wire ft_miosio_i_del;
+
+SYNCHRONIZER_EDGES u_sync_ft_clk (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_clk_i),
+ .syn_o(),
+ .syn_del_o(),
+ .posedge_o(ft_clk_rising),
+ .negedge_o(ft_clk_falling)
+ );
+
+SYNCHRONIZER_EDGES u_sync_ft_ssn (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_ssn_i),
+ .syn_o(ft_ssn),
+ .syn_del_o(),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+SYNCHRONIZER_EDGES u_sync_ft_din (
+ .testmode_i(1'b0),
+ .clk_i(aclk),
+ .reset_n_i(aresetn),
+ .asyn_i(ft_miosio_i),
+ .syn_o( ),
+ .syn_del_o(ft_miosio_i_del),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+//----------------------------------------------
+//-- FT1248 1-bit protocol State Machine
+//----------------------------------------------
+
+reg [4:0] ft_state; // 17-state for bit-serial
+wire [4:0] ft_nextstate = ft_state + 5'b00001;
+
+// advance state count on rising edge of ft_clk
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ ft_state <= 5'b11111;
+ else if (ft_ssn) // sync reset
+ ft_state <= 5'b11111;
+ else if (ft_clk_rising) // loop if multi-data
+// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
+ ft_state <= ft_nextstate;
+
+// 16: bus turnaround (or bit[5])
+// 0 for CMD3
+// 3 for CMD2
+// 5 for CMD1
+// 6 for CMD0
+// 7 for cmd turnaround
+// 8 for data bit0
+// 9 for data bit1
+// 10 for data bit2
+// 11 for data bit3
+// 12 for data bit4
+// 13 for data bit5
+// 14 for data bit6
+// 15 for data bit7
+
+// capture 7-bit CMD on falling edge of clock (mid-data)
+reg [7:0] ft_cmd;
+// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ ft_cmd <= 8'b00000001;
+ else if (ft_ssn) // sync reset
+ ft_cmd <= 8'b00000001;
+ else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase)
+ ft_cmd <= {ft_cmd[6:0],ft_miosio_i};
+
+wire ft_cmd_valid = ft_cmd[7];
+wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
+wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
+
+// tristate enable for miosio (deselected status or serialized data for read command)
+wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
+assign ft_miosio_z = !ft_miosio_e;
+
+// capture (ft_cmd_txd) serial data out on falling edge of clock
+// bit [0] indicated byte valid
+reg [7:0] rxd_sr;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ rxd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ rxd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
+ rxd_sr <= {ft_miosio_i_del, rxd_sr[7:1]};
+
+// AXI STREAM handshake interfaces
+// TX stream delivers valid FT1248 read data transfer
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] txstream;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ txstream <= 9'b000000000;
+ else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
+ txstream[8] <= 1'b0;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
+ txstream[8:0] <= {1'b1, ft_miosio_i_del, rxd_sr[7:1]};
+
+assign txd_tvalid_o = txstream[8];
+assign txd_tdata8_o = txstream[7:0];
+
+
+// AXI STREAM handshake interfaces
+// RX stream accepts 8-bit data to transfer over FT1248 channel
+// 8-bit write port with extra top-bit used as valid qualifer
+
+/*
+reg [8:0] rxstream;
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ rxstream <= 9'b000000000;
+ else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data
+ rxstream[8:0] <= {1'b1,rxd_tdata8_i};
+ else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
+ rxstream[8] <= 1'b0;
+assign rxd_tready_o = !rxstream[8]; // ready until loaded
+*/
+
+// shift TXD on rising edge of clock
+reg [8:0] txd_sr;
+// rewrite for clocked
+always @(posedge aclk or negedge aresetn)
+ if (!aresetn)
+ txd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ txd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_rxd & rxd_tvalid_i & (ft_state == 5'b00111))
+ txd_sr <= rxd_tdata8_i;
+ else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
+ txd_sr <= {1'b0,txd_sr[7:1]};
+
+assign rxd_tready_o = (ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01110)); // hold until final shift
+
+//FT1248 FIFO status signals
+
+// ft_miso_o reflects TXF when deselected
+assign ft_miosio_o = (ft_ssn_i) ? txstream[8] : txd_sr[0];
+
+// ft_miso_o reflects RXE when deselected
+//assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
+assign ft_miso_o = (ft_ssn_i) ? !rxd_tvalid_i : ((ft_state == 5'b00111) & ((ft_cmd_txd) ? txstream[8]: !rxd_tvalid_i));
+
+endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
new file mode 100644
index 0000000000000000000000000000000000000000..03004bea96fe4c5e9ea0984b905d5f7a4b91d771
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_rxd8.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_axi_streamio_v1_0_rxd8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
new file mode 100644
index 0000000000000000000000000000000000000000..28cc34eafd0d52416bcfd2c8472fcda1245cd9a6
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/hdl/ft1248x1_to_axi_streamio_v1_0_txd8.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_axi_streamio_v1_0_txd8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip
new file mode 100644
index 0000000000000000000000000000000000000000..7cc581a635a8bd18d2224fc4f7b002adf2093b95
Binary files /dev/null and b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/soclabs.org_user_ft1248x1_to_axi_streamio_1.0.zip differ
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..f4b8c38737c46cbcd6d7a1adc43b9844e6b2e07f
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_axi_streamio_1.0/xgui/ft1248x1_to_axi_streamio_v1_0.tcl
@@ -0,0 +1,35 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+
+}
+
+proc update_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } {
+ # Procedure called to update C_rxd8_TDATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_rxd8_TDATA_WIDTH { PARAM_VALUE.C_rxd8_TDATA_WIDTH } {
+ # Procedure called to validate C_rxd8_TDATA_WIDTH
+ return true
+}
+
+proc update_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } {
+ # Procedure called to update C_txd8_TDATA_WIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_txd8_TDATA_WIDTH { PARAM_VALUE.C_txd8_TDATA_WIDTH } {
+ # Procedure called to validate C_txd8_TDATA_WIDTH
+ return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH { MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH PARAM_VALUE.C_rxd8_TDATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_rxd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_rxd8_TDATA_WIDTH}
+}
+
+proc update_MODELPARAM_VALUE.C_txd8_TDATA_WIDTH { MODELPARAM_VALUE.C_txd8_TDATA_WIDTH PARAM_VALUE.C_txd8_TDATA_WIDTH } {
+ # Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+ set_property value [get_property value ${PARAM_VALUE.C_txd8_TDATA_WIDTH}] ${MODELPARAM_VALUE.C_txd8_TDATA_WIDTH}
+}
+
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/bd/bd.tcl b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/bd/bd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4804aeba807dc4c53516378f9a0796c29f028d13
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/bd/bd.tcl
@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+ set full_sbusif_list [list ]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {
+ set busif_param_list [list]
+ set busif_name [get_property NAME $busif]
+ if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {
+ continue
+ }
+ foreach tparam $axi_standard_param_list {
+ lappend busif_param_list "C_${busif_name}_${tparam}"
+ }
+ bd::mark_propagate_only $cell_handle $busif_param_list
+ }
+ }
+}
+
+
+proc pre_propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ if { $val_on_cell != "" } {
+ set_property CONFIG.${tparam} $val_on_cell $busif
+ }
+ }
+ }
+ }
+}
+
+
+proc propagate {cellpath otherInfo } {
+
+ set cell_handle [get_bd_cells $cellpath]
+ set all_busif [get_bd_intf_pins $cellpath/*]
+ set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+
+ foreach busif $all_busif {
+ if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {
+ continue
+ }
+ if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {
+ continue
+ }
+
+ set busif_name [get_property NAME $busif]
+ foreach tparam $axi_standard_param_list {
+ set busif_param_name "C_${busif_name}_${tparam}"
+
+ set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]
+ set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]
+
+ if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {
+ #override property of bd_interface_net to bd_cell -- only for slaves. May check for supported values..
+ if { $val_on_cell_intf_pin != "" } {
+ set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle
+ }
+ }
+ }
+ }
+}
+
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/component.xml b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/component.xml
new file mode 100644
index 0000000000000000000000000000000000000000..c9d8d6e573fef4d3a7f1d643e634a02f82032d93
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/component.xml
@@ -0,0 +1,127 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>soclabs.org</spirit:vendor>
+ <spirit:library>ip</spirit:library>
+ <spirit:name>ft1248x1_to_stream8_1.0</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:model>
+ <spirit:views>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagesynthesis</spirit:name>
+ <spirit:displayName>Synthesis</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:synthesis</spirit:envIdentifier>
+ <spirit:language>Verilog</spirit:language>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagesynthesis_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>5c0c346d</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ <spirit:view>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
+ <spirit:displayName>Simulation</spirit:displayName>
+ <spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
+ <spirit:language>Verilog</spirit:language>
+ <spirit:fileSetRef>
+ <spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
+ </spirit:fileSetRef>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>viewChecksum</spirit:name>
+ <spirit:value>5c0c346d</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ </spirit:view>
+ </spirit:views>
+ </spirit:model>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>src/synclib.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>src/ft1248x1_to_stream8.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>CHECKSUM_06e9a745</spirit:userFileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>src/synclib.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>src/ft1248x1_to_stream8.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:logicalName>ft1248x1_to_stream8_1.0</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>ft1248x1_to_stream8_1.0:1.0</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ft1248x1_to_stream8_1_0_v1_0</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:taxonomies>
+ <xilinx:taxonomy>/AXI_Infrastructure</xilinx:taxonomy>
+ <xilinx:taxonomy>/Debug_&_Verification/Debug</xilinx:taxonomy>
+ <xilinx:taxonomy>/Embedded_Processing/Debug_&_Verification/Debug</xilinx:taxonomy>
+ </xilinx:taxonomies>
+ <xilinx:displayName>ft1248x1_to_stream8_1.0_v1_0</xilinx:displayName>
+ <xilinx:hideInCatalogGUI>true</xilinx:hideInCatalogGUI>
+ <xilinx:definitionSource>package_project</xilinx:definitionSource>
+ <xilinx:vendorDisplayName>soclabs.org</xilinx:vendorDisplayName>
+ <xilinx:vendorURL>http://soclabs.org</xilinx:vendorURL>
+ <xilinx:coreRevision>1</xilinx:coreRevision>
+ <xilinx:upgrades>
+ <xilinx:canUpgradeFrom>xilinx.com:ip:ft1248x1_to_stream8_1.0:1.0</xilinx:canUpgradeFrom>
+ </xilinx:upgrades>
+ <xilinx:coreCreationDateTime>2022-08-18T13:41:50Z</xilinx:coreCreationDateTime>
+ <xilinx:tags>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@554a8be0_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@2c2e0f51_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4bf8650c_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@50a2d20f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@679c5188_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@61453e2b_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@20d8eb40_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@9d02819_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1f726801_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7d50b16d_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@558791b8_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@dade147_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@50c7becf_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@134862eb_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4c308b0f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@174caa76_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@33e02927_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@1bc1eca_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@247a24c1_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7f189307_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@4fc3a402_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@62f43e05_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@7f223669_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ <xilinx:tag xilinx:name="ui.data.coregen.df@77281e8f_ARCHIVE_LOCATION">/home/dwf1m12/soclabs_git/soclabs-cortexm0-mcu/Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/ip_repo/ft1248x1_to_stream8_1.0</xilinx:tag>
+ </xilinx:tags>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2021.1</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="8af10ea9"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="f93808b1"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix
new file mode 100644
index 0000000000000000000000000000000000000000..1b2410ad1ecde98574e898028f41ad55c1c8f3b1
Binary files /dev/null and b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/ft1248x1_to_stream8_0.xcix differ
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..822ab4cd47a344ec599d082d80384686bdb6360d
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0.v
@@ -0,0 +1,75 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+
+ // Parameters of Axi Slave Bus Interface RXD8
+ parameter integer C_RXD8_TDATA_WIDTH = 32,
+
+ // Parameters of Axi Master Bus Interface TXD8
+ parameter integer C_TXD8_TDATA_WIDTH = 32,
+ parameter integer C_TXD8_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+
+ // Ports of Axi Slave Bus Interface RXD8
+ input wire rxd8_aclk,
+ input wire rxd8_aresetn,
+ output wire rxd8_tready,
+ input wire [C_RXD8_TDATA_WIDTH-1 : 0] rxd8_tdata,
+ input wire [(C_RXD8_TDATA_WIDTH/8)-1 : 0] rxd8_tstrb,
+ input wire rxd8_tlast,
+ input wire rxd8_tvalid,
+
+ // Ports of Axi Master Bus Interface TXD8
+ input wire txd8_aclk,
+ input wire txd8_aresetn,
+ output wire txd8_tvalid,
+ output wire [C_TXD8_TDATA_WIDTH-1 : 0] txd8_tdata,
+ output wire [(C_TXD8_TDATA_WIDTH/8)-1 : 0] txd8_tstrb,
+ output wire txd8_tlast,
+ input wire txd8_tready
+ );
+// Instantiation of Axi Bus Interface RXD8
+ ft1248x1_to_stream8_v1_0_RXD8 # (
+ .C_S_AXIS_TDATA_WIDTH(C_RXD8_TDATA_WIDTH)
+ ) ft1248x1_to_stream8_v1_0_RXD8_inst (
+ .S_AXIS_ACLK(rxd8_aclk),
+ .S_AXIS_ARESETN(rxd8_aresetn),
+ .S_AXIS_TREADY(rxd8_tready),
+ .S_AXIS_TDATA(rxd8_tdata),
+ .S_AXIS_TSTRB(rxd8_tstrb),
+ .S_AXIS_TLAST(rxd8_tlast),
+ .S_AXIS_TVALID(rxd8_tvalid)
+ );
+
+// Instantiation of Axi Bus Interface TXD8
+ ft1248x1_to_stream8_v1_0_TXD8 # (
+ .C_M_AXIS_TDATA_WIDTH(C_TXD8_TDATA_WIDTH),
+ .C_M_START_COUNT(C_TXD8_START_COUNT)
+ ) ft1248x1_to_stream8_v1_0_TXD8_inst (
+ .M_AXIS_ACLK(txd8_aclk),
+ .M_AXIS_ARESETN(txd8_aresetn),
+ .M_AXIS_TVALID(txd8_tvalid),
+ .M_AXIS_TDATA(txd8_tdata),
+ .M_AXIS_TSTRB(txd8_tstrb),
+ .M_AXIS_TLAST(txd8_tlast),
+ .M_AXIS_TREADY(txd8_tready)
+ );
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
new file mode 100644
index 0000000000000000000000000000000000000000..9b39ac62c1aa1246d5b566160b5bd7b5dd1d07ad
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_RXD8.v
@@ -0,0 +1,167 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0_RXD8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // AXI4Stream sink: Data Width
+ parameter integer C_S_AXIS_TDATA_WIDTH = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // AXI4Stream sink: Clock
+ input wire S_AXIS_ACLK,
+ // AXI4Stream sink: Reset
+ input wire S_AXIS_ARESETN,
+ // Ready to accept data in
+ output wire S_AXIS_TREADY,
+ // Data in
+ input wire [C_S_AXIS_TDATA_WIDTH-1 : 0] S_AXIS_TDATA,
+ // Byte qualifier
+ input wire [(C_S_AXIS_TDATA_WIDTH/8)-1 : 0] S_AXIS_TSTRB,
+ // Indicates boundary of last packet
+ input wire S_AXIS_TLAST,
+ // Data is in valid
+ input wire S_AXIS_TVALID
+ );
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // Total number of input data.
+ localparam NUMBER_OF_INPUT_WORDS = 8;
+ // bit_num gives the minimum number of bits needed to address 'NUMBER_OF_INPUT_WORDS' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_INPUT_WORDS-1);
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 1'b0, // This is the initial/idle state
+
+ WRITE_FIFO = 1'b1; // In this state FIFO is written with the
+ // input stream data S_AXIS_TDATA
+ wire axis_tready;
+ // State variable
+ reg mst_exec_state;
+ // FIFO implementation signals
+ genvar byte_index;
+ // FIFO write enable
+ wire fifo_wren;
+ // FIFO full flag
+ reg fifo_full_flag;
+ // FIFO write pointer
+ reg [bit_num-1:0] write_pointer;
+ // sink has accepted all the streaming data and stored in FIFO
+ reg writes_done;
+ // I/O Connections assignments
+
+ assign S_AXIS_TREADY = axis_tready;
+ // Control state machine implementation
+ always @(posedge S_AXIS_ACLK)
+ begin
+ if (!S_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The sink starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if (S_AXIS_TVALID)
+ begin
+ mst_exec_state <= WRITE_FIFO;
+ end
+ else
+ begin
+ mst_exec_state <= IDLE;
+ end
+ WRITE_FIFO:
+ // When the sink has accepted all the streaming input data,
+ // the interface swiches functionality to a streaming master
+ if (writes_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ // The sink accepts and stores tdata
+ // into FIFO
+ mst_exec_state <= WRITE_FIFO;
+ end
+
+ endcase
+ end
+ // AXI Streaming Sink
+ //
+ // The example design sink is always ready to accept the S_AXIS_TDATA until
+ // the FIFO is not filled with NUMBER_OF_INPUT_WORDS number of input words.
+ assign axis_tready = ((mst_exec_state == WRITE_FIFO) && (write_pointer <= NUMBER_OF_INPUT_WORDS-1));
+
+ always@(posedge S_AXIS_ACLK)
+ begin
+ if(!S_AXIS_ARESETN)
+ begin
+ write_pointer <= 0;
+ writes_done <= 1'b0;
+ end
+ else
+ if (write_pointer <= NUMBER_OF_INPUT_WORDS-1)
+ begin
+ if (fifo_wren)
+ begin
+ // write pointer is incremented after every write to the FIFO
+ // when FIFO write signal is enabled.
+ write_pointer <= write_pointer + 1;
+ writes_done <= 1'b0;
+ end
+ if ((write_pointer == NUMBER_OF_INPUT_WORDS-1)|| S_AXIS_TLAST)
+ begin
+ // reads_done is asserted when NUMBER_OF_INPUT_WORDS numbers of streaming data
+ // has been written to the FIFO which is also marked by S_AXIS_TLAST(kept for optional usage).
+ writes_done <= 1'b1;
+ end
+ end
+ end
+
+ // FIFO write enable generation
+ assign fifo_wren = S_AXIS_TVALID && axis_tready;
+
+ // FIFO Implementation
+ generate
+ for(byte_index=0; byte_index<= (C_S_AXIS_TDATA_WIDTH/8-1); byte_index=byte_index+1)
+ begin:FIFO_GEN
+
+ reg [(C_S_AXIS_TDATA_WIDTH/4)-1:0] stream_data_fifo [0 : NUMBER_OF_INPUT_WORDS-1];
+
+ // Streaming input data is stored in FIFO
+
+ always @( posedge S_AXIS_ACLK )
+ begin
+ if (fifo_wren)// && S_AXIS_TSTRB[byte_index])
+ begin
+ stream_data_fifo[write_pointer] <= S_AXIS_TDATA[(byte_index*8+7) -: 8];
+ end
+ end
+ end
+ endgenerate
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
new file mode 100644
index 0000000000000000000000000000000000000000..3abf9f8a3c52a9a6716e09c985c2a15faa383be5
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/hdl/ft1248x1_to_stream8_v1_0_TXD8.v
@@ -0,0 +1,228 @@
+
+`timescale 1 ns / 1 ps
+
+ module ft1248x1_to_stream8_v1_0_TXD8 #
+ (
+ // Users to add parameters here
+
+ // User parameters ends
+ // Do not modify the parameters beyond this line
+
+ // Width of S_AXIS address bus. The slave accepts the read and write addresses of width C_M_AXIS_TDATA_WIDTH.
+ parameter integer C_M_AXIS_TDATA_WIDTH = 32,
+ // Start count is the number of clock cycles the master will wait before initiating/issuing any transaction.
+ parameter integer C_M_START_COUNT = 32
+ )
+ (
+ // Users to add ports here
+
+ // User ports ends
+ // Do not modify the ports beyond this line
+
+ // Global ports
+ input wire M_AXIS_ACLK,
+ //
+ input wire M_AXIS_ARESETN,
+ // Master Stream Ports. TVALID indicates that the master is driving a valid transfer, A transfer takes place when both TVALID and TREADY are asserted.
+ output wire M_AXIS_TVALID,
+ // TDATA is the primary payload that is used to provide the data that is passing across the interface from the master.
+ output wire [C_M_AXIS_TDATA_WIDTH-1 : 0] M_AXIS_TDATA,
+ // TSTRB is the byte qualifier that indicates whether the content of the associated byte of TDATA is processed as a data byte or a position byte.
+ output wire [(C_M_AXIS_TDATA_WIDTH/8)-1 : 0] M_AXIS_TSTRB,
+ // TLAST indicates the boundary of a packet.
+ output wire M_AXIS_TLAST,
+ // TREADY indicates that the slave can accept a transfer in the current cycle.
+ input wire M_AXIS_TREADY
+ );
+ // Total number of output data
+ localparam NUMBER_OF_OUTPUT_WORDS = 8;
+
+ // function called clogb2 that returns an integer which has the
+ // value of the ceiling of the log base 2.
+ function integer clogb2 (input integer bit_depth);
+ begin
+ for(clogb2=0; bit_depth>0; clogb2=clogb2+1)
+ bit_depth = bit_depth >> 1;
+ end
+ endfunction
+
+ // WAIT_COUNT_BITS is the width of the wait counter.
+ localparam integer WAIT_COUNT_BITS = clogb2(C_M_START_COUNT-1);
+
+ // bit_num gives the minimum number of bits needed to address 'depth' size of FIFO.
+ localparam bit_num = clogb2(NUMBER_OF_OUTPUT_WORDS);
+
+ // Define the states of state machine
+ // The control state machine oversees the writing of input streaming data to the FIFO,
+ // and outputs the streaming data from the FIFO
+ parameter [1:0] IDLE = 2'b00, // This is the initial/idle state
+
+ INIT_COUNTER = 2'b01, // This state initializes the counter, once
+ // the counter reaches C_M_START_COUNT count,
+ // the state machine changes state to SEND_STREAM
+ SEND_STREAM = 2'b10; // In this state the
+ // stream data is output through M_AXIS_TDATA
+ // State variable
+ reg [1:0] mst_exec_state;
+ // Example design FIFO read pointer
+ reg [bit_num-1:0] read_pointer;
+
+ // AXI Stream internal signals
+ //wait counter. The master waits for the user defined number of clock cycles before initiating a transfer.
+ reg [WAIT_COUNT_BITS-1 : 0] count;
+ //streaming data valid
+ wire axis_tvalid;
+ //streaming data valid delayed by one clock cycle
+ reg axis_tvalid_delay;
+ //Last of the streaming data
+ wire axis_tlast;
+ //Last of the streaming data delayed by one clock cycle
+ reg axis_tlast_delay;
+ //FIFO implementation signals
+ reg [C_M_AXIS_TDATA_WIDTH-1 : 0] stream_data_out;
+ wire tx_en;
+ //The master has issued all the streaming data stored in FIFO
+ reg tx_done;
+
+
+ // I/O Connections assignments
+
+ assign M_AXIS_TVALID = axis_tvalid_delay;
+ assign M_AXIS_TDATA = stream_data_out;
+ assign M_AXIS_TLAST = axis_tlast_delay;
+ assign M_AXIS_TSTRB = {(C_M_AXIS_TDATA_WIDTH/8){1'b1}};
+
+
+ // Control state machine implementation
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ // Synchronous reset (active low)
+ begin
+ mst_exec_state <= IDLE;
+ count <= 0;
+ end
+ else
+ case (mst_exec_state)
+ IDLE:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ //if ( count == 0 )
+ // begin
+ mst_exec_state <= INIT_COUNTER;
+ // end
+ //else
+ // begin
+ // mst_exec_state <= IDLE;
+ // end
+
+ INIT_COUNTER:
+ // The slave starts accepting tdata when
+ // there tvalid is asserted to mark the
+ // presence of valid streaming data
+ if ( count == C_M_START_COUNT - 1 )
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ else
+ begin
+ count <= count + 1;
+ mst_exec_state <= INIT_COUNTER;
+ end
+
+ SEND_STREAM:
+ // The example design streaming master functionality starts
+ // when the master drives output tdata from the FIFO and the slave
+ // has finished storing the S_AXIS_TDATA
+ if (tx_done)
+ begin
+ mst_exec_state <= IDLE;
+ end
+ else
+ begin
+ mst_exec_state <= SEND_STREAM;
+ end
+ endcase
+ end
+
+
+ //tvalid generation
+ //axis_tvalid is asserted when the control state machine's state is SEND_STREAM and
+ //number of output streaming data is less than the NUMBER_OF_OUTPUT_WORDS.
+ assign axis_tvalid = ((mst_exec_state == SEND_STREAM) && (read_pointer < NUMBER_OF_OUTPUT_WORDS));
+
+ // AXI tlast generation
+ // axis_tlast is asserted number of output streaming data is NUMBER_OF_OUTPUT_WORDS-1
+ // (0 to NUMBER_OF_OUTPUT_WORDS-1)
+ assign axis_tlast = (read_pointer == NUMBER_OF_OUTPUT_WORDS-1);
+
+
+ // Delay the axis_tvalid and axis_tlast signal by one clock cycle
+ // to match the latency of M_AXIS_TDATA
+ always @(posedge M_AXIS_ACLK)
+ begin
+ if (!M_AXIS_ARESETN)
+ begin
+ axis_tvalid_delay <= 1'b0;
+ axis_tlast_delay <= 1'b0;
+ end
+ else
+ begin
+ axis_tvalid_delay <= axis_tvalid;
+ axis_tlast_delay <= axis_tlast;
+ end
+ end
+
+
+ //read_pointer pointer
+
+ always@(posedge M_AXIS_ACLK)
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ read_pointer <= 0;
+ tx_done <= 1'b0;
+ end
+ else
+ if (read_pointer <= NUMBER_OF_OUTPUT_WORDS-1)
+ begin
+ if (tx_en)
+ // read pointer is incremented after every read from the FIFO
+ // when FIFO read signal is enabled.
+ begin
+ read_pointer <= read_pointer + 1;
+ tx_done <= 1'b0;
+ end
+ end
+ else if (read_pointer == NUMBER_OF_OUTPUT_WORDS)
+ begin
+ // tx_done is asserted when NUMBER_OF_OUTPUT_WORDS numbers of streaming data
+ // has been out.
+ tx_done <= 1'b1;
+ end
+ end
+
+
+ //FIFO read enable generation
+
+ assign tx_en = M_AXIS_TREADY && axis_tvalid;
+
+ // Streaming output data is read from FIFO
+ always @( posedge M_AXIS_ACLK )
+ begin
+ if(!M_AXIS_ARESETN)
+ begin
+ stream_data_out <= 1;
+ end
+ else if (tx_en)// && M_AXIS_TSTRB[byte_index]
+ begin
+ stream_data_out <= read_pointer + 32'b1;
+ end
+ end
+
+ // Add user logic here
+
+ // User logic ends
+
+ endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/ip_project_archive.zip b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/ip_project_archive.zip
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diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip
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Binary files /dev/null and b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/soclabs.org_user_ft1248x1_to_stream8_1.0.zip differ
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
new file mode 100755
index 0000000000000000000000000000000000000000..6c55abc8d956769a1ca142d910603d780445a4ca
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/src/ft1248x1_to_stream8.v
@@ -0,0 +1,187 @@
+//-----------------------------------------------------------------------------
+// FT1248 1-bit-data to 8-bit AXI-Stream IO
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Abstract : FT1248 1-bit data off-chip interface (emulate FT232H device)
+//-----------------------------------------------------------------------------
+
+
+module ft1248x1_to_stream8
+ (
+ input wire ft_clk_i, // SCLK
+ input wire ft_ssn_i, // SS_N
+ output wire ft_miso_o, // MISO
+// inout wire ft_miosio_io, // MIOSIO tristate output control
+ input wire ft_miosio_i,
+ output wire ft_miosio_o,
+ output wire ft_miosio_z,
+// assign ft_miosio_io = (ft_miosio_z) ? 1'bz : ft_miosio_o;// tri-state pad control for MIOSIO
+//
+// assign #1 ft_miosio_i = ft_miosio_io; //add notional delay on inout to ensure last "half-bit" on FT1248TXD is sampled before tri-stated
+
+ input wire clk, // external primary clock
+ input wire resetn, // external reset (active low)
+
+ // Ports of Axi stream Bus Interface TXD
+ output wire txd_tvalid_o,
+ output wire [7 : 0] txd_tdata8_o,
+ input wire txd_tready_i,
+
+ // Ports of Axi stream Bus Interface RXD
+ output wire rxd_tready_o,
+ input wire [7 : 0] rxd_tdata8_i,
+ input wire rxd_tvalid_i
+
+ );
+
+//wire ft_clk;
+wire ft_clk_rising;
+wire ft_clk_falling;
+
+wire ft_ssn;
+//wire ft_ssn_rising;
+//wire ft_ssn_falling;
+
+SYNCHRONIZER_EDGES u_xync_ft_clk (
+ .testmode_i(1'b0),
+ .clk_i(clk),
+ .reset_n_i(resetn),
+ .asyn_i(ft_clk_i),
+ .syn_o(),
+ .posedge_o(ft_clk_rising),
+ .negedge_o(ft_clk_falling)
+ );
+
+SYNCHRONIZER_EDGES u_xync_ft_ssn (
+ .testmode_i(1'b0),
+ .clk_i(clk),
+ .reset_n_i(resetn),
+ .asyn_i(ft_ssn_i),
+ .syn_o(ft_ssn),
+ .posedge_o( ),
+ .negedge_o( )
+ );
+
+//----------------------------------------------
+//-- FT1248 1-bit protocol State Machine
+//----------------------------------------------
+
+reg [4:0] ft_state; // 17-state for bit-serial
+wire [4:0] ft_nextstate = ft_state + 5'b00001;
+
+// advance state count on rising edge of ft_clk
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ ft_state <= 5'b11111;
+ else if (ft_ssn) // sync reset
+ ft_state <= 5'b11111;
+ else if (ft_clk_rising) // loop if multi-data
+// ft_state <= (ft_state == 5'b01111) ? 5'b01000 : ft_nextstate;
+ ft_state <= ft_nextstate;
+
+// 16: bus turnaround (or bit[5])
+// 0 for CMD3
+// 3 for CMD2
+// 5 for CMD1
+// 6 for CMD0
+// 7 for cmd turnaround
+// 8 for data bit0
+// 9 for data bit1
+// 10 for data bit2
+// 11 for data bit3
+// 12 for data bit4
+// 13 for data bit5
+// 14 for data bit6
+// 15 for data bit7
+
+// capture 7-bit CMD on falling edge of clock (mid-data)
+reg [7:0] ft_cmd;
+// - valid sample ready after 7th edge (ready RX or TX data phase functionality)
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ ft_cmd <= 8'b00000001;
+ else if (ft_ssn) // sync reset
+ ft_cmd <= 8'b00000001;
+ else if (ft_clk_falling & !ft_state[3] & !ft_nextstate[3]) // on shift if CMD phase)
+ ft_cmd <= {ft_cmd[6:0],ft_miosio_i};
+
+wire ft_cmd_valid = ft_cmd[7];
+wire ft_cmd_rxd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & ft_cmd[0];
+wire ft_cmd_txd = ft_cmd[7] & !ft_cmd[6] & !ft_cmd[3] & !ft_cmd[1] & !ft_cmd[0];
+
+// tristate enable for miosio (deselected status or serialized data for read command)
+wire ft_miosio_e = ft_ssn_i | (ft_cmd_rxd & !ft_state[4] & ft_state[3]);
+assign ft_miosio_z = !ft_miosio_e;
+
+// capture (ft_cmd_txd) serial data out on falling edge of clock
+// bit [0] indicated byte valid
+reg [7:0] rxd_sr;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ rxd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ rxd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state[4:3] == 2'b01)) //serial shift
+ rxd_sr <= {ft_miosio_i, rxd_sr[7:1]};
+
+// AXI STREAM handshake interfaces
+// TX stream delivers valid FT1248 read data transfer
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] txstream;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ txstream <= 9'b000000000;
+ else if (txstream[8] & txd_tready_i) // priority clear stream data valid when accepted
+ txstream[8] <= 1'b0;
+ else if (ft_clk_falling & ft_cmd_txd & (ft_state==5'b01111)) //load as last shift arrives
+ txstream[8:0] <= {1'b1, 1'b0, rxd_sr[7:1]};
+
+assign txd_tvalid_o = txstream[8];
+assign txd_tdata8_o = txstream[7:0];
+
+
+// AXI STREAM handshake interfaces
+// RX stream accepts 8-bit data to transfer over FT1248 channel
+// 8-bit write port with extra top-bit used as valid qualifer
+reg [8:0] rxstream;
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ rxstream <= 9'b000000000;
+ else if (!rxstream[8] & rxd_tvalid_i) // if empty can accept valid RX stream data
+ rxstream[8:0] <= {1'b1,rxd_tdata8_i};
+ else if (rxstream[8] & ft_clk_rising & ft_cmd_rxd & (ft_state==5'b01111)) // hold until final shift completion
+ rxstream[8] <= 1'b0;
+assign rxd_tready_o = !rxstream[8]; // ready until loaded
+
+// shift TXD on rising edge of clock
+reg [7:0] txd_sr;
+// rewrite for clocked
+always @(posedge clk or negedge resetn)
+ if (!resetn)
+ txd_sr <= 8'b00000000;
+ else if (ft_ssn) // sync reset
+ txd_sr <= 8'b00000000;
+ else if (ft_clk_falling & ft_cmd_rxd & (ft_state == 5'b00111))
+ txd_sr <= rxstream[8] ? rxstream[7:0] : 8'b00000000;
+ else if (ft_clk_rising & ft_cmd_rxd & (ft_state[4:3] == 2'b01)) //serial shift
+ txd_sr <= {1'b0,txd_sr[7:1]};
+
+
+//FT1248 FIFO status signals
+
+// ft_miso_o reflects TXF when deselected
+assign ft_miosio_o = (ft_ssn_i) ? !txstream[8] : txd_sr[0];
+
+// ft_miso_o reflects RXE when deselected
+assign ft_miso_o = (ft_ssn_i) ? rxstream[8] : (ft_state == 5'b00111);
+
+
+endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/src/synclib.v b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/src/synclib.v
new file mode 100755
index 0000000000000000000000000000000000000000..1daf61f27dffed42591278f8e46a4239a46554a2
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/src/synclib.v
@@ -0,0 +1,139 @@
+// A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+//
+// Contributors
+//
+// David Flynn (d.w.flynn@soton.ac.uk)
+//
+// Copyright � 2022, SoC Labs (www.soclabs.org)
+//-----------------------------------------------------------------------------
+
+module SYNCHRONIZER (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+module SYNCHRONIZER_EDGES (
+ input wire testmode_i
+ ,input wire clk_i
+ ,input wire reset_n_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ ,output wire posedge_o
+ ,output wire negedge_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+reg sync_stage3;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ sync_stage3 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ sync_stage3 <= sync_stage2;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+assign posedge_o = (testmode_i) ? asyn_i : ( sync_stage2 & !sync_stage3);
+assign negedge_o = (testmode_i) ? asyn_i : (!sync_stage2 & sync_stage3);
+
+endmodule
+
+module SYNCHRONIZER_RST_LO (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+module SYNCHRONIZER_RST_HI (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,input wire asyn_i
+ ,output wire syn_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b1;
+ sync_stage2 <= 1'b1;
+ end
+ else begin
+ sync_stage1 <= asyn_i;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign syn_o = (testmode_i) ? asyn_i : sync_stage2;
+
+endmodule
+
+
+module NRST_SYNCHRONIZER_LO (
+ input wire reset_n_i
+ ,input wire testmode_i
+ ,input wire clk_i
+ ,output wire synreset_n_o
+ );
+
+reg sync_stage1;
+reg sync_stage2;
+
+ always @(posedge clk_i or negedge reset_n_i)
+ if(~reset_n_i) begin
+ sync_stage1 <= 1'b0;
+ sync_stage2 <= 1'b0;
+ end
+ else begin
+ sync_stage1 <= 1'b1;
+ sync_stage2 <= sync_stage1;
+ end
+
+assign synreset_n_o = (testmode_i) ? reset_n_i : sync_stage2;
+
+endmodule
diff --git a/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..0db18e9a9d18f3e4b14481f7664b048781110ca3
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/ip_repo/ft1248x1_to_stream8_1.0/xgui/ft1248x1_to_stream8_v1_0.tcl
@@ -0,0 +1,10 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+ ipgui::add_param $IPINST -name "Component_Name"
+ #Adding Page
+ ipgui::add_page $IPINST -name "Page 0"
+
+
+}
+
+
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/arm_tests/aes128_tests.bin b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/arm_tests/aes128_tests.bin
new file mode 100644
index 0000000000000000000000000000000000000000..dbe07530288c1e4f1c3358399e609b9349d89af6
Binary files /dev/null and b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/arm_tests/aes128_tests.bin differ
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
new file mode 100755
index 0000000000000000000000000000000000000000..4da3b3396dff1710d66e943d7e91337483665b50
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/driver/uartlite.py
@@ -0,0 +1,88 @@
+from time import sleep, time
+from pynq import MMIO
+
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+
+#Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+OVERRUN_ERR = 5
+FRAME_ERR = 6
+PARITY_ERR =7
+
+#Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class UartLite:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address,0x10000, debug=False)
+ self.address = address
+
+ def getBit(self,num,pos):
+ return (num&1<<pos)>>pos
+
+ def setupCtrlReg(self):
+ # Reset FIFOs, disable interrupts
+ self.uart.write(CTRL_REG, 1<<RST_TX | 1<<RST_RX)
+ sleep(0.0)
+ self.uart.write(CTRL_REG,0)
+ sleep(0.0)
+
+ def currentStatus(self):
+ """Returns object that specifies current status of axi core"""
+ status = self.uart.read(STAT_REG)
+ return {'RX_VALID':self.getBit(status,RX_VALID),
+ 'RX_FULL':self.getBit(status, RX_FULL),
+ 'TX_EMPTY':self.getBit(status, TX_EMPTY),
+ 'TX_FULL':self.getBit(status, TX_FULL),
+ 'IS_INTR':self.getBit(status, IS_INTR),
+ 'OVERRUN_ERR':self.getBit(status, OVERRUN_ERR),
+ 'FRAME_ERR':self.getBit(status, FRAME_ERR),
+ 'PARITY_ERR':self.getBit(status, PARITY_ERR)}
+
+ def read(self, count, timeout = 1):
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, skip if timeout exceeded
+ while (not (self.uart.read(STAT_REG) & 1<<RX_VALID)) and (time()<stop_time):
+ pass
+ if time()>=stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout = 10):
+ """
+ buf: iterable
+
+ """
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ #Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1<<TX_FULL) and (time()<stop_time):
+ pass
+ # Check timeout
+ if time()>stop_time:
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+ def readLine(self):
+ buf = self.read(1)
+ if len(buf) ==0:
+ return ""
+ while '\n' not in buf:
+ buf += self.read(1)
+ return buf
\ No newline at end of file
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-ADP-validation.ipynb b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-ADP-validation.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..5026330001cae9fd0d4bc810e1a45dffa18f7efc
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-ADP-validation.ipynb
@@ -0,0 +1,682 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# nanosoc ADP validation\n",
+ "\n",
+ "This notebook demonstrates how to download an FPGA overlay and examine programmable logic state. \n",
+ "\n",
+ "## 1. Setting up and checking the overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, an overlay called `base` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"base.bit\")\n",
+ "```\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol = Overlay(PL.bitfile_name)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2023/4/24 19:21:45 +459963'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the overlay\n",
+ "Uncomment the #PL.ip_dict command to see the full details"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {
+ "scrolled": false
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "/home/xilinx/pynq/overlays/soclabs/design_1.bit\n",
+ "2023/4/24 19:21:45 +459963\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(PL.bitfile_name)\n",
+ "print(PL.timestamp)\n",
+ "\n",
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Interrogate the HWH database for interface addresses"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "ADPIO stream interface: 0x43c00000\n",
+ "UART(2) interface: 0x42c00000\n"
+ ]
+ }
+ ],
+ "source": [
+ "ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']\n",
+ "print(\"ADPIO stream interface: \",hex(ADP_address))\n",
+ "UART2_address = PL.ip_dict['cmsdk_socket/axi_uartlite_0']['phys_addr']\n",
+ "print(\"UART(2) interface: \",hex(UART2_address))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Set up interface functions for ADP"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "from pynq import MMIO\n",
+ "import time\n",
+ "from time import sleep, time\n",
+ "\n",
+ "# HARDWARE CONSTANTS\n",
+ "RX_FIFO = 0x00\n",
+ "TX_FIFO = 0x04\n",
+ "# Status Reg\n",
+ "STAT_REG = 0x08\n",
+ "RX_VALID = 0\n",
+ "RX_FULL = 1\n",
+ "TX_EMPTY = 2\n",
+ "TX_FULL = 3\n",
+ "IS_INTR = 4\n",
+ "\n",
+ "# Ctrl Reg\n",
+ "CTRL_REG = 0x0C\n",
+ "RST_TX = 0\n",
+ "RST_RX = 1\n",
+ "INTR_EN = 4\n",
+ "\n",
+ "class ADPIO:\n",
+ " def __init__(self, address):\n",
+ " # Setup axi core\n",
+ " self.uart = MMIO(address, 0x10000, debug=False)\n",
+ " self.address = address\n",
+ "\n",
+ " def setupCtrlReg(self):\n",
+ "# # Reset FIFOs, disable interrupts\n",
+ "# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)\n",
+ "# sleep(1)\n",
+ " self.uart.write(CTRL_REG, 0)\n",
+ " sleep(1)\n",
+ "\n",
+ " def monitorModeEnter(self):\n",
+ " self.uart.write(TX_FIFO, 0x1b)\n",
+ "\n",
+ " def monitorModeExit(self):\n",
+ " self.uart.write(TX_FIFO, 0x04)\n",
+ "\n",
+ " def wbyte(self, b, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL):\n",
+ " pass\n",
+ " self.uart.write_reg(TX_FIFO,int(b))\n",
+ " return\n",
+ "\n",
+ " def read(self, count, timeout=1):\n",
+ " # status = currentStatus(uart) bad idea\n",
+ " buf = \"\"\n",
+ " stop_time = time() + timeout\n",
+ " for i in range(count):\n",
+ " # Wait till RX fifo has valid data, stop waiting if timeoutpasses\n",
+ " while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):\n",
+ " pass\n",
+ " if time() >= stop_time:\n",
+ " break\n",
+ " buf += chr(self.uart.read(RX_FIFO))\n",
+ " return buf\n",
+ " \n",
+ " def write(self, buf, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " stop_time = time() + timeout\n",
+ " wr_count = 0\n",
+ " for i in buf:\n",
+ " # Wait while TX FIFO is Full, stop waiting if timeout passes\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):\n",
+ " pass\n",
+ " # Check timeout\n",
+ " if time() > stop_time:\n",
+ " wr_count = -1\n",
+ " break\n",
+ " self.uart.write(TX_FIFO, ord(i))\n",
+ " wr_count += 1\n",
+ " return wr_count\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Inspect the ADP banner after reset (0x50CLAB03 expected)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ " 0x50c1ab04\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp = ADPIO(ADP_address)\n",
+ "# Setup AXI UART register\n",
+ "adp.setupCtrlReg()\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Enter ADP monitor mode ('ESC' char)\n",
+ "And check the ']' prompt appears"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Also check the UART2 RX channel for any boot message"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "''"
+ ]
+ },
+ "execution_count": 9,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "uart = ADPIO(UART2_address)\n",
+ "# Setup AXI UART register\n",
+ "uart.setupCtrlReg()\n",
+ "uart.read(50)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Test 'binary' file upload to memory:\n",
+ "set base address with 'A <hex_address>'\n",
+ "Calculate transfer length in words , padding out final bytes to word boundary\n",
+ "Use the 'U <hex_word_count>' Up-load command (and newline) floolowed by binary file byte-stream\n",
+ "After hex_word_count transfers the ADP prompt is generated and transfer is complete"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 11,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "file size in bytes is 7192\n",
+ "U 0x1C18\n",
+ "\n",
+ "7192\n",
+ "0\n",
+ "?\n",
+ "]U 0x00001C18\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "import os\n",
+ "file_name= \"arm_tests/aes128_tests.bin\"\n",
+ "file_stats= os.stat(file_name)\n",
+ "file_len_in_bytes = file_stats.st_size\n",
+ "print(f'file size in bytes is {file_len_in_bytes}')\n",
+ "bytecount_hex=hex(file_len_in_bytes)\n",
+ "print(f'file size in bytes is {bytecount_hex}')\n",
+ "print(f'U '+bytecount_hex+'\\n')\n",
+ "adp.write('A 0x20000000\\n')\n",
+ "adp.write('U '+bytecount_hex+'\\n')\n",
+ "count = file_len_in_bytes\n",
+ "print(count)\n",
+ "with open(file_name, mode='rb') as file:\n",
+ " while (count>0) :\n",
+ " b=file.read(1)\n",
+ " adp.wbyte(ord(b))\n",
+ " count-=1\n",
+ "print(count)\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 12,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x20000000\n",
+ "\r",
+ "]R 0x30001ca0\n",
+ "\r",
+ "R 0x00001149\n",
+ "\r",
+ "R 0x00001151\n",
+ "\r",
+ "R 0x00001153\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00001155\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00001157\n",
+ "\r",
+ "R 0x00001159\n",
+ "\r",
+ "R 0x00000cf3\n",
+ "\r",
+ "R 0x00000d17\n",
+ "\r",
+ "R 0x00000d3b\n",
+ "\r",
+ "R 0x00000d5f\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x00000cb1\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0xf802f000\n",
+ "\r",
+ "R 0xf842f000\n",
+ "\r",
+ "R 0xc830a00c\n",
+ "\r",
+ "R 0x18243808\n",
+ "\r",
+ "R 0x46a2182d\n",
+ "\r",
+ "R 0x46ab1e67\n",
+ "\r",
+ "R 0x465d4654\n",
+ "\r",
+ "R 0xd10142ac\n",
+ "\r",
+ "R 0xf834f000\n",
+ "\r",
+ "R 0x3e0f467e\n",
+ "\r",
+ "R 0x46b6cc0f\n",
+ "\r",
+ "R 0x42332601\n",
+ "\r",
+ "R 0x1afbd000\n",
+ "\r",
+ "R 0x46ab46a2\n",
+ "\r",
+ "R 0x47184333\n",
+ "\r",
+ "R 0x00001938\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x20000000\\n')\n",
+ "adp.write('R 40\\n')\n",
+ "print(adp.read(10000))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Soft reset to enter the downloaded code"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 13,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "C 0x00000200\n",
+ "\r",
+ "] 0x50c1ab04\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "soclabs AES128v1\n",
+ "AES128 test program\n",
+ " AES128 ID: aes128 0.01\n",
+ "AES128 SW (memcpy) tests...\n",
+ " AES128 reference pattern test\n",
+ " AES128 input/output bypass test\n",
+ " AES128 encrypt test\n",
+ " AES128 decrypt test\n",
+ " AES128 logic toggle test\n",
+ " AES128 input/output pattern test\n",
+ " AES128 pattern encrypt test\n",
+ " AES128 pattern decrypt test\n",
+ "AES128 DMA tests...\n",
+ " AES128 dma input/output bypass test\n",
+ " ++ DMA_DONE IRQ count = 2\n",
+ " AES128 dma encrypt test\n",
+ " AES128 dma decrypt test\n",
+ " ++ DMA_DONE IRQ count = 6\n",
+ " AES128 dma unaligned pattern test\n",
+ " AES128 dma input/output pattern test\n",
+ " AES128 dma pattern encrypt test\n",
+ " AES128 dma pattern decrypt test\n",
+ " ++ DMA_DONE IRQ count = 14\n",
+ "Data retrieved from the AES is: aes128 0.01\n",
+ "Data expected from the AES is: soclabs AES128v1\n",
+ "** AES TEST PASSED **\n",
+ "\u0004\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('C 0x200\\n')\n",
+ "adp.write('C 0x201\\n')\n",
+ "print(adp.read(10000))"
+ ]
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-ADPtest.ipynb b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-ADPtest.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..8d000a3dbe36d61a466f5a08c27024291f9fa407
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-ADPtest.ipynb
@@ -0,0 +1,924 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# nanosoc ADP io test\n",
+ "\n",
+ "This notebook demonstrates how to download an FPGA overlay and examine programmable logic state. \n",
+ "\n",
+ "## 1. Setting up and checking the overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, an overlay called `base` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"base.bit\")\n",
+ "```\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol = Overlay(PL.bitfile_name)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2023/3/17 12:2:13 +667853'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the overlay\n",
+ "Uncomment the #PL.ip_dict command to see the full details"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {
+ "scrolled": false
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "/home/xilinx/pynq/overlays/soclabs/design_1.bit\n",
+ "2023/3/17 12:2:13 +667853\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(PL.bitfile_name)\n",
+ "print(PL.timestamp)\n",
+ "\n",
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Interrogate the HWH database for interface addresses"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "ADPIO stream interface: 0x80020000\n",
+ "UART(2) interface: 0x80060000\n"
+ ]
+ }
+ ],
+ "source": [
+ "ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']\n",
+ "print(\"ADPIO stream interface: \",hex(ADP_address))\n",
+ "UART2_address = PL.ip_dict['cmsdk_socket/axi_uartlite_0']['phys_addr']\n",
+ "print(\"UART(2) interface: \",hex(UART2_address))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Set up interface functions for ADP"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "from pynq import MMIO\n",
+ "import time\n",
+ "from time import sleep, time\n",
+ "\n",
+ "# HARDWARE CONSTANTS\n",
+ "RX_FIFO = 0x00\n",
+ "TX_FIFO = 0x04\n",
+ "# Status Reg\n",
+ "STAT_REG = 0x08\n",
+ "RX_VALID = 0\n",
+ "RX_FULL = 1\n",
+ "TX_EMPTY = 2\n",
+ "TX_FULL = 3\n",
+ "IS_INTR = 4\n",
+ "\n",
+ "# Ctrl Reg\n",
+ "CTRL_REG = 0x0C\n",
+ "RST_TX = 0\n",
+ "RST_RX = 1\n",
+ "INTR_EN = 4\n",
+ "\n",
+ "class ADPIO:\n",
+ " def __init__(self, address):\n",
+ " # Setup axi core\n",
+ " self.uart = MMIO(address, 0x10000, debug=False)\n",
+ " self.address = address\n",
+ "\n",
+ " def setupCtrlReg(self):\n",
+ "# # Reset FIFOs, disable interrupts\n",
+ "# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)\n",
+ "# sleep(1)\n",
+ " self.uart.write(CTRL_REG, 0)\n",
+ " sleep(1)\n",
+ "\n",
+ " def monitorModeEnter(self):\n",
+ " self.uart.write(TX_FIFO, 0x1b)\n",
+ "\n",
+ " def monitorModeExit(self):\n",
+ " self.uart.write(TX_FIFO, 0x04)\n",
+ "\n",
+ " def read(self, count, timeout=1):\n",
+ " # status = currentStatus(uart) bad idea\n",
+ " buf = \"\"\n",
+ " stop_time = time() + timeout\n",
+ " for i in range(count):\n",
+ " # Wait till RX fifo has valid data, stop waiting if timeoutpasses\n",
+ " while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):\n",
+ " pass\n",
+ " if time() >= stop_time:\n",
+ " break\n",
+ " buf += chr(self.uart.read(RX_FIFO))\n",
+ " return buf\n",
+ " \n",
+ " def write(self, buf, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " stop_time = time() + timeout\n",
+ " wr_count = 0\n",
+ " for i in buf:\n",
+ " # Wait while TX FIFO is Full, stop waiting if timeout passes\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):\n",
+ " pass\n",
+ " # Check timeout\n",
+ " if time() > stop_time:\n",
+ " wr_count = -1\n",
+ " break\n",
+ " self.uart.write(TX_FIFO, ord(i))\n",
+ " wr_count += 1\n",
+ " return wr_count\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Inspect the ADP banner after reset (0x50CLAB03 expected)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ " 0x50c1ab03\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp = ADPIO(ADP_address)\n",
+ "# Setup AXI UART register\n",
+ "adp.setupCtrlReg()\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Enter ADP monitor mode ('ESC' char)\n",
+ "And check the ']' prompt appears"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Also check the UART2 RX channel for any boot message"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "''"
+ ]
+ },
+ "execution_count": 9,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "uart = ADPIO(UART2_address)\n",
+ "# Setup AXI UART register\n",
+ "uart.setupCtrlReg()\n",
+ "uart.read(50)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Demonstrate basic ADP console functionality\n",
+ "\"A\" command with no parameter simply prints current Address pointer\n",
+ "\n",
+ "Here, check adp Address pointer resets to zero"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A\\n')\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Do a sequence of (4) auto-incrementing 32-bit reads from ROM1 space\n",
+ "\n",
+ " * \"A hexparam\" sets adddress pointer\n",
+ " * \"R hexparam\" performs number of 32-bit reads auto-incementing address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 11,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "\r",
+ "]R 0x30000368\n",
+ "\r",
+ "R 0x10000335\n",
+ "\r",
+ "R 0x1000033d\n",
+ "\r",
+ "R 0x1000033f\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x10000000\\nR 4\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 12,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x05f5e100\n",
+ "\r",
+ "]R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR\\nR \\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Write patterns to RAM3 base\n",
+ "\n",
+ " * \"W hexparam\" writes 32-bit data and auto-increments address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 13,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]W!0x11111111\n",
+ "\r",
+ "]W!0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Read back the patterns from RAM3"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 14,
+ "metadata": {
+ "scrolled": true
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x05f5e100\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR 3\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Next try writes to map with bus errors\n",
+ "\n",
+ " get a \"!\" warning on faulting accesses\n",
+ " \n",
+ "(0x5xxxxxxx address range is illegal and faults in nanosoc address map)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 15,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]W!0x11111111\n",
+ "\r",
+ "]W!0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 16,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]R!0x00000000\n",
+ "\r",
+ "R!0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nR 2\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Poll bus address (no auto-incrment)\n",
+ "\n",
+ " * \"M hexparam\" sets up MASK pattern to use\n",
+ " * \"V hexparam\" sets up VALUE of masked pattern to match\n",
+ " * \"P hexparam\" Poll command reads from address and tests <param> times\n",
+ "\n",
+ " * match when (mem[A] & M) == \"V\"\n",
+ "\n",
+ "Run a poll cammand (indicated '!' for failure to match), followed by a poll with match (and returns the number of poll iteration until matched)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 17,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x00000000\n",
+ "]P!0x00004000\n",
+ "]\n",
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x30000000\n",
+ "]P 0x00000001\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 10000000\\nM 0xF0000000\\nV 0\\nP 4000\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 10000000\\nM\\nV 30000000\\nP 2000\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Fill command - set a pattern value from current base address pointer\n",
+ "\n",
+ " * \"V hexparam\" sets up VALUE of data pattern to write\n",
+ " * \"F hexparam\" Fill command writes <param> number of 32-bit words\n"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 18,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "\r",
+ "]V 0x87654321\n",
+ "\r",
+ "]F 0x00000400\n",
+ "\r",
+ "]A 0x90001000\n",
+ "\r",
+ "]W!0xffffffff\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 90000000\\nV 0x87654321\\nF 400\\nA\\nW FFFFFFFF\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 19,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "]R 0x87654321\n",
+ "R 0x87654321\n",
+ "R 0x87654321\n",
+ "]\n",
+ "A 0x90000ffc\n",
+ "]R 0x87654321\n",
+ "R 0x00000000\n",
+ "R 0x00000000\n",
+ "]?\n",
+ "]A 0x90001008\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x90000000\\nR 3\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 0x90000FFC\\nr 0003\\n\\nA\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 20,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "S!0x00000031\n",
+ "\r",
+ "]?\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('S 0x31\\n\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 21,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeExit()\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "\n",
+ "## ol.download()\n",
+ "ol.timestamp\n",
+ "ol.reset()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ip_info = {'trace_cntrl':\"ft1248tb_i/ila_0\"}\n",
+ "class pynq.logictools.trace_analyzer.TraceAnalyzer(ip_info)\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "gpio_0.register_map\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.timestamp\n",
+ "\n",
+ "PL.ip_dict\n",
+ "\n",
+ "leds_address = PL.ip_dict['led_4bits']['phys_addr']\n",
+ " \n",
+ "from pynq import MMIO\n",
+ "mmio_buttons = MMIO(0xa0000000, 16)\n",
+ "help (mmio_buttons)\n",
+ "\n",
+ "#print(hex(mmio_buttons))\n",
+ "#print(hex(mmio_buttons.read(0)))\n",
+ "\n",
+ "hex(pl.ip_dict[\"axi_gpio_1\"][\"phys_addr\"])\n",
+ "\n",
+ "\n",
+ "#buttons_address = ssc_dpram.ip_dict['push_button_4bits']['phys_addr']\n",
+ "#switches_address = ssc_dpram.ip_dict['dip_switch_4bits']['phys_addr']\n",
+ "#leds_address = ssc_dpram.ip_dict['led_4bitss']['phys_addr']"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..991e408815402687db3dd0161b9d9454c36fc95d
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz104/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb
@@ -0,0 +1,924 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# nanosoc ADP io test\n",
+ "\n",
+ "This notebook demonstrates how to download an FPGA overlay and examine programmable logic state. \n",
+ "\n",
+ "## 1. Setting up and checking the overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, an overlay called `base` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"base.bit\")\n",
+ "```\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol = Overlay(PL.bitfile_name)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2023/3/15 14:49:29 +450152'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the overlay\n",
+ "Uncomment the #PL.ip_dict command to see the full details"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {
+ "scrolled": false
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "/home/xilinx/pynq/overlays/soclabs/design_1.bit\n",
+ "2023/3/15 14:49:29 +450152\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(PL.bitfile_name)\n",
+ "print(PL.timestamp)\n",
+ "\n",
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Interrogate the HWH database for interface addresses"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "ADPIO stream interface: 0x80020000\n",
+ "UART(2) interface: 0x80060000\n"
+ ]
+ }
+ ],
+ "source": [
+ "ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']\n",
+ "print(\"ADPIO stream interface: \",hex(ADP_address))\n",
+ "UART2_address = PL.ip_dict['cmsdk_socket/axi_uartlite_0']['phys_addr']\n",
+ "print(\"UART(2) interface: \",hex(UART2_address))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Set up interface functions for ADP"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "from pynq import MMIO\n",
+ "import time\n",
+ "from time import sleep, time\n",
+ "\n",
+ "# HARDWARE CONSTANTS\n",
+ "RX_FIFO = 0x00\n",
+ "TX_FIFO = 0x04\n",
+ "# Status Reg\n",
+ "STAT_REG = 0x08\n",
+ "RX_VALID = 0\n",
+ "RX_FULL = 1\n",
+ "TX_EMPTY = 2\n",
+ "TX_FULL = 3\n",
+ "IS_INTR = 4\n",
+ "\n",
+ "# Ctrl Reg\n",
+ "CTRL_REG = 0x0C\n",
+ "RST_TX = 0\n",
+ "RST_RX = 1\n",
+ "INTR_EN = 4\n",
+ "\n",
+ "class ADPIO:\n",
+ " def __init__(self, address):\n",
+ " # Setup axi core\n",
+ " self.uart = MMIO(address, 0x10000, debug=False)\n",
+ " self.address = address\n",
+ "\n",
+ " def setupCtrlReg(self):\n",
+ "# # Reset FIFOs, disable interrupts\n",
+ "# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)\n",
+ "# sleep(1)\n",
+ " self.uart.write(CTRL_REG, 0)\n",
+ " sleep(1)\n",
+ "\n",
+ " def monitorModeEnter(self):\n",
+ " self.uart.write(TX_FIFO, 0x1b)\n",
+ "\n",
+ " def monitorModeExit(self):\n",
+ " self.uart.write(TX_FIFO, 0x04)\n",
+ "\n",
+ " def read(self, count, timeout=1):\n",
+ " # status = currentStatus(uart) bad idea\n",
+ " buf = \"\"\n",
+ " stop_time = time() + timeout\n",
+ " for i in range(count):\n",
+ " # Wait till RX fifo has valid data, stop waiting if timeoutpasses\n",
+ " while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):\n",
+ " pass\n",
+ " if time() >= stop_time:\n",
+ " break\n",
+ " buf += chr(self.uart.read(RX_FIFO))\n",
+ " return buf\n",
+ " \n",
+ " def write(self, buf, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " stop_time = time() + timeout\n",
+ " wr_count = 0\n",
+ " for i in buf:\n",
+ " # Wait while TX FIFO is Full, stop waiting if timeout passes\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):\n",
+ " pass\n",
+ " # Check timeout\n",
+ " if time() > stop_time:\n",
+ " wr_count = -1\n",
+ " break\n",
+ " self.uart.write(TX_FIFO, ord(i))\n",
+ " wr_count += 1\n",
+ " return wr_count\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Inspect the ADP banner after reset (0x50CLAB03 expected)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ " 0x50c1ab03\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp = ADPIO(ADP_address)\n",
+ "# Setup AXI UART register\n",
+ "adp.setupCtrlReg()\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Enter ADP monitor mode ('ESC' char)\n",
+ "And check the ']' prompt appears"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Also check the UART2 RX channel for any boot message"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "''"
+ ]
+ },
+ "execution_count": 9,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "uart = ADPIO(UART2_address)\n",
+ "# Setup AXI UART register\n",
+ "uart.setupCtrlReg()\n",
+ "uart.read(50)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Demonstrate basic ADP console functionality\n",
+ "\"A\" command with no parameter simply prints current Address pointer\n",
+ "\n",
+ "Here, check adp Address pointer resets to zero"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A\\n')\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Do a sequence of (4) auto-incrementing 32-bit reads from ROM1 space\n",
+ "\n",
+ " * \"A hexparam\" sets adddress pointer\n",
+ " * \"R hexparam\" performs number of 32-bit reads auto-incementing address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 11,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "\r",
+ "]R 0x30000368\n",
+ "\r",
+ "R 0x10000335\n",
+ "\r",
+ "R 0x1000033d\n",
+ "\r",
+ "R 0x1000033f\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x10000000\\nR 4\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 12,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x05f5e100\n",
+ "\r",
+ "]R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR\\nR \\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Write patterns to RAM3 base\n",
+ "\n",
+ " * \"W hexparam\" writes 32-bit data and auto-increments address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 13,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]W 0x11111111\n",
+ "\r",
+ "]W 0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Read back the patterns from RAM3"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 14,
+ "metadata": {
+ "scrolled": true
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x11111111\n",
+ "\r",
+ "R 0x22222222\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR 3\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Next try writes to map with bus errors\n",
+ "\n",
+ " get a \"!\" warning on faulting accesses\n",
+ " \n",
+ "(0x5xxxxxxx address range is illegal and faults in nanosoc address map)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 15,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]W!0x11111111\n",
+ "\r",
+ "]W!0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 16,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]R!0x00000000\n",
+ "\r",
+ "R!0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nR 2\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Poll bus address (no auto-incrment)\n",
+ "\n",
+ " * \"M hexparam\" sets up MASK pattern to use\n",
+ " * \"V hexparam\" sets up VALUE of masked pattern to match\n",
+ " * \"P hexparam\" Poll command reads from address and tests <param> times\n",
+ "\n",
+ " * match when (mem[A] & M) == \"V\"\n",
+ "\n",
+ "Run a poll cammand (indicated '!' for failure to match), followed by a poll with match (and returns the number of poll iteration until matched)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 17,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x00000000\n",
+ "]P!0x00004000\n",
+ "]\n",
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x30000000\n",
+ "]P 0x00000001\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 10000000\\nM 0xF0000000\\nV 0\\nP 4000\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 10000000\\nM\\nV 30000000\\nP 2000\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Fill command - set a pattern value from current base address pointer\n",
+ "\n",
+ " * \"V hexparam\" sets up VALUE of data pattern to write\n",
+ " * \"F hexparam\" Fill command writes <param> number of 32-bit words\n"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 18,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "\r",
+ "]V 0x87654321\n",
+ "\r",
+ "]F 0x00000400\n",
+ "\r",
+ "]A 0x90001000\n",
+ "\r",
+ "]W 0xffffffff\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 90000000\\nV 0x87654321\\nF 400\\nA\\nW FFFFFFFF\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 19,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "]R 0x87654321\n",
+ "R 0x87654321\n",
+ "R 0x87654321\n",
+ "]\n",
+ "A 0x90000ffc\n",
+ "]R 0x87654321\n",
+ "R 0xffffffff\n",
+ "R 0x00000000\n",
+ "]?\n",
+ "]A 0x90001008\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x90000000\\nR 3\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 0x90000FFC\\nr 0003\\n\\nA\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 20,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "S!0x00000031\n",
+ "\r",
+ "]?\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('S 0x31\\n\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 21,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeExit()\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "\n",
+ "## ol.download()\n",
+ "ol.timestamp\n",
+ "ol.reset()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ip_info = {'trace_cntrl':\"ft1248tb_i/ila_0\"}\n",
+ "class pynq.logictools.trace_analyzer.TraceAnalyzer(ip_info)\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "gpio_0.register_map\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.timestamp\n",
+ "\n",
+ "PL.ip_dict\n",
+ "\n",
+ "leds_address = PL.ip_dict['led_4bits']['phys_addr']\n",
+ " \n",
+ "from pynq import MMIO\n",
+ "mmio_buttons = MMIO(0xa0000000, 16)\n",
+ "help (mmio_buttons)\n",
+ "\n",
+ "#print(hex(mmio_buttons))\n",
+ "#print(hex(mmio_buttons.read(0)))\n",
+ "\n",
+ "hex(pl.ip_dict[\"axi_gpio_1\"][\"phys_addr\"])\n",
+ "\n",
+ "\n",
+ "#buttons_address = ssc_dpram.ip_dict['push_button_4bits']['phys_addr']\n",
+ "#switches_address = ssc_dpram.ip_dict['dip_switch_4bits']['phys_addr']\n",
+ "#leds_address = ssc_dpram.ip_dict['led_4bitss']['phys_addr']"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
new file mode 100755
index 0000000000000000000000000000000000000000..4da3b3396dff1710d66e943d7e91337483665b50
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/driver/uartlite.py
@@ -0,0 +1,88 @@
+from time import sleep, time
+from pynq import MMIO
+
+RX_FIFO = 0x00
+TX_FIFO = 0x04
+
+#Status Reg
+STAT_REG = 0x08
+RX_VALID = 0
+RX_FULL = 1
+TX_EMPTY = 2
+TX_FULL = 3
+IS_INTR = 4
+OVERRUN_ERR = 5
+FRAME_ERR = 6
+PARITY_ERR =7
+
+#Ctrl Reg
+CTRL_REG = 0x0C
+RST_TX = 0
+RST_RX = 1
+INTR_EN = 4
+
+class UartLite:
+ def __init__(self, address):
+ # Setup axi core
+ self.uart = MMIO(address,0x10000, debug=False)
+ self.address = address
+
+ def getBit(self,num,pos):
+ return (num&1<<pos)>>pos
+
+ def setupCtrlReg(self):
+ # Reset FIFOs, disable interrupts
+ self.uart.write(CTRL_REG, 1<<RST_TX | 1<<RST_RX)
+ sleep(0.0)
+ self.uart.write(CTRL_REG,0)
+ sleep(0.0)
+
+ def currentStatus(self):
+ """Returns object that specifies current status of axi core"""
+ status = self.uart.read(STAT_REG)
+ return {'RX_VALID':self.getBit(status,RX_VALID),
+ 'RX_FULL':self.getBit(status, RX_FULL),
+ 'TX_EMPTY':self.getBit(status, TX_EMPTY),
+ 'TX_FULL':self.getBit(status, TX_FULL),
+ 'IS_INTR':self.getBit(status, IS_INTR),
+ 'OVERRUN_ERR':self.getBit(status, OVERRUN_ERR),
+ 'FRAME_ERR':self.getBit(status, FRAME_ERR),
+ 'PARITY_ERR':self.getBit(status, PARITY_ERR)}
+
+ def read(self, count, timeout = 1):
+ buf = ""
+ stop_time = time() + timeout
+ for i in range(count):
+ # Wait till RX fifo has valid data, skip if timeout exceeded
+ while (not (self.uart.read(STAT_REG) & 1<<RX_VALID)) and (time()<stop_time):
+ pass
+ if time()>=stop_time:
+ break
+ buf += chr(self.uart.read(RX_FIFO))
+ return buf
+
+ def write(self, buf, timeout = 10):
+ """
+ buf: iterable
+
+ """
+ stop_time = time() + timeout
+ wr_count = 0
+ for i in buf:
+ #Wait while TX FIFO is Full, stop waiting if timeout passes
+ while (self.uart.read(STAT_REG) & 1<<TX_FULL) and (time()<stop_time):
+ pass
+ # Check timeout
+ if time()>stop_time:
+ break
+ self.uart.write(TX_FIFO, ord(i))
+ wr_count += 1
+ return wr_count
+
+ def readLine(self):
+ buf = self.read(1)
+ if len(buf) ==0:
+ return ""
+ while '\n' not in buf:
+ buf += self.read(1)
+ return buf
\ No newline at end of file
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-ADP-validation.ipynb b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-ADP-validation.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..5026330001cae9fd0d4bc810e1a45dffa18f7efc
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-ADP-validation.ipynb
@@ -0,0 +1,682 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# nanosoc ADP validation\n",
+ "\n",
+ "This notebook demonstrates how to download an FPGA overlay and examine programmable logic state. \n",
+ "\n",
+ "## 1. Setting up and checking the overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, an overlay called `base` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"base.bit\")\n",
+ "```\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol = Overlay(PL.bitfile_name)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2023/4/24 19:21:45 +459963'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the overlay\n",
+ "Uncomment the #PL.ip_dict command to see the full details"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {
+ "scrolled": false
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "/home/xilinx/pynq/overlays/soclabs/design_1.bit\n",
+ "2023/4/24 19:21:45 +459963\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(PL.bitfile_name)\n",
+ "print(PL.timestamp)\n",
+ "\n",
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Interrogate the HWH database for interface addresses"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "ADPIO stream interface: 0x43c00000\n",
+ "UART(2) interface: 0x42c00000\n"
+ ]
+ }
+ ],
+ "source": [
+ "ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']\n",
+ "print(\"ADPIO stream interface: \",hex(ADP_address))\n",
+ "UART2_address = PL.ip_dict['cmsdk_socket/axi_uartlite_0']['phys_addr']\n",
+ "print(\"UART(2) interface: \",hex(UART2_address))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Set up interface functions for ADP"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "from pynq import MMIO\n",
+ "import time\n",
+ "from time import sleep, time\n",
+ "\n",
+ "# HARDWARE CONSTANTS\n",
+ "RX_FIFO = 0x00\n",
+ "TX_FIFO = 0x04\n",
+ "# Status Reg\n",
+ "STAT_REG = 0x08\n",
+ "RX_VALID = 0\n",
+ "RX_FULL = 1\n",
+ "TX_EMPTY = 2\n",
+ "TX_FULL = 3\n",
+ "IS_INTR = 4\n",
+ "\n",
+ "# Ctrl Reg\n",
+ "CTRL_REG = 0x0C\n",
+ "RST_TX = 0\n",
+ "RST_RX = 1\n",
+ "INTR_EN = 4\n",
+ "\n",
+ "class ADPIO:\n",
+ " def __init__(self, address):\n",
+ " # Setup axi core\n",
+ " self.uart = MMIO(address, 0x10000, debug=False)\n",
+ " self.address = address\n",
+ "\n",
+ " def setupCtrlReg(self):\n",
+ "# # Reset FIFOs, disable interrupts\n",
+ "# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)\n",
+ "# sleep(1)\n",
+ " self.uart.write(CTRL_REG, 0)\n",
+ " sleep(1)\n",
+ "\n",
+ " def monitorModeEnter(self):\n",
+ " self.uart.write(TX_FIFO, 0x1b)\n",
+ "\n",
+ " def monitorModeExit(self):\n",
+ " self.uart.write(TX_FIFO, 0x04)\n",
+ "\n",
+ " def wbyte(self, b, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL):\n",
+ " pass\n",
+ " self.uart.write_reg(TX_FIFO,int(b))\n",
+ " return\n",
+ "\n",
+ " def read(self, count, timeout=1):\n",
+ " # status = currentStatus(uart) bad idea\n",
+ " buf = \"\"\n",
+ " stop_time = time() + timeout\n",
+ " for i in range(count):\n",
+ " # Wait till RX fifo has valid data, stop waiting if timeoutpasses\n",
+ " while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):\n",
+ " pass\n",
+ " if time() >= stop_time:\n",
+ " break\n",
+ " buf += chr(self.uart.read(RX_FIFO))\n",
+ " return buf\n",
+ " \n",
+ " def write(self, buf, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " stop_time = time() + timeout\n",
+ " wr_count = 0\n",
+ " for i in buf:\n",
+ " # Wait while TX FIFO is Full, stop waiting if timeout passes\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):\n",
+ " pass\n",
+ " # Check timeout\n",
+ " if time() > stop_time:\n",
+ " wr_count = -1\n",
+ " break\n",
+ " self.uart.write(TX_FIFO, ord(i))\n",
+ " wr_count += 1\n",
+ " return wr_count\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Inspect the ADP banner after reset (0x50CLAB03 expected)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ " 0x50c1ab04\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp = ADPIO(ADP_address)\n",
+ "# Setup AXI UART register\n",
+ "adp.setupCtrlReg()\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Enter ADP monitor mode ('ESC' char)\n",
+ "And check the ']' prompt appears"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Also check the UART2 RX channel for any boot message"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "''"
+ ]
+ },
+ "execution_count": 9,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "uart = ADPIO(UART2_address)\n",
+ "# Setup AXI UART register\n",
+ "uart.setupCtrlReg()\n",
+ "uart.read(50)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Test 'binary' file upload to memory:\n",
+ "set base address with 'A <hex_address>'\n",
+ "Calculate transfer length in words , padding out final bytes to word boundary\n",
+ "Use the 'U <hex_word_count>' Up-load command (and newline) floolowed by binary file byte-stream\n",
+ "After hex_word_count transfers the ADP prompt is generated and transfer is complete"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 11,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "file size in bytes is 7192\n",
+ "U 0x1C18\n",
+ "\n",
+ "7192\n",
+ "0\n",
+ "?\n",
+ "]U 0x00001C18\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "import os\n",
+ "file_name= \"arm_tests/aes128_tests.bin\"\n",
+ "file_stats= os.stat(file_name)\n",
+ "file_len_in_bytes = file_stats.st_size\n",
+ "print(f'file size in bytes is {file_len_in_bytes}')\n",
+ "bytecount_hex=hex(file_len_in_bytes)\n",
+ "print(f'file size in bytes is {bytecount_hex}')\n",
+ "print(f'U '+bytecount_hex+'\\n')\n",
+ "adp.write('A 0x20000000\\n')\n",
+ "adp.write('U '+bytecount_hex+'\\n')\n",
+ "count = file_len_in_bytes\n",
+ "print(count)\n",
+ "with open(file_name, mode='rb') as file:\n",
+ " while (count>0) :\n",
+ " b=file.read(1)\n",
+ " adp.wbyte(ord(b))\n",
+ " count-=1\n",
+ "print(count)\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 12,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x20000000\n",
+ "\r",
+ "]R 0x30001ca0\n",
+ "\r",
+ "R 0x00001149\n",
+ "\r",
+ "R 0x00001151\n",
+ "\r",
+ "R 0x00001153\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00001155\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00001157\n",
+ "\r",
+ "R 0x00001159\n",
+ "\r",
+ "R 0x00000cf3\n",
+ "\r",
+ "R 0x00000d17\n",
+ "\r",
+ "R 0x00000d3b\n",
+ "\r",
+ "R 0x00000d5f\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x00000cb1\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0x0000115b\n",
+ "\r",
+ "R 0xf802f000\n",
+ "\r",
+ "R 0xf842f000\n",
+ "\r",
+ "R 0xc830a00c\n",
+ "\r",
+ "R 0x18243808\n",
+ "\r",
+ "R 0x46a2182d\n",
+ "\r",
+ "R 0x46ab1e67\n",
+ "\r",
+ "R 0x465d4654\n",
+ "\r",
+ "R 0xd10142ac\n",
+ "\r",
+ "R 0xf834f000\n",
+ "\r",
+ "R 0x3e0f467e\n",
+ "\r",
+ "R 0x46b6cc0f\n",
+ "\r",
+ "R 0x42332601\n",
+ "\r",
+ "R 0x1afbd000\n",
+ "\r",
+ "R 0x46ab46a2\n",
+ "\r",
+ "R 0x47184333\n",
+ "\r",
+ "R 0x00001938\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x20000000\\n')\n",
+ "adp.write('R 40\\n')\n",
+ "print(adp.read(10000))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Soft reset to enter the downloaded code"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 13,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "C 0x00000200\n",
+ "\r",
+ "] 0x50c1ab04\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "soclabs AES128v1\n",
+ "AES128 test program\n",
+ " AES128 ID: aes128 0.01\n",
+ "AES128 SW (memcpy) tests...\n",
+ " AES128 reference pattern test\n",
+ " AES128 input/output bypass test\n",
+ " AES128 encrypt test\n",
+ " AES128 decrypt test\n",
+ " AES128 logic toggle test\n",
+ " AES128 input/output pattern test\n",
+ " AES128 pattern encrypt test\n",
+ " AES128 pattern decrypt test\n",
+ "AES128 DMA tests...\n",
+ " AES128 dma input/output bypass test\n",
+ " ++ DMA_DONE IRQ count = 2\n",
+ " AES128 dma encrypt test\n",
+ " AES128 dma decrypt test\n",
+ " ++ DMA_DONE IRQ count = 6\n",
+ " AES128 dma unaligned pattern test\n",
+ " AES128 dma input/output pattern test\n",
+ " AES128 dma pattern encrypt test\n",
+ " AES128 dma pattern decrypt test\n",
+ " ++ DMA_DONE IRQ count = 14\n",
+ "Data retrieved from the AES is: aes128 0.01\n",
+ "Data expected from the AES is: soclabs AES128v1\n",
+ "** AES TEST PASSED **\n",
+ "\u0004\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('C 0x200\\n')\n",
+ "adp.write('C 0x201\\n')\n",
+ "print(adp.read(10000))"
+ ]
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-ADPtest.ipynb b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-ADPtest.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..8d000a3dbe36d61a466f5a08c27024291f9fa407
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-ADPtest.ipynb
@@ -0,0 +1,924 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# nanosoc ADP io test\n",
+ "\n",
+ "This notebook demonstrates how to download an FPGA overlay and examine programmable logic state. \n",
+ "\n",
+ "## 1. Setting up and checking the overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, an overlay called `base` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"base.bit\")\n",
+ "```\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol = Overlay(PL.bitfile_name)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2023/3/17 12:2:13 +667853'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the overlay\n",
+ "Uncomment the #PL.ip_dict command to see the full details"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {
+ "scrolled": false
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "/home/xilinx/pynq/overlays/soclabs/design_1.bit\n",
+ "2023/3/17 12:2:13 +667853\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(PL.bitfile_name)\n",
+ "print(PL.timestamp)\n",
+ "\n",
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Interrogate the HWH database for interface addresses"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "ADPIO stream interface: 0x80020000\n",
+ "UART(2) interface: 0x80060000\n"
+ ]
+ }
+ ],
+ "source": [
+ "ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']\n",
+ "print(\"ADPIO stream interface: \",hex(ADP_address))\n",
+ "UART2_address = PL.ip_dict['cmsdk_socket/axi_uartlite_0']['phys_addr']\n",
+ "print(\"UART(2) interface: \",hex(UART2_address))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Set up interface functions for ADP"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "from pynq import MMIO\n",
+ "import time\n",
+ "from time import sleep, time\n",
+ "\n",
+ "# HARDWARE CONSTANTS\n",
+ "RX_FIFO = 0x00\n",
+ "TX_FIFO = 0x04\n",
+ "# Status Reg\n",
+ "STAT_REG = 0x08\n",
+ "RX_VALID = 0\n",
+ "RX_FULL = 1\n",
+ "TX_EMPTY = 2\n",
+ "TX_FULL = 3\n",
+ "IS_INTR = 4\n",
+ "\n",
+ "# Ctrl Reg\n",
+ "CTRL_REG = 0x0C\n",
+ "RST_TX = 0\n",
+ "RST_RX = 1\n",
+ "INTR_EN = 4\n",
+ "\n",
+ "class ADPIO:\n",
+ " def __init__(self, address):\n",
+ " # Setup axi core\n",
+ " self.uart = MMIO(address, 0x10000, debug=False)\n",
+ " self.address = address\n",
+ "\n",
+ " def setupCtrlReg(self):\n",
+ "# # Reset FIFOs, disable interrupts\n",
+ "# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)\n",
+ "# sleep(1)\n",
+ " self.uart.write(CTRL_REG, 0)\n",
+ " sleep(1)\n",
+ "\n",
+ " def monitorModeEnter(self):\n",
+ " self.uart.write(TX_FIFO, 0x1b)\n",
+ "\n",
+ " def monitorModeExit(self):\n",
+ " self.uart.write(TX_FIFO, 0x04)\n",
+ "\n",
+ " def read(self, count, timeout=1):\n",
+ " # status = currentStatus(uart) bad idea\n",
+ " buf = \"\"\n",
+ " stop_time = time() + timeout\n",
+ " for i in range(count):\n",
+ " # Wait till RX fifo has valid data, stop waiting if timeoutpasses\n",
+ " while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):\n",
+ " pass\n",
+ " if time() >= stop_time:\n",
+ " break\n",
+ " buf += chr(self.uart.read(RX_FIFO))\n",
+ " return buf\n",
+ " \n",
+ " def write(self, buf, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " stop_time = time() + timeout\n",
+ " wr_count = 0\n",
+ " for i in buf:\n",
+ " # Wait while TX FIFO is Full, stop waiting if timeout passes\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):\n",
+ " pass\n",
+ " # Check timeout\n",
+ " if time() > stop_time:\n",
+ " wr_count = -1\n",
+ " break\n",
+ " self.uart.write(TX_FIFO, ord(i))\n",
+ " wr_count += 1\n",
+ " return wr_count\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Inspect the ADP banner after reset (0x50CLAB03 expected)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ " 0x50c1ab03\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp = ADPIO(ADP_address)\n",
+ "# Setup AXI UART register\n",
+ "adp.setupCtrlReg()\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Enter ADP monitor mode ('ESC' char)\n",
+ "And check the ']' prompt appears"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Also check the UART2 RX channel for any boot message"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "''"
+ ]
+ },
+ "execution_count": 9,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "uart = ADPIO(UART2_address)\n",
+ "# Setup AXI UART register\n",
+ "uart.setupCtrlReg()\n",
+ "uart.read(50)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Demonstrate basic ADP console functionality\n",
+ "\"A\" command with no parameter simply prints current Address pointer\n",
+ "\n",
+ "Here, check adp Address pointer resets to zero"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A\\n')\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Do a sequence of (4) auto-incrementing 32-bit reads from ROM1 space\n",
+ "\n",
+ " * \"A hexparam\" sets adddress pointer\n",
+ " * \"R hexparam\" performs number of 32-bit reads auto-incementing address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 11,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "\r",
+ "]R 0x30000368\n",
+ "\r",
+ "R 0x10000335\n",
+ "\r",
+ "R 0x1000033d\n",
+ "\r",
+ "R 0x1000033f\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x10000000\\nR 4\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 12,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x05f5e100\n",
+ "\r",
+ "]R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR\\nR \\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Write patterns to RAM3 base\n",
+ "\n",
+ " * \"W hexparam\" writes 32-bit data and auto-increments address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 13,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]W!0x11111111\n",
+ "\r",
+ "]W!0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Read back the patterns from RAM3"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 14,
+ "metadata": {
+ "scrolled": true
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x05f5e100\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR 3\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Next try writes to map with bus errors\n",
+ "\n",
+ " get a \"!\" warning on faulting accesses\n",
+ " \n",
+ "(0x5xxxxxxx address range is illegal and faults in nanosoc address map)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 15,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]W!0x11111111\n",
+ "\r",
+ "]W!0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 16,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]R!0x00000000\n",
+ "\r",
+ "R!0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nR 2\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Poll bus address (no auto-incrment)\n",
+ "\n",
+ " * \"M hexparam\" sets up MASK pattern to use\n",
+ " * \"V hexparam\" sets up VALUE of masked pattern to match\n",
+ " * \"P hexparam\" Poll command reads from address and tests <param> times\n",
+ "\n",
+ " * match when (mem[A] & M) == \"V\"\n",
+ "\n",
+ "Run a poll cammand (indicated '!' for failure to match), followed by a poll with match (and returns the number of poll iteration until matched)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 17,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x00000000\n",
+ "]P!0x00004000\n",
+ "]\n",
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x30000000\n",
+ "]P 0x00000001\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 10000000\\nM 0xF0000000\\nV 0\\nP 4000\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 10000000\\nM\\nV 30000000\\nP 2000\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Fill command - set a pattern value from current base address pointer\n",
+ "\n",
+ " * \"V hexparam\" sets up VALUE of data pattern to write\n",
+ " * \"F hexparam\" Fill command writes <param> number of 32-bit words\n"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 18,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "\r",
+ "]V 0x87654321\n",
+ "\r",
+ "]F 0x00000400\n",
+ "\r",
+ "]A 0x90001000\n",
+ "\r",
+ "]W!0xffffffff\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 90000000\\nV 0x87654321\\nF 400\\nA\\nW FFFFFFFF\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 19,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "]R 0x87654321\n",
+ "R 0x87654321\n",
+ "R 0x87654321\n",
+ "]\n",
+ "A 0x90000ffc\n",
+ "]R 0x87654321\n",
+ "R 0x00000000\n",
+ "R 0x00000000\n",
+ "]?\n",
+ "]A 0x90001008\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x90000000\\nR 3\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 0x90000FFC\\nr 0003\\n\\nA\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 20,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "S!0x00000031\n",
+ "\r",
+ "]?\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('S 0x31\\n\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 21,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeExit()\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "\n",
+ "## ol.download()\n",
+ "ol.timestamp\n",
+ "ol.reset()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ip_info = {'trace_cntrl':\"ft1248tb_i/ila_0\"}\n",
+ "class pynq.logictools.trace_analyzer.TraceAnalyzer(ip_info)\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "gpio_0.register_map\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.timestamp\n",
+ "\n",
+ "PL.ip_dict\n",
+ "\n",
+ "leds_address = PL.ip_dict['led_4bits']['phys_addr']\n",
+ " \n",
+ "from pynq import MMIO\n",
+ "mmio_buttons = MMIO(0xa0000000, 16)\n",
+ "help (mmio_buttons)\n",
+ "\n",
+ "#print(hex(mmio_buttons))\n",
+ "#print(hex(mmio_buttons.read(0)))\n",
+ "\n",
+ "hex(pl.ip_dict[\"axi_gpio_1\"][\"phys_addr\"])\n",
+ "\n",
+ "\n",
+ "#buttons_address = ssc_dpram.ip_dict['push_button_4bits']['phys_addr']\n",
+ "#switches_address = ssc_dpram.ip_dict['dip_switch_4bits']['phys_addr']\n",
+ "#leds_address = ssc_dpram.ip_dict['led_4bitss']['phys_addr']"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb
new file mode 100755
index 0000000000000000000000000000000000000000..991e408815402687db3dd0161b9d9454c36fc95d
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/pynq_export/pz2/jupyter_notebooks/soclabs/nanosoc-iotest.ipynb
@@ -0,0 +1,924 @@
+{
+ "cells": [
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "# nanosoc ADP io test\n",
+ "\n",
+ "This notebook demonstrates how to download an FPGA overlay and examine programmable logic state. \n",
+ "\n",
+ "## 1. Setting up and checking the overlay\n",
+ "With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.\n",
+ "\n",
+ "* A bitstream file (\\*.bit).\n",
+ "* An hwh file (\\*.hwh).\n",
+ "* A python class (\\*.py).\n",
+ "\n",
+ "For example, an overlay called `base` can be loaded by:\n",
+ "```python\n",
+ "from pynq.overlays.base import BaseOverlay\n",
+ "overlay = BaseOverlay(\"base.bit\")\n",
+ "```\n",
+ "Users can also use the absolute file path of the bitstream to instantiate the overlay.\n",
+ "\n",
+ "In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 1,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ },
+ {
+ "data": {
+ "application/javascript": [
+ "\n",
+ "try {\n",
+ "require(['notebook/js/codecell'], function(codecell) {\n",
+ " codecell.CodeCell.options_default.highlight_modes[\n",
+ " 'magic_text/x-csrc'] = {'reg':[/^%%pybind11/]};\n",
+ " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n",
+ " Jupyter.notebook.get_cells().map(function(cell){\n",
+ " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n",
+ " });\n",
+ "});\n",
+ "} catch (e) {};\n"
+ ]
+ },
+ "metadata": {},
+ "output_type": "display_data"
+ }
+ ],
+ "source": [
+ "import os, warnings\n",
+ "from pynq import PL\n",
+ "from pynq import Overlay\n",
+ "\n",
+ "ol = Overlay(\"/home/xilinx/pynq/overlays/soclabs/design_1.bit\")\n",
+ "\n",
+ "if not os.path.exists(PL.bitfile_name):\n",
+ " warnings.warn('There is no overlay loaded after boot.', UserWarning)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "**Note**: If you see a warning message in the above cell, it means that no overlay\n",
+ "has been loaded after boot, hence the PL server is not aware of the \n",
+ "current status of the PL. In that case you won't be able to run this notebook\n",
+ "until you manually load an overlay at least once using:\n",
+ "\n",
+ "```python\n",
+ "from pynq import Overlay\n",
+ "ol = Overlay('your_overlay.bit')\n",
+ "```\n",
+ "\n",
+ "If you do not see any warning message, you can safely proceed."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 2,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol = Overlay(PL.bitfile_name)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Now we can check the download timestamp for this overlay."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 3,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "'2023/3/15 14:49:29 +450152'"
+ ]
+ },
+ "execution_count": 3,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "ol.download()\n",
+ "ol.timestamp"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the overlay\n",
+ "Uncomment the #PL.ip_dict command to see the full details"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 4,
+ "metadata": {
+ "scrolled": false
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "/home/xilinx/pynq/overlays/soclabs/design_1.bit\n",
+ "2023/3/15 14:49:29 +450152\n"
+ ]
+ }
+ ],
+ "source": [
+ "print(PL.bitfile_name)\n",
+ "print(PL.timestamp)\n",
+ "\n",
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Interrogate the HWH database for interface addresses"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 5,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "ADPIO stream interface: 0x80020000\n",
+ "UART(2) interface: 0x80060000\n"
+ ]
+ }
+ ],
+ "source": [
+ "ADP_address = PL.ip_dict['cmsdk_socket/axi_stream_io_0']['phys_addr']\n",
+ "print(\"ADPIO stream interface: \",hex(ADP_address))\n",
+ "UART2_address = PL.ip_dict['cmsdk_socket/axi_uartlite_0']['phys_addr']\n",
+ "print(\"UART(2) interface: \",hex(UART2_address))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Set up interface functions for ADP"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 6,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "from pynq import Overlay\n",
+ "from pynq import MMIO\n",
+ "import time\n",
+ "from time import sleep, time\n",
+ "\n",
+ "# HARDWARE CONSTANTS\n",
+ "RX_FIFO = 0x00\n",
+ "TX_FIFO = 0x04\n",
+ "# Status Reg\n",
+ "STAT_REG = 0x08\n",
+ "RX_VALID = 0\n",
+ "RX_FULL = 1\n",
+ "TX_EMPTY = 2\n",
+ "TX_FULL = 3\n",
+ "IS_INTR = 4\n",
+ "\n",
+ "# Ctrl Reg\n",
+ "CTRL_REG = 0x0C\n",
+ "RST_TX = 0\n",
+ "RST_RX = 1\n",
+ "INTR_EN = 4\n",
+ "\n",
+ "class ADPIO:\n",
+ " def __init__(self, address):\n",
+ " # Setup axi core\n",
+ " self.uart = MMIO(address, 0x10000, debug=False)\n",
+ " self.address = address\n",
+ "\n",
+ " def setupCtrlReg(self):\n",
+ "# # Reset FIFOs, disable interrupts\n",
+ "# self.uart.write(CTRL_REG, 1 << RST_TX | 1 << RST_RX)\n",
+ "# sleep(1)\n",
+ " self.uart.write(CTRL_REG, 0)\n",
+ " sleep(1)\n",
+ "\n",
+ " def monitorModeEnter(self):\n",
+ " self.uart.write(TX_FIFO, 0x1b)\n",
+ "\n",
+ " def monitorModeExit(self):\n",
+ " self.uart.write(TX_FIFO, 0x04)\n",
+ "\n",
+ " def read(self, count, timeout=1):\n",
+ " # status = currentStatus(uart) bad idea\n",
+ " buf = \"\"\n",
+ " stop_time = time() + timeout\n",
+ " for i in range(count):\n",
+ " # Wait till RX fifo has valid data, stop waiting if timeoutpasses\n",
+ " while (not (self.uart.read(STAT_REG) & 1 << RX_VALID)) and (time() < stop_time):\n",
+ " pass\n",
+ " if time() >= stop_time:\n",
+ " break\n",
+ " buf += chr(self.uart.read(RX_FIFO))\n",
+ " return buf\n",
+ " \n",
+ " def write(self, buf, timeout=1):\n",
+ " # Write bytes via UART\n",
+ " stop_time = time() + timeout\n",
+ " wr_count = 0\n",
+ " for i in buf:\n",
+ " # Wait while TX FIFO is Full, stop waiting if timeout passes\n",
+ " while (self.uart.read(STAT_REG) & 1 << TX_FULL) and (time() < stop_time):\n",
+ " pass\n",
+ " # Check timeout\n",
+ " if time() > stop_time:\n",
+ " wr_count = -1\n",
+ " break\n",
+ " self.uart.write(TX_FIFO, ord(i))\n",
+ " wr_count += 1\n",
+ " return wr_count\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Inspect the ADP banner after reset (0x50CLAB03 expected)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 7,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ " 0x50c1ab03\n",
+ "\r\n",
+ "\n",
+ "\n",
+ "SOCLABS: ARM Cortex-M0 nanosoc\n",
+ "** Remap->RAM2\n",
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp = ADPIO(ADP_address)\n",
+ "# Setup AXI UART register\n",
+ "adp.setupCtrlReg()\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Enter ADP monitor mode ('ESC' char)\n",
+ "And check the ']' prompt appears"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 8,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeEnter()\n",
+ "print(adp.read(4))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Also check the UART2 RX channel for any boot message"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 9,
+ "metadata": {},
+ "outputs": [
+ {
+ "data": {
+ "text/plain": [
+ "''"
+ ]
+ },
+ "execution_count": 9,
+ "metadata": {},
+ "output_type": "execute_result"
+ }
+ ],
+ "source": [
+ "uart = ADPIO(UART2_address)\n",
+ "# Setup AXI UART register\n",
+ "uart.setupCtrlReg()\n",
+ "uart.read(50)"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "### Demonstrate basic ADP console functionality\n",
+ "\"A\" command with no parameter simply prints current Address pointer\n",
+ "\n",
+ "Here, check adp Address pointer resets to zero"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 10,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A\\n')\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Do a sequence of (4) auto-incrementing 32-bit reads from ROM1 space\n",
+ "\n",
+ " * \"A hexparam\" sets adddress pointer\n",
+ " * \"R hexparam\" performs number of 32-bit reads auto-incementing address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 11,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "\r",
+ "]R 0x30000368\n",
+ "\r",
+ "R 0x10000335\n",
+ "\r",
+ "R 0x1000033d\n",
+ "\r",
+ "R 0x1000033f\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x10000000\\nR 4\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 12,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x05f5e100\n",
+ "\r",
+ "]R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR\\nR \\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Write patterns to RAM3 base\n",
+ "\n",
+ " * \"W hexparam\" writes 32-bit data and auto-increments address pointer"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 13,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]W 0x11111111\n",
+ "\r",
+ "]W 0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Read back the patterns from RAM3"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 14,
+ "metadata": {
+ "scrolled": true
+ },
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x30000000\n",
+ "\r",
+ "]R 0x11111111\n",
+ "\r",
+ "R 0x22222222\n",
+ "\r",
+ "R 0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x30000000\\nR 3\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Next try writes to map with bus errors\n",
+ "\n",
+ " get a \"!\" warning on faulting accesses\n",
+ " \n",
+ "(0x5xxxxxxx address range is illegal and faults in nanosoc address map)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 15,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]W!0x11111111\n",
+ "\r",
+ "]W!0x22222222\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nW 0x11111111\\nW22222222\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 16,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x50000000\n",
+ "\r",
+ "]R!0x00000000\n",
+ "\r",
+ "R!0x00000000\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x50000000\\nR 2\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Poll bus address (no auto-incrment)\n",
+ "\n",
+ " * \"M hexparam\" sets up MASK pattern to use\n",
+ " * \"V hexparam\" sets up VALUE of masked pattern to match\n",
+ " * \"P hexparam\" Poll command reads from address and tests <param> times\n",
+ "\n",
+ " * match when (mem[A] & M) == \"V\"\n",
+ "\n",
+ "Run a poll cammand (indicated '!' for failure to match), followed by a poll with match (and returns the number of poll iteration until matched)"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 17,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x00000000\n",
+ "]P!0x00004000\n",
+ "]\n",
+ "A 0x10000000\n",
+ "]M 0xf0000000\n",
+ "]V 0x30000000\n",
+ "]P 0x00000001\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 10000000\\nM 0xF0000000\\nV 0\\nP 4000\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 10000000\\nM\\nV 30000000\\nP 2000\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Fill command - set a pattern value from current base address pointer\n",
+ "\n",
+ " * \"V hexparam\" sets up VALUE of data pattern to write\n",
+ " * \"F hexparam\" Fill command writes <param> number of 32-bit words\n"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 18,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "\r",
+ "]V 0x87654321\n",
+ "\r",
+ "]F 0x00000400\n",
+ "\r",
+ "]A 0x90001000\n",
+ "\r",
+ "]W 0xffffffff\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 90000000\\nV 0x87654321\\nF 400\\nA\\nW FFFFFFFF\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 19,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "A 0x90000000\n",
+ "]R 0x87654321\n",
+ "R 0x87654321\n",
+ "R 0x87654321\n",
+ "]\n",
+ "A 0x90000ffc\n",
+ "]R 0x87654321\n",
+ "R 0xffffffff\n",
+ "R 0x00000000\n",
+ "]?\n",
+ "]A 0x90001008\n",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('A 0x90000000\\nR 3\\n')\n",
+ "print(adp.read(100))\n",
+ "adp.write('A 0x90000FFC\\nr 0003\\n\\nA\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 20,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "S!0x00000031\n",
+ "\r",
+ "]?\n",
+ "\r",
+ "]\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.write('S 0x31\\n\\n')\n",
+ "print(adp.read(100))"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": 21,
+ "metadata": {},
+ "outputs": [
+ {
+ "name": "stdout",
+ "output_type": "stream",
+ "text": [
+ "\n"
+ ]
+ }
+ ],
+ "source": [
+ "adp.monitorModeExit()\n",
+ "print(adp.read(100))\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "\n",
+ "## ol.download()\n",
+ "ol.timestamp\n",
+ "ol.reset()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ip_info = {'trace_cntrl':\"ft1248tb_i/ila_0\"}\n",
+ "class pynq.logictools.trace_analyzer.TraceAnalyzer(ip_info)\n",
+ "\n",
+ " "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "#PL.ip_dict"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "gpio_0.register_map\n"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 2. Examining the PL state\n",
+ "\n",
+ "While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). \n",
+ "\n",
+ "This bitstream state is held in the singleton class, PL, and is available for user queries."
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.bitfile_name"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "PL.timestamp\n",
+ "\n",
+ "PL.ip_dict\n",
+ "\n",
+ "leds_address = PL.ip_dict['led_4bits']['phys_addr']\n",
+ " \n",
+ "from pynq import MMIO\n",
+ "mmio_buttons = MMIO(0xa0000000, 16)\n",
+ "help (mmio_buttons)\n",
+ "\n",
+ "#print(hex(mmio_buttons))\n",
+ "#print(hex(mmio_buttons.read(0)))\n",
+ "\n",
+ "hex(pl.ip_dict[\"axi_gpio_1\"][\"phys_addr\"])\n",
+ "\n",
+ "\n",
+ "#buttons_address = ssc_dpram.ip_dict['push_button_4bits']['phys_addr']\n",
+ "#switches_address = ssc_dpram.ip_dict['dip_switch_4bits']['phys_addr']\n",
+ "#leds_address = ssc_dpram.ip_dict['led_4bitss']['phys_addr']"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "ol.is_loaded()"
+ ]
+ },
+ {
+ "cell_type": "markdown",
+ "metadata": {},
+ "source": [
+ "## 3. Overlay downloading overhead\n",
+ "\n",
+ "Finally, using Python, we can see the bitstream download time over 50 downloads. "
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": [
+ "import time\n",
+ "import matplotlib.pyplot as plt\n",
+ "\n",
+ "length = 50\n",
+ "time_log = []\n",
+ "for i in range(length):\n",
+ " start = time.time()\n",
+ " ol.download()\n",
+ " end = time.time()\n",
+ " time_log.append((end-start)*1000)\n",
+ "\n",
+ "%matplotlib inline\n",
+ "plt.plot(range(length), time_log, 'ro')\n",
+ "plt.title('Bitstream loading time (ms)')\n",
+ "plt.axis([0, length, 0, 1000])\n",
+ "plt.show()"
+ ]
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ },
+ {
+ "cell_type": "code",
+ "execution_count": null,
+ "metadata": {},
+ "outputs": [],
+ "source": []
+ }
+ ],
+ "metadata": {
+ "kernelspec": {
+ "display_name": "Python 3",
+ "language": "python",
+ "name": "python3"
+ },
+ "language_info": {
+ "codemirror_mode": {
+ "name": "ipython",
+ "version": 3
+ },
+ "file_extension": ".py",
+ "mimetype": "text/x-python",
+ "name": "python",
+ "nbconvert_exporter": "python",
+ "pygments_lexer": "ipython3",
+ "version": "3.6.5"
+ }
+ },
+ "nbformat": 4,
+ "nbformat_minor": 1
+}
diff --git a/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_arm_mps3.tcl b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_arm_mps3.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..40985d1a435e4ee5a60c221818f0e01673199eee
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_arm_mps3.tcl
@@ -0,0 +1,114 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_pynq_zcu104.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright � 2022, SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_pynq_zcu104.tcl
+# vivado -mode gui -source scripts/build_mcu_fpga_pynq_zcu104.tcl
+
+# for ARM MPS3 as target
+set xilinx_part xcku115-flvb1760-1-c
+set project project_arm_mps3
+set importDir target_fpga_arm_mps3
+set ipDir ./ip_repo
+set mcuDir ./vivado/built_mcu_fpga/MCULIB
+set outDir ./MPS_FPGA_build
+
+#
+# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
+#
+source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ $ipDir\
+ $mcuDir\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize $ipDir] [file normalize $mcuDir]" $obj
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+#
+# STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+#
+# using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $importDir/design_1_wrapper.v
+source $importDir/design_1.tcl
+create_root_design ""
+
+add_files -norecurse -scan_for_includes {../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v ../verilog/pl230_defs.v}
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property is_global_include true [get_files ../verilog/pl230_defs.v]
+
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files ../verilog/pl230_defs.v]
+
+add_files $importDir/fpga_pinmap.xdc
+
+set_property top design_1_wrapper [current_fileset]
+
+#
+# STEP#3: save in Project mode to complete flow
+#
+
+save_project_as $project ./$project -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+#
+# STEP#4: synthesize project
+#
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+#
+# STEP#5: place and route project
+#
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+#
+# STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+#
+
+write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+exec unzip -u -o $project/design_1.xsa -d $project/export
+exec mkdir -p $outDir
+exec cp -p $project/export/design_1.bit $outDir
+exec cp -p $project/export/design_1.hwh $outDir
+
+#exec rm -Rf vivado/
+
+exit 1
diff --git a/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_batch.tcl b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_batch.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..789b2768f6c87b947825adc38fc1c4d65a518fd3
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_batch.tcl
@@ -0,0 +1,122 @@
+# build_mcu_fpga_batch.tcl
+#
+# cmsdk_mcu sample design
+# A Vivado script that demonstrates a very simple RTL-to-bitstream non-project batch flow
+#
+# NOTE: typical usage would be "vivado -mode tcl -source build_mcu_fpga_batch.tcl"
+#
+# STEP#0: define output directory area.
+#
+
+##if {$argc < 1} {
+#puts "target_fpga arg must be \[ac701 \| arm_mps3 \| pynz_z2 \| zcu104\]"
+#}
+#set target [lindex $argv 0]
+#puts "target requested : $target"
+#set target_dir target_fpga
+#append target_dir $target
+#puts "target directory : $target_dir"
+
+set outputDir ./vivado/built_mcu_fpga
+file mkdir $outputDir
+#
+# STEP#1: setup design sources and constraints
+#
+
+# local search path for configurations
+set search_path ../verilog
+
+set cortexm0_vlog ../../../../../../arm-AAA-ip/Cortex-M0/AT510-BU-00000-r0p0-03rel3/logical
+source scripts/rtl_source_cm0.tcl
+
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
+read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
+read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
+
+# Arm unmodified CMSDK RTL
+set cmsdk_vlog ../../../../../../arm-AAA-ip/Corstone-101_Foundation_IP/BP210-BU-00000-r1p1-00rel0
+source scripts/rtl_source_cmsdk.tcl
+
+set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
+###read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+###read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
+###read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
+
+# ADP, FT1248 and streamio IP
+source scripts/rtl_source_soclabs_ip.tcl
+
+# FPGA-specific pads
+source scripts/rtl_source_fpga_ip.tcl
+
+# soclabs modified mcu system
+set soc_vlog ../verilog
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_default_slave.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix_lite.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_AhbMatrix.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_Arbiter.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MasterInput.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_adp.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_cpu.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma2.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_MatrixDecode_dma.v
+read_verilog $soc_vlog/gen_ahb_busmatrix/verilog/built/soclabs_4x7_AhbMatrix/soclabs_4x7_SlaveOutput.v
+read_verilog $soc_vlog/ahb_bootrom.v
+read_verilog $soc_vlog/bootrom.v
+read_verilog $soc_vlog/cmsdk_ahb_cs_rom_table.v
+read_verilog $soc_vlog/cmsdk_apb_usrt.v
+read_verilog $soc_vlog/cmsdk_clkreset.v
+read_verilog $soc_vlog/cmsdk_ft1248x1_adpio.v
+read_verilog $soc_vlog/cmsdk_mcu_clkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_pin_mux.v
+read_verilog $soc_vlog/cmsdk_mcu_stclkctrl.v
+read_verilog $soc_vlog/cmsdk_mcu_sysctrl.v
+read_verilog $soc_vlog/cmsdk_uart_capture.v
+read_verilog $soc_vlog/nanosoc_ahb_sys_decode.v
+read_verilog $soc_vlog/nanosoc_chip_pads.v
+read_verilog $soc_vlog/nanosoc_chip.v
+read_verilog $soc_vlog/nanosoc_cpu.v
+read_verilog $soc_vlog/nanosoc_sys_ahb_decode.v
+read_verilog $soc_vlog/nanosoc_sysio.v
+
+
+# FPGA specific timing constraints
+read_xdc target_fpga/fpga_timing.xdc
+
+# FPGA board specific pin constraints
+read_xdc target_fpga/fpga_pinmap.xdc
+
+#
+# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+source target_fpga/fpga_synth.tcl
+
+write_checkpoint -force $outputDir/post_synth
+report_timing_summary -file $outputDir/post_synth_timing_summary.rpt
+report_power -file $outputDir/post_synth_power.rpt
+#
+# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
+#
+opt_design
+place_design
+phys_opt_design
+write_checkpoint -force $outputDir/post_place
+report_timing_summary -file $outputDir/post_place_timing_summary.rpt
+#
+# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
+#
+route_design
+write_checkpoint -force $outputDir/post_route
+report_timing_summary -file $outputDir/post_route_timing_summary.rpt
+report_timing -sort_by group -max_paths 100 -path_type summary -file $outputDir/post_route_timing.rpt
+report_clock_utilization -file $outputDir/clock_util.rpt
+report_utilization -file $outputDir/post_route_util.rpt
+report_power -file $outputDir/post_route_power.rpt
+report_drc -file $outputDir/post_imp_drc.rpt
+write_verilog -force $outputDir/cmsdk_mcu_impl_netlist.v
+write_xdc -no_fixed_only -force $outputDir/cmsdk_mcu_impl.xdc
+#
+# STEP#5: generate a bitstream
+#
+write_bitstream -force $outputDir/cmsdk_mcu.bit
diff --git a/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_ip.tcl b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..3a246c661ddf107d47fe5fdbd74646adb3dab9f3
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_ip.tcl
@@ -0,0 +1,146 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_ip.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright (C) 2022-3 SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#0: define output directory area.
+#
+
+set outputDir ./built_mcu_fpga
+file mkdir $outputDir
+
+#
+# STEP#1: setup design sources and constraints
+#
+# requrire paths setup
+# $AAA_ip
+# $fpga_impl
+# $nanosoc_sys
+
+# local search path for configurations
+set search_path $nanosoc_sys/src/verilog
+
+set cortexm0_vlog $AAA_ip/Cortex-M0/logical
+source $fpga_impl/scripts/rtl_source_cm0.tcl
+
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_integration/verilog ]
+read_verilog [ glob $cortexm0_vlog/cortexm0_integration/verilog/*.v ]
+read_verilog [ glob $cortexm0_vlog/models/cells/*.v ]
+
+# Arm unmodified CMSDK RTL
+set cmsdk_vlog $AAA_ip/Corstone-101
+source $fpga_impl/scripts/rtl_source_cmsdk.tcl
+
+set search_path [ concat $search_path $cmsdk_vlog/logical/models/memories ]
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_memory_models_defs.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_rom.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_ahb_ram.v
+read_verilog $cmsdk_vlog/logical/models/memories/cmsdk_fpga_sram.v
+
+# configured Arm DMA-PL230 RTL (include ../verilog/pl230_defs.v for local configuration, not the distribution, already on search path)
+set search_path [ concat $search_path $proj_dir/system/defines/pl230 ]
+set dma230_vlog $AAA_ip/DMA-230/src/PL230-BU-00000-r0p0-02rel2/shared/logical/pl230_udma/verilog
+set search_path [ concat $search_path $dma230_vlog ]
+source $fpga_impl/scripts/rtl_source_dma230.tcl
+
+set search_path [ concat $search_path $nanosoc_sys/src/verilog ]
+
+# ADP, FT1248 and streamio IP
+set iplib_vlog $nanosoc_sys/test_io/verilog
+source $fpga_impl/scripts/rtl_source_soclabs_ip.tcl
+
+## FPGA-specific pads
+#source $fpga_impl/scripts/rtl_source_fpga_ip.tcl
+
+# soclabs modified mcu system
+
+read_verilog $proj_dir/system/src/bootrom/verilog/bootrom.v
+
+set soc_vlog $nanosoc_sys/src
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_default_slave.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix_lite.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_busmatrix.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_arbiter.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_inititator_input.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_adp.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_cpu.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma2.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_matrix_decode_dma.v
+read_verilog $soc_vlog/nanosoc_ahb_busmatrix/verilog/nanosoc_ahb32_4x7_busmatrix/nanosoc_ahb32_4x7_target_output.v
+read_verilog $soc_vlog/verilog/nanosoc_ahb_bootrom.v
+read_verilog $soc_vlog/verilog/nanosoc_apb_subsystem.v
+read_verilog $soc_vlog/verilog/nanosoc_ahb_cs_rom_table.v
+read_verilog $soc_vlog/verilog/nanosoc_apb_usrt.v
+##read_verilog $soc_vlog/cmsdk_clkreset.v
+#read_verilog ../test_io/verilog/nanosoc_ft1248x1_adpio.v
+read_verilog $soc_vlog/verilog/nanosoc_mcu_clkctrl.v
+read_verilog $soc_vlog/verilog/nanosoc_mcu_pin_mux.v
+read_verilog $soc_vlog/verilog/nanosoc_mcu_stclkctrl.v
+read_verilog $soc_vlog/verilog/nanosoc_mcu_sysctrl.v
+##read_verilog $soc_vlog/cmsdk_uart_capture.v
+read_verilog $soc_vlog/verilog/nanosoc_cpu.v
+read_verilog $soc_vlog/verilog/nanosoc_sys_ahb_decode.v
+read_verilog $soc_vlog/verilog/nanosoc_sysio.v
+###read_verilog ../aes/src/nanosoc_acc_wrapper.v
+read_verilog $soc_vlog/verilog/nanosoc_chip.v
+###read_verilog $soc_vlog/verilog/nanosoc_chip_pads.v
+###set search_path [ concat $search_path ../../../secworks-aes/src/rtl ]
+###read_verilog ../aes/src/soclabs_ahb_aes128_ctrl.v
+
+#set_property generic {NANOSOC_EXPANSION_REGION=1} [current_fileset]
+###set_property verilog_define {NANOSOC_EXPANSION_REGION=1} [current_fileset]
+###set_property top nanosoc_chip [current_fileset]
+
+# FPGA specific timing constraints
+#read_xdc target_fpga/fpga_timing.xdc
+
+## FPGA board specific pin constraints
+#read_xdc target_fpga/fpga_pinmap.xdc
+
+#
+# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+
+update_compile_order -fileset sources_1
+
+###set mculib_ip $outputDir/MCULIB
+
+ipx::package_project -root_dir $mcu_lib -vendor soclabs.org -library user -taxonomy /UserIP -import_files -set_current false -force -force_update_compile_order
+
+ipx::unload_core $mcu_lib/component.xml
+ipx::edit_ip_in_project -upgrade true -name tmp_edit_project -directory $mcu_lib $mcu_lib/component.xml
+
+update_compile_order -fileset sources_1
+set_property ipi_drc {ignore_freq_hz true} [ipx::current_core]
+ipx::merge_project_changes files [ipx::current_core]
+
+set_property core_revision 2 [ipx::current_core]
+ipx::update_source_project_archive -component [ipx::current_core]
+ipx::create_xgui_files [ipx::current_core]
+ipx::update_checksums [ipx::current_core]
+ipx::check_integrity [ipx::current_core]
+
+ipx::save_core [ipx::current_core]
+ipx::check_integrity -quiet -xrt [ipx::current_core]
+ipx::archive_core $mcu_lib/soclabs.org:user:nanosoc_chip:1.0.zip [ipx::current_core]
+ipx::move_temp_component_back -component [ipx::current_core]
+#close_project -delete
+close_project
+
+###set_property ip_repo_paths { $ip_repo $mculib_ip} [current_project]
+set_property ip_repo_paths [list $ip_repo $mcu_lib] [current_project]
+update_ip_catalog
+close_project
diff --git a/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_pynq_z2.tcl b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_pynq_z2.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..97539f4b9277ec444b86221431224e8f2ca8e923
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_pynq_z2.tcl
@@ -0,0 +1,128 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_pynq_z2.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright (C) 2022-3 SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source $SOCLABS_FPGA_IMP_PATH/scripts/build_mcu_fpga_pynq_z2.tcl
+# vivado -mode gui -source $SOCLABS_FPGA_IMP_PATH/scripts/build_mcu_fpga_pynq_z2.tcl
+
+### Design specific
+set proj_dir $::env(SOCLABS_PROJECT_DIR)
+set fpga_impl $::env(SOCLABS_FPGA_IMP_PATH)
+set AAA_ip $::env(ARM_IP_LIBRARY_PATH)/latest
+set nanosoc_sys $::env(SOCLABS_NANOSOC_TECH_DIR)/system
+
+### Target specific
+# for TUL PYNQ-Z2 as PYNQ target
+set xilinx_part xc7z020clg400-1
+set project project_pynq_z2
+set fpga_target $fpga_impl/target_fpga_pynq_z2
+set ip_repo $fpga_impl/ip_repo
+set mcu_lib ./built_mcu_fpga/MCULIB
+set pynqDir ./pynq_export/pz2/pynq/overlays/soclabs
+set exportDir /research/soclabs/pynq_export/pz2/pynq/overlays/soclabs
+#set_property BOARD_PART tul.com:pynq-z2:part0:1.1 [current_project]
+
+#
+# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
+#
+source $fpga_impl/scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ $ip_repo\
+ $mcu_lib\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize $ip_repo] [file normalize $mcu_lib]" $obj
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+#
+# STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+#
+# using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $fpga_target/design_1_wrapper.v
+source $fpga_target/design_1.tcl
+create_root_design ""
+
+set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest
+add_files -norecurse -scan_for_includes "$arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v $proj_dir/system/defines/pl230/pl230_defs.v"
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property is_global_include true [get_files $proj_dir/system/defines/pl230/pl230_defs.v]
+
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files $proj_dir/system/defines/pl230/pl230_defs.v]
+
+add_files $fpga_target/fpga_pinmap.xdc
+
+set_property top design_1_wrapper [current_fileset]
+
+#
+# STEP#3: save in Project mode to complete flow
+#
+save_project_as $project ./$project -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+#
+# STEP#4: synthesize project
+#
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+#
+# STEP#5: place and route project
+#
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+#
+# STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+#
+
+write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+exec unzip -u -o $project/design_1.xsa -d $project/export
+
+exec mkdir -p $pynqDir
+exec cp -p $project/export/design_1.bit $pynqDir
+exec cp -p $project/export/design_1.hwh $pynqDir
+#exec cp -p $project/export/design_1.bit $exportDir
+#exec cp -p $project/export/design_1.hwh $exportDir
+
+exec rm -Rf $project/design_1.xsa
+exec rm -Rf $project/export
+exec rm -Rf ./vivado/
+
+exit 1
diff --git a/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_pynq_zcu104.tcl b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_pynq_zcu104.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..d197085f17a3a38751af7b94d4c12d6fec165f1b
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/build_mcu_fpga_pynq_zcu104.tcl
@@ -0,0 +1,128 @@
+###-----------------------------------------------------------------------------
+### example: build_mcu_fpga_pynq_zcu104.tcl
+### A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
+###
+### Contributors
+###
+### David Flynn (d.w.flynn@soton.ac.uk)
+###
+### Copyright (C) 2022-3 SoC Labs (www.soclabs.org)
+###-----------------------------------------------------------------------------
+#
+# developed & tested using vivado_version 2021.1
+#
+# usage:
+# vivado -mode tcl -source $SOCLABS_FPGA_IMP_PATH/scripts/build_mcu_fpga_pynq_zcu104.tcl
+# vivado -mode gui -source $SOCLABS_FPGA_IMP_PATH/scripts/build_mcu_fpga_pynq_zcu104.tcl
+
+### Design specific
+set proj_dir $::env(SOCLABS_PROJECT_DIR)
+set fpga_impl $::env(SOCLABS_FPGA_IMP_PATH)
+set AAA_ip $::env(ARM_IP_LIBRARY_PATH)/latest
+set nanosoc_sys $::env(SOCLABS_NANOSOC_TECH_DIR)/system
+
+### Target specific
+# for Xilinx ZCU104 as PYNQ target
+set xilinx_part xczu7ev-ffvc1156-2-e
+set project project_pynq_zcu104
+set fpga_target $fpga_impl/target_fpga_zcu104
+set ip_repo $fpga_impl/ip_repo
+set mcu_lib ./built_mcu_fpga/MCULIB
+set pynqDir ./pynq_export/pz104/pynq/overlays/soclabs
+set exportDir /research/soclabs/pynq_export/pz104/pynq/overlays/soclabs
+#set_property BOARD_PART xilinx.com:zcu104:part0:1.1 [current_project]
+
+#
+# STEP#0: build the cm0sdk design (without pads) as an "IP" library component for the testbench (in MCULIB)
+#
+source $fpga_impl/scripts/build_mcu_fpga_ip.tcl
+
+#
+# STEP#1: setup design sources and constraints
+#
+set_part $xilinx_part
+set_property TARGET_LANGUAGE Verilog [current_project]
+set_property DEFAULT_LIB work [current_project]
+
+set paths [list \
+ $ip_repo\
+ $mcu_lib\
+ ]
+
+# Set IP repository paths
+set obj [get_filesets sources_1]
+if { $obj != {} } {
+ set_property "ip_repo_paths" "[file normalize $ip_repo] [file normalize $mcu_lib]" $obj
+ # Rebuild user ip_repo's index before adding any source files
+ update_ip_catalog -rebuild
+}
+
+report_ip_status
+
+#
+# STEP#2: create Block Diagram and add specific IO wrapper (and import matching pinmap.xdc)
+#
+# using script written out from GUI capture
+
+create_bd_design design_1
+
+read_verilog $fpga_target/design_1_wrapper.v
+source $fpga_target/design_1.tcl
+create_root_design ""
+
+set arm_ip_lib $::env(ARM_IP_LIBRARY_PATH)/latest
+add_files -norecurse -scan_for_includes "$arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v $proj_dir/system/defines/pl230/pl230_defs.v"
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property is_global_include true [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property is_global_include true [get_files $proj_dir/system/defines/pl230/pl230_defs.v]
+
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_dualtimers/verilog/cmsdk_apb_dualtimers_defs.v]
+set_property file_type {Verilog Header} [get_files $arm_ip_lib/Corstone-101/logical/cmsdk_apb_watchdog/verilog/cmsdk_apb_watchdog_defs.v]
+set_property file_type {Verilog Header} [get_files $proj_dir/system/defines/pl230/pl230_defs.v]
+
+add_files $fpga_target/fpga_pinmap.xdc
+
+set_property top design_1_wrapper [current_fileset]
+
+#
+# STEP#3: save in Project mode to complete flow
+#
+save_project_as $project ./$project -exclude_run_results -force
+
+update_compile_order -fileset sources_1
+
+#
+# STEP#4: synthesize project
+#
+set_property part $xilinx_part [get_runs synth_1]
+launch_runs synth_1 -jobs 8
+
+wait_on_run synth_1
+
+#
+# STEP#5: place and route project
+#
+set_property part $xilinx_part [get_runs impl_1]
+launch_runs impl_1 -to_step write_bitstream -jobs 8
+
+wait_on_run impl_1
+
+#
+# STEP#6: export design_1.bit and design_1.hwh files for PYNQ
+#
+
+write_hw_platform -fixed -include_bit -force -file $project/design_1.xsa
+
+exec unzip -u -o $project/design_1.xsa -d $project/export
+
+exec mkdir -p $pynqDir
+exec cp -p $project/export/design_1.bit $pynqDir
+exec cp -p $project/export/design_1.hwh $pynqDir
+#exec cp -p $project/export/design_1.bit $exportDir
+#exec cp -p $project/export/design_1.hwh $exportDir
+
+exec rm -Rf $project/design_1.xsa
+exec rm -Rf $project/export
+exec rm -Rf ./vivado/
+
+exit 1
diff --git a/implement/fpga/xilinx_vivado/scripts/rtl_source_cm0.tcl b/implement/fpga/xilinx_vivado/scripts/rtl_source_cm0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..b76287f3995fc4ff1584a546bf0c82dc5d4c3217
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/rtl_source_cm0.tcl
@@ -0,0 +1,17 @@
+### Cortex-M0 rtl source build
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0/verilog ]
+read_verilog [ glob $cortexm0_vlog/cortexm0/verilog/*.v ]
+set search_path [ concat $search_path $cortexm0_vlog/cortexm0_dap/verilog ]
+##read_verilog [ glob $cortexm0_vlog/cortexm0_dap/verilog/*.v ]
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_cdc.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_cdc.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap_mast_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_ap.v
+###read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_jtag_defs.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_pwr.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/cm0_dap_dp_sw.v
+read_verilog $cortexm0_vlog/cortexm0_dap/verilog/CORTEXM0DAP.v
diff --git a/implement/fpga/xilinx_vivado/scripts/rtl_source_cmsdk.tcl b/implement/fpga/xilinx_vivado/scripts/rtl_source_cmsdk.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..cd99c878a8278d9fa6b59166f4f0b2cc0e54d461
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/rtl_source_cmsdk.tcl
@@ -0,0 +1,17 @@
+### CMSDK rtl source build
+###read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/*.v ]
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_to_iop.v
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_gpio/verilog/cmsdk_ahb_gpio.v
+read_verilog $cmsdk_vlog/logical/cmsdk_iop_gpio/verilog/cmsdk_iop_gpio.v
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_timer/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_dualtimers/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_watchdog/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_uart/verilog/*.v ]
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_default_slave/verilog/cmsdk_ahb_default_slave.v
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_slave_mux/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_to_apb/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_slave_mux/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_apb_subsystem/verilog/*.v ]
+read_verilog [ glob $cmsdk_vlog/logical/cmsdk_ahb_master_mux/verilog/*.v ]
+read_verilog $cmsdk_vlog/logical/models/clkgate/cmsdk_clock_gate.v
+read_verilog $cmsdk_vlog/logical/cmsdk_ahb_to_sram/verilog/cmsdk_ahb_to_sram.v
diff --git a/implement/fpga/xilinx_vivado/scripts/rtl_source_dma230.tcl b/implement/fpga/xilinx_vivado/scripts/rtl_source_dma230.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7500b8ee58918d6f289781217ade658e04d7e4a4
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/rtl_source_dma230.tcl
@@ -0,0 +1,10 @@
+### DMA PL230 rtl source build
+
+read_verilog $proj_dir/system/defines/pl230/pl230_defs.v
+read_verilog $dma230_vlog/pl230_ahb_ctrl.v
+read_verilog $dma230_vlog/pl230_apb_regs.v
+read_verilog $dma230_vlog/pl230_dma_data.v
+read_verilog $dma230_vlog/pl230_udma.v
+read_verilog $dma230_vlog/pl230_undefs.v
+
+#+incdir+$::env(SOCLABS_PROJECT_DIR)/system/defines/pl230
diff --git a/implement/fpga/xilinx_vivado/scripts/rtl_source_fpga_ip.tcl b/implement/fpga/xilinx_vivado/scripts/rtl_source_fpga_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..376d757658bf7dc98669ac9c626075f3126f64c0
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/rtl_source_fpga_ip.tcl
@@ -0,0 +1,9 @@
+# rtl_source_fpga_ip.tcl
+#
+
+set fpgalib_vlog ../../../../../FPGALIB
+read_verilog $fpgalib_vlog/pads/verilog/PAD_INOUT8MA_NOE.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VDDIO.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VSSIO.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VDDSOC.v
+read_verilog $fpgalib_vlog/pads/verilog/PAD_VSS.v
diff --git a/implement/fpga/xilinx_vivado/scripts/rtl_source_soclabs_ip.tcl b/implement/fpga/xilinx_vivado/scripts/rtl_source_soclabs_ip.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ba5139f1457e244a3fcffe25593eb181be114e9e
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/scripts/rtl_source_soclabs_ip.tcl
@@ -0,0 +1,6 @@
+# rtl_source_soclabs_ip.tcl
+#
+
+read_verilog $iplib_vlog/nanosoc_ft1248_stream_io_v1_0.v
+read_verilog $iplib_vlog/nanosoc_adp_control_v1_0.v
+read_verilog $iplib_vlog/nanosoc_adp_manager.v
diff --git a/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_pinmap.xdc b/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..b8889af48409d7409031d5229f5949e72f9dc5ef
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_pinmap.xdc
@@ -0,0 +1,983 @@
+##################################################################################
+## ##
+## AC701 Master XDC ##
+## ##
+##################################################################################
+
+set_property CFGBVS VCCO [current_design]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+##set_property PACKAGE_PIN AB22 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN AE25 [get_ports FMC1_HPC_HA02_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA02_P]
+##set_property PACKAGE_PIN AE26 [get_ports FMC1_HPC_HA02_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA02_N]
+##set_property PACKAGE_PIN AC22 [get_ports FMC1_HPC_HA03_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA03_P]
+##set_property PACKAGE_PIN AC23 [get_ports FMC1_HPC_HA03_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA03_N]
+##set_property PACKAGE_PIN AF24 [get_ports FMC1_HPC_HA04_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA04_P]
+##set_property PACKAGE_PIN AF25 [get_ports FMC1_HPC_HA04_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA04_N]
+##set_property PACKAGE_PIN AD25 [get_ports FMC1_HPC_HA05_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA05_P]
+##set_property PACKAGE_PIN AD26 [get_ports FMC1_HPC_HA05_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA05_N]
+##set_property PACKAGE_PIN AE23 [get_ports FMC1_HPC_HA06_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA06_P]
+##set_property PACKAGE_PIN AF23 [get_ports FMC1_HPC_HA06_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA06_N]
+##set_property PACKAGE_PIN AD23 [get_ports FMC1_HPC_HA07_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA07_P]
+##set_property PACKAGE_PIN AD24 [get_ports FMC1_HPC_HA07_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA07_N]
+##set_property PACKAGE_PIN AD21 [get_ports FMC1_HPC_HA08_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA08_P]
+##set_property PACKAGE_PIN AE21 [get_ports FMC1_HPC_HA08_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA08_N]
+##set_property PACKAGE_PIN AF19 [get_ports FMC1_HPC_HA09_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA09_P]
+##set_property PACKAGE_PIN AF20 [get_ports FMC1_HPC_HA09_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA09_N]
+##set_property PACKAGE_PIN AE22 [get_ports FMC1_HPC_HA10_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA10_P]
+##set_property PACKAGE_PIN AF22 [get_ports FMC1_HPC_HA10_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA10_N]
+##set_property PACKAGE_PIN AD20 [get_ports FMC1_HPC_HA11_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_P]
+##set_property PACKAGE_PIN AE20 [get_ports FMC1_HPC_HA11_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA11_N]
+##set_property PACKAGE_PIN AB21 [get_ports FMC1_HPC_HA01_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA01_CC_P]
+##set_property PACKAGE_PIN AC21 [get_ports FMC1_HPC_HA01_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA01_CC_N]
+##set_property PACKAGE_PIN AA20 [get_ports FMC1_HPC_HA17_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA17_CC_P]
+##set_property PACKAGE_PIN AB20 [get_ports FMC1_HPC_HA17_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA17_CC_N]
+##set_property PACKAGE_PIN AA19 [get_ports FMC1_HPC_HA00_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA00_CC_P]
+##set_property PACKAGE_PIN AB19 [get_ports FMC1_HPC_HA00_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA00_CC_N]
+##set_property PACKAGE_PIN AC19 [get_ports FMC1_HPC_HA12_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_P]
+##set_property PACKAGE_PIN AD19 [get_ports FMC1_HPC_HA12_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA12_N]
+##set_property PACKAGE_PIN AC18 [get_ports FMC1_HPC_HA13_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA13_P]
+##set_property PACKAGE_PIN AD18 [get_ports FMC1_HPC_HA13_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA13_N]
+##set_property PACKAGE_PIN AE18 [get_ports FMC1_HPC_HA14_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA14_P]
+##set_property PACKAGE_PIN AF18 [get_ports FMC1_HPC_HA14_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA14_N]
+##set_property PACKAGE_PIN Y18 [get_ports FMC1_HPC_HA15_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA15_P]
+##set_property PACKAGE_PIN AA18 [get_ports FMC1_HPC_HA15_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA15_N]
+##set_property PACKAGE_PIN AE17 [get_ports FMC1_HPC_HA16_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA16_P]
+##set_property PACKAGE_PIN AF17 [get_ports FMC1_HPC_HA16_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA16_N]
+##set_property PACKAGE_PIN AA17 [get_ports FMC1_HPC_HA18_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA18_P]
+##set_property PACKAGE_PIN AB17 [get_ports FMC1_HPC_HA18_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA18_N]
+##set_property PACKAGE_PIN AC17 [get_ports FMC1_HPC_HA19_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA19_P]
+##set_property PACKAGE_PIN AD17 [get_ports FMC1_HPC_HA19_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA19_N]
+##set_property PACKAGE_PIN Y16 [get_ports FMC1_HPC_HA20_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA20_P]
+##set_property PACKAGE_PIN Y17 [get_ports FMC1_HPC_HA20_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA20_N]
+##set_property PACKAGE_PIN AB16 [get_ports FMC1_HPC_HA21_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA21_P]
+##set_property PACKAGE_PIN AC16 [get_ports FMC1_HPC_HA21_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA21_N]
+##set_property PACKAGE_PIN Y15 [get_ports FMC1_HPC_HA22_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_P]
+##set_property PACKAGE_PIN AA15 [get_ports FMC1_HPC_HA22_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA22_N]
+##set_property PACKAGE_PIN W14 [get_ports FMC1_HPC_HA23_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_P]
+##set_property PACKAGE_PIN W15 [get_ports FMC1_HPC_HA23_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_HA23_N]
+##set_property PACKAGE_PIN W16 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN U24 [get_ports HDMI_R_D21]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D21]
+##set_property PACKAGE_PIN U25 [get_ports HDMI_R_D16]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D16]
+##set_property PACKAGE_PIN U26 [get_ports HDMI_R_D11]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D11]
+##set_property PACKAGE_PIN V26 [get_ports HDMI_R_D7]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D7]
+##set_property PACKAGE_PIN W26 [get_ports HDMI_R_D8]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D8]
+##set_property PACKAGE_PIN AB26 [get_ports HDMI_R_DE]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_DE]
+##set_property PACKAGE_PIN AC26 [get_ports HDMI_R_VSYNC]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_VSYNC]
+##set_property PACKAGE_PIN W25 [get_ports HDMI_R_D9]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D9]
+##set_property PACKAGE_PIN Y26 [get_ports HDMI_R_D6]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D6]
+##set_property PACKAGE_PIN Y25 [get_ports HDMI_R_D5]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D5]
+##set_property PACKAGE_PIN AA25 [get_ports HDMI_R_D29]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D29]
+##set_property PACKAGE_PIN V24 [get_ports HDMI_R_D17]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D17]
+##set_property PACKAGE_PIN W24 [get_ports HDMI_R_D10]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D10]
+##set_property PACKAGE_PIN AA24 [get_ports HDMI_R_D4]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D4]
+##set_property PACKAGE_PIN AB25 [get_ports HDMI_R_D30]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D30]
+##set_property PACKAGE_PIN AA22 [get_ports HDMI_R_HSYNC]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_HSYNC]
+##set_property PACKAGE_PIN AA23 [get_ports HDMI_R_D28]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D28]
+##set_property PACKAGE_PIN AB24 [get_ports HDMI_R_D32]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D32]
+##set_property PACKAGE_PIN AC24 [get_ports HDMI_R_D31]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D31]
+##set_property PACKAGE_PIN V23 [get_ports HDMI_R_D23]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D23]
+##set_property PACKAGE_PIN W23 [get_ports HDMI_R_D19]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D19]
+##set_property PACKAGE_PIN Y22 [get_ports HDMI_R_D33]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D33]
+##set_property PACKAGE_PIN Y23 [get_ports HDMI_R_D34]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D34]
+##set_property INTERNAL_VREF 0.90 [get_iobanks 13]
+##set_property PACKAGE_PIN U22 [get_ports PHY_TX_CLK]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CLK]
+##set_property PACKAGE_PIN V22 [get_ports HDMI_R_D35]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D35]
+##set_property PACKAGE_PIN U21 [get_ports PHY_RX_CLK]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CLK]
+##set_property PACKAGE_PIN V21 [get_ports HDMI_R_CLK]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_CLK]
+##set_property PACKAGE_PIN W21 [get_ports HDMI_INT]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_INT]
+##set_property PACKAGE_PIN Y21 [get_ports HDMI_R_SPDIF]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_SPDIF]
+##set_property PACKAGE_PIN T20 [get_ports HDMI_SPDIF_OUT_LS]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_SPDIF_OUT_LS]
+##set_property PACKAGE_PIN U20 [get_ports HDMI_R_D18]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D18]
+##set_property PACKAGE_PIN W20 [get_ports HDMI_R_D20]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D20]
+##set_property PACKAGE_PIN Y20 [get_ports HDMI_R_D22]
+##set_property IOSTANDARD LVCMOS18 [get_ports HDMI_R_D22]
+##set_property PACKAGE_PIN T19 [get_ports USB_UART_TX]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_TX]
+##set_property PACKAGE_PIN U19 [get_ports USB_UART_RX]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RX]
+##set_property PACKAGE_PIN V19 [get_ports USB_UART_RTS]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_RTS]
+##set_property PACKAGE_PIN W19 [get_ports USB_UART_CTS]
+##set_property IOSTANDARD LVCMOS18 [get_ports USB_UART_CTS]
+##set_property PACKAGE_PIN V18 [get_ports PHY_RESET_B]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_RESET_B]
+##set_property PACKAGE_PIN W18 [get_ports PHY_MDC]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDC]
+##set_property PACKAGE_PIN T14 [get_ports PHY_MDIO]
+##set_property IOSTANDARD LVCMOS18 [get_ports PHY_MDIO]
+##set_property PACKAGE_PIN T15 [get_ports PHY_TX_CTRL]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TX_CTRL]
+##set_property PACKAGE_PIN T17 [get_ports PHY_TXD3]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD3]
+##set_property PACKAGE_PIN T18 [get_ports PHY_TXD2]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD2]
+##set_property PACKAGE_PIN U15 [get_ports PHY_TXD1]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD1]
+##set_property PACKAGE_PIN U16 [get_ports PHY_TXD0]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_TXD0]
+##set_property PACKAGE_PIN U14 [get_ports PHY_RX_CTRL]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RX_CTRL]
+##set_property PACKAGE_PIN V14 [get_ports PHY_RXD3]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD3]
+##set_property PACKAGE_PIN V16 [get_ports PHY_RXD2]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD2]
+##set_property PACKAGE_PIN V17 [get_ports PHY_RXD1]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD1]
+##set_property PACKAGE_PIN U17 [get_ports PHY_RXD0]
+##set_property IOSTANDARD HSTL_I_18 [get_ports PHY_RXD0]
+##set_property PACKAGE_PIN M19 [get_ports SI5324_INT_ALM_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports SI5324_INT_ALM_B]
+##set_property PACKAGE_PIN R14 [get_ports FLASH_D0]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D0]
+##set_property PACKAGE_PIN R15 [get_ports FLASH_D1]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D1]
+##set_property PACKAGE_PIN P14 [get_ports FLASH_D2]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D2]
+##set_property PACKAGE_PIN N14 [get_ports FLASH_D3]
+##set_property IOSTANDARD LVCMOS33 [get_ports FLASH_D3]
+##set_property PACKAGE_PIN P15 [get_ports CTRL2_PWRGOOD]
+##set_property IOSTANDARD LVCMOS33 [get_ports CTRL2_PWRGOOD]
+##set_property PACKAGE_PIN P16 [get_ports FPGA_EMCCLK]
+##set_property IOSTANDARD LVCMOS33 [get_ports FPGA_EMCCLK]
+##set_property PACKAGE_PIN N16 [get_ports FMC1_HPC_PRSNT_M2C_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC1_HPC_PRSNT_M2C_B]
+##set_property PACKAGE_PIN N17 [get_ports FMC1_HPC_PG_M2C]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC1_HPC_PG_M2C]
+##set_property PACKAGE_PIN R16 [get_ports FMC_VADJ_ON_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports FMC_VADJ_ON_B]
+##set_property PACKAGE_PIN R17 [get_ports IIC_MUX_RESET_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_MUX_RESET_B]
+##set_property PACKAGE_PIN P18 [get_ports QSPI_IC_CS_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports QSPI_IC_CS_B]
+##set_property PACKAGE_PIN N18 [get_ports IIC_SCL_MAIN]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_SCL_MAIN]
+##set_property PACKAGE_PIN K25 [get_ports IIC_SDA_MAIN]
+##set_property IOSTANDARD LVCMOS33 [get_ports IIC_SDA_MAIN]
+##set_property PACKAGE_PIN K26 [get_ports PCIE_WAKE_B]
+##set_property IOSTANDARD LVCMOS33 [get_ports PCIE_WAKE_B]
+##set_property PACKAGE_PIN M20 [get_ports PCIE_PERST]
+##set_property IOSTANDARD LVCMOS33 [get_ports PCIE_PERST]
+##set_property PACKAGE_PIN L20 [get_ports LCD_E_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_E_LS]
+##set_property PACKAGE_PIN L24 [get_ports LCD_RW_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_RW_LS]
+##set_property PACKAGE_PIN L25 [get_ports LCD_DB4_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB4_LS]
+##set_property PACKAGE_PIN M24 [get_ports LCD_DB5_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB5_LS]
+##set_property PACKAGE_PIN M25 [get_ports LCD_DB6_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB6_LS]
+##set_property PACKAGE_PIN L22 [get_ports LCD_DB7_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_DB7_LS]
+##set_property PACKAGE_PIN L23 [get_ports LCD_RS_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports LCD_RS_LS]
+##set_property PACKAGE_PIN M21 [get_ports USER_CLOCK_P]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_P]
+##set_property PACKAGE_PIN M22 [get_ports USER_CLOCK_N]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_CLOCK_N]
+##set_property PACKAGE_PIN N21 [get_ports ROTARY_PUSH]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_PUSH]
+##set_property PACKAGE_PIN N22 [get_ports ROTARY_INCA]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCA]
+##set_property PACKAGE_PIN P20 [get_ports ROTARY_INCB]
+##set_property IOSTANDARD LVCMOS33 [get_ports ROTARY_INCB]
+##set_property PACKAGE_PIN P21 [get_ports SDIO_CD_DAT3]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CD_DAT3]
+##set_property PACKAGE_PIN N23 [get_ports SDIO_CMD]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CMD]
+##set_property PACKAGE_PIN N24 [get_ports SDIO_CLK]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_CLK]
+##set_property PACKAGE_PIN P19 [get_ports SDIO_DAT0]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT0]
+##set_property PACKAGE_PIN N19 [get_ports SDIO_DAT1]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT1]
+##set_property PACKAGE_PIN P23 [get_ports SDIO_DAT2]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_DAT2]
+##set_property PACKAGE_PIN P24 [get_ports SDIO_SDDET]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDDET]
+##set_property PACKAGE_PIN R20 [get_ports SDIO_SDWP]
+##set_property IOSTANDARD LVCMOS33 [get_ports SDIO_SDWP]
+##set_property PACKAGE_PIN R21 [get_ports PMBUS_CLK_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CLK_LS]
+##set_property PACKAGE_PIN R25 [get_ports PMBUS_DATA_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_DATA_LS]
+##set_property PACKAGE_PIN P25 [get_ports PMBUS_CTRL_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_CTRL_LS]
+##set_property PACKAGE_PIN N26 [get_ports PMBUS_ALERT_LS]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMBUS_ALERT_LS]
+##set_property PACKAGE_PIN M26 [get_ports GPIO_LED_0]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_0]
+##set_property PACKAGE_PIN T24 [get_ports GPIO_LED_1]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_1]
+##set_property PACKAGE_PIN T25 [get_ports GPIO_LED_2]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_2]
+##set_property PACKAGE_PIN R26 [get_ports GPIO_LED_3]
+##set_property IOSTANDARD LVCMOS33 [get_ports GPIO_LED_3]
+##set_property PACKAGE_PIN P26 [get_ports PMOD_0]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_0]
+##set_property PACKAGE_PIN T22 [get_ports PMOD_1]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_1]
+##set_property PACKAGE_PIN R22 [get_ports PMOD_2]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_2]
+##set_property PACKAGE_PIN T23 [get_ports PMOD_3]
+##set_property IOSTANDARD LVCMOS33 [get_ports PMOD_3]
+##set_property PACKAGE_PIN R23 [get_ports SFP_LOS]
+##set_property IOSTANDARD LVCMOS33 [get_ports SFP_LOS]
+##set_property PACKAGE_PIN R18 [get_ports SFP_TX_DISABLE]
+##set_property IOSTANDARD LVCMOS33 [get_ports SFP_TX_DISABLE]
+##set_property PACKAGE_PIN K18 [get_ports XADC_GPIO_2]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_2]
+##set_property PACKAGE_PIN K15 [get_ports XADC_VAUX0_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_P]
+##set_property PACKAGE_PIN J16 [get_ports XADC_VAUX0_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX0_R_N]
+##set_property PACKAGE_PIN J14 [get_ports XADC_VAUX8_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_P]
+##set_property PACKAGE_PIN J15 [get_ports XADC_VAUX8_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_VAUX8_R_N]
+##set_property PACKAGE_PIN K16 [get_ports XADC_AD1_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_P]
+##set_property PACKAGE_PIN K17 [get_ports XADC_AD1_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD1_R_N]
+##set_property PACKAGE_PIN M14 [get_ports FMC1_HPC_LA19_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA19_P]
+##set_property PACKAGE_PIN L14 [get_ports FMC1_HPC_LA19_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA19_N]
+##set_property PACKAGE_PIN M15 [get_ports XADC_AD9_R_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_P]
+##set_property PACKAGE_PIN L15 [get_ports XADC_AD9_R_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_AD9_R_N]
+##set_property PACKAGE_PIN M16 [get_ports FMC1_HPC_LA20_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA20_P]
+##set_property PACKAGE_PIN M17 [get_ports FMC1_HPC_LA20_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA20_N]
+##set_property PACKAGE_PIN J19 [get_ports FMC1_HPC_LA21_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA21_P]
+##set_property PACKAGE_PIN H19 [get_ports FMC1_HPC_LA21_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA21_N]
+##set_property PACKAGE_PIN L17 [get_ports FMC1_HPC_LA22_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA22_P]
+##set_property PACKAGE_PIN L18 [get_ports FMC1_HPC_LA22_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA22_N]
+##set_property PACKAGE_PIN K20 [get_ports FMC1_HPC_LA23_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA23_P]
+##set_property PACKAGE_PIN J20 [get_ports FMC1_HPC_LA23_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA23_N]
+##set_property PACKAGE_PIN J18 [get_ports FMC1_HPC_LA24_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA24_P]
+##set_property PACKAGE_PIN H18 [get_ports FMC1_HPC_LA24_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA24_N]
+##set_property PACKAGE_PIN G20 [get_ports FMC1_HPC_LA18_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA18_CC_P]
+##set_property PACKAGE_PIN G21 [get_ports FMC1_HPC_LA18_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA18_CC_N]
+##set_property PACKAGE_PIN K21 [get_ports FMC1_HPC_LA17_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_P]
+##set_property PACKAGE_PIN J21 [get_ports FMC1_HPC_LA17_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA17_CC_N]
+##set_property PACKAGE_PIN H21 [get_ports FMC1_HPC_CLK1_M2C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK1_M2C_P]
+##set_property PACKAGE_PIN H22 [get_ports FMC1_HPC_CLK1_M2C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK1_M2C_N]
+##set_property PACKAGE_PIN J23 [get_ports USER_SMA_CLOCK_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_P]
+##set_property PACKAGE_PIN H23 [get_ports USER_SMA_CLOCK_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports USER_SMA_CLOCK_N]
+##set_property PACKAGE_PIN G22 [get_ports FMC1_HPC_LA25_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_P]
+##set_property PACKAGE_PIN F22 [get_ports FMC1_HPC_LA25_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA25_N]
+##set_property PACKAGE_PIN J24 [get_ports FMC1_HPC_LA26_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_P]
+##set_property PACKAGE_PIN H24 [get_ports FMC1_HPC_LA26_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA26_N]
+##set_property PACKAGE_PIN F23 [get_ports FMC1_HPC_LA27_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_P]
+##set_property PACKAGE_PIN E23 [get_ports FMC1_HPC_LA27_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA27_N]
+##set_property PACKAGE_PIN K22 [get_ports FMC1_HPC_LA28_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA28_P]
+##set_property PACKAGE_PIN K23 [get_ports FMC1_HPC_LA28_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA28_N]
+##set_property PACKAGE_PIN G24 [get_ports FMC1_HPC_LA29_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA29_P]
+##set_property PACKAGE_PIN F24 [get_ports FMC1_HPC_LA29_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA29_N]
+##set_property PACKAGE_PIN E25 [get_ports FMC1_HPC_LA30_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA30_P]
+##set_property PACKAGE_PIN D25 [get_ports FMC1_HPC_LA30_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA30_N]
+##set_property PACKAGE_PIN E26 [get_ports FMC1_HPC_LA31_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA31_P]
+##set_property PACKAGE_PIN D26 [get_ports FMC1_HPC_LA31_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA31_N]
+##set_property PACKAGE_PIN H26 [get_ports FMC1_HPC_LA32_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA32_P]
+##set_property PACKAGE_PIN G26 [get_ports FMC1_HPC_LA32_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA32_N]
+##set_property PACKAGE_PIN G25 [get_ports FMC1_HPC_LA33_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA33_P]
+##set_property PACKAGE_PIN F25 [get_ports FMC1_HPC_LA33_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA33_N]
+##set_property PACKAGE_PIN J25 [get_ports SM_FAN_TACH]
+##set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_TACH]
+##set_property PACKAGE_PIN J26 [get_ports SM_FAN_PWM]
+##set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_PWM]
+##set_property PACKAGE_PIN L19 [get_ports XADC_GPIO_3]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_3]
+##set_property PACKAGE_PIN H17 [get_ports XADC_GPIO_0]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_0]
+##set_property PACKAGE_PIN H14 [get_ports FMC1_HPC_LA02_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA02_P]
+##set_property PACKAGE_PIN H15 [get_ports FMC1_HPC_LA02_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA02_N]
+##set_property PACKAGE_PIN G17 [get_ports FMC1_HPC_LA03_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA03_P]
+##set_property PACKAGE_PIN F17 [get_ports FMC1_HPC_LA03_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA03_N]
+##set_property PACKAGE_PIN F18 [get_ports FMC1_HPC_LA04_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA04_P]
+##set_property PACKAGE_PIN F19 [get_ports FMC1_HPC_LA04_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA04_N]
+##set_property PACKAGE_PIN G15 [get_ports FMC1_HPC_LA05_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA05_P]
+##set_property PACKAGE_PIN F15 [get_ports FMC1_HPC_LA05_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA05_N]
+##set_property PACKAGE_PIN G19 [get_ports FMC1_HPC_LA06_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA06_P]
+##set_property PACKAGE_PIN F20 [get_ports FMC1_HPC_LA06_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA06_N]
+##set_property PACKAGE_PIN H16 [get_ports FMC1_HPC_LA07_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA07_P]
+##set_property PACKAGE_PIN G16 [get_ports FMC1_HPC_LA07_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA07_N]
+##set_property PACKAGE_PIN C17 [get_ports FMC1_HPC_LA08_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA08_P]
+##set_property PACKAGE_PIN B17 [get_ports FMC1_HPC_LA08_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA08_N]
+##set_property PACKAGE_PIN E16 [get_ports FMC1_HPC_LA09_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA09_P]
+##set_property PACKAGE_PIN D16 [get_ports FMC1_HPC_LA09_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA09_N]
+##set_property PACKAGE_PIN A17 [get_ports FMC1_HPC_LA10_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA10_P]
+##set_property PACKAGE_PIN A18 [get_ports FMC1_HPC_LA10_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA10_N]
+##set_property PACKAGE_PIN B19 [get_ports FMC1_HPC_LA11_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA11_P]
+##set_property PACKAGE_PIN A19 [get_ports FMC1_HPC_LA11_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA11_N]
+##set_property PACKAGE_PIN E17 [get_ports FMC1_HPC_LA01_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA01_CC_P]
+##set_property PACKAGE_PIN E18 [get_ports FMC1_HPC_LA01_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA01_CC_N]
+##set_property PACKAGE_PIN D18 [get_ports FMC1_HPC_LA00_CC_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA00_CC_P]
+##set_property PACKAGE_PIN C18 [get_ports FMC1_HPC_LA00_CC_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA00_CC_N]
+##set_property PACKAGE_PIN D19 [get_ports FMC1_HPC_CLK0_M2C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK0_M2C_P]
+##set_property PACKAGE_PIN C19 [get_ports FMC1_HPC_CLK0_M2C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports FMC1_HPC_CLK0_M2C_N]
+##set_property PACKAGE_PIN E20 [get_ports FMC1_HPC_LA12_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA12_P]
+##set_property PACKAGE_PIN D20 [get_ports FMC1_HPC_LA12_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA12_N]
+##set_property PACKAGE_PIN B20 [get_ports FMC1_HPC_LA13_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA13_P]
+##set_property PACKAGE_PIN A20 [get_ports FMC1_HPC_LA13_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA13_N]
+##set_property PACKAGE_PIN C21 [get_ports FMC1_HPC_LA14_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA14_P]
+##set_property PACKAGE_PIN B21 [get_ports FMC1_HPC_LA14_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA14_N]
+##set_property PACKAGE_PIN B22 [get_ports FMC1_HPC_LA15_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA15_P]
+##set_property PACKAGE_PIN A22 [get_ports FMC1_HPC_LA15_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA15_N]
+##set_property PACKAGE_PIN E21 [get_ports FMC1_HPC_LA16_P]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_P]
+##set_property PACKAGE_PIN D21 [get_ports FMC1_HPC_LA16_N]
+##set_property IOSTANDARD LVCMOS25 [get_ports FMC1_HPC_LA16_N]
+##set_property PACKAGE_PIN C22 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN C23 [get_ports No]
+##set_property IOSTANDARD LVCMOS25 [get_ports No]
+##set_property PACKAGE_PIN B25 [get_ports XADC_MUX_ADDR0_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR0_LS]
+##set_property PACKAGE_PIN A25 [get_ports XADC_MUX_ADDR1_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR1_LS]
+##set_property PACKAGE_PIN A23 [get_ports XADC_MUX_ADDR2_LS]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_MUX_ADDR2_LS]
+##set_property PACKAGE_PIN A24 [get_ports PCIE_MGT_CLK_SEL0]
+##set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL0]
+##set_property PACKAGE_PIN C26 [get_ports PCIE_MGT_CLK_SEL1]
+##set_property IOSTANDARD LVCMOS25 [get_ports PCIE_MGT_CLK_SEL1]
+##set_property PACKAGE_PIN B26 [get_ports SFP_MGT_CLK_SEL0]
+##set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL0]
+##set_property PACKAGE_PIN C24 [get_ports SFP_MGT_CLK_SEL1]
+##set_property IOSTANDARD LVCMOS25 [get_ports SFP_MGT_CLK_SEL1]
+##set_property PACKAGE_PIN B24 [get_ports SI5324_RST_LS_B]
+##set_property IOSTANDARD LVCMOS25 [get_ports SI5324_RST_LS_B]
+##set_property PACKAGE_PIN D23 [get_ports REC_CLOCK_C_P]
+##set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_P]
+##set_property PACKAGE_PIN D24 [get_ports REC_CLOCK_C_N]
+##set_property IOSTANDARD LVDS_25 [get_ports REC_CLOCK_C_N]
+##set_property PACKAGE_PIN E22 [get_ports XADC_GPIO_1]
+##set_property IOSTANDARD LVCMOS25 [get_ports XADC_GPIO_1]
+##set_property PACKAGE_PIN V4 [get_ports No]
+##set_property IOSTANDARD LVCMOS15 [get_ports No]
+##set_property PACKAGE_PIN V1 [get_ports DDR3_D31]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D31]
+##set_property PACKAGE_PIN W1 [get_ports DDR3_D30]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D30]
+##set_property PACKAGE_PIN W5 [get_ports DDR3_D29]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D29]
+##set_property PACKAGE_PIN W4 [get_ports DDR3_D28]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D28]
+##set_property PACKAGE_PIN V3 [get_ports DDR3_DQS3_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P]
+##set_property PACKAGE_PIN V2 [get_ports DDR3_DQS3_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N]
+##set_property PACKAGE_PIN V6 [get_ports DDR3_D27]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D27]
+##set_property PACKAGE_PIN W6 [get_ports DDR3_D26]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D26]
+##set_property PACKAGE_PIN W3 [get_ports DDR3_D25]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D25]
+##set_property PACKAGE_PIN Y3 [get_ports DDR3_D24]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D24]
+##set_property PACKAGE_PIN U7 [get_ports DDR3_DM3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM3]
+##set_property PACKAGE_PIN V7 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN AB1 [get_ports DDR3_D23]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D23]
+##set_property PACKAGE_PIN AC1 [get_ports DDR3_D22]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D22]
+##set_property PACKAGE_PIN Y2 [get_ports DDR3_D21]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D21]
+##set_property PACKAGE_PIN Y1 [get_ports DDR3_D20]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D20]
+##set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS2_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_P]
+##set_property PACKAGE_PIN AE1 [get_ports DDR3_DQS2_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_N]
+##set_property PACKAGE_PIN AE2 [get_ports DDR3_D19]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D19]
+##set_property PACKAGE_PIN AF2 [get_ports DDR3_D18]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D18]
+##set_property PACKAGE_PIN AB2 [get_ports DDR3_D17]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D17]
+##set_property PACKAGE_PIN AC2 [get_ports DDR3_D16]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D16]
+##set_property PACKAGE_PIN AA3 [get_ports DDR3_DM2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM2]
+##set_property PACKAGE_PIN AA2 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN AA4 [get_ports DDR3_D15]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D15]
+##set_property PACKAGE_PIN AB4 [get_ports DDR3_D14]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D14]
+##set_property PACKAGE_PIN AC3 [get_ports DDR3_D13]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D13]
+##set_property PACKAGE_PIN AD3 [get_ports DDR3_D12]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D12]
+##set_property PACKAGE_PIN AD5 [get_ports DDR3_DQS1_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
+##set_property PACKAGE_PIN AE5 [get_ports DDR3_DQS1_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
+##set_property PACKAGE_PIN AE3 [get_ports DDR3_D11]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D11]
+##set_property PACKAGE_PIN AF3 [get_ports DDR3_D10]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D10]
+##set_property PACKAGE_PIN AF5 [get_ports DDR3_D9]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D9]
+##set_property PACKAGE_PIN AF4 [get_ports DDR3_D8]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D8]
+##set_property PACKAGE_PIN AC4 [get_ports DDR3_DM1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM1]
+##set_property PACKAGE_PIN AD4 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN Y7 [get_ports DDR3_D7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D7]
+##set_property PACKAGE_PIN AA7 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN Y6 [get_ports DDR3_D6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D6]
+##set_property PACKAGE_PIN Y5 [get_ports DDR3_D5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D5]
+##set_property PACKAGE_PIN V8 [get_ports DDR3_DQS0_P]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_P]
+##set_property PACKAGE_PIN W8 [get_ports DDR3_DQS0_N]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DQS0_N]
+##set_property PACKAGE_PIN AA5 [get_ports DDR3_D4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D4]
+##set_property PACKAGE_PIN AB5 [get_ports DDR3_D3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D3]
+##set_property PACKAGE_PIN Y8 [get_ports DDR3_D2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D2]
+##set_property PACKAGE_PIN AA8 [get_ports DDR3_D1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D1]
+##set_property PACKAGE_PIN AB6 [get_ports DDR3_D0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D0]
+##set_property PACKAGE_PIN AC6 [get_ports DDR3_DM0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM0]
+##set_property PACKAGE_PIN V9 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN N8 [get_ports DDR3_RESET_B]
+##set_property IOSTANDARD LVCMOS15 [get_ports DDR3_RESET_B]
+##set_property PACKAGE_PIN K3 [get_ports DDR3_A9]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A9]
+##set_property PACKAGE_PIN J3 [get_ports DDR3_A1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A1]
+##set_property PACKAGE_PIN M7 [get_ports DDR3_A5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A5]
+##set_property PACKAGE_PIN L7 [get_ports DDR3_A12]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A12]
+##set_property PACKAGE_PIN M4 [get_ports DDR3_A0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A0]
+##set_property PACKAGE_PIN L4 [get_ports DDR3_A3]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A3]
+##set_property PACKAGE_PIN L5 [get_ports DDR3_A11]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A11]
+##set_property PACKAGE_PIN K5 [get_ports DDR3_A4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A4]
+##set_property PACKAGE_PIN N7 [get_ports DDR3_A10]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A10]
+##set_property PACKAGE_PIN N6 [get_ports DDR3_A13]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A13]
+##set_property PACKAGE_PIN M6 [get_ports DDR3_A7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A7]
+##set_property PACKAGE_PIN M5 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN K1 [get_ports DDR3_A6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A6]
+##set_property PACKAGE_PIN J1 [get_ports DDR3_A2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A2]
+##set_property PACKAGE_PIN L3 [get_ports DDR3_A14]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A14]
+##set_property PACKAGE_PIN K2 [get_ports DDR3_A15]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A15]
+##set_property PACKAGE_PIN N1 [get_ports DDR3_BA0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA0]
+##set_property PACKAGE_PIN M1 [get_ports DDR3_BA1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA1]
+##set_property PACKAGE_PIN H2 [get_ports DDR3_BA2]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_BA2]
+##set_property PACKAGE_PIN H1 [get_ports DDR3_A8]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_A8]
+##set_property PACKAGE_PIN M2 [get_ports DDR3_CLK0_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_P]
+##set_property PACKAGE_PIN L2 [get_ports DDR3_CLK0_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK0_N]
+##set_property PACKAGE_PIN N3 [get_ports DDR3_CLK1_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_P]
+##set_property PACKAGE_PIN N2 [get_ports DDR3_CLK1_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_CLK1_N]
+##set_property PACKAGE_PIN R3 [get_ports SYSCLK_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_P]
+##set_property PACKAGE_PIN P3 [get_ports SYSCLK_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SYSCLK_N]
+##set_property PACKAGE_PIN P4 [get_ports DDR3_CKE0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE0]
+##set_property PACKAGE_PIN N4 [get_ports DDR3_CKE1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CKE1]
+##set_property PACKAGE_PIN R1 [get_ports DDR3_WE_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_WE_B]
+##set_property PACKAGE_PIN P1 [get_ports DDR3_RAS_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_RAS_B]
+##set_property PACKAGE_PIN T4 [get_ports DDR3_CAS_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_CAS_B]
+##set_property PACKAGE_PIN T3 [get_ports DDR3_S0_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_S0_B]
+##set_property PACKAGE_PIN T2 [get_ports DDR3_S1_B]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_S1_B]
+##set_property PACKAGE_PIN R2 [get_ports DDR3_ODT0]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT0]
+##set_property PACKAGE_PIN U2 [get_ports DDR3_ODT1]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_ODT1]
+##set_property PACKAGE_PIN U1 [get_ports DDR3_TEMP_EVENT]
+##set_property IOSTANDARD LVCMOS15 [get_ports DDR3_TEMP_EVENT]
+##set_property PACKAGE_PIN P6 [get_ports GPIO_SW_N]
+##set_property IOSTANDARD LVCMOS15 [get_ports GPIO_SW_N]
+##set_property PACKAGE_PIN P5 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN T5 [get_ports GPIO_SW_S]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_S]
+##set_property PACKAGE_PIN R5 [get_ports GPIO_SW_W]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_W]
+##set_property PACKAGE_PIN U6 [get_ports GPIO_SW_C]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_C]
+##set_property PACKAGE_PIN U5 [get_ports GPIO_SW_E]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_SW_E]
+##set_property PACKAGE_PIN R8 [get_ports GPIO_DIP_SW0]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW0]
+##set_property PACKAGE_PIN P8 [get_ports GPIO_DIP_SW1]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW1]
+##set_property PACKAGE_PIN R7 [get_ports GPIO_DIP_SW2]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW2]
+##set_property PACKAGE_PIN R6 [get_ports GPIO_DIP_SW3]
+##set_property IOSTANDARD SSTL15 [get_ports GPIO_DIP_SW3]
+##set_property PACKAGE_PIN T8 [get_ports USER_SMA_GPIO_P]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_P]
+##set_property PACKAGE_PIN T7 [get_ports USER_SMA_GPIO_N]
+##set_property IOSTANDARD LVDS_25 [get_ports USER_SMA_GPIO_N]
+##set_property PACKAGE_PIN U4 [get_ports CPU_RESET]
+##set_property IOSTANDARD LVCMOS15 [get_ports CPU_RESET]
+##set_property PACKAGE_PIN J8 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN E6 [get_ports DDR3_D63]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D63]
+##set_property PACKAGE_PIN D6 [get_ports DDR3_D62]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D62]
+##set_property PACKAGE_PIN H8 [get_ports DDR3_D61]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D61]
+##set_property PACKAGE_PIN G8 [get_ports DDR3_D60]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D60]
+##set_property PACKAGE_PIN H7 [get_ports DDR3_DQS7_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
+##set_property PACKAGE_PIN G7 [get_ports DDR3_DQS7_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
+##set_property PACKAGE_PIN F8 [get_ports DDR3_D59]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D59]
+##set_property PACKAGE_PIN F7 [get_ports DDR3_D58]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D58]
+##set_property PACKAGE_PIN H6 [get_ports DDR3_D57]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D57]
+##set_property PACKAGE_PIN G6 [get_ports DDR3_D56]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D56]
+##set_property PACKAGE_PIN H9 [get_ports DDR3_DM7]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
+##set_property PACKAGE_PIN G9 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN J6 [get_ports DDR3_D55]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D55]
+##set_property PACKAGE_PIN J5 [get_ports DDR3_D54]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D54]
+##set_property PACKAGE_PIN L8 [get_ports DDR3_D53]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D53]
+##set_property PACKAGE_PIN K8 [get_ports DDR3_D52]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D52]
+##set_property PACKAGE_PIN J4 [get_ports DDR3_DQS6_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
+##set_property PACKAGE_PIN H4 [get_ports DDR3_DQS6_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
+##set_property PACKAGE_PIN K7 [get_ports DDR3_D51]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D51]
+##set_property PACKAGE_PIN K6 [get_ports DDR3_D50]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D50]
+##set_property PACKAGE_PIN G4 [get_ports DDR3_D49]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D49]
+##set_property PACKAGE_PIN F4 [get_ports DDR3_D48]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D48]
+##set_property PACKAGE_PIN G5 [get_ports DDR3_DM6]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
+##set_property PACKAGE_PIN F5 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN E5 [get_ports DDR3_D47]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D47]
+##set_property PACKAGE_PIN D5 [get_ports DDR3_D46]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D46]
+##set_property PACKAGE_PIN D4 [get_ports DDR3_D45]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D45]
+##set_property PACKAGE_PIN C4 [get_ports DDR3_D44]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D44]
+##set_property PACKAGE_PIN B5 [get_ports DDR3_DQS5_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
+##set_property PACKAGE_PIN A5 [get_ports DDR3_DQS5_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
+##set_property PACKAGE_PIN B4 [get_ports DDR3_D43]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D43]
+##set_property PACKAGE_PIN A4 [get_ports DDR3_D42]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D42]
+##set_property PACKAGE_PIN D3 [get_ports DDR3_D41]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D41]
+##set_property PACKAGE_PIN C3 [get_ports DDR3_D40]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D40]
+##set_property PACKAGE_PIN F3 [get_ports DDR3_DM5]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
+##set_property PACKAGE_PIN E3 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN C2 [get_ports DDR3_D39]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D39]
+##set_property PACKAGE_PIN B2 [get_ports VTTVREF]
+##set_property IOSTANDARD SSTL15 [get_ports VTTVREF]
+##set_property PACKAGE_PIN A3 [get_ports DDR3_D38]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D38]
+##set_property PACKAGE_PIN A2 [get_ports DDR3_D37]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D37]
+##set_property PACKAGE_PIN C1 [get_ports DDR3_DQS4_P]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
+##set_property PACKAGE_PIN B1 [get_ports DDR3_DQS4_N]
+##set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
+##set_property PACKAGE_PIN F2 [get_ports DDR3_D36]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D36]
+##set_property PACKAGE_PIN E2 [get_ports DDR3_D35]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D35]
+##set_property PACKAGE_PIN E1 [get_ports DDR3_D34]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D34]
+##set_property PACKAGE_PIN D1 [get_ports DDR3_D33]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D33]
+##set_property PACKAGE_PIN G2 [get_ports DDR3_D32]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_D32]
+##set_property PACKAGE_PIN G1 [get_ports DDR3_DM4]
+##set_property IOSTANDARD SSTL15 [get_ports DDR3_DM4]
+##set_property PACKAGE_PIN H3 [get_ports No]
+##set_property IOSTANDARD SSTL15 [get_ports No]
+##set_property PACKAGE_PIN AB13 [get_ports SFP_MGT_CLK0_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_N]
+##set_property PACKAGE_PIN AA13 [get_ports SFP_MGT_CLK0_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK0_P]
+##set_property PACKAGE_PIN AF15 [get_ports MGTRREF_213]
+##set_property IOSTANDARD LVDS_25 [get_ports MGTRREF_213]
+##set_property PACKAGE_PIN AA11 [get_ports SFP_MGT_CLK1_P]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_P]
+##set_property PACKAGE_PIN AB11 [get_ports SFP_MGT_CLK1_N]
+##set_property IOSTANDARD LVDS_25 [get_ports SFP_MGT_CLK1_N]
+##set_property PACKAGE_PIN E11 [get_ports PCIE_CLK_QO_N]
+##set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_N]
+##set_property PACKAGE_PIN F11 [get_ports PCIE_CLK_QO_P]
+##set_property IOSTANDARD LVDS_25 [get_ports PCIE_CLK_QO_P]
+##set_property PACKAGE_PIN A15 [get_ports MGTRREF_216]
+##set_property IOSTANDARD LVDS_25 [get_ports MGTRREF_216]
+##set_property PACKAGE_PIN F13 [get_ports No]
+##set_property IOSTANDARD LVDS_25 [get_ports No]
+##set_property PACKAGE_PIN E13 [get_ports No]
+##set_property IOSTANDARD LVDS_25 [get_ports No]
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P0[15]} ]
+
+set_property PULLUP true [get_ports {P0[0]} ]
+set_property PULLUP true [get_ports {P0[1]} ]
+set_property PULLUP true [get_ports {P0[2]} ]
+set_property PULLUP true [get_ports {P0[3]} ]
+set_property PULLUP true [get_ports {P0[4]} ]
+set_property PULLUP true [get_ports {P0[5]} ]
+set_property PULLUP true [get_ports {P0[6]} ]
+set_property PULLUP true [get_ports {P0[7]} ]
+set_property PULLUP true [get_ports {P0[8]} ]
+set_property PULLUP true [get_ports {P0[9]} ]
+set_property PULLUP true [get_ports {P0[10]} ]
+set_property PULLUP true [get_ports {P0[11]} ]
+set_property PULLUP true [get_ports {P0[12]} ]
+set_property PULLUP true [get_ports {P0[13]} ]
+set_property PULLUP true [get_ports {P0[14]} ]
+set_property PULLUP true [get_ports {P0[15]} ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[0]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[1]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[2]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[3]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[4]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[5]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[6]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[7]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[8]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[9]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[10]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[11]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[12]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[13]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[14]} ]
+set_property IOSTANDARD LVCMOS33 [get_ports {P1[15]} ]
+
+set_property PULLUP true [get_ports {P1[0]} ]
+set_property PULLUP true [get_ports {P1[1]} ]
+set_property PULLUP true [get_ports {P1[2]} ]
+set_property PULLUP true [get_ports {P1[3]} ]
+set_property PULLUP true [get_ports {P1[4]} ]
+set_property PULLUP true [get_ports {P1[5]} ]
+set_property PULLUP true [get_ports {P1[6]} ]
+set_property PULLUP true [get_ports {P1[7]} ]
+set_property PULLUP true [get_ports {P1[8]} ]
+set_property PULLUP true [get_ports {P1[9]} ]
+set_property PULLUP true [get_ports {P1[10]} ]
+set_property PULLUP true [get_ports {P1[11]} ]
+set_property PULLUP true [get_ports {P1[12]} ]
+set_property PULLUP true [get_ports {P1[13]} ]
+set_property PULLUP true [get_ports {P1[14]} ]
+set_property PULLUP true [get_ports {P1[15]} ]
+
+set_property PULLDOWN true [get_ports {SWDIOTMS} ]
+set_property PULLDOWN true [get_ports {SWCLKTCK} ]
+
+#PMODA pin0 to FTCLK
+set_property PACKAGE_PIN T22 [get_ports {P1[1]}]
+
+#PMODA pin1 to FTSSN
+set_property PACKAGE_PIN T23 [get_ports {P1[3]}]
+
+#PMODA pin2 to FTMISO
+set_property PACKAGE_PIN P26 [get_ports {P1[0]}]
+
+#PMODA pin3 to FTMIOSIO
+set_property PACKAGE_PIN R22 [get_ports {P1[2]}]
+
+#PMODB pin1 to SWDIOTMS
+##set_property PACKAGE_PIN G6 [get_ports SWDIOTMS]
+
+#PMODB pin4 to SWCLKTCK
+##set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+##set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+set_property PACKAGE_PIN M26 [get_ports {P0[0]}]
+# LED1 to P0[1]
+set_property PACKAGE_PIN T24 [get_ports {P0[1]}]
+# LED2 to P0[2]
+set_property PACKAGE_PIN T25 [get_ports {P0[2]}]
+# LED3 to P0[3]
+set_property PACKAGE_PIN R26 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+set_property PACKAGE_PIN R8 [get_ports NRST]
+
+# USR CLOCK P (need dvider)
+##set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+#set_property PACKAGE_PIN M21 [get_ports XTAL1]
+#set_property PACKAGE_PIN R17 [get_ports XTAL2]
+
+#Board ref clock - 200MHz (need dvider)
+#set_property PACKAGE_PIN R3 [get_ports XTAL1]
+#set_property PACKAGE_PIN P3 [get_ports XTAL2]
+#Board user clock - 200MHz (need dvider)
+set_property PACKAGE_PIN M21 [get_ports XTAL1]
+set_property PACKAGE_PIN M22 [get_ports XTAL2]
+
+
+## auto mapped - to remap
+set_property PACKAGE_PIN R20 [get_ports {P0[10]}]
+set_property PACKAGE_PIN P24 [get_ports {P0[11]}]
+set_property PACKAGE_PIN P23 [get_ports {P0[12]}]
+set_property PACKAGE_PIN N19 [get_ports {P0[13]}]
+set_property PACKAGE_PIN P19 [get_ports {P0[14]}]
+set_property PACKAGE_PIN N24 [get_ports {P0[15]}]
+set_property PACKAGE_PIN R18 [get_ports {P0[4]}]
+set_property PACKAGE_PIN R23 [get_ports {P0[5]}]
+set_property PACKAGE_PIN N26 [get_ports {P0[6]}]
+set_property PACKAGE_PIN P25 [get_ports {P0[7]}]
+set_property PACKAGE_PIN R25 [get_ports {P0[8]}]
+set_property PACKAGE_PIN R21 [get_ports {P0[9]}]
+set_property PACKAGE_PIN M25 [get_ports {P1[10]}]
+set_property PACKAGE_PIN M24 [get_ports {P1[11]}]
+set_property PACKAGE_PIN L25 [get_ports {P1[12]}]
+set_property PACKAGE_PIN L24 [get_ports {P1[13]}]
+set_property PACKAGE_PIN L20 [get_ports {P1[14]}]
+set_property PACKAGE_PIN M20 [get_ports {P1[15]}]
+set_property PACKAGE_PIN N23 [get_ports {P1[4]}]
+set_property PACKAGE_PIN P21 [get_ports {P1[5]}]
+set_property PACKAGE_PIN P20 [get_ports {P1[6]}]
+set_property PACKAGE_PIN N22 [get_ports {P1[7]}]
+set_property PACKAGE_PIN N21 [get_ports {P1[8]}]
+set_property PACKAGE_PIN L23 [get_ports {P1[9]}]
+set_property PACKAGE_PIN L22 [get_ports SWCLKTCK]
+set_property PACKAGE_PIN K26 [get_ports SWDIOTMS]
+set_property PACKAGE_PIN K25 [get_ports VDD]
+set_property PACKAGE_PIN N18 [get_ports VDDIO]
+set_property PACKAGE_PIN P18 [get_ports VSS]
+set_property PACKAGE_PIN R17 [get_ports VSSIO]
diff --git a/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_synth.tcl b/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..a13e2b6e4b167fed62c60f4aa382e932b1b9593a
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_synth.tcl
@@ -0,0 +1,40 @@
+
+synth_design -top cmsdk_mcu_chip -part xc7a200tfbg676-2
+
+write_verilog -force $outputDir/cmsdk_mcu_synth_netlist.v
+
+# # Create interface ports
+#
+# disconnect_net -net XTAL1 -objects {uPAD_XTAL_I/XTAL1}
+# disconnect_net -net XTAL2 -objects {uPAD_XTAL_O/XTAL2}
+# #disconnect_net -net xtal_clk_in] [get_pins XTAL1 uPAD_XTAL1_PAD/IOBUF3V3/I]]
+
+# set sys_diff_clock [ create_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 sys_diff_clock ]
+# set_property -dict [ list \
+# CONFIG.FREQ_HZ {200000000} \
+# ] $sys_diff_clock
+
+# set reset [ create_bd_port -dir I -type rst reset ]
+# set_property -dict [ list \
+# CONFIG.POLARITY {ACTIVE_HIGH} \
+# ] $reset
+
+# # Create instance: clk_wiz_20M, and set properties
+# set clk_wiz_20M [ create_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_20M ]
+# set_property -dict [ list \
+# CONFIG.CLKOUT1_JITTER {155.788} \
+# CONFIG.CLKOUT1_PHASE_ERROR {94.329} \
+# CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {20.000} \
+# CONFIG.CLK_IN1_BOARD_INTERFACE {sys_diff_clock} \
+# CONFIG.MMCM_CLKFBOUT_MULT_F {4.250} \
+# CONFIG.MMCM_CLKOUT0_DIVIDE_F {42.500} \
+# CONFIG.RESET_BOARD_INTERFACE {reset} \
+# CONFIG.USE_BOARD_FLOW {false} \
+#] $clk_wiz_20M
+
+# # Create interface connections
+# connect_net -intf_net sys_diff_clock_1 [get_ports sys_diff_clock] [get_pins clk_wiz_20M/CLK_IN1_D]
+
+# # Create port connections
+# connect_net -net clk_wiz_0_clk_out1 [get_pins xtal_clk_in] [get_bd_pins clk_wiz_20M/clk_out1]
+# connect_net -net reset_1 [get_bd_ports reset] [get_bd_pins clk_wiz_20M/reset]
diff --git a/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_timing.xdc b/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..cb4cef44a99ecc3e62b7c6d18c03ca623885f6a8
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_ac701/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]}]
+
+set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/design_1.tcl b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..5f7080c391909e4b7854fe7f0da96e23e5c21b6c
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/design_1.tcl
@@ -0,0 +1,572 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {0} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/design_1_wrapper.v b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..438e63b62a3ae503d340521c5736e4ae5f000192
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/design_1_wrapper.v
@@ -0,0 +1,15 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper();
+
+
+endmodule
diff --git a/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_pinmap.xdc b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5fbe61eb28f3d716824d54418909d555a4f29ad4
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_pinmap.xdc
@@ -0,0 +1,915 @@
+# -----------------------------------------------------------------------------
+# Purpose : Main timing constraints and pin list for MPS3
+# -----------------------------------------------------------------------------
+
+####################################################################################
+# Pin Assigment
+####################################################################################
+
+set_property IOSTANDARD LVCMOS18 [get_ports {SMBF_* ETH_* USB_* CLCD_* USER_nLED* USER_SW* USER_nPB* HDMI_* CS_* SH_ADC* UART_*}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {OSCCLK[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[23]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[22]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[21]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[20]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[19]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[18]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[17]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[16]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[15]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[14]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[13]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[12]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[11]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[10]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[9]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[8]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_DATA[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {MMB_SD[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_DE]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_HS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_IDCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_SCK]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_VS]
+set_property IOSTANDARD LVCMOS18 [get_ports MMB_WS]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[6]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[5]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[4]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[3]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[2]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[1]}]
+set_property IOSTANDARD LVCMOS18 [get_ports {EMMC_DAT[0]}]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CLK]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_CMD]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_DS]
+set_property IOSTANDARD LVCMOS18 [get_ports EMMC_nRST]
+# not used
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[3]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_P[2]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_BIDIR_N[2]}]
+
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_LRCK]
+set_property PACKAGE_PIN Y30 [get_ports AUD_LRCK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_MCLK]
+set_property PACKAGE_PIN AB29 [get_ports AUD_MCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_nRST]
+set_property PACKAGE_PIN AA27 [get_ports AUD_nRST]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCL]
+set_property PACKAGE_PIN AA28 [get_ports AUD_SCL]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SCLK]
+set_property PACKAGE_PIN AB30 [get_ports AUD_SCLK]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDA]
+set_property PACKAGE_PIN AA29 [get_ports AUD_SDA]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDIN]
+set_property PACKAGE_PIN AA30 [get_ports AUD_SDIN]
+set_property IOSTANDARD LVCMOS18 [get_ports AUD_SDOUT]
+set_property PACKAGE_PIN Y27 [get_ports AUD_SDOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nPOR]
+set_property PACKAGE_PIN AU22 [get_ports CB_nPOR]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_nRST]
+set_property PACKAGE_PIN AV23 [get_ports CB_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CB_RUN]
+set_property PACKAGE_PIN AR25 [get_ports CB_RUN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_CLK]
+set_property PACKAGE_PIN AT20 [get_ports CFG_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAIN]
+set_property PACKAGE_PIN AT19 [get_ports CFG_DATAIN]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_DATAOUT]
+set_property PACKAGE_PIN AV18 [get_ports CFG_DATAOUT]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_LOAD]
+set_property PACKAGE_PIN AW18 [get_ports CFG_LOAD]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_nRST]
+set_property PACKAGE_PIN AR20 [get_ports CFG_nRST]
+set_property IOSTANDARD LVCMOS33 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AT18 [get_ports CFG_WnR]
+set_property PACKAGE_PIN AJ16 [get_ports CLCD_BL]
+set_property PACKAGE_PIN AP15 [get_ports CLCD_CS]
+set_property PACKAGE_PIN AN17 [get_ports {CLCD_PD[10]}]
+set_property PACKAGE_PIN AP16 [get_ports {CLCD_PD[11]}]
+set_property PACKAGE_PIN AP18 [get_ports {CLCD_PD[12]}]
+set_property PACKAGE_PIN AR18 [get_ports {CLCD_PD[13]}]
+set_property PACKAGE_PIN AM16 [get_ports {CLCD_PD[14]}]
+set_property PACKAGE_PIN AN16 [get_ports {CLCD_PD[15]}]
+set_property PACKAGE_PIN AR17 [get_ports {CLCD_PD[16]}]
+set_property PACKAGE_PIN AR16 [get_ports {CLCD_PD[17]}]
+set_property PACKAGE_PIN AM15 [get_ports CLCD_RD]
+set_property PACKAGE_PIN AN14 [get_ports CLCD_RS]
+set_property PACKAGE_PIN AK18 [get_ports CLCD_RST]
+#set_property PACKAGE_PIN AN18 [get_ports CLCD_SDI]
+#set_property PACKAGE_PIN AH16 [get_ports CLCD_SDO]
+set_property PACKAGE_PIN AJ14 [get_ports CLCD_TINT]
+set_property PACKAGE_PIN AL17 [get_ports CLCD_TNC]
+set_property PACKAGE_PIN AL18 [get_ports CLCD_TSCL]
+set_property PACKAGE_PIN AJ15 [get_ports CLCD_TSDA]
+set_property PACKAGE_PIN AP14 [get_ports CLCD_WR_SCL]
+# not used
+# set_property PACKAGE_PIN N28 [get_ports {CLK_BIDIR_P[2]}]
+# set_property PACKAGE_PIN N29 [get_ports {CLK_BIDIR_N[2]}]
+# set_property PACKAGE_PIN E32 [get_ports {CLK_BIDIR_P[3]}]
+# set_property PACKAGE_PIN D33 [get_ports {CLK_BIDIR_N[3]}]
+# set_property PACKAGE_PIN G31 [get_ports {CLK_M2C_P[0]}]
+# set_property PACKAGE_PIN F32 [get_ports {CLK_M2C_N[0]}]
+# set_property PACKAGE_PIN E31 [get_ports {CLK_M2C_P[1]}]
+# set_property PACKAGE_PIN D31 [get_ports {CLK_M2C_N[1]}]
+set_property PACKAGE_PIN BB39 [get_ports CS_nDET]
+set_property PACKAGE_PIN BB36 [get_ports CS_nSRST]
+set_property PACKAGE_PIN BB37 [get_ports CS_nTRST]
+set_property PACKAGE_PIN AW33 [get_ports CS_T_CLK]
+set_property PACKAGE_PIN AY35 [get_ports CS_T_CTL]
+set_property PACKAGE_PIN AW34 [get_ports {CS_T_D[0]}]
+set_property PACKAGE_PIN AT34 [get_ports {CS_T_D[1]}]
+set_property PACKAGE_PIN AU34 [get_ports {CS_T_D[2]}]
+set_property PACKAGE_PIN AV36 [get_ports {CS_T_D[3]}]
+set_property PACKAGE_PIN AW36 [get_ports {CS_T_D[4]}]
+set_property PACKAGE_PIN AT35 [get_ports {CS_T_D[5]}]
+set_property PACKAGE_PIN AU35 [get_ports {CS_T_D[6]}]
+set_property PACKAGE_PIN AU36 [get_ports {CS_T_D[7]}]
+set_property PACKAGE_PIN AV37 [get_ports {CS_T_D[8]}]
+set_property PACKAGE_PIN AW35 [get_ports {CS_T_D[9]}]
+set_property PACKAGE_PIN AY36 [get_ports {CS_T_D[10]}]
+set_property PACKAGE_PIN AY37 [get_ports {CS_T_D[11]}]
+set_property PACKAGE_PIN BB34 [get_ports {CS_T_D[12]}]
+set_property PACKAGE_PIN BB35 [get_ports {CS_T_D[13]}]
+set_property PACKAGE_PIN BA37 [get_ports {CS_T_D[14]}]
+set_property PACKAGE_PIN BA38 [get_ports {CS_T_D[15]}]
+set_property PACKAGE_PIN AV33 [get_ports CS_TCK]
+set_property PACKAGE_PIN BA35 [get_ports CS_TDI]
+set_property PACKAGE_PIN AW38 [get_ports CS_TDO]
+set_property PACKAGE_PIN AY38 [get_ports CS_TMS]
+# not used
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[0]}]
+#set_property PACKAGE_PIN J19 [get_ports {DDR_CHIPID[0]}]
+#set_property IOSTANDARD POD12_DCI [get_ports {DDR_CHIPID[1]}]
+#set_property PACKAGE_PIN G20 [get_ports {DDR_CHIPID[1]}]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nALERT]
+#set_property PACKAGE_PIN P15 [get_ports DDR_nALERT]
+#set_property IOSTANDARD POD12_DCI [get_ports DDR_nEVENT]
+#set_property PACKAGE_PIN C17 [get_ports DDR_nEVENT]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_PARITY]
+# set_property PACKAGE_PIN D18 [get_ports DDR_PARITY]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SCL]
+# set_property PACKAGE_PIN N21 [get_ports DDR_SCL]
+# set_property IOSTANDARD POD12_DCI [get_ports DDR_SDA]
+# set_property PACKAGE_PIN P21 [get_ports DDR_SDA]
+# set_property PACKAGE_PIN AC42 [get_ports {DP_M2C_N[0]}]
+# set_property PACKAGE_PIN AJ42 [get_ports {DP_M2C_N[1]}]
+# set_property PACKAGE_PIN AE42 [get_ports {DP_M2C_N[2]}]
+# set_property PACKAGE_PIN W42 [get_ports {DP_M2C_N[3]}]
+# set_property PACKAGE_PIN R42 [get_ports {DP_M2C_N[4]}]
+# set_property PACKAGE_PIN L42 [get_ports {DP_M2C_N[5]}]
+# set_property PACKAGE_PIN N42 [get_ports {DP_M2C_N[6]}]
+# set_property PACKAGE_PIN U42 [get_ports {DP_M2C_N[7]}]
+# set_property PACKAGE_PIN AA42 [get_ports {DP_M2C_N[8]}]
+# set_property PACKAGE_PIN AG42 [get_ports {DP_M2C_N[9]}]
+# set_property PACKAGE_PIN AC41 [get_ports {DP_M2C_P[0]}]
+# set_property PACKAGE_PIN AJ41 [get_ports {DP_M2C_P[1]}]
+# set_property PACKAGE_PIN AE41 [get_ports {DP_M2C_P[2]}]
+# set_property PACKAGE_PIN W41 [get_ports {DP_M2C_P[3]}]
+# set_property PACKAGE_PIN R41 [get_ports {DP_M2C_P[4]}]
+# set_property PACKAGE_PIN L41 [get_ports {DP_M2C_P[5]}]
+# set_property PACKAGE_PIN N41 [get_ports {DP_M2C_P[6]}]
+# set_property PACKAGE_PIN U41 [get_ports {DP_M2C_P[7]}]
+# set_property PACKAGE_PIN AA41 [get_ports {DP_M2C_P[8]}]
+# set_property PACKAGE_PIN AG41 [get_ports {DP_M2C_P[9]}]
+set_property PACKAGE_PIN AG34 [get_ports HDMI_CSCL]
+set_property PACKAGE_PIN AE33 [get_ports HDMI_CSDA]
+set_property PACKAGE_PIN AF33 [get_ports HDMI_INT]
+set_property PACKAGE_PIN W29 [get_ports EMMC_CLK]
+set_property PACKAGE_PIN AC34 [get_ports EMMC_CMD]
+set_property PACKAGE_PIN Y32 [get_ports {EMMC_DAT[0]}]
+set_property PACKAGE_PIN Y33 [get_ports {EMMC_DAT[1]}]
+set_property PACKAGE_PIN W33 [get_ports {EMMC_DAT[2]}]
+set_property PACKAGE_PIN W34 [get_ports {EMMC_DAT[3]}]
+set_property PACKAGE_PIN AA34 [get_ports {EMMC_DAT[4]}]
+set_property PACKAGE_PIN AB34 [get_ports {EMMC_DAT[5]}]
+set_property PACKAGE_PIN W31 [get_ports {EMMC_DAT[6]}]
+set_property PACKAGE_PIN Y31 [get_ports {EMMC_DAT[7]}]
+set_property PACKAGE_PIN AE32 [get_ports EMMC_DS]
+set_property PACKAGE_PIN W30 [get_ports EMMC_nRST]
+set_property PACKAGE_PIN AK23 [get_ports ETH_INT]
+set_property PACKAGE_PIN AL24 [get_ports ETH_nCS]
+set_property PACKAGE_PIN AJ23 [get_ports ETH_nOE]
+# not used
+# set_property PACKAGE_PIN AV38 [get_ports FMC_CLK_DIR]
+# set_property PACKAGE_PIN AL42 [get_ports FMC_nPRSNT]
+# set_property PACKAGE_PIN BB40 [get_ports {HA_N[2]}]
+# set_property PACKAGE_PIN BA41 [get_ports {HA_N[3]}]
+# set_property PACKAGE_PIN AY40 [get_ports {HA_N[4]}]
+# set_property PACKAGE_PIN AU42 [get_ports {HA_N[5]}]
+# set_property PACKAGE_PIN AY42 [get_ports {HA_N[6]}]
+# set_property PACKAGE_PIN AW41 [get_ports {HA_N[7]}]
+# set_property PACKAGE_PIN AU37 [get_ports {HA_N[8]}]
+# set_property PACKAGE_PIN AT42 [get_ports {HA_N[9]}]
+# set_property PACKAGE_PIN AT38 [get_ports {HA_N[10]}]
+# set_property PACKAGE_PIN AV42 [get_ports {HA_N[11]}]
+# set_property PACKAGE_PIN AR37 [get_ports {HA_N[12]}]
+# set_property PACKAGE_PIN AN42 [get_ports {HA_N[13]}]
+# set_property PACKAGE_PIN AP38 [get_ports {HA_N[14]}]
+# set_property PACKAGE_PIN AN37 [get_ports {HA_N[15]}]
+# set_property PACKAGE_PIN AM42 [get_ports {HA_N[16]}]
+# set_property PACKAGE_PIN AR41 [get_ports {HA_N[18]}]
+# set_property PACKAGE_PIN AM39 [get_ports {HA_N[19]}]
+# set_property PACKAGE_PIN AR40 [get_ports {HA_N[20]}]
+# set_property PACKAGE_PIN AM40 [get_ports {HA_N[21]}]
+# set_property PACKAGE_PIN AK38 [get_ports {HA_N[22]}]
+# set_property PACKAGE_PIN AL38 [get_ports {HA_N[23]}]
+# set_property PACKAGE_PIN AT39 [get_ports {HA_P[0]}]
+# set_property PACKAGE_PIN AT40 [get_ports {HA_N[0]}]
+# set_property PACKAGE_PIN AU39 [get_ports {HA_P[1]}]
+# set_property PACKAGE_PIN AU40 [get_ports {HA_N[1]}]
+# set_property PACKAGE_PIN BA39 [get_ports {HA_P[2]}]
+# set_property PACKAGE_PIN BA40 [get_ports {HA_P[3]}]
+# set_property PACKAGE_PIN AW39 [get_ports {HA_P[4]}]
+# set_property PACKAGE_PIN AU41 [get_ports {HA_P[5]}]
+# set_property PACKAGE_PIN AY41 [get_ports {HA_P[6]}]
+# set_property PACKAGE_PIN AW40 [get_ports {HA_P[7]}]
+# set_property PACKAGE_PIN AT37 [get_ports {HA_P[8]}]
+# set_property PACKAGE_PIN AR42 [get_ports {HA_P[9]}]
+# set_property PACKAGE_PIN AR38 [get_ports {HA_P[10]}]
+# set_property PACKAGE_PIN AV41 [get_ports {HA_P[11]}]
+# set_property PACKAGE_PIN AR36 [get_ports {HA_P[12]}]
+# set_property PACKAGE_PIN AN41 [get_ports {HA_P[13]}]
+# set_property PACKAGE_PIN AN38 [get_ports {HA_P[14]}]
+# set_property PACKAGE_PIN AM37 [get_ports {HA_P[15]}]
+# set_property PACKAGE_PIN AM41 [get_ports {HA_P[16]}]
+# set_property PACKAGE_PIN AN39 [get_ports {HA_P[17]}]
+# set_property PACKAGE_PIN AP39 [get_ports {HA_N[17]}]
+# set_property PACKAGE_PIN AP41 [get_ports {HA_P[18]}]
+# set_property PACKAGE_PIN AL39 [get_ports {HA_P[19]}]
+# set_property PACKAGE_PIN AP40 [get_ports {HA_P[20]}]
+# set_property PACKAGE_PIN AL40 [get_ports {HA_P[21]}]
+# set_property PACKAGE_PIN AK37 [get_ports {HA_P[22]}]
+# set_property PACKAGE_PIN AL37 [get_ports {HA_P[23]}]
+# set_property PACKAGE_PIN T32 [get_ports {HB_N[1]}]
+# set_property PACKAGE_PIN V33 [get_ports {HB_N[2]}]
+# set_property PACKAGE_PIN V29 [get_ports {HB_N[3]}]
+# set_property PACKAGE_PIN T30 [get_ports {HB_N[4]}]
+# set_property PACKAGE_PIN T34 [get_ports {HB_N[5]}]
+# set_property PACKAGE_PIN R32 [get_ports {HB_N[7]}]
+# set_property PACKAGE_PIN P29 [get_ports {HB_N[8]}]
+# set_property PACKAGE_PIN P30 [get_ports {HB_N[9]}]
+# set_property PACKAGE_PIN K28 [get_ports {HB_N[10]}]
+# set_property PACKAGE_PIN L29 [get_ports {HB_N[11]}]
+# set_property PACKAGE_PIN K31 [get_ports {HB_N[12]}]
+# set_property PACKAGE_PIN L33 [get_ports {HB_N[13]}]
+# set_property PACKAGE_PIN U31 [get_ports {HB_N[14]}]
+# set_property PACKAGE_PIN N33 [get_ports {HB_N[15]}]
+# set_property PACKAGE_PIN L34 [get_ports {HB_N[16]}]
+# set_property PACKAGE_PIN R28 [get_ports {HB_N[18]}]
+# set_property PACKAGE_PIN N27 [get_ports {HB_N[19]}]
+# set_property PACKAGE_PIN U34 [get_ports {HB_N[20]}]
+# set_property PACKAGE_PIN N34 [get_ports {HB_N[21]}]
+# set_property PACKAGE_PIN N31 [get_ports {HB_P[0]}]
+# set_property PACKAGE_PIN M31 [get_ports {HB_N[0]}]
+# set_property PACKAGE_PIN U32 [get_ports {HB_P[1]}]
+# set_property PACKAGE_PIN V32 [get_ports {HB_P[2]}]
+# set_property PACKAGE_PIN V28 [get_ports {HB_P[3]}]
+# set_property PACKAGE_PIN U30 [get_ports {HB_P[4]}]
+# set_property PACKAGE_PIN T33 [get_ports {HB_P[5]}]
+# set_property PACKAGE_PIN M30 [get_ports {HB_P[6]}]
+# set_property PACKAGE_PIN L30 [get_ports {HB_N[6]}]
+# set_property PACKAGE_PIN R31 [get_ports {HB_P[7]}]
+# set_property PACKAGE_PIN P28 [get_ports {HB_P[8]}]
+# set_property PACKAGE_PIN R30 [get_ports {HB_P[9]}]
+# set_property PACKAGE_PIN L28 [get_ports {HB_P[10]}]
+# set_property PACKAGE_PIN M29 [get_ports {HB_P[11]}]
+# set_property PACKAGE_PIN K30 [get_ports {HB_P[12]}]
+# set_property PACKAGE_PIN L32 [get_ports {HB_P[13]}]
+# set_property PACKAGE_PIN V31 [get_ports {HB_P[14]}]
+# set_property PACKAGE_PIN P33 [get_ports {HB_P[15]}]
+# set_property PACKAGE_PIN M34 [get_ports {HB_P[16]}]
+# set_property PACKAGE_PIN N32 [get_ports {HB_P[17]}]
+# set_property PACKAGE_PIN M32 [get_ports {HB_N[17]}]
+# set_property PACKAGE_PIN T28 [get_ports {HB_P[18]}]
+# set_property PACKAGE_PIN N26 [get_ports {HB_P[19]}]
+# set_property PACKAGE_PIN V34 [get_ports {HB_P[20]}]
+# set_property PACKAGE_PIN P34 [get_ports {HB_P[21]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {CLK_CFG}]
+# set_property PACKAGE_PIN AT27 [get_ports {CLK_CFG}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_CSIB}]
+# set_property PACKAGE_PIN BA27 [get_ports {IOFPGA_CSIB}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[4]}]
+# set_property PACKAGE_PIN AV26 [get_ports {IOFPGA_D[4]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[5]}]
+# set_property PACKAGE_PIN AV27 [get_ports {IOFPGA_D[5]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[6]}]
+# set_property PACKAGE_PIN AU29 [get_ports {IOFPGA_D[6]}]
+# set_property IOSTANDARD LVCMOS33 [get_ports {IOFPGA_D[7]}]
+# set_property PACKAGE_PIN AV29 [get_ports {IOFPGA_D[7]}]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NRST]
+set_property PACKAGE_PIN AV31 [get_ports IOFPGA_NRST]
+set_property IOSTANDARD LVCMOS18 [get_ports IOFPGA_NSPIR]
+set_property PACKAGE_PIN AV32 [get_ports IOFPGA_NSPIR]
+set_property IOSTANDARD LVCMOS33 [get_ports IOFPGA_SYSWDT]
+set_property PACKAGE_PIN AU20 [get_ports IOFPGA_SYSWDT]
+# not used
+# set_property PACKAGE_PIN AN27 [get_ports {LA_N[2]}]
+# set_property PACKAGE_PIN AP30 [get_ports {LA_N[3]}]
+# set_property PACKAGE_PIN AN29 [get_ports {LA_N[4]}]
+# set_property PACKAGE_PIN AR35 [get_ports {LA_N[5]}]
+# set_property PACKAGE_PIN AR33 [get_ports {LA_N[6]}]
+# set_property PACKAGE_PIN AN32 [get_ports {LA_N[7]}]
+# set_property PACKAGE_PIN AP31 [get_ports {LA_N[8]}]
+# set_property PACKAGE_PIN AN34 [get_ports {LA_N[9]}]
+# set_property PACKAGE_PIN AL35 [get_ports {LA_N[10]}]
+# set_property PACKAGE_PIN AM36 [get_ports {LA_N[11]}]
+# set_property PACKAGE_PIN AP34 [get_ports {LA_N[12]}]
+# set_property PACKAGE_PIN AL32 [get_ports {LA_N[13]}]
+# set_property PACKAGE_PIN AK36 [get_ports {LA_N[14]}]
+# set_property PACKAGE_PIN AJ34 [get_ports {LA_N[15]}]
+# set_property PACKAGE_PIN AL33 [get_ports {LA_N[16]}]
+# set_property PACKAGE_PIN AJ29 [get_ports {LA_N[19]}]
+# set_property PACKAGE_PIN AJ33 [get_ports {LA_N[20]}]
+# set_property PACKAGE_PIN AH29 [get_ports {LA_N[21]}]
+# set_property PACKAGE_PIN AH31 [get_ports {LA_N[22]}]
+# set_property PACKAGE_PIN AG30 [get_ports {LA_N[23]}]
+# set_property PACKAGE_PIN G32 [get_ports {LA_N[24]}]
+# set_property PACKAGE_PIN H34 [get_ports {LA_N[25]}]
+# set_property PACKAGE_PIN H31 [get_ports {LA_N[26]}]
+# set_property PACKAGE_PIN K33 [get_ports {LA_N[27]}]
+# set_property PACKAGE_PIN H29 [get_ports {LA_N[28]}]
+# set_property PACKAGE_PIN H33 [get_ports {LA_N[29]}]
+# set_property PACKAGE_PIN F34 [get_ports {LA_N[30]}]
+# set_property PACKAGE_PIN E33 [get_ports {LA_N[31]}]
+# set_property PACKAGE_PIN C34 [get_ports {LA_N[32]}]
+# set_property PACKAGE_PIN G30 [get_ports {LA_N[33]}]
+# set_property PACKAGE_PIN AM29 [get_ports {LA_P[0]}]
+# set_property PACKAGE_PIN AM30 [get_ports {LA_N[0]}]
+# set_property PACKAGE_PIN AL29 [get_ports {LA_P[1]}]
+# set_property PACKAGE_PIN AL30 [get_ports {LA_N[1]}]
+# set_property PACKAGE_PIN AM27 [get_ports {LA_P[2]}]
+# set_property PACKAGE_PIN AP29 [get_ports {LA_P[3]}]
+# set_property PACKAGE_PIN AN28 [get_ports {LA_P[4]}]
+# set_property PACKAGE_PIN AP35 [get_ports {LA_P[5]}]
+# set_property PACKAGE_PIN AP33 [get_ports {LA_P[6]}]
+# set_property PACKAGE_PIN AM32 [get_ports {LA_P[7]}]
+# set_property PACKAGE_PIN AN31 [get_ports {LA_P[8]}]
+# set_property PACKAGE_PIN AM34 [get_ports {LA_P[9]}]
+# set_property PACKAGE_PIN AL34 [get_ports {LA_P[10]}]
+# set_property PACKAGE_PIN AM35 [get_ports {LA_P[11]}]
+# set_property PACKAGE_PIN AN33 [get_ports {LA_P[12]}]
+# set_property PACKAGE_PIN AK32 [get_ports {LA_P[13]}]
+# set_property PACKAGE_PIN AK35 [get_ports {LA_P[14]}]
+# set_property PACKAGE_PIN AH34 [get_ports {LA_P[15]}]
+# set_property PACKAGE_PIN AK33 [get_ports {LA_P[16]}]
+# set_property PACKAGE_PIN AK30 [get_ports {LA_P[17]}]
+# set_property PACKAGE_PIN AK31 [get_ports {LA_N[17]}]
+# set_property PACKAGE_PIN AJ30 [get_ports {LA_P[18]}]
+# set_property PACKAGE_PIN AJ31 [get_ports {LA_N[18]}]
+# set_property PACKAGE_PIN AJ28 [get_ports {LA_P[19]}]
+# set_property PACKAGE_PIN AH33 [get_ports {LA_P[20]}]
+# set_property PACKAGE_PIN AH28 [get_ports {LA_P[21]}]
+# set_property PACKAGE_PIN AG31 [get_ports {LA_P[22]}]
+# set_property PACKAGE_PIN AG29 [get_ports {LA_P[23]}]
+# set_property PACKAGE_PIN H32 [get_ports {LA_P[24]}]
+# set_property PACKAGE_PIN J34 [get_ports {LA_P[25]}]
+# set_property PACKAGE_PIN J30 [get_ports {LA_P[26]}]
+# set_property PACKAGE_PIN K32 [get_ports {LA_P[27]}]
+# set_property PACKAGE_PIN J29 [get_ports {LA_P[28]}]
+# set_property PACKAGE_PIN J33 [get_ports {LA_P[29]}]
+# set_property PACKAGE_PIN G34 [get_ports {LA_P[30]}]
+# set_property PACKAGE_PIN F33 [get_ports {LA_P[31]}]
+# set_property PACKAGE_PIN D34 [get_ports {LA_P[32]}]
+# set_property PACKAGE_PIN G29 [get_ports {LA_P[33]}]
+set_property PACKAGE_PIN AM17 [get_ports {MMB_DATA[0]}]
+set_property PACKAGE_PIN AL14 [get_ports {MMB_DATA[1]}]
+set_property PACKAGE_PIN AK15 [get_ports {MMB_DATA[2]}]
+set_property PACKAGE_PIN AK17 [get_ports {MMB_DATA[3]}]
+set_property PACKAGE_PIN AM14 [get_ports {MMB_DATA[4]}]
+set_property PACKAGE_PIN AN13 [get_ports {MMB_DATA[5]}]
+set_property PACKAGE_PIN AM11 [get_ports {MMB_DATA[6]}]
+set_property PACKAGE_PIN AN11 [get_ports {MMB_DATA[7]}]
+set_property PACKAGE_PIN AR13 [get_ports {MMB_DATA[8]}]
+set_property PACKAGE_PIN AR12 [get_ports {MMB_DATA[9]}]
+set_property PACKAGE_PIN AL10 [get_ports {MMB_DATA[10]}]
+set_property PACKAGE_PIN AM10 [get_ports {MMB_DATA[11]}]
+set_property PACKAGE_PIN AM12 [get_ports {MMB_DATA[12]}]
+set_property PACKAGE_PIN AN12 [get_ports {MMB_DATA[13]}]
+set_property PACKAGE_PIN AP13 [get_ports {MMB_DATA[14]}]
+set_property PACKAGE_PIN AK13 [get_ports {MMB_DATA[15]}]
+set_property PACKAGE_PIN AK12 [get_ports {MMB_DATA[16]}]
+set_property PACKAGE_PIN AK11 [get_ports {MMB_DATA[17]}]
+set_property PACKAGE_PIN AK10 [get_ports {MMB_DATA[18]}]
+set_property PACKAGE_PIN AH13 [get_ports {MMB_DATA[19]}]
+set_property PACKAGE_PIN AJ13 [get_ports {MMB_DATA[20]}]
+set_property PACKAGE_PIN AJ11 [get_ports {MMB_DATA[21]}]
+set_property PACKAGE_PIN AJ10 [get_ports {MMB_DATA[22]}]
+set_property PACKAGE_PIN AH12 [get_ports {MMB_DATA[23]}]
+set_property PACKAGE_PIN AH11 [get_ports MMB_DE]
+set_property PACKAGE_PIN AG12 [get_ports MMB_HS]
+set_property PACKAGE_PIN AH14 [get_ports MMB_IDCLK]
+set_property PACKAGE_PIN AF29 [get_ports MMB_SCK]
+set_property PACKAGE_PIN AC28 [get_ports {MMB_SD[0]}]
+set_property PACKAGE_PIN AC29 [get_ports {MMB_SD[1]}]
+set_property PACKAGE_PIN AE27 [get_ports {MMB_SD[2]}]
+set_property PACKAGE_PIN AF34 [get_ports {MMB_SD[3]}]
+set_property PACKAGE_PIN AG11 [get_ports MMB_VS]
+set_property PACKAGE_PIN AF30 [get_ports MMB_WS]
+set_property PACKAGE_PIN AL15 [get_ports {OSCCLK[0]}]
+set_property PACKAGE_PIN AK16 [get_ports {OSCCLK[1]}]
+set_property PACKAGE_PIN AY32 [get_ports {OSCCLK[2]}]
+set_property PACKAGE_PIN AY30 [get_ports {OSCCLK[3]}]
+set_property PACKAGE_PIN AC31 [get_ports {OSCCLK[4]}]
+set_property PACKAGE_PIN AC32 [get_ports {OSCCLK[5]}]
+set_property PACKAGE_PIN AT29 [get_ports PB_IRQ]
+
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D0]
+set_property PACKAGE_PIN AU24 [get_ports QSPI_D0]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D1]
+set_property PACKAGE_PIN AV24 [get_ports QSPI_D1]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D2]
+set_property PACKAGE_PIN AV21 [get_ports QSPI_D2]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_D3]
+set_property PACKAGE_PIN AV22 [get_ports QSPI_D3]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_nCS]
+set_property PACKAGE_PIN AT24 [get_ports QSPI_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports QSPI_SCLK]
+set_property PACKAGE_PIN AT25 [get_ports QSPI_SCLK]
+# not used
+# set_property PACKAGE_PIN AL13 [get_ports SATA_CLK_P]
+# set_property PACKAGE_PIN AL12 [get_ports SATA_CLK_N]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[0]}]
+set_property PACKAGE_PIN AW14 [get_ports {SH0_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[1]}]
+set_property PACKAGE_PIN AW13 [get_ports {SH0_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[2]}]
+set_property PACKAGE_PIN AW15 [get_ports {SH0_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[3]}]
+set_property PACKAGE_PIN AY15 [get_ports {SH0_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[4]}]
+set_property PACKAGE_PIN AY13 [get_ports {SH0_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[5]}]
+set_property PACKAGE_PIN AY12 [get_ports {SH0_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[6]}]
+set_property PACKAGE_PIN BA15 [get_ports {SH0_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[7]}]
+set_property PACKAGE_PIN BB14 [get_ports {SH0_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[8]}]
+set_property PACKAGE_PIN BA12 [get_ports {SH0_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[9]}]
+set_property PACKAGE_PIN BB12 [get_ports {SH0_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[10]}]
+set_property PACKAGE_PIN BA14 [get_ports {SH0_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[11]}]
+set_property PACKAGE_PIN BA13 [get_ports {SH0_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[12]}]
+set_property PACKAGE_PIN BB15 [get_ports {SH0_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[13]}]
+set_property PACKAGE_PIN AU12 [get_ports {SH0_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[14]}]
+set_property PACKAGE_PIN AV12 [get_ports {SH0_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[15]}]
+set_property PACKAGE_PIN AV17 [get_ports {SH0_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[16]}]
+set_property PACKAGE_PIN AV16 [get_ports {SH0_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH0_IO[17]}]
+set_property PACKAGE_PIN AT14 [get_ports {SH0_IO[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[0]}]
+set_property PACKAGE_PIN AT17 [get_ports {SH1_IO[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[1]}]
+set_property PACKAGE_PIN AU17 [get_ports {SH1_IO[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[2]}]
+set_property PACKAGE_PIN AV19 [get_ports {SH1_IO[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[3]}]
+set_property PACKAGE_PIN AW19 [get_ports {SH1_IO[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[4]}]
+set_property PACKAGE_PIN AW20 [get_ports {SH1_IO[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[5]}]
+set_property PACKAGE_PIN BA19 [get_ports {SH1_IO[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[6]}]
+set_property PACKAGE_PIN BA18 [get_ports {SH1_IO[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[7]}]
+set_property PACKAGE_PIN AY20 [get_ports {SH1_IO[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[8]}]
+set_property PACKAGE_PIN BA20 [get_ports {SH1_IO[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[9]}]
+set_property PACKAGE_PIN BA17 [get_ports {SH1_IO[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[10]}]
+set_property PACKAGE_PIN BB17 [get_ports {SH1_IO[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[11]}]
+set_property PACKAGE_PIN BB20 [get_ports {SH1_IO[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[12]}]
+set_property PACKAGE_PIN BB19 [get_ports {SH1_IO[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[13]}]
+set_property PACKAGE_PIN AW16 [get_ports {SH1_IO[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[14]}]
+set_property PACKAGE_PIN AY16 [get_ports {SH1_IO[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[15]}]
+set_property PACKAGE_PIN AY18 [get_ports {SH1_IO[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[16]}]
+set_property PACKAGE_PIN AY17 [get_ports {SH1_IO[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN BB16 [get_ports {SH1_IO[17]}]
+set_property PACKAGE_PIN AL25 [get_ports SH_ADC_CK]
+set_property PACKAGE_PIN AM25 [get_ports SH_ADC_CS]
+set_property PACKAGE_PIN AP25 [get_ports SH_ADC_DI]
+set_property PACKAGE_PIN AP26 [get_ports SH_ADC_DO]
+set_property IOSTANDARD LVCMOS33 [get_ports SH_nRST]
+set_property PACKAGE_PIN AU14 [get_ports SH_nRST]
+set_property PACKAGE_PIN AK20 [get_ports {SMBF_ADDR[0]}]
+set_property PACKAGE_PIN AK21 [get_ports {SMBF_ADDR[1]}]
+set_property PACKAGE_PIN AJ18 [get_ports {SMBF_ADDR[2]}]
+set_property PACKAGE_PIN AJ19 [get_ports {SMBF_ADDR[3]}]
+set_property PACKAGE_PIN AH21 [get_ports {SMBF_ADDR[4]}]
+set_property PACKAGE_PIN AJ21 [get_ports {SMBF_ADDR[5]}]
+set_property PACKAGE_PIN AH19 [get_ports {SMBF_ADDR[6]}]
+set_property PACKAGE_PIN AK22 [get_ports {SMBF_DATA[0]}]
+set_property PACKAGE_PIN AL22 [get_ports {SMBF_DATA[1]}]
+set_property PACKAGE_PIN AL19 [get_ports {SMBF_DATA[2]}]
+set_property PACKAGE_PIN AL20 [get_ports {SMBF_DATA[3]}]
+set_property PACKAGE_PIN AH18 [get_ports {SMBF_DATA[4]}]
+set_property PACKAGE_PIN AM19 [get_ports {SMBF_DATA[5]}]
+set_property PACKAGE_PIN AN19 [get_ports {SMBF_DATA[6]}]
+set_property PACKAGE_PIN AP19 [get_ports {SMBF_DATA[7]}]
+set_property PACKAGE_PIN AP20 [get_ports {SMBF_DATA[8]}]
+set_property PACKAGE_PIN AM20 [get_ports {SMBF_DATA[9]}]
+set_property PACKAGE_PIN AN21 [get_ports {SMBF_DATA[10]}]
+set_property PACKAGE_PIN AP21 [get_ports {SMBF_DATA[11]}]
+set_property PACKAGE_PIN AR22 [get_ports {SMBF_DATA[12]}]
+set_property PACKAGE_PIN AM21 [get_ports {SMBF_DATA[13]}]
+set_property PACKAGE_PIN AM22 [get_ports {SMBF_DATA[14]}]
+set_property PACKAGE_PIN AN22 [get_ports {SMBF_DATA[15]}]
+set_property PACKAGE_PIN AJ20 [get_ports SMBF_FIFOSEL]
+set_property PACKAGE_PIN AN23 [get_ports SMBF_nOE]
+set_property PACKAGE_PIN AL23 [get_ports SMBF_nRST]
+set_property PACKAGE_PIN AP23 [get_ports SMBF_nWE]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[16]}]
+set_property PACKAGE_PIN AR26 [get_ports {SMBM_A[16]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[17]}]
+set_property PACKAGE_PIN AT22 [get_ports {SMBM_A[17]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[18]}]
+set_property PACKAGE_PIN AT23 [get_ports {SMBM_A[18]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[19]}]
+set_property PACKAGE_PIN AU21 [get_ports {SMBM_A[19]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[20]}]
+set_property PACKAGE_PIN AY22 [get_ports {SMBM_A[20]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[21]}]
+set_property PACKAGE_PIN BA22 [get_ports {SMBM_A[21]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[22]}]
+set_property PACKAGE_PIN AW21 [get_ports {SMBM_A[22]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[23]}]
+set_property PACKAGE_PIN AY21 [get_ports {SMBM_A[23]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[24]}]
+set_property PACKAGE_PIN BA23 [get_ports {SMBM_A[24]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_A[25]}]
+set_property PACKAGE_PIN BA24 [get_ports {SMBM_A[25]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_CLK]
+set_property PACKAGE_PIN AY25 [get_ports SMBM_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[0]}]
+set_property PACKAGE_PIN BB21 [get_ports {SMBM_D[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[1]}]
+set_property PACKAGE_PIN BB22 [get_ports {SMBM_D[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[2]}]
+set_property PACKAGE_PIN AW24 [get_ports {SMBM_D[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {SMBM_D[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[4]}]
+set_property PACKAGE_PIN AW23 [get_ports {SMBM_D[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[5]}]
+set_property PACKAGE_PIN AY23 [get_ports {SMBM_D[5]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[6]}]
+set_property PACKAGE_PIN BB24 [get_ports {SMBM_D[6]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[7]}]
+set_property PACKAGE_PIN AY27 [get_ports {SMBM_D[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[8]}]
+set_property PACKAGE_PIN AY26 [get_ports {SMBM_D[8]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[9]}]
+set_property PACKAGE_PIN AY28 [get_ports {SMBM_D[9]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[10]}]
+set_property PACKAGE_PIN BA28 [get_ports {SMBM_D[10]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[11]}]
+set_property PACKAGE_PIN BA25 [get_ports {SMBM_D[11]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[12]}]
+set_property PACKAGE_PIN BB25 [get_ports {SMBM_D[12]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[13]}]
+set_property PACKAGE_PIN AW28 [get_ports {SMBM_D[13]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[14]}]
+set_property PACKAGE_PIN AW29 [get_ports {SMBM_D[14]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_D[15]}]
+set_property PACKAGE_PIN BB26 [get_ports {SMBM_D[15]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[0]}]
+set_property PACKAGE_PIN AU26 [get_ports {SMBM_nBL[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nBL[1]}]
+set_property PACKAGE_PIN AR28 [get_ports {SMBM_nBL[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[1]}]
+set_property PACKAGE_PIN BB27 [get_ports {SMBM_nE[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[2]}]
+set_property PACKAGE_PIN AU27 [get_ports {SMBM_nE[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[3]}]
+set_property PACKAGE_PIN AV28 [get_ports {SMBM_nE[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {SMBM_nE[4]}]
+set_property PACKAGE_PIN AU25 [get_ports {SMBM_nE[4]}]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nOE]
+set_property PACKAGE_PIN AT28 [get_ports SMBM_nOE]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWAIT]
+set_property PACKAGE_PIN AP28 [get_ports SMBM_nWAIT]
+set_property IOSTANDARD LVCMOS33 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AR27 [get_ports SMBM_nWE]
+set_property PACKAGE_PIN AF28 [get_ports {UART_RX_F[0]}]
+set_property PACKAGE_PIN AE31 [get_ports {UART_RX_F[1]}]
+set_property PACKAGE_PIN AE28 [get_ports {UART_RX_F[2]}]
+set_property PACKAGE_PIN AD30 [get_ports {UART_RX_F[3]}]
+set_property PACKAGE_PIN AF27 [get_ports {UART_TX_F[0]}]
+set_property PACKAGE_PIN AE30 [get_ports {UART_TX_F[1]}]
+set_property PACKAGE_PIN AD28 [get_ports {UART_TX_F[2]}]
+set_property PACKAGE_PIN AD29 [get_ports {UART_TX_F[3]}]
+set_property PACKAGE_PIN AN26 [get_ports USB_DACK]
+set_property PACKAGE_PIN AN24 [get_ports USB_DREQ]
+set_property PACKAGE_PIN AP24 [get_ports USB_INT]
+set_property PACKAGE_PIN AM26 [get_ports USB_nCS]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CLK]
+set_property PACKAGE_PIN AU15 [get_ports USD_CLK]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_CMD]
+set_property PACKAGE_PIN AU16 [get_ports USD_CMD]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[0]}]
+set_property PACKAGE_PIN AV14 [get_ports {USD_DAT[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[1]}]
+set_property PACKAGE_PIN AV13 [get_ports {USD_DAT[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[2]}]
+set_property PACKAGE_PIN AT13 [get_ports {USD_DAT[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {USD_DAT[3]}]
+set_property PACKAGE_PIN AT12 [get_ports {USD_DAT[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports USD_NCD]
+set_property PACKAGE_PIN AT15 [get_ports USD_NCD]
+set_property PACKAGE_PIN AU32 [get_ports {USER_nLED[0]}]
+set_property PACKAGE_PIN AU30 [get_ports {USER_nLED[1]}]
+set_property PACKAGE_PIN AU31 [get_ports {USER_nLED[2]}]
+set_property PACKAGE_PIN AR32 [get_ports {USER_nLED[3]}]
+set_property PACKAGE_PIN AT33 [get_ports {USER_nLED[4]}]
+set_property PACKAGE_PIN AW30 [get_ports {USER_nLED[5]}]
+set_property PACKAGE_PIN AW31 [get_ports {USER_nLED[6]}]
+set_property PACKAGE_PIN AR30 [get_ports {USER_nLED[7]}]
+set_property PACKAGE_PIN BB31 [get_ports {USER_nLED[8]}]
+set_property PACKAGE_PIN BB32 [get_ports {USER_nLED[9]}]
+set_property PACKAGE_PIN AT30 [get_ports {USER_nPB[0]}]
+set_property PACKAGE_PIN AT32 [get_ports {USER_nPB[1]}]
+set_property PACKAGE_PIN BA29 [get_ports {USER_SW[0]}]
+set_property PACKAGE_PIN BB29 [get_ports {USER_SW[1]}]
+set_property PACKAGE_PIN BA32 [get_ports {USER_SW[2]}]
+set_property PACKAGE_PIN BA33 [get_ports {USER_SW[3]}]
+set_property PACKAGE_PIN BA30 [get_ports {USER_SW[4]}]
+set_property PACKAGE_PIN BB30 [get_ports {USER_SW[5]}]
+set_property PACKAGE_PIN AY33 [get_ports {USER_SW[6]}]
+set_property PACKAGE_PIN AY31 [get_ports {USER_SW[7]}]
+set_property IOSTANDARD LVCMOS33 [get_ports WDOG_RREQ]
+set_property PACKAGE_PIN AU19 [get_ports WDOG_RREQ]
+
+# native DDR pin names
+
+# set_property PACKAGE_PIN A17 [get_ports {c0_ddr4_dq[37]}]
+# set_property PACKAGE_PIN F24 [get_ports {c0_ddr4_dq[54]}]
+# set_property PACKAGE_PIN F23 [get_ports {c0_ddr4_dq[55]}]
+# set_property PACKAGE_PIN B15 [get_ports {c0_ddr4_dq[28]}]
+# set_property PACKAGE_PIN D23 [get_ports {c0_ddr4_dq[52]}]
+# set_property PACKAGE_PIN D24 [get_ports {c0_ddr4_dq[53]}]
+# set_property PACKAGE_PIN C24 [get_ports {c0_ddr4_dm_dbi_n[5]}]
+# set_property PACKAGE_PIN A22 [get_ports {c0_ddr4_dq[46]}]
+# set_property PACKAGE_PIN A23 [get_ports {c0_ddr4_dq[47]}]
+# set_property PACKAGE_PIN C13 [get_ports {c0_ddr4_dq[29]}]
+# set_property PACKAGE_PIN A14 [get_ports {c0_ddr4_dq[27]}]
+# set_property PACKAGE_PIN E22 [get_ports {c0_ddr4_dqs_t[6]}]
+# set_property PACKAGE_PIN E21 [get_ports {c0_ddr4_dqs_c[6]}]
+# set_property PACKAGE_PIN G22 [get_ports {c0_ddr4_dq[50]}]
+# set_property PACKAGE_PIN G21 [get_ports {c0_ddr4_dq[51]}]
+# set_property PACKAGE_PIN H24 [get_ports {c0_ddr4_dm_dbi_n[6]}]
+# set_property PACKAGE_PIN A24 [get_ports {c0_ddr4_dq[42]}]
+# set_property PACKAGE_PIN B22 [get_ports {c0_ddr4_dqs_t[5]}]
+# set_property PACKAGE_PIN B21 [get_ports {c0_ddr4_dqs_c[5]}]
+# set_property PACKAGE_PIN B17 [get_ports {c0_ddr4_dqs_t[4]}]
+# set_property PACKAGE_PIN B16 [get_ports {c0_ddr4_dqs_c[4]}]
+# set_property PACKAGE_PIN A18 [get_ports {c0_ddr4_dq[38]}]
+# set_property PACKAGE_PIN A12 [get_ports {c0_ddr4_dq[31]}]
+# set_property PACKAGE_PIN D25 [get_ports {c0_ddr4_dq[48]}]
+# set_property PACKAGE_PIN E23 [get_ports {c0_ddr4_dq[49]}]
+# set_property PACKAGE_PIN C23 [get_ports {c0_ddr4_dq[40]}]
+# set_property PACKAGE_PIN A25 [get_ports {c0_ddr4_dq[43]}]
+# set_property PACKAGE_PIN C22 [get_ports {c0_ddr4_dq[44]}]
+# set_property PACKAGE_PIN B14 [get_ports {c0_ddr4_dq[24]}]
+# set_property PACKAGE_PIN K18 [get_ports {c0_ddr4_adr[4]}]
+# set_property PACKAGE_PIN C21 [get_ports {c0_ddr4_dq[41]}]
+# set_property PACKAGE_PIN D21 [get_ports {c0_ddr4_dq[45]}]
+# set_property PACKAGE_PIN C16 [get_ports {c0_ddr4_dq[32]}]
+# set_property PACKAGE_PIN E12 [get_ports {c0_ddr4_dq[16]}]
+# set_property PACKAGE_PIN D13 [get_ports {c0_ddr4_dq[25]}]
+# set_property PACKAGE_PIN C12 [get_ports {c0_ddr4_dqs_t[3]}]
+# set_property PACKAGE_PIN B12 [get_ports {c0_ddr4_dqs_c[3]}]
+# set_property PACKAGE_PIN E15 [get_ports {c0_ddr4_dq[18]}]
+# #set_property PACKAGE_PIN P18 [get_ports {c0_ddr4_ck_t[1]}]
+# #set_property PACKAGE_PIN N18 [get_ports {c0_ddr4_ck_c[1]}]
+# set_property PACKAGE_PIN L19 [get_ports {c0_ddr4_adr[0]}]
+# set_property PACKAGE_PIN J18 [get_ports {c0_ddr4_adr[5]}]
+# #set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke[0]}]
+# set_property PACKAGE_PIN E20 [get_ports {c0_ddr4_cke}]
+# set_property PACKAGE_PIN D19 [get_ports c0_ddr4_act_n]
+# set_property PACKAGE_PIN F12 [get_ports {c0_ddr4_dq[17]}]
+# set_property PACKAGE_PIN F15 [get_ports {c0_ddr4_dq[19]}]
+# set_property PACKAGE_PIN L18 [get_ports {c0_ddr4_adr[2]}]
+# set_property PACKAGE_PIN K16 [get_ports {c0_ddr4_adr[3]}]
+# set_property PACKAGE_PIN J16 [get_ports {c0_ddr4_adr[1]}]
+# #set_property PACKAGE_PIN E17 [get_ports {c0_ddr4_cke[1]}]
+# set_property PACKAGE_PIN E18 [get_ports c0_ddr4_reset_n]
+# set_property PACKAGE_PIN F14 [get_ports {c0_ddr4_dqs_t[2]}]
+# set_property PACKAGE_PIN F13 [get_ports {c0_ddr4_dqs_c[2]}]
+# #set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t[0]}]
+# set_property PACKAGE_PIN P16 [get_ports {c0_ddr4_ck_t}]
+# #set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c[0]}]
+# set_property PACKAGE_PIN N16 [get_ports {c0_ddr4_ck_c}]
+# set_property PACKAGE_PIN F19 [get_ports {c0_ddr4_bg[0]}]
+# #set_property PACKAGE_PIN F18 [get_ports {c0_ddr4_bg[1]}]
+# #set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt[0]}]
+# set_property PACKAGE_PIN E16 [get_ports {c0_ddr4_odt}]
+# #set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n[0]}]
+# set_property PACKAGE_PIN F17 [get_ports {c0_ddr4_cs_n}]
+# #set_property PACKAGE_PIN F20 [get_ports {c0_ddr4_cs_n[1]}]
+# #set_property PACKAGE_PIN D20 [get_ports {c0_ddr4_odt[1]}]
+# set_property PACKAGE_PIN K13 [get_ports {c0_ddr4_dq[10]}]
+# set_property PACKAGE_PIN J14 [get_ports {c0_ddr4_dq[11]}]
+# set_property PACKAGE_PIN H17 [get_ports {c0_ddr4_adr[16]}]
+# set_property PACKAGE_PIN G17 [get_ports {c0_ddr4_ba[0]}]
+# set_property PACKAGE_PIN H16 [get_ports {c0_ddr4_adr[14]}]
+# set_property PACKAGE_PIN G19 [get_ports {c0_ddr4_ba[1]}]
+# set_property PACKAGE_PIN N11 [get_ports {c0_ddr4_dqs_t[0]}]
+# set_property PACKAGE_PIN M11 [get_ports {c0_ddr4_dqs_c[0]}]
+# set_property PACKAGE_PIN J15 [get_ports {c0_ddr4_dq[8]}]
+# set_property PACKAGE_PIN K15 [get_ports {c0_ddr4_dq[9]}]
+# set_property PACKAGE_PIN G16 [get_ports {c0_ddr4_adr[15]}]
+# set_property PACKAGE_PIN M10 [get_ports {c0_ddr4_dq[6]}]
+# set_property PACKAGE_PIN L10 [get_ports {c0_ddr4_dq[7]}]
+# set_property PACKAGE_PIN J11 [get_ports {c0_ddr4_dqs_t[1]}]
+# set_property PACKAGE_PIN J10 [get_ports {c0_ddr4_dqs_c[1]}]
+# set_property PACKAGE_PIN L17 [get_ports {c0_ddr4_adr[6]}]
+# set_property PACKAGE_PIN K17 [get_ports {c0_ddr4_adr[8]}]
+# set_property PACKAGE_PIN M17 [get_ports {c0_ddr4_adr[9]}]
+# set_property PACKAGE_PIN M16 [get_ports {c0_ddr4_adr[7]}]
+# set_property PACKAGE_PIN M19 [get_ports {c0_ddr4_adr[10]}]
+# set_property PACKAGE_PIN M15 [get_ports {c0_ddr4_adr[11]}]
+# set_property PACKAGE_PIN N17 [get_ports {c0_ddr4_adr[12]}]
+# set_property PACKAGE_PIN N19 [get_ports {c0_ddr4_adr[13]}]
+# set_property PACKAGE_PIN L22 [get_ports {c0_ddr4_dm_dbi_n[7]}]
+# set_property PACKAGE_PIN P11 [get_ports {c0_ddr4_dq[0]}]
+# set_property PACKAGE_PIN P10 [get_ports {c0_ddr4_dq[1]}]
+# set_property PACKAGE_PIN L12 [get_ports {c0_ddr4_dq[2]}]
+# set_property PACKAGE_PIN M12 [get_ports {c0_ddr4_dq[3]}]
+# set_property PACKAGE_PIN N13 [get_ports {c0_ddr4_dq[4]}]
+# set_property PACKAGE_PIN N12 [get_ports {c0_ddr4_dq[5]}]
+# set_property PACKAGE_PIN K11 [get_ports {c0_ddr4_dq[12]}]
+# set_property PACKAGE_PIN K10 [get_ports {c0_ddr4_dq[13]}]
+# set_property PACKAGE_PIN J13 [get_ports {c0_ddr4_dq[14]}]
+# set_property PACKAGE_PIN K12 [get_ports {c0_ddr4_dq[15]}]
+# set_property PACKAGE_PIN H12 [get_ports {c0_ddr4_dq[20]}]
+# set_property PACKAGE_PIN G12 [get_ports {c0_ddr4_dq[21]}]
+# set_property PACKAGE_PIN G15 [get_ports {c0_ddr4_dq[22]}]
+# set_property PACKAGE_PIN G14 [get_ports {c0_ddr4_dq[23]}]
+# set_property PACKAGE_PIN A13 [get_ports {c0_ddr4_dq[26]}]
+# set_property PACKAGE_PIN A15 [get_ports {c0_ddr4_dq[30]}]
+# set_property PACKAGE_PIN C19 [get_ports {c0_ddr4_dq[33]}]
+# set_property PACKAGE_PIN B19 [get_ports {c0_ddr4_dq[34]}]
+# set_property PACKAGE_PIN A20 [get_ports {c0_ddr4_dq[35]}]
+# set_property PACKAGE_PIN D16 [get_ports {c0_ddr4_dq[36]}]
+# set_property PACKAGE_PIN A19 [get_ports {c0_ddr4_dq[39]}]
+# set_property PACKAGE_PIN H22 [get_ports {c0_ddr4_dq[56]}]
+# set_property PACKAGE_PIN J23 [get_ports {c0_ddr4_dq[57]}]
+# set_property PACKAGE_PIN K20 [get_ports {c0_ddr4_dq[58]}]
+# set_property PACKAGE_PIN L20 [get_ports {c0_ddr4_dq[59]}]
+# set_property PACKAGE_PIN H21 [get_ports {c0_ddr4_dq[60]}]
+# set_property PACKAGE_PIN H23 [get_ports {c0_ddr4_dq[61]}]
+# set_property PACKAGE_PIN K23 [get_ports {c0_ddr4_dq[62]}]
+# set_property PACKAGE_PIN J21 [get_ports {c0_ddr4_dq[63]}]
+# set_property PACKAGE_PIN N14 [get_ports {c0_ddr4_dm_dbi_n[0]}]
+# set_property PACKAGE_PIN L14 [get_ports {c0_ddr4_dm_dbi_n[1]}]
+# set_property PACKAGE_PIN H14 [get_ports {c0_ddr4_dm_dbi_n[2]}]
+# set_property PACKAGE_PIN D14 [get_ports {c0_ddr4_dm_dbi_n[3]}]
+# set_property PACKAGE_PIN C18 [get_ports {c0_ddr4_dm_dbi_n[4]}]
+# set_property PACKAGE_PIN K21 [get_ports {c0_ddr4_dqs_t[7]}]
+
+#set_property CFGBVS GND [current_design]
+#set_property CONFIG_VOLTAGE 1.8 [current_design]
+
+# set_property PACKAGE_PIN H19 [get_ports c0_sys_clk_p]
+# set_property PACKAGE_PIN H18 [get_ports c0_sys_clk_n]
+
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports SATA_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_N]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports GTX_CLK_P]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[1]}]
+# set_property IOSTANDARD DIFF_HSTL_I_18 [get_ports {CLK_M2C_P[0]}]
+
+# set_property PACKAGE_PIN AB31 [get_ports GTX_CLK_P]
+# set_property PACKAGE_PIN AB32 [get_ports GTX_CLK_N]
+
+# set_property PACKAGE_PIN AH39 [get_ports {DP_C2M_N[0]}]
+# set_property PACKAGE_PIN AF39 [get_ports {DP_C2M_N[1]}]
+# set_property PACKAGE_PIN AD39 [get_ports {DP_C2M_N[2]}]
+# set_property PACKAGE_PIN AB39 [get_ports {DP_C2M_N[3]}]
+# set_property PACKAGE_PIN Y39 [get_ports {DP_C2M_N[4]}]
+# set_property PACKAGE_PIN V39 [get_ports {DP_C2M_N[5]}]
+# set_property PACKAGE_PIN K39 [get_ports {DP_C2M_N[6]}]
+# set_property PACKAGE_PIN M39 [get_ports {DP_C2M_N[7]}]
+# set_property PACKAGE_PIN P39 [get_ports {DP_C2M_N[8]}]
+# set_property PACKAGE_PIN T39 [get_ports {DP_C2M_N[9]}]
+# set_property PACKAGE_PIN AH38 [get_ports {DP_C2M_P[0]}]
+# set_property PACKAGE_PIN AF38 [get_ports {DP_C2M_P[1]}]
+# set_property PACKAGE_PIN AD38 [get_ports {DP_C2M_P[2]}]
+# set_property PACKAGE_PIN AB38 [get_ports {DP_C2M_P[3]}]
+# set_property PACKAGE_PIN Y38 [get_ports {DP_C2M_P[4]}]
+# set_property PACKAGE_PIN V38 [get_ports {DP_C2M_P[5]}]
+# set_property PACKAGE_PIN K38 [get_ports {DP_C2M_P[6]}]
+# set_property PACKAGE_PIN M38 [get_ports {DP_C2M_P[7]}]
+# set_property PACKAGE_PIN P38 [get_ports {DP_C2M_P[8]}]
+# set_property PACKAGE_PIN T38 [get_ports {DP_C2M_P[9]}]
+# set_property PACKAGE_PIN AE36 [get_ports {GBTCLK_M2C_P[0]}]
+# set_property PACKAGE_PIN AE37 [get_ports {GBTCLK_M2C_N[0]}]
+# set_property PACKAGE_PIN AA36 [get_ports {GBTCLK_M2C_P[1]}]
+# set_property PACKAGE_PIN AA37 [get_ports {GBTCLK_M2C_N[1]}]
+
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y4_p [get_ports {GBTCLK_M2C_P[0]}]
+# create_clock -period 15.515 -name clk_mgtrefclk0_x0y7_p [get_ports {GBTCLK_M2C_P[1]}]
+
+# # False path constraints
+# # ----------------------------------------------------------------------------------------------------------------------
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *bit_synchronizer*inst/i_in_meta_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *reset_synchronizer*inst/rst_in_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_tx_inst/*gtwiz_userclk_tx_active_*_reg}]
+# set_false_path -to [get_cells -hierarchical -filter {NAME =~ *gtwiz_userclk_rx_inst/*gtwiz_userclk_rx_active_*_reg}]
+
+#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iACLK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CFG_CLK_IBUF_inst/O]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iGPUCLK]
+# set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets iMCLK]
+
+set_property PULLUP true [get_ports QSPI_D0]
+set_property PULLUP true [get_ports QSPI_D1]
+set_property PULLUP true [get_ports QSPI_D2]
+set_property PULLUP true [get_ports QSPI_D3]
+
+# set_property IOSTANDARD SSTL12_DCI [get_ports "c0_ddr4_bg[0]"]
+# set_property OUTPUT_IMPEDANCE RDRV_40_40 [get_ports "c0_ddr4_bg[0]"]
+
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
+set_property BITSTREAM.CONFIG.PERSIST Yes [current_design]
+set_property BITSTREAM.STARTUP.MATCH_CYCLE Auto [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
+set_property CONFIG_MODE S_SELECTMAP [current_design]
+
+set_property PACKAGE_PIN AR26 [get_ports NRST]
+set_property PACKAGE_PIN AR27 [get_ports {P0[0]}]
+set_property PACKAGE_PIN AW29 [get_ports {P0[10]}]
+set_property PACKAGE_PIN BA25 [get_ports {P0[11]}]
+set_property PACKAGE_PIN BB25 [get_ports {P0[12]}]
+set_property PACKAGE_PIN AY28 [get_ports {P0[13]}]
+set_property PACKAGE_PIN BA28 [get_ports {P0[14]}]
+set_property PACKAGE_PIN AY26 [get_ports {P0[15]}]
+set_property PACKAGE_PIN AR28 [get_ports {P0[1]}]
+set_property PACKAGE_PIN AT28 [get_ports {P0[2]}]
+set_property PACKAGE_PIN AU25 [get_ports {P0[3]}]
+set_property PACKAGE_PIN AU26 [get_ports {P0[4]}]
+set_property PACKAGE_PIN AU27 [get_ports {P0[5]}]
+set_property PACKAGE_PIN AV28 [get_ports {P0[6]}]
+set_property PACKAGE_PIN BB26 [get_ports {P0[7]}]
+set_property PACKAGE_PIN BB27 [get_ports {P0[8]}]
+set_property PACKAGE_PIN AW28 [get_ports {P0[9]}]
+set_property PACKAGE_PIN AW26 [get_ports {P1[0]}]
+set_property PACKAGE_PIN AY21 [get_ports {P1[10]}]
+set_property PACKAGE_PIN AY22 [get_ports {P1[11]}]
+set_property PACKAGE_PIN BA22 [get_ports {P1[12]}]
+set_property PACKAGE_PIN AT22 [get_ports {P1[13]}]
+set_property PACKAGE_PIN AT23 [get_ports {P1[14]}]
+set_property PACKAGE_PIN AR25 [get_ports {P1[15]}]
+set_property PACKAGE_PIN AY27 [get_ports {P1[1]}]
+set_property PACKAGE_PIN AW23 [get_ports {P1[2]}]
+set_property PACKAGE_PIN AY23 [get_ports {P1[3]}]
+set_property PACKAGE_PIN AW25 [get_ports {P1[4]}]
+set_property PACKAGE_PIN BB21 [get_ports {P1[5]}]
+set_property PACKAGE_PIN BB22 [get_ports {P1[6]}]
+set_property PACKAGE_PIN BA23 [get_ports {P1[7]}]
+set_property PACKAGE_PIN BA24 [get_ports {P1[8]}]
+set_property PACKAGE_PIN AW21 [get_ports {P1[9]}]
+set_property PACKAGE_PIN AW24 [get_ports SWCLKTCK]
+set_property PACKAGE_PIN AU22 [get_ports SWDIOTMS]
+set_property PACKAGE_PIN AV23 [get_ports VDD]
+set_property PACKAGE_PIN AT24 [get_ports VDDIO]
+set_property PACKAGE_PIN AT25 [get_ports VSS]
+set_property PACKAGE_PIN AV21 [get_ports VSSIO]
+set_property PACKAGE_PIN AY25 [get_ports XTAL1]
+set_property PACKAGE_PIN AV22 [get_ports XTAL2]
diff --git a/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_synth.tcl b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..4b89d747c16fc5a7319b9e0a8f1e0f48df0fafd8
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xcku115-flvb1760-1-c
diff --git a/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_timing.xdc b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..78ac5e66193d3180e0df08f400cc924f8f74e8be
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_arm_mps3/fpga_timing.xdc
@@ -0,0 +1,99 @@
+##################################################################################
+## ##
+## Arm MPS3 Rev-C timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks SWCLK]
+
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
+set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
+set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
+set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
+set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]
+
diff --git a/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/design_1.tcl b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..e315668f358e9835ae7579d1b495e30e84673413
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/design_1.tcl
@@ -0,0 +1,644 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:processing_system7:5.5\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {Hamming} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Memory_Type {Single_Port_RAM} \
+ CONFIG.Port_A_Write_Rate {50} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: processing_system7_0, and set properties
+ set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
+ set_property -dict [ list \
+ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {666.666687} \
+ CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.158730} \
+ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {20.000000} \
+ CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \
+ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {10.000000} \
+ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {111.111115} \
+ CONFIG.PCW_ARMPLL_CTRL_FBDIV {40} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_CLK0_FREQ {20000000} \
+ CONFIG.PCW_CLK1_FREQ {10000000} \
+ CONFIG.PCW_CLK2_FREQ {10000000} \
+ CONFIG.PCW_CLK3_FREQ {10000000} \
+ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1333.333} \
+ CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {15} \
+ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {7} \
+ CONFIG.PCW_DDRPLL_CTRL_FBDIV {32} \
+ CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1066.667} \
+ CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \
+ CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {10} \
+ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {8} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \
+ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {20} \
+ CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \
+ CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \
+ CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \
+ CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \
+ CONFIG.PCW_IOPLL_CTRL_FBDIV {48} \
+ CONFIG.PCW_IO_IO_PLL_FREQMHZ {1600.000} \
+ CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {8} \
+ CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {1} \
+ CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {533.333374} \
+ ] $processing_system7_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net S00_AXI_1 [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins processing_system7_0/M_AXI_GP0]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK]
+
+ # Create address segments
+ assign_bd_address -offset 0x41200000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x41210000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C20000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x43C30000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42C00000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x42C10000 -range 0x00010000 -target_address_space [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/design_1_wrapper.v b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..ce586c7af967a217fedd3c4fae7ef758794c7931
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_pinmap.xdc b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..5599cd2eec9ca0da4c7b57e21412e609fd7d41de
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_pinmap.xdc
@@ -0,0 +1,33 @@
+##################################################################################
+## ##
+## PZ2 PMODA XDC ##
+## ##
+##################################################################################
+
+
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+
+set_property PACKAGE_PIN Y18 [get_ports PMOD0_0]
+set_property PACKAGE_PIN Y19 [get_ports PMOD0_1]
+set_property PACKAGE_PIN Y16 [get_ports PMOD0_2]
+set_property PACKAGE_PIN Y17 [get_ports PMOD0_3]
+set_property PACKAGE_PIN U18 [get_ports PMOD0_4]
+set_property PACKAGE_PIN U19 [get_ports PMOD0_5]
+set_property PACKAGE_PIN W18 [get_ports PMOD0_6]
+set_property PACKAGE_PIN W19 [get_ports PMOD0_7]
+
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF]
diff --git a/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_synth.tcl b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1a9e44eff2f8e3cc3a24a1c5e1da88ae70f62c90
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top cmsdk_mcu_chip -part xc7z020clg400-1
diff --git a/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_timing.xdc b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..879aaadbadf756cabae24bf0f3f919d9951a8e5d
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_pynq_z2/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports XTAL1]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 18.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P0[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {P1[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/implement/fpga/xilinx_vivado/target_fpga_zcu104/design_1.tcl b/implement/fpga/xilinx_vivado/target_fpga_zcu104/design_1.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1c371ce955932e2bb0f599980de721b9bf6feb7f
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_zcu104/design_1.tcl
@@ -0,0 +1,1154 @@
+
+################################################################
+# This is a generated script based on design: design_1
+#
+# Though there are limitations about the generated script,
+# the main purpose of this utility is to make learning
+# IP Integrator Tcl commands easier.
+################################################################
+
+namespace eval _tcl {
+proc get_script_folder {} {
+ set script_path [file normalize [info script]]
+ set script_folder [file dirname $script_path]
+ return $script_folder
+}
+}
+variable script_folder
+set script_folder [_tcl::get_script_folder]
+
+################################################################
+# Check if script is running in correct Vivado version.
+################################################################
+set scripts_vivado_version 2021.1
+set current_vivado_version [version -short]
+
+if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
+ puts ""
+ catch {common::send_gid_msg -ssname BD::TCL -id 2041 -severity "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}
+
+ return 1
+}
+
+################################################################
+# START
+################################################################
+
+# To test this script, run the following commands from Vivado Tcl console:
+# source design_1_script.tcl
+
+set bCheckIPsPassed 1
+##################################################################
+# CHECK IPs
+##################################################################
+set bCheckIPs 1
+if { $bCheckIPs == 1 } {
+ set list_check_ips "\
+soclabs.org:user:nanosoc_chip:1.0\
+xilinx.com:ip:zynq_ultra_ps_e:3.3\
+soclabs.org:user:ADPcontrol:1.0\
+xilinx.com:ip:ahblite_axi_bridge:3.0\
+xilinx.com:ip:axi_bram_ctrl:4.1\
+xilinx.com:ip:axi_gpio:2.0\
+soclabs.org:user:axi_stream_io:1.0\
+xilinx.com:ip:axi_uartlite:2.0\
+xilinx.com:ip:axis_data_fifo:2.0\
+xilinx.com:ip:blk_mem_gen:8.4\
+soclabs.org:user:ft1248x1_to_axi_streamio:1.0\
+xilinx.com:ip:xlslice:1.0\
+xilinx.com:ip:xlconcat:2.1\
+xilinx.com:ip:proc_sys_reset:5.0\
+xilinx.com:ip:smartconnect:1.0\
+xilinx.com:ip:xlconstant:1.1\
+"
+
+ set list_ips_missing ""
+ common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
+
+ foreach ip_vlnv $list_check_ips {
+ set ip_obj [get_ipdefs -all $ip_vlnv]
+ if { $ip_obj eq "" } {
+ lappend list_ips_missing $ip_vlnv
+ }
+ }
+
+ if { $list_ips_missing ne "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
+ set bCheckIPsPassed 0
+ }
+
+}
+
+if { $bCheckIPsPassed != 1 } {
+ common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
+ return 3
+}
+
+##################################################################
+# DESIGN PROCs
+##################################################################
+
+
+# Hierarchical cell: cmsdk_socket
+proc create_hier_cell_cmsdk_socket { parentCell nameHier } {
+
+ variable script_folder
+
+ if { $parentCell eq "" || $nameHier eq "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_cmsdk_socket() - Empty argument(s)!"}
+ return
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+ # Create cell and set as current instance
+ set hier_obj [create_bd_cell -type hier $nameHier]
+ current_bd_instance $hier_obj
+
+ # Create interface pins
+ create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S00_AXI
+
+
+ # Create pins
+ create_bd_pin -dir I -type clk aclk
+ create_bd_pin -dir I -type rst ext_reset_in
+ create_bd_pin -dir O -from 0 -to 0 -type rst nrst
+ create_bd_pin -dir O -from 15 -to 0 p0_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p0_tri_z
+ create_bd_pin -dir O -from 15 -to 0 p1_tri_i
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_o
+ create_bd_pin -dir I -from 15 -to 0 p1_tri_z
+ create_bd_pin -dir I -from 7 -to 0 pmoda_tri_i
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_o
+ create_bd_pin -dir O -from 7 -to 0 pmoda_tri_z
+ create_bd_pin -dir O -from 0 -to 0 swdclk_i
+ create_bd_pin -dir O -from 0 -to 0 swdio_tri_i
+ create_bd_pin -dir I swdio_tri_o
+ create_bd_pin -dir I swdio_tri_z
+
+ # Create instance: ADPcontrol_0, and set properties
+ set ADPcontrol_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ADPcontrol:1.0 ADPcontrol_0 ]
+
+ # Create instance: ahblite_axi_bridge_0, and set properties
+ set ahblite_axi_bridge_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ahblite_axi_bridge:3.0 ahblite_axi_bridge_0 ]
+
+ # Create instance: axi_bram_ctrl_0, and set properties
+ set axi_bram_ctrl_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_bram_ctrl:4.1 axi_bram_ctrl_0 ]
+ set_property -dict [ list \
+ CONFIG.ECC_TYPE {0} \
+ CONFIG.PROTOCOL {AXI4} \
+ CONFIG.SINGLE_PORT_BRAM {1} \
+ ] $axi_bram_ctrl_0
+
+ # Create instance: axi_gpio_0, and set properties
+ set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_0
+
+ # Create instance: axi_gpio_1, and set properties
+ set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ]
+ set_property -dict [ list \
+ CONFIG.C_GPIO2_WIDTH {16} \
+ CONFIG.C_GPIO_WIDTH {16} \
+ CONFIG.C_IS_DUAL {1} \
+ ] $axi_gpio_1
+
+ # Create instance: axi_stream_io_0, and set properties
+ set axi_stream_io_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_0 ]
+
+ # Create instance: axi_stream_io_1, and set properties
+ set axi_stream_io_1 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_1 ]
+
+ # Create instance: axi_stream_io_2, and set properties
+ set axi_stream_io_2 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_2 ]
+
+ # Create instance: axi_stream_io_3, and set properties
+ set axi_stream_io_3 [ create_bd_cell -type ip -vlnv soclabs.org:user:axi_stream_io:1.0 axi_stream_io_3 ]
+
+ # Create instance: axi_uartlite_0, and set properties
+ set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_0
+
+ # Create instance: axi_uartlite_1, and set properties
+ set axi_uartlite_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_1 ]
+ set_property -dict [ list \
+ CONFIG.C_S_AXI_ACLK_FREQ_HZ {19752890} \
+ ] $axi_uartlite_1
+
+ # Create instance: axis_data_fifo_0, and set properties
+ set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_0 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_0
+
+ # Create instance: axis_data_fifo_1, and set properties
+ set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_1 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_1
+
+ # Create instance: axis_data_fifo_2, and set properties
+ set axis_data_fifo_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_2 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_2
+
+ # Create instance: axis_data_fifo_3, and set properties
+ set axis_data_fifo_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_3 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_3
+
+ # Create instance: axis_data_fifo_4, and set properties
+ set axis_data_fifo_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 axis_data_fifo_4 ]
+ set_property -dict [ list \
+ CONFIG.FIFO_DEPTH {64} \
+ ] $axis_data_fifo_4
+
+ # Create instance: blk_mem_gen_0, and set properties
+ set blk_mem_gen_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 blk_mem_gen_0 ]
+ set_property -dict [ list \
+ CONFIG.Byte_Size {8} \
+ CONFIG.EN_SAFETY_CKT {true} \
+ CONFIG.Enable_32bit_Address {true} \
+ CONFIG.Read_Width_A {32} \
+ CONFIG.Read_Width_B {32} \
+ CONFIG.Register_PortA_Output_of_Memory_Primitives {false} \
+ CONFIG.Use_Byte_Write_Enable {true} \
+ CONFIG.Use_RSTA_Pin {true} \
+ CONFIG.Write_Width_A {32} \
+ CONFIG.Write_Width_B {32} \
+ CONFIG.use_bram_block {BRAM_Controller} \
+ ] $blk_mem_gen_0
+
+ # Create instance: ft1248x1_to_axi_stream_0, and set properties
+ set ft1248x1_to_axi_stream_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:ft1248x1_to_axi_streamio:1.0 ft1248x1_to_axi_stream_0 ]
+
+ # Create instance: p1_i_bit15to6, and set properties
+ set p1_i_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_i_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_i_bit15to6
+
+ # Create instance: p1_i_concat, and set properties
+ set p1_i_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 p1_i_concat ]
+ set_property -dict [ list \
+ CONFIG.IN0_WIDTH {1} \
+ CONFIG.IN1_WIDTH {1} \
+ CONFIG.IN2_WIDTH {1} \
+ CONFIG.IN3_WIDTH {1} \
+ CONFIG.IN4_WIDTH {1} \
+ CONFIG.IN5_WIDTH {1} \
+ CONFIG.IN6_WIDTH {10} \
+ CONFIG.IN7_WIDTH {1} \
+ CONFIG.IN8_WIDTH {8} \
+ CONFIG.NUM_PORTS {7} \
+ ] $p1_i_concat
+
+ # Create instance: p1_o_bit1, and set properties
+ set p1_o_bit1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit1 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {1} \
+ CONFIG.DIN_TO {1} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit1
+
+ # Create instance: p1_o_bit15to6, and set properties
+ set p1_o_bit15to6 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit15to6 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {15} \
+ CONFIG.DIN_TO {6} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {10} \
+ ] $p1_o_bit15to6
+
+ # Create instance: p1_o_bit2, and set properties
+ set p1_o_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit2
+
+ # Create instance: p1_o_bit3, and set properties
+ set p1_o_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit3
+
+ # Create instance: p1_o_bit5, and set properties
+ set p1_o_bit5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_o_bit5 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {5} \
+ CONFIG.DIN_TO {5} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_o_bit5
+
+ # Create instance: p1_z_bit2, and set properties
+ set p1_z_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 p1_z_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {16} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $p1_z_bit2
+
+ # Create instance: pmoda_i_bit2, and set properties
+ set pmoda_i_bit2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit2 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {2} \
+ CONFIG.DIN_TO {2} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit2
+
+ # Create instance: pmoda_i_bit3, and set properties
+ set pmoda_i_bit3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit3 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {3} \
+ CONFIG.DIN_TO {3} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit3
+
+ # Create instance: pmoda_i_bit4, and set properties
+ set pmoda_i_bit4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit4 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {4} \
+ CONFIG.DIN_TO {4} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit4
+
+ # Create instance: pmoda_i_bit7, and set properties
+ set pmoda_i_bit7 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 pmoda_i_bit7 ]
+ set_property -dict [ list \
+ CONFIG.DIN_FROM {7} \
+ CONFIG.DIN_TO {7} \
+ CONFIG.DIN_WIDTH {8} \
+ CONFIG.DOUT_WIDTH {1} \
+ ] $pmoda_i_bit7
+
+ # Create instance: pmoda_o_concat8, and set properties
+ set pmoda_o_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_o_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_o_concat8
+
+ # Create instance: pmoda_z_concat8, and set properties
+ set pmoda_z_concat8 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 pmoda_z_concat8 ]
+ set_property -dict [ list \
+ CONFIG.NUM_PORTS {8} \
+ ] $pmoda_z_concat8
+
+ # Create instance: proc_sys_reset_0, and set properties
+ set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ]
+
+ # Create instance: smartconnect_0, and set properties
+ set smartconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:smartconnect:1.0 smartconnect_0 ]
+ set_property -dict [ list \
+ CONFIG.NUM_MI {8} \
+ CONFIG.NUM_SI {1} \
+ ] $smartconnect_0
+
+ # Create instance: xlconstant_0, and set properties
+ set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ]
+ set_property -dict [ list \
+ CONFIG.CONST_VAL {0} \
+ ] $xlconstant_0
+
+ # Create instance: xlconstant_1, and set properties
+ set xlconstant_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_1 ]
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net ADPcontrol_0_ahb [get_bd_intf_pins ADPcontrol_0/ahb] [get_bd_intf_pins ahblite_axi_bridge_0/AHB_INTERFACE]
+ connect_bd_intf_net -intf_net ADPcontrol_0_com_tx [get_bd_intf_pins ADPcontrol_0/com_tx] [get_bd_intf_pins axis_data_fifo_3/S_AXIS]
+ connect_bd_intf_net -intf_net ADPcontrol_0_stdio_tx [get_bd_intf_pins ADPcontrol_0/stdio_tx] [get_bd_intf_pins axis_data_fifo_4/S_AXIS]
+ connect_bd_intf_net -intf_net ahblite_axi_bridge_0_M_AXI [get_bd_intf_pins ahblite_axi_bridge_0/M_AXI] [get_bd_intf_pins axi_bram_ctrl_0/S_AXI]
+ connect_bd_intf_net -intf_net axi_bram_ctrl_0_BRAM_PORTA [get_bd_intf_pins axi_bram_ctrl_0/BRAM_PORTA] [get_bd_intf_pins blk_mem_gen_0/BRAM_PORTA]
+ connect_bd_intf_net -intf_net axi_stream_io_0_tx [get_bd_intf_pins axi_stream_io_0/tx] [get_bd_intf_pins ft1248x1_to_axi_stream_0/rxd8]
+ connect_bd_intf_net -intf_net axi_stream_io_1_tx [get_bd_intf_pins axi_stream_io_1/rx] [get_bd_intf_pins axi_stream_io_1/tx]
+ connect_bd_intf_net -intf_net axi_stream_io_2_tx [get_bd_intf_pins axi_stream_io_2/tx] [get_bd_intf_pins axis_data_fifo_1/S_AXIS]
+ connect_bd_intf_net -intf_net axi_stream_io_3_tx [get_bd_intf_pins axi_stream_io_3/tx] [get_bd_intf_pins axis_data_fifo_2/S_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins axi_stream_io_0/rx] [get_bd_intf_pins axis_data_fifo_0/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins axi_stream_io_2/rx] [get_bd_intf_pins axis_data_fifo_1/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_2_M_AXIS [get_bd_intf_pins ADPcontrol_0/com_rx] [get_bd_intf_pins axis_data_fifo_2/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_3_M_AXIS [get_bd_intf_pins axi_stream_io_3/rx] [get_bd_intf_pins axis_data_fifo_3/M_AXIS]
+ connect_bd_intf_net -intf_net axis_data_fifo_4_M_AXIS [get_bd_intf_pins ADPcontrol_0/stdio_rx] [get_bd_intf_pins axis_data_fifo_4/M_AXIS]
+ connect_bd_intf_net -intf_net ft1248x1_to_axi_stre_0_txd8 [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins ft1248x1_to_axi_stream_0/txd8]
+ connect_bd_intf_net -intf_net smartconnect_0_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins smartconnect_0/M00_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins smartconnect_0/M01_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins smartconnect_0/M02_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M03_AXI [get_bd_intf_pins axi_uartlite_1/S_AXI] [get_bd_intf_pins smartconnect_0/M03_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M04_AXI [get_bd_intf_pins axi_stream_io_0/S_AXI] [get_bd_intf_pins smartconnect_0/M04_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M05_AXI [get_bd_intf_pins axi_stream_io_1/S_AXI] [get_bd_intf_pins smartconnect_0/M05_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M06_AXI [get_bd_intf_pins axi_stream_io_2/S_AXI] [get_bd_intf_pins smartconnect_0/M06_AXI]
+ connect_bd_intf_net -intf_net smartconnect_0_M07_AXI [get_bd_intf_pins axi_stream_io_3/S_AXI] [get_bd_intf_pins smartconnect_0/M07_AXI]
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins S00_AXI] [get_bd_intf_pins smartconnect_0/S00_AXI]
+
+ # Create port connections
+ connect_bd_net -net ADPcontrol_0_gpo8 [get_bd_pins ADPcontrol_0/gpi8] [get_bd_pins ADPcontrol_0/gpo8]
+ connect_bd_net -net UART2_TXD [get_bd_pins axi_uartlite_0/rx] [get_bd_pins p1_o_bit5/Dout]
+ connect_bd_net -net ahblite_axi_bridge_0_s_ahb_hready_out [get_bd_pins ADPcontrol_0/ahb_hready] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_in] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hready_out]
+ connect_bd_net -net axi_bram_ctrl_0_bram_addr_a [get_bd_pins axi_bram_ctrl_0/bram_addr_a] [get_bd_pins blk_mem_gen_0/addra]
+ connect_bd_net -net axi_bram_ctrl_0_bram_clk_a [get_bd_pins axi_bram_ctrl_0/bram_clk_a] [get_bd_pins blk_mem_gen_0/clka]
+ connect_bd_net -net axi_bram_ctrl_0_bram_en_a [get_bd_pins axi_bram_ctrl_0/bram_en_a] [get_bd_pins blk_mem_gen_0/ena]
+ connect_bd_net -net axi_bram_ctrl_0_bram_we_a [get_bd_pins axi_bram_ctrl_0/bram_we_a] [get_bd_pins blk_mem_gen_0/wea]
+ connect_bd_net -net axi_bram_ctrl_0_bram_wrdata_a [get_bd_pins axi_bram_ctrl_0/bram_wrdata_a] [get_bd_pins blk_mem_gen_0/dina]
+ connect_bd_net -net axi_gpio_0_gpio_io_o [get_bd_pins p0_tri_i] [get_bd_pins axi_gpio_0/gpio_io_o]
+ connect_bd_net -net axi_gpio_1_gpio_io_o [get_bd_pins axi_gpio_1/gpio_io_o] [get_bd_pins p1_i_bit15to6/Din]
+ connect_bd_net -net axi_uartlite_0_tx [get_bd_pins axi_uartlite_0/tx] [get_bd_pins p1_i_concat/In4]
+ connect_bd_net -net axi_uartlite_1_tx [get_bd_pins axi_uartlite_1/rx] [get_bd_pins axi_uartlite_1/tx]
+ connect_bd_net -net blk_mem_gen_0_douta [get_bd_pins axi_bram_ctrl_0/bram_rddata_a] [get_bd_pins blk_mem_gen_0/douta]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_o [get_bd_pins p0_tri_o] [get_bd_pins axi_gpio_0/gpio_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p0_z [get_bd_pins p0_tri_z] [get_bd_pins axi_gpio_0/gpio2_io_i]
+ connect_bd_net -net cmsdk_mcu_chip_0_p1_o [get_bd_pins p1_tri_o] [get_bd_pins axi_gpio_1/gpio_io_i] [get_bd_pins p1_o_bit1/Din] [get_bd_pins p1_o_bit15to6/Din] [get_bd_pins p1_o_bit2/Din] [get_bd_pins p1_o_bit3/Din] [get_bd_pins p1_o_bit5/Din]
+ connect_bd_net -net const0 [get_bd_pins p1_i_concat/In1] [get_bd_pins p1_i_concat/In3] [get_bd_pins p1_i_concat/In5] [get_bd_pins pmoda_o_concat8/In2] [get_bd_pins pmoda_o_concat8/In5] [get_bd_pins pmoda_o_concat8/In6] [get_bd_pins pmoda_o_concat8/In7] [get_bd_pins pmoda_z_concat8/In0] [get_bd_pins pmoda_z_concat8/In1] [get_bd_pins xlconstant_0/dout]
+ connect_bd_net -net const1 [get_bd_pins ahblite_axi_bridge_0/s_ahb_hsel] [get_bd_pins pmoda_z_concat8/In2] [get_bd_pins pmoda_z_concat8/In5] [get_bd_pins pmoda_z_concat8/In6] [get_bd_pins pmoda_z_concat8/In7] [get_bd_pins xlconstant_1/dout]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miosio_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_o] [get_bd_pins p1_i_concat/In2]
+ connect_bd_net -net ft1248x1_to_axi_stre_0_ft_miso_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_miso_o] [get_bd_pins p1_i_concat/In0]
+ connect_bd_net -net ftclk_o [get_bd_pins ft1248x1_to_axi_stream_0/ft_clk_i] [get_bd_pins p1_o_bit1/Dout] [get_bd_pins pmoda_o_concat8/In0]
+ connect_bd_net -net ftmiosio_o [get_bd_pins p1_o_bit2/Dout] [get_bd_pins pmoda_o_concat8/In3]
+ connect_bd_net -net ftmiosio_z [get_bd_pins p1_z_bit2/Dout] [get_bd_pins pmoda_z_concat8/In3]
+ connect_bd_net -net ftssn_n [get_bd_pins ft1248x1_to_axi_stream_0/ft_ssn_i] [get_bd_pins p1_o_bit3/Dout] [get_bd_pins pmoda_o_concat8/In1]
+ connect_bd_net -net p1_i [get_bd_pins p1_tri_i] [get_bd_pins p1_i_concat/dout]
+ connect_bd_net -net p1_i_bit15to6_Dout [get_bd_pins p1_i_bit15to6/Dout] [get_bd_pins p1_i_concat/In6]
+ connect_bd_net -net p1_z [get_bd_pins p1_tri_z] [get_bd_pins axi_gpio_1/gpio2_io_i] [get_bd_pins p1_z_bit2/Din]
+ connect_bd_net -net pmoda_i_1 [get_bd_pins pmoda_tri_i] [get_bd_pins pmoda_i_bit2/Din] [get_bd_pins pmoda_i_bit3/Din] [get_bd_pins pmoda_i_bit4/Din] [get_bd_pins pmoda_i_bit7/Din]
+ connect_bd_net -net pmoda_i_bit3_Dout [get_bd_pins ft1248x1_to_axi_stream_0/ft_miosio_i] [get_bd_pins pmoda_i_bit3/Dout]
+ connect_bd_net -net pmoda_i_bit4_Dout [get_bd_pins swdio_tri_i] [get_bd_pins pmoda_i_bit4/Dout]
+ connect_bd_net -net pmoda_i_bit7_Dout [get_bd_pins swdclk_i] [get_bd_pins pmoda_i_bit7/Dout]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_pins pmoda_tri_z] [get_bd_pins pmoda_z_concat8/dout]
+ connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins ADPcontrol_0/ahb_hresetn] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hresetn] [get_bd_pins axi_bram_ctrl_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_stream_io_0/S_AXI_ARESETN] [get_bd_pins axi_stream_io_1/S_AXI_ARESETN] [get_bd_pins axi_stream_io_2/S_AXI_ARESETN] [get_bd_pins axi_stream_io_3/S_AXI_ARESETN] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins axi_uartlite_1/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_data_fifo_2/s_axis_aresetn] [get_bd_pins axis_data_fifo_3/s_axis_aresetn] [get_bd_pins axis_data_fifo_4/s_axis_aresetn] [get_bd_pins ft1248x1_to_axi_stream_0/aresetn] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins smartconnect_0/aresetn]
+ connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins nrst] [get_bd_pins proc_sys_reset_0/peripheral_aresetn]
+ connect_bd_net -net swdio_o_1 [get_bd_pins swdio_tri_o] [get_bd_pins pmoda_o_concat8/In4]
+ connect_bd_net -net swdio_z_1 [get_bd_pins swdio_tri_z] [get_bd_pins pmoda_z_concat8/In4]
+ connect_bd_net -net xlconcat_0_dout [get_bd_pins pmoda_tri_o] [get_bd_pins pmoda_o_concat8/dout]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins aclk] [get_bd_pins ADPcontrol_0/ahb_hclk] [get_bd_pins ahblite_axi_bridge_0/s_ahb_hclk] [get_bd_pins axi_bram_ctrl_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_stream_io_0/S_AXI_ACLK] [get_bd_pins axi_stream_io_1/S_AXI_ACLK] [get_bd_pins axi_stream_io_2/S_AXI_ACLK] [get_bd_pins axi_stream_io_3/S_AXI_ACLK] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins axi_uartlite_1/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_data_fifo_2/s_axis_aclk] [get_bd_pins axis_data_fifo_3/s_axis_aclk] [get_bd_pins axis_data_fifo_4/s_axis_aclk] [get_bd_pins ft1248x1_to_axi_stream_0/aclk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins smartconnect_0/aclk]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_resetn0 [get_bd_pins ext_reset_in] [get_bd_pins proc_sys_reset_0/ext_reset_in]
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+}
+
+
+# Procedure to create entire design; Provide argument to make
+# procedure reusable. If parentCell is "", will use root.
+proc create_root_design { parentCell } {
+
+ variable script_folder
+
+ if { $parentCell eq "" } {
+ set parentCell [get_bd_cells /]
+ }
+
+ # Get object for parentCell
+ set parentObj [get_bd_cells $parentCell]
+ if { $parentObj == "" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
+ return
+ }
+
+ # Make sure parentObj is hier blk
+ set parentType [get_property TYPE $parentObj]
+ if { $parentType ne "hier" } {
+ catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
+ return
+ }
+
+ # Save current instance; Restore later
+ set oldCurInst [current_bd_instance .]
+
+ # Set parent object as current
+ current_bd_instance $parentObj
+
+
+ # Create interface ports
+
+ # Create ports
+ set pmoda_tri_i [ create_bd_port -dir I -from 7 -to 0 pmoda_tri_i ]
+ set pmoda_tri_o [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_o ]
+ set pmoda_tri_z [ create_bd_port -dir O -from 7 -to 0 pmoda_tri_z ]
+
+ # Create instance: cmsdk_socket
+ create_hier_cell_cmsdk_socket [current_bd_instance .] cmsdk_socket
+
+ # Create instance: nanosoc_chip_0, and set properties
+ set nanosoc_chip_0 [ create_bd_cell -type ip -vlnv soclabs.org:user:nanosoc_chip:1.0 nanosoc_chip_0 ]
+
+ # Create instance: zynq_ultra_ps_e_0, and set properties
+ set zynq_ultra_ps_e_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.3 zynq_ultra_ps_e_0 ]
+ set_property -dict [ list \
+ CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \
+ CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \
+ CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \
+ CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN {0} \
+ CONFIG.PSU_MIO_0_DIRECTION {out} \
+ CONFIG.PSU_MIO_0_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_0_POLARITY {Default} \
+ CONFIG.PSU_MIO_16_DIRECTION {inout} \
+ CONFIG.PSU_MIO_16_POLARITY {Default} \
+ CONFIG.PSU_MIO_17_DIRECTION {inout} \
+ CONFIG.PSU_MIO_17_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_DIRECTION {in} \
+ CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_18_POLARITY {Default} \
+ CONFIG.PSU_MIO_18_SLEW {fast} \
+ CONFIG.PSU_MIO_19_DIRECTION {out} \
+ CONFIG.PSU_MIO_19_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_19_POLARITY {Default} \
+ CONFIG.PSU_MIO_1_DIRECTION {inout} \
+ CONFIG.PSU_MIO_1_POLARITY {Default} \
+ CONFIG.PSU_MIO_20_DIRECTION {out} \
+ CONFIG.PSU_MIO_20_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_20_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_DIRECTION {in} \
+ CONFIG.PSU_MIO_21_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_21_POLARITY {Default} \
+ CONFIG.PSU_MIO_21_SLEW {fast} \
+ CONFIG.PSU_MIO_24_DIRECTION {out} \
+ CONFIG.PSU_MIO_24_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_24_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_DIRECTION {in} \
+ CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_25_POLARITY {Default} \
+ CONFIG.PSU_MIO_25_SLEW {fast} \
+ CONFIG.PSU_MIO_27_DIRECTION {out} \
+ CONFIG.PSU_MIO_27_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_27_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_DIRECTION {in} \
+ CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_28_POLARITY {Default} \
+ CONFIG.PSU_MIO_28_SLEW {fast} \
+ CONFIG.PSU_MIO_29_DIRECTION {out} \
+ CONFIG.PSU_MIO_29_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_29_POLARITY {Default} \
+ CONFIG.PSU_MIO_2_DIRECTION {inout} \
+ CONFIG.PSU_MIO_2_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_DIRECTION {in} \
+ CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_30_POLARITY {Default} \
+ CONFIG.PSU_MIO_30_SLEW {fast} \
+ CONFIG.PSU_MIO_3_DIRECTION {inout} \
+ CONFIG.PSU_MIO_3_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_DIRECTION {in} \
+ CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_45_POLARITY {Default} \
+ CONFIG.PSU_MIO_45_SLEW {fast} \
+ CONFIG.PSU_MIO_46_DIRECTION {inout} \
+ CONFIG.PSU_MIO_46_POLARITY {Default} \
+ CONFIG.PSU_MIO_47_DIRECTION {inout} \
+ CONFIG.PSU_MIO_47_POLARITY {Default} \
+ CONFIG.PSU_MIO_48_DIRECTION {inout} \
+ CONFIG.PSU_MIO_48_POLARITY {Default} \
+ CONFIG.PSU_MIO_49_DIRECTION {inout} \
+ CONFIG.PSU_MIO_49_POLARITY {Default} \
+ CONFIG.PSU_MIO_4_DIRECTION {inout} \
+ CONFIG.PSU_MIO_4_POLARITY {Default} \
+ CONFIG.PSU_MIO_50_DIRECTION {inout} \
+ CONFIG.PSU_MIO_50_POLARITY {Default} \
+ CONFIG.PSU_MIO_51_DIRECTION {out} \
+ CONFIG.PSU_MIO_51_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_51_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_DIRECTION {in} \
+ CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_52_POLARITY {Default} \
+ CONFIG.PSU_MIO_52_SLEW {fast} \
+ CONFIG.PSU_MIO_53_DIRECTION {in} \
+ CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_53_POLARITY {Default} \
+ CONFIG.PSU_MIO_53_SLEW {fast} \
+ CONFIG.PSU_MIO_54_DIRECTION {inout} \
+ CONFIG.PSU_MIO_54_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_DIRECTION {in} \
+ CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_55_POLARITY {Default} \
+ CONFIG.PSU_MIO_55_SLEW {fast} \
+ CONFIG.PSU_MIO_56_DIRECTION {inout} \
+ CONFIG.PSU_MIO_56_POLARITY {Default} \
+ CONFIG.PSU_MIO_57_DIRECTION {inout} \
+ CONFIG.PSU_MIO_57_POLARITY {Default} \
+ CONFIG.PSU_MIO_58_DIRECTION {out} \
+ CONFIG.PSU_MIO_58_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_58_POLARITY {Default} \
+ CONFIG.PSU_MIO_59_DIRECTION {inout} \
+ CONFIG.PSU_MIO_59_POLARITY {Default} \
+ CONFIG.PSU_MIO_5_DIRECTION {out} \
+ CONFIG.PSU_MIO_5_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_5_POLARITY {Default} \
+ CONFIG.PSU_MIO_60_DIRECTION {inout} \
+ CONFIG.PSU_MIO_60_POLARITY {Default} \
+ CONFIG.PSU_MIO_61_DIRECTION {inout} \
+ CONFIG.PSU_MIO_61_POLARITY {Default} \
+ CONFIG.PSU_MIO_62_DIRECTION {inout} \
+ CONFIG.PSU_MIO_62_POLARITY {Default} \
+ CONFIG.PSU_MIO_63_DIRECTION {inout} \
+ CONFIG.PSU_MIO_63_POLARITY {Default} \
+ CONFIG.PSU_MIO_64_DIRECTION {out} \
+ CONFIG.PSU_MIO_64_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_64_POLARITY {Default} \
+ CONFIG.PSU_MIO_65_DIRECTION {out} \
+ CONFIG.PSU_MIO_65_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_65_POLARITY {Default} \
+ CONFIG.PSU_MIO_66_DIRECTION {out} \
+ CONFIG.PSU_MIO_66_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_66_POLARITY {Default} \
+ CONFIG.PSU_MIO_67_DIRECTION {out} \
+ CONFIG.PSU_MIO_67_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_67_POLARITY {Default} \
+ CONFIG.PSU_MIO_68_DIRECTION {out} \
+ CONFIG.PSU_MIO_68_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_68_POLARITY {Default} \
+ CONFIG.PSU_MIO_69_DIRECTION {out} \
+ CONFIG.PSU_MIO_69_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_69_POLARITY {Default} \
+ CONFIG.PSU_MIO_6_DIRECTION {out} \
+ CONFIG.PSU_MIO_6_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_6_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_DIRECTION {in} \
+ CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_70_POLARITY {Default} \
+ CONFIG.PSU_MIO_70_SLEW {fast} \
+ CONFIG.PSU_MIO_71_DIRECTION {in} \
+ CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_71_POLARITY {Default} \
+ CONFIG.PSU_MIO_71_SLEW {fast} \
+ CONFIG.PSU_MIO_72_DIRECTION {in} \
+ CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_72_POLARITY {Default} \
+ CONFIG.PSU_MIO_72_SLEW {fast} \
+ CONFIG.PSU_MIO_73_DIRECTION {in} \
+ CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_73_POLARITY {Default} \
+ CONFIG.PSU_MIO_73_SLEW {fast} \
+ CONFIG.PSU_MIO_74_DIRECTION {in} \
+ CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_74_POLARITY {Default} \
+ CONFIG.PSU_MIO_74_SLEW {fast} \
+ CONFIG.PSU_MIO_75_DIRECTION {in} \
+ CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \
+ CONFIG.PSU_MIO_75_POLARITY {Default} \
+ CONFIG.PSU_MIO_75_SLEW {fast} \
+ CONFIG.PSU_MIO_76_DIRECTION {out} \
+ CONFIG.PSU_MIO_76_INPUT_TYPE {cmos} \
+ CONFIG.PSU_MIO_76_POLARITY {Default} \
+ CONFIG.PSU_MIO_77_DIRECTION {inout} \
+ CONFIG.PSU_MIO_77_POLARITY {Default} \
+ CONFIG.PSU_MIO_TREE_PERIPHERALS {Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad\
+SPI Flash#Feedback Clk##########I2C 1#I2C 1#UART 0#UART 0#UART 1#UART 1###CAN\
+1#CAN 1##DPAUX#DPAUX#DPAUX#DPAUX###############SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#SD\
+1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#Gem\
+3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#Gem 3#MDIO 3#MDIO\
+3}\
+ CONFIG.PSU_MIO_TREE_SIGNALS {sclk_out#miso_mo1#mo2#mo3#mosi_mi0#n_ss_out#clk_for_lpbk##########scl_out#sda_out#rxd#txd#txd#rxd###phy_tx#phy_rx##dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in###############sdio1_cd_n#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#rgmii_tx_clk#rgmii_txd[0]#rgmii_txd[1]#rgmii_txd[2]#rgmii_txd[3]#rgmii_tx_ctl#rgmii_rx_clk#rgmii_rxd[0]#rgmii_rxd[1]#rgmii_rxd[2]#rgmii_rxd[3]#rgmii_rx_ctl#gem3_mdc#gem3_mdio_out}\
+ CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \
+ CONFIG.PSU_USB3__DUAL_CLOCK_ENABLE {1} \
+ CONFIG.PSU__ACT_DDR_FREQ_MHZ {1050.000000} \
+ CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \
+ CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__CAN1__PERIPHERAL__IO {MIO 24 .. 25} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1200.000000} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \
+ CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {1067} \
+ CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {63} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {25.000000} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.785715} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {14} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {300.000000} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \
+ CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {0} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {600.000000} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \
+ CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {525.000000} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.33} \
+ CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {50.000000} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {30} \
+ CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1500.000000} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {90} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {500.000000} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \
+ CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \
+ CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {125.000000} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {12} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {125} \
+ CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {45} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.000000} \
+ CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \
+ CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {0} \
+ CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {2} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.500000} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \
+ CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {7} \
+ CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \
+ CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {250.000000} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \
+ CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \
+ CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {25} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {3} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \
+ CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \
+ CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \
+ CONFIG.PSU__DDRC__ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__BANK_ADDR_COUNT {2} \
+ CONFIG.PSU__DDRC__BG_ADDR_COUNT {1} \
+ CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \
+ CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit} \
+ CONFIG.PSU__DDRC__CL {15} \
+ CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \
+ CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \
+ CONFIG.PSU__DDRC__COMPONENTS {Components} \
+ CONFIG.PSU__DDRC__CWL {14} \
+ CONFIG.PSU__DDRC__DDR3L_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {0} \
+ CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {0} \
+ CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_MODE {0} \
+ CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {Normal (0-85)} \
+ CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \
+ CONFIG.PSU__DDRC__DEVICE_CAPACITY {4096 MBits} \
+ CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {0} \
+ CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \
+ CONFIG.PSU__DDRC__DQMAP_0_3 {0} \
+ CONFIG.PSU__DDRC__DQMAP_12_15 {0} \
+ CONFIG.PSU__DDRC__DQMAP_16_19 {0} \
+ CONFIG.PSU__DDRC__DQMAP_20_23 {0} \
+ CONFIG.PSU__DDRC__DQMAP_24_27 {0} \
+ CONFIG.PSU__DDRC__DQMAP_28_31 {0} \
+ CONFIG.PSU__DDRC__DQMAP_32_35 {0} \
+ CONFIG.PSU__DDRC__DQMAP_36_39 {0} \
+ CONFIG.PSU__DDRC__DQMAP_40_43 {0} \
+ CONFIG.PSU__DDRC__DQMAP_44_47 {0} \
+ CONFIG.PSU__DDRC__DQMAP_48_51 {0} \
+ CONFIG.PSU__DDRC__DQMAP_4_7 {0} \
+ CONFIG.PSU__DDRC__DQMAP_52_55 {0} \
+ CONFIG.PSU__DDRC__DQMAP_56_59 {0} \
+ CONFIG.PSU__DDRC__DQMAP_60_63 {0} \
+ CONFIG.PSU__DDRC__DQMAP_64_67 {0} \
+ CONFIG.PSU__DDRC__DQMAP_68_71 {0} \
+ CONFIG.PSU__DDRC__DQMAP_8_11 {0} \
+ CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits} \
+ CONFIG.PSU__DDRC__ECC {Disabled} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \
+ CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \
+ CONFIG.PSU__DDRC__FGRM {1X} \
+ CONFIG.PSU__DDRC__LPDDR3_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LPDDR4_T_REF_RANGE {NA} \
+ CONFIG.PSU__DDRC__LP_ASR {manual normal} \
+ CONFIG.PSU__DDRC__MEMORY_TYPE {DDR 4} \
+ CONFIG.PSU__DDRC__PARITY_ENABLE {0} \
+ CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \
+ CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \
+ CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \
+ CONFIG.PSU__DDRC__SB_TARGET {15-15-15} \
+ CONFIG.PSU__DDRC__SELF_REF_ABORT {0} \
+ CONFIG.PSU__DDRC__SPEED_BIN {DDR4_2133P} \
+ CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \
+ CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \
+ CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \
+ CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \
+ CONFIG.PSU__DDRC__T_FAW {30.0} \
+ CONFIG.PSU__DDRC__T_RAS_MIN {33} \
+ CONFIG.PSU__DDRC__T_RC {47.06} \
+ CONFIG.PSU__DDRC__T_RCD {15} \
+ CONFIG.PSU__DDRC__T_RP {15} \
+ CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \
+ CONFIG.PSU__DDRC__VREF {1} \
+ CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \
+ CONFIG.PSU__DDR__INTERFACE__FREQMHZ {533.500} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \
+ CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \
+ CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DLL__ISUSED {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \
+ CONFIG.PSU__DP__LANE_SEL {Dual Lower} \
+ CONFIG.PSU__DP__REF_CLK_FREQ {27} \
+ CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk3} \
+ CONFIG.PSU__ENET3__FIFO__ENABLE {0} \
+ CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1} \
+ CONFIG.PSU__ENET3__GRP_MDIO__IO {MIO 76 .. 77} \
+ CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__ENET3__PERIPHERAL__IO {MIO 64 .. 75} \
+ CONFIG.PSU__ENET3__PTP__ENABLE {0} \
+ CONFIG.PSU__ENET3__TSU__ENABLE {0} \
+ CONFIG.PSU__FPDMASTERS_COHERENCY {0} \
+ CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \
+ CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__FPGA_PL0_ENABLE {1} \
+ CONFIG.PSU__GEM3_COHERENCY {0} \
+ CONFIG.PSU__GEM3_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__GEM__TSU__ENABLE {0} \
+ CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__GT__LINK_SPEED {HBR} \
+ CONFIG.PSU__GT__PRE_EMPH_LVL_4 {0} \
+ CONFIG.PSU__GT__VLT_SWNG_LVL_4 {0} \
+ CONFIG.PSU__HIGH_ADDRESS__ENABLE {0} \
+ CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {0} \
+ CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 16 .. 17} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC0_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC1_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL {APB} \
+ CONFIG.PSU__IOU_SLCR__TTC0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC1__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC2__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__TTC3__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__ACT_FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT0__FREQMHZ {100.000000} \
+ CONFIG.PSU__IOU_SLCR__WDT_CLK_SEL__SELECT {APB} \
+ CONFIG.PSU__MAXIGP0__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP1__DATA_WIDTH {128} \
+ CONFIG.PSU__MAXIGP2__DATA_WIDTH {32} \
+ CONFIG.PSU__OVERRIDE__BASIC_CLOCK {0} \
+ CONFIG.PSU__PL_CLK0_BUF {TRUE} \
+ CONFIG.PSU__PRESET_APPLIED {1} \
+ CONFIG.PSU__PROTECTION__MASTERS {USB1:NonSecure;0|USB0:NonSecure;1|S_AXI_LPD:NA;0|S_AXI_HPC1_FPD:NA;0|S_AXI_HPC0_FPD:NA;0|S_AXI_HP3_FPD:NA;0|S_AXI_HP2_FPD:NA;0|S_AXI_HP1_FPD:NA;0|S_AXI_HP0_FPD:NA;0|S_AXI_ACP:NA;0|S_AXI_ACE:NA;0|SD1:NonSecure;1|SD0:NonSecure;0|SATA1:NonSecure;1|SATA0:NonSecure;1|RPU1:Secure;1|RPU0:Secure;1|QSPI:NonSecure;1|PMU:NA;1|PCIe:NonSecure;0|NAND:NonSecure;0|LDMA:NonSecure;1|GPU:NonSecure;1|GEM3:NonSecure;1|GEM2:NonSecure;0|GEM1:NonSecure;0|GEM0:NonSecure;0|FDMA:NonSecure;1|DP:NonSecure;1|DAP:NA;1|Coresight:NA;1|CSU:NA;1|APU:NA;1}\
+ CONFIG.PSU__PROTECTION__SLAVES {LPD;USB3_1_XHCI;FE300000;FE3FFFFF;0|LPD;USB3_1;FF9E0000;FF9EFFFF;0|LPD;USB3_0_XHCI;FE200000;FE2FFFFF;1|LPD;USB3_0;FF9D0000;FF9DFFFF;1|LPD;UART1;FF010000;FF01FFFF;1|LPD;UART0;FF000000;FF00FFFF;1|LPD;TTC3;FF140000;FF14FFFF;1|LPD;TTC2;FF130000;FF13FFFF;1|LPD;TTC1;FF120000;FF12FFFF;1|LPD;TTC0;FF110000;FF11FFFF;1|FPD;SWDT1;FD4D0000;FD4DFFFF;1|LPD;SWDT0;FF150000;FF15FFFF;1|LPD;SPI1;FF050000;FF05FFFF;0|LPD;SPI0;FF040000;FF04FFFF;0|FPD;SMMU_REG;FD5F0000;FD5FFFFF;1|FPD;SMMU;FD800000;FDFFFFFF;1|FPD;SIOU;FD3D0000;FD3DFFFF;1|FPD;SERDES;FD400000;FD47FFFF;1|LPD;SD1;FF170000;FF17FFFF;1|LPD;SD0;FF160000;FF16FFFF;0|FPD;SATA;FD0C0000;FD0CFFFF;1|LPD;RTC;FFA60000;FFA6FFFF;1|LPD;RSA_CORE;FFCE0000;FFCEFFFF;1|LPD;RPU;FF9A0000;FF9AFFFF;1|LPD;R5_TCM_RAM_GLOBAL;FFE00000;FFE3FFFF;1|LPD;R5_1_Instruction_Cache;FFEC0000;FFECFFFF;1|LPD;R5_1_Data_Cache;FFED0000;FFEDFFFF;1|LPD;R5_1_BTCM_GLOBAL;FFEB0000;FFEBFFFF;1|LPD;R5_1_ATCM_GLOBAL;FFE90000;FFE9FFFF;1|LPD;R5_0_Instruction_Cache;FFE40000;FFE4FFFF;1|LPD;R5_0_Data_Cache;FFE50000;FFE5FFFF;1|LPD;R5_0_BTCM_GLOBAL;FFE20000;FFE2FFFF;1|LPD;R5_0_ATCM_GLOBAL;FFE00000;FFE0FFFF;1|LPD;QSPI_Linear_Address;C0000000;DFFFFFFF;1|LPD;QSPI;FF0F0000;FF0FFFFF;1|LPD;PMU_RAM;FFDC0000;FFDDFFFF;1|LPD;PMU_GLOBAL;FFD80000;FFDBFFFF;1|FPD;PCIE_MAIN;FD0E0000;FD0EFFFF;0|FPD;PCIE_LOW;E0000000;EFFFFFFF;0|FPD;PCIE_HIGH2;8000000000;BFFFFFFFFF;0|FPD;PCIE_HIGH1;600000000;7FFFFFFFF;0|FPD;PCIE_DMA;FD0F0000;FD0FFFFF;0|FPD;PCIE_ATTRIB;FD480000;FD48FFFF;0|LPD;OCM_XMPU_CFG;FFA70000;FFA7FFFF;1|LPD;OCM_SLCR;FF960000;FF96FFFF;1|OCM;OCM;FFFC0000;FFFFFFFF;1|LPD;NAND;FF100000;FF10FFFF;0|LPD;MBISTJTAG;FFCF0000;FFCFFFFF;1|LPD;LPD_XPPU_SINK;FF9C0000;FF9CFFFF;1|LPD;LPD_XPPU;FF980000;FF98FFFF;1|LPD;LPD_SLCR_SECURE;FF4B0000;FF4DFFFF;1|LPD;LPD_SLCR;FF410000;FF4AFFFF;1|LPD;LPD_GPV;FE100000;FE1FFFFF;1|LPD;LPD_DMA_7;FFAF0000;FFAFFFFF;1|LPD;LPD_DMA_6;FFAE0000;FFAEFFFF;1|LPD;LPD_DMA_5;FFAD0000;FFADFFFF;1|LPD;LPD_DMA_4;FFAC0000;FFACFFFF;1|LPD;LPD_DMA_3;FFAB0000;FFABFFFF;1|LPD;LPD_DMA_2;FFAA0000;FFAAFFFF;1|LPD;LPD_DMA_1;FFA90000;FFA9FFFF;1|LPD;LPD_DMA_0;FFA80000;FFA8FFFF;1|LPD;IPI_CTRL;FF380000;FF3FFFFF;1|LPD;IOU_SLCR;FF180000;FF23FFFF;1|LPD;IOU_SECURE_SLCR;FF240000;FF24FFFF;1|LPD;IOU_SCNTRS;FF260000;FF26FFFF;1|LPD;IOU_SCNTR;FF250000;FF25FFFF;1|LPD;IOU_GPV;FE000000;FE0FFFFF;1|LPD;I2C1;FF030000;FF03FFFF;1|LPD;I2C0;FF020000;FF02FFFF;0|FPD;GPU;FD4B0000;FD4BFFFF;1|LPD;GPIO;FF0A0000;FF0AFFFF;1|LPD;GEM3;FF0E0000;FF0EFFFF;1|LPD;GEM2;FF0D0000;FF0DFFFF;0|LPD;GEM1;FF0C0000;FF0CFFFF;0|LPD;GEM0;FF0B0000;FF0BFFFF;0|FPD;FPD_XMPU_SINK;FD4F0000;FD4FFFFF;1|FPD;FPD_XMPU_CFG;FD5D0000;FD5DFFFF;1|FPD;FPD_SLCR_SECURE;FD690000;FD6CFFFF;1|FPD;FPD_SLCR;FD610000;FD68FFFF;1|FPD;FPD_DMA_CH7;FD570000;FD57FFFF;1|FPD;FPD_DMA_CH6;FD560000;FD56FFFF;1|FPD;FPD_DMA_CH5;FD550000;FD55FFFF;1|FPD;FPD_DMA_CH4;FD540000;FD54FFFF;1|FPD;FPD_DMA_CH3;FD530000;FD53FFFF;1|FPD;FPD_DMA_CH2;FD520000;FD52FFFF;1|FPD;FPD_DMA_CH1;FD510000;FD51FFFF;1|FPD;FPD_DMA_CH0;FD500000;FD50FFFF;1|LPD;EFUSE;FFCC0000;FFCCFFFF;1|FPD;Display\
+Port;FD4A0000;FD4AFFFF;1|FPD;DPDMA;FD4C0000;FD4CFFFF;1|FPD;DDR_XMPU5_CFG;FD050000;FD05FFFF;1|FPD;DDR_XMPU4_CFG;FD040000;FD04FFFF;1|FPD;DDR_XMPU3_CFG;FD030000;FD03FFFF;1|FPD;DDR_XMPU2_CFG;FD020000;FD02FFFF;1|FPD;DDR_XMPU1_CFG;FD010000;FD01FFFF;1|FPD;DDR_XMPU0_CFG;FD000000;FD00FFFF;1|FPD;DDR_QOS_CTRL;FD090000;FD09FFFF;1|FPD;DDR_PHY;FD080000;FD08FFFF;1|DDR;DDR_LOW;0;7FFFFFFF;1|DDR;DDR_HIGH;800000000;800000000;0|FPD;DDDR_CTRL;FD070000;FD070FFF;1|LPD;Coresight;FE800000;FEFFFFFF;1|LPD;CSU_DMA;FFC80000;FFC9FFFF;1|LPD;CSU;FFCA0000;FFCAFFFF;1|LPD;CRL_APB;FF5E0000;FF85FFFF;1|FPD;CRF_APB;FD1A0000;FD2DFFFF;1|FPD;CCI_REG;FD5E0000;FD5EFFFF;1|LPD;CAN1;FF070000;FF07FFFF;1|LPD;CAN0;FF060000;FF06FFFF;0|FPD;APU;FD5C0000;FD5CFFFF;1|LPD;APM_INTC_IOU;FFA20000;FFA2FFFF;1|LPD;APM_FPD_LPD;FFA30000;FFA3FFFF;1|FPD;APM_5;FD490000;FD49FFFF;1|FPD;APM_0;FD0B0000;FD0BFFFF;1|LPD;APM2;FFA10000;FFA1FFFF;1|LPD;APM1;FFA00000;FFA0FFFF;1|LPD;AMS;FFA50000;FFA5FFFF;1|FPD;AFI_5;FD3B0000;FD3BFFFF;1|FPD;AFI_4;FD3A0000;FD3AFFFF;1|FPD;AFI_3;FD390000;FD39FFFF;1|FPD;AFI_2;FD380000;FD38FFFF;1|FPD;AFI_1;FD370000;FD37FFFF;1|FPD;AFI_0;FD360000;FD36FFFF;1|LPD;AFIFM6;FF9B0000;FF9BFFFF;1|FPD;ACPU_GIC;F9010000;F907FFFF;1}\
+ CONFIG.PSU__PSS_REF_CLK__FREQMHZ {33.333333} \
+ CONFIG.PSU__QSPI_COHERENCY {0} \
+ CONFIG.PSU__QSPI_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__ENABLE {1} \
+ CONFIG.PSU__QSPI__GRP_FBCLK__IO {MIO 6} \
+ CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4} \
+ CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__QSPI__PERIPHERAL__IO {MIO 0 .. 5} \
+ CONFIG.PSU__QSPI__PERIPHERAL__MODE {Single} \
+ CONFIG.PSU__SATA__LANE0__ENABLE {0} \
+ CONFIG.PSU__SATA__LANE1__ENABLE {1} \
+ CONFIG.PSU__SATA__LANE1__IO {GT Lane3} \
+ CONFIG.PSU__SATA__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SATA__REF_CLK_FREQ {125} \
+ CONFIG.PSU__SATA__REF_CLK_SEL {Ref Clk1} \
+ CONFIG.PSU__SD1_COHERENCY {0} \
+ CONFIG.PSU__SD1_ROUTE_THROUGH_FPD {0} \
+ CONFIG.PSU__SD1__DATA_TRANSFER_MODE {4Bit} \
+ CONFIG.PSU__SD1__GRP_CD__ENABLE {1} \
+ CONFIG.PSU__SD1__GRP_CD__IO {MIO 45} \
+ CONFIG.PSU__SD1__GRP_POW__ENABLE {0} \
+ CONFIG.PSU__SD1__GRP_WP__ENABLE {0} \
+ CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SD1__PERIPHERAL__IO {MIO 46 .. 51} \
+ CONFIG.PSU__SD1__RESET__ENABLE {0} \
+ CONFIG.PSU__SD1__SLOT_TYPE {SD 2.0} \
+ CONFIG.PSU__SWDT0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT0__RESET__ENABLE {0} \
+ CONFIG.PSU__SWDT1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__SWDT1__RESET__ENABLE {0} \
+ CONFIG.PSU__TSU__BUFG_PORT_PAIR {0} \
+ CONFIG.PSU__TTC0__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC0__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC1__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC1__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC2__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC2__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__TTC3__CLOCK__ENABLE {0} \
+ CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__TTC3__WAVEOUT__ENABLE {0} \
+ CONFIG.PSU__UART0__BAUD_RATE {115200} \
+ CONFIG.PSU__UART0__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART0__PERIPHERAL__IO {MIO 18 .. 19} \
+ CONFIG.PSU__UART1__BAUD_RATE {115200} \
+ CONFIG.PSU__UART1__MODEM__ENABLE {0} \
+ CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 20 .. 21} \
+ CONFIG.PSU__USB0_COHERENCY {0} \
+ CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB0__PERIPHERAL__IO {MIO 52 .. 63} \
+ CONFIG.PSU__USB0__REF_CLK_FREQ {26} \
+ CONFIG.PSU__USB0__REF_CLK_SEL {Ref Clk2} \
+ CONFIG.PSU__USB0__RESET__ENABLE {0} \
+ CONFIG.PSU__USB1__RESET__ENABLE {0} \
+ CONFIG.PSU__USB2_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__EMIO__ENABLE {0} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1} \
+ CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane2} \
+ CONFIG.PSU__USB__RESET__MODE {Boot Pin} \
+ CONFIG.PSU__USB__RESET__POLARITY {Active Low} \
+ CONFIG.PSU__USE__IRQ0 {1} \
+ CONFIG.PSU__USE__M_AXI_GP0 {0} \
+ CONFIG.PSU__USE__M_AXI_GP1 {0} \
+ CONFIG.PSU__USE__M_AXI_GP2 {1} \
+ ] $zynq_ultra_ps_e_0
+
+ # Create interface connections
+ connect_bd_intf_net -intf_net zynq_ultra_ps_e_0_M_AXI_HPM0_LPD [get_bd_intf_pins cmsdk_socket/S00_AXI] [get_bd_intf_pins zynq_ultra_ps_e_0/M_AXI_HPM0_LPD]
+
+ # Create port connections
+ connect_bd_net -net cmsdk_socket_nrst [get_bd_pins cmsdk_socket/nrst] [get_bd_pins nanosoc_chip_0/nrst_i]
+ connect_bd_net -net cmsdk_socket_p0_tri_i [get_bd_pins cmsdk_socket/p0_tri_i] [get_bd_pins nanosoc_chip_0/p0_i]
+ connect_bd_net -net cmsdk_socket_p1_tri_i [get_bd_pins cmsdk_socket/p1_tri_i] [get_bd_pins nanosoc_chip_0/p1_i]
+ connect_bd_net -net cmsdk_socket_swdclk_i [get_bd_pins cmsdk_socket/swdclk_i] [get_bd_pins nanosoc_chip_0/swdclk_i]
+ connect_bd_net -net cmsdk_socket_swdio_i [get_bd_pins cmsdk_socket/swdio_tri_i] [get_bd_pins nanosoc_chip_0/swdio_i]
+ connect_bd_net -net ext_reset_in_1 [get_bd_pins cmsdk_socket/ext_reset_in] [get_bd_pins zynq_ultra_ps_e_0/pl_resetn0]
+ connect_bd_net -net p0_tri_o_1 [get_bd_pins cmsdk_socket/p0_tri_o] [get_bd_pins nanosoc_chip_0/p0_o]
+ connect_bd_net -net p0_tri_z_1 [get_bd_pins cmsdk_socket/p0_tri_z] [get_bd_pins nanosoc_chip_0/p0_z]
+ connect_bd_net -net p1_tri_o_1 [get_bd_pins cmsdk_socket/p1_tri_o] [get_bd_pins nanosoc_chip_0/p1_o]
+ connect_bd_net -net p1_tri_z_1 [get_bd_pins cmsdk_socket/p1_tri_z] [get_bd_pins nanosoc_chip_0/p1_z]
+ connect_bd_net -net pmoda_i_1 [get_bd_ports pmoda_tri_i] [get_bd_pins cmsdk_socket/pmoda_tri_i]
+ connect_bd_net -net pmoda_o_concat9_dout [get_bd_ports pmoda_tri_z] [get_bd_pins cmsdk_socket/pmoda_tri_z]
+ connect_bd_net -net swdio_tri_o_1 [get_bd_pins cmsdk_socket/swdio_tri_o] [get_bd_pins nanosoc_chip_0/swdio_o]
+ connect_bd_net -net swdio_tri_z_1 [get_bd_pins cmsdk_socket/swdio_tri_z] [get_bd_pins nanosoc_chip_0/swdio_z]
+ connect_bd_net -net xlconcat_0_dout [get_bd_ports pmoda_tri_o] [get_bd_pins cmsdk_socket/pmoda_tri_o]
+ connect_bd_net -net zynq_ultra_ps_e_0_pl_clk0 [get_bd_pins cmsdk_socket/aclk] [get_bd_pins nanosoc_chip_0/xtal_clk_i] [get_bd_pins zynq_ultra_ps_e_0/maxihpm0_lpd_aclk] [get_bd_pins zynq_ultra_ps_e_0/pl_clk0]
+
+ # Create address segments
+ assign_bd_address -offset 0x80000000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80010000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_gpio_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80020000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80030000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80040000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_2/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80050000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_stream_io_3/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80060000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_0/S_AXI/Reg] -force
+ assign_bd_address -offset 0x80070000 -range 0x00010000 -target_address_space [get_bd_addr_spaces zynq_ultra_ps_e_0/Data] [get_bd_addr_segs cmsdk_socket/axi_uartlite_1/S_AXI/Reg] -force
+ assign_bd_address -offset 0xC0000000 -range 0x00002000 -target_address_space [get_bd_addr_spaces cmsdk_socket/ADPcontrol_0/ahb] [get_bd_addr_segs cmsdk_socket/axi_bram_ctrl_0/S_AXI/Mem0] -force
+
+
+ # Restore current instance
+ current_bd_instance $oldCurInst
+
+}
+# End of create_root_design()
+
+
+
+
+proc available_tcl_procs { } {
+ puts "##################################################################"
+ puts "# Available Tcl procedures to recreate hierarchical blocks:"
+ puts "#"
+ puts "# create_hier_cell_cmsdk_socket parentCell nameHier"
+ puts "# create_root_design"
+ puts "#"
+ puts "#"
+ puts "# The following procedures will create hiearchical blocks with addressing "
+ puts "# for IPs within those blocks and their sub-hierarchical blocks. Addressing "
+ puts "# will not be handled outside those blocks:"
+ puts "#"
+ puts "# create_root_design"
+ puts "#"
+ puts "##################################################################"
+}
+
+available_tcl_procs
diff --git a/implement/fpga/xilinx_vivado/target_fpga_zcu104/design_1_wrapper.v b/implement/fpga/xilinx_vivado/target_fpga_zcu104/design_1_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..ce586c7af967a217fedd3c4fae7ef758794c7931
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_zcu104/design_1_wrapper.v
@@ -0,0 +1,107 @@
+//Copyright 1986-2021 Xilinx, Inc. All Rights Reserved.
+//--------------------------------------------------------------------------------
+//Tool Version: Vivado v.2021.1 (lin64) Build 3247384 Thu Jun 10 19:36:07 MDT 2021
+//Date : Wed Jun 22 15:58:42 2022
+//Host : srv03335 running 64-bit Red Hat Enterprise Linux release 8.6 (Ootpa)
+//Command : generate_target design_1_wrapper.bd
+//Design : design_1_wrapper
+//Purpose : IP block netlist
+//--------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+module design_1_wrapper
+ (PMOD0_0,
+ PMOD0_1,
+ PMOD0_2,
+ PMOD0_3,
+ PMOD0_4,
+ PMOD0_5,
+ PMOD0_6,
+ PMOD0_7
+ );
+// PMOD1_0,
+// PMOD1_1,
+// PMOD1_2,
+// PMOD1_3,
+// PMOD1_4,
+// PMOD1_5,
+// PMOD1_6,
+// PMOD1_7,
+// dip_switch_4bits_tri_i,
+// led_4bits_tri_o);
+
+ inout wire PMOD0_0;
+ inout wire PMOD0_1;
+ inout wire PMOD0_2;
+ inout wire PMOD0_3;
+ inout wire PMOD0_4;
+ inout wire PMOD0_5;
+ inout wire PMOD0_6;
+ inout wire PMOD0_7;
+// inout wire PMOD1_0;
+// inout wire PMOD1_1;
+// inout wire PMOD1_2;
+// inout wire PMOD1_3;
+// inout wire PMOD1_4;
+// inout wire PMOD1_5;
+// inout wire PMOD1_6;
+// inout wire PMOD1_7;
+
+// input wire [3:0]dip_switch_4bits_tri_i;
+// output wire [3:0]led_4bits_tri_o;
+
+ wire [7:0]PMOD0_tri_i;
+ wire [7:0]PMOD0_tri_o;
+ wire [7:0]PMOD0_tri_z;
+
+ assign PMOD0_tri_i[0] = PMOD0_0;
+ assign PMOD0_tri_i[1] = PMOD0_1;
+ assign PMOD0_tri_i[2] = PMOD0_2;
+ assign PMOD0_tri_i[3] = PMOD0_3;
+ assign PMOD0_tri_i[4] = PMOD0_4;
+ assign PMOD0_tri_i[5] = PMOD0_5;
+ assign PMOD0_tri_i[6] = PMOD0_6;
+ assign PMOD0_tri_i[7] = PMOD0_7;
+
+ assign PMOD0_0 = PMOD0_tri_z[0] ? 1'bz : PMOD0_tri_o[0];
+ assign PMOD0_1 = PMOD0_tri_z[1] ? 1'bz : PMOD0_tri_o[1];
+ assign PMOD0_2 = PMOD0_tri_z[2] ? 1'bz : PMOD0_tri_o[2];
+ assign PMOD0_3 = PMOD0_tri_z[3] ? 1'bz : PMOD0_tri_o[3];
+ assign PMOD0_4 = PMOD0_tri_z[4] ? 1'bz : PMOD0_tri_o[4];
+ assign PMOD0_5 = PMOD0_tri_z[5] ? 1'bz : PMOD0_tri_o[5];
+ assign PMOD0_6 = PMOD0_tri_z[6] ? 1'bz : PMOD0_tri_o[6];
+ assign PMOD0_7 = PMOD0_tri_z[7] ? 1'bz : PMOD0_tri_o[7];
+
+// wire [7:0]PMOD1_tri_i;
+// wire [7:0]PMOD1_tri_o;
+// wire [7:0]PMOD1_tri_z;
+
+// assign PMOD1_tri_i[0] = PMOD1_0;
+// assign PMOD1_tri_i[1] = PMOD1_1;
+// assign PMOD1_tri_i[2] = PMOD1_2;
+// assign PMOD1_tri_i[3] = PMOD1_3;
+// assign PMOD1_tri_i[4] = PMOD1_4;
+// assign PMOD1_tri_i[5] = PMOD1_5;
+// assign PMOD1_tri_i[6] = PMOD1_6;
+// assign PMOD1_tri_i[7] = PMOD1_7;
+
+// assign PMOD1_0 = PMOD1_tri_z[0] ? 1'bz : PMOD1_tri_o[0];
+// assign PMOD1_1 = PMOD1_tri_z[1] ? 1'bz : PMOD1_tri_o[1];
+// assign PMOD1_2 = PMOD1_tri_z[2] ? 1'bz : PMOD1_tri_o[2];
+// assign PMOD1_3 = PMOD1_tri_z[3] ? 1'bz : PMOD1_tri_o[3];
+// assign PMOD1_4 = PMOD1_tri_z[4] ? 1'bz : PMOD1_tri_o[4];
+// assign PMOD1_5 = PMOD1_tri_z[5] ? 1'bz : PMOD1_tri_o[5];
+// assign PMOD1_6 = PMOD1_tri_z[6] ? 1'bz : PMOD1_tri_o[6];
+// assign PMOD1_7 = PMOD1_tri_z[7] ? 1'bz : PMOD1_tri_o[7];
+
+ design_1 design_1_i
+ (.pmoda_tri_i(PMOD0_tri_i),
+ .pmoda_tri_o(PMOD0_tri_o),
+ .pmoda_tri_z(PMOD0_tri_z)//,
+// .PMOD1_tri_i(PMOD1_tri_i),
+// .PMOD1_tri_o(PMOD1_tri_o),
+// .PMOD1_tri_z(PMOD1_tri_z),
+// .dip_switch_4bits_tri_i(dip_switch_4bits_tri_i),
+// .led_4bits_tri_o(led_4bits_tri_o)
+ );
+endmodule
diff --git a/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_pinmap.xdc b/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_pinmap.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..4a635dde3eeee4ba52cd771abdd9df48b7e59231
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_pinmap.xdc
@@ -0,0 +1,1031 @@
+##################################################################################
+## ##
+## ZCU104 Rev1.0 Master XDC ##
+## ##
+##################################################################################
+
+#Other net PACKAGE_PIN V17 - SYSMON_DXN Bank 0 - DXN
+#Other net PACKAGE_PIN V18 - SYSMON_DXP Bank 0 - DXP
+#Other net PACKAGE_PIN R17 - SYSMON_AGND Bank 0 - GNDADC
+#Other net PACKAGE_PIN AA12 - 3N5824 Bank 0 - POR_OVERRIDE
+#Other net PACKAGE_PIN AA13 - 3N5822 Bank 0 - PUDC_B
+#Other net PACKAGE_PIN R18 - FPGA_SYSMON_AVCC Bank 0 - VCCADC
+#Other net PACKAGE_PIN U17 - SYSMON_VN_R Bank 0 - VN
+#Other net PACKAGE_PIN T18 - SYSMON_VP_R Bank 0 - VP
+#Other net PACKAGE_PIN T17 - SYSMON_AGND Bank 0 - VREFN
+#Other net PACKAGE_PIN U18 - SYSMON_AGND Bank 0 - VREFP
+#set_property PACKAGE_PIN B21 [get_ports "5N7582"] ;# Bank 28 VCCO - VCC1V8 - IO_L24N_T3U_N11_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7582"] ;# Bank 28 VCCO - VCC1V8 - IO_L24N_T3U_N11_28
+#set_property PACKAGE_PIN B20 [get_ports "5N7577"] ;# Bank 28 VCCO - VCC1V8 - IO_L24P_T3U_N10_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7577"] ;# Bank 28 VCCO - VCC1V8 - IO_L24P_T3U_N10_28
+#set_property PACKAGE_PIN A23 [get_ports "5N7578"] ;# Bank 28 VCCO - VCC1V8 - IO_L23N_T3U_N9_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7578"] ;# Bank 28 VCCO - VCC1V8 - IO_L23N_T3U_N9_28
+#set_property PACKAGE_PIN A22 [get_ports "5N7569"] ;# Bank 28 VCCO - VCC1V8 - IO_L23P_T3U_N8_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7569"] ;# Bank 28 VCCO - VCC1V8 - IO_L23P_T3U_N8_28
+#set_property PACKAGE_PIN B19 [get_ports "5N7570"] ;# Bank 28 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7570"] ;# Bank 28 VCCO - VCC1V8 - IO_L22N_T3U_N7_DBC_AD0N_28
+#set_property PACKAGE_PIN B18 [get_ports "5N7565"] ;# Bank 28 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7565"] ;# Bank 28 VCCO - VCC1V8 - IO_L22P_T3U_N6_DBC_AD0P_28
+#set_property PACKAGE_PIN A21 [get_ports "5N7709"] ;# Bank 28 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7709"] ;# Bank 28 VCCO - VCC1V8 - IO_L21N_T3L_N5_AD8N_28
+#set_property PACKAGE_PIN A18 [get_ports "5N7704"] ;# Bank 28 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7704"] ;# Bank 28 VCCO - VCC1V8 - IO_L19P_T3L_N0_DBC_AD9P_28
+#set_property PACKAGE_PIN B23 [get_ports "5N7581"] ;# Bank 28 VCCO - VCC1V8 - IO_T3U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7581"] ;# Bank 28 VCCO - VCC1V8 - IO_T3U_N12_28
+#set_property PACKAGE_PIN F25 [get_ports "5N7703"] ;# Bank 28 VCCO - VCC1V8 - IO_T2U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7703"] ;# Bank 28 VCCO - VCC1V8 - IO_T2U_N12_28
+#set_property PACKAGE_PIN G26 [get_ports "5N7702"] ;# Bank 28 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7702"] ;# Bank 28 VCCO - VCC1V8 - IO_L18N_T2U_N11_AD2N_28
+#set_property PACKAGE_PIN G25 [get_ports "5N7694"] ;# Bank 28 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7694"] ;# Bank 28 VCCO - VCC1V8 - IO_L18P_T2U_N10_AD2P_28
+#set_property PACKAGE_PIN C23 [get_ports "5N7693"] ;# Bank 28 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7693"] ;# Bank 28 VCCO - VCC1V8 - IO_L17N_T2U_N9_AD10N_28
+#set_property PACKAGE_PIN D22 [get_ports "5N7690"] ;# Bank 28 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7690"] ;# Bank 28 VCCO - VCC1V8 - IO_L17P_T2U_N8_AD10P_28
+#set_property PACKAGE_PIN D24 [get_ports "5N7688"] ;# Bank 28 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7688"] ;# Bank 28 VCCO - VCC1V8 - IO_L16N_T2U_N7_QBC_AD3N_28
+#set_property PACKAGE_PIN E24 [get_ports "5N7682"] ;# Bank 28 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7682"] ;# Bank 28 VCCO - VCC1V8 - IO_L16P_T2U_N6_QBC_AD3P_28
+#set_property PACKAGE_PIN C22 [get_ports "5N7681"] ;# Bank 28 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7681"] ;# Bank 28 VCCO - VCC1V8 - IO_L15N_T2L_N5_AD11N_28
+#set_property PACKAGE_PIN C21 [get_ports "5N7678"] ;# Bank 28 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7678"] ;# Bank 28 VCCO - VCC1V8 - IO_L15P_T2L_N4_AD11P_28
+#set_property PACKAGE_PIN G24 [get_ports "5N7676"] ;# Bank 28 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7676"] ;# Bank 28 VCCO - VCC1V8 - IO_L14N_T2L_N3_GC_28
+#set_property PACKAGE_PIN G23 [get_ports "5N7672"] ;# Bank 28 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7672"] ;# Bank 28 VCCO - VCC1V8 - IO_L14P_T2L_N2_GC_28
+#set_property PACKAGE_PIN F20 [get_ports "5N7532"] ;# Bank 28 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7532"] ;# Bank 28 VCCO - VCC1V8 - IO_L10N_T1U_N7_QBC_AD4N_28
+#set_property PACKAGE_PIN G20 [get_ports "5N7533"] ;# Bank 28 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7533"] ;# Bank 28 VCCO - VCC1V8 - IO_L10P_T1U_N6_QBC_AD4P_28
+#set_property PACKAGE_PIN D21 [get_ports "5N7524"] ;# Bank 28 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7524"] ;# Bank 28 VCCO - VCC1V8 - IO_L9N_T1L_N5_AD12N_28
+#set_property PACKAGE_PIN D20 [get_ports "5N7525"] ;# Bank 28 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7525"] ;# Bank 28 VCCO - VCC1V8 - IO_L9P_T1L_N4_AD12P_28
+#set_property PACKAGE_PIN H22 [get_ports "5N7520"] ;# Bank 28 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7520"] ;# Bank 28 VCCO - VCC1V8 - IO_L8N_T1L_N3_AD5N_28
+#set_property PACKAGE_PIN H21 [get_ports "5N7521"] ;# Bank 28 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7521"] ;# Bank 28 VCCO - VCC1V8 - IO_L8P_T1L_N2_AD5P_28
+#set_property PACKAGE_PIN D19 [get_ports "5N7512"] ;# Bank 28 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7512"] ;# Bank 28 VCCO - VCC1V8 - IO_L7N_T1L_N1_QBC_AD13N_28
+#set_property PACKAGE_PIN E19 [get_ports "5N7513"] ;# Bank 28 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7513"] ;# Bank 28 VCCO - VCC1V8 - IO_L7P_T1L_N0_QBC_AD13P_28
+#set_property PACKAGE_PIN E20 [get_ports "5N7726"] ;# Bank 28 VCCO - VCC1V8 - IO_T1U_N12_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7726"] ;# Bank 28 VCCO - VCC1V8 - IO_T1U_N12_28
+#set_property PACKAGE_PIN H23 [get_ports "5N7508"] ;# Bank 28 VCCO - VCC1V8 - IO_T0U_N12_VRP_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7508"] ;# Bank 28 VCCO - VCC1V8 - IO_T0U_N12_VRP_28
+#set_property PACKAGE_PIN H24 [get_ports "5N7509"] ;# Bank 28 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7509"] ;# Bank 28 VCCO - VCC1V8 - IO_L6N_T0U_N11_AD6N_28
+#set_property PACKAGE_PIN J24 [get_ports "5N7500"] ;# Bank 28 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7500"] ;# Bank 28 VCCO - VCC1V8 - IO_L6P_T0U_N10_AD6P_28
+#set_property PACKAGE_PIN H26 [get_ports "5N7501"] ;# Bank 28 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7501"] ;# Bank 28 VCCO - VCC1V8 - IO_L5N_T0U_N9_AD14N_28
+#set_property PACKAGE_PIN J25 [get_ports "5N7496"] ;# Bank 28 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7496"] ;# Bank 28 VCCO - VCC1V8 - IO_L5P_T0U_N8_AD14P_28
+#set_property PACKAGE_PIN K23 [get_ports "5N7497"] ;# Bank 28 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7497"] ;# Bank 28 VCCO - VCC1V8 - IO_L4N_T0U_N7_DBC_AD7N_28
+#set_property PACKAGE_PIN K22 [get_ports "5N7488"] ;# Bank 28 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7488"] ;# Bank 28 VCCO - VCC1V8 - IO_L4P_T0U_N6_DBC_AD7P_28
+#set_property PACKAGE_PIN J22 [get_ports "5N7489"] ;# Bank 28 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7489"] ;# Bank 28 VCCO - VCC1V8 - IO_L3N_T0L_N5_AD15N_28
+#set_property PACKAGE_PIN J21 [get_ports "5N7484"] ;# Bank 28 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7484"] ;# Bank 28 VCCO - VCC1V8 - IO_L3P_T0L_N4_AD15P_28
+#set_property PACKAGE_PIN K24 [get_ports "5N7485"] ;# Bank 28 VCCO - VCC1V8 - IO_L2N_T0L_N3_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7485"] ;# Bank 28 VCCO - VCC1V8 - IO_L2N_T0L_N3_28
+#set_property PACKAGE_PIN L23 [get_ports "5N7476"] ;# Bank 28 VCCO - VCC1V8 - IO_L2P_T0L_N2_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7476"] ;# Bank 28 VCCO - VCC1V8 - IO_L2P_T0L_N2_28
+#set_property PACKAGE_PIN L22 [get_ports "5N7477"] ;# Bank 28 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7477"] ;# Bank 28 VCCO - VCC1V8 - IO_L1N_T0L_N1_DBC_28
+#set_property PACKAGE_PIN L21 [get_ports "5N7472"] ;# Bank 28 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_28
+#set_property IOSTANDARD LVCMOSxx [get_ports "5N7472"] ;# Bank 28 VCCO - VCC1V8 - IO_L1P_T0L_N0_DBC_28
+#Other net PACKAGE_PIN M23 - 5N7631 Bank 28 - VREF_28
+#set_property PACKAGE_PIN A9 [get_ports "4N9784"] ;# Bank 68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9784"] ;# Bank 68 VCCO - VADJ_FMC - IO_T3U_N12_68
+#set_property PACKAGE_PIN G13 [get_ports "4N9781"] ;# Bank 68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9781"] ;# Bank 68 VCCO - VADJ_FMC - IO_T2U_N12_68
+#set_property PACKAGE_PIN G11 [get_ports "4N9820"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9820"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_68
+#set_property PACKAGE_PIN H11 [get_ports "4N9817"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9817"] ;# Bank 68 VCCO - VADJ_FMC - IO_L13P_T2L_N0_GC_QBC_68
+#set_property PACKAGE_PIN G9 [get_ports "4N9823"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9823"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_68
+#set_property PACKAGE_PIN H9 [get_ports "4N9826"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9826"] ;# Bank 68 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_68
+#set_property PACKAGE_PIN D7 [get_ports "4N9778"] ;# Bank 68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9778"] ;# Bank 68 VCCO - VADJ_FMC - IO_T1U_N12_68
+#set_property PACKAGE_PIN H14 [get_ports "VRP_68"] ;# Bank 68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_68"] ;# Bank 68 VCCO - VADJ_FMC - IO_T0U_N12_VRP_68
+#set_property PACKAGE_PIN K13 [get_ports "4N9759"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9759"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_68
+#set_property PACKAGE_PIN L14 [get_ports "4N9760"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9760"] ;# Bank 68 VCCO - VADJ_FMC - IO_L6P_T0U_N10_AD6P_68
+#set_property PACKAGE_PIN J14 [get_ports "4N9755"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9755"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5N_T0U_N9_AD14N_68
+#set_property PACKAGE_PIN K14 [get_ports "4N9756"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9756"] ;# Bank 68 VCCO - VADJ_FMC - IO_L5P_T0U_N8_AD14P_68
+#set_property PACKAGE_PIN J11 [get_ports "4N9771"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9771"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_68
+#set_property PACKAGE_PIN K12 [get_ports "4N9772"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9772"] ;# Bank 68 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_68
+#set_property PACKAGE_PIN L11 [get_ports "4N9767"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9767"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_68
+#set_property PACKAGE_PIN L12 [get_ports "4N9768"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#set_property IOSTANDARD LVCMOSxx [get_ports "4N9768"] ;# Bank 68 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_68
+#Other net PACKAGE_PIN J12 - 4N9503 Bank 68 - VREF_68
+#set_property PACKAGE_PIN J20 [get_ports "7N10213"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10213"] ;# Bank 67 VCCO - VADJ_FMC - IO_T3U_N12_67
+#set_property PACKAGE_PIN J19 [get_ports "7N10210"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10210"] ;# Bank 67 VCCO - VADJ_FMC - IO_T2U_N12_67
+#set_property PACKAGE_PIN G16 [get_ports "FMC_LPC_LA09_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L18N_T2U_N11_AD2N_67
+#set_property PACKAGE_PIN D14 [get_ports "7N10403"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10403"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11N_T1U_N9_GC_67
+#set_property PACKAGE_PIN D15 [get_ports "7N10406"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10406"] ;# Bank 67 VCCO - VADJ_FMC - IO_L11P_T1U_N8_GC_67
+#set_property PACKAGE_PIN F13 [get_ports "7N10612"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10612"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10N_T1U_N7_QBC_AD4N_67
+#set_property PACKAGE_PIN G14 [get_ports "7N10614"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10614"] ;# Bank 67 VCCO - VADJ_FMC - IO_L10P_T1U_N6_QBC_AD4P_67
+#set_property PACKAGE_PIN E13 [get_ports "7N10207"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10207"] ;# Bank 67 VCCO - VADJ_FMC - IO_T1U_N12_67
+#set_property PACKAGE_PIN C14 [get_ports "7N10204"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10204"] ;# Bank 67 VCCO - VADJ_FMC - IO_T0U_N12_VRP_67
+#set_property PACKAGE_PIN C12 [get_ports "FMC_LPC_LA14_N"] ;# Bank 67 VCCO - VADJ_FMC - IO_L6N_T0U_N11_AD6N_67
+#set_property PACKAGE_PIN B13 [get_ports "7N10197"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10197"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4N_T0U_N7_DBC_AD7N_67
+#set_property PACKAGE_PIN B14 [get_ports "7N10198"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10198"] ;# Bank 67 VCCO - VADJ_FMC - IO_L4P_T0U_N6_DBC_AD7P_67
+#set_property PACKAGE_PIN A14 [get_ports "7N10193"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10193"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3N_T0L_N5_AD15N_67
+#set_property PACKAGE_PIN A15 [get_ports "7N10194"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10194"] ;# Bank 67 VCCO - VADJ_FMC - IO_L3P_T0L_N4_AD15P_67
+#set_property PACKAGE_PIN B15 [get_ports "7N10185"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10185"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2N_T0L_N3_67
+#set_property PACKAGE_PIN B16 [get_ports "7N10186"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10186"] ;# Bank 67 VCCO - VADJ_FMC - IO_L2P_T0L_N2_67
+#set_property PACKAGE_PIN A16 [get_ports "7N10181"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10181"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1N_T0L_N1_DBC_67
+#set_property PACKAGE_PIN A17 [get_ports "7N10182"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10182"] ;# Bank 67 VCCO - VADJ_FMC - IO_L1P_T0L_N0_DBC_67
+#Other net PACKAGE_PIN L18 - 7N9719 Bank 67 - VREF_67
+#set_property PACKAGE_PIN AF10 [get_ports "7N10601"] ;# Bank 66 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10601"] ;# Bank 66 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_66
+#set_property PACKAGE_PIN AC14 [get_ports "7N10603"] ;# Bank 66 VCCO - VCC1V2 - IO_T3U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10603"] ;# Bank 66 VCCO - VCC1V2 - IO_T3U_N12_66
+#set_property PACKAGE_PIN AH8 [get_ports "7N10599"] ;# Bank 66 VCCO - VCC1V2 - IO_T2U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10599"] ;# Bank 66 VCCO - VCC1V2 - IO_T2U_N12_66
+#set_property PACKAGE_PIN AJ12 [get_ports "7N10597"] ;# Bank 66 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10597"] ;# Bank 66 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_66
+#set_property PACKAGE_PIN AL13 [get_ports "7N10593"] ;# Bank 66 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10593"] ;# Bank 66 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_66
+#set_property PACKAGE_PIN AM13 [get_ports "7N10595"] ;# Bank 66 VCCO - VCC1V2 - IO_T1U_N12_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10595"] ;# Bank 66 VCCO - VCC1V2 - IO_T1U_N12_66
+#set_property PACKAGE_PIN AP8 [get_ports "VRP_66"] ;# Bank 66 VCCO - VCC1V2 - IO_T0U_N12_VRP_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_66"] ;# Bank 66 VCCO - VCC1V2 - IO_T0U_N12_VRP_66
+#set_property PACKAGE_PIN AP12 [get_ports "7N10591"] ;# Bank 66 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_66
+#set_property IOSTANDARD LVCMOSxx [get_ports "7N10591"] ;# Bank 66 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_66
+#Other net PACKAGE_PIN AB12 - 7N8282 Bank 66 - VREF_66
+#set_property PACKAGE_PIN AE19 [get_ports "6N12439"] ;# Bank 65 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12439"] ;# Bank 65 VCCO - VCC1V2 - IO_L19N_T3L_N1_DBC_AD9N_65
+#set_property PACKAGE_PIN AE22 [get_ports "6N12442"] ;# Bank 65 VCCO - VCC1V2 - IO_T3U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12442"] ;# Bank 65 VCCO - VCC1V2 - IO_T3U_N12_65
+#set_property PACKAGE_PIN AF20 [get_ports "6N12436"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12436"] ;# Bank 65 VCCO - VCC1V2 - IO_T2U_N12_65
+#set_property PACKAGE_PIN AH23 [get_ports "6N12433"] ;# Bank 65 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12433"] ;# Bank 65 VCCO - VCC1V2 - IO_L13N_T2L_N1_GC_QBC_65
+#set_property PACKAGE_PIN AL21 [get_ports "6N12427"] ;# Bank 65 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12427"] ;# Bank 65 VCCO - VCC1V2 - IO_L7N_T1L_N1_QBC_AD13N_65
+#set_property PACKAGE_PIN AH19 [get_ports "6N12430"] ;# Bank 65 VCCO - VCC1V2 - IO_T1U_N12_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12430"] ;# Bank 65 VCCO - VCC1V2 - IO_T1U_N12_65
+#set_property PACKAGE_PIN AM20 [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V2 - IO_T0U_N12_VRP_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "VRP_65"] ;# Bank 65 VCCO - VCC1V2 - IO_T0U_N12_VRP_65
+#set_property PACKAGE_PIN AP20 [get_ports "6N12401"] ;# Bank 65 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_65
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12401"] ;# Bank 65 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_65
+#Other net PACKAGE_PIN AB20 - 6N11582 Bank 65 - VREF_65
+#set_property PACKAGE_PIN AA17 [get_ports "6N12707"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12707"] ;# Bank 64 VCCO - VCC1V2 - IO_T3U_N12_64
+#set_property PACKAGE_PIN AE17 [get_ports "6N12705"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12705"] ;# Bank 64 VCCO - VCC1V2 - IO_L15P_T2L_N4_AD11P_64
+#set_property PACKAGE_PIN AP14 [get_ports "VRP_64"] ;# Bank 64 VCCO - VCC1V2 - IO_T0U_N12_VRP_64
+#set_property PACKAGE_PIN AP15 [get_ports "6N12788"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12788"] ;# Bank 64 VCCO - VCC1V2 - IO_L5N_T0U_N9_AD14N_64
+#set_property PACKAGE_PIN AP16 [get_ports "6N12789"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12789"] ;# Bank 64 VCCO - VCC1V2 - IO_L5P_T0U_N8_AD14P_64
+#set_property PACKAGE_PIN AN14 [get_ports "6N12782"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12782"] ;# Bank 64 VCCO - VCC1V2 - IO_L4N_T0U_N7_DBC_AD7N_64
+#set_property PACKAGE_PIN AM14 [get_ports "6N12783"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12783"] ;# Bank 64 VCCO - VCC1V2 - IO_L4P_T0U_N6_DBC_AD7P_64
+#set_property PACKAGE_PIN AN18 [get_ports "6N12780"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12780"] ;# Bank 64 VCCO - VCC1V2 - IO_L3N_T0L_N5_AD15N_64
+#set_property PACKAGE_PIN AM18 [get_ports "6N12781"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12781"] ;# Bank 64 VCCO - VCC1V2 - IO_L3P_T0L_N4_AD15P_64
+#set_property PACKAGE_PIN AP13 [get_ports "6N12774"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12774"] ;# Bank 64 VCCO - VCC1V2 - IO_L2N_T0L_N3_64
+#set_property PACKAGE_PIN AN13 [get_ports "6N12775"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12775"] ;# Bank 64 VCCO - VCC1V2 - IO_L2P_T0L_N2_64
+#set_property PACKAGE_PIN AP17 [get_ports "6N12772"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64
+#set_property IOSTANDARD LVCMOSxx [get_ports "6N12772"] ;# Bank 64 VCCO - VCC1V2 - IO_L1N_T0L_N1_DBC_64
+#set_property PACKAGE_PIN AP18 [get_ports "6N12773"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64
+#set_property IOSTANDARD LVCMOSxxn [get_ports "6N12773"] ;# Bank 64 VCCO - VCC1V2 - IO_L1P_T0L_N0_DBC_64
+#Other net PACKAGE_PIN AG16 - 6N11370 Bank 64 - VREF_64
+#Other net PACKAGE_PIN AD9 - MGT1V2 Bank 224 - MGTAVTTRCAL_R
+#Other net PACKAGE_PIN A24 - MIO0_QSPI_LWR_CLK Bank 500 - PS_MIO0
+#Other net PACKAGE_PIN C24 - MIO1_QSPI_LWR_DQ1 Bank 500 - PS_MIO1
+#Other net PACKAGE_PIN F26 - 53N7803 Bank 500 - PS_MIO10
+#Other net PACKAGE_PIN B26 - 53N7806 Bank 500 - PS_MIO11
+#Other net PACKAGE_PIN C27 - 53N7809 Bank 500 - PS_MIO12
+#Other net PACKAGE_PIN D27 - 53N7788 Bank 500 - PS_MIO13
+#Other net PACKAGE_PIN A27 - 53N7844 Bank 500 - PS_MIO14
+#Other net PACKAGE_PIN E27 - 53N7842 Bank 500 - PS_MIO15
+#Other net PACKAGE_PIN A28 - MIO16_I2C1_SCL Bank 500 - PS_MIO16
+#Other net PACKAGE_PIN C29 - MIO17_I2C1_SDA Bank 500 - PS_MIO17
+#Other net PACKAGE_PIN F27 - UART0_TXD_MIO18_RXD Bank 500 - PS_MIO18
+#Other net PACKAGE_PIN B28 - UART0_RXD_MIO19_TXD Bank 500 - PS_MIO19
+#Other net PACKAGE_PIN B24 - MIO2_QSPI_LWR_DQ2 Bank 500 - PS_MIO2
+#Other net PACKAGE_PIN E29 - UART1_RXD_MIO20_TXD Bank 500 - PS_MIO20
+#Other net PACKAGE_PIN C28 - UART1_TXD_MIO21_RXD Bank 500 - PS_MIO21
+#Other net PACKAGE_PIN F28 - 53N7824 Bank 500 - PS_MIO22
+#Other net PACKAGE_PIN B29 - 53N7822 Bank 500 - PS_MIO23
+#Other net PACKAGE_PIN E28 - MIO24_CAN_TX Bank 500 - PS_MIO24
+#Other net PACKAGE_PIN D29 - MIO25_CAN_RX Bank 500 - PS_MIO25
+#Other net PACKAGE_PIN E25 - MIO3_QSPI_LWR_DQ3 Bank 500 - PS_MIO3
+#Other net PACKAGE_PIN A25 - MIO4_QSPI_LWR_DQ0 Bank 500 - PS_MIO4
+#Other net PACKAGE_PIN D25 - MIO5_QSPI_LWR_CS_B Bank 500 - PS_MIO5
+#Other net PACKAGE_PIN A26 - 53N6816 Bank 500 - PS_MIO6
+#Other net PACKAGE_PIN B25 - 53N7794 Bank 500 - PS_MIO7
+#Other net PACKAGE_PIN D26 - 53N7797 Bank 500 - PS_MIO8
+#Other net PACKAGE_PIN C26 - 53N7800 Bank 500 - PS_MIO9
+#Other net PACKAGE_PIN AA25 - PS_SYSMON_AVCC Bank 500 - VCC_PSADC
+#Other net PACKAGE_PIN AA24 - PS_SYSMON_AGND Bank 500 - GND_PSADC
+#Other net PACKAGE_PIN A29 - 53N7791 Bank 501 - PS_MIO26
+#Other net PACKAGE_PIN A30 - MIO27_DP_AUX_OUT Bank 501 - PS_MIO27
+#Other net PACKAGE_PIN A31 - MIO28_DP_HPD Bank 501 - PS_MIO28
+#Other net PACKAGE_PIN A32 - MIO29_DP_OE Bank 501 - PS_MIO29
+#Other net PACKAGE_PIN A33 - MIO30_DP_AUX_IN Bank 501 - PS_MIO30
+#Other net PACKAGE_PIN B30 - 53N7736 Bank 501 - PS_MIO31
+#Other net PACKAGE_PIN B31 - 53N7739 Bank 501 - PS_MIO32
+#Other net PACKAGE_PIN B33 - 53N7742 Bank 501 - PS_MIO33
+#Other net PACKAGE_PIN B34 - 53N7745 Bank 501 - PS_MIO34
+#Other net PACKAGE_PIN C31 - 53N7748 Bank 501 - PS_MIO35
+#Other net PACKAGE_PIN C32 - 53N7751 Bank 501 - PS_MIO36
+#Other net PACKAGE_PIN C33 - 53N7754 Bank 501 - PS_MIO37
+#Other net PACKAGE_PIN C34 - 53N7768 Bank 501 - PS_MIO38
+#Other net PACKAGE_PIN D30 - 53N7771 Bank 501 - PS_MIO39
+#Other net PACKAGE_PIN D31 - 53N7773 Bank 501 - PS_MIO40
+#Other net PACKAGE_PIN D32 - 53N7775 Bank 501 - PS_MIO41
+#Other net PACKAGE_PIN D34 - 53N7777 Bank 501 - PS_MIO42
+#Other net PACKAGE_PIN E30 - 53N6798 Bank 501 - PS_MIO43
+#Other net PACKAGE_PIN E32 - 53N7783 Bank 501 - PS_MIO44
+#Other net PACKAGE_PIN E33 - MIO45_SDIO_DETECT Bank 501 - PS_MIO45
+#Other net PACKAGE_PIN E34 - MIO46_SDIO_DAT0_R Bank 501 - PS_MIO46
+#Other net PACKAGE_PIN F30 - MIO47_SDIO_DAT1_R Bank 501 - PS_MIO47
+#Other net PACKAGE_PIN F31 - MIO48_SDIO_DAT2_R Bank 501 - PS_MIO48
+#Other net PACKAGE_PIN F32 - MIO49_SDIO_DAT3_R Bank 501 - PS_MIO49
+#Other net PACKAGE_PIN F33 - MIO50_SDIO_CMD_R Bank 501 - PS_MIO50
+#Other net PACKAGE_PIN F34 - MIO51_SDIO_CLK_R Bank 501 - PS_MIO51
+#Other net PACKAGE_PIN G29 - MIO52_USB_CLK Bank 502 - PS_MIO52
+#Other net PACKAGE_PIN G30 - MIO53_USB_DIR Bank 502 - PS_MIO53
+#Other net PACKAGE_PIN G31 - MIO54_USB_DATA2_R Bank 502 - PS_MIO54
+#Other net PACKAGE_PIN G33 - MIO55_USB_NXT Bank 502 - PS_MIO55
+#Other net PACKAGE_PIN G34 - MIO56_USB_DATA0_R Bank 502 - PS_MIO56
+#Other net PACKAGE_PIN H29 - MIO57_USB_DATA1_R Bank 502 - PS_MIO57
+#Other net PACKAGE_PIN H31 - MIO58_USB_STP_R Bank 502 - PS_MIO58
+#Other net PACKAGE_PIN H32 - MIO59_USB_DATA3_R Bank 502 - PS_MIO59
+#Other net PACKAGE_PIN H33 - MIO60_USB_DATA4_R Bank 502 - PS_MIO60
+#Other net PACKAGE_PIN H34 - MIO61_USB_DATA5_R Bank 502 - PS_MIO61
+#Other net PACKAGE_PIN J29 - MIO62_USB_DATA6_R Bank 502 - PS_MIO62
+#Other net PACKAGE_PIN J30 - MIO63_USB_DATA7_R Bank 502 - PS_MIO63
+#Other net PACKAGE_PIN J31 - MIO64_ENET_TX_CLK Bank 502 - PS_MIO64
+#Other net PACKAGE_PIN J32 - MIO65_ENET_TX_D0 Bank 502 - PS_MIO65
+#Other net PACKAGE_PIN J34 - MIO66_ENET_TX_D1 Bank 502 - PS_MIO66
+#Other net PACKAGE_PIN K28 - MIO67_ENET_TX_D2 Bank 502 - PS_MIO67
+#Other net PACKAGE_PIN K29 - MIO68_ENET_TX_D3 Bank 502 - PS_MIO68
+#Other net PACKAGE_PIN K30 - MIO69_ENET_TX_CTRL Bank 502 - PS_MIO69
+#Other net PACKAGE_PIN K31 - MIO70_ENET_RX_CLK Bank 502 - PS_MIO70
+#Other net PACKAGE_PIN K32 - MIO71_ENET_RX_D0 Bank 502 - PS_MIO71
+#Other net PACKAGE_PIN K33 - MIO72_ENET_RX_D1 Bank 502 - PS_MIO72
+#Other net PACKAGE_PIN K34 - MIO73_ENET_RX_D2 Bank 502 - PS_MIO73
+#Other net PACKAGE_PIN L29 - MIO74_ENET_RX_D3 Bank 502 - PS_MIO74
+#Other net PACKAGE_PIN L30 - MIO75_ENET_RX_CTRL Bank 502 - PS_MIO75
+#Other net PACKAGE_PIN L33 - MIO76_ENET_MDC Bank 502 - PS_MIO76
+#Other net PACKAGE_PIN L34 - MIO77_ENET_MDIO Bank 502 - PS_MIO77
+#Other net PACKAGE_PIN N24 - PS_DONE Bank 503 - PS_DONE
+#Other net PACKAGE_PIN T25 - PS_ERR_OUT Bank 503 - PS_ERROR_OUT
+#Other net PACKAGE_PIN R25 - PS_ERR_STATUS Bank 503 - PS_ERROR_STATUS
+#Other net PACKAGE_PIN P24 - PS_INIT_B Bank 503 - PS_INIT_B
+#Other net PACKAGE_PIN K27 - FPGA_TCK Bank 503 - PS_JTAG_TCK
+#Other net PACKAGE_PIN J27 - FPGA_TDI Bank 503 - PS_JTAG_TDI
+#Other net PACKAGE_PIN G28 - FPGA_TDO_FMC_TDI Bank 503 - PS_JTAG_TDO
+#Other net PACKAGE_PIN H28 - FPGA_TMS Bank 503 - PS_JTAG_TMS
+#Other net PACKAGE_PIN H27 - PS_MODE0 Bank 503 - PS_MODE0
+#Other net PACKAGE_PIN J26 - PS_MODE1 Bank 503 - PS_MODE1
+#Other net PACKAGE_PIN K26 - PS_MODE2 Bank 503 - PS_MODE2
+#Other net PACKAGE_PIN K25 - PS_MODE3 Bank 503 - PS_MODE3
+#Other net PACKAGE_PIN M25 - PS_PADI Bank 503 - PS_PADI
+#Other net PACKAGE_PIN L25 - PS_PADO Bank 503 - PS_PADO
+#Other net PACKAGE_PIN M24 - PS_POR_B Bank 503 - PS_POR_B
+#Other net PACKAGE_PIN T24 - PS_PROG_B Bank 503 - PS_PROG_B
+#Other net PACKAGE_PIN R24 - PS_REF_CLK Bank 503 - PS_REF_CLK
+#Other net PACKAGE_PIN P25 - PS_SRST_B Bank 503 - PS_SRST_B
+#Other net PACKAGE_PIN AN34 - DDR4_A0 Bank 504 - PS_DDR_A0
+#Other net PACKAGE_PIN AM34 - DDR4_A1 Bank 504 - PS_DDR_A1
+#Other net PACKAGE_PIN AG31 - DDR4_A10 Bank 504 - PS_DDR_A10
+#Other net PACKAGE_PIN AF31 - DDR4_A11 Bank 504 - PS_DDR_A11
+#Other net PACKAGE_PIN AG30 - DDR4_A12 Bank 504 - PS_DDR_A12
+#Other net PACKAGE_PIN AF30 - DDR4_A13 Bank 504 - PS_DDR_A13
+#Other net PACKAGE_PIN AG29 - DDR4_A14_WE_B Bank 504 - PS_DDR_A14
+#Other net PACKAGE_PIN AG28 - DDR4_A15_CAS_B Bank 504 - PS_DDR_A15
+#Other net PACKAGE_PIN AF28 - DDR4_A16_RAS_B Bank 504 - PS_DDR_A16
+#Other net PACKAGE_PIN AF26 - 68N6692 Bank 504 - PS_DDR_A17
+#Other net PACKAGE_PIN AM33 - DDR4_A2 Bank 504 - PS_DDR_A2
+#Other net PACKAGE_PIN AL34 - DDR4_A3 Bank 504 - PS_DDR_A3
+#Other net PACKAGE_PIN AL33 - DDR4_A4 Bank 504 - PS_DDR_A4
+#Other net PACKAGE_PIN AK33 - DDR4_A5 Bank 504 - PS_DDR_A5
+#Other net PACKAGE_PIN AK30 - DDR4_A6 Bank 504 - PS_DDR_A6
+#Other net PACKAGE_PIN AJ30 - DDR4_A7 Bank 504 - PS_DDR_A7
+#Other net PACKAGE_PIN AJ31 - DDR4_A8 Bank 504 - PS_DDR_A8
+#Other net PACKAGE_PIN AH31 - DDR4_A9 Bank 504 - PS_DDR_A9
+#Other net PACKAGE_PIN AE25 - DDR4_ACT_B Bank 504 - PS_DDR_ACT_N
+#Other net PACKAGE_PIN AB26 - DDR4_ALERT_B Bank 504 - PS_DDR_ALERT_N
+#Other net PACKAGE_PIN AE27 - DDR4_BA0 Bank 504 - PS_DDR_BA0
+#Other net PACKAGE_PIN AE28 - DDR4_BA1 Bank 504 - PS_DDR_BA1
+#Other net PACKAGE_PIN AD27 - DDR4_BG0 Bank 504 - PS_DDR_BG0
+#Other net PACKAGE_PIN AF27 - 68N7393 Bank 504 - PS_DDR_BG1
+#Other net PACKAGE_PIN AL31 - DDR4_CK_T Bank 504 - PS_DDR_CK0
+#Other net PACKAGE_PIN AL30 - 68N7399 Bank 504 - PS_DDR_CK1
+#Other net PACKAGE_PIN AN33 - DDR4_CKE Bank 504 - PS_DDR_CKE0
+#Other net PACKAGE_PIN AH32 - 68N7405 Bank 504 - PS_DDR_CKE1
+#Other net PACKAGE_PIN AN32 - DDR4_CK_C Bank 504 - PS_DDR_CK_N0
+#Other net PACKAGE_PIN AL32 - 68N7402 Bank 504 - PS_DDR_CK_N1
+#Other net PACKAGE_PIN AP33 - DDR4_CS_B Bank 504 - PS_DDR_CS_N0
+#Other net PACKAGE_PIN AK32 - 68N7396 Bank 504 - PS_DDR_CS_N1
+#Other net PACKAGE_PIN AN24 - DDR4_DM0 Bank 504 - PS_DDR_DM0
+#Other net PACKAGE_PIN AM29 - DDR4_DM1 Bank 504 - PS_DDR_DM1
+#Other net PACKAGE_PIN AH24 - DDR4_DM2 Bank 504 - PS_DDR_DM2
+#Other net PACKAGE_PIN AJ29 - DDR4_DM3 Bank 504 - PS_DDR_DM3
+#Other net PACKAGE_PIN AD29 - DDR4_DM4 Bank 504 - PS_DDR_DM4
+#Other net PACKAGE_PIN Y29 - DDR4_DM5 Bank 504 - PS_DDR_DM5
+#Other net PACKAGE_PIN AC32 - DDR4_DM6 Bank 504 - PS_DDR_DM6
+#Other net PACKAGE_PIN Y32 - DDR4_DM7 Bank 504 - PS_DDR_DM7
+#Other net PACKAGE_PIN AF34 - 68N7353 Bank 504 - PS_DDR_DM8
+#Other net PACKAGE_PIN AP27 - DDR4_DQ0 Bank 504 - PS_DDR_DQ0
+#Other net PACKAGE_PIN AP25 - DDR4_DQ1 Bank 504 - PS_DDR_DQ1
+#Other net PACKAGE_PIN AP29 - DDR4_DQ10 Bank 504 - PS_DDR_DQ10
+#Other net PACKAGE_PIN AP28 - DDR4_DQ11 Bank 504 - PS_DDR_DQ11
+#Other net PACKAGE_PIN AM31 - DDR4_DQ12 Bank 504 - PS_DDR_DQ12
+#Other net PACKAGE_PIN AP31 - DDR4_DQ13 Bank 504 - PS_DDR_DQ13
+#Other net PACKAGE_PIN AN31 - DDR4_DQ14 Bank 504 - PS_DDR_DQ14
+#Other net PACKAGE_PIN AM30 - DDR4_DQ15 Bank 504 - PS_DDR_DQ15
+#Other net PACKAGE_PIN AF25 - DDR4_DQ16 Bank 504 - PS_DDR_DQ16
+#Other net PACKAGE_PIN AG25 - DDR4_DQ17 Bank 504 - PS_DDR_DQ17
+#Other net PACKAGE_PIN AG26 - DDR4_DQ18 Bank 504 - PS_DDR_DQ18
+#Other net PACKAGE_PIN AJ25 - DDR4_DQ19 Bank 504 - PS_DDR_DQ19
+#Other net PACKAGE_PIN AP26 - DDR4_DQ2 Bank 504 - PS_DDR_DQ2
+#Other net PACKAGE_PIN AG24 - DDR4_DQ20 Bank 504 - PS_DDR_DQ20
+#Other net PACKAGE_PIN AK25 - DDR4_DQ21 Bank 504 - PS_DDR_DQ21
+#Other net PACKAGE_PIN AJ24 - DDR4_DQ22 Bank 504 - PS_DDR_DQ22
+#Other net PACKAGE_PIN AK24 - DDR4_DQ23 Bank 504 - PS_DDR_DQ23
+#Other net PACKAGE_PIN AH28 - DDR4_DQ24 Bank 504 - PS_DDR_DQ24
+#Other net PACKAGE_PIN AH27 - DDR4_DQ25 Bank 504 - PS_DDR_DQ25
+#Other net PACKAGE_PIN AJ27 - DDR4_DQ26 Bank 504 - PS_DDR_DQ26
+#Other net PACKAGE_PIN AK27 - DDR4_DQ27 Bank 504 - PS_DDR_DQ27
+#Other net PACKAGE_PIN AL26 - DDR4_DQ28 Bank 504 - PS_DDR_DQ28
+#Other net PACKAGE_PIN AL27 - DDR4_DQ29 Bank 504 - PS_DDR_DQ29
+#Other net PACKAGE_PIN AM26 - DDR4_DQ3 Bank 504 - PS_DDR_DQ3
+#Other net PACKAGE_PIN AH29 - DDR4_DQ30 Bank 504 - PS_DDR_DQ30
+#Other net PACKAGE_PIN AL28 - DDR4_DQ31 Bank 504 - PS_DDR_DQ31
+#Other net PACKAGE_PIN AB29 - DDR4_DQ32 Bank 504 - PS_DDR_DQ32
+#Other net PACKAGE_PIN AB30 - DDR4_DQ33 Bank 504 - PS_DDR_DQ33
+#Other net PACKAGE_PIN AC29 - DDR4_DQ34 Bank 504 - PS_DDR_DQ34
+#Other net PACKAGE_PIN AD32 - DDR4_DQ35 Bank 504 - PS_DDR_DQ35
+#Other net PACKAGE_PIN AC31 - DDR4_DQ36 Bank 504 - PS_DDR_DQ36
+#Other net PACKAGE_PIN AE30 - DDR4_DQ37 Bank 504 - PS_DDR_DQ37
+#Other net PACKAGE_PIN AC28 - DDR4_DQ38 Bank 504 - PS_DDR_DQ38
+#Other net PACKAGE_PIN AE29 - DDR4_DQ39 Bank 504 - PS_DDR_DQ39
+#Other net PACKAGE_PIN AP24 - DDR4_DQ4 Bank 504 - PS_DDR_DQ4
+#Other net PACKAGE_PIN AC27 - DDR4_DQ40 Bank 504 - PS_DDR_DQ40
+#Other net PACKAGE_PIN AA27 - DDR4_DQ41 Bank 504 - PS_DDR_DQ41
+#Other net PACKAGE_PIN AA28 - DDR4_DQ42 Bank 504 - PS_DDR_DQ42
+#Other net PACKAGE_PIN AB28 - DDR4_DQ43 Bank 504 - PS_DDR_DQ43
+#Other net PACKAGE_PIN W27 - DDR4_DQ44 Bank 504 - PS_DDR_DQ44
+#Other net PACKAGE_PIN W29 - DDR4_DQ45 Bank 504 - PS_DDR_DQ45
+#Other net PACKAGE_PIN W28 - DDR4_DQ46 Bank 504 - PS_DDR_DQ46
+#Other net PACKAGE_PIN V27 - DDR4_DQ47 Bank 504 - PS_DDR_DQ47
+#Other net PACKAGE_PIN AA32 - DDR4_DQ48 Bank 504 - PS_DDR_DQ48
+#Other net PACKAGE_PIN AA33 - DDR4_DQ49 Bank 504 - PS_DDR_DQ49
+#Other net PACKAGE_PIN AL25 - DDR4_DQ5 Bank 504 - PS_DDR_DQ5
+#Other net PACKAGE_PIN AA34 - DDR4_DQ50 Bank 504 - PS_DDR_DQ50
+#Other net PACKAGE_PIN AE34 - DDR4_DQ51 Bank 504 - PS_DDR_DQ51
+#Other net PACKAGE_PIN AD34 - DDR4_DQ52 Bank 504 - PS_DDR_DQ52
+#Other net PACKAGE_PIN AB31 - DDR4_DQ53 Bank 504 - PS_DDR_DQ53
+#Other net PACKAGE_PIN AC34 - DDR4_DQ54 Bank 504 - PS_DDR_DQ54
+#Other net PACKAGE_PIN AC33 - DDR4_DQ55 Bank 504 - PS_DDR_DQ55
+#Other net PACKAGE_PIN AA30 - DDR4_DQ56 Bank 504 - PS_DDR_DQ56
+#Other net PACKAGE_PIN Y30 - DDR4_DQ57 Bank 504 - PS_DDR_DQ57
+#Other net PACKAGE_PIN AA31 - DDR4_DQ58 Bank 504 - PS_DDR_DQ58
+#Other net PACKAGE_PIN W30 - DDR4_DQ59 Bank 504 - PS_DDR_DQ59
+#Other net PACKAGE_PIN AM25 - DDR4_DQ6 Bank 504 - PS_DDR_DQ6
+#Other net PACKAGE_PIN Y33 - DDR4_DQ60 Bank 504 - PS_DDR_DQ60
+#Other net PACKAGE_PIN W33 - DDR4_DQ61 Bank 504 - PS_DDR_DQ61
+#Other net PACKAGE_PIN W34 - DDR4_DQ62 Bank 504 - PS_DDR_DQ62
+#Other net PACKAGE_PIN Y34 - DDR4_DQ63 Bank 504 - PS_DDR_DQ63
+#Other net PACKAGE_PIN AF32 - 68N7356 Bank 504 - PS_DDR_DQ64
+#Other net PACKAGE_PIN AE32 - 68N7359 Bank 504 - PS_DDR_DQ65
+#Other net PACKAGE_PIN AH33 - 68N7362 Bank 504 - PS_DDR_DQ66
+#Other net PACKAGE_PIN AE33 - 68N7364 Bank 504 - PS_DDR_DQ67
+#Other net PACKAGE_PIN AF33 - 68N7368 Bank 504 - PS_DDR_DQ68
+#Other net PACKAGE_PIN AH34 - 68N7370 Bank 504 - PS_DDR_DQ69
+#Other net PACKAGE_PIN AM24 - DDR4_DQ7 Bank 504 - PS_DDR_DQ7
+#Other net PACKAGE_PIN AJ34 - 68N7374 Bank 504 - PS_DDR_DQ70
+#Other net PACKAGE_PIN AK34 - 68N7376 Bank 504 - PS_DDR_DQ71
+#Other net PACKAGE_PIN AM28 - DDR4_DQ8 Bank 504 - PS_DDR_DQ8
+#Other net PACKAGE_PIN AN28 - DDR4_DQ9 Bank 504 - PS_DDR_DQ9
+#Other net PACKAGE_PIN AN27 - DDR4_DQS0_C Bank 504 - PS_DDR_DQS_N0
+#Other net PACKAGE_PIN AP30 - DDR4_DQS1_C Bank 504 - PS_DDR_DQS_N1
+#Other net PACKAGE_PIN AJ26 - DDR4_DQS2_C Bank 504 - PS_DDR_DQS_N2
+#Other net PACKAGE_PIN AK29 - DDR4_DQS3_C Bank 504 - PS_DDR_DQS_N3
+#Other net PACKAGE_PIN AD31 - DDR4_DQS4_C Bank 504 - PS_DDR_DQS_N4
+#Other net PACKAGE_PIN Y28 - DDR4_DQS5_C Bank 504 - PS_DDR_DQS_N5
+#Other net PACKAGE_PIN AB34 - DDR4_DQS6_C Bank 504 - PS_DDR_DQS_N6
+#Other net PACKAGE_PIN W32 - DDR4_DQS7_C Bank 504 - PS_DDR_DQS_N7
+#Other net PACKAGE_PIN AG34 - 68N7350 Bank 504 - PS_DDR_DQS_N8
+#Other net PACKAGE_PIN AN26 - DDR4_DQS0_T Bank 504 - PS_DDR_DQS_P0
+#Other net PACKAGE_PIN AN29 - DDR4_DQS1_T Bank 504 - PS_DDR_DQS_P1
+#Other net PACKAGE_PIN AH26 - DDR4_DQS2_T Bank 504 - PS_DDR_DQS_P2
+#Other net PACKAGE_PIN AK28 - DDR4_DQS3_T Bank 504 - PS_DDR_DQS_P3
+#Other net PACKAGE_PIN AD30 - DDR4_DQS4_T Bank 504 - PS_DDR_DQS_P4
+#Other net PACKAGE_PIN Y27 - DDR4_DQS5_T Bank 504 - PS_DDR_DQS_P5
+#Other net PACKAGE_PIN AB33 - DDR4_DQS6_T Bank 504 - PS_DDR_DQS_P6
+#Other net PACKAGE_PIN W31 - DDR4_DQS7_T Bank 504 - PS_DDR_DQS_P7
+#Other net PACKAGE_PIN AG33 - 68N7347 Bank 504 - PS_DDR_DQS_P8
+#Other net PACKAGE_PIN AP32 - DDR4_ODT Bank 504 - PS_DDR_ODT0
+#Other net PACKAGE_PIN AJ32 - 68N7408 Bank 504 - PS_DDR_ODT1
+#Other net PACKAGE_PIN AA26 - DDR4_PAR Bank 504 - PS_DDR_PARITY
+#Other net PACKAGE_PIN AD26 - DDR4_RESET_B Bank 504 - PS_DDR_RAM_RST_N
+#Other net PACKAGE_PIN AC26 - SODIMM_ZQ Bank 504 - PS_DDR_ZQ
+#Other net PACKAGE_PIN U34 - 69N6524 Bank 505 - PS_MGTRRXN0_505
+#Other net PACKAGE_PIN T32 - 69N6530 Bank 505 - PS_MGTRRXN1_505
+#Other net PACKAGE_PIN R34 - GT2_USB0_RX_N Bank 505 - PS_MGTRRXN2_505
+#Other net PACKAGE_PIN N34 - GT3_SATA1_RX_N Bank 505 - PS_MGTRRXN3_505
+#Other net PACKAGE_PIN U33 - 69N6521 Bank 505 - PS_MGTRRXP0_505
+#Other net PACKAGE_PIN T31 - 69N6527 Bank 505 - PS_MGTRRXP1_505
+#Other net PACKAGE_PIN R33 - GT2_USB0_RX_P Bank 505 - PS_MGTRRXP2_505
+#Other net PACKAGE_PIN N33 - GT3_SATA1_RX_P Bank 505 - PS_MGTRRXP3_505
+#Other net PACKAGE_PIN U30 - GT0_DP_TX_N Bank 505 - PS_MGTRTXN0_505
+#Other net PACKAGE_PIN R30 - GT1_DP_TX_N Bank 505 - PS_MGTRTXN1_505
+#Other net PACKAGE_PIN P32 - GT2_USB0_TX_N Bank 505 - PS_MGTRTXN2_505
+#Other net PACKAGE_PIN N30 - GT3_SATA1_TX_N Bank 505 - PS_MGTRTXN3_505
+#Other net PACKAGE_PIN U29 - GT0_DP_TX_P Bank 505 - PS_MGTRTXP0_505
+#Other net PACKAGE_PIN R29 - GT1_DP_TX_P Bank 505 - PS_MGTRTXP1_505
+#Other net PACKAGE_PIN P31 - GT2_USB0_TX_P Bank 505 - PS_MGTRTXP2_505
+#Other net PACKAGE_PIN N29 - GT3_SATA1_TX_P Bank 505 - PS_MGTRTXP3_505
+#Other net PACKAGE_PIN T28 - 69N6536 Bank 505 - PS_MGTREFCLK0N_505
+#Other net PACKAGE_PIN T27 - 69N6533 Bank 505 - PS_MGTREFCLK0P_505
+#Other net PACKAGE_PIN P28 - GTR_REF_CLK_SATA_C_N Bank 505 - PS_MGTREFCLK1N_505
+#Other net PACKAGE_PIN P27 - GTR_REF_CLK_SATA_C_P Bank 505 - PS_MGTREFCLK1P_505
+#Other net PACKAGE_PIN M28 - GTR_REF_CLK_USB3_C_N Bank 505 - PS_MGTREFCLK2N_505
+#Other net PACKAGE_PIN M27 - GTR_REF_CLK_USB3_C_P Bank 505 - PS_MGTREFCLK2P_505
+#Other net PACKAGE_PIN M32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505
+#Other net PACKAGE_PIN M31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505
+#Other net PACKAGE_PIN U31 - 69N5804 Bank 505 - PS_MGTRREF_505
+#Other net PACKAGE_PIN AE16 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AH15 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AJ18 - VCC1V2 Bank 64 - VCCO_64
+#Other net PACKAGE_PIN AF19 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AG22 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AK21 - VCC1V2 Bank 65 - VCCO_65
+#Other net PACKAGE_PIN AF9 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN AG12 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN AK11 - VCC1V2 Bank 66 - VCCO_66
+#Other net PACKAGE_PIN E21 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN F24 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN H20 - VCC1V8 Bank 28 - VCCO_28
+#Other net PACKAGE_PIN D13 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN E16 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN H15 - VADJ_FMC Bank 67 - VCCO_67
+#Other net PACKAGE_PIN F9 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN G12 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN K11 - VADJ_FMC Bank 68 - VCCO_68
+#Other net PACKAGE_PIN J8 - VCC3V3 Bank 87 - VCCO_87
+#Other net PACKAGE_PIN N10 - VCC3V3 Bank 87 - VCCO_87
+#Other net PACKAGE_PIN D3 - VCC3V3 Bank 88 - VCCO_88
+#Other net PACKAGE_PIN E6 - VCC3V3 Bank 88 - VCCO_88
+#Other net PACKAGE_PIN C25 - VCC1V8 Bank 500 - VCCO_PSIO0_500
+#Other net PACKAGE_PIN D28 - VCC1V8 Bank 500 - VCCO_PSIO0_500
+#Other net PACKAGE_PIN B32 - VCC1V8 Bank 501 - VCCO_PSIO1_501
+#Other net PACKAGE_PIN E31 - VCC1V8 Bank 501 - VCCO_PSIO1_501
+#Other net PACKAGE_PIN H30 - VCC1V8 Bank 502 - VCCO_PSIO2_502
+#Other net PACKAGE_PIN J33 - VCC1V8 Bank 502 - VCCO_PSIO2_502
+#Other net PACKAGE_PIN G27 - VCC1V8 Bank 503 - VCCO_PSIO3_503
+#Other net PACKAGE_PIN N25 - VCC1V8 Bank 503 - VCCO_PSIO3_503
+#Other net PACKAGE_PIN AE26 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AE31 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AG27 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AG32 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AJ28 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AJ33 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN AL29 - VCC1V2 Bank 504 - VCCO_PSDDR_504
+#Other net PACKAGE_PIN A1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN A34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN A4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AB9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AC7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AD5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AE9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AF7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AG7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AH7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AJ8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AK7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AL9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AM7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AN7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AP7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN B7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN C5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN D8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN E11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN E26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN F3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN G5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H25 - GND Bank 999 - GND
+#Other net PACKAGE_PIN H5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN J5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K6 - GND Bank 999 - GND
+#Other net PACKAGE_PIN K7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN L9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN M7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN N7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P10 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P22 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P8 - GND Bank 999 - GND
+#Other net PACKAGE_PIN P9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN R7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN T9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U21 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U24 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U27 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN U7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V28 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V29 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V30 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V32 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V33 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V34 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN V9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W13 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W15 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W17 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W19 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W23 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W3 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W4 - GND Bank 999 - GND
+#Other net PACKAGE_PIN W7 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y1 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y11 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y12 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y14 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y16 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y18 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y2 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y20 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y26 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y31 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y5 - GND Bank 999 - GND
+#Other net PACKAGE_PIN Y9 - GND Bank 999 - GND
+#Other net PACKAGE_PIN AA8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AB10 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AC8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN R8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN T10 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN U8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN W8 - MGTAVCC Bank 999 - MGTAVCC_R
+#Other net PACKAGE_PIN AB6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AD6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AF6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AH6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AK6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AM6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN AP6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN M6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN P6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN T6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN V6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN Y6 - MGT1V2 Bank 999 - MGTAVTT_R
+#Other net PACKAGE_PIN V10 - MGT1V8 Bank 999 - MGTVCCAUX_R
+#Other net PACKAGE_PIN Y10 - MGT1V8 Bank 999 - MGTVCCAUX_R
+#Other net PACKAGE_PIN N27 - MGTRAVCC Bank 999 - PS_MGTRAVCC
+#Other net PACKAGE_PIN R27 - MGTRAVCC Bank 999 - PS_MGTRAVCC
+#Other net PACKAGE_PIN N31 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN P29 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN T29 - MGT1V8 Bank 999 - PS_MGTRAVTT
+#Other net PACKAGE_PIN P23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN R23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN U23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN V23 - VCC1V8 Bank 999 - VCCAUX
+#Other net PACKAGE_PIN N22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN R22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN T22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN U22 - VCC1V8 Bank 999 - VCCAUX_IO
+#Other net PACKAGE_PIN R12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN T12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN V12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN W12 - VCCINT Bank 999 - VCCBRAM
+#Other net PACKAGE_PIN M15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN M21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N18 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN N20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN R20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN T21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN U20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN V21 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W14 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W16 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W18 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN W20 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y15 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y17 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN Y19 - VCCINT Bank 999 - VCCINT
+#Other net PACKAGE_PIN P13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN T13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN U13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN V13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN Y13 - VCCINT Bank 999 - VCCINT_IO
+#Other net PACKAGE_PIN V26 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN W25 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN W26 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN Y25 - VCC1V8 Bank 999 - VCC_PSAUX
+#Other net PACKAGE_PIN Y23 - VCC_PSBATT Bank 999 - VCC_PSBATT
+#Other net PACKAGE_PIN U25 - VCCPSDDRPLL Bank 999 - VCC_PSDDR_PLL
+#Other net PACKAGE_PIN V25 - VCCPSDDRPLL Bank 999 - VCC_PSDDR_PLL
+#Other net PACKAGE_PIN AA23 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB21 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB22 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB23 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB24 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AC21 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AC22 - VCCINT Bank 999 - VCC_PSINTFP
+#Other net PACKAGE_PIN AB25 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AC24 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AC25 - VCCINT Bank 999 - VCC_PSINTFP_DDR
+#Other net PACKAGE_PIN AA22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN V22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN W21 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN W22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN Y21 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN Y22 - VCCINT Bank 999 - VCC_PSINTLP
+#Other net PACKAGE_PIN V24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN W24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN Y24 - MGT1V2 Bank 999 - VCC_PSPLL
+#Other net PACKAGE_PIN AD21 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD22 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD23 - VCCINT_VCU Bank 999 - VCCINT_VCU
+#Other net PACKAGE_PIN AD24 - VCCINT_VCU Bank 999 - VCCINT_VCU
+
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_0]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_1]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_2]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_3]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_4]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_5]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_6]
+set_property IOSTANDARD LVCMOS33 [get_ports PMOD0_7]
+set_property PACKAGE_PIN G8 [get_ports PMOD0_0]
+set_property PACKAGE_PIN H8 [get_ports PMOD0_1]
+set_property PACKAGE_PIN G7 [get_ports PMOD0_2]
+set_property PACKAGE_PIN H7 [get_ports PMOD0_3]
+set_property PACKAGE_PIN G6 [get_ports PMOD0_4]
+set_property PACKAGE_PIN H6 [get_ports PMOD0_5]
+set_property PACKAGE_PIN J6 [get_ports PMOD0_6]
+set_property PACKAGE_PIN J7 [get_ports PMOD0_7]
+set_property PULLUP true [get_ports PMOD0_2]
+set_property PULLDOWN true [get_ports PMOD0_3]
+set_property PULLUP true [get_ports PMOD0_4]
+set_property PULLUP true [get_ports PMOD0_5]
+set_property PULLUP true [get_ports PMOD0_6]
+set_property PULLUP true [get_ports PMOD0_7]
+
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets PMOD0_7_IBUF_inst/O]
+
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_0]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_1]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_2]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_3]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_4]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_5]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_6]
+#set_property IOSTANDARD LVCMOS33 [get_ports PMOD1_7]
+#set_property PACKAGE_PIN J9 [get_ports PMOD1_0]
+#set_property PACKAGE_PIN K9 [get_ports PMOD1_1]
+#set_property PACKAGE_PIN K8 [get_ports PMOD1_2]
+#set_property PACKAGE_PIN L8 [get_ports PMOD1_3]
+#set_property PACKAGE_PIN L10 [get_ports PMOD1_4]
+#set_property PACKAGE_PIN M10 [get_ports PMOD1_5]
+#set_property PACKAGE_PIN M8 [get_ports PMOD1_6]
+#set_property PACKAGE_PIN M9 [get_ports PMOD1_7]
+
+#set_property PULLUP true [get_ports PMOD1_7]
+#set_property PULLUP true [get_ports PMOD1_6]
+#set_property PULLUP true [get_ports PMOD1_5]
+#set_property PULLUP true [get_ports PMOD1_4]
+#set_property PULLUP true [get_ports PMOD1_3]
+#set_property PULLUP true [get_ports PMOD1_2]
+#set_property PULLUP true [get_ports PMOD1_1]
+#set_property PULLUP true [get_ports PMOD1_0]
+
+
+#PMODA pin0 to FTCLK
+#set_property PACKAGE_PIN K9 [get_ports {P1[1]}]
+
+#PMODA pin1 to FTSSN
+#set_property PACKAGE_PIN L8 [get_ports {P1[3]}]
+
+#PMODA pin2 to FTMISO
+#set_property PACKAGE_PIN J9 [get_ports {P1[0]}]
+
+#PMODA pin3 to FTMIOSIO
+#set_property PACKAGE_PIN K8 [get_ports {P1[2]}]
+
+#PMODB pin1 to SWDIOTMS
+#set_property PACKAGE_PIN G8 [get_ports SWDIOTMS]
+
+#PMODB pin4 to SWCLKTCK
+#set_property PACKAGE_PIN H7 [get_ports SWCLKTCK]
+#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets uPAD_SWDCLK_I/IOBUF3V3/O]
+
+#PMODA pin4 : UART2RXD
+#PMODA pin4 : UART2TXD
+
+
+# LED0 to P0[0]
+#set_property PACKAGE_PIN D5 [get_ports {P0[0]}]
+# LED1 to P0[1]
+#set_property PACKAGE_PIN D6 [get_ports {P0[1]}]
+# LED2 to P0[2]
+#set_property PACKAGE_PIN A5 [get_ports {P0[2]}]
+# LED3 to P0[3]
+#set_property PACKAGE_PIN B5 [get_ports {P0[3]}]
+
+# SW0 to NRST (Down for active low)
+#set_property PACKAGE_PIN B4 [get_ports NRST]
+
+# CLK125MHz (need dvider)
+#set_property IOSTANDARD LVCMOS18 [get_ports XTAL1 ]
+#set_property PACKAGE_PIN F23 [get_ports XTAL1]
+
+
+## auto mapped - to remap
+#set_property PACKAGE_PIN C4 [get_ports {P0[10]}]
+#set_property PACKAGE_PIN C3 [get_ports {P0[11]}]
+#set_property PACKAGE_PIN B3 [get_ports {P0[12]}]
+#set_property PACKAGE_PIN D2 [get_ports {P0[13]}]
+#set_property PACKAGE_PIN C2 [get_ports {P0[14]}]
+#set_property PACKAGE_PIN E3 [get_ports {P0[15]}]
+#set_property PACKAGE_PIN F6 [get_ports {P0[4]}]
+#set_property PACKAGE_PIN E5 [get_ports {P0[5]}]
+#set_property PACKAGE_PIN F5 [get_ports {P0[6]}]
+#set_property PACKAGE_PIN F4 [get_ports {P0[7]}]
+#set_property PACKAGE_PIN E4 [get_ports {P0[8]}]
+#set_property PACKAGE_PIN D4 [get_ports {P0[9]}]
+#set_property PACKAGE_PIN M10 [get_ports {P1[10]}]
+#set_property PACKAGE_PIN L10 [get_ports {P1[11]}]
+#set_property PACKAGE_PIN M9 [get_ports {P1[12]}]
+#set_property PACKAGE_PIN M8 [get_ports {P1[13]}]
+#set_property PACKAGE_PIN N11 [get_ports {P1[14]}]
+#set_property PACKAGE_PIN M11 [get_ports {P1[15]}]
+#set_property PACKAGE_PIN H8 [get_ports {P1[4]}]
+#set_property PACKAGE_PIN G7 [get_ports {P1[5]}]
+#set_property PACKAGE_PIN H6 [get_ports {P1[6]}]
+#set_property PACKAGE_PIN G6 [get_ports {P1[7]}]
+#set_property PACKAGE_PIN J7 [get_ports {P1[8]}]
+#set_property PACKAGE_PIN J6 [get_ports {P1[9]}]
+#set_property PACKAGE_PIN E2 [get_ports VDD]
+#set_property PACKAGE_PIN A3 [get_ports VDDIO]
+#set_property PACKAGE_PIN A2 [get_ports VSS]
+#set_property PACKAGE_PIN C1 [get_ports VSSIO]
+#set_property PACKAGE_PIN B1 [get_ports XTAL2]
diff --git a/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_synth.tcl b/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_synth.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7e6b0c29e7c2584df999ce9a0bc5b3cb502f4185
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_synth.tcl
@@ -0,0 +1 @@
+synth_design -top nanosoc_chip -part xczu7ev-ffvc1156-2-e
diff --git a/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_timing.xdc b/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_timing.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..fe6eb50301a0e98b47f0d17b9ca18580479e66f7
--- /dev/null
+++ b/implement/fpga/xilinx_vivado/target_fpga_zcu104/fpga_timing.xdc
@@ -0,0 +1,95 @@
+##################################################################################
+## ##
+## ZYNQ timing XDC ##
+## ##
+##################################################################################
+
+create_clock -name CLK -period 30 [get_ports xtal_clk_i]
+create_clock -name VCLK -period 30 -waveform {5 20}
+
+create_clock -name SWCLK -period 60 [get_ports swdclk_i]
+create_clock -name VSWCLK -period 60 -waveform {5 35}
+
+set_clock_groups -name async_clk_swclock -asynchronous \
+-group [get_clocks -include_generated_clocks CLK] \
+-group [get_clocks -include_generated_clocks VSWCLK]
+
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
+#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
+#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
+#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
+#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p0_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p0_o[15]}]
+
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[0]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[1]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[2]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[3]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[4]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[5]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[6]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[7]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[8]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[9]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[10]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[11]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[12]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[13]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[14]}]
+set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {p1_o[15]}]
+set_output_delay -clock [get_clocks CLK] -max -add_delay 18.000 [get_ports {p1_o[15]}]
+
+#set_property C_CLK_INPUT_FREQ_HZ 5000000 [get_debug_cores dbg_hub]
+#set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
+#set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
+#connect_debug_port dbg_hub/clk [get_nets clk]
diff --git a/set_env.sh b/set_env.sh
index 8304f5c4cd0707b5b64d8035f3736a7f86bcf08a..7e0a00a861f1b062412c9e201efb6f7e5a19ad4a 100755
--- a/set_env.sh
+++ b/set_env.sh
@@ -35,6 +35,8 @@ else
# Add in location for socsim scripts
export SOCLABS_SOCSIM_PATH=$SOCLABS_PROJECT_DIR/simulate/socsim
+ # Add in location for socsim scripts
+ export SOCLABS_FPGA_IMP_PATH=$SOCLABS_PROJECT_DIR/implement/fpga/xilinx_vivado
# Source dependency environment variable script
source $SOCLABS_PROJECT_DIR/env/dependency_env.sh
@@ -69,4 +71,4 @@ if [ ! -f $SOCLABS_PROJECT_DIR/.socinit ]; then
git config --file .gitmodules --get-regexp path | awk '{ print $2 }' | while read line; do cd $SOCLABS_PROJECT_DIR/$line && git checkout `grep $line $SOCLABS_PROJECT_DIR/proj-branch | awk '{ print $2 }'` && git pull; done
git restore $SOCLABS_DESIGN_ROOT/.gitmodules
touch $SOCLABS_PROJECT_DIR/.socinit
-fi
\ No newline at end of file
+fi