These are trivial modules, but add convenience when wiring up
the processor.

This will be directly implemented in CanCore instead.

- add a companion object for less verbose cw decl
- add a read port for pm
- test improvements
- naming improvements

A redesign is also performed.

This allows switching between Mem (usually synthesized into
register groups) and SyncReadMem (usually synthesized into FPGA
block memories).

LFSR PRNGs cannot be properly implemented

It turns out that a older version is mistakenly used.

This gives a 'Error: chiselplugin takes no options', which should
not happen at all.