Particularly: firrtl_black_box_resource_files.f

This may be used to interrupt an external controller.

There is now only a 'halt' signal that stops the processor.

Now Read-After-Write gives old data (Read-First). Quartus does not
give warnings. No bypass logic is implemented.

Two simultaneous read causes Quartus to synthesize additional BRAM
and is unnecessary. This commit attempts to make Quartus to infer
a Simple Dual-Port RAM.

Plus a take pin exposed from CanCore, which can be used to take
control on both of the memories.

This version of core uses a more RISC-like architecture.

- a register file is added
- unused configs and signals are removed
- various changes

This reverts 585b1228.

... as a preparation of architecture refactor.

Architectural change: the flattened columnar round and diagonal
round are now stacked and controlled by a signal, which means only
one can be activated now.

An addition is trivially synthesized to a ripple-carry adder. With
512b + 512b the carry chain is super long and delay becomes super
high. Although the results are same, now just use 16 32b ripple-
carry adders, which is also what the standards specify. Later a
faster adder may be considered.

This commit includes a lot of damages:

- change to a more structural pkg hierarchy: config, core, types
- refactor some modules to use a more OOP paradigm
- further integrate implicit cfg to modules
- add imm width to config
- change all modules to accept UInt, which makes all data paths in
  core UInt(512.W)
- temporary remove all test cases because of the changes above;
  they need to be rewritten
- maybe more

The top level should pass all parameter down.

This is a more Scala-ish and Chisel-ish style for configuring the
core.

Boring change lol

This is the processor without any peripheral.

These are trivial modules, but add convenience when wiring up
the processor.