- 11 Jul, 2021 2 commits
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Minyong Li authored
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Minyong Li authored
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- 08 Jul, 2021 1 commit
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Minyong Li authored
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- 06 Jul, 2021 1 commit
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Minyong Li authored
This commit includes a lot of damages: - change to a more structural pkg hierarchy: config, core, types - refactor some modules to use a more OOP paradigm - further integrate implicit cfg to modules - add imm width to config - change all modules to accept UInt, which makes all data paths in core UInt(512.W) - temporary remove all test cases because of the changes above; they need to be rewritten - maybe more
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- 05 Jul, 2021 1 commit
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Minyong Li authored
The top level should pass all parameter down.
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- 25 Jun, 2021 1 commit
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Minyong Li authored
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- 24 Jun, 2021 2 commits
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Minyong Li authored
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Minyong Li authored
This allows switching between Mem (usually synthesized into register groups) and SyncReadMem (usually synthesized into FPGA block memories).
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- 17 Jun, 2021 1 commit
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Minyong Li authored
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- 13 Jun, 2021 2 commits
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Minyong Li authored
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Minyong Li authored
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