From f21b78bc3631a127a35946ab3c9a12062f0c30dd Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Mon, 5 Jul 2021 20:56:52 +0100
Subject: [PATCH] core.CanCore: use Chisel3 log2Ceil instead
---
src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala b/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala
index 4b78448..2ea297c 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/CanCore.scala
@@ -4,19 +4,15 @@
package uk.ac.soton.ecs.can.core
import chisel3._
-import scala.math.{ceil, log}
+import chisel3.util.log2Ceil
class CanCore(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
// ========== Calculated Parameters ========== //
- private val programMemoryAddressWidth = ceil(
- log(cfg.programMemoryWords) / log(2)
- ).toInt
+ private val programMemoryAddressWidth = log2Ceil(cfg.programMemoryWords)
private val controlWordWidth = ControlWord(programMemoryAddressWidth).getWidth
- private val dataMemoryAddressWidth = ceil(
- log(cfg.dataMemoryWords) / log(2)
- ).toInt
+ private val dataMemoryAddressWidth = log2Ceil(cfg.dataMemoryWords)
private val blockWidth = 512
// ========== External I/O Ports ========== //
--
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