From 9e63e4d7d66118d53f7565ae37aac451334a6d09 Mon Sep 17 00:00:00 2001 From: Minyong Li <ml10g20@soton.ac.uk> Date: Mon, 23 Aug 2021 22:59:23 +0100 Subject: [PATCH] firmware/test: add program and data for demo --- firmware/test/test.data.hex | 10 ++++++++ firmware/test/test.prog.hex | 51 +++++++++++++++++++++++++++++++++++++ 2 files changed, 61 insertions(+) create mode 100644 firmware/test/test.data.hex create mode 100644 firmware/test/test.prog.hex diff --git a/firmware/test/test.data.hex b/firmware/test/test.data.hex new file mode 100644 index 0000000..301174e --- /dev/null +++ b/firmware/test/test.data.hex @@ -0,0 +1,10 @@ +// Data for demonstration +// +// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk> +// SPDX-License-Identifier: CC0-1.0 + +// Block 0 (initial state, constant to be filled) +0 + +// Block 1 (plain text) +0 diff --git a/firmware/test/test.prog.hex b/firmware/test/test.prog.hex new file mode 100644 index 0000000..7da0154 --- /dev/null +++ b/firmware/test/test.prog.hex @@ -0,0 +1,51 @@ +// A simple Control Word (CW) program running the ChaCha20 block function for +// demonstration +// +// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk> +// SPDX-License-Identifier: GPL-3.0-or-later + +// Can Architecture Variant: Mem(Sync-P128-D16)-Reg(2) +// -> PM ADDR W 7b - DM ADDR W 4b +// +// /- rwf +// /- dmwe | /- rwe +// /- hlt | /- dmwa | | /- rwa +// 0_0000_0_0000_0_0_0_0_0_0_0_000 +// \- dmra | \- r1ra | | \- aluf +// \- r0ra | \- incblkcnt +// \- flcnst +// +// 0000_0000_0000_0000_0000 (20.W) +// 0_0000_0_0000_0_0_0_0_0_0_0_000 // + + // | | | | | +00000 // 0_0000_0_0000_0_0_0_0_0_0_0_000 // %0 <- #0 +000c0 // 0_0000_0_0000_0_0_1_1_0_0_0_000 // %0 <- #0 // Delayed load +00051 // 0_0000_0_0000_0_0_0_1_0_1_0_001 // %0 <- ! %0 +00066 // 0_0000_0_0000_0_0_0_1_1_0_0_110 // %1 <- %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +00042 // 0_0000_0_0000_0_0_0_1_0_0_0_010 // %0 <- | %0 +00043 // 0_0000_0_0000_0_0_0_1_0_0_0_011 // %0 <- \ %0 +08144 // 0_0000_0_0000_0_1_0_1_0_0_0_100 // %0 <- %0 + %1 +08000 // 0_0001_0_0000_0_0_0_0_0_0_0_000 // %1 <- #1 +080e0 // 0_0001_0_0000_0_0_1_1_1_0_0_000 // %1 <- #1 // Delayed load +04505 // 0_0000_0_0000_0_1_0_1_1_0_0_101 // %1 <- %0 ^ %1 +04507 // 0_0000_1_0001_0_1_0_0_0_0_0_111 // #1 <- %1 +80000 // 1_0000_0_0000_0_0_0_0_0_0_0_000 // Halt -- GitLab