From 6b278e2cca79287cd15fd675bd593cdc20bd7ed2 Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Thu, 8 Jul 2021 14:10:32 +0100
Subject: [PATCH] core.DataMemory: change ports from 2r1w to 1r1w
---
.../uk/ac/soton/ecs/can/core/DataMemory.scala | 15 +++++----------
1 file changed, 5 insertions(+), 10 deletions(-)
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index cd5cade..7b89b67 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -10,15 +10,10 @@ import uk.ac.soton.ecs.can.config.CanCoreConfiguration
class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
private val addrWidth = log2Ceil(cfg.dataMemoryWords)
- val read = IO(
- Vec(
- 2,
- new Bundle {
- val addr = Input(UInt(addrWidth.W))
- val data = Output(UInt(512.W))
- }
- )
- )
+ val read = IO(new Bundle {
+ val addr = Input(UInt(addrWidth.W))
+ val data = Output(UInt(512.W))
+ })
val write = IO(new Bundle {
val en = Input(Bool())
val addr = Input(UInt(addrWidth.W))
@@ -31,7 +26,7 @@ class DataMemory(implicit cfg: CanCoreConfiguration) extends MultiIOModule {
else
Mem(cfg.dataMemoryWords, UInt(512.W))
- read.foreach(p => p.data := mem(p.addr))
+ read.data := mem(read.addr)
when(write.en) {
mem(write.addr) := write.data
--
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