diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
index 8d726db7e810b0b5c37140cd099af4caf3adb8b2..a1ec5b6328b906ae422c8d8533c4be855282a47d 100644
--- a/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/DataMemory.scala
@@ -11,10 +11,15 @@ class DataMemory(
     size: Int,
     syncMem: Boolean = true
 ) extends MultiIOModule {
-  val read = IO(new Bundle {
-    val addr = Input(UInt(addrWidth.W))
-    val data = Output(UInt(dataWidth.W))
-  })
+  val read = IO(
+    Vec(
+      2,
+      new Bundle {
+        val addr = Input(UInt(addrWidth.W))
+        val data = Output(UInt(dataWidth.W))
+      }
+    )
+  )
   val write = IO(new Bundle {
     val en = Input(Bool())
     val addr = Input(UInt(addrWidth.W))
@@ -25,7 +30,7 @@ class DataMemory(
     if (syncMem) SyncReadMem(size, UInt(dataWidth.W))
     else Mem(size, UInt(dataWidth.W))
 
-  read.data := mem(read.addr)
+  read.foreach(p => p.data := mem(p.addr))
 
   when(write.en) {
     mem(write.addr) := write.data
diff --git a/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala b/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala
index 936cff057e510b893c4d7aaa00549c31ac4476b8..e7200b089bc2add699636ae6f6d154378b84fefe 100644
--- a/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala
+++ b/src/test/scala/uk/ac/soton/ecs/can/core/DataMemoryTest.scala
@@ -21,18 +21,18 @@ class DataMemoryTest extends FlatSpec with ChiselScalatestTester {
       c.write.en.poke(true.B)
       c.clock.step()
       c.write.en.poke(false.B)
-      c.read.addr.poke("h01".U(addrWidth.W))
+      c.read.foreach(_.addr.poke("h01".U(addrWidth.W)))
       c.clock.step()
-      c.read.data.expect("h1234".U(dataWidth.W))
+      c.read.foreach(_.data.expect("h1234".U(dataWidth.W)))
 
       c.write.addr.poke("h0a".U(addrWidth.W))
       c.write.data.poke("hfefe".U(dataWidth.W))
       c.write.en.poke(true.B)
       c.clock.step()
       c.write.en.poke(false.B)
-      c.read.addr.poke("h0a".U(addrWidth.W))
+      c.read.foreach(_.addr.poke("h0a".U(addrWidth.W)))
       c.clock.step()
-      c.read.data.expect("hfefe".U(dataWidth.W))
+      c.read.foreach(_.data.expect("hfefe".U(dataWidth.W)))
     }
   }
 
@@ -43,13 +43,13 @@ class DataMemoryTest extends FlatSpec with ChiselScalatestTester {
       c.write.en.poke(true.B)
       c.clock.step()
       c.write.en.poke(false.B)
-      c.read.addr.poke("h06".U(addrWidth.W))
+      c.read.foreach(_.addr.poke("h06".U(addrWidth.W)))
       c.clock.step()
-      c.read.data.expect("hcafe".U(dataWidth.W))
+      c.read.foreach(_.data.expect("hcafe".U(dataWidth.W)))
 
       c.write.data.poke("hefac".U(dataWidth.W))
       c.clock.step()
-      c.read.data.expect("hcafe".U(dataWidth.W))
+      c.read.foreach(_.data.expect("hcafe".U(dataWidth.W)))
     }
   }
 }