From 0cf08793af595ef9fb219908742ba4e28c3bad5f Mon Sep 17 00:00:00 2001
From: Minyong Li <ml10g20@soton.ac.uk>
Date: Wed, 7 Jul 2021 11:00:38 +0100
Subject: [PATCH] core.TwoStageQuarterRound: add
---
.../ecs/can/core/TwoStageQuarterRound.scala | 34 +++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 src/main/scala/uk/ac/soton/ecs/can/core/TwoStageQuarterRound.scala
diff --git a/src/main/scala/uk/ac/soton/ecs/can/core/TwoStageQuarterRound.scala b/src/main/scala/uk/ac/soton/ecs/can/core/TwoStageQuarterRound.scala
new file mode 100644
index 0000000..d6ec7fd
--- /dev/null
+++ b/src/main/scala/uk/ac/soton/ecs/can/core/TwoStageQuarterRound.scala
@@ -0,0 +1,34 @@
+// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
+// SPDX-License-Identifier: CERN-OHL-W-2.0
+
+package uk.ac.soton.ecs.can.core
+
+import chisel3._
+
+class TwoStageQuarterRound extends BaseQuarterRound {
+ private val a0 = in(0)
+ private val b0 = in(1)
+ private val c0 = in(2)
+ private val d0 = in(3)
+
+ private val a1 = a0 + b0
+ private val d1 = rotateLeft(d0 ^ a1, 16)
+ private val c1 = c0 + d1
+ private val b1 = rotateLeft(b0 ^ c1, 12)
+
+ private val reg = Reg(Vec(4, UInt(32.W)))
+ reg(0) := a1
+ reg(1) := b1
+ reg(2) := c1
+ reg(3) := d1
+
+ private val a2 = reg(0) + reg(1)
+ private val d2 = rotateLeft(reg(3) ^ a2, 8)
+ private val c2 = reg(2) + d2
+ private val b2 = rotateLeft(reg(1) ^ c2, 7)
+
+ out(0) := a2
+ out(1) := b2
+ out(2) := c2
+ out(3) := d2
+}
--
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