ProgramMemory.scala 1.1 KB
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// SPDX-FileCopyrightText: 2021 Minyong Li <ml10g20@soton.ac.uk>
// SPDX-License-Identifier: CERN-OHL-W-2.0

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package uk.ac.soton.ecs.can.core

import chisel3._

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class ProgramMemory(
    addrWidth: Int,
    cwWidth: Int,
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    nWords: Int,
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    syncMem: Boolean
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) extends MultiIOModule {
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  val br = IO(new Bundle {
    val abs = Input(Bool())
    val rel = Input(Bool())
    val addr = Input(UInt(addrWidth.W))
  })
  val cw = IO(Output(UInt(cwWidth.W)))
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  val read = IO(new Bundle {
    val addr = Input(UInt(addrWidth.W))
    val data = Output(UInt(cwWidth.W))
  })
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  val write = IO(new Bundle {
    val en = Input(Bool())
    val addr = Input(UInt(addrWidth.W))
    val data = Input(UInt(cwWidth.W))
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  })

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  private val mem =
    if (syncMem) SyncReadMem(nWords, UInt(cwWidth.W))
    else Mem(nWords, UInt(cwWidth.W))
  private val pc = RegInit(0.U(addrWidth.W))
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  when(br.abs) {
    pc := br.addr.asUInt()
  }.elsewhen(br.rel) {
    pc := (pc.asSInt() + br.addr.asSInt()).asUInt()
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  }.otherwise {
    pc := pc + 1.U
  }

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  cw := mem(pc)
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  read.data := mem(read.addr)

  when(write.en) {
    mem(write.addr) := write.data
  }
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}