Skip to content
Snippets Groups Projects
Select Git revision
  • b66f3e85872ae951d77ee95920d87ab7fcc57434
  • master default protected
2 results

README.md

Blame
    • Forked from SERG / woRkflow
    Source project has a limited visibility.
    fpga_timing.xdc 7.55 KiB 
    ##################################################################################
##                                                                              ##
## Arm MPS3 Rev-C timing XDC                                                    ##
##                                                                              ##
##################################################################################

create_clock -name CLK -period 30 [get_ports XTAL1]
create_clock -name VCLK -period 30 -waveform {5 20}

create_clock -name SWCLK -period 60 [get_ports SWCLKTCK]
create_clock -name VSWCLK -period 60 -waveform {5 35}

set_clock_groups -name async_clk_swclock -asynchronous \
-group [get_clocks -include_generated_clocks CLK] \
-group [get_clocks -include_generated_clocks SWCLK]

set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_SW[*]}]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_SW[*]}]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports {USER_nPB[*]}]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nPB[*]}]
set_input_delay -clock [get_clocks oscclk_0] -min -add_delay 2.800 [get_ports CB_nPOR]
set_input_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports CB_nPOR]
set_output_delay -clock [get_clocks oscclk_0] -min -add_delay -1.200 [get_ports {USER_nLED[*]}]
set_output_delay -clock [get_clocks oscclk_0] -max -add_delay 5.800 [get_ports {USER_nLED[*]}]

#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports {dip_switch_4bits_tri_i[*]}]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_2]
#set_input_delay -clock [get_clocks clk_pl_0] -min -add_delay 20.000 [get_ports PMOD0_3]
#set_input_delay -clock [get_clocks clk_pl_0] -max -add_delay 25.000 [get_ports PMOD0_3]
#set_output_delay -clock [get_clocks clk_pl_0] -min -add_delay 5.000 [get_ports {led_4bits_tri_o[*]}]
#set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {led_4bits_tri_o[*]}]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[0]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[0]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[1]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[1]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[2]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[2]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[3]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[3]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[4]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[4]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[5]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[5]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[6]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[6]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[7]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[7]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[8]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[8]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[9]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[9]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[10]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[10]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P011]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[11]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[12]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[12]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P013]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[13]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P0[14]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[14]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P015]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P0[15]} ]

set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[0]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[0]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[1]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[1]} ]
    set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[2]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[2]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[3]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[3]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[4]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[4]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[5]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[5]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[6]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[6]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[7]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[7]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[8]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[8]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[9]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[9]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[10]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[10]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P111]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[11]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[12]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[12]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P113]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[13]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P1[14]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[14]} ]
set_output_delay -clock [get_clocks CLK] -min -add_delay 5.000 [get_ports {P115]} ]
set_output_delay -clock [get_clocks CLK] -max -add_delay 25.000 [get_ports {P1[15]} ]