diff --git a/.simvision/100023_ks6n19__autosave.tcl b/.simvision/100023_ks6n19__autosave.tcl
deleted file mode 100644
index 3e789f963219c6a26a49bb47dccdeac8a42c8cd0..0000000000000000000000000000000000000000
--- a/.simvision/100023_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-
-# NC-Sim Command File
-# TOOL: ncsim(64) 15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into memory.shm memory -default
-database -open -shm -into waves.shm waves
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y
-probe -create -database waves de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-probe -create -database memory de1_soc_wrapper_stim.dut.raz_inst.V_count de1_soc_wrapper_stim.dut.raz_inst.H_count
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
-
-simvision -input /home/ks6n19/Documents/project/.simvision/100023_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/100023_ks6n19__autosave.tcl.svcf b/.simvision/100023_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index bf58ed695a405319103d8ef51981303fa230db4c..0000000000000000000000000000000000000000
--- a/.simvision/100023_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,260 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
- usual
- position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
- usual
- position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
- usual
- position -pos 1
-}
-preferences set toolbar-Standard-Console {
- usual
- position -pos 1
-}
-preferences set toolbar-Search-Console {
- usual
- position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
- usual
- position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
- usual
- position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
- usual
- position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Design Browser windows
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 730x500+261+33}] != ""} {
- window geometry "Design Browser 1" 730x500+261+33
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set \
- -signalsort name
-browser timecontrol set -lock 0
-
-#
-# Waveform windows
-#
-if {[catch {window new WaveWindow -name "Waves for ARM SoC Example" -geometry 1244x600+0+25}] != ""} {
- window geometry "Waves for ARM SoC Example" 1244x600+0+25
-}
-window target "Waves for ARM SoC Example" on
-waveform using {Waves for ARM SoC Example}
-waveform sidebar visibility partial
-waveform set \
- -primarycursor TimeA \
- -signalnames name \
- -signalwidth 175 \
- -units ps \
- -valuewidth 75
-waveform baseline set -time 0
-
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.CLOCK_50
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.KEY[2:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.SW[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.LEDR[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX0[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX1[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX2[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX3[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_HS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_VS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_CLK
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_BLANK_N
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.CLOCK_50
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.KEY[2:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.SW[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.LEDR[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX0[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX1[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX2[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX3[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_HS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_VS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_CLK
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_BLANK_N
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_x[9:0]}
- } ]
-waveform format $id -radix %d
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_y[8:0]}
- } ]
-waveform format $id -radix %d
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address[18:0]}
- } ]
-waveform format $id -radix %d
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.raz_inst.V_count[10:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.raz_inst.H_count[10:0]}
- } ]
-
-waveform xview limits 15056311800ps 16936872800ps
-
-#
-# Waveform Window Links
-#
-
-#
-# Memory Viewer windows
-#
-if {[catch {window new MemViewer -name "Memory Viewer 6" -geometry 361x500+904+75}] != ""} {
- window geometry "Memory Viewer 6" 361x500+904+75
-}
-window target "Memory Viewer 6" on
-memviewer using {Memory Viewer 6}
-memviewer set \
--primarycursor TimeE \
--units ps \
--radix default \
--addressradix default \
--addressorder MSBtoLSB
-
-memviewer add {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.memory[0:307199]}
-
-memviewer sidebar visibility partial
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+0+431
-
-#
-# Layout selection
-#
diff --git a/.simvision/17087_ks6n19__autosave.tcl b/.simvision/17087_ks6n19__autosave.tcl
deleted file mode 100644
index 0c9a2bb8d22664ffdcac519842c88aa07f598a7a..0000000000000000000000000000000000000000
--- a/.simvision/17087_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,57 +0,0 @@
-
-# NC-Sim Command File
-# TOOL: ncsim(64) 15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into waves.shm waves
-database -open -shm -into memory.shm memory -default
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_x de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_y
-
-simvision -input /home/ks6n19/Documents/project/.simvision/17087_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/17087_ks6n19__autosave.tcl.svcf b/.simvision/17087_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index d896d0e2a3806a35a135dfa30ec6f0544f302787..0000000000000000000000000000000000000000
--- a/.simvision/17087_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,178 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
- usual
- position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
- usual
- position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
- usual
- position -pos 1
-}
-preferences set toolbar-Standard-Console {
- usual
- position -pos 1
-}
-preferences set toolbar-Search-Console {
- usual
- position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
- usual
- position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
- usual
- position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
- usual
- position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Design Browser windows
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 730x500+261+33}] != ""} {
- window geometry "Design Browser 1" 730x500+261+33
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set -scope simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1
-browser set \
- -signalsort name
-browser yview see simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1
-browser timecontrol set -lock 0
-
-#
-# Waveform windows
-#
-if {[catch {window new WaveWindow -name "Waves for ARM SoC Example" -geometry 1010x600+4+49}] != ""} {
- window geometry "Waves for ARM SoC Example" 1010x600+4+49
-}
-window target "Waves for ARM SoC Example" on
-waveform using {Waves for ARM SoC Example}
-waveform sidebar visibility partial
-waveform set \
- -primarycursor TimeA \
- -signalnames name \
- -signalwidth 175 \
- -units ps \
- -valuewidth 75
-waveform baseline set -time 0
-
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.CLOCK_50
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.KEY[2:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.SW[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.LEDR[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX0[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX1[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX2[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX3[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_HS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_VS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_CLK
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_BLANK_N
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
- } ]
-
-waveform xview limits 0 40354010000ps
-
-#
-# Waveform Window Links
-#
-
-#
-# Memory Viewer windows
-#
-if {[catch {window new MemViewer -name "Memory Viewer 1" -geometry 700x500+8+73}] != ""} {
- window geometry "Memory Viewer 1" 700x500+8+73
-}
-window target "Memory Viewer 1" on
-memviewer using {Memory Viewer 1}
-memviewer set \
--primarycursor TimeA \
--units ps \
--radix default \
--addressradix default \
--addressorder MSBtoLSB
-
-memviewer add {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.memory[0:307199]}
-
-memviewer sidebar visibility partial
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+0+431
-
-#
-# Layout selection
-#
diff --git a/.simvision/33338_ks6n19__autosave.tcl b/.simvision/33338_ks6n19__autosave.tcl
deleted file mode 100644
index d4a9ae3675f52c3ed4cf787d3f84afcf45923e83..0000000000000000000000000000000000000000
--- a/.simvision/33338_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,50 +0,0 @@
-
-# NC-Sim Command File
-# TOOL: ncsim(64) 15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into waves.shm waves -default
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-
-simvision -input /home/ks6n19/Documents/project/.simvision/33338_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/33338_ks6n19__autosave.tcl.svcf b/.simvision/33338_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index cf580ace36dcbc319e7c4958bb92fa7061ce6df1..0000000000000000000000000000000000000000
--- a/.simvision/33338_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,189 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
- usual
- position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
- usual
- position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
- usual
- position -pos 1
-}
-preferences set toolbar-Standard-Console {
- usual
- position -pos 1
-}
-preferences set toolbar-Search-Console {
- usual
- position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
- usual
- position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
- usual
- position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
- usual
- position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Design Browser windows
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 730x500+261+33}] != ""} {
- window geometry "Design Browser 1" 730x500+261+33
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set \
- -signalsort name
-browser timecontrol set -lock 0
-
-#
-# Waveform windows
-#
-if {[catch {window new WaveWindow -name "Waves for ARM SoC Example" -geometry 1297x670+0+25}] != ""} {
- window geometry "Waves for ARM SoC Example" 1297x670+0+25
-}
-window target "Waves for ARM SoC Example" on
-waveform using {Waves for ARM SoC Example}
-waveform sidebar visibility partial
-waveform set \
- -primarycursor TimeA \
- -signalnames name \
- -signalwidth 175 \
- -units ps \
- -valuewidth 75
-waveform baseline set -time 0
-
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.CLOCK_50
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.KEY[2:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.SW[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.LEDR[9:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX0[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX1[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX2[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.HEX3[6:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_HS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_VS
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_CLK
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.VGA_BLANK_N
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_x[9:0]}
- } ]
-waveform format $id -radix %d
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_y[8:0]}
- } ]
-set id [waveform add -signals {
- simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel
- } ]
-set id [waveform add -signals {
- {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address[18:0]}
- } ]
-
-waveform xview limits 17442608900ps 17443562700ps
-
-#
-# Waveform Window Links
-#
-
-#
-# Memory Viewer windows
-#
-if {[catch {window new MemViewer -name "Memory Viewer 2" -geometry 700x500+304+138}] != ""} {
- window geometry "Memory Viewer 2" 700x500+304+138
-}
-window target "Memory Viewer 2" on
-memviewer using {Memory Viewer 2}
-memviewer set \
--primarycursor TimeA \
--units ps \
--radix default \
--addressradix default \
--addressorder MSBtoLSB
-
-memviewer add {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.memory[0:307199]}
-
-memviewer sidebar visibility partial
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+261+442
-
-#
-# Layout selection
-#
diff --git a/.simvision/93894_ks6n19__autosave.tcl b/.simvision/93894_ks6n19__autosave.tcl
deleted file mode 100644
index 4cebbb427ef39d373c083d874d726da3fcd679bd..0000000000000000000000000000000000000000
--- a/.simvision/93894_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,59 +0,0 @@
-
-# NC-Sim Command File
-# TOOL: ncsim(64) 15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into waves.shm waves
-database -open -shm -into memory.shm memory -default
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y
-probe -create -database waves de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-probe -create -database memory de1_soc_wrapper_stim.dut.raz_inst.V_count de1_soc_wrapper_stim.dut.raz_inst.H_count
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
-probe -create -database memory de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address de1_soc_wrapper_stim.dut.raz_inst.V_count de1_soc_wrapper_stim.dut.raz_inst.H_count
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_x de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_y
-
-simvision -input /home/ks6n19/Documents/project/.simvision/93894_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/93894_ks6n19__autosave.tcl.svcf b/.simvision/93894_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index d7313c6ff401af4f93681333b58646727435607d..0000000000000000000000000000000000000000
--- a/.simvision/93894_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,61 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
- usual
- position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
- usual
- position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
- usual
- position -pos 1
-}
-preferences set toolbar-Standard-Console {
- usual
- position -pos 1
-}
-preferences set toolbar-Search-Console {
- usual
- position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
- usual
- position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
- usual
- position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
- usual
- position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+0+431
-
-#
-# Layout selection
-#
diff --git a/INCA_libs/history b/INCA_libs/history
index 74c5f4219a4649e365b4b8fe604b17202abe8269..28f35bc41d58b110993de41a3cb77f68d8dabe1f 100644
--- a/INCA_libs/history
+++ b/INCA_libs/history
@@ -171,3 +171,6 @@ s166::(07Oct2020:16:45:59):( ncverilog -sv +gui +ncaccess+r -y behavioural +libe
s167::(07Oct2020:16:51:56):( ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s )
s168::(08Oct2020:15:46:51):( ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s )
s169::(08Oct2020:16:21:39):( ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s )
+s170::(16Oct2020:21:52:43):( ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex )
+s171::(16Oct2020:21:53:12):( ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex )
+s172::(16Oct2020:21:54:42):( ncverilog -sv testbench/de1_soc_wrapper_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl +define+prog_file=software/code.hex )
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts b/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts
index 009b8064a87c96f4252d8f3050f110ecab9d137b..ffa856ffd9ecbf5ae9fb7490b3ca821114946829 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts
+++ b/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts
@@ -1,12 +1,12 @@
-1601287526 /home/ks6n19/Documents/project/testbench/de1_soc_wrapper_stim.sv
1581871298 /home/ks6n19/Documents/project/behavioural/ahb_switches.sv
+1601287526 /home/ks6n19/Documents/project/testbench/de1_soc_wrapper_stim.sv
1581871483 /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv
1562613351 /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv
1601209925 /home/ks6n19/Documents/project/testbench/arm_soc_stim.sv
-1601912985 /home/ks6n19/Documents/project/behavioural/razzle.sv
+1602343537 /home/ks6n19/Documents/project/behavioural/razzle.sv
1599064789 /home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv
1599554396 /home/ks6n19/Documents/project/behavioural/ahb_ram.sv
1599325330 /home/ks6n19/Documents/project/behavioural/ahb_out.sv
-1601464831 /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv
-1601464829 /home/ks6n19/Documents/project/behavioural/arm_soc.sv
+1602343537 /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv
1601912659 /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv
+1601464829 /home/ks6n19/Documents/project/behavioural/arm_soc.sv
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args b/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args
index 122dbce8efb364ec344f4bdb7c940f8b87b41326..65f45bc2b811320d1781fed97f1114626150a408 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args
@@ -2,9 +2,10 @@
// File created by: ncverilog
// Do not modify this file
//
++libext+.sv
+gui
+ncaccess+r
-+libext+.sv
++tcl+testbench/de0_wrapper.tcl
+define+prog_file=software/code.hex
-noshowtop
-ACCESS
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args b/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args
index 713d24163252d6502ef1316dc41c53330e18d22a..ecd262b49b9a6b590ad160f6cded07e2cf88efcc 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args
@@ -2,17 +2,19 @@
// File created by: ncverilog
// Do not modify this file
//
++libext+.sv
+gui
+ncaccess+r
-+libext+.sv
++tcl+testbench/de0_wrapper.tcl
+define+prog_file=software/code.hex
-gui
--TCL
+-INPUT
+testbench/de0_wrapper.tcl
-MESSAGES
+EMGRLOG
ncverilog.log
-XLSTIME
-1602170499
+1602881682
-XLKEEP
-XLMODE
./INCA_libs/irun.lnx8664.15.20.nc
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args b/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args
index 03222e9cfcefc8025eb1c2f0a263dd6460067287..c2f431c5b5eb10cc879770f410722702de99b424 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args
@@ -2,17 +2,19 @@
// File created by: ncverilog
// Do not modify this file
//
++libext+.sv
+gui
+ncaccess+r
-+libext+.sv
++tcl+testbench/de0_wrapper.tcl
+define+prog_file=software/code.hex
-gui
--TCL
+-INPUT
+testbench/de0_wrapper.tcl
-MESSAGES
+EMGRLOG
ncverilog.log
-XLSTIME
-1602170499
+1602881682
-XLKEEP
-XLMODE
./INCA_libs/irun.lnx8664.15.20.nc
@@ -26,4 +28,4 @@ ncverilog
-XLVERSION
"TOOL: ncverilog 15.20-s058"
-XLNAME
-./INCA_libs/irun.lnx8664.15.20.nc/srv02749_15047
+./INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args b/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args
index 3b1f1f2c96b607e37f7e40ee8db28b42eae72277..a85f9bca314c85c71af960b51a593c86c09d1c08 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args
@@ -3,11 +3,11 @@
// Do not modify this file
//
-sv
-+gui
-+ncaccess+r
+testbench/de1_soc_wrapper_stim.sv
-y
behavioural
+libext+.sv
++gui
++ncaccess+r
++tcl+testbench/de0_wrapper.tcl
+define+prog_file=software/code.hex
-testbench/de1_soc_wrapper_stim.sv
--s
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args b/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args
index fb4afc80e07db2e72240d9afe0669f320d772c50..d672617409d066fbaea356eed67e529c7e61de02 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args
@@ -6,13 +6,13 @@
./INCA_libs/irun.lnx8664.15.20.nc
-RUNMODE
-sv
+testbench/de1_soc_wrapper_stim.sv
-YDIR
behavioural
-LIBEXT
.sv
-DEFINE
prog_file=software/code.hex
-testbench/de1_soc_wrapper_stim.sv
-CDSLIB
./INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib
-HDLVAR
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_cdsrun.lib b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_cdsrun.lib
new file mode 100644
index 0000000000000000000000000000000000000000..ef1745b8d419df87767188f71f84640abfa61d2f
--- /dev/null
+++ b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_cdsrun.lib
@@ -0,0 +1,2 @@
+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_hdlrun.var b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_hdlrun.var
new file mode 100644
index 0000000000000000000000000000000000000000..eb1315888c965da47ed3972aff584632e6e0541b
--- /dev/null
+++ b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_hdlrun.var
@@ -0,0 +1,89 @@
+DEFINE LANG_MAP (\
+ .v => verilog,\
+ .vp => verilog,\
+ .vs => verilog,\
+ .V => verilog,\
+ .VP => verilog,\
+ .VS => verilog,\
+ .v95 => verilog95,\
+ .v95p => verilog95,\
+ .V95 => verilog95,\
+ .V95P => verilog95,\
+ .vhd => vhdl,\
+ .vhdp => vhdl,\
+ .vhdl => vhdl,\
+ .vhdlp => vhdl,\
+ .VHDL => vhdl,\
+ .VHDLP => vhdl,\
+ .VHD => vhdl,\
+ .VHDP => vhdl,\
+ .e => e,\
+ .E => e,\
+ .elib => elib,\
+ .ELIB => elib,\
+ .viplib => elib,\
+ .VIPLIB => elib,\
+ .sv => systemverilog,\
+ .svp => systemverilog,\
+ .SV => systemverilog,\
+ .SVP => systemverilog,\
+ .svi => systemverilog,\
+ .svh => systemverilog,\
+ .vlib => systemverilog,\
+ .VLIB => systemverilog,\
+ .vams => verilog-ams,\
+ .VAMS => verilog-ams,\
+ .svams => sv-ams,\
+ .SVAMS => sv-ams,\
+ .svms => sv-ams,\
+ .SVMS => sv-ams,\
+ .vha => vhdl-ams,\
+ .VHA => vhdl-ams,\
+ .vhams => vhdl-ams,\
+ .VHAMS => vhdl-ams,\
+ .vhms => vhdl-ams,\
+ .VHMS => vhdl-ams,\
+ .scs => scs,\
+ .sp => scs,\
+ .s => assembly,\
+ .c => c,\
+ .o => o,\
+ .cpp => cpp,\
+ .cc => cpp,\
+ .a => a,\
+ .so => so,\
+ .sl => so,\
+ .pslvlog => psl_vlog,\
+ .pslvhdl => psl_vhdl,\
+ .pslsc => psl_sc,\
+ .vhcfg => vhcfg,\
+ .vhcfgp => vhcfg,\
+ .sv.gz => systemverilog,\
+ .sv.Z => systemverilog,\
+ DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/.inca.db.150.lnx8664 b/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/.inca.db.150.lnx8664
index b0b223722f913bc0e152079643732565b2727a96..9eeff495e20c9c4134e47a4e2ee5e81e88b36425 100644
Binary files a/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/.inca.db.150.lnx8664 and b/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/.inca.db.150.lnx8664 differ
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/inca.lnx8664.150.pak b/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/inca.lnx8664.150.pak
index c1ea5d0622fb323754ee53ab840dd12ae47a43f9..4d676ef0af9160b6943d8bf9b7c152a42fe10f36 100644
Binary files a/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/inca.lnx8664.150.pak and b/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/inca.lnx8664.150.pak differ
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts b/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts
index 938b324f2417b02ca4474c1ab8924e30b0500618..c52bf37c450817783cf94495a1c8c7de79e433fe 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts
@@ -1 +1 @@
-1602168452 behavioural
+1602881525 behavioural
diff --git a/INCA_libs/worklib/.inca.db.150.lnx8664 b/INCA_libs/worklib/.inca.db.150.lnx8664
index 973b8742d7c90b8783a36499f125d43052537b45..02f009b97e9d36231a0b7d433f30729160db312c 100644
Binary files a/INCA_libs/worklib/.inca.db.150.lnx8664 and b/INCA_libs/worklib/.inca.db.150.lnx8664 differ
diff --git a/INCA_libs/worklib/inca.lnx8664.150.pak b/INCA_libs/worklib/inca.lnx8664.150.pak
index 5b867d1cb259698566d3235361cb7c7cf6cdecc4..a7d9bc53de42eade285367f0d39801a2015deac4 100644
Binary files a/INCA_libs/worklib/inca.lnx8664.150.pak and b/INCA_libs/worklib/inca.lnx8664.150.pak differ
diff --git a/ncverilog.history b/ncverilog.history
index e14c63c749b902b06294a940962b9f10ff0fb9a7..a2b44ce3261d034a085feb3dcbc05f1028fab6f2 100644
--- a/ncverilog.history
+++ b/ncverilog.history
@@ -167,3 +167,6 @@ s166(07Oct2020:16:45:59): ncverilog -sv +gui +ncaccess+r -y behavioural +libext
s167(07Oct2020:16:51:56): ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s
s168(08Oct2020:15:46:51): ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s
s169(08Oct2020:16:21:39): ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s
+s170(16Oct2020:21:52:43): ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex
+s171(16Oct2020:21:53:12): ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex
+s172(16Oct2020:21:54:42): ncverilog -sv testbench/de1_soc_wrapper_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl +define+prog_file=software/code.hex
diff --git a/ncverilog.key b/ncverilog.key
index 6e67483f4dcec38d76a1f7065dedb72447db4c2d..a3abe50906e1a7234d71453aaa367b0f8d7a9c2d 100644
--- a/ncverilog.key
+++ b/ncverilog.key
@@ -1,5 +1 @@
-# Restoring simulation environment...
-input {testbench/de0_wrapper.tcl}
-input -quiet .reinvoke.sim
-file delete .reinvoke.sim
-run
+exit
diff --git a/ncverilog.log b/ncverilog.log
index ec6505ce4a1294b5ba173a69346003a0b6f05511..e311f6254b51d9ca91fc2f69173277bd1840372c 100644
--- a/ncverilog.log
+++ b/ncverilog.log
@@ -1,23 +1,47 @@
ncverilog(64): 15.20-s058: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
-TOOL: ncverilog 15.20-s058: Started on Oct 08, 2020 at 16:21:39 BST
+TOOL: ncverilog 15.20-s058: Started on Oct 16, 2020 at 21:54:42 BST
ncverilog
-sv
- +gui
- +ncaccess+r
+ testbench/de1_soc_wrapper_stim.sv
-y
behavioural
+libext+.sv
+ +gui
+ +ncaccess+r
+ +tcl+testbench/de0_wrapper.tcl
+define+prog_file=software/code.hex
- testbench/de1_soc_wrapper_stim.sv
- -s
+Recompiling... reason: file './behavioural/de1_soc_wrapper.sv' is newer than expected.
+ expected: Wed Sep 30 12:20:31 2020
+ actual: Sat Oct 10 16:25:37 2020
+ Caching library 'behavioural' ....... Done
+ Caching library 'worklib' ....... Done
+ Elaborating the design hierarchy:
+ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
+ de1_soc_wrapper dut(.CLOCK_50, .LEDR, .SW, .KEY, .HEX0, .HEX1, .HEX2, .HEX3,.VGA_R, .VGA_G, .VGA_B, .VGA_HS, .VGA_VS, .VGA_CLK, .VGA_BLANK_N);
+ |
+ncelab: *W,CUVMPW (./testbench/de1_soc_wrapper_stim.sv,20|48): port sizes differ in port connection (3/4).
+ Building instance overlay tables: .................... Done
+ Building instance specific data structures.
+ Loading native compiled code: .................... Done
+ Design hierarchy summary:
+ Instances Unique
+ Modules: 10 10
+ Registers: 919 919
+ Scalar wires: 11159 -
+ Expanded wires: 122 6
+ Vectored wires: 51 -
+ Always blocks: 858 858
+ Initial blocks: 3 3
+ Cont. assignments: 973 11132
+ Pseudo assignments: 22 22
+ Simulation timescale: 100ps
+ Writing initial simulation snapshot: worklib.de1_soc_wrapper_stim:sv
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
-ncsim>
-ncsim> source /eda/cadence/incisiv/tools/inca/files/ncsimrc
-ncsim>
+
-------------------------------------
Relinquished control to SimVision...
-# Restoring simulation environment...
-ncsim> input {testbench/de0_wrapper.tcl}
+ncsim>
+ncsim> source /eda/cadence/incisiv/tools/inca/files/ncsimrc
ncsim> # SimVision command script arm_soc.tcl
ncsim>
ncsim> simvision {
@@ -52,8 +76,6 @@ ncsim> simvision {
>
> }
ncsim>
-ncsim> input -quiet .reinvoke.sim
-ncsim> file delete .reinvoke.sim
-ncsim> run
-Simulation interrupted at 35438205 NS + 5
-ncsim>
\ No newline at end of file
+ncsim> ^C
+ncsim> exit
+TOOL: ncverilog 15.20-s058: Exiting on Oct 16, 2020 at 21:54:58 BST (total: 00:00:16)
diff --git a/simulate_wrapper b/simulate_wrapper
new file mode 100755
index 0000000000000000000000000000000000000000..ef56a5990bf3380193e937ede10be0c514d6466d
--- /dev/null
+++ b/simulate_wrapper
@@ -0,0 +1,20 @@
+#! /bin/sh
+
+if [ "$1" != "-no_graphics" ]
+then
+ options=" +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl"
+ shift
+fi
+
+HEXPROG=software/code.hex
+PROGRAM=" +define+prog_file=${HEXPROG}"
+
+if [ -f "$1" ]
+then
+ testbench=$1
+else
+ testbench=testbench/de1_soc_wrapper_stim.sv
+fi
+
+ncverilog -sv $testbench -y behavioural +libext+.sv $options $PROGRAM
+
diff --git a/testbench/simulate_command b/testbench/simulate_command
deleted file mode 100644
index 4dacb5708d41b15a18574bbc27c4b823f62a09c5..0000000000000000000000000000000000000000
--- a/testbench/simulate_command
+++ /dev/null
@@ -1,5 +0,0 @@
- ncverilog -sv +gui +ncaccess+r \
- +tcl+testbench/de0_wrapper.tcl \
- -y behavioural +libext+.sv \
- +define+prog_file=software/code.hex \
- testbench/de1_soc_wrapper_stim.sv