From 927920187c2bbd157cb2dd4dd5b72c5777e5d8f0 Mon Sep 17 00:00:00 2001
From: ks6n19 <ks6n19@soton.ac.uk>
Date: Fri, 16 Oct 2020 21:56:49 +0100
Subject: [PATCH] made simulate_wrapper sh

---
 .simvision/100023_ks6n19__autosave.tcl        |  56 ----
 .simvision/100023_ks6n19__autosave.tcl.svcf   | 260 ------------------
 .simvision/17087_ks6n19__autosave.tcl         |  57 ----
 .simvision/17087_ks6n19__autosave.tcl.svcf    | 178 ------------
 .simvision/33338_ks6n19__autosave.tcl         |  50 ----
 .simvision/33338_ks6n19__autosave.tcl.svcf    | 189 -------------
 .simvision/93894_ks6n19__autosave.tcl         |  59 ----
 .simvision/93894_ks6n19__autosave.tcl.svcf    |  61 ----
 INCA_libs/history                             |   3 +
 INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts |   8 +-
 INCA_libs/irun.lnx8664.15.20.nc/ncelab.args   |   3 +-
 INCA_libs/irun.lnx8664.15.20.nc/ncsim.args    |   8 +-
 .../irun.lnx8664.15.20.nc/ncsim_restart.args  |  10 +-
 .../irun.lnx8664.15.20.nc/ncverilog.args      |   8 +-
 INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args   |   2 +-
 .../srv02749_60374_cdsrun.lib                 |   2 +
 .../srv02749_60374_hdlrun.var                 |  89 ++++++
 .../xllibs/behavioural/.inca.db.150.lnx8664   | Bin 8 -> 8 bytes
 .../xllibs/behavioural/inca.lnx8664.150.pak   | Bin 8146380 -> 8146380 bytes
 INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts |   2 +-
 INCA_libs/worklib/.inca.db.150.lnx8664        | Bin 8 -> 8 bytes
 INCA_libs/worklib/inca.lnx8664.150.pak        | Bin 7738646 -> 7738685 bytes
 ncverilog.history                             |   3 +
 ncverilog.key                                 |   6 +-
 ncverilog.log                                 |  52 +++-
 simulate_wrapper                              |  20 ++
 testbench/simulate_command                    |   5 -
 27 files changed, 178 insertions(+), 953 deletions(-)
 delete mode 100644 .simvision/100023_ks6n19__autosave.tcl
 delete mode 100644 .simvision/100023_ks6n19__autosave.tcl.svcf
 delete mode 100644 .simvision/17087_ks6n19__autosave.tcl
 delete mode 100644 .simvision/17087_ks6n19__autosave.tcl.svcf
 delete mode 100644 .simvision/33338_ks6n19__autosave.tcl
 delete mode 100644 .simvision/33338_ks6n19__autosave.tcl.svcf
 delete mode 100644 .simvision/93894_ks6n19__autosave.tcl
 delete mode 100644 .simvision/93894_ks6n19__autosave.tcl.svcf
 create mode 100644 INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_cdsrun.lib
 create mode 100644 INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_hdlrun.var
 create mode 100755 simulate_wrapper
 delete mode 100644 testbench/simulate_command

diff --git a/.simvision/100023_ks6n19__autosave.tcl b/.simvision/100023_ks6n19__autosave.tcl
deleted file mode 100644
index 3e789f9..0000000
--- a/.simvision/100023_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,56 +0,0 @@
-
-# NC-Sim Command File
-# TOOL:	ncsim(64)	15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into memory.shm memory -default
-database -open -shm -into waves.shm waves
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y
-probe -create -database waves de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-probe -create -database memory de1_soc_wrapper_stim.dut.raz_inst.V_count de1_soc_wrapper_stim.dut.raz_inst.H_count
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
-
-simvision -input /home/ks6n19/Documents/project/.simvision/100023_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/100023_ks6n19__autosave.tcl.svcf b/.simvision/100023_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index bf58ed6..0000000
--- a/.simvision/100023_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,260 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
-  usual
-  position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
-  usual
-  position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Standard-Console {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Search-Console {
-  usual
-  position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
-  usual
-  position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
-  usual
-  position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
-  usual
-  position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Design Browser windows
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 730x500+261+33}] != ""} {
-    window geometry "Design Browser 1" 730x500+261+33
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set \
-    -signalsort name
-browser timecontrol set -lock 0
-
-#
-# Waveform windows
-#
-if {[catch {window new WaveWindow -name "Waves for ARM SoC Example" -geometry 1244x600+0+25}] != ""} {
-    window geometry "Waves for ARM SoC Example" 1244x600+0+25
-}
-window target "Waves for ARM SoC Example" on
-waveform using {Waves for ARM SoC Example}
-waveform sidebar visibility partial
-waveform set \
-    -primarycursor TimeA \
-    -signalnames name \
-    -signalwidth 175 \
-    -units ps \
-    -valuewidth 75
-waveform baseline set -time 0
-
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.CLOCK_50
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.KEY[2:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.SW[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.LEDR[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX0[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX1[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX2[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX3[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_HS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_VS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_CLK
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_BLANK_N
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.CLOCK_50
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.KEY[2:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.SW[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.LEDR[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX0[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX1[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX2[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX3[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_HS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_VS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_CLK
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_BLANK_N
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_x[9:0]}
-	} ]
-waveform format $id -radix %d
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_y[8:0]}
-	} ]
-waveform format $id -radix %d
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address[18:0]}
-	} ]
-waveform format $id -radix %d
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.raz_inst.V_count[10:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.raz_inst.H_count[10:0]}
-	} ]
-
-waveform xview limits 15056311800ps 16936872800ps
-
-#
-# Waveform Window Links
-#
-
-#
-# Memory Viewer windows
-#
-if {[catch {window new MemViewer -name "Memory Viewer 6" -geometry 361x500+904+75}] != ""} {
-    window geometry "Memory Viewer 6" 361x500+904+75
-}
-window target "Memory Viewer 6" on
-memviewer using {Memory Viewer 6}
-memviewer set \
--primarycursor TimeE \
--units ps \
--radix default \
--addressradix default \
--addressorder MSBtoLSB
-
-memviewer add  {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.memory[0:307199]} 
-
-memviewer sidebar visibility partial
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+0+431
-
-#
-# Layout selection
-#
diff --git a/.simvision/17087_ks6n19__autosave.tcl b/.simvision/17087_ks6n19__autosave.tcl
deleted file mode 100644
index 0c9a2bb..0000000
--- a/.simvision/17087_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,57 +0,0 @@
-
-# NC-Sim Command File
-# TOOL:	ncsim(64)	15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into waves.shm waves
-database -open -shm -into memory.shm memory -default
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_x de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_y
-
-simvision -input /home/ks6n19/Documents/project/.simvision/17087_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/17087_ks6n19__autosave.tcl.svcf b/.simvision/17087_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index d896d0e..0000000
--- a/.simvision/17087_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,178 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
-  usual
-  position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
-  usual
-  position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Standard-Console {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Search-Console {
-  usual
-  position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
-  usual
-  position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
-  usual
-  position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
-  usual
-  position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Design Browser windows
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 730x500+261+33}] != ""} {
-    window geometry "Design Browser 1" 730x500+261+33
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set -scope  simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1 
-browser set \
-    -signalsort name
-browser yview see  simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1 
-browser timecontrol set -lock 0
-
-#
-# Waveform windows
-#
-if {[catch {window new WaveWindow -name "Waves for ARM SoC Example" -geometry 1010x600+4+49}] != ""} {
-    window geometry "Waves for ARM SoC Example" 1010x600+4+49
-}
-window target "Waves for ARM SoC Example" on
-waveform using {Waves for ARM SoC Example}
-waveform sidebar visibility partial
-waveform set \
-    -primarycursor TimeA \
-    -signalnames name \
-    -signalwidth 175 \
-    -units ps \
-    -valuewidth 75
-waveform baseline set -time 0
-
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.CLOCK_50
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.KEY[2:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.SW[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.LEDR[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX0[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX1[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX2[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX3[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_HS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_VS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_CLK
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_BLANK_N
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-	} ]
-
-waveform xview limits 0 40354010000ps
-
-#
-# Waveform Window Links
-#
-
-#
-# Memory Viewer windows
-#
-if {[catch {window new MemViewer -name "Memory Viewer 1" -geometry 700x500+8+73}] != ""} {
-    window geometry "Memory Viewer 1" 700x500+8+73
-}
-window target "Memory Viewer 1" on
-memviewer using {Memory Viewer 1}
-memviewer set \
--primarycursor TimeA \
--units ps \
--radix default \
--addressradix default \
--addressorder MSBtoLSB
-
-memviewer add  {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.memory[0:307199]} 
-
-memviewer sidebar visibility partial
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+0+431
-
-#
-# Layout selection
-#
diff --git a/.simvision/33338_ks6n19__autosave.tcl b/.simvision/33338_ks6n19__autosave.tcl
deleted file mode 100644
index d4a9ae3..0000000
--- a/.simvision/33338_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,50 +0,0 @@
-
-# NC-Sim Command File
-# TOOL:	ncsim(64)	15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into waves.shm waves -default
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-
-simvision -input /home/ks6n19/Documents/project/.simvision/33338_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/33338_ks6n19__autosave.tcl.svcf b/.simvision/33338_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index cf580ac..0000000
--- a/.simvision/33338_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,189 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
-  usual
-  position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
-  usual
-  position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Standard-Console {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Search-Console {
-  usual
-  position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
-  usual
-  position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
-  usual
-  position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
-  usual
-  position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Design Browser windows
-#
-if {[catch {window new WatchList -name "Design Browser 1" -geometry 730x500+261+33}] != ""} {
-    window geometry "Design Browser 1" 730x500+261+33
-}
-window target "Design Browser 1" on
-browser using {Design Browser 1}
-browser set \
-    -signalsort name
-browser timecontrol set -lock 0
-
-#
-# Waveform windows
-#
-if {[catch {window new WaveWindow -name "Waves for ARM SoC Example" -geometry 1297x670+0+25}] != ""} {
-    window geometry "Waves for ARM SoC Example" 1297x670+0+25
-}
-window target "Waves for ARM SoC Example" on
-waveform using {Waves for ARM SoC Example}
-waveform sidebar visibility partial
-waveform set \
-    -primarycursor TimeA \
-    -signalnames name \
-    -signalwidth 175 \
-    -units ps \
-    -valuewidth 75
-waveform baseline set -time 0
-
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.CLOCK_50
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.KEY[2:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.SW[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.LEDR[9:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX0[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX1[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX2[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.HEX3[6:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_R[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_G[7:0]}
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.VGA_B[7:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_HS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_VS
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_CLK
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.VGA_BLANK_N
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.soc_inst.HADDR[31:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HWRITE
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_x[9:0]}
-	} ]
-waveform format $id -radix %d
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel_y[8:0]}
-	} ]
-set id [waveform add -signals  {
-	simulator::de1_soc_wrapper_stim.dut.raz_inst.pixel
-	} ]
-set id [waveform add -signals  {
-	{simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address[18:0]}
-	} ]
-
-waveform xview limits 17442608900ps 17443562700ps
-
-#
-# Waveform Window Links
-#
-
-#
-# Memory Viewer windows
-#
-if {[catch {window new MemViewer -name "Memory Viewer 2" -geometry 700x500+304+138}] != ""} {
-    window geometry "Memory Viewer 2" 700x500+304+138
-}
-window target "Memory Viewer 2" on
-memviewer using {Memory Viewer 2}
-memviewer set \
--primarycursor TimeA \
--units ps \
--radix default \
--addressradix default \
--addressorder MSBtoLSB
-
-memviewer add  {simulator::de1_soc_wrapper_stim.dut.soc_inst.pix1.memory[0:307199]} 
-
-memviewer sidebar visibility partial
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+261+442
-
-#
-# Layout selection
-#
diff --git a/.simvision/93894_ks6n19__autosave.tcl b/.simvision/93894_ks6n19__autosave.tcl
deleted file mode 100644
index 4cebbb4..0000000
--- a/.simvision/93894_ks6n19__autosave.tcl
+++ /dev/null
@@ -1,59 +0,0 @@
-
-# NC-Sim Command File
-# TOOL:	ncsim(64)	15.20-s058
-#
-
-set tcl_prompt1 {puts -nonewline "ncsim> "}
-set tcl_prompt2 {puts -nonewline "> "}
-set vlog_format %h
-set vhdl_format %v
-set real_precision 6
-set display_unit auto
-set time_unit module
-set heap_garbage_size -200
-set heap_garbage_time 0
-set assert_report_level note
-set assert_stop_level error
-set autoscope yes
-set assert_1164_warnings yes
-set pack_assert_off {}
-set severity_pack_assert_off {note warning}
-set assert_output_stop_level failed
-set tcl_debug_level 0
-set relax_path_name 1
-set vhdl_vcdmap XX01ZX01X
-set intovf_severity_level ERROR
-set probe_screen_format 0
-set rangecnst_severity_level ERROR
-set textio_severity_level ERROR
-set vital_timing_checks_on 1
-set vlog_code_show_force 0
-set assert_count_attempts 1
-set tcl_all64 false
-set tcl_runerror_exit false
-set assert_report_incompletes 0
-set show_force 1
-set force_reset_by_reinvoke 0
-set tcl_relaxed_literal 0
-set probe_exclude_patterns {}
-set probe_packed_limit 4k
-set probe_unpacked_limit 16k
-set assert_internal_msg no
-set svseed 1
-set assert_reporting_mode 0
-alias . run
-alias iprof profile
-alias quit exit
-database -open -shm -into waves.shm waves
-database -open -shm -into memory.shm memory -default
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT
-probe -create -database waves de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y
-probe -create -database waves de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address
-probe -create -database memory de1_soc_wrapper_stim.dut.raz_inst.V_count de1_soc_wrapper_stim.dut.raz_inst.H_count
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel
-probe -create -database memory de1_soc_wrapper_stim.CLOCK_50 de1_soc_wrapper_stim.KEY de1_soc_wrapper_stim.SW de1_soc_wrapper_stim.LEDR de1_soc_wrapper_stim.HEX0 de1_soc_wrapper_stim.HEX1 de1_soc_wrapper_stim.HEX2 de1_soc_wrapper_stim.HEX3 de1_soc_wrapper_stim.VGA_R de1_soc_wrapper_stim.VGA_G de1_soc_wrapper_stim.VGA_B de1_soc_wrapper_stim.VGA_HS de1_soc_wrapper_stim.VGA_VS de1_soc_wrapper_stim.VGA_CLK de1_soc_wrapper_stim.VGA_BLANK_N de1_soc_wrapper_stim.dut.soc_inst.HADDR de1_soc_wrapper_stim.dut.soc_inst.HWRITE de1_soc_wrapper_stim.dut.soc_inst.HSEL_RAM de1_soc_wrapper_stim.dut.soc_inst.HSEL_SW de1_soc_wrapper_stim.dut.soc_inst.HSEL_DOUT de1_soc_wrapper_stim.dut.raz_inst.pixel de1_soc_wrapper_stim.dut.raz_inst.pixel_x de1_soc_wrapper_stim.dut.raz_inst.pixel_y de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_address de1_soc_wrapper_stim.dut.raz_inst.V_count de1_soc_wrapper_stim.dut.raz_inst.H_count
-probe -create -database memory de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_x de1_soc_wrapper_stim.dut.soc_inst.pix1.pixel_y
-
-simvision -input /home/ks6n19/Documents/project/.simvision/93894_ks6n19__autosave.tcl.svcf
diff --git a/.simvision/93894_ks6n19__autosave.tcl.svcf b/.simvision/93894_ks6n19__autosave.tcl.svcf
deleted file mode 100644
index d7313c6..0000000
--- a/.simvision/93894_ks6n19__autosave.tcl.svcf
+++ /dev/null
@@ -1,61 +0,0 @@
-
-#
-# Preferences
-#
-preferences set toolbar-CursorControl-MemViewer {
-  usual
-  position -row 0 -anchor e
-}
-preferences set toolbar-Standard-MemViewer {
-  usual
-  position -row 1
-}
-preferences set plugin-enable-svdatabrowser-new 1
-preferences set toolbar-sendToIndago-WaveWindow {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Standard-Console {
-  usual
-  position -pos 1
-}
-preferences set toolbar-Search-Console {
-  usual
-  position -pos 2
-}
-preferences set plugin-enable-groupscope 0
-preferences set plugin-enable-interleaveandcompare 0
-preferences set plugin-enable-waveformfrequencyplot 0
-preferences set toolbar-Windows-MemViewer {
-  usual
-  position -row 1 -pos 1
-}
-preferences set toolbar-TimeSearch-MemViewer {
-  usual
-  position -row 2 -pos 0
-}
-preferences set whats-new-dont-show-at-startup 1
-preferences set toolbar-SimControl-MemViewer {
-  usual
-  position -row 3 -pos 0
-}
-
-#
-# Mnemonic Maps
-#
-mmap new -reuse -name {Boolean as Logic} -radix %b -contents {{%c=FALSE -edgepriority 1 -shape low}
-{%c=TRUE -edgepriority 1 -shape high}}
-mmap new -reuse -name {Example Map} -radix %x -contents {{%b=11???? -bgcolor orange -label REG:%x -linecolor yellow -shape bus}
-{%x=1F -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=2C -bgcolor red -label ERROR -linecolor white -shape EVENT}
-{%x=* -label %x -linecolor gray -shape bus}}
-
-#
-# Console windows
-#
-console set -windowname Console
-window geometry Console 730x250+0+431
-
-#
-# Layout selection
-#
diff --git a/INCA_libs/history b/INCA_libs/history
index 74c5f42..28f35bc 100644
--- a/INCA_libs/history
+++ b/INCA_libs/history
@@ -171,3 +171,6 @@ s166::(07Oct2020:16:45:59):( ncverilog -sv +gui +ncaccess+r -y behavioural +libe
 s167::(07Oct2020:16:51:56):( ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s )
 s168::(08Oct2020:15:46:51):( ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s )
 s169::(08Oct2020:16:21:39):( ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s )
+s170::(16Oct2020:21:52:43):( ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex )
+s171::(16Oct2020:21:53:12):( ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex )
+s172::(16Oct2020:21:54:42):( ncverilog -sv testbench/de1_soc_wrapper_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl +define+prog_file=software/code.hex )
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts b/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts
index 009b806..ffa856f 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts
+++ b/INCA_libs/irun.lnx8664.15.20.nc/.timestamp.ts
@@ -1,12 +1,12 @@
-1601287526 /home/ks6n19/Documents/project/testbench/de1_soc_wrapper_stim.sv
 1581871298 /home/ks6n19/Documents/project/behavioural/ahb_switches.sv
+1601287526 /home/ks6n19/Documents/project/testbench/de1_soc_wrapper_stim.sv
 1581871483 /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv
 1562613351 /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv
 1601209925 /home/ks6n19/Documents/project/testbench/arm_soc_stim.sv
-1601912985 /home/ks6n19/Documents/project/behavioural/razzle.sv
+1602343537 /home/ks6n19/Documents/project/behavioural/razzle.sv
 1599064789 /home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv
 1599554396 /home/ks6n19/Documents/project/behavioural/ahb_ram.sv
 1599325330 /home/ks6n19/Documents/project/behavioural/ahb_out.sv
-1601464831 /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv
-1601464829 /home/ks6n19/Documents/project/behavioural/arm_soc.sv
+1602343537 /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv
 1601912659 /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv
+1601464829 /home/ks6n19/Documents/project/behavioural/arm_soc.sv
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args b/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args
index 122dbce..65f45bc 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncelab.args
@@ -2,9 +2,10 @@
 // File created by:  ncverilog
 // Do not modify this file
 //
++libext+.sv
 +gui
 +ncaccess+r
-+libext+.sv
++tcl+testbench/de0_wrapper.tcl
 +define+prog_file=software/code.hex
 -noshowtop
 -ACCESS
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args b/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args
index 713d241..ecd262b 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncsim.args
@@ -2,17 +2,19 @@
 // File created by:  ncverilog
 // Do not modify this file
 //
++libext+.sv
 +gui
 +ncaccess+r
-+libext+.sv
++tcl+testbench/de0_wrapper.tcl
 +define+prog_file=software/code.hex
 -gui
--TCL
+-INPUT
+testbench/de0_wrapper.tcl
 -MESSAGES
 +EMGRLOG
 ncverilog.log
 -XLSTIME
-1602170499
+1602881682
 -XLKEEP
 -XLMODE
 ./INCA_libs/irun.lnx8664.15.20.nc
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args b/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args
index 03222e9..c2f431c 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncsim_restart.args
@@ -2,17 +2,19 @@
 // File created by:  ncverilog
 // Do not modify this file
 //
++libext+.sv
 +gui
 +ncaccess+r
-+libext+.sv
++tcl+testbench/de0_wrapper.tcl
 +define+prog_file=software/code.hex
 -gui
--TCL
+-INPUT
+testbench/de0_wrapper.tcl
 -MESSAGES
 +EMGRLOG
 ncverilog.log
 -XLSTIME
-1602170499
+1602881682
 -XLKEEP
 -XLMODE
 ./INCA_libs/irun.lnx8664.15.20.nc
@@ -26,4 +28,4 @@ ncverilog
 -XLVERSION
 "TOOL:	ncverilog	15.20-s058"
 -XLNAME
-./INCA_libs/irun.lnx8664.15.20.nc/srv02749_15047
+./INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args b/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args
index 3b1f1f2..a85f9bc 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncverilog.args
@@ -3,11 +3,11 @@
 // Do not modify this file
 //
 -sv
-+gui
-+ncaccess+r
+testbench/de1_soc_wrapper_stim.sv
 -y
 behavioural
 +libext+.sv
++gui
++ncaccess+r
++tcl+testbench/de0_wrapper.tcl
 +define+prog_file=software/code.hex
-testbench/de1_soc_wrapper_stim.sv
--s
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args b/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args
index fb4afc8..d672617 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ncvlog.args
@@ -6,13 +6,13 @@
 ./INCA_libs/irun.lnx8664.15.20.nc
 -RUNMODE
 -sv
+testbench/de1_soc_wrapper_stim.sv
 -YDIR
 behavioural
 -LIBEXT
 .sv
 -DEFINE
 prog_file=software/code.hex
-testbench/de1_soc_wrapper_stim.sv
 -CDSLIB
 ./INCA_libs/irun.lnx8664.15.20.nc/cdsrun.lib
 -HDLVAR
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_cdsrun.lib b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_cdsrun.lib
new file mode 100644
index 0000000..ef1745b
--- /dev/null
+++ b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_cdsrun.lib
@@ -0,0 +1,2 @@
+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_hdlrun.var b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_hdlrun.var
new file mode 100644
index 0000000..eb13158
--- /dev/null
+++ b/INCA_libs/irun.lnx8664.15.20.nc/srv02749_60374_hdlrun.var
@@ -0,0 +1,89 @@
+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)
diff --git a/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/.inca.db.150.lnx8664 b/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/.inca.db.150.lnx8664
index b0b223722f913bc0e152079643732565b2727a96..9eeff495e20c9c4134e47a4e2ee5e81e88b36425 100644
GIT binary patch
literal 8
Kcmcc500968007_s

literal 8
Kcmcb|00967_yFGk

diff --git a/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/inca.lnx8664.150.pak b/INCA_libs/irun.lnx8664.15.20.nc/xllibs/behavioural/inca.lnx8664.150.pak
index c1ea5d0622fb323754ee53ab840dd12ae47a43f9..4d676ef0af9160b6943d8bf9b7c152a42fe10f36 100644
GIT binary patch
delta 546
zcmX>z`y(?5H?%OeFtsqZu(YtYu(hzaaI|o4;S#82F1*w@{lWce*>;0ku6Bc3?skJ(
zo_2#;-gbjpzIKCJ{&s^}fp&vh!FGdMp>~5>;dX;sk#>Vx(RPDcv37%6@pgk+iFSip
z$##QUsdj@}>2`x!nRbI(ka=?L2DS3-2DJ+92DOUq2DM7<2DQrV2DK{f2DPf~2DNJK
z2DR$#2DKXP2DO^)2DMu42DRGl2DLiv2DQ5F2DN(a2DSR_2DJw52DOIm2DL`*2DQfR
z2DK*b2DPT`2DN7G2DRqx2DKLL2DO&$2DMi02DR4h2DLWr2DP^B2DNtW2DSF>2DJ|D
z2DOgu2DMJ@2DQ%Z2DL8j2DPs32DNVO2DR?(2DKjT2DP5;2DM)82DRSp2DLuz2DQHJ
z2DN_e2DSd}2DJh02DO3h2DL%$2DQQM2DKsW2DPE>2DM@B2DRbs2DK6G2DOpx2DMS`
z2DQ=c2DLHm2DP#62DNeR2DS0+2DJ(82DORp2DM4;2DQoU2DK^e2DPc}2DNGJ2DRz!
z2DKUO2DO>(2DMr32DRDk2DLfu2DQ2E2DN$Z2DSO^2DJt42DOFl2DL@)2DQcQ2DK&a
z2DPQ_2DN4F2DRnw2DKIK2DO##2DMe&4Qi{`CV`@K`-A({w$anYre_FDXW@(!nC>7c
V$+6wlx~5!6;64Kc$V$|J836R3#TNho

delta 552
zcmX>z`y(?5H?%OeFtsqZu(YtYu(hzaaI|o4;S#82{-0Sg{lWce*>;0ku6Bc3?skJ(
zo_2#;-gbjpzIKCJ{&s^}fp&vh!FGdMp>~5>;dX;sk#>Vx(RPDcv37%6@pgk+iFSip
z$##QUsdj@}>2`x!nRbI(ka=?L2DS3-2DJ+92DOUq2DM7<2DQrV2DK{f2DPf~2DNJK
z2DR$#2DKXP2DO^)2DMu42DRGl2DLiv2DQ5F2DN(a2DSR_2DJw52DOIm2DL`*2DQfR
z2DK*b2DPT`2DN7G2DRqx2DKLL2DO&$2DMi02DR4h2DLWr2DP^B2DNtW2DSF>2DJ|D
z2DOgu2DMJ@2DQ%Z2DL8j2DPs32DNVO2DR?(2DKjT2DP5;2DM)82DRSp2DLuz2DQHJ
z2DN_e2DSd}2DJh02DO3h2DL%$2DQQM2DKsW2DPE>2DM@B2DRbs2DK6G2DOpx2DMS`
z2DQ=c2DLHm2DP#62DNeR2DS0+2DJ(82DORp2DM4;2DQoU2DK^e2DPc}2DNGJ2DRz!
z2DKUO2DO>(2DMr32DRDk2DLfu2DQ2E2DN$Z2DSO^2DJt42DOFl2DL@)2DQcQ2DK&a
z2DPQ_2DN4F2DRnw2DKIK2DO##2DMe&4Qi{`CNa-+sNVkIezk2h*F6RpnEsC=PHeh^
Vq$J07SL>Q`Apw|_tV9i14FHE&#OVM4

diff --git a/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts b/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts
index 938b324..c52bf37 100644
--- a/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts
+++ b/INCA_libs/irun.lnx8664.15.20.nc/ydir_files.ts
@@ -1 +1 @@
-1602168452 behavioural
+1602881525 behavioural
diff --git a/INCA_libs/worklib/.inca.db.150.lnx8664 b/INCA_libs/worklib/.inca.db.150.lnx8664
index 973b8742d7c90b8783a36499f125d43052537b45..02f009b97e9d36231a0b7d433f30729160db312c 100644
GIT binary patch
literal 8
KcmXS6fB*mkr~q{U

literal 8
KcmXSBfB*mkpa66L

diff --git a/INCA_libs/worklib/inca.lnx8664.150.pak b/INCA_libs/worklib/inca.lnx8664.150.pak
index 5b867d1cb259698566d3235361cb7c7cf6cdecc4..a7d9bc53de42eade285367f0d39801a2015deac4 100644
GIT binary patch
delta 11781
zcmbQX>IU=PRX3P7>^aU++8*5_WN&a`^O55s9L$qBx+dQ~Z^|-trPadefz?7Gn=>w~
z;FO%q(G}0Yz`$Uok{=18t@q9mW@BJraG3s(i%Fa(qePMgB&<;`$uj-lVK)f@5O2m7
zA+YF=Z9>SR?;vVtd_+;(CjnL)F-Zbh?Jse#=#0PONTL$bVqnn-88IZ$3PXrmiv=iZ
z-$Ts(@e$eF4l{@wR#+grp+a5?Y_5f>6q30fpX9)zFFwg3iO#qJ@ms`IWWQCMhlomC
zKo;H6V+A%r;-58=2`>&PfkjswR6-K%a5MsoW;h!miSCGoi2jH{7M+m}5v|BT7VRj2
zh<X$mu}qe^E5oy5i3Qlm6{{^+Cf6*I;kmICqGHBMBZxqU3`D>~5h`%P!4#||!`&3D
z!i=L$7A)Y=0ii+B3&t!AVDTAZU>-w+ft*%)Jp+TqYz3|K`pI&OrMY)NjJmNCViXSt
zlMPsl2D1&=Y@QAth=7MMRNzKEMBqk?4a?*;_hd{MN+A)GPywMKb}=wO>}FuNAp{X=
z*vktx`ok4omdSta$r?|{0=p)ovj9v(R538H2{0&t*gwF@l!2k48Dj1NZ)ujvKKEr!
z3ZlU3J2pjwX^>hFW)onr0MQ&UeF;He`32v?w9+Tfy)R?jEDd%*$36%RQVhau0t_A?
zIs&G#Sq7|*p+$ye@|*jzCIMbxgAPDxkXjIC7hs40(JNs39Gt-F7#y9n(kI(KkTLNw
z1{?H3(gaL{6oW9E00Rez-T(_311qq`3kFeI>63dO$QU;yfdwW=rh;jZVi0CkU@!pD
z9lRitfgvFal1epNlvpO;c_72HpamlEVzLs;WS>_uJPTwX5xl{~lx4EcLmBP|?ht{5
zOw-A;U&-<?R6_U;t)LX}P?qPzA5Bmid11_{l|K3HD`}nw7LfF(VQa)P`OHIEE@nsq
zn89H)+4{9C&jDcw|AmeX%Ve2HGTaV*=3wu395tWZ{aTiX<E|N)-*DHAWpd6VS*{n{
zV17a!@8sLB<+wjUxDB6$Stjp!B+F&T2bM0d<D0DgMwVyBB#8YR78<ck=6Nj3y8x7W
z85lY^v_Pr2?u`@=hbhDp1rDYxlVcvsaPP>32+XK3oqYO@EYFHo2!BGiDa+(Fk7aob
zB*6juKtWC`eX{IZX`UIj5L+r7j94cBc`U>I<20nSNH`}nIs2^~w=Tq&C#-E)Ci^^*
z;eK%x;>#CL%qQ=DE6dYS4k@)dUP!V`p7TVO>$@n}8wwI)leyo?^8EM+k<XBnVwo(z
zNmPg%5{Ek`LCQdmmlBhsLF)cON=gAU36{w=Pi43zY#<6UIwU5qekaGXpa|^r9o2h4
ziRGy@cf==%f(ir4$-m#p@^Dx}Y)Z(JWSM;DsSMu?RY(pxQ3#?ZPgIoR`|%Cpy9eJv
zG)RcsVjINb7u&=q&wek<<1twT>;Z%MA}o_@p2=``%!ddFtQVR5`n@bq#VSZ*yRZqA
z*jCAK@7M|v@Ytm^+4_SVj{_&zr5=U?pg?{u&BJjBqCn!963gVC4>CL_oFSo}5n;qK
zIp?_yPed$4ARxtvW%8X5GCVgjAOaS-Ml6%}JeTDzg76ipj94b?eAJmN@Pdb>ebM&q
zlLHwQxIDTcC7?s^^gu2)vB?Q9IGBFeOb=9MlbbA1&7s2pl{bQB*%OI;%%Es!fQp0I
zApFC|jHP+ci}pP)7~A)}U~1p<g1LRq3zqghFIe06ykKkJ^Mbv7&kK(BJuf)h_q^b0
z-}8dIea{P?_B}6n+xNWSYv1#NzkSaOf%ZKw1l#w#5NhA^Lb!d;3z7CcFGSn-ybx>O
z^Fq9R&kKq6Juf8N_q>p5-}6Gcea{P-_B}6T+xNVXYv1!izJ1RNh4wu!6x;W_P-@@v
zLb-j<3zhagFI3z2yijZ3^FqCS&kK$AJufud_q@<*-}6Gdea{P>_B}6j+xNWCYv1!i
zzkSaOgZ4cy4BPj-FlyiP!nl3U3zPOeFHGC_yfACu^TND+&kKw8JufV`?|ET$=V84k
z7s%fX3|h(CB0n~5d@z4^S8?t1hDlj2+3<Enh6+SY)5De*ov&XXYdtvW-t?<izg+!&
zWzXe(x4+DPb8AcMp2^pD++KHh*@->pA53`E`@HGl)LozV{@eec=V|+w+nWw-z5R9O
z_x|mT+nd+US=qj|b@kC@ov-@p|6bmIZOhaxv$o9s)bMro)|=bUe?R#B@Y_2tkAFS-
zy7k$~Rp<6j{y*)@)h}OePP{tveBYfrfA4&{yY<%gOMj<5y}Y+)>#TblFD*Z{{@~VQ
zFK51PdDs17&gNfRzHfWk`lj#irQIj@T>3NNU)#QpeO*hYF6i6Sv*^tFh8H~#&h5Cl
zx@&do>iU+q^Ix^BI=14%i+eBbd^-H?#;aRjX8pXj@7A^%@B07V`TO@m`-xc>FD^T|
z`@){9+qcj8F!T4kXOnhLe==#(&U>p59eUaRr1e?rgUJt0@7y`*S?kL~+b%D-vhDKT
zd)sFIow4G3!>7rQCx2^Mb#L#*i@)amp8I9i|0_$b?Y!6cyzf!_u9M5^4{SNS=)%@n
zKc{_~zVqUiGiM&IdAaN5iubF2{=72v+SCip7cTtn?EE+JamSP1_Xn3A__*%wri*<)
zyI;+E)&F<V#ieH!&VDg(-rY$Drd;ei@@2#0v-?h*cy{tx-@~4l$JX9^(YC#B;nS{{
zb3RV_)%W+(q6_=4Zn(U><5mCjwhuGEHGiD&r~c2SKbQYr{xk3Q<WDVco4&U`>F9Xb
z_;}CN-RD=`*nMT!m5rB{b^Pw_ebe%6=g9>(_Fn9J-1fTVTmQmKOO_m6dw#;B=644+
zA3eI{%({<FU+28&e%$u;_KJJ=_Mctwzvpqoy1T1apICl%;gLNTAGUs5d34p;CC6XR
zdh@2^?VaWi^ZzWqvaJ62_T!5#{OkSwyYt1Q7cCFZ?>Tj9-RWOTukF0m`l;dJ#D^{4
zR^D27d{xW$#>Vvx>yNKEx}g8b^o8gD9e=Ur@Pey5?ruK5W%lct-{$<B_3q%-3yZIB
zy|C}@)~&O*&e}3->%k@07av@5YURO$9m|d^Jh|fD_8V*O@4NJ8|A$52Hosmr?Na0V
z`bTH>pL{;?@1(D{x6Sx6>(Q+@x85E2c;w5iHTPGqespHt>BWb(+}(71>y;hTzR&-=
z==9QyTaGO~wdB<LGdrf;{@V88-ijlu&phg1cy{sa$5$U;|9Rr?*~e3#O`3H3>-0~v
ze)m4<{@3%ias9bvM`pin`ZfRanuAMDF1xa}`P_raPfzc?xbLR=_gPzRY&-Yuz_&wh
z?!LJ3t>JTf`?&{A&->ra_&D$N%pX&B-QIk$@6X)HhbQWCz3aKW;QGE(D-SN2+%r+P
z{_?(ulm5=z@b~h9Yd`uP^}af?vi)`I-=m+8e!Tzg_UogY4{X`;_wvRod+x42wD!iT
z)5|+wwSI4YHt+M{<yX3&cf4<Vdb(}J?X}HcXMUTwA32vy*mq+0`SWcnPOU$_?844#
zi!W}t^J&`WLv!CXKH7U~$IX>D_ndpMw)sPS+lqUe?(UlM^ZM?qYo{)ry0Cv=_wK2W
zCp>www)tVpo8I4({&xJD{r%?ZQyWe#JN$M*-{0<~m-k=TKJ&}1Z8sLoST|!$)8@8q
zGv3X8`Eo(u&uLHkA9uYtw&?h`mAAHD>-^XAcJAAbUrVnoI=!sp=<6Bp4s5%%_0pe-
z`!DZ3`uFtTlh3a`p8o%=HAnrN&yBCz-uEs(zG(89{TDXBnf<ckN5|Xw2R0vHhid1m
zNeibhp0@bl*XcX2?mqnc?C<jrFFd{ayW?S7+xdsh&-&ia{4oF3jGt3?-`~}JW%-HK
zUz$Hocrf8>`^qP$cAkGY{r8m5cQ?#ickS7Q$JZV=?Ce~Adg<M#m!H;O{D1EE>8I2F
z&zN!X|J)xFKDNJW{L=Qkd+CvFw_Co?_<eQ8wxgTpzHWcfzwpeXORHutp0f7b_jA9m
z?!3N!`oigpd-rtioc^Tu)vLw5@4Fr~f1UHW?aS1k*Qea>ygTDS@7|xQT24Nn^61R2
zYdi0Kn7g_8_o?59exF-AAECb<y8&Bnue`hCz}mS#yRPoMw(-X9sW-m0e!jc<_=@un
zdlpT4b@xs0>%JF#FOID`vZrNJ%Z7RDXRT`aKJVwx4fFoY{5auR|AVQ|+g=@6dUpMX
zncthAP5D0K+l;^SULEONeq~Y5uW3K$ZMggS@b0c%_jlKK?YX&o>d)!#uRpy0`0SsP
zKd&!2yK2?rv+GYSI=uDH=3`r~?wtN@-k-%6H{AWaZ^GlLyU#8>x3c}!kuN>_Z$E0^
z*7W$||H*$__jd2?Tt02_<h|#XA2`st{OE!cEAMZ+x#r&f%YWy5nRas5*(Db?-`;oj
z@w$f3t*h^Dyti}uuPaaHtUR&uRQ>OHe`apKz4h$Z!(R`+zxVp~*S7Z^9S7g{zG!$j
z{olkV)4tE%dS%bO#*Z@|w7%SSd*9_f=eEzh@~iXz#pS1$9DdudZr-zNPcLk|`t-uH
z6H88Q>e|z_Z^FVUOS*ne`2Kz0giq7|&wJ7MZuZNLC#QDYTzqrug@2ppzMHY_z?#EL
zx}Kl>*|@#Fb<>5HH}}Jm1FqC?ecPFBxAsrG^QrOs&Gm=ZoPOG|Y}&gUukP+|+lFTG
z%eF_4R<}NHde!}R%J05Eb3fkScWuk-*`K=JH{aQKW#_desNq=urDsq7uG{<jcl9hf
zx8TNuYY(pcI{ok5gXTBbLg7>En;E|+e`{U+?8NS~kEi~e_VNCvIcu&wY<SqT`PvrL
zsJOTB>eV@$E^NKK=hWgeJ5R4V_M-D)^PP3)7xf%`Kj+nvP4_ll`!RKQefQ@BOXmJK
z`FGB`hBr;W4t+WF?Z(SHZw@Uyhb<MHT5@6Q@g=91o?dr$=k!}&+CSb0)d`RL7EE|?
z^JUMAoA0|&ljQS`H*c19zwCL^`gzvZhEJ3KU)*$e{q23nR?q(511d`H?X91D??dy~
z+iMT5JNdk8$&@#@Uv<Cjc-Qgnz?wt5nzl4;o3V1vnx=<+<YzEY{`xZe|Nm_>e$D?r
z?Lp_W$qyUe99n#F&*KUI=WP04e{s>3Up)`{UmRQAy7lazBcD&LoUn4vrh6Msd^q;u
z$gA7$?tPg22fb`KxMb?7o!7R$n)|-*U*GGQ+kahIe(`_j)2_FN*EMW7@#Eaz6MyF|
zM=hpie4jk|)|cit^S;jfFlo<?y*-x~oL}>~<y-Fb=hHtm++TBJ<DF0YCqA08>&$}l
zE81Qk{o1>)V^8Ovd#^f{omz6|$)zV3{+<7I>Ph>Ho}Qzx@s^q3TzYBG{e2T2pIvx<
zd;iY<-BXuLT-g7o|IeT44aXcMrW-IaaR~E4+l{cXr%4=L(<QH3%Q9w6-k2%Q0vd{%
zd|z8;ass2m<bo~^!2~8q8&X3YLd#9}>SdLm9-n5<G5y?CYX?Sw$qQY?nPvz~4rH_w
z(t!4mcL+mN&k&s)$SB67Au~CUQE&POCZ>pbS4N0bCX_CQ($!G94oX8*F)+-7^4CD=
zn@~D^nsO{i&1)zhUB0@|GY%yGA634d0cJq3eKmL#P8jM#bOU0X!@=@$IOGo%KrGP1
zA^$hC1gzf@MZTT^?trVO{J{!*Q4}EL3okW-<zZ2P?m(D)7F2%|lwJ#^)3z3Z^}hgj
znLuH|z`!s)?kX$y^!R2wj_J>CSPM+vaFK&)hw${qIw!U1@jD=*5=;+-r#F_ls7;Um
zY{xO#;F1IrhsgB6I7hYV@p|?g)5~sJOE4LTOb<Ngpf)`|!5(VVg-aYv5hBwY*<978
z$4|HCn9g>~T7s!TWP0N<kl`m`>Jlz<2(1u-x(7-%aDx)c^mrBrj_K1t+AfGpZ!`mG
zvvc5>{NS>L&<`{nC!jj=9XO_|-L{rsQV^Zq_zvX6RSq1}k3Fy!nA~uMgK387^uTZS
zYSZICIB-ng22yuGbb2G7v)c4{Q%A6fz+{1|9851nr#FUyM2j3bCQIB9;99WwPYE+a
z1A~Cr^u~G4YSa5SK_n(GxXQs~AvV478A$MlBgf<wHw3uKjOvzwR40f{Z`5;9o4!Gm
z2`n+$;2MWu2Xs6S>Q{yj(;b<Z#HaUHJAu`3?GiJd3evnmY<lB97q#jAd!0C@x81WA
zn0(+G2h$C)>49wyYSa6fojIm|yK61M#2`LB&<-SG4-pZV9B`dO5SI5~wn)HiaRwVE
zArJt~oG=B`H=gAYpWb)SnRB|^9czKf53X}CRR~RQoaPF$%!OmR*nMjWrUgRN8~s2c
z4lW!Jbp<y#m`(^y4_xM`Hod>ig=6}%`_>YIAJ9xsfLebBs%_Fu4nYZMu>f<y3aA<$
zSB~js53D7a9E7I_ih+#vbcM#vgqs{p8N!nT8P%ru_ql>2R$}_W-Fy<G!{pG3fdL*S
z2an+*50k?p7fgdkq!<`HM8P};dW@bIK<%Q&=y^Tz=sCm-P!c*+&%qDjCm@aNLPQ`W
zs|kcQfT}|t@P)`gNSL|^m^#Qfa6JQPAQ++qLc$a_Koug54@1KmRox1xI^=O<hzbY^
zGw%XaT>|oWa(z8S5r~8-`~g*nJj@J|hhdmH1?Z670>tn$RtI`O)gcc{!^~m;*$*?Y
z0ICpaxEia0Gob2_$D!c{f~GmPKzIkB>LO6ary+76l4T16*nWl=P=&~&)*uBi3{nVU
z3kZTp1_q?TY!nB=)LB5)ArEpxbV5j&x&%Rp{R|Pvqu-z)fv97EDeQn6h&(0^RRX49
z>NY^tAq|ydb>I!CIuBjw+!1IH9c&VmfEmaDE%TAa*0CBWzyr~UJmwA&fso8cAhZQk
z-3!=Qe7yu@auOoVzyMR209A-QNDos3qG9Sfpz4qY?NJ;EQ?~)C?g!FfKFAz35COt4
zg*TuIkp}r$7#Jo`R1_A4&hbPbkN4M4H*{kZPK8M!2L7?SA^@rmc|rhWISj)bQ2|v)
z)I32w(mVlHTNgl0L!Li?*$ASUuYgDfh7(YANYe_a=0VkcfU1K|H?T6m<{Rpf<{Pl;
zl;DHd6oEVuft221E^&aWL!O?1=!B3kbs11~&{>Om2GFzxL<xk1DVzXRh&-DCQ2`-g
z>UKcYAy0BZR6t0Wx(85oE088X7#N^Q2c(qw%5?8uR=LR+0yw7oy|Lz){*1*&0>oo_
zAU)k%mJK2^4<r+q$_A17AU)lCEmY<mSmrC6#Pos^CQe3~>E5>N5IuHptvRL#wz5O?
z2*^zLJ`0uU1IaXsazJDhWTscga_CL(uXECzKH->?`t*K2XN}1RYB;8M)^aLL@1N(a
zF}?p8h|qJ<nBHFoBKCm@Hdl@5{eB=~nyUsQq?I{2fl+`F(&7U%Aq_h)6VliPF~RN4
z$q9^tOyJhO8WXq)uQoki&5mRG0dXb^$pmOmr2$HJ$bbTifgxi$|3_<S=2uH!PY-ls
zl2>M6K%Sh2sDY3iauE8&^!$(3($i}sm}Kf-Kuu|Y&SNsXhD=~WR5CDd$U;~Ro{)*m
z1C0<GBFey^0h5R7n*pU^@*XhxMG$=l9zkfRd_6-3Q~|>qh{Y068mfSy11jI}7@{%a
z2|r5ySOJx1cnT3Ocmttf`cJ^*<pjX`JX9exL|%k};RQ^A8bl&NcY5GoR&hl=2={;?
zgodbRV0ZxyL=U;i4~@k*IF>Ll$oqy|ogBz0QJ(>oYk<xIGkk{l38uFLCa-W-8#FI{
zK;a^ohRLsh$wT!uKxvr#37GtcJz#wYJ{$nkQ2EJGj9m6#pjN_YsGNs9grNbYAv^|#
z0w@FIk9Oh2_mcw|6%`Sa*5Dw6Dq&aw)!QLIJy6YFoQ;Knf&JF6=^ulcloW8Ro8SPi
zeqdmDF}?qbwKR*+&J*`RbDN3{IMz#KK-GIpe-Bdcy`*d%L_N~F37B(0^a-f?71RB{
zT01D<SZbi52vW<yz%hOOS8HjOz59M>LQKW6`l17>K4UunH){t4<h2(_CGHETsuR=m
zzgf#LsXU#WXs)Q#fMa2XhZ4jM8cNgkqItyF*#sB@RIa;Do){so0$LY>Sf&9{2O(EL
zb#*9BSCV70SA?$GKwrJVp$t*}0%3T<|1N>a8%-3Y8jx3VAUQund3pg`nb`Dy->rFA
z4kpa0hXe_ZWgZ;R>CzR`{eM`S*Pnn|*Z^JaaRN$1oWa2G0w(|94tNDd!vn}l446EO
zZZL$b7U_V}FmV{|0ksy!uYfQ(8F)$<81~ETUIcP97h+KcXm(s|x`P4}C#NiAg-*kZ
z>4863#ds9dAzCf=^0G`XQD9PKd3akpef#R4*3Qf<48OTqwm(s3TFb=j%EvN&iW<||
zt@$?L0$dp|Q$B!AnLclYEeFdET>+N%C+1AspO`amoeHyv!ESosZ&oouhX;^BwH?sR
zs{mTumfmi++_v3rxm~;6a{G3><qq5JmOCaev3N)eu(VIPz}`OP0!RCl3!Lp!E^tks
za)Fx_ZffcDKz24U0S5-i*yIjdNHI8BF;jeU0wX8LMO@QXxr*_@oeIuclLHxrr{@bY
zva{?ckz$!{a*?}q`u0_>=E4>;AS)v(61u<vVxTHIec>usvFYNgUBg*^T(oAHUbNaZ
zX1d;LS1w105)TJRuaSF)K3GddC&UO?kV=??g&BBWK;(DmS%b@s2aHpub6@6`oo=?q
zRbslrWo}L-rYT^h&_Ou34vTJx4ueCJAv&h5ag|`Th*Ho>pT2pGt96zHh*{6T0J9Qo
z3IhWJ&l`x-ER5vA%QIl|kicSK;Q0WRPeyg}ZHP-5c)md7cWi;ICR0!c54Gj3b>%?B
zeKR-;1RWe8rdogln1MlIav-Dq^!VfU9NQOM;oic+^uK=ky_?)d+dFP@voJaSuV-M0
zgt${6kdc7_#9s&DUpUPG;Xi@$8KCkYnt_2qAPB^te)cx^bRm#7Z-_Dh(D3j7`ssRC
zxwW=0xWk>n(H^$Xb$i%8w=FkWLG?+%^u{74;pq#$3G%e-&2Vqmo8i%}H^Z}CZ-&=)
zy&2vHe7x{P0xBt|XD{=X;eeK`VBc&%x6FGFlXQ0yI50i_KY&;aB0YBUv?gh#Pmez(
zsKe3$V)dUAltE{mKPBiU-3-(IkRigO`2dG!r`rOL9X)*@O$Mh0WmqPHSOFjw$jI#l
zrv)9ESbMm%)9XQbC2PCFIYACarVAF+1qIj~rYBSj-2*lMwg+4g?BLrjx6eCa10uD9
zi*Q(K=U@l<tDb>jdcy)CvG%%tq4v6d;q7((B0^f*ug&n=k%tHYP^mtBHoLzJ2iOQ`
ze765%_uu}HJz$0-O8j%M$+231bhID#3}`>>8Q6Z<GpPNrXYlsJo*|#7qNwF$6BBee
zAPEXI1`B9y01n;h4u_>Aw%a`jX|O^#15~0<KP?q1!vS5X2QDw%rx*N|;^c*uKHwsJ
zav-CWk_AXTQYp?Rz>om42_CUN(*qUQ#HP=a4&~$kYhz%5nrQGxijxOsBB;Ec&Mgxv
z!vQVu!7kjMClmVP4BR&ycR}T;9IFMWbe?|pq_pw$e=kEh+RwcVZ9n%ito_`}@b+^r
zBihfsjBG#mGOGRD%jouVFJs!zy^L)?_cE^i+{^g(b1xIx&%I1+Kld`J{oKps_H!>&
z+RwdAZ9n%it^M4~^!9TvGuqF+%xpjRGOPXE%k1`ZFLT<@z07St_cE{j+{^s-b1w_p
z&%G>cKliez{oKpq?dM*Wy!g+QAv-<r7pt6+LxMHP_Y4Q_K$hh})>DCnz=Q*IxgMCq
zz`y{}C$?SgRp|#MLDyHMV2J~qV2Yt+`oa<>`RR7NWd)$+$<sITmYGg(GH?@_{)@Lv
zZTbY>GO_7qd}Rtu3=GpF_{vsHo)jTAeI8F4$8<UVG6_(-e7YrnS*h@3=o;pTQxMm^
zmA9HMC{QLl{T_c=5O}pD1A~RybccVXV$=Nu$|R<X371JtZ{R5tn=bdJlw<llu$V}h
z!E`<l_Z^7)rHDshx|m?uEU=||ze_o$pA#&Tn4aVXa-Lur55%ETLLi6om$6NE6Dl*9
zE+$YWz^%v1vk~M$XJ3Zt6NSo5QAOQ-8KyrJD)R?<%1F4(WV#s0Vm*+>^MuPJCWkXB
zFx>#Pm*l2@6D|{&?#ae&F*$*eW4fD2nE-UWi-92+0;Z>mlr0n}0olgDzyJ$h02{H3
A^8f$<

delta 11441
zcmdnH>IU<)RX3P7>^aWCwD#@8PNq{+Hy=4J!oj@6p?dP|^QJ7a6^rgp4rFwloWRJx
zIpe|#&grT5tOYm^`$p!oF)%PVOn=D5B+h-pP>Pj-fq|jJL~8Qv1#(=4!eA~(iSXp#
z^JTeztcFPcSSJPHdrN}lclb*}_}eAG{2#j{CjXu<$8|#t%-wNQZ1U>`a$N7k!Q2_K
z5ZN^l%@OM%nqPc|@HxIoPS#!|$8{HC*NsO~lW#AS<Juq(*8F3GJXm%L#AP?8KwZ`c
z;m_!Y@K1PIgOzLSu>rY^=SQ6~n7^Z5nRT+yEm^MrMqqvgqcPa@X;AIc!P<E^RE)vW
zFI0?KC)eDO<+g|LJsgc$C(GQG;gQ$?(IBy1n03116KffsABQc#T6P?_fQqbm?g$pi
zc;g5adEo$YMTfgGRAfgKMC3;dL_|bvh8QRU7#JcZtPh`G&%j{udt><g`pI>Rq<A7e
zKn$$-2siMh9M}qu*K$w;XRLyVL~MkKXdHovXq<$Ih)h0kkHe(FNE)p3fhmNBSjxb_
zzye|25Q5MQwR~W81ylG~C;z!8Yy9Ci*jX7b86!Z>gQ{X+6JSsPv404FNCt)mXNb8A
zxMf(U7cTP_nVfK+)8xWyu;vb-w_qBglmVpK0>tKkX+H26EWaS^Mfm*5bMMO-JIjDw
z(NPDXL5e|`O@P4zL`T3hI?IC9F}TRGPQNG>Dl+K-r^$xfV8aeTX^?slW*1<H0MRR8
zdKX*<t7BMrIeh+P+Xph-Tqa<{UR*a}oh~R7Dk8c88Ym4DPJ@+RnD9D${^Z^VGR6-+
zg9Rp3ego4Wb3vF@fx!SockqHp28M>SkQnrM?#Md%&I1`9hGtQ)9UhZJStt9vlHqC4
zfFy_s4$7>Pbsoy_9PorhpF_4B>*P7FWOxo_Lj)Kq<X9)yJe1`L=mXpNV)Cr;`IFzi
zlHvXaN!urW8L>`2^H7$1Aw<KBWpb>OZC=ap9GGJVw)DkTJJ!iEk7RfnzCi>|=-RVR
z?s+Z4^W%>LSVh5K2iD0sk7T)*@qqaWHhip;@4S}fUI*bfY!qRgyyuZD_g`o#`OC*T
zS?7%mPe(DtUkjQ<Sts*6mgQyG1a@Rc#%^$Gej~**;}*o349|>MC&xUN;d$W>@%o7{
zW!A}O-pF#tLii5J%B+*uJeK8|unKI(gNF6t^C!!`mF9U-4#|Zls)Si5|9LFKQ_&3(
zc+e}%IyvX949|{@5Wia-kYk<f^F)TnVwEY_Cl)77Stsv#E5q}`1X9ktSSrOjdCn7A
z?(L95OW}qX>tvpHGCUFMAqq}hlVY7Lze!Y>8xofi0g&=4W0@rD<QR~`-H_6+;Ijnl
zWSgflJQY770w-K0StqY~C(FaY0?so#Zu>^epWORYnrFv)h#5EDO0rJ=^G=2*;~PZa
zfVLFt<U3Dg_$(enY|qdK<)_IL6{YxQxI+BY;0B^WLOe5yAvSrGNU%<x^InGMMKC1%
zFT{(oPOf<-!=sS^5!jF~$~yVYdl~MI3`pocC{Uj4y-JqnL@|UPQK8H_+2(^R&w^Rt
z(Ds<P5ER<arMV><ASyIklqYw8kmb3-2q_dR#Ee-d=RB9;J|PJaIG|uW`Su4{9uHLr
ze}$$o>*PJpWw{(7d<9SA$=V-vCkwpbVM*VazH@RQqXO58Q)b|ZS#V~0pfbDI<b)R-
zOfO=l2kNrRO%|x;&`E&G8$q+{i9|kTP((a{ii6l7{36DIwRz8r_B}5c+xNU+YTxsM
zxqZ(Imi9d_Sljo!U~Av=g1vpu3y$_ZFF4!xyx?lz^Mbp5&kLURJui6M_q^b1-}8dM
zea{Pl_B}5I+xNT>YTxrhxP8wHk@h_=MBDeg5NqG_LcD#?3yJnUFC^RdypU?&^Fq3P
z&kLFMJuhV2_q>p6-}6Ggea{Pp_B}5Y+xNUsYTxrhxqZ(ImG(U^RNMEwP;1}wLcM*@
z3yt<YFErctywGaj^Fq6Q&kLRQJuh_I_q@<+-}6Ghea{Pn_B}5Q+xNUMYTxt1xP8wH
zllDC?OxyRoFl*oQ!n}RY3ybzWFD$q3d0}<uVZ9a?$lnYMKH?{eYdE+Z*edy|#Z7#f
zvs|(ntW@$NL9z)dAd-RMVbk;OR~;QopDp^h_sh0z)3?poet*N=9n=5x@4Wu({)a8M
zcbr{tboKo;&7T|JwLEP4c5}kLxp$i1w>_D@<Kp6LJEr}b^5)8;D-X{7KlS9=vlGjX
zzUq8iKX1dGt=GR@|9Sn##K+TqT-$YJ&6Gt`7WD1!S~6`}$FtT|C)eKlFz4&^ZPTak
z`n2uWnz#G+&)Yw7-?g1rHqQInw&C9UYd`m1+IVE;nMK!@cKzyj-ut5a|Am>?r(ErN
z*8g_i#v7~dZ=C;m?$f)k@4h_#?eN?C?+>m&^SJwc^V-|HPP{zv>_q+ZzCWGMPcA*Z
zxqEN-{)r2w?(W<<{pYN$cXwX>-TP+V{(18@KUw{A)25@VZfw54?aGz^Gv2netUtKu
z@Pfn3t}g5S|NqL4i<_^lyY=z@np?L%PW>?L|HLo%*WcZAwd+mm%btyg)}G#fV&(09
z6F<%UIcL+Y{l|~LTK;I`qs31ae)@EO-rae(>pO1W{?OF)b=C_|IGtK|`q$EHJ8!jq
zYIr#DVavCbx7HnBHR18psn=$no`0+9{QuoAj%_`B`0b&$t*_c2on3bIaqphiRqq-f
zP5(9jW9zq@D{pVPxBJGL=7%kBdVf#)+wp7m_wP5q-}rXp`_vCJe)d1>{L}Zox%pAo
zi|zL|99ejI!~Ko*_jlb~+x(%e?Ro#(O@~%r-gc|?Mel?Dzb&h7u3vv{*^${VJD#52
zaqisu<4b>a{+s@|;YIJi3yZH_-EwU8m-ZLkORp_haCptVRp+<gde!%L(Yb}k)}MJa
z@%i)SXV*J^Px-#${@OEp&aAxswe7=)rpGfM_rE%_{oui+2R^R5yXj)z&+b>Vru&_-
z<_PQm)77=4d&!x_=T^78pR?-7*E5fopICiw^R*pk_D^^)>F@MU6Q7>icYDR1eYdw>
z+qZARzKQ!M?mM;q&Wcm(4=y@&s(J1CRfiT|-E(=_m900wZ~49Q?~Vs+=iZzgHPOKB
zz`9%e&#pVT{@{}1o9ABm*ZceG;`0lRzie4`Y{i8a_g>ujbokq`7xUiEoO$8joSzdv
zw7qZm+WxF-$<ejvCp_r<IOWIkQ|k|{y+8TM1cUnT(|%u_vF+&Qxv$$_^e;T~sPDmy
z1=AKx+10(TZ^5;t7cb7(c4gzu9p{#x*n586p*Oux+i$GCv-RMjQ|s@1+CTBplwD^Q
zoL|xQ`sm8z``b6RZ=Snm=F0YuP2axlpZIy&zxgj4-p_i``SkRv8(Uw^{5Ey>w;QYP
zer|o)_VE0oo(Fy3&iy!7|Le-r3lGliIK6-Ww;Q|eZ@;$S<g&{P53Ff=*!QR7?bIJ9
z*4%G+)BL3O-GSc47nXJWoAh_qmYd&af9>7cytQ%tyw$U}9^P=|Nbll<OU|slz3J|X
zTf49SocrVCw5MG!w;kMkY0;(aM_(`N_}#ns>dtE$=YP7h;oh=&E9R|g+1jvS-iz7q
z-}^1=c-8;B?ZeD(%^xTHxwPQm?t^PjJX_uRtzq4bEw}ef`hRin<<*myPF~)*qj&G*
zr_&xiTHX3-?)#P(jgQZ+Jo9(a#eH|1zP3M`_N@8iy1Oe6OlLc1tx!MxN7uvNCv7Xv
ztekOt%k3S{Cp>EY-280H=^ba5qMH41=Bha>=B_yPZ_cKB8%}&U_Tk8@+wbmuXnxh(
zd*oHe+tw$OeouKg`O~}&S2i}>UvqfD|Bhd?U(f#6v*`W7O-EkM`7r;-wcS&f-hF%f
z#oZU(o0`@fSa<E+jd%68z8w8<;N9FWlPBN$GVSy1Up-H|{`bCVSa*K!h5kR2Kir$V
z_uP(Y4|*QAtUCVk=E4ap<}W+?=jexfo9--`vue(Yw(U)u=Dcrv_;5wrlg5`F|EB-w
z{Xg&1o%t7<u1!AOw(Zlx{zGr(zdXM2?xw51r|szYaPY&)4@Z|xLFli?ZovKvi>_@x
zy=>a2#(SIY?z+5T-sQi2Kdvn}v-rrX_LVaqUVGm5p!IR<<FgCTZ|~pPzkBMEi3|Jx
zO#Sp}_tfu`e$9T{@_OEz-iPPc9b58y(w~mE^Z!i#JNetxhv%Et++W%Laqg$7yRZE?
zv7vF}l?@J!+b?aH_i4_PJFo7%IQIR}r#tJ9EnN8G*ph=QPwczC<Lv%>o96tT`hCT%
z-Pe9>o&93ohGVOaF6w!B{(t+H3om>2cD|TwIz>fp<FWO(cU;(d?8VaVAAJk1?Yg>Y
z&d2-jr!P9Z=-`K`-zR^btWy7L^6S1wdoOIgvHj?tN%ucCeYv&f!1@!<x|dFUd-vV#
zUH9JIetUTR!JUoU8@JA0HGh5Mr`do0Y@Pjc&X=i=yPi&X)cpS7=1VIs?YsST$F!%D
z_nuyUVtwPAL!Y|#^zFR;=+YKgbmEH5JBfRb@4dKX*7cuVe=aRKvHZZh=CyO5UVeCO
zOYdGZiy!sAe7T_SP3OagZ}UI2exLU1%GSI4A58e!_@v|duKSzru161u?JXNGY-!mz
znR%+pWbr9Flh02Pt6zF#W&5co(;uGSd3D#_&+|4k{5ZXS+UG;xrZ4S&-udz5|C4_&
zKf3<><f^0C!usI)+xyO}Kd|n=(qo(ET>Rhj>k6n`ebKsl_Tx*B+8<wf(uf-IZ<?P!
zU)S)c{e9n$iT}EP&iHbxe&@9%7q*^VFyTu(C}&>XHsk8=j(-=HomzV6P2>9c&o4Y|
zc-H*1`RVE9CpUKP@7z0i(e&k=uUg4Z#-LREf5Mk9dnbRK@@MYr`lh!tUUfe|x#HIL
z7qh=i-}&X%%KIPNU$;CyyP$91vG3=999%Se(e#~HcOU+J_V@XR7oJ}IJ>xri4m`Df
z-oZ_G_dT5Ur1fj-gGqZpHSCwBca6_ZEbZQX`18?khrdl-gIX9&{xf67#s3}8>!<#k
z^n2#^%iG#-tUj{*NB`eBZ|3~$zOwxCuIoRy%z8P0<MGu;7WY0l_pfbh^Y*6gS06U7
zJ-Gh*`<w4?e?9W?;QOA(?d|6t;4PWJdEw^vD_dv3IJWA@o|a858|JN_wW{TN%lGdL
z4AZ3;ndF4ub3$58uvXL(hwAATSFL3k6DDuW6lXc?8<{`7@T#?oU<4CHp@KMsmYZH5
zXD`n<WBRkJ*6xfPlNY*(Gffbf9LQ)VqyX(hZV-kjogg|nkWq|DL1uCwqu%rnOiT`p
zeA5k?nZ)b87$GV`pmYqBj)&3^Sq6rBD8Cm<?}F0l)0AUDYR*9U=<?Nto^c@g2iWE7
z8G`Mr<3S3(U{}Bp;~Wl_|BpldPyxgOerV{RJK%3-30S`rR{1mrhO4Li!3y-SDqvvv
z4>iCMhx|+jhzGo(^2t!T4@#$PEsUS;dzMv(ao+TOH>~BEHV98&QRbw^cp1bMpDugT
znuF<v@bndVE^3T?)BSE*%L_4xfPw^pC$LW6lj<SH<jFjJ{|#%g>1#oHG(@H=HZjRh
zPGDqbte$@FrnNj%fXMU}|6J4<H%(W&Wi8KCAu@f%J|{J%C(P6HZ&}N6Er1(4U0=9N
zY;rs!$Ml+0JRH;a-m;cpIw3NBg`SfdW90OIx2)xbKEM@2+;M;#oQAqsCiCjbF-eF{
zU-8UQjq&L8zT4LFOcO+>SG==VW8|JLcgI?M`rF&q985bzr>|ghR$~kRiODlP5S_ll
z&smMJce3CO@#(d9tT~uC#HO#9=B&ne79=!z!Bq|>1F`8V?m4S53Qt~mLwq{#U26`e
z2(jra)LhgUBSAuw4X$wrHb6(OAnsydcro3PiAkJs8c4zPxgb3&#HO#<=Ay=UWBR$f
z*78gj#HLr&IjAwpO^>^0Ek0fMo;3&453%VLW)5nMQ6MpSL0FD~nJEA^lW7|J^z(PE
z#isAQXU!qt0nJq~HPaK1@`y7r+?oFFp0zwvfzb37eXeRuavamw-?0{(?t9;wgK37)
z^c8NdYK+m->+W02GaV3`UNO&6jcFlN&E5Of9D*;<jE#U;{hVVu{{w3|K>=tUhS|CR
zBCXCjT^?jj?gMKMCJW)|6?~3rj49LSJ+PLa9=L`Nlq@)zR&q}7zillx{qF;7j_H9r
z`6NaMUvUh+8rwsL4M2mhu#g7R(4k5PQ815zc4M*`P#b7ACM#Oc5Ag%?03k#KLb94b
zXbq@3<Z(lY41|QK3xKLa9!`X)fRHeC6;O5c$is{fB@hy(Z~;^y^5`Q(1%!mDI{{Uf
z5P&o)Sr1VIB4O%2K-D!s1}p0sK%<o)1uzU#C;=VsS%5T(2~z{2Vd@;9>W~LFLGmyR
zQ<ni%hdk!Vz<|Yt6QBx_hcaP?foPU3Ad-P$2UJ}I$`B_+4n)G#J%Fl19`^*vgE7c{
zm_iOgun+_Ccql{!Lc-J;K-EPcjgvxDKuDOn2$(wL@l%k65M>M?bzp7-R3Y-PDpU=a
z0x1MBRzTGukG6uuVHl?F0#qIHAS_G`h=!^AAqWkB<iS~x0vLuV<lupbAdlHXL?9&d
z5eRJnQ-?H`3z314Fm(}7brI|9A)~CIF<yug2nkcz09A-Q<_l2)Az|uPK-EPc4Fy9~
zKuDOn3s80N5#oAR$ha>=83O}M;SZ?72;`w-aAZML!qh21Cm4_ilp!i0But$LR2}j-
zGf0IRhyY=j!UCv53u4Bf>ygKwL8ibk%(NL$(~yUyVQN4$^A!-uz;FPn4tca1A_E~|
z>Rv$AK?ku}7@(ur^~j^x5G@cArcr<o!jC{6-9`>is6#BE>X62~!K2d<-3$yc^Ae!y
zpkv|n44}bqm?97jQ`iAjh%`oy)xZr<b;x7qAah_CX5I~`x)q2qbyfxjXlel|X1+4L
zA<kZIvVk85(*^124a*?x>Ar8QIi|P0vzGwNJdmE=VCDc(^+I}jLmia;L3(mwh&ZVI
z3Q{)xEm#wuqr~)rdL~XrnduE-j$lpGZQp{7o975IPC#b*hG$TjUXaW-JtvLn+sZ)1
zJ`lm?tTBC?ABdO+BJP0*H5ZNP+wwrfHW2X-M7X(XOyAb$s=)|p>`hK!6kvojzQ9aK
zLkrA=v@k(TaGP&(0;Aw`Q{gg!$?=R5OyGvGT0N|LRsn7I&w$c9p!5wW{R2u%fM*sM
z7%ZT41eC6T(hV}85N2RVfYJ~i1499{`^P50(9yp)KN>1NT{4(S${uMV6)Fy)<RH`m
zG_xK|h4iX8mM}0lEV*}kav-Bb{R60?2Izbo!%E0J9K;9)1_oIOtAU*#oVpI!LuiO7
z1A_ug9;$B!l!nPWK;;<{A^IE^LTIRbJwpOa!77Nw5>OhdfS~~<zX+mn!6E^$Ltyd?
zVDgJ0;wx4`Xqfx~nEV}xc*A1|4UrdNV0Zvi@B|{!@p^jTUp8^YHxO>Zdk76t&%p2i
z8oCa0lOGz3aexBz!6NOW;J{3P$~8bIGZ{8Q`~=h60F!Tsiv&$|A81Gd(=ho3FnOrH
z1}F`aKLC>t@B`~R5D)~Wq4JZX7`f~=L9K+*P&o&A2txr%LwF1f1yBaaAGSMpPyd+6
zq-2LQ_X?E;QwyMa8=y2;kb!|A0h)+GGyOM|zf2blW>R#(xf}pIsn5Xh0L_pWKOoTx
zn)bg`)_xr{g(ua3V{Jf!!u0*&K4Sa|Cm?QM6JXE?@o$)Zv4BZY5qY5iL>fXKfZDuZ
zdf8WN2MHV#><ZHb6`8~ZIGiAvg-w9L;>GRzmLTUSHsDxo(4YvhAz`}NH){tw<h2G!
zHNgX@ssm6OqKAQj!y3W@Ej@5HIY0d%6O*D+1CI3x4oVQk3QE)UqItyF*aR2?w)~$S
z_?B5ou>onV0z?&rTmaS6Fg@(MwSyvb)dKqJ1qNk^>IV>$IoJdk5=5O>tp@qrp#ga*
z1CpN-pqd<@G{gu7hK#ci7MlPAhh4tU1dt($4M@u$Akt70I+eI!df5+a^ZEl&vtVl?
zPC(a2Kov7QfXO@Lf#;JO93UM7m^_Sbm<U-@(E+7l;xO6)YAuXk0by`5@RTqxh;BOg
z2;^uk#KHy8%(2*X2L&b$t`&E9!Kt-j+4R7lY+}=ESGjVq?5N>moxbv?wJM8aZsh#!
zmwsA1GqX(C$-}x`@~`z8CYFX>JgnPK{<l^UMCe}!*3aYM0I_?=YXR2jf&Z;V+JBfc
zZU14;ykII^EyLgGfxp?rroUZg%gMZvhjqH3bg0kt4R2W#+tZfYwx=z(YfoEl-=4PI
zVSCzg$9N`|j++9k?I%|{wx3+-)P8cMbNk7aF4Ir0bY+1X*<dt1kb_-p`rDPRoXmgt
zSf_tn=B+aQ#RYB!KDZCTIdF0yqww^6K}HT{BWc#@nX6oVSY}8|uuk8($~6YuXPz#(
z+Es={LQH~n>O>on>AtI7Js{#USG&frc&xTzo&IyRtIYJ$RjvZlRoA!*Oh0gmn{&F|
z8dq~J4k;UOU>Yz@w_oEb#**>VnsxfjHLf<SJHBrWpFjQ98dq!88FrvWOAHJO>X49v
zkvwl8J?R^4Af;AoU8Sc#xXdjuJ$0?C0M`l)h{+1-pwX=93Rk$1qRtuO_q}UfIXS?d
zWMEL39LQ)tz2_AV$MywRxVNw{{i&aR?<Tj=_P?84S(qIE)H5)E=e`*j1Ogcu7(o1W
z5Qkhi%>dy)f$|xk@*tXlfk7Y$#GiilHurQPkT!3KGJ!gfaQ$?>tK3@K7u?~_;ApSi
z=eoUipWBw3te_eqV0vQ_lkoHf-voK4@43RwF<oIFuRwe54EOfj86NGqGd$aKXLxPT
zo#8FPrvr~NXvqe#0zo=JJG2(g(yYrjF7sxVehpb;<njLjLY2o(o~NI~=TDD6C8)#l
z0>tV+B`AZ=I)6&gP5LoR`$L8ZkLCj$o}F$BJa+WF18FiiEhxkC5yT1ru|P&{FE}me
z$i(_)cEtR8=)ytO?F#1vIT)E9e48#P!0s?Pfzb>Nvw>QR+XF5LcJOU?-RGUK0g*Dn
zg)uy3vO|46y<vfnSbJT+P<vg!@b<cX5h1PZe`omZ$TNh8543zn_!+`-H~<-Zvj7_m
zO%2;C)I<w-rk_3M&Cxzr#DDu-kpKl#L<Vx69>~cq$7%sGvi+53K>I7t!1h<3LG7<R
zgSWr(4Ec=6zYWgQ1G(76rvJSk!pZC`!#aKAGH;jZ4u_>AroWX472IC-ASB-k5sA=J
z8sanr>A)Zb=2$q(f=hr9M0kLU=*fYMQc4zRnn6W5NEbW=xTXgxvWp2iI6w^pYlZmO
zb-LakDK3ON&<bCWF(B-a0M*K6!n!?BCe-FEJWzi80hN?;tQMehclz0r(#Gv?Uxv27
zeHqsN_GNhc+m{jTZ(l~XzkM0i{`O^b``ec>?QdVkw!eKD*Z%fpeEZv%3GHuRCbqwQ
znbiLFWpex5mnrRUU#7OdeVNw&_GNne+m{*bZ(nA%zkQk2{`O^d``ec}?QdV^w!eLu
z*Z%fpe*4>(1?_KN7Ph~AS=9daW%2g6FH1iBXIgP*df+cMx#@pjmU3uqfG$Qe0+&%B
z??AA@U&tag2#<jQqDgGK>#NcaN`i8)O2HBbpmR9I(-)R7$xlz^Eh_*mik*Igx6G93
zh4OTMzA_8O+{qt3M5o8{l_@Z7d_KLNuWSWW$d<oMfqAkI<MagnvQnuf(D{UjQ;<f$
zF?lPn9Tn=+-}9GcFy)3#4}4Q9GCfxSr0Wgi^a%oG;vmtL0%ayl`;4dG7buf}n#?O$
zrog<MhjF@rVA*o0*jtd;4DF2R0zzf7EdSrH|2W-HsLYI!W4ghcQqk$PLS+g}FLb8Q
z7b=rrWS?H}uT*sUS&*2A^7Qv0F|X+tUX_YYmlZCv0@-?ztxRP4-Z!Nj(@TZRB$zpj
z<EB3lC=-WTwpX}Jfw|h5ar(x4E}~Y`7;?ivez~CuA{iK*d?EA;C?CROU<h~xVM#!P
tb&1aO4Lh8~rau)Z)0mzsQYOIvOc>G@I~fdy(|bh9777$YbTPnU1prLkL<j%?

diff --git a/ncverilog.history b/ncverilog.history
index e14c63c..a2b44ce 100644
--- a/ncverilog.history
+++ b/ncverilog.history
@@ -167,3 +167,6 @@ s166(07Oct2020:16:45:59):  ncverilog -sv +gui +ncaccess+r -y behavioural +libext
 s167(07Oct2020:16:51:56):  ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s 
 s168(08Oct2020:15:46:51):  ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s 
 s169(08Oct2020:16:21:39):  ncverilog -sv +gui +ncaccess+r -y behavioural +libext+.sv +define+prog_file=software/code.hex testbench/de1_soc_wrapper_stim.sv -s 
+s170(16Oct2020:21:52:43):  ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex 
+s171(16Oct2020:21:53:12):  ncverilog -sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl -y behavioural +libext+.sv +define+prog_file=software/code.hex 
+s172(16Oct2020:21:54:42):  ncverilog -sv testbench/de1_soc_wrapper_stim.sv -y behavioural +libext+.sv +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl +define+prog_file=software/code.hex 
diff --git a/ncverilog.key b/ncverilog.key
index 6e67483..a3abe50 100644
--- a/ncverilog.key
+++ b/ncverilog.key
@@ -1,5 +1 @@
-# Restoring simulation environment...
-input {testbench/de0_wrapper.tcl}
-input -quiet .reinvoke.sim
-file delete .reinvoke.sim
-run
+exit
diff --git a/ncverilog.log b/ncverilog.log
index ec6505c..e311f62 100644
--- a/ncverilog.log
+++ b/ncverilog.log
@@ -1,23 +1,47 @@
 ncverilog(64): 15.20-s058: (c) Copyright 1995-2018 Cadence Design Systems, Inc.
-TOOL:	ncverilog	15.20-s058: Started on Oct 08, 2020 at 16:21:39 BST
+TOOL:	ncverilog	15.20-s058: Started on Oct 16, 2020 at 21:54:42 BST
 ncverilog
 	-sv
-	+gui
-	+ncaccess+r
+	testbench/de1_soc_wrapper_stim.sv
 	-y
 	behavioural
 	+libext+.sv
+	+gui
+	+ncaccess+r
+	+tcl+testbench/de0_wrapper.tcl
 	+define+prog_file=software/code.hex
-	testbench/de1_soc_wrapper_stim.sv
-	-s
+Recompiling... reason: file './behavioural/de1_soc_wrapper.sv' is newer than expected.
+	expected: Wed Sep 30 12:20:31 2020
+	actual:   Sat Oct 10 16:25:37 2020
+		Caching library 'behavioural' ....... Done
+		Caching library 'worklib' ....... Done
+	Elaborating the design hierarchy:
+ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
+  de1_soc_wrapper dut(.CLOCK_50, .LEDR, .SW, .KEY, .HEX0, .HEX1, .HEX2, .HEX3,.VGA_R, .VGA_G, .VGA_B, .VGA_HS, .VGA_VS, .VGA_CLK, .VGA_BLANK_N);
+                                                |
+ncelab: *W,CUVMPW (./testbench/de1_soc_wrapper_stim.sv,20|48): port sizes differ in port connection (3/4).
+	Building instance overlay tables: .................... Done
+	Building instance specific data structures.
+	Loading native compiled code:     .................... Done
+	Design hierarchy summary:
+		                   Instances  Unique
+		Modules:                  10      10
+		Registers:               919     919
+		Scalar wires:          11159       -
+		Expanded wires:          122       6
+		Vectored wires:           51       -
+		Always blocks:           858     858
+		Initial blocks:            3       3
+		Cont. assignments:       973   11132
+		Pseudo assignments:       22      22
+		Simulation timescale:  100ps
+	Writing initial simulation snapshot: worklib.de1_soc_wrapper_stim:sv
 ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
-ncsim> 
-ncsim> source /eda/cadence/incisiv/tools/inca/files/ncsimrc
-ncsim> 
+
 -------------------------------------
 Relinquished control to SimVision...
-# Restoring simulation environment...
-ncsim> input {testbench/de0_wrapper.tcl}
+ncsim> 
+ncsim> source /eda/cadence/incisiv/tools/inca/files/ncsimrc
 ncsim> # SimVision command script arm_soc.tcl
 ncsim> 
 ncsim> simvision {
@@ -52,8 +76,6 @@ ncsim> simvision {
 > 
 > }
 ncsim> 
-ncsim> input -quiet .reinvoke.sim
-ncsim> file delete .reinvoke.sim
-ncsim> run
-Simulation interrupted at 35438205 NS + 5
-ncsim> 
\ No newline at end of file
+ncsim> ^C
+ncsim> exit
+TOOL:	ncverilog	15.20-s058: Exiting on Oct 16, 2020 at 21:54:58 BST  (total: 00:00:16)
diff --git a/simulate_wrapper b/simulate_wrapper
new file mode 100755
index 0000000..ef56a59
--- /dev/null
+++ b/simulate_wrapper
@@ -0,0 +1,20 @@
+#! /bin/sh
+
+if [ "$1" != "-no_graphics" ]
+then
+  options=" +gui +ncaccess+r +tcl+testbench/de0_wrapper.tcl"
+  shift
+fi
+
+HEXPROG=software/code.hex
+PROGRAM=" +define+prog_file=${HEXPROG}"
+
+if [ -f "$1" ]
+then
+  testbench=$1
+else
+  testbench=testbench/de1_soc_wrapper_stim.sv
+fi
+
+ncverilog -sv $testbench -y behavioural +libext+.sv $options $PROGRAM
+
diff --git a/testbench/simulate_command b/testbench/simulate_command
deleted file mode 100644
index 4dacb57..0000000
--- a/testbench/simulate_command
+++ /dev/null
@@ -1,5 +0,0 @@
-    ncverilog -sv +gui +ncaccess+r \
-              +tcl+testbench/de0_wrapper.tcl \
-              -y behavioural +libext+.sv \
-              +define+prog_file=software/code.hex \
-              testbench/de1_soc_wrapper_stim.sv
-- 
GitLab