x2go push

INCA_libs/irun.lnx8664.15.20.nc/srv02749_114143_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_116463_cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/srv02749_116463_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_121124_cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/srv02749_121124_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_12162_cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/srv02749_12162_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_12818/ncsim.args

+//
+// File created by:  ncverilog
+// Do not modify this file
+//
++libext+.sv
++gui
++ncaccess+r
++define+prog_file=software/code.hex
+-gui
+-TCL
+-MESSAGES
++EMGRLOG
+ncverilog.log
+-XLSTIME
+1600165753
+-XLKEEP
+-XLMODE
+./INCA_libs/irun.lnx8664.15.20.nc
+-RUNMODE
+-CDSLIB
+./INCA_libs/irun.lnx8664.15.20.nc/cds.lib
+-HDLVAR
+./INCA_libs/irun.lnx8664.15.20.nc/hdl.var
+-XLNAME
+ncverilog
+-XLVERSION
+"TOOL:	ncverilog	15.20-s058"
+-XLNAME
+./INCA_libs/irun.lnx8664.15.20.nc/srv02749_12818

INCA_libs/irun.lnx8664.15.20.nc/srv02749_12818/ncsim.env

+#!/bin/csh
+#
+# File created by:  ncverilog
+# Do not modify this file
+#
+#<< :  <#3 ncverilog:./INCA_libs/irun.lnx8664.15.20.nc>#>
+setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.20.nc"
+#<< :  <#3 FALSE>#>
+setenv IRUNBATCH "FALSE"

INCA_libs/irun.lnx8664.15.20.nc/srv02749_12818/ncverilog.args

+//
+// File created by:  ncverilog
+// Do not modify this file
+//
+-sv
+testbench/arm_soc_stim.sv
+-y
+behavioural
++libext+.sv
++gui
++ncaccess+r
++define+prog_file=software/code.hex
+-s

INCA_libs/irun.lnx8664.15.20.nc/srv02749_12818_cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/srv02749_12818_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_13786_cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/srv02749_13786_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_17142_cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/srv02749_17142_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_17360_cdsrun.lib

+SOFTINCLUDE /eda/cadence/incisiv/tools/inca/files/cds.lib
+define worklib ../worklib

INCA_libs/irun.lnx8664.15.20.nc/srv02749_17360_hdlrun.var

+DEFINE LANG_MAP (\
+	.v => verilog,\
+	.vp => verilog,\
+	.vs => verilog,\
+	.V => verilog,\
+	.VP => verilog,\
+	.VS => verilog,\
+	.v95 => verilog95,\
+	.v95p => verilog95,\
+	.V95 => verilog95,\
+	.V95P => verilog95,\
+	.vhd => vhdl,\
+	.vhdp => vhdl,\
+	.vhdl => vhdl,\
+	.vhdlp => vhdl,\
+	.VHDL => vhdl,\
+	.VHDLP => vhdl,\
+	.VHD => vhdl,\
+	.VHDP => vhdl,\
+	.e => e,\
+	.E => e,\
+	.elib => elib,\
+	.ELIB => elib,\
+	.viplib => elib,\
+	.VIPLIB => elib,\
+	.sv => systemverilog,\
+	.svp => systemverilog,\
+	.SV => systemverilog,\
+	.SVP => systemverilog,\
+	.svi => systemverilog,\
+	.svh => systemverilog,\
+	.vlib => systemverilog,\
+	.VLIB => systemverilog,\
+	.vams => verilog-ams,\
+	.VAMS => verilog-ams,\
+	.svams => sv-ams,\
+	.SVAMS => sv-ams,\
+	.svms => sv-ams,\
+	.SVMS => sv-ams,\
+	.vha => vhdl-ams,\
+	.VHA => vhdl-ams,\
+	.vhams => vhdl-ams,\
+	.VHAMS => vhdl-ams,\
+	.vhms => vhdl-ams,\
+	.VHMS => vhdl-ams,\
+	.scs => scs,\
+	.sp => scs,\
+	.s => assembly,\
+	.c => c,\
+	.o => o,\
+	.cpp => cpp,\
+	.cc => cpp,\
+	.a => a,\
+	.so => so,\
+	.sl => so,\
+	.pslvlog => psl_vlog,\
+	.pslvhdl => psl_vhdl,\
+	.pslsc => psl_sc,\
+	.vhcfg => vhcfg,\
+	.vhcfgp => vhcfg,\
+	.sv.gz => systemverilog,\
+	.sv.Z => systemverilog,\
+	DEF => verilog\
+)
+define VIEW_MAP ( $VIEW_MAP, * => verilog)
+define VIEW_MAP ( $VIEW_MAP \
+, .v => v \
+, .vp => vp \
+, .vs => vs \
+, .V => V \
+, .VP => VP \
+, .VS => VS \
+, .sv => sv \
+, .svp => svp \
+, .SV => SV \
+, .SVP => SVP \
+, .svi => svi \
+, .svh => svh \
+, .vlib => vlib \
+, .VLIB => VLIB \
+, .vams => vams \
+, .VAMS => VAMS \
+, .svams => svams \
+, .SVAMS => SVAMS \
+, .svms => svms \
+, .SVMS => SVMS \
+, .sv.gz => sv \
+, .sv.Z => sv \
+)

INCA_libs/irun.lnx8664.15.20.nc/srv02749_18045/ncsim.args

+//
+// File created by:  ncverilog
+// Do not modify this file
+//
++libext+.sv
++gui
++ncaccess+r
++tcl+testbench/arm_soc.tcl
++define+prog_file=software/code.hex
+-gui
+-INPUT
+testbench/arm_soc.tcl
+-MESSAGES
++EMGRLOG
+ncverilog.log
+-XLSTIME
+1599559888
+-XLKEEP
+-XLMODE
+./INCA_libs/irun.lnx8664.15.20.nc
+-RUNMODE
+-CDSLIB
+./INCA_libs/irun.lnx8664.15.20.nc/cds.lib
+-HDLVAR
+./INCA_libs/irun.lnx8664.15.20.nc/hdl.var
+-XLNAME
+ncverilog
+-XLVERSION
+"TOOL:	ncverilog	15.20-s058"
+-XLNAME
+./INCA_libs/irun.lnx8664.15.20.nc/srv02749_18045

INCA_libs/irun.lnx8664.15.20.nc/srv02749_18045/ncsim.env

+#!/bin/csh
+#
+# File created by:  ncverilog
+# Do not modify this file
+#
+#<< :  <#3 ncverilog:./INCA_libs/irun.lnx8664.15.20.nc>#>
+setenv NCRUNMODE "ncverilog:./INCA_libs/irun.lnx8664.15.20.nc"
+#<< :  <#3 FALSE>#>
+setenv IRUNBATCH "FALSE"