diff --git a/Msc_proj.qpf b/Msc_proj.qpf
deleted file mode 100644
index a5a1864b64015e786a43e39dc210d205d4e6ecb8..0000000000000000000000000000000000000000
--- a/Msc_proj.qpf
+++ /dev/null
@@ -1,31 +0,0 @@
-# -------------------------------------------------------------------------- #
-#
-# Copyright (C) 2017 Intel Corporation. All rights reserved.
-# Your use of Intel Corporation's design tools, logic functions
-# and other software and tools, and its AMPP partner logic
-# functions, and any output files from any of the foregoing
-# (including device programming or simulation files), and any
-# associated documentation or information are expressly subject
-# to the terms and conditions of the Intel Program License
-# Subscription Agreement, the Intel Quartus Prime License Agreement,
-# the Intel MegaCore Function License Agreement, or other
-# applicable license agreement, including, without limitation,
-# that your use is for the sole purpose of programming logic
-# devices manufactured by Intel and sold by Intel or its
-# authorized distributors. Please refer to the applicable
-# agreement for further details.
-#
-# -------------------------------------------------------------------------- #
-#
-# Quartus Prime
-# Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-# Date created = 17:49:50 September 17, 2020
-#
-# -------------------------------------------------------------------------- #
-
-QUARTUS_VERSION = "16.1"
-DATE = "17:49:50 September 17, 2020"
-
-# Revisions
-
-PROJECT_REVISION = "de1_soc_wrapper"
diff --git a/db/de1_soc_wrapper.(0).cnf.cdb b/db/de1_soc_wrapper.(0).cnf.cdb
deleted file mode 100644
index c08f0c5a4f6779f4060880068f82f15bb3f1b310..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(0).cnf.hdb b/db/de1_soc_wrapper.(0).cnf.hdb
deleted file mode 100644
index 8fc07a2561ee03ff91b2e08b0b2fbd7d911d6ef7..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(1).cnf.cdb b/db/de1_soc_wrapper.(1).cnf.cdb
deleted file mode 100644
index b2903d6567d688b9e6adcb76c9a501f9a8911bef..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(1).cnf.hdb b/db/de1_soc_wrapper.(1).cnf.hdb
deleted file mode 100644
index 35994e4e00383f980531adca8e12d47b1ffd8c31..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(10).cnf.cdb b/db/de1_soc_wrapper.(10).cnf.cdb
deleted file mode 100644
index 0d7f5c13c80f2a0b4a918c3ead2b29666ed46e24..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(10).cnf.hdb b/db/de1_soc_wrapper.(10).cnf.hdb
deleted file mode 100644
index 75af61730680edc8dbc7f991d94a3f31663928b3..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(11).cnf.cdb b/db/de1_soc_wrapper.(11).cnf.cdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(11).cnf.hdb b/db/de1_soc_wrapper.(11).cnf.hdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(12).cnf.cdb b/db/de1_soc_wrapper.(12).cnf.cdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(12).cnf.hdb b/db/de1_soc_wrapper.(12).cnf.hdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(13).cnf.cdb b/db/de1_soc_wrapper.(13).cnf.cdb
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diff --git a/db/de1_soc_wrapper.(14).cnf.cdb b/db/de1_soc_wrapper.(14).cnf.cdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(15).cnf.cdb b/db/de1_soc_wrapper.(15).cnf.cdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(15).cnf.hdb b/db/de1_soc_wrapper.(15).cnf.hdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(2).cnf.cdb b/db/de1_soc_wrapper.(2).cnf.cdb
deleted file mode 100644
index f0311f50f0473e2926da924c39f0d4ab55816148..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(2).cnf.hdb b/db/de1_soc_wrapper.(2).cnf.hdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(3).cnf.cdb b/db/de1_soc_wrapper.(3).cnf.cdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(3).cnf.hdb b/db/de1_soc_wrapper.(3).cnf.hdb
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diff --git a/db/de1_soc_wrapper.(4).cnf.cdb b/db/de1_soc_wrapper.(4).cnf.cdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(4).cnf.hdb b/db/de1_soc_wrapper.(4).cnf.hdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(5).cnf.cdb b/db/de1_soc_wrapper.(5).cnf.cdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(5).cnf.hdb b/db/de1_soc_wrapper.(5).cnf.hdb
deleted file mode 100644
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diff --git a/db/de1_soc_wrapper.(6).cnf.cdb b/db/de1_soc_wrapper.(6).cnf.cdb
deleted file mode 100644
index 62b6c714920c41183caf8c4f0d0df6e694bfe19b..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(6).cnf.hdb b/db/de1_soc_wrapper.(6).cnf.hdb
deleted file mode 100644
index 9dee2d6b4777af949be260d2eb90a0e56f669196..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(7).cnf.cdb b/db/de1_soc_wrapper.(7).cnf.cdb
deleted file mode 100644
index 9adb3a5a8770df66ed6783d8659a1900c7722864..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(7).cnf.hdb b/db/de1_soc_wrapper.(7).cnf.hdb
deleted file mode 100644
index d548d6bc103decbcc64d3c12f6fbe77a2a59bb61..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(8).cnf.cdb b/db/de1_soc_wrapper.(8).cnf.cdb
deleted file mode 100644
index 3626e883fb8a7238fd25b2ca87f8e57c0d107351..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(8).cnf.hdb b/db/de1_soc_wrapper.(8).cnf.hdb
deleted file mode 100644
index 3870ffd9fb8eecac63209364e7b4a98f36f2c3a6..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.(9).cnf.cdb b/db/de1_soc_wrapper.(9).cnf.cdb
deleted file mode 100644
index f39135f06256453441801ec21597748fe45949ab..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.(9).cnf.cdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.(9).cnf.hdb b/db/de1_soc_wrapper.(9).cnf.hdb
deleted file mode 100644
index 84204859beb1f25f5fde8cfda380ab1560067974..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.(9).cnf.hdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.asm.qmsg b/db/de1_soc_wrapper.asm.qmsg
deleted file mode 100644
index 1bcbb04c837690639f3c02da9385d78368addba0..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.asm.qmsg
+++ /dev/null
@@ -1,6 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1600361916725 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition " "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600361916727 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 17 17:58:36 2020 " "Processing started: Thu Sep 17 17:58:36 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600361916727 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1600361916727 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper " "Command: quartus_asm --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1600361916727 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1600361918005 ""}
-{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1600361928036 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1153 " "Peak virtual memory: 1153 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600361928690 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 17 17:58:48 2020 " "Processing ended: Thu Sep 17 17:58:48 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600361928690 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Elapsed time: 00:00:12" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600361928690 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:11 " "Total CPU time (on all processors): 00:00:11" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600361928690 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1600361928690 ""}
diff --git a/db/de1_soc_wrapper.asm.rdb b/db/de1_soc_wrapper.asm.rdb
deleted file mode 100644
index 08beafe7873d781ae048d269c576b7c33a2f6694..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.asm.rdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.cbx.xml b/db/de1_soc_wrapper.cbx.xml
deleted file mode 100644
index 17573ffb4dc61da1c6db756afd6fc95e808e3f45..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.cbx.xml
+++ /dev/null
@@ -1,5 +0,0 @@
-<?xml version="1.0" ?>
-<LOG_ROOT>
- <PROJECT NAME="de1_soc_wrapper">
- </PROJECT>
-</LOG_ROOT>
diff --git a/db/de1_soc_wrapper.cmp.bpm b/db/de1_soc_wrapper.cmp.bpm
deleted file mode 100644
index 8344635dc916a8157298a3bf3897500617c274f3..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.cmp.cdb b/db/de1_soc_wrapper.cmp.cdb
deleted file mode 100644
index e76826e5575503eda06df62580265793e5e99524..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cmp.cdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.cmp.hdb b/db/de1_soc_wrapper.cmp.hdb
deleted file mode 100644
index afa8498743511e34e63cdc9a4af03cad3f9080a3..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cmp.hdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.cmp.idb b/db/de1_soc_wrapper.cmp.idb
deleted file mode 100644
index a419d84a14586818fc82ece53aa4a826f10627b4..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cmp.idb and /dev/null differ
diff --git a/db/de1_soc_wrapper.cmp.logdb b/db/de1_soc_wrapper.cmp.logdb
deleted file mode 100644
index 6366904b391ab2e07ad267fab17c8a6d99fb25e3..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.cmp.logdb
+++ /dev/null
@@ -1,121 +0,0 @@
-v1
-IO_RULES,NUM_CLKS_NOT_EXCEED_CLKS_AVAILABLE,INAPPLICABLE,IO_000002,Capacity Checks,Number of clocks in an I/O bank should not exceed the number of clocks available.,Critical,No Global Signal assignments found.,,I/O,,
-IO_RULES,NUM_VREF_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000003,Capacity Checks,Number of pins in a Vrefgroup should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,NUM_PINS_NOT_EXCEED_LOC_AVAILABLE,INAPPLICABLE,IO_000001,Capacity Checks,Number of pins in an I/O bank should not exceed the number of locations available.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,IO_BANK_SUPPORT_VCCIO,INAPPLICABLE,IO_000004,Voltage Compatibility Checks,The I/O bank should support the requested VCCIO.,Critical,No IOBANK_VCCIO assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VREF,INAPPLICABLE,IO_000005,Voltage Compatibility Checks,The I/O bank should not have competing VREF values.,Critical,No VREF I/O Standard assignments found.,,I/O,,
-IO_RULES,IO_BANK_NOT_HAVE_COMPETING_VCCIO,PASS,IO_000006,Voltage Compatibility Checks,The I/O bank should not have competing VCCIO values.,Critical,0 such failures found.,,I/O,,
-IO_RULES,CHECK_UNAVAILABLE_LOC,INAPPLICABLE,IO_000007,Valid Location Checks,Checks for unavailable locations.,Critical,No Location assignments found.,,I/O,,
-IO_RULES,CHECK_RESERVED_LOC,INAPPLICABLE,IO_000008,Valid Location Checks,Checks for reserved locations.,Critical,No reserved LogicLock region found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000022,I/O Properties Checks for One I/O,The I/O standard should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000021,I/O Properties Checks for One I/O,The I/O standard should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000046,I/O Properties Checks for One I/O,The location should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OPEN_DRAIN_VALUE,INAPPLICABLE,IO_000023,I/O Properties Checks for One I/O,The I/O standard should support the Open Drain value.,Critical,No open drain assignments found.,,I/O,,
-IO_RULES,IO_DIR_SUPPORT_OCT_VALUE,PASS,IO_000024,I/O Properties Checks for One I/O,The I/O direction should support the On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,OCT_AND_CURRENT_STRENGTH_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000026,I/O Properties Checks for One I/O,On Chip Termination and Current Strength should not be used at the same time.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,WEAK_PULL_UP_AND_BUS_HOLD_NOT_USED_SIMULTANEOUSLY,INAPPLICABLE,IO_000027,I/O Properties Checks for One I/O,Weak Pull Up and Bus Hold should not be used at the same time.,Critical,No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000045,I/O Properties Checks for One I/O,The I/O standard should support the requested Slew Rate value.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,OCT_SUPPORTS_SLEW_RATE,INAPPLICABLE,IO_000047,I/O Properties Checks for One I/O,On Chip Termination and Slew Rate should not be used at the same time.,Critical,No Slew Rate assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000020,I/O Properties Checks for One I/O,The I/O standard should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_OCT_VALUE,PASS,IO_000019,I/O Properties Checks for One I/O,The I/O standard should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,IO_STD_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000018,I/O Properties Checks for One I/O,The I/O standard should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_PCI_CLAMP_DIODE,INAPPLICABLE,IO_000015,I/O Properties Checks for One I/O,The location should support the requested PCI Clamp Diode.,Critical,No Clamping Diode assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_WEAK_PULL_UP_VALUE,INAPPLICABLE,IO_000014,I/O Properties Checks for One I/O,The location should support the requested Weak Pull Up value.,Critical,No Weak Pull-Up Resistor assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_BUS_HOLD_VALUE,INAPPLICABLE,IO_000013,I/O Properties Checks for One I/O,The location should support the requested Bus Hold value.,Critical,No Enable Bus-Hold Circuitry assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_OCT_VALUE,PASS,IO_000012,I/O Properties Checks for One I/O,The location should support the requested On Chip Termination value.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_CURRENT_STRENGTH,INAPPLICABLE,IO_000011,I/O Properties Checks for One I/O,The location should support the requested Current Strength.,Critical,No Current Strength assignments found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_DIR,PASS,IO_000010,I/O Properties Checks for One I/O,The location should support the requested I/O direction.,Critical,0 such failures found.,,I/O,,
-IO_RULES,LOC_SUPPORT_IO_STD,PASS,IO_000009,I/O Properties Checks for One I/O,The location should support the requested I/O standard.,Critical,0 such failures found.,,I/O,,
-IO_RULES,SINGLE_ENDED_OUTPUTS_LAB_ROWS_FROM_DIFF_IO,INAPPLICABLE,IO_000034,SI Related Distance Checks,Single-ended outputs should be 0 LAB row(s) away from a differential I/O.,High,No Differential I/O Standard assignments found.,,I/O,,
-IO_RULES,DEV_IO_RULE_OCT_DISCLAIMER,,,,,,,,,,
-IO_RULES_MATRIX,Pin/Rules,IO_000002;IO_000003;IO_000001;IO_000004;IO_000005;IO_000006;IO_000007;IO_000008;IO_000022;IO_000021;IO_000046;IO_000023;IO_000024;IO_000026;IO_000027;IO_000045;IO_000047;IO_000020;IO_000019;IO_000018;IO_000015;IO_000014;IO_000013;IO_000012;IO_000011;IO_000010;IO_000009;IO_000034,
-IO_RULES_MATRIX,Total Pass,0;0;0;0;0;81;0;0;0;0;0;0;66;0;0;0;0;0;66;0;0;0;0;66;0;81;81;0,
-IO_RULES_MATRIX,Total Unchecked,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,Total Inapplicable,81;81;81;81;81;0;81;81;81;81;81;81;15;81;81;81;81;81;15;81;81;81;81;15;81;0;0;81,
-IO_RULES_MATRIX,Total Fail,0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0;0,
-IO_RULES_MATRIX,KEY[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,LEDR[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX0[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX1[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX2[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,HEX3[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_R[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_G[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_B[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_HS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_VS,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_CLK,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,VGA_BLANK_N,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,CLOCK_50,Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[7],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,KEY[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[2],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[9],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[1],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[4],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[3],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[5],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[8],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[0],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_MATRIX,SW[6],Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Inapplicable;Pass;Pass;Inapplicable,
-IO_RULES_SUMMARY,Total I/O Rules,28,
-IO_RULES_SUMMARY,Number of I/O Rules Passed,6,
-IO_RULES_SUMMARY,Number of I/O Rules Failed,0,
-IO_RULES_SUMMARY,Number of I/O Rules Unchecked,0,
-IO_RULES_SUMMARY,Number of I/O Rules Inapplicable,22,
diff --git a/db/de1_soc_wrapper.cmp.rdb b/db/de1_soc_wrapper.cmp.rdb
deleted file mode 100644
index 59cdd1d03dd885beb8b5a14938e1c3d302996129..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cmp.rdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.cmp_merge.kpt b/db/de1_soc_wrapper.cmp_merge.kpt
deleted file mode 100644
index b2655245e28f4e9497c334b21fa82de236c4b45d..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cmp_merge.kpt and /dev/null differ
diff --git a/db/de1_soc_wrapper.cyclonev_io_sim_cache.ff_0c_fast.hsd b/db/de1_soc_wrapper.cyclonev_io_sim_cache.ff_0c_fast.hsd
deleted file mode 100644
index fec2c9f4847c658ffed7135e24bce1d98cafe778..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cyclonev_io_sim_cache.ff_0c_fast.hsd and /dev/null differ
diff --git a/db/de1_soc_wrapper.cyclonev_io_sim_cache.ff_85c_fast.hsd b/db/de1_soc_wrapper.cyclonev_io_sim_cache.ff_85c_fast.hsd
deleted file mode 100644
index 647cbddbb117257d1c79e03f24166e5ffa114372..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cyclonev_io_sim_cache.ff_85c_fast.hsd and /dev/null differ
diff --git a/db/de1_soc_wrapper.cyclonev_io_sim_cache.tt_0c_slow.hsd b/db/de1_soc_wrapper.cyclonev_io_sim_cache.tt_0c_slow.hsd
deleted file mode 100644
index 6406a8fb5f5d0c7b15e3d6223d66b2ba38af89ce..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cyclonev_io_sim_cache.tt_0c_slow.hsd and /dev/null differ
diff --git a/db/de1_soc_wrapper.cyclonev_io_sim_cache.tt_85c_slow.hsd b/db/de1_soc_wrapper.cyclonev_io_sim_cache.tt_85c_slow.hsd
deleted file mode 100644
index e197f90d59b93576918a9c0c113c2fb07ced993f..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.cyclonev_io_sim_cache.tt_85c_slow.hsd and /dev/null differ
diff --git a/db/de1_soc_wrapper.db_info b/db/de1_soc_wrapper.db_info
index 7ce9828723537d02e1004f9c9316e3654a50520d..41e5984910064af4c7205fa697b271a6ce26fa5e 100644
--- a/db/de1_soc_wrapper.db_info
+++ b/db/de1_soc_wrapper.db_info
@@ -1,3 +1,3 @@
Quartus_Version = Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
Version_Index = 419482368
-Creation_Time = Thu Sep 17 17:49:51 2020
+Creation_Time = Thu Sep 24 10:40:14 2020
diff --git a/db/de1_soc_wrapper.eda.qmsg b/db/de1_soc_wrapper.eda.qmsg
deleted file mode 100644
index 226fd8b7ab04b675380fafacecc1bd5f35f33111..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.eda.qmsg
+++ /dev/null
@@ -1,7 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1600361949215 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition " "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600361949218 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 17 17:59:09 2020 " "Processing started: Thu Sep 17 17:59:09 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600361949218 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1600361949218 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper " "Command: quartus_eda --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1600361949218 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1600361950379 ""}
-{ "Warning" "WQNETO_SWITCH_TO_FUNCTIONAL_SIMULATION" "" "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." { } { } 0 10905 "Generated the EDA functional simulation netlist because it is the only supported netlist type for this device." 0 0 "EDA Netlist Writer" 0 -1 1600361950521 ""}
-{ "Info" "IWSC_DONE_HDL_GENERATION" "de1_soc_wrapper.svo /home/ks6n19/Documents/project/simulation/modelsim/ simulation " "Generated file de1_soc_wrapper.svo in folder \"/home/ks6n19/Documents/project/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1600361951902 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 2 s Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1355 " "Peak virtual memory: 1355 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600361952129 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 17 17:59:12 2020 " "Processing ended: Thu Sep 17 17:59:12 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600361952129 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600361952129 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600361952129 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1600361952129 ""}
diff --git a/db/de1_soc_wrapper.fit.qmsg b/db/de1_soc_wrapper.fit.qmsg
deleted file mode 100644
index 994d4250b56426f431e95c2970e38a178fe3fd43..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.fit.qmsg
+++ /dev/null
@@ -1,44 +0,0 @@
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1600361728009 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 24 " "Parallel compilation is enabled and will use 16 of the 24 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1600361728011 ""}
-{ "Info" "IMPP_MPP_USER_DEVICE" "de1_soc_wrapper 5CSEMA5F31C6 " "Selected device 5CSEMA5F31C6 for design \"de1_soc_wrapper\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1600361728071 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600361728109 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1600361728109 ""}
-{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1600361728644 ""}
-{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1600361728880 ""}
-{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1600361729003 ""}
-{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "81 81 " "No exact pin location assignment(s) for 81 pins of 81 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." { } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report." 0 0 "Fitter" 0 -1 1600361729125 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_START_INFO" "" "Starting Fitter periphery placement operations" { } { } 0 184020 "Starting Fitter periphery placement operations" 0 0 "Fitter" 0 -1 1600361742434 ""}
-{ "Info" "ICCLK_CLOCKS_TOP" "1 (1 global) " "Promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "CLOCK_50~inputCLKENA0 1667 global CLKCTRL_G8 " "CLOCK_50~inputCLKENA0 with 1667 fanout uses global clock CLKCTRL_G8" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1600361742816 ""} } { } 0 11178 "Promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1600361742816 ""}
-{ "Info" "ICCLK_CLOCKS_TOP_AUTO" "1 (1 global) " "Automatically promoted 1 clock (1 global)" { { "Info" "ICCLK_PROMOTE_ASSIGNMENT" "KEY\[2\]~inputCLKENA0 983 global CLKCTRL_G10 " "KEY\[2\]~inputCLKENA0 with 983 fanout uses global clock CLKCTRL_G10" { } { } 0 11162 "%1!s! with %2!d! fanout uses %3!s! clock %4!s!" 0 0 "Design Software" 0 -1 1600361742816 ""} } { } 0 11191 "Automatically promoted %1!d! clock%2!s! %3!s!" 0 0 "Fitter" 0 -1 1600361742816 ""}
-{ "Info" "IFITCC_FITCC_FITTER_PERIPHERY_PLACEMENT_END_INFO" "00:00:00 " "Fitter periphery placement operations ending: elapsed time is 00:00:00" { } { } 0 184021 "Fitter periphery placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600361742816 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1600361742873 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1600361742879 ""}
-{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1600361742888 ""}
-{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1600361742897 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1600361742898 ""}
-{ "Extra Info" "IFSAC_FSAC_START_IO_MAC_RAM_PACKING" "" "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" { } { } 1 176246 "Moving registers into I/O cells, DSP blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1600361742903 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "de1_soc_wrapper.sdc " "Synopsys Design Constraints File file not found: 'de1_soc_wrapper.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1600361744303 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1600361744303 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "Fitter" 0 -1 1600361744384 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "Fitter" 0 -1 1600361744384 ""}
-{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1600361744386 ""}
-{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MAC_RAM_PACKING" "" "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" { } { } 1 176247 "Finished moving registers into I/O cells, DSP blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1600361744816 ""}
-{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1600361744821 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1600361744821 ""}
-{ "Info" "IFSV_FITTER_PREPARATION_END" "00:00:17 " "Fitter preparation operations ending: elapsed time is 00:00:17" { } { } 0 11798 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600361745139 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1600361750203 ""}
-{ "Info" "IVPR20K_VPR_APL_ENABLED" "" "The Fitter is using Advanced Physical Optimization." { } { } 0 14951 "The Fitter is using Advanced Physical Optimization." 0 0 "Fitter" 0 -1 1600361751311 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:17 " "Fitter placement preparation operations ending: elapsed time is 00:00:17" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600361767156 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1600361791027 ""}
-{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1600361810474 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:20 " "Fitter placement operations ending: elapsed time is 00:00:20" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600361810474 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1600361812701 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "5 " "Router estimated average interconnect usage is 5% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "43 X33_Y11 X44_Y22 " "Router estimated peak interconnect usage is 43% of the available device resources in the region that extends from location X33_Y11 to location X44_Y22" { } { { "loc" "" { Generic "/home/ks6n19/Documents/project/" { { 1 { 0 "Router estimated peak interconnect usage is 43% of the available device resources in the region that extends from location X33_Y11 to location X44_Y22"} { { 12 { 0 ""} 33 11 12 12 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1600361826638 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1600361826638 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1600361889333 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1600361889333 ""}
-{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:01:13 " "Fitter routing operations ending: elapsed time is 00:01:13" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600361889339 ""}
-{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 9.69 " "Total time spent on timing analysis during the Fitter is 9.69 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1600361898060 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1600361898301 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1600361900101 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1600361900107 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1600361901802 ""}
-{ "Info" "IFSV_FITTER_POST_OPERATION_END" "00:00:13 " "Fitter post-fit operations ending: elapsed time is 00:00:13" { } { } 0 11801 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1600361911177 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "2695 " "Peak virtual memory: 2695 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600361914555 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 17 17:58:34 2020 " "Processing ended: Thu Sep 17 17:58:34 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600361914555 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:03:08 " "Elapsed time: 00:03:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600361914555 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:15:08 " "Total CPU time (on all processors): 00:15:08" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600361914555 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1600361914555 ""}
diff --git a/db/de1_soc_wrapper.hier_info b/db/de1_soc_wrapper.hier_info
deleted file mode 100644
index 77e52a45840b5972888c98c6d2dc33414039dbc6..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.hier_info
+++ /dev/null
@@ -1,3832 +0,0 @@
-|de1_soc_wrapper
-CLOCK_50 => CLOCK_50.IN1
-SW[0] => arm_soc:soc_inst.Switches[0]
-SW[1] => arm_soc:soc_inst.Switches[1]
-SW[2] => arm_soc:soc_inst.Switches[2]
-SW[3] => arm_soc:soc_inst.Switches[3]
-SW[4] => arm_soc:soc_inst.Switches[4]
-SW[5] => arm_soc:soc_inst.Switches[5]
-SW[6] => arm_soc:soc_inst.Switches[6]
-SW[7] => arm_soc:soc_inst.Switches[7]
-SW[8] => arm_soc:soc_inst.Switches[8]
-SW[9] => arm_soc:soc_inst.Switches[9]
-KEY[0] => KEY[0].IN1
-KEY[1] => KEY[1].IN1
-KEY[2] => HRESETn.IN1
-KEY[3] => KEY[3].IN1
-LEDR[0] <= <GND>
-LEDR[1] <= <GND>
-LEDR[2] <= <GND>
-LEDR[3] <= <GND>
-LEDR[4] <= <GND>
-LEDR[5] <= <GND>
-LEDR[6] <= <GND>
-LEDR[7] <= <GND>
-LEDR[8] <= <GND>
-LEDR[9] <= <GND>
-HEX0[0] <= <VCC>
-HEX0[1] <= <VCC>
-HEX0[2] <= heartbeat.DB_MAX_OUTPUT_PORT_TYPE
-HEX0[3] <= heartbeat.DB_MAX_OUTPUT_PORT_TYPE
-HEX0[4] <= heartbeat.DB_MAX_OUTPUT_PORT_TYPE
-HEX0[5] <= <VCC>
-HEX0[6] <= heartbeat.DB_MAX_OUTPUT_PORT_TYPE
-HEX1[0] <= arm_soc:soc_inst.LOCKUP
-HEX1[1] <= <VCC>
-HEX1[2] <= <VCC>
-HEX1[3] <= <VCC>
-HEX1[4] <= <VCC>
-HEX1[5] <= <VCC>
-HEX1[6] <= <VCC>
-HEX2[0] <= <VCC>
-HEX2[1] <= <VCC>
-HEX2[2] <= <VCC>
-HEX2[3] <= <VCC>
-HEX2[4] <= running.DB_MAX_OUTPUT_PORT_TYPE
-HEX2[5] <= <VCC>
-HEX2[6] <= running.DB_MAX_OUTPUT_PORT_TYPE
-HEX3[0] <= <VCC>
-HEX3[1] <= <VCC>
-HEX3[2] <= <VCC>
-HEX3[3] <= arm_soc:soc_inst.LOCKUP
-HEX3[4] <= arm_soc:soc_inst.LOCKUP
-HEX3[5] <= arm_soc:soc_inst.LOCKUP
-HEX3[6] <= <VCC>
-VGA_R[0] <= razzle:raz_inst.VGA_R
-VGA_R[1] <= razzle:raz_inst.VGA_R
-VGA_R[2] <= razzle:raz_inst.VGA_R
-VGA_R[3] <= razzle:raz_inst.VGA_R
-VGA_R[4] <= razzle:raz_inst.VGA_R
-VGA_R[5] <= razzle:raz_inst.VGA_R
-VGA_R[6] <= razzle:raz_inst.VGA_R
-VGA_R[7] <= razzle:raz_inst.VGA_R
-VGA_G[0] <= razzle:raz_inst.VGA_G
-VGA_G[1] <= razzle:raz_inst.VGA_G
-VGA_G[2] <= razzle:raz_inst.VGA_G
-VGA_G[3] <= razzle:raz_inst.VGA_G
-VGA_G[4] <= razzle:raz_inst.VGA_G
-VGA_G[5] <= razzle:raz_inst.VGA_G
-VGA_G[6] <= razzle:raz_inst.VGA_G
-VGA_G[7] <= razzle:raz_inst.VGA_G
-VGA_B[0] <= razzle:raz_inst.VGA_B
-VGA_B[1] <= razzle:raz_inst.VGA_B
-VGA_B[2] <= razzle:raz_inst.VGA_B
-VGA_B[3] <= razzle:raz_inst.VGA_B
-VGA_B[4] <= razzle:raz_inst.VGA_B
-VGA_B[5] <= razzle:raz_inst.VGA_B
-VGA_B[6] <= razzle:raz_inst.VGA_B
-VGA_B[7] <= razzle:raz_inst.VGA_B
-VGA_HS <= razzle:raz_inst.VGA_HS
-VGA_VS <= razzle:raz_inst.VGA_VS
-VGA_CLK <= razzle:raz_inst.VGA_CLK
-VGA_BLANK_N <= razzle:raz_inst.VGA_BLANK_N
-
-
-|de1_soc_wrapper|arm_soc:soc_inst
-HCLK => CORTEXM0DS:m0_1.HCLK
-HCLK => ahb_interconnect:interconnect_1.HCLK
-HCLK => ahb_ram:ram_1.HCLK
-HCLK => ahb_switches:switches_1.HCLK
-HCLK => ahb_pixel_memory:pix1.HCLK
-HRESETn => CORTEXM0DS:m0_1.HRESETn
-HRESETn => ahb_interconnect:interconnect_1.HRESETn
-HRESETn => ahb_ram:ram_1.HRESETn
-HRESETn => ahb_switches:switches_1.HRESETn
-HRESETn => ahb_pixel_memory:pix1.HRESETn
-pixel_x[0] => ahb_pixel_memory:pix1.pixel_x[0]
-pixel_x[1] => ahb_pixel_memory:pix1.pixel_x[1]
-pixel_x[2] => ahb_pixel_memory:pix1.pixel_x[2]
-pixel_x[3] => ahb_pixel_memory:pix1.pixel_x[3]
-pixel_x[4] => ahb_pixel_memory:pix1.pixel_x[4]
-pixel_x[5] => ahb_pixel_memory:pix1.pixel_x[5]
-pixel_x[6] => ahb_pixel_memory:pix1.pixel_x[6]
-pixel_x[7] => ahb_pixel_memory:pix1.pixel_x[7]
-pixel_x[8] => ahb_pixel_memory:pix1.pixel_x[8]
-pixel_x[9] => ahb_pixel_memory:pix1.pixel_x[9]
-pixel_y[0] => ahb_pixel_memory:pix1.pixel_y[0]
-pixel_y[1] => ahb_pixel_memory:pix1.pixel_y[1]
-pixel_y[2] => ahb_pixel_memory:pix1.pixel_y[2]
-pixel_y[3] => ahb_pixel_memory:pix1.pixel_y[3]
-pixel_y[4] => ahb_pixel_memory:pix1.pixel_y[4]
-pixel_y[5] => ahb_pixel_memory:pix1.pixel_y[5]
-pixel_y[6] => ahb_pixel_memory:pix1.pixel_y[6]
-pixel_y[7] => ahb_pixel_memory:pix1.pixel_y[7]
-pixel_y[8] => ahb_pixel_memory:pix1.pixel_y[8]
-Switches[0] => ahb_switches:switches_1.Switches[0]
-Switches[1] => ahb_switches:switches_1.Switches[1]
-Switches[2] => ahb_switches:switches_1.Switches[2]
-Switches[3] => ahb_switches:switches_1.Switches[3]
-Switches[4] => ahb_switches:switches_1.Switches[4]
-Switches[5] => ahb_switches:switches_1.Switches[5]
-Switches[6] => ahb_switches:switches_1.Switches[6]
-Switches[7] => ahb_switches:switches_1.Switches[7]
-Switches[8] => ahb_switches:switches_1.Switches[8]
-Switches[9] => ahb_switches:switches_1.Switches[9]
-Switches[10] => ahb_switches:switches_1.Switches[10]
-Switches[11] => ahb_switches:switches_1.Switches[11]
-Switches[12] => ahb_switches:switches_1.Switches[12]
-Switches[13] => ahb_switches:switches_1.Switches[13]
-Switches[14] => ahb_switches:switches_1.Switches[14]
-Switches[15] => ahb_switches:switches_1.Switches[15]
-Buttons[0] => ahb_switches:switches_1.Buttons[0]
-Buttons[1] => ahb_switches:switches_1.Buttons[1]
-pixel <= ahb_pixel_memory:pix1.pixel
-LOCKUP <= CORTEXM0DS:m0_1.LOCKUP
-
-
-|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1
-HCLK => HCLK.IN1
-HRESETn => HRESETn.IN1
-HADDR[0] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[1] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[2] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[3] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[4] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[5] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[6] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[7] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[8] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[9] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[10] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[11] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[12] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[13] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[14] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[15] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[16] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[17] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[18] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[19] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[20] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[21] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[22] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[23] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[24] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[25] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[26] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[27] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[28] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[29] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[30] <= cortexm0ds_logic:u_logic.haddr_o
-HADDR[31] <= cortexm0ds_logic:u_logic.haddr_o
-HBURST[0] <= cortexm0ds_logic:u_logic.hburst_o
-HBURST[1] <= cortexm0ds_logic:u_logic.hburst_o
-HBURST[2] <= cortexm0ds_logic:u_logic.hburst_o
-HMASTLOCK <= cortexm0ds_logic:u_logic.hmastlock_o
-HPROT[0] <= cortexm0ds_logic:u_logic.hprot_o
-HPROT[1] <= cortexm0ds_logic:u_logic.hprot_o
-HPROT[2] <= cortexm0ds_logic:u_logic.hprot_o
-HPROT[3] <= cortexm0ds_logic:u_logic.hprot_o
-HSIZE[0] <= cortexm0ds_logic:u_logic.hsize_o
-HSIZE[1] <= cortexm0ds_logic:u_logic.hsize_o
-HSIZE[2] <= cortexm0ds_logic:u_logic.hsize_o
-HTRANS[0] <= cortexm0ds_logic:u_logic.htrans_o
-HTRANS[1] <= cortexm0ds_logic:u_logic.htrans_o
-HWDATA[0] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[1] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[2] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[3] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[4] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[5] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[6] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[7] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[8] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[9] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[10] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[11] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[12] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[13] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[14] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[15] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[16] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[17] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[18] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[19] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[20] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[21] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[22] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[23] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[24] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[25] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[26] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[27] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[28] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[29] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[30] <= cortexm0ds_logic:u_logic.hwdata_o
-HWDATA[31] <= cortexm0ds_logic:u_logic.hwdata_o
-HWRITE <= cortexm0ds_logic:u_logic.hwrite_o
-HRDATA[0] => HRDATA[0].IN1
-HRDATA[1] => HRDATA[1].IN1
-HRDATA[2] => HRDATA[2].IN1
-HRDATA[3] => HRDATA[3].IN1
-HRDATA[4] => HRDATA[4].IN1
-HRDATA[5] => HRDATA[5].IN1
-HRDATA[6] => HRDATA[6].IN1
-HRDATA[7] => HRDATA[7].IN1
-HRDATA[8] => HRDATA[8].IN1
-HRDATA[9] => HRDATA[9].IN1
-HRDATA[10] => HRDATA[10].IN1
-HRDATA[11] => HRDATA[11].IN1
-HRDATA[12] => HRDATA[12].IN1
-HRDATA[13] => HRDATA[13].IN1
-HRDATA[14] => HRDATA[14].IN1
-HRDATA[15] => HRDATA[15].IN1
-HRDATA[16] => HRDATA[16].IN1
-HRDATA[17] => HRDATA[17].IN1
-HRDATA[18] => HRDATA[18].IN1
-HRDATA[19] => HRDATA[19].IN1
-HRDATA[20] => HRDATA[20].IN1
-HRDATA[21] => HRDATA[21].IN1
-HRDATA[22] => HRDATA[22].IN1
-HRDATA[23] => HRDATA[23].IN1
-HRDATA[24] => HRDATA[24].IN1
-HRDATA[25] => HRDATA[25].IN1
-HRDATA[26] => HRDATA[26].IN1
-HRDATA[27] => HRDATA[27].IN1
-HRDATA[28] => HRDATA[28].IN1
-HRDATA[29] => HRDATA[29].IN1
-HRDATA[30] => HRDATA[30].IN1
-HRDATA[31] => HRDATA[31].IN1
-HREADY => HREADY.IN1
-HRESP => HRESP.IN1
-NMI => NMI.IN1
-IRQ[0] => IRQ[0].IN1
-IRQ[1] => IRQ[1].IN1
-IRQ[2] => IRQ[2].IN1
-IRQ[3] => IRQ[3].IN1
-IRQ[4] => IRQ[4].IN1
-IRQ[5] => IRQ[5].IN1
-IRQ[6] => IRQ[6].IN1
-IRQ[7] => IRQ[7].IN1
-IRQ[8] => IRQ[8].IN1
-IRQ[9] => IRQ[9].IN1
-IRQ[10] => IRQ[10].IN1
-IRQ[11] => IRQ[11].IN1
-IRQ[12] => IRQ[12].IN1
-IRQ[13] => IRQ[13].IN1
-IRQ[14] => IRQ[14].IN1
-IRQ[15] => IRQ[15].IN1
-TXEV <= cortexm0ds_logic:u_logic.txev_o
-RXEV => RXEV.IN1
-LOCKUP <= cortexm0ds_logic:u_logic.lockup_o
-SYSRESETREQ <= cortexm0ds_logic:u_logic.sys_reset_req_o
-SLEEPING <= cortexm0ds_logic:u_logic.sleeping_o
-
-
-|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic
-hclk => Ypi3z4.CLK
-hclk => Joi3z4.CLK
-hclk => Umi3z4.CLK
-hclk => Fli3z4.CLK
-hclk => Qji3z4.CLK
-hclk => Aii3z4.CLK
-hclk => Lgi3z4.CLK
-hclk => Uei3z4.CLK
-hclk => Ddi3z4.CLK
-hclk => Rbi3z4.CLK
-hclk => Cai3z4.CLK
-hclk => N8i3z4.CLK
-hclk => Y6i3z4.CLK
-hclk => J5i3z4.CLK
-hclk => S3i3z4.CLK
-hclk => B2i3z4.CLK
-hclk => M0i3z4.CLK
-hclk => Xyh3z4.CLK
-hclk => Ixh3z4.CLK
-hclk => Tvh3z4.CLK
-hclk => Euh3z4.CLK
-hclk => Psh3z4.CLK
-hclk => Arh3z4.CLK
-hclk => Lph3z4.CLK
-hclk => Wnh3z4.CLK
-hclk => Hmh3z4.CLK
-hclk => Skh3z4.CLK
-hclk => Djh3z4.CLK
-hclk => Ohh3z4.CLK
-hclk => Zfh3z4.CLK
-hclk => Ieh3z4.CLK
-hclk => Tch3z4.CLK
-hclk => Ebh3z4.CLK
-hclk => P9h3z4.CLK
-hclk => A8h3z4.CLK
-hclk => I6h3z4.CLK
-hclk => Q4h3z4.CLK
-hclk => Z2h3z4.CLK
-hclk => I1h3z4.CLK
-hclk => Tzg3z4.CLK
-hclk => Eyg3z4.CLK
-hclk => Pwg3z4.CLK
-hclk => Avg3z4.CLK
-hclk => Ltg3z4.CLK
-hclk => Wrg3z4.CLK
-hclk => Hqg3z4.CLK
-hclk => Sog3z4.CLK
-hclk => Dng3z4.CLK
-hclk => Olg3z4.CLK
-hclk => Zjg3z4.CLK
-hclk => Kig3z4.CLK
-hclk => Vgg3z4.CLK
-hclk => Gfg3z4.CLK
-hclk => Rdg3z4.CLK
-hclk => Ccg3z4.CLK
-hclk => Nag3z4.CLK
-hclk => B9g3z4.CLK
-hclk => K7g3z4.CLK
-hclk => T5g3z4.CLK
-hclk => D4g3z4.CLK
-hclk => O2g3z4.CLK
-hclk => Z0g3z4.CLK
-hclk => Kzf3z4.CLK
-hclk => Vxf3z4.CLK
-hclk => Jwf3z4.CLK
-hclk => Uuf3z4.CLK
-hclk => Ftf3z4.CLK
-hclk => Qrf3z4.CLK
-hclk => Bqf3z4.CLK
-hclk => Mof3z4.CLK
-hclk => Xmf3z4.CLK
-hclk => Ilf3z4.CLK
-hclk => Tjf3z4.CLK
-hclk => Eif3z4.CLK
-hclk => Pgf3z4.CLK
-hclk => Aff3z4.CLK
-hclk => Ldf3z4.CLK
-hclk => Wbf3z4.CLK
-hclk => Kaf3z4.CLK
-hclk => T8f3z4.CLK
-hclk => C7f3z4.CLK
-hclk => M5f3z4.CLK
-hclk => W3f3z4.CLK
-hclk => H2f3z4.CLK
-hclk => Q0f3z4.CLK
-hclk => Aze3z4.CLK
-hclk => Kxe3z4.CLK
-hclk => Vve3z4.CLK
-hclk => Hue3z4.CLK
-hclk => Tse3z4.CLK
-hclk => Fre3z4.CLK
-hclk => Rpe3z4.CLK
-hclk => Foe3z4.CLK
-hclk => Tme3z4.CLK
-hclk => Ble3z4.CLK
-hclk => Jje3z4.CLK
-hclk => She3z4.CLK
-hclk => Bge3z4.CLK
-hclk => Lee3z4.CLK
-hclk => Wce3z4.CLK
-hclk => Ibe3z4.CLK
-hclk => U9e3z4.CLK
-hclk => F8e3z4.CLK
-hclk => Q6e3z4.CLK
-hclk => B5e3z4.CLK
-hclk => M3e3z4.CLK
-hclk => X1e3z4.CLK
-hclk => I0e3z4.CLK
-hclk => Tyd3z4.CLK
-hclk => Exd3z4.CLK
-hclk => Pvd3z4.CLK
-hclk => Aud3z4.CLK
-hclk => Lsd3z4.CLK
-hclk => Wqd3z4.CLK
-hclk => Hpd3z4.CLK
-hclk => Snd3z4.CLK
-hclk => Gmd3z4.CLK
-hclk => Rkd3z4.CLK
-hclk => Bjd3z4.CLK
-hclk => Lhd3z4.CLK
-hclk => Vfd3z4.CLK
-hclk => Fed3z4.CLK
-hclk => Pcd3z4.CLK
-hclk => Zad3z4.CLK
-hclk => J9d3z4.CLK
-hclk => T7d3z4.CLK
-hclk => G6d3z4.CLK
-hclk => V4d3z4.CLK
-hclk => H3d3z4.CLK
-hclk => T1d3z4.CLK
-hclk => E0d3z4.CLK
-hclk => Qyc3z4.CLK
-hclk => Cxc3z4.CLK
-hclk => Ovc3z4.CLK
-hclk => Ztc3z4.CLK
-hclk => Jsc3z4.CLK
-hclk => Tqc3z4.CLK
-hclk => Dpc3z4.CLK
-hclk => Nnc3z4.CLK
-hclk => Ylc3z4.CLK
-hclk => Jkc3z4.CLK
-hclk => Uic3z4.CLK
-hclk => Fhc3z4.CLK
-hclk => Qfc3z4.CLK
-hclk => Bec3z4.CLK
-hclk => Mcc3z4.CLK
-hclk => Vac3z4.CLK
-hclk => E9c3z4.CLK
-hclk => N7c3z4.CLK
-hclk => W5c3z4.CLK
-hclk => F4c3z4.CLK
-hclk => O2c3z4.CLK
-hclk => X0c3z4.CLK
-hclk => Gzb3z4.CLK
-hclk => Pxb3z4.CLK
-hclk => Yvb3z4.CLK
-hclk => Hub3z4.CLK
-hclk => Qsb3z4.CLK
-hclk => Zqb3z4.CLK
-hclk => Ipb3z4.CLK
-hclk => Rnb3z4.CLK
-hclk => Bmb3z4.CLK
-hclk => Kkb3z4.CLK
-hclk => Tib3z4.CLK
-hclk => Dhb3z4.CLK
-hclk => Nfb3z4.CLK
-hclk => Xdb3z4.CLK
-hclk => Gcb3z4.CLK
-hclk => Pab3z4.CLK
-hclk => Z8b3z4.CLK
-hclk => J7b3z4.CLK
-hclk => S5b3z4.CLK
-hclk => C4b3z4.CLK
-hclk => M2b3z4.CLK
-hclk => W0b3z4.CLK
-hclk => Gza3z4.CLK
-hclk => Qxa3z4.CLK
-hclk => Zva3z4.CLK
-hclk => Iua3z4.CLK
-hclk => Rsa3z4.CLK
-hclk => Ara3z4.CLK
-hclk => Jpa3z4.CLK
-hclk => Tna3z4.CLK
-hclk => Cma3z4.CLK
-hclk => Mka3z4.CLK
-hclk => Wia3z4.CLK
-hclk => Gha3z4.CLK
-hclk => Qfa3z4.CLK
-hclk => Aea3z4.CLK
-hclk => Jca3z4.CLK
-hclk => Taa3z4.CLK
-hclk => C9a3z4.CLK
-hclk => L7a3z4.CLK
-hclk => U5a3z4.CLK
-hclk => D4a3z4.CLK
-hclk => P2a3z4.CLK
-hclk => B1a3z4.CLK
-hclk => Lz93z4.CLK
-hclk => Xx93z4.CLK
-hclk => Jw93z4.CLK
-hclk => Vu93z4.CLK
-hclk => Gt93z4.CLK
-hclk => Rr93z4.CLK
-hclk => Cq93z4.CLK
-hclk => No93z4.CLK
-hclk => Ym93z4.CLK
-hclk => Jl93z4.CLK
-hclk => Uj93z4.CLK
-hclk => Fi93z4.CLK
-hclk => Qg93z4.CLK
-hclk => Bf93z4.CLK
-hclk => Md93z4.CLK
-hclk => Yb93z4.CLK
-hclk => Ka93z4.CLK
-hclk => W893z4.CLK
-hclk => I793z4.CLK
-hclk => U593z4.CLK
-hclk => G493z4.CLK
-hclk => R293z4.CLK
-hclk => C193z4.CLK
-hclk => Nz83z4.CLK
-hclk => Yx83z4.CLK
-hclk => Jw83z4.CLK
-hclk => Uu83z4.CLK
-hclk => Ft83z4.CLK
-hclk => Rr83z4.CLK
-hclk => Dq83z4.CLK
-hclk => Po83z4.CLK
-hclk => An83z4.CLK
-hclk => Ll83z4.CLK
-hclk => Wj83z4.CLK
-hclk => Hi83z4.CLK
-hclk => Sg83z4.CLK
-hclk => Df83z4.CLK
-hclk => Od83z4.CLK
-hclk => Zb83z4.CLK
-hclk => Ka83z4.CLK
-hclk => V883z4.CLK
-hclk => H783z4.CLK
-hclk => T583z4.CLK
-hclk => F483z4.CLK
-hclk => R283z4.CLK
-hclk => C183z4.CLK
-hclk => Nz73z4.CLK
-hclk => Yx73z4.CLK
-hclk => Jw73z4.CLK
-hclk => Uu73z4.CLK
-hclk => Ft73z4.CLK
-hclk => Rr73z4.CLK
-hclk => Dq73z4.CLK
-hclk => Po73z4.CLK
-hclk => An73z4.CLK
-hclk => Ll73z4.CLK
-hclk => Wj73z4.CLK
-hclk => Ii73z4.CLK
-hclk => Ug73z4.CLK
-hclk => Gf73z4.CLK
-hclk => Rd73z4.CLK
-hclk => Cc73z4.CLK
-hclk => Na73z4.CLK
-hclk => Y873z4.CLK
-hclk => J773z4.CLK
-hclk => U573z4.CLK
-hclk => F473z4.CLK
-hclk => Q273z4.CLK
-hclk => B173z4.CLK
-hclk => Mz63z4.CLK
-hclk => Yx63z4.CLK
-hclk => Kw63z4.CLK
-hclk => Wu63z4.CLK
-hclk => It63z4.CLK
-hclk => Tr63z4.CLK
-hclk => Eq63z4.CLK
-hclk => Po63z4.CLK
-hclk => An63z4.CLK
-hclk => Ll63z4.CLK
-hclk => Wj63z4.CLK
-hclk => Ii63z4.CLK
-hclk => Ug63z4.CLK
-hclk => Gf63z4.CLK
-hclk => Rd63z4.CLK
-hclk => Cc63z4.CLK
-hclk => Na63z4.CLK
-hclk => Z863z4.CLK
-hclk => L763z4.CLK
-hclk => X563z4.CLK
-hclk => I463z4.CLK
-hclk => T263z4.CLK
-hclk => E163z4.CLK
-hclk => Pz53z4.CLK
-hclk => Ay53z4.CLK
-hclk => Lw53z4.CLK
-hclk => Wu53z4.CLK
-hclk => Ht53z4.CLK
-hclk => Sr53z4.CLK
-hclk => Dq53z4.CLK
-hclk => Po53z4.CLK
-hclk => Bn53z4.CLK
-hclk => Nl53z4.CLK
-hclk => Zj53z4.CLK
-hclk => Ki53z4.CLK
-hclk => Vg53z4.CLK
-hclk => Gf53z4.CLK
-hclk => Rd53z4.CLK
-hclk => Cc53z4.CLK
-hclk => Na53z4.CLK
-hclk => Z853z4.CLK
-hclk => L753z4.CLK
-hclk => X553z4.CLK
-hclk => I453z4.CLK
-hclk => T253z4.CLK
-hclk => E153z4.CLK
-hclk => Qz43z4.CLK
-hclk => Cy43z4.CLK
-hclk => Ow43z4.CLK
-hclk => Zu43z4.CLK
-hclk => Kt43z4.CLK
-hclk => Vr43z4.CLK
-hclk => Gq43z4.CLK
-hclk => Ro43z4.CLK
-hclk => Cn43z4.CLK
-hclk => Nl43z4.CLK
-hclk => Yj43z4.CLK
-hclk => Ji43z4.CLK
-hclk => Ug43z4.CLK
-hclk => Gf43z4.CLK
-hclk => Sd43z4.CLK
-hclk => Ec43z4.CLK
-hclk => Qa43z4.CLK
-hclk => B943z4.CLK
-hclk => M743z4.CLK
-hclk => X543z4.CLK
-hclk => I443z4.CLK
-hclk => T243z4.CLK
-hclk => E143z4.CLK
-hclk => Qz33z4.CLK
-hclk => Cy33z4.CLK
-hclk => Ow33z4.CLK
-hclk => Zu33z4.CLK
-hclk => Kt33z4.CLK
-hclk => Vr33z4.CLK
-hclk => Hq33z4.CLK
-hclk => To33z4.CLK
-hclk => Fn33z4.CLK
-hclk => Ql33z4.CLK
-hclk => Bk33z4.CLK
-hclk => Mi33z4.CLK
-hclk => Xg33z4.CLK
-hclk => If33z4.CLK
-hclk => Td33z4.CLK
-hclk => Ec33z4.CLK
-hclk => Pa33z4.CLK
-hclk => A933z4.CLK
-hclk => L733z4.CLK
-hclk => X533z4.CLK
-hclk => J433z4.CLK
-hclk => V233z4.CLK
-hclk => H133z4.CLK
-hclk => Sz23z4.CLK
-hclk => Dy23z4.CLK
-hclk => Ow23z4.CLK
-hclk => Zu23z4.CLK
-hclk => Kt23z4.CLK
-hclk => Vr23z4.CLK
-hclk => Hq23z4.CLK
-hclk => To23z4.CLK
-hclk => Fn23z4.CLK
-hclk => Ql23z4.CLK
-hclk => Bk23z4.CLK
-hclk => Mi23z4.CLK
-hclk => Yg23z4.CLK
-hclk => Kf23z4.CLK
-hclk => Wd23z4.CLK
-hclk => Hc23z4.CLK
-hclk => Sa23z4.CLK
-hclk => D923z4.CLK
-hclk => O723z4.CLK
-hclk => Z523z4.CLK
-hclk => K423z4.CLK
-hclk => V223z4.CLK
-hclk => G123z4.CLK
-hclk => Rz13z4.CLK
-hclk => Cy13z4.CLK
-hclk => Ow13z4.CLK
-hclk => Av13z4.CLK
-hclk => Mt13z4.CLK
-hclk => Yr13z4.CLK
-hclk => Jq13z4.CLK
-hclk => Uo13z4.CLK
-hclk => Fn13z4.CLK
-hclk => Ql13z4.CLK
-hclk => Bk13z4.CLK
-hclk => Mi13z4.CLK
-hclk => Yg13z4.CLK
-hclk => Kf13z4.CLK
-hclk => Wd13z4.CLK
-hclk => Hc13z4.CLK
-hclk => Sa13z4.CLK
-hclk => E913z4.CLK
-hclk => Q713z4.CLK
-hclk => B613z4.CLK
-hclk => M413z4.CLK
-hclk => X213z4.CLK
-hclk => I113z4.CLK
-hclk => Tz03z4.CLK
-hclk => Ey03z4.CLK
-hclk => Pw03z4.CLK
-hclk => Bv03z4.CLK
-hclk => Nt03z4.CLK
-hclk => Zr03z4.CLK
-hclk => Lq03z4.CLK
-hclk => Wo03z4.CLK
-hclk => Hn03z4.CLK
-hclk => Sl03z4.CLK
-hclk => Ek03z4.CLK
-hclk => Qi03z4.CLK
-hclk => Ch03z4.CLK
-hclk => Nf03z4.CLK
-hclk => Yd03z4.CLK
-hclk => Kc03z4.CLK
-hclk => Wa03z4.CLK
-hclk => H903z4.CLK
-hclk => S703z4.CLK
-hclk => D603z4.CLK
-hclk => O403z4.CLK
-hclk => Z203z4.CLK
-hclk => K103z4.CLK
-hclk => Vzz2z4.CLK
-hclk => Hyz2z4.CLK
-hclk => Twz2z4.CLK
-hclk => Fvz2z4.CLK
-hclk => Rtz2z4.CLK
-hclk => Csz2z4.CLK
-hclk => Nqz2z4.CLK
-hclk => Yoz2z4.CLK
-hclk => Knz2z4.CLK
-hclk => Wlz2z4.CLK
-hclk => Ikz2z4.CLK
-hclk => Tiz2z4.CLK
-hclk => Ehz2z4.CLK
-hclk => Pfz2z4.CLK
-hclk => Aez2z4.CLK
-hclk => Mcz2z4.CLK
-hclk => Yaz2z4.CLK
-hclk => K9z2z4.CLK
-hclk => W7z2z4.CLK
-hclk => I6z2z4.CLK
-hclk => U4z2z4.CLK
-hclk => C3z2z4.CLK
-hclk => K1z2z4.CLK
-hclk => Wzy2z4.CLK
-hclk => Hyy2z4.CLK
-hclk => Swy2z4.CLK
-hclk => Dvy2z4.CLK
-hclk => Pty2z4.CLK
-hclk => Bsy2z4.CLK
-hclk => Nqy2z4.CLK
-hclk => Zoy2z4.CLK
-hclk => Lny2z4.CLK
-hclk => Xly2z4.CLK
-hclk => Jky2z4.CLK
-hclk => Viy2z4.CLK
-hclk => Jhy2z4.CLK
-hclk => Ufy2z4.CLK
-hclk => Fey2z4.CLK
-hclk => Qcy2z4.CLK
-hclk => Bby2z4.CLK
-hclk => M9y2z4.CLK
-hclk => Y7y2z4.CLK
-hclk => K6y2z4.CLK
-hclk => W4y2z4.CLK
-hclk => I3y2z4.CLK
-hclk => T1y2z4.CLK
-hclk => F0y2z4.CLK
-hclk => Tyx2z4.CLK
-hclk => Hxx2z4.CLK
-hclk => Vvx2z4.CLK
-hclk => Jux2z4.CLK
-hclk => Xsx2z4.CLK
-hclk => Lrx2z4.CLK
-hclk => Zpx2z4.CLK
-hclk => Nox2z4.CLK
-hclk => Bnx2z4.CLK
-hclk => Plx2z4.CLK
-hclk => Dkx2z4.CLK
-hclk => Rix2z4.CLK
-hclk => Fhx2z4.CLK
-hclk => Ufx2z4.CLK
-hclk => Jex2z4.CLK
-hclk => Ycx2z4.CLK
-hclk => Nbx2z4.CLK
-hclk => Cax2z4.CLK
-hclk => R8x2z4.CLK
-hclk => G7x2z4.CLK
-hclk => U5x2z4.CLK
-hclk => J4x2z4.CLK
-hclk => U2x2z4.CLK
-hclk => F1x2z4.CLK
-hclk => Qzw2z4.CLK
-hclk => Byw2z4.CLK
-hclk => Mww2z4.CLK
-hclk => Xuw2z4.CLK
-hclk => Itw2z4.CLK
-hclk => Urw2z4.CLK
-hclk => Gqw2z4.CLK
-hclk => Sow2z4.CLK
-hclk => Enw2z4.CLK
-hclk => Qlw2z4.CLK
-hclk => Ckw2z4.CLK
-hclk => Oiw2z4.CLK
-hclk => Ahw2z4.CLK
-hclk => Mfw2z4.CLK
-hclk => Ydw2z4.CLK
-hclk => Jcw2z4.CLK
-hclk => Vaw2z4.CLK
-hclk => G9w2z4.CLK
-hclk => U7w2z4.CLK
-hclk => I6w2z4.CLK
-hclk => S4w2z4.CLK
-hclk => C3w2z4.CLK
-hclk => R1w2z4.CLK
-hclk => G0w2z4.CLK
-hclk => Uyv2z4.CLK
-hclk => Fxv2z4.CLK
-hclk => Rvv2z4.CLK
-hclk => Duv2z4.CLK
-hclk => Psv2z4.CLK
-hclk => Arv2z4.CLK
-hclk => Lpv2z4.CLK
-hclk => Wnv2z4.CLK
-hclk => Hmv2z4.CLK
-hclk => Skv2z4.CLK
-hclk => Djv2z4.CLK
-hclk => Ohv2z4.CLK
-hclk => Zfv2z4.CLK
-hclk => Kev2z4.CLK
-hclk => Vcv2z4.CLK
-hclk => Hbv2z4.CLK
-hclk => T9v2z4.CLK
-hclk => F8v2z4.CLK
-hclk => R6v2z4.CLK
-hclk => C5v2z4.CLK
-hclk => N3v2z4.CLK
-hclk => Y1v2z4.CLK
-hclk => J0v2z4.CLK
-hclk => Uyu2z4.CLK
-hclk => Fxu2z4.CLK
-hclk => Rvu2z4.CLK
-hclk => Duu2z4.CLK
-hclk => Psu2z4.CLK
-hclk => Aru2z4.CLK
-hclk => Lpu2z4.CLK
-hclk => Wnu2z4.CLK
-hclk => Imu2z4.CLK
-hclk => Uku2z4.CLK
-hclk => Gju2z4.CLK
-hclk => Rhu2z4.CLK
-hclk => Cgu2z4.CLK
-hclk => Neu2z4.CLK
-hclk => Ycu2z4.CLK
-hclk => Jbu2z4.CLK
-hclk => U9u2z4.CLK
-hclk => F8u2z4.CLK
-hclk => Q6u2z4.CLK
-hclk => B5u2z4.CLK
-hclk => M3u2z4.CLK
-hclk => Y1u2z4.CLK
-hclk => K0u2z4.CLK
-hclk => Wyt2z4.CLK
-hclk => Ixt2z4.CLK
-hclk => Tvt2z4.CLK
-hclk => Eut2z4.CLK
-hclk => Pst2z4.CLK
-hclk => Art2z4.CLK
-hclk => Lpt2z4.CLK
-hclk => Wnt2z4.CLK
-hclk => Imt2z4.CLK
-hclk => Ukt2z4.CLK
-hclk => Gjt2z4.CLK
-hclk => Rht2z4.CLK
-hclk => Cgt2z4.CLK
-hclk => Pet2z4.CLK
-hclk => Adt2z4.CLK
-hclk => Mbt2z4.CLK
-hclk => Y9t2z4.CLK
-hclk => L8t2z4.CLK
-hclk => Y6t2z4.CLK
-hclk => O5t2z4.CLK
-hclk => A4t2z4.CLK
-hclk => I2t2z4.CLK
-hclk => R0t2z4.CLK
-hclk => Azs2z4.CLK
-hclk => Jxs2z4.CLK
-hclk => Svs2z4.CLK
-hclk => Bus2z4.CLK
-hclk => Kss2z4.CLK
-hclk => Tqs2z4.CLK
-hclk => Cps2z4.CLK
-hclk => Lns2z4.CLK
-hclk => Uls2z4.CLK
-hclk => Dks2z4.CLK
-hclk => Mis2z4.CLK
-hclk => Vgs2z4.CLK
-hclk => Ffs2z4.CLK
-hclk => Rds2z4.CLK
-hclk => Dcs2z4.CLK
-hclk => Oas2z4.CLK
-hclk => Z8s2z4.CLK
-hclk => K7s2z4.CLK
-hclk => W5s2z4.CLK
-hclk => I4s2z4.CLK
-hclk => U2s2z4.CLK
-hclk => G1s2z4.CLK
-hclk => Szr2z4.CLK
-hclk => Eyr2z4.CLK
-hclk => Qwr2z4.CLK
-hclk => Cvr2z4.CLK
-hclk => Otr2z4.CLK
-hclk => Asr2z4.CLK
-hclk => Lqr2z4.CLK
-hclk => Wor2z4.CLK
-hclk => Hnr2z4.CLK
-hclk => Slr2z4.CLK
-hclk => Dkr2z4.CLK
-hclk => Oir2z4.CLK
-hclk => Zgr2z4.CLK
-hclk => Kfr2z4.CLK
-hclk => Vdr2z4.CLK
-hclk => Gcr2z4.CLK
-hclk => Oar2z4.CLK
-hclk => W8r2z4.CLK
-hclk => I7r2z4.CLK
-hclk => U5r2z4.CLK
-hclk => G4r2z4.CLK
-hclk => S2r2z4.CLK
-hclk => E1r2z4.CLK
-hclk => Qzq2z4.CLK
-hclk => Cyq2z4.CLK
-hclk => Owq2z4.CLK
-hclk => Wuq2z4.CLK
-hclk => Etq2z4.CLK
-hclk => Trq2z4.CLK
-hclk => Eqq2z4.CLK
-hclk => Poq2z4.CLK
-hclk => Anq2z4.CLK
-hclk => Llq2z4.CLK
-hclk => Zjq2z4.CLK
-hclk => Kiq2z4.CLK
-hclk => Vgq2z4.CLK
-hclk => Gfq2z4.CLK
-hclk => Rdq2z4.CLK
-hclk => Ccq2z4.CLK
-hclk => Naq2z4.CLK
-hclk => Y8q2z4.CLK
-hclk => J7q2z4.CLK
-hclk => U5q2z4.CLK
-hclk => F4q2z4.CLK
-hclk => Q2q2z4.CLK
-hclk => B1q2z4.CLK
-hclk => Mzp2z4.CLK
-hclk => Wxp2z4.CLK
-hclk => Iwp2z4.CLK
-hclk => Uup2z4.CLK
-hclk => Gtp2z4.CLK
-hclk => Qrp2z4.CLK
-hclk => Aqp2z4.CLK
-hclk => Kop2z4.CLK
-hclk => Wmp2z4.CLK
-hclk => Ilp2z4.CLK
-hclk => Ujp2z4.CLK
-hclk => Gip2z4.CLK
-hclk => Sgp2z4.CLK
-hclk => Efp2z4.CLK
-hclk => Tdp2z4.CLK
-hclk => Ecp2z4.CLK
-hclk => Pap2z4.CLK
-hclk => A9p2z4.CLK
-hclk => L7p2z4.CLK
-hclk => W5p2z4.CLK
-hclk => H4p2z4.CLK
-hclk => S2p2z4.CLK
-hclk => D1p2z4.CLK
-hclk => Ozo2z4.CLK
-hclk => Zxo2z4.CLK
-hclk => Kwo2z4.CLK
-hclk => Vuo2z4.CLK
-hclk => Gto2z4.CLK
-hclk => Rro2z4.CLK
-hclk => Cqo2z4.CLK
-hclk => Noo2z4.CLK
-hclk => Ymo2z4.CLK
-hclk => Jlo2z4.CLK
-hclk => Ujo2z4.CLK
-hclk => Fio2z4.CLK
-hclk => Ogo2z4.CLK
-hclk => Xeo2z4.CLK
-hclk => Gdo2z4.CLK
-hclk => Rbo2z4.CLK
-hclk => Cao2z4.CLK
-hclk => N8o2z4.CLK
-hclk => Y6o2z4.CLK
-hclk => J5o2z4.CLK
-hclk => V3o2z4.CLK
-hclk => F2o2z4.CLK
-hclk => O0o2z4.CLK
-hclk => Xyn2z4.CLK
-hclk => Ixn2z4.CLK
-hclk => Tvn2z4.CLK
-hclk => Eun2z4.CLK
-hclk => Psn2z4.CLK
-hclk => Arn2z4.CLK
-hclk => Ipn2z4.CLK
-hclk => Qnn2z4.CLK
-hclk => Cmn2z4.CLK
-hclk => Okn2z4.CLK
-hclk => Ajn2z4.CLK
-hclk => Mhn2z4.CLK
-hclk => Yfn2z4.CLK
-hclk => Nen2z4.CLK
-hclk => Zcn2z4.CLK
-hclk => Lbn2z4.CLK
-hclk => X9n2z4.CLK
-hclk => G8n2z4.CLK
-hclk => R6n2z4.CLK
-hclk => C5n2z4.CLK
-hclk => N3n2z4.CLK
-hclk => Y1n2z4.CLK
-hclk => J0n2z4.CLK
-hclk => Rym2z4.CLK
-hclk => Axm2z4.CLK
-hclk => Mvm2z4.CLK
-hclk => Ytm2z4.CLK
-hclk => Ksm2z4.CLK
-hclk => Wqm2z4.CLK
-hclk => Ipm2z4.CLK
-hclk => Unm2z4.CLK
-hclk => Gmm2z4.CLK
-hclk => Skm2z4.CLK
-hclk => Ejm2z4.CLK
-hclk => Thm2z4.CLK
-hclk => Fgm2z4.CLK
-hclk => Qem2z4.CLK
-hclk => Bdm2z4.CLK
-hclk => Nbm2z4.CLK
-hclk => Cam2z4.CLK
-hclk => L8m2z4.CLK
-hclk => X6m2z4.CLK
-hclk => J5m2z4.CLK
-hclk => V3m2z4.CLK
-hclk => H2m2z4.CLK
-hclk => T0m2z4.CLK
-hclk => Fzl2z4.CLK
-hclk => Rxl2z4.CLK
-hclk => Dwl2z4.CLK
-hclk => Lul2z4.CLK
-hclk => Usl2z4.CLK
-hclk => Grl2z4.CLK
-hclk => Spl2z4.CLK
-hclk => Eol2z4.CLK
-hclk => Qml2z4.CLK
-hclk => Cll2z4.CLK
-hclk => Mjl2z4.CLK
-hclk => Xhl2z4.CLK
-hclk => Igl2z4.CLK
-hclk => Tel2z4.CLK
-hclk => Edl2z4.CLK
-hclk => Pbl2z4.CLK
-hclk => Y9l2z4.CLK
-hclk => H8l2z4.CLK
-hclk => Q6l2z4.CLK
-hclk => Z4l2z4.CLK
-hclk => K3l2z4.CLK
-hclk => V1l2z4.CLK
-hclk => J0l2z4.CLK
-hclk => Xyk2z4.CLK
-hclk => Gxk2z4.CLK
-hclk => Svk2z4.CLK
-hclk => Auk2z4.CLK
-hclk => Nsk2z4.CLK
-hclk => Ark2z4.CLK
-hclk => Npk2z4.CLK
-hclk => Aok2z4.CLK
-hclk => Omk2z4.CLK
-hclk => Zkk2z4.CLK
-hclk => Kjk2z4.CLK
-hclk => Vhk2z4.CLK
-hclk => Ggk2z4.CLK
-hclk => Rek2z4.CLK
-hclk => Idk2z4.CLK
-hclk => Wbk2z4.CLK
-hclk => Hak2z4.CLK
-hclk => S8k2z4.CLK
-hclk => D7k2z4.CLK
-hclk => O5k2z4.CLK
-hclk => Z3k2z4.CLK
-hclk => K2k2z4.CLK
-hclk => V0k2z4.CLK
-hclk => Hzj2z4.CLK
-hclk => Txj2z4.CLK
-hclk => Fwj2z4.CLK
-hclk => Ruj2z4.CLK
-hclk => Dtj2z4.CLK
-hclk => Orj2z4.CLK
-hclk => Zpj2z4.CLK
-hclk => Koj2z4.CLK
-hclk => Vmj2z4.CLK
-hclk => Glj2z4.CLK
-hclk => Sjj2z4.CLK
-hclk => Fij2z4.CLK
-hclk => Sgj2z4.CLK
-hclk => Ffj2z4.CLK
-hclk => Qdj2z4.CLK
-hclk => Fcj2z4.CLK
-hclk => Uaj2z4.CLK
-hclk => F9j2z4.CLK
-hclk => Q7j2z4.CLK
-hclk => B6j2z4.CLK
-hclk => M4j2z4.CLK
-hclk => X2j2z4.CLK
-hclk => M1j2z4.CLK
-hclk => Yzi2z4.CLK
-hclk => Kyi2z4.CLK
-hclk => Ywi2z4.CLK
-hclk => Mvi2z4.CLK
-hclk => Xti2z4.CLK
-hclk => Isi2z4.CLK
-hclk => Uqi2z4.CLK
-hclk => Fpi2z4.CLK
-hclk => Rni2z4.CLK
-hclk => Emi2z4.CLK
-hclk => Tki2z4.CLK
-hclk => Gji2z4.CLK
-hclk => Rhi2z4.CLK
-hclk => Igi2z4.CLK
-hclk => Zei2z4.CLK
-hclk => Pdi2z4.CLK
-hclk => Gci2z4.CLK
-hclk => Wai2z4.CLK
-hclk => H9i2z4.CLK
-hclk => Z7i2z4.CLK
-hclk => J6i2z4.CLK
-hreset_n => Ypi3z4.ACLR
-hreset_n => Xti2z4.PRESET
-hreset_n => Uu83z4.PRESET
-hreset_n => Jw83z4.PRESET
-hreset_n => Zkk2z4.PRESET
-hreset_n => Yx83z4.PRESET
-hreset_n => Nz83z4.PRESET
-hreset_n => C193z4.PRESET
-hreset_n => R293z4.PRESET
-hreset_n => Wbf3z4.PRESET
-hreset_n => Md93z4.PRESET
-hreset_n => Bf93z4.PRESET
-hreset_n => Nag3z4.PRESET
-hreset_n => Qg93z4.PRESET
-hreset_n => Fi93z4.PRESET
-hreset_n => Uj93z4.PRESET
-hreset_n => Jl93z4.PRESET
-hreset_n => E0d3z4.PRESET
-hreset_n => No93z4.PRESET
-hreset_n => Cq93z4.PRESET
-hreset_n => Rr93z4.PRESET
-hreset_n => Snd3z4.PRESET
-hreset_n => Gt93z4.PRESET
-hreset_n => Cxc3z4.PRESET
-hreset_n => Qyc3z4.PRESET
-hreset_n => Grl2z4.PRESET
-hreset_n => G493z4.PRESET
-hreset_n => W893z4.PRESET
-hreset_n => Ka93z4.PRESET
-hreset_n => Yb93z4.PRESET
-hreset_n => Vu93z4.PRESET
-hreset_n => Txj2z4.PRESET
-hreset_n => Unm2z4.PRESET
-hreset_n => Koj2z4.PRESET
-hreset_n => Rro2z4.PRESET
-hreset_n => Fio2z4.PRESET
-hreset_n => Kjk2z4.PRESET
-hreset_n => Gfq2z4.PRESET
-hreset_n => V0k2z4.PRESET
-hreset_n => Pbl2z4.PRESET
-hreset_n => Zpj2z4.PRESET
-hreset_n => Orj2z4.PRESET
-hreset_n => J0n2z4.PRESET
-hreset_n => Anq2z4.PRESET
-hreset_n => Ccg3z4.PRESET
-hreset_n => A9p2z4.PRESET
-hreset_n => Arn2z4.PRESET
-hreset_n => Kwo2z4.PRESET
-hreset_n => J5o2z4.PRESET
-hreset_n => Naq2z4.PRESET
-hreset_n => Mzp2z4.PRESET
-hreset_n => Hnr2z4.PRESET
-hreset_n => Gcr2z4.PRESET
-hreset_n => Hpd3z4.PRESET
-hreset_n => K7s2z4.PRESET
-hreset_n => U2s2z4.PRESET
-hreset_n => Asr2z4.PRESET
-hreset_n => Spl2z4.PRESET
-hreset_n => Ipm2z4.PRESET
-hreset_n => Sgp2z4.PRESET
-hreset_n => E1r2z4.PRESET
-hreset_n => T0m2z4.PRESET
-hreset_n => Yfn2z4.PRESET
-hreset_n => Fwj2z4.PRESET
-hreset_n => Gmm2z4.PRESET
-hreset_n => Ll73z4.PRESET
-hreset_n => Ft73z4.PRESET
-hreset_n => Uu73z4.PRESET
-hreset_n => An73z4.PRESET
-hreset_n => Jw73z4.PRESET
-hreset_n => Yx73z4.PRESET
-hreset_n => Nz73z4.PRESET
-hreset_n => C183z4.PRESET
-hreset_n => Ldf3z4.PRESET
-hreset_n => V883z4.PRESET
-hreset_n => Ka83z4.PRESET
-hreset_n => Rdg3z4.PRESET
-hreset_n => Zb83z4.PRESET
-hreset_n => Od83z4.PRESET
-hreset_n => Df83z4.PRESET
-hreset_n => Sg83z4.PRESET
-hreset_n => Ft83z4.PRESET
-hreset_n => Hi83z4.PRESET
-hreset_n => Wj83z4.PRESET
-hreset_n => Ll83z4.PRESET
-hreset_n => Wqd3z4.PRESET
-hreset_n => An83z4.PRESET
-hreset_n => Dq83z4.PRESET
-hreset_n => Rr83z4.PRESET
-hreset_n => Po73z4.PRESET
-hreset_n => R283z4.PRESET
-hreset_n => F483z4.PRESET
-hreset_n => T583z4.PRESET
-hreset_n => H783z4.PRESET
-hreset_n => Po83z4.PRESET
-hreset_n => Dq73z4.PRESET
-hreset_n => Rr73z4.PRESET
-hreset_n => Cc63z4.PRESET
-hreset_n => Wj63z4.PRESET
-hreset_n => Ll63z4.PRESET
-hreset_n => Rd63z4.PRESET
-hreset_n => An63z4.PRESET
-hreset_n => Po63z4.PRESET
-hreset_n => Eq63z4.PRESET
-hreset_n => Tr63z4.PRESET
-hreset_n => Aff3z4.PRESET
-hreset_n => Mz63z4.PRESET
-hreset_n => B173z4.PRESET
-hreset_n => Gfg3z4.PRESET
-hreset_n => Q273z4.PRESET
-hreset_n => F473z4.PRESET
-hreset_n => U573z4.PRESET
-hreset_n => J773z4.PRESET
-hreset_n => Wj73z4.PRESET
-hreset_n => Y873z4.PRESET
-hreset_n => Na73z4.PRESET
-hreset_n => Cc73z4.PRESET
-hreset_n => Lsd3z4.PRESET
-hreset_n => Rd73z4.PRESET
-hreset_n => Ug73z4.PRESET
-hreset_n => Ii73z4.PRESET
-hreset_n => Gf63z4.PRESET
-hreset_n => It63z4.PRESET
-hreset_n => Wu63z4.PRESET
-hreset_n => Kw63z4.PRESET
-hreset_n => Yx63z4.PRESET
-hreset_n => Gf73z4.PRESET
-hreset_n => Ug63z4.PRESET
-hreset_n => Ii63z4.PRESET
-hreset_n => Lpu2z4.PRESET
-hreset_n => Fxu2z4.PRESET
-hreset_n => Uyu2z4.PRESET
-hreset_n => Aru2z4.PRESET
-hreset_n => J0v2z4.PRESET
-hreset_n => Y1v2z4.PRESET
-hreset_n => N3v2z4.PRESET
-hreset_n => C5v2z4.PRESET
-hreset_n => Xmf3z4.PRESET
-hreset_n => Vcv2z4.PRESET
-hreset_n => Kev2z4.PRESET
-hreset_n => Dng3z4.PRESET
-hreset_n => Zfv2z4.PRESET
-hreset_n => Ohv2z4.PRESET
-hreset_n => Djv2z4.PRESET
-hreset_n => Skv2z4.PRESET
-hreset_n => Fxv2z4.PRESET
-hreset_n => Hmv2z4.PRESET
-hreset_n => Wnv2z4.PRESET
-hreset_n => Lpv2z4.PRESET
-hreset_n => I0e3z4.PRESET
-hreset_n => Arv2z4.PRESET
-hreset_n => Duv2z4.PRESET
-hreset_n => Rvv2z4.PRESET
-hreset_n => Psu2z4.PRESET
-hreset_n => R6v2z4.PRESET
-hreset_n => F8v2z4.PRESET
-hreset_n => T9v2z4.PRESET
-hreset_n => Hbv2z4.PRESET
-hreset_n => Psv2z4.PRESET
-hreset_n => Duu2z4.PRESET
-hreset_n => Rvu2z4.PRESET
-hreset_n => Glj2z4.PRESET
-hreset_n => Gto2z4.PRESET
-hreset_n => Ujo2z4.PRESET
-hreset_n => Ggk2z4.PRESET
-hreset_n => Vgq2z4.PRESET
-hreset_n => K2k2z4.PRESET
-hreset_n => Edl2z4.PRESET
-hreset_n => Vmj2z4.PRESET
-hreset_n => Mof3z4.PRESET
-hreset_n => Y1n2z4.PRESET
-hreset_n => Poq2z4.PRESET
-hreset_n => Sog3z4.PRESET
-hreset_n => Pap2z4.PRESET
-hreset_n => Psn2z4.PRESET
-hreset_n => Zxo2z4.PRESET
-hreset_n => Y6o2z4.PRESET
-hreset_n => Ccq2z4.PRESET
-hreset_n => B1q2z4.PRESET
-hreset_n => Wor2z4.PRESET
-hreset_n => Vdr2z4.PRESET
-hreset_n => X1e3z4.PRESET
-hreset_n => Z8s2z4.PRESET
-hreset_n => I4s2z4.PRESET
-hreset_n => Otr2z4.PRESET
-hreset_n => Qml2z4.PRESET
-hreset_n => Wqm2z4.PRESET
-hreset_n => Gip2z4.PRESET
-hreset_n => S2r2z4.PRESET
-hreset_n => H2m2z4.PRESET
-hreset_n => Mhn2z4.PRESET
-hreset_n => Dtj2z4.PRESET
-hreset_n => Ejm2z4.PRESET
-hreset_n => Cgt2z4.PRESET
-hreset_n => Wnt2z4.PRESET
-hreset_n => Lpt2z4.PRESET
-hreset_n => Rht2z4.PRESET
-hreset_n => Art2z4.PRESET
-hreset_n => Pst2z4.PRESET
-hreset_n => Eut2z4.PRESET
-hreset_n => Tvt2z4.PRESET
-hreset_n => Bqf3z4.PRESET
-hreset_n => M3u2z4.PRESET
-hreset_n => B5u2z4.PRESET
-hreset_n => Hqg3z4.PRESET
-hreset_n => Q6u2z4.PRESET
-hreset_n => F8u2z4.PRESET
-hreset_n => U9u2z4.PRESET
-hreset_n => Jbu2z4.PRESET
-hreset_n => Wnu2z4.PRESET
-hreset_n => Ycu2z4.PRESET
-hreset_n => Neu2z4.PRESET
-hreset_n => Cgu2z4.PRESET
-hreset_n => M3e3z4.PRESET
-hreset_n => Rhu2z4.PRESET
-hreset_n => Uku2z4.PRESET
-hreset_n => Imu2z4.PRESET
-hreset_n => Gjt2z4.PRESET
-hreset_n => Ixt2z4.PRESET
-hreset_n => Wyt2z4.PRESET
-hreset_n => K0u2z4.PRESET
-hreset_n => Y1u2z4.PRESET
-hreset_n => Gju2z4.PRESET
-hreset_n => Ukt2z4.PRESET
-hreset_n => Imt2z4.PRESET
-hreset_n => Isi2z4.PRESET
-hreset_n => Vuo2z4.PRESET
-hreset_n => Jlo2z4.PRESET
-hreset_n => Vhk2z4.PRESET
-hreset_n => Kiq2z4.PRESET
-hreset_n => Z3k2z4.PRESET
-hreset_n => Tel2z4.PRESET
-hreset_n => F9j2z4.PRESET
-hreset_n => Fpi2z4.PRESET
-hreset_n => N3n2z4.PRESET
-hreset_n => Eqq2z4.PRESET
-hreset_n => Wrg3z4.PRESET
-hreset_n => Ecp2z4.PRESET
-hreset_n => Eun2z4.PRESET
-hreset_n => Ozo2z4.PRESET
-hreset_n => N8o2z4.PRESET
-hreset_n => Rdq2z4.PRESET
-hreset_n => Q2q2z4.PRESET
-hreset_n => Lqr2z4.PRESET
-hreset_n => Kfr2z4.PRESET
-hreset_n => B5e3z4.PRESET
-hreset_n => Oas2z4.PRESET
-hreset_n => W5s2z4.PRESET
-hreset_n => Cvr2z4.PRESET
-hreset_n => Eol2z4.PRESET
-hreset_n => Ksm2z4.PRESET
-hreset_n => Ujp2z4.PRESET
-hreset_n => G4r2z4.PRESET
-hreset_n => V3m2z4.PRESET
-hreset_n => Ajn2z4.PRESET
-hreset_n => Ruj2z4.PRESET
-hreset_n => Skm2z4.PRESET
-hreset_n => T253z4.PRESET
-hreset_n => Na53z4.PRESET
-hreset_n => Cc53z4.PRESET
-hreset_n => I453z4.PRESET
-hreset_n => Rd53z4.PRESET
-hreset_n => Gf53z4.PRESET
-hreset_n => Vg53z4.PRESET
-hreset_n => Ki53z4.PRESET
-hreset_n => Pgf3z4.PRESET
-hreset_n => Dq53z4.PRESET
-hreset_n => Sr53z4.PRESET
-hreset_n => Vgg3z4.PRESET
-hreset_n => Ht53z4.PRESET
-hreset_n => Wu53z4.PRESET
-hreset_n => Lw53z4.PRESET
-hreset_n => Ay53z4.PRESET
-hreset_n => Na63z4.PRESET
-hreset_n => Pz53z4.PRESET
-hreset_n => E163z4.PRESET
-hreset_n => T263z4.PRESET
-hreset_n => Aud3z4.PRESET
-hreset_n => I463z4.PRESET
-hreset_n => L763z4.PRESET
-hreset_n => Z863z4.PRESET
-hreset_n => X553z4.PRESET
-hreset_n => Zj53z4.PRESET
-hreset_n => Nl53z4.PRESET
-hreset_n => Bn53z4.PRESET
-hreset_n => Po53z4.PRESET
-hreset_n => X563z4.PRESET
-hreset_n => L753z4.PRESET
-hreset_n => Z853z4.PRESET
-hreset_n => Kt33z4.PRESET
-hreset_n => E143z4.PRESET
-hreset_n => T243z4.PRESET
-hreset_n => Zu33z4.PRESET
-hreset_n => I443z4.PRESET
-hreset_n => X543z4.PRESET
-hreset_n => M743z4.PRESET
-hreset_n => B943z4.PRESET
-hreset_n => Eif3z4.PRESET
-hreset_n => Ug43z4.PRESET
-hreset_n => Ji43z4.PRESET
-hreset_n => Kig3z4.PRESET
-hreset_n => Yj43z4.PRESET
-hreset_n => Nl43z4.PRESET
-hreset_n => Cn43z4.PRESET
-hreset_n => Ro43z4.PRESET
-hreset_n => E153z4.PRESET
-hreset_n => Gq43z4.PRESET
-hreset_n => Vr43z4.PRESET
-hreset_n => Kt43z4.PRESET
-hreset_n => Pvd3z4.PRESET
-hreset_n => Zu43z4.PRESET
-hreset_n => Cy43z4.PRESET
-hreset_n => Qz43z4.PRESET
-hreset_n => Ow33z4.PRESET
-hreset_n => Qa43z4.PRESET
-hreset_n => Ec43z4.PRESET
-hreset_n => Sd43z4.PRESET
-hreset_n => Gf43z4.PRESET
-hreset_n => Ow43z4.PRESET
-hreset_n => Cy33z4.PRESET
-hreset_n => Qz33z4.PRESET
-hreset_n => Bk23z4.PRESET
-hreset_n => Vr23z4.PRESET
-hreset_n => Kt23z4.PRESET
-hreset_n => Ql23z4.PRESET
-hreset_n => Zu23z4.PRESET
-hreset_n => Ow23z4.PRESET
-hreset_n => Dy23z4.PRESET
-hreset_n => Sz23z4.PRESET
-hreset_n => Tjf3z4.PRESET
-hreset_n => L733z4.PRESET
-hreset_n => A933z4.PRESET
-hreset_n => Zjg3z4.PRESET
-hreset_n => Pa33z4.PRESET
-hreset_n => Ec33z4.PRESET
-hreset_n => Td33z4.PRESET
-hreset_n => If33z4.PRESET
-hreset_n => Vr33z4.PRESET
-hreset_n => Xg33z4.PRESET
-hreset_n => Mi33z4.PRESET
-hreset_n => Bk33z4.PRESET
-hreset_n => Exd3z4.PRESET
-hreset_n => Ql33z4.PRESET
-hreset_n => To33z4.PRESET
-hreset_n => Hq33z4.PRESET
-hreset_n => Fn23z4.PRESET
-hreset_n => H133z4.PRESET
-hreset_n => V233z4.PRESET
-hreset_n => J433z4.PRESET
-hreset_n => X533z4.PRESET
-hreset_n => Fn33z4.PRESET
-hreset_n => To23z4.PRESET
-hreset_n => Hq23z4.PRESET
-hreset_n => Sa13z4.PRESET
-hreset_n => Mi13z4.PRESET
-hreset_n => Bk13z4.PRESET
-hreset_n => Hc13z4.PRESET
-hreset_n => Ql13z4.PRESET
-hreset_n => Fn13z4.PRESET
-hreset_n => Uo13z4.PRESET
-hreset_n => Jq13z4.PRESET
-hreset_n => Ilf3z4.PRESET
-hreset_n => Cy13z4.PRESET
-hreset_n => Rz13z4.PRESET
-hreset_n => Olg3z4.PRESET
-hreset_n => G123z4.PRESET
-hreset_n => V223z4.PRESET
-hreset_n => K423z4.PRESET
-hreset_n => Z523z4.PRESET
-hreset_n => Mi23z4.PRESET
-hreset_n => O723z4.PRESET
-hreset_n => D923z4.PRESET
-hreset_n => Sa23z4.PRESET
-hreset_n => Tyd3z4.PRESET
-hreset_n => Hc23z4.PRESET
-hreset_n => Kf23z4.PRESET
-hreset_n => Yg23z4.PRESET
-hreset_n => Wd13z4.PRESET
-hreset_n => Yr13z4.PRESET
-hreset_n => Mt13z4.PRESET
-hreset_n => Av13z4.PRESET
-hreset_n => Ow13z4.PRESET
-hreset_n => Wd23z4.PRESET
-hreset_n => Kf13z4.PRESET
-hreset_n => Yg13z4.PRESET
-hreset_n => Ehz2z4.PRESET
-hreset_n => J5i3z4.PRESET
-hreset_n => Yoz2z4.PRESET
-hreset_n => Tiz2z4.PRESET
-hreset_n => Djh3z4.PRESET
-hreset_n => Nqz2z4.PRESET
-hreset_n => Csz2z4.PRESET
-hreset_n => Qji3z4.PRESET
-hreset_n => Qrf3z4.PRESET
-hreset_n => Vzz2z4.PRESET
-hreset_n => A8h3z4.PRESET
-hreset_n => Ltg3z4.PRESET
-hreset_n => Tvh3z4.PRESET
-hreset_n => K103z4.PRESET
-hreset_n => Z203z4.PRESET
-hreset_n => O403z4.PRESET
-hreset_n => Lph3z4.PRESET
-hreset_n => D603z4.PRESET
-hreset_n => Vxf3z4.PRESET
-hreset_n => S703z4.PRESET
-hreset_n => Q6e3z4.PRESET
-hreset_n => H903z4.PRESET
-hreset_n => Rpe3z4.PRESET
-hreset_n => Kc03z4.PRESET
-hreset_n => Ikz2z4.PRESET
-hreset_n => Rtz2z4.PRESET
-hreset_n => Fvz2z4.PRESET
-hreset_n => Twz2z4.PRESET
-hreset_n => Hyz2z4.PRESET
-hreset_n => Wa03z4.PRESET
-hreset_n => Wlz2z4.PRESET
-hreset_n => Knz2z4.PRESET
-hreset_n => Yd03z4.PRESET
-hreset_n => Y6i3z4.PRESET
-hreset_n => Sl03z4.PRESET
-hreset_n => Nf03z4.PRESET
-hreset_n => Skh3z4.PRESET
-hreset_n => Hn03z4.PRESET
-hreset_n => Wo03z4.PRESET
-hreset_n => Fli3z4.PRESET
-hreset_n => Ftf3z4.PRESET
-hreset_n => Pw03z4.PRESET
-hreset_n => P9h3z4.PRESET
-hreset_n => Avg3z4.PRESET
-hreset_n => Ixh3z4.PRESET
-hreset_n => Ey03z4.PRESET
-hreset_n => Tz03z4.PRESET
-hreset_n => I113z4.PRESET
-hreset_n => Arh3z4.PRESET
-hreset_n => X213z4.PRESET
-hreset_n => Kzf3z4.PRESET
-hreset_n => M413z4.PRESET
-hreset_n => F8e3z4.PRESET
-hreset_n => B613z4.PRESET
-hreset_n => Fre3z4.PRESET
-hreset_n => E913z4.PRESET
-hreset_n => Ch03z4.PRESET
-hreset_n => Lq03z4.PRESET
-hreset_n => Zr03z4.PRESET
-hreset_n => Nt03z4.PRESET
-hreset_n => Bv03z4.PRESET
-hreset_n => Q713z4.PRESET
-hreset_n => Qi03z4.PRESET
-hreset_n => Ek03z4.PRESET
-hreset_n => X2j2z4.PRESET
-hreset_n => N8i3z4.PRESET
-hreset_n => Ymo2z4.PRESET
-hreset_n => Rek2z4.PRESET
-hreset_n => Hmh3z4.PRESET
-hreset_n => O5k2z4.PRESET
-hreset_n => Igl2z4.PRESET
-hreset_n => Umi3z4.PRESET
-hreset_n => M4j2z4.PRESET
-hreset_n => C5n2z4.PRESET
-hreset_n => Ebh3z4.PRESET
-hreset_n => Pwg3z4.PRESET
-hreset_n => Xyh3z4.PRESET
-hreset_n => Tvn2z4.PRESET
-hreset_n => D1p2z4.PRESET
-hreset_n => Cao2z4.PRESET
-hreset_n => Psh3z4.PRESET
-hreset_n => F4q2z4.PRESET
-hreset_n => Z0g3z4.PRESET
-hreset_n => Zgr2z4.PRESET
-hreset_n => U9e3z4.PRESET
-hreset_n => Dcs2z4.PRESET
-hreset_n => Tse3z4.PRESET
-hreset_n => Qwr2z4.PRESET
-hreset_n => Cll2z4.PRESET
-hreset_n => Ytm2z4.PRESET
-hreset_n => Ilp2z4.PRESET
-hreset_n => U5r2z4.PRESET
-hreset_n => J5m2z4.PRESET
-hreset_n => Okn2z4.PRESET
-hreset_n => Pfz2z4.PRESET
-hreset_n => Cai3z4.PRESET
-hreset_n => Noo2z4.PRESET
-hreset_n => Aez2z4.PRESET
-hreset_n => Wnh3z4.PRESET
-hreset_n => D7k2z4.PRESET
-hreset_n => Xhl2z4.PRESET
-hreset_n => Joi3z4.PRESET
-hreset_n => Uuf3z4.PRESET
-hreset_n => R6n2z4.PRESET
-hreset_n => Tch3z4.PRESET
-hreset_n => Eyg3z4.PRESET
-hreset_n => M0i3z4.PRESET
-hreset_n => Ixn2z4.PRESET
-hreset_n => S2p2z4.PRESET
-hreset_n => Rbo2z4.PRESET
-hreset_n => Euh3z4.PRESET
-hreset_n => U5q2z4.PRESET
-hreset_n => O2g3z4.PRESET
-hreset_n => Oir2z4.PRESET
-hreset_n => Ibe3z4.PRESET
-hreset_n => Rds2z4.PRESET
-hreset_n => Hue3z4.PRESET
-hreset_n => Eyr2z4.PRESET
-hreset_n => Mcz2z4.PRESET
-hreset_n => Mvm2z4.PRESET
-hreset_n => Wmp2z4.PRESET
-hreset_n => I7r2z4.PRESET
-hreset_n => X6m2z4.PRESET
-hreset_n => Cmn2z4.PRESET
-hreset_n => J0l2z4.PRESET
-hreset_n => Omk2z4.PRESET
-hreset_n => Vvx2z4.PRESET
-hreset_n => Jux2z4.PRESET
-hreset_n => Xsx2z4.PRESET
-hreset_n => Lrx2z4.PRESET
-hreset_n => Zpx2z4.PRESET
-hreset_n => Xyk2z4.PRESET
-hreset_n => Kaf3z4.PRESET
-hreset_n => Nox2z4.PRESET
-hreset_n => Foe3z4.PRESET
-hreset_n => B9g3z4.PRESET
-hreset_n => Zjq2z4.PRESET
-hreset_n => Bnx2z4.PRESET
-hreset_n => Plx2z4.PRESET
-hreset_n => Dkx2z4.PRESET
-hreset_n => Jwf3z4.PRESET
-hreset_n => Rix2z4.PRESET
-hreset_n => Tme3z4.PRESET
-hreset_n => Fhx2z4.PRESET
-hreset_n => Gmd3z4.PRESET
-hreset_n => Ufx2z4.PRESET
-hreset_n => V4d3z4.PRESET
-hreset_n => Jex2z4.PRESET
-hreset_n => Ycx2z4.PRESET
-hreset_n => Nbx2z4.PRESET
-hreset_n => Cax2z4.PRESET
-hreset_n => R8x2z4.PRESET
-hreset_n => G7x2z4.PRESET
-hreset_n => J4x2z4.PRESET
-hreset_n => Fcj2z4.PRESET
-hreset_n => Gci2z4.PRESET
-hreset_n => Igi2z4.PRESET
-hreset_n => Zei2z4.ACLR
-hreset_n => Idk2z4.ACLR
-hreset_n => Z7i2z4.PRESET
-hreset_n => Tdp2z4.ACLR
-hreset_n => Trq2z4.ACLR
-hreset_n => Cam2z4.ACLR
-hreset_n => Uaj2z4.ACLR
-hreset_n => G0w2z4.PRESET
-hreset_n => R1w2z4.PRESET
-hreset_n => Nen2z4.ACLR
-hreset_n => Thm2z4.ACLR
-hreset_n => J6i2z4.ACLR
-hreset_n => H9i2z4.PRESET
-hreset_n => Wai2z4.PRESET
-hreset_n => Pdi2z4.PRESET
-hreset_n => Rhi2z4.PRESET
-hreset_n => Gji2z4.ACLR
-hreset_n => Tki2z4.ACLR
-hreset_n => Emi2z4.ACLR
-hreset_n => Rni2z4.PRESET
-hreset_n => Uqi2z4.ACLR
-hreset_n => Mvi2z4.ACLR
-hreset_n => Ywi2z4.ACLR
-hreset_n => Kyi2z4.PRESET
-hreset_n => Yzi2z4.PRESET
-hreset_n => M1j2z4.PRESET
-hreset_n => B6j2z4.PRESET
-hreset_n => Q7j2z4.PRESET
-hreset_n => Qdj2z4.PRESET
-hreset_n => Ffj2z4.ACLR
-hreset_n => Sgj2z4.ACLR
-hreset_n => Fij2z4.ACLR
-hreset_n => Sjj2z4.PRESET
-hreset_n => Hzj2z4.ACLR
-hreset_n => S8k2z4.PRESET
-hreset_n => Hak2z4.PRESET
-hreset_n => Wbk2z4.ACLR
-hreset_n => Aok2z4.ACLR
-hreset_n => Npk2z4.ACLR
-hreset_n => Ark2z4.ACLR
-hreset_n => Nsk2z4.ACLR
-hreset_n => Auk2z4.PRESET
-hreset_n => Svk2z4.PRESET
-hreset_n => Gxk2z4.ACLR
-hreset_n => V1l2z4.PRESET
-hreset_n => K3l2z4.ACLR
-hreset_n => Z4l2z4.ACLR
-hreset_n => Q6l2z4.ACLR
-hreset_n => H8l2z4.ACLR
-hreset_n => Y9l2z4.ACLR
-hreset_n => Mjl2z4.ACLR
-hreset_n => Usl2z4.ACLR
-hreset_n => Lul2z4.ACLR
-hreset_n => Dwl2z4.PRESET
-hreset_n => Rxl2z4.PRESET
-hreset_n => Fzl2z4.PRESET
-hreset_n => L8m2z4.PRESET
-hreset_n => Nbm2z4.ACLR
-hreset_n => Bdm2z4.PRESET
-hreset_n => Qem2z4.PRESET
-hreset_n => Fgm2z4.PRESET
-hreset_n => Axm2z4.ACLR
-hreset_n => Rym2z4.ACLR
-hreset_n => G8n2z4.ACLR
-hreset_n => X9n2z4.ACLR
-hreset_n => Lbn2z4.PRESET
-hreset_n => Zcn2z4.PRESET
-hreset_n => Qnn2z4.ACLR
-hreset_n => Ipn2z4.ACLR
-hreset_n => Xyn2z4.PRESET
-hreset_n => O0o2z4.PRESET
-hreset_n => F2o2z4.PRESET
-hreset_n => V3o2z4.ACLR
-hreset_n => Gdo2z4.PRESET
-hreset_n => Xeo2z4.PRESET
-hreset_n => Ogo2z4.PRESET
-hreset_n => Cqo2z4.PRESET
-hreset_n => H4p2z4.PRESET
-hreset_n => W5p2z4.PRESET
-hreset_n => L7p2z4.PRESET
-hreset_n => Efp2z4.PRESET
-hreset_n => Kop2z4.ACLR
-hreset_n => Aqp2z4.ACLR
-hreset_n => Qrp2z4.ACLR
-hreset_n => Gtp2z4.PRESET
-hreset_n => Uup2z4.PRESET
-hreset_n => Iwp2z4.PRESET
-hreset_n => Wxp2z4.ACLR
-hreset_n => J7q2z4.PRESET
-hreset_n => Y8q2z4.PRESET
-hreset_n => Llq2z4.PRESET
-hreset_n => Etq2z4.ACLR
-hreset_n => Wuq2z4.ACLR
-hreset_n => Owq2z4.PRESET
-hreset_n => Cyq2z4.PRESET
-hreset_n => Qzq2z4.PRESET
-hreset_n => W8r2z4.ACLR
-hreset_n => Oar2z4.ACLR
-hreset_n => Dkr2z4.PRESET
-hreset_n => Slr2z4.PRESET
-hreset_n => Szr2z4.PRESET
-hreset_n => G1s2z4.PRESET
-hreset_n => Ffs2z4.ACLR
-hreset_n => Vgs2z4.ACLR
-hreset_n => Mis2z4.ACLR
-hreset_n => Dks2z4.ACLR
-hreset_n => Uls2z4.ACLR
-hreset_n => Lns2z4.ACLR
-hreset_n => Cps2z4.ACLR
-hreset_n => Tqs2z4.ACLR
-hreset_n => Kss2z4.ACLR
-hreset_n => Bus2z4.ACLR
-hreset_n => Svs2z4.ACLR
-hreset_n => Jxs2z4.ACLR
-hreset_n => Azs2z4.ACLR
-hreset_n => R0t2z4.ACLR
-hreset_n => I2t2z4.PRESET
-hreset_n => A4t2z4.ACLR
-hreset_n => O5t2z4.PRESET
-hreset_n => Y6t2z4.ACLR
-hreset_n => L8t2z4.ACLR
-hreset_n => Y9t2z4.ACLR
-hreset_n => Mbt2z4.ACLR
-hreset_n => Adt2z4.ACLR
-hreset_n => Pet2z4.ACLR
-hreset_n => Uyv2z4.ACLR
-hreset_n => C3w2z4.ACLR
-hreset_n => S4w2z4.ACLR
-hreset_n => I6w2z4.ACLR
-hreset_n => U7w2z4.ACLR
-hreset_n => G9w2z4.PRESET
-hreset_n => Vaw2z4.ACLR
-hreset_n => Jcw2z4.PRESET
-hreset_n => Ydw2z4.PRESET
-hreset_n => Mfw2z4.PRESET
-hreset_n => Ahw2z4.PRESET
-hreset_n => Oiw2z4.PRESET
-hreset_n => Ckw2z4.PRESET
-hreset_n => Qlw2z4.PRESET
-hreset_n => Enw2z4.PRESET
-hreset_n => Sow2z4.PRESET
-hreset_n => Gqw2z4.PRESET
-hreset_n => Urw2z4.PRESET
-hreset_n => Itw2z4.PRESET
-hreset_n => Xuw2z4.PRESET
-hreset_n => Mww2z4.PRESET
-hreset_n => Byw2z4.PRESET
-hreset_n => Qzw2z4.PRESET
-hreset_n => F1x2z4.PRESET
-hreset_n => U2x2z4.PRESET
-hreset_n => U5x2z4.ACLR
-hreset_n => Hxx2z4.PRESET
-hreset_n => Tyx2z4.PRESET
-hreset_n => F0y2z4.PRESET
-hreset_n => T1y2z4.PRESET
-hreset_n => I3y2z4.PRESET
-hreset_n => W4y2z4.PRESET
-hreset_n => K6y2z4.PRESET
-hreset_n => Y7y2z4.PRESET
-hreset_n => M9y2z4.PRESET
-hreset_n => Bby2z4.PRESET
-hreset_n => Qcy2z4.PRESET
-hreset_n => Fey2z4.PRESET
-hreset_n => Ufy2z4.PRESET
-hreset_n => Jhy2z4.ACLR
-hreset_n => Viy2z4.PRESET
-hreset_n => Jky2z4.PRESET
-hreset_n => Xly2z4.PRESET
-hreset_n => Lny2z4.PRESET
-hreset_n => Zoy2z4.PRESET
-hreset_n => Nqy2z4.PRESET
-hreset_n => Bsy2z4.PRESET
-hreset_n => Pty2z4.PRESET
-hreset_n => Dvy2z4.PRESET
-hreset_n => Swy2z4.PRESET
-hreset_n => Hyy2z4.PRESET
-hreset_n => Wzy2z4.PRESET
-hreset_n => K1z2z4.PRESET
-hreset_n => C3z2z4.PRESET
-hreset_n => U4z2z4.PRESET
-hreset_n => I6z2z4.PRESET
-hreset_n => W7z2z4.PRESET
-hreset_n => K9z2z4.PRESET
-hreset_n => Yaz2z4.PRESET
-hreset_n => U593z4.PRESET
-hreset_n => I793z4.PRESET
-hreset_n => Ym93z4.PRESET
-hreset_n => Jw93z4.PRESET
-hreset_n => Xx93z4.PRESET
-hreset_n => Lz93z4.ACLR
-hreset_n => B1a3z4.ACLR
-hreset_n => P2a3z4.ACLR
-hreset_n => D4a3z4.PRESET
-hreset_n => U5a3z4.PRESET
-hreset_n => L7a3z4.PRESET
-hreset_n => C9a3z4.PRESET
-hreset_n => Taa3z4.PRESET
-hreset_n => Jca3z4.PRESET
-hreset_n => Aea3z4.PRESET
-hreset_n => Qfa3z4.PRESET
-hreset_n => Gha3z4.PRESET
-hreset_n => Wia3z4.PRESET
-hreset_n => Mka3z4.PRESET
-hreset_n => Cma3z4.PRESET
-hreset_n => Tna3z4.ACLR
-hreset_n => Jpa3z4.PRESET
-hreset_n => Ara3z4.PRESET
-hreset_n => Rsa3z4.PRESET
-hreset_n => Iua3z4.PRESET
-hreset_n => Zva3z4.PRESET
-hreset_n => Qxa3z4.PRESET
-hreset_n => Gza3z4.PRESET
-hreset_n => W0b3z4.PRESET
-hreset_n => M2b3z4.PRESET
-hreset_n => C4b3z4.PRESET
-hreset_n => S5b3z4.ACLR
-hreset_n => J7b3z4.PRESET
-hreset_n => Z8b3z4.PRESET
-hreset_n => Pab3z4.ACLR
-hreset_n => Gcb3z4.ACLR
-hreset_n => Xdb3z4.ACLR
-hreset_n => Nfb3z4.PRESET
-hreset_n => Dhb3z4.PRESET
-hreset_n => Tib3z4.ACLR
-hreset_n => Kkb3z4.ACLR
-hreset_n => Bmb3z4.ACLR
-hreset_n => Rnb3z4.ACLR
-hreset_n => Ipb3z4.ACLR
-hreset_n => Zqb3z4.ACLR
-hreset_n => Qsb3z4.ACLR
-hreset_n => Hub3z4.ACLR
-hreset_n => Yvb3z4.ACLR
-hreset_n => Pxb3z4.ACLR
-hreset_n => Gzb3z4.ACLR
-hreset_n => X0c3z4.ACLR
-hreset_n => O2c3z4.ACLR
-hreset_n => F4c3z4.ACLR
-hreset_n => W5c3z4.ACLR
-hreset_n => N7c3z4.ACLR
-hreset_n => E9c3z4.ACLR
-hreset_n => Vac3z4.ACLR
-hreset_n => Mcc3z4.ACLR
-hreset_n => Bec3z4.ACLR
-hreset_n => Qfc3z4.ACLR
-hreset_n => Fhc3z4.ACLR
-hreset_n => Uic3z4.ACLR
-hreset_n => Jkc3z4.ACLR
-hreset_n => Ylc3z4.ACLR
-hreset_n => Nnc3z4.ACLR
-hreset_n => Dpc3z4.ACLR
-hreset_n => Tqc3z4.ACLR
-hreset_n => Jsc3z4.ACLR
-hreset_n => Ztc3z4.ACLR
-hreset_n => Ovc3z4.PRESET
-hreset_n => T1d3z4.PRESET
-hreset_n => H3d3z4.PRESET
-hreset_n => G6d3z4.PRESET
-hreset_n => T7d3z4.ACLR
-hreset_n => J9d3z4.ACLR
-hreset_n => Zad3z4.ACLR
-hreset_n => Pcd3z4.ACLR
-hreset_n => Fed3z4.ACLR
-hreset_n => Vfd3z4.ACLR
-hreset_n => Lhd3z4.ACLR
-hreset_n => Bjd3z4.ACLR
-hreset_n => Rkd3z4.PRESET
-hreset_n => Wce3z4.PRESET
-hreset_n => Lee3z4.ACLR
-hreset_n => Bge3z4.PRESET
-hreset_n => She3z4.PRESET
-hreset_n => Jje3z4.ACLR
-hreset_n => Ble3z4.ACLR
-hreset_n => Vve3z4.ACLR
-hreset_n => Kxe3z4.PRESET
-hreset_n => Aze3z4.PRESET
-hreset_n => Q0f3z4.ACLR
-hreset_n => H2f3z4.ACLR
-hreset_n => W3f3z4.PRESET
-hreset_n => M5f3z4.PRESET
-hreset_n => C7f3z4.ACLR
-hreset_n => T8f3z4.ACLR
-hreset_n => D4g3z4.ACLR
-hreset_n => T5g3z4.PRESET
-hreset_n => K7g3z4.PRESET
-hreset_n => Tzg3z4.PRESET
-hreset_n => I1h3z4.PRESET
-hreset_n => Z2h3z4.PRESET
-hreset_n => Q4h3z4.ACLR
-hreset_n => I6h3z4.ACLR
-hreset_n => Ieh3z4.PRESET
-hreset_n => Zfh3z4.PRESET
-hreset_n => Ohh3z4.PRESET
-hreset_n => B2i3z4.PRESET
-hreset_n => S3i3z4.PRESET
-hreset_n => Rbi3z4.PRESET
-hreset_n => Ddi3z4.PRESET
-hreset_n => Uei3z4.PRESET
-hreset_n => Lgi3z4.PRESET
-hreset_n => Aii3z4.ACLR
-haddr_o[0] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[1] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[2] <= Fvovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[3] <= Ekovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[4] <= Yuovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[5] <= Rxzvx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[6] <= Hszvx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[7] <= S4qvx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[8] <= Z6ovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[9] <= Xxovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[10] <= Jxovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[11] <= Owovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[12] <= Cqovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[13] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[14] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[15] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[16] <= Vpovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[17] <= Bv0wx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[18] <= Fq0wx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[19] <= Ql0wx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[20] <= Ug0wx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[21] <= Fc0wx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[22] <= C70wx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[23] <= Y92wx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[24] <= Y1pvx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[25] <= Rnovx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[26] <= Nhzvx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[27] <= Vezvx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[28] <= V2qvx4.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[29] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[30] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-haddr_o[31] <= haddr_o.DB_MAX_OUTPUT_PORT_TYPE
-hburst_o[0] <= <GND>
-hburst_o[1] <= <GND>
-hburst_o[2] <= <GND>
-hmastlock_o <= <GND>
-hprot_o[0] <= hprot_o.DB_MAX_OUTPUT_PORT_TYPE
-hprot_o[1] <= <VCC>
-hprot_o[2] <= hprot_o.DB_MAX_OUTPUT_PORT_TYPE
-hprot_o[3] <= hprot_o.DB_MAX_OUTPUT_PORT_TYPE
-hsize_o[0] <= hsize_o.DB_MAX_OUTPUT_PORT_TYPE
-hsize_o[1] <= hsize_o.DB_MAX_OUTPUT_PORT_TYPE
-hsize_o[2] <= <GND>
-htrans_o[0] <= <GND>
-htrans_o[1] <= htrans_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[0] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[1] <= O15wx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[2] <= L35wx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[3] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[4] <= Jyuvx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[5] <= Dvuvx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[6] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[7] <= Youvx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[8] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[9] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[10] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[11] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[12] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[13] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[14] <= Bq5wx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[15] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[16] <= O24wx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[17] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[18] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[19] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[20] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[21] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[22] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[23] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[24] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[25] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[26] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[27] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[28] <= Sx3wx4.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[29] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[30] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwdata_o[31] <= hwdata_o.DB_MAX_OUTPUT_PORT_TYPE
-hwrite_o <= hwrite_o.DB_MAX_OUTPUT_PORT_TYPE
-hrdata_i[0] => Wkqvx4.IN1
-hrdata_i[0] => Cvqvx4.IN1
-hrdata_i[0] => Fgowx4.IN1
-hrdata_i[1] => Rzqvx4.IN1
-hrdata_i[1] => Iqrvx4.IN1
-hrdata_i[1] => W9twx4.IN1
-hrdata_i[2] => L3rvx4.IN1
-hrdata_i[2] => Msrvx4.IN1
-hrdata_i[2] => Bxqwx4.IN1
-hrdata_i[3] => U4rvx4.IN1
-hrdata_i[3] => Xurvx4.IN1
-hrdata_i[3] => Mptwx4.IN1
-hrdata_i[4] => D6rvx4.IN1
-hrdata_i[4] => Ixrvx4.IN1
-hrdata_i[4] => Wdwwx4.IN1
-hrdata_i[5] => R6rvx4.IN1
-hrdata_i[5] => Tzrvx4.IN1
-hrdata_i[5] => K1vwx4.IN1
-hrdata_i[6] => O8rvx4.IN1
-hrdata_i[6] => E2svx4.IN1
-hrdata_i[6] => Lppwx4.IN1
-hrdata_i[7] => X9rvx4.IN1
-hrdata_i[7] => P4svx4.IN1
-hrdata_i[7] => Ouwwx4.IN1
-hrdata_i[8] => Zarvx4.IN1
-hrdata_i[8] => A7svx4.IN1
-hrdata_i[8] => Oaowx4.IN1
-hrdata_i[9] => Bcrvx4.IN1
-hrdata_i[9] => L9svx4.IN1
-hrdata_i[9] => R3twx4.IN1
-hrdata_i[10] => Ddrvx4.IN1
-hrdata_i[10] => Wbsvx4.IN1
-hrdata_i[10] => Qnqwx4.IN1
-hrdata_i[11] => Fervx4.IN1
-hrdata_i[11] => Hesvx4.IN1
-hrdata_i[11] => Lltwx4.IN1
-hrdata_i[12] => Hfrvx4.IN1
-hrdata_i[12] => Sgsvx4.IN1
-hrdata_i[12] => J3wwx4.IN1
-hrdata_i[13] => Udpvx4.IN1
-hrdata_i[13] => Jgrvx4.IN1
-hrdata_i[13] => Wmuwx4.IN1
-hrdata_i[14] => Hmrvx4.IN1
-hrdata_i[14] => Djsvx4.IN1
-hrdata_i[14] => Qapwx4.IN1
-hrdata_i[15] => Oapvx4.IN1
-hrdata_i[15] => Cnrvx4.IN1
-hrdata_i[15] => Ofxwx4.IN1
-hrdata_i[16] => Dlqvx4.IN1
-hrdata_i[16] => S7mwx4.IN1
-hrdata_i[16] => U6owx4.IN1
-hrdata_i[17] => Pqrvx4.IN1
-hrdata_i[17] => N8mwx4.IN1
-hrdata_i[17] => Mbtwx4.IN1
-hrdata_i[18] => Tsrvx4.IN1
-hrdata_i[18] => B9mwx4.IN1
-hrdata_i[18] => P5qwx4.IN1
-hrdata_i[19] => Evrvx4.IN1
-hrdata_i[19] => P9mwx4.IN1
-hrdata_i[19] => Nttwx4.IN1
-hrdata_i[20] => Pxrvx4.IN1
-hrdata_i[20] => Damwx4.IN1
-hrdata_i[20] => Sjvwx4.IN1
-hrdata_i[21] => A0svx4.IN1
-hrdata_i[21] => Ramwx4.IN1
-hrdata_i[21] => C5uwx4.IN1
-hrdata_i[22] => L2svx4.IN1
-hrdata_i[22] => Fbmwx4.IN1
-hrdata_i[22] => D0pwx4.IN1
-hrdata_i[23] => W4svx4.IN1
-hrdata_i[23] => Tbmwx4.IN1
-hrdata_i[23] => D6xwx4.IN1
-hrdata_i[24] => H7svx4.IN1
-hrdata_i[24] => Hcmwx4.IN1
-hrdata_i[24] => Qbowx4.IN1
-hrdata_i[25] => S9svx4.IN1
-hrdata_i[25] => Vcmwx4.IN1
-hrdata_i[25] => Xdtwx4.IN1
-hrdata_i[26] => Dcsvx4.IN1
-hrdata_i[26] => Jdmwx4.IN1
-hrdata_i[26] => T7qwx4.IN1
-hrdata_i[27] => Oesvx4.IN1
-hrdata_i[27] => Xdmwx4.IN1
-hrdata_i[27] => Mwtwx4.IN1
-hrdata_i[28] => Zgsvx4.IN1
-hrdata_i[28] => Lemwx4.IN1
-hrdata_i[28] => G5wwx4.IN1
-hrdata_i[29] => Bepvx4.IN1
-hrdata_i[29] => Zemwx4.IN1
-hrdata_i[29] => Touwx4.IN1
-hrdata_i[30] => Fksvx4.IN1
-hrdata_i[30] => Nfmwx4.IN1
-hrdata_i[30] => Gcpwx4.IN1
-hrdata_i[31] => Cbpvx4.IN1
-hrdata_i[31] => Bgmwx4.IN1
-hrdata_i[31] => Msxwx4.IN1
-hready_i => Q5ovx4.IN1
-hready_i => Kgovx4.IN1
-hready_i => Thovx4.IN1
-hready_i => Cjovx4.IN1
-hready_i => Skovx4.IN1
-hready_i => Lqpvx4.IN1
-hready_i => Ziqvx4.OUTPUTSELECT
-hready_i => Gosvx4.IN1
-hready_i => U6wvx4.IN1
-hready_i => Rfpvx4.IN1
-hready_i => Upyvx4.IN1
-hready_i => Vtyvx4.IN1
-hready_i => U5qvx4.IN1
-hready_i => Ro1wx4.IN1
-hready_i => Rg2wx4.IN1
-hready_i => Z9zvx4.IN1
-hready_i => Df3wx4.IN1
-hready_i => J86wx4.IN1
-hready_i => Poewx4.IN1
-hready_i => Ewiwx4.IN1
-hready_i => M6kwx4.IN1
-hready_i => Xslwx4.IN1
-hready_i => J5vvx4.IN1
-hready_i => Mdrwx4.IN1
-hready_i => Yafwx4.IN1
-hready_i => Qllwx4.IN1
-hready_i => K6yvx4.IN1
-hready_i => Qaiwx4.IN1
-hready_i => Obovx4.IN1
-hready_i => A3pvx4.IN1
-hready_i => Q4pvx4.IN1
-hready_i => Vvpvx4.OUTPUTSELECT
-hready_i => B6qvx4.IN1
-hready_i => Ysqvx4.IN1
-hready_i => Nxqvx4.IN1
-hready_i => Dn2wx4.IN1
-hready_i => Xaiwx4.OUTPUTSELECT
-hready_i => Kkjwx4.IN1
-hready_i => Trkwx4.IN1
-hready_i => Stlwx4.IN1
-hready_i => Bpsvx4.IN1
-hready_i => Qmywx4.IN1
-hready_i => Cmywx4.IN1
-hready_i => Wai2z4.ENA
-hready_i => Tki2z4.ENA
-hready_i => Ffj2z4.ENA
-hready_i => Sgj2z4.ENA
-hready_i => Fij2z4.ENA
-hready_i => Ark2z4.ENA
-hready_i => Y9t2z4.ENA
-hready_i => Pet2z4.ENA
-hready_i => G9w2z4.ENA
-hready_i => Vaw2z4.ENA
-hready_i => Hxx2z4.ENA
-hready_i => Aii3z4.ENA
-hresp_i => Y7qvx4.IN1
-hresp_i => Igmwx4.IN1
-hresp_i => Iiywx4.IN1
-nmi_i => I1vvx4.IN1
-nmi_i => Nx4wx4.IN1
-irq_i[0] => Gmnvx4.IN1
-irq_i[0] => Wy4wx4.IN1
-irq_i[1] => Y4mvx4.IN1
-irq_i[1] => T05wx4.IN1
-irq_i[2] => Bamvx4.IN1
-irq_i[2] => Q25wx4.IN1
-irq_i[3] => Iamvx4.IN1
-irq_i[3] => G45wx4.IN1
-irq_i[4] => S8mvx4.IN1
-irq_i[4] => W55wx4.IN1
-irq_i[5] => Z8mvx4.IN1
-irq_i[5] => M75wx4.IN1
-irq_i[6] => G9mvx4.IN1
-irq_i[6] => C95wx4.IN1
-irq_i[7] => N9mvx4.IN1
-irq_i[7] => Sa5wx4.IN1
-irq_i[8] => O6mvx4.IN1
-irq_i[8] => Ic5wx4.IN1
-irq_i[9] => V6mvx4.IN1
-irq_i[9] => Te5wx4.IN1
-irq_i[10] => C7mvx4.IN1
-irq_i[10] => Qg5wx4.IN1
-irq_i[11] => J7mvx4.IN1
-irq_i[11] => Ui5wx4.IN1
-irq_i[12] => A6mvx4.IN1
-irq_i[12] => Yk5wx4.IN1
-irq_i[13] => Dbmvx4.IN1
-irq_i[13] => Cn5wx4.IN1
-irq_i[14] => R4mvx4.IN1
-irq_i[14] => Gp5wx4.IN1
-irq_i[15] => Kbmvx4.IN1
-irq_i[15] => Rr5wx4.IN1
-txev_o <= txev_o.DB_MAX_OUTPUT_PORT_TYPE
-rxev_i => Rt3wx4.IN1
-lockup_o <= Z5pvx4.DB_MAX_OUTPUT_PORT_TYPE
-sys_reset_req_o <= Ypi3z4.DB_MAX_OUTPUT_PORT_TYPE
-sleeping_o <= sleeping_o.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[0] <= Unm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[1] <= Txj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[2] <= Vu93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[3] <= Yb93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[4] <= Ka93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[5] <= W893z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[6] <= G493z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[7] <= Grl2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[8] <= Qyc3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[9] <= Cxc3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[10] <= Gt93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[11] <= Snd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[12] <= Rr93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[13] <= Cq93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[14] <= No93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[15] <= E0d3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[16] <= Jl93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[17] <= Uj93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[18] <= Fi93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[19] <= Qg93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[20] <= Nag3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[21] <= Bf93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[22] <= Md93z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[23] <= Wbf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[24] <= R293z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[25] <= C193z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[26] <= Nz83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[27] <= Yx83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[28] <= Zkk2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[29] <= Jw83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[30] <= Uu83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r0_o[31] <= Xti2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[0] <= Gmm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[1] <= Fwj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[2] <= Yfn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[3] <= T0m2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[4] <= E1r2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[5] <= Sgp2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[6] <= Ipm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[7] <= Spl2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[8] <= Asr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[9] <= U2s2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[10] <= K7s2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[11] <= Hpd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[12] <= Gcr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[13] <= Hnr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[14] <= Mzp2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[15] <= Naq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[16] <= J5o2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[17] <= Kwo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[18] <= Arn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[19] <= A9p2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[20] <= Ccg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[21] <= Anq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[22] <= J0n2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[23] <= Orj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[24] <= Zpj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[25] <= Pbl2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[26] <= V0k2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[27] <= Gfq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[28] <= Kjk2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[29] <= Fio2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[30] <= Rro2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r1_o[31] <= Koj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[0] <= Rr73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[1] <= Dq73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[2] <= Po83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[3] <= H783z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[4] <= T583z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[5] <= F483z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[6] <= R283z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[7] <= Po73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[8] <= Rr83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[9] <= Dq83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[10] <= An83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[11] <= Wqd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[12] <= Ll83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[13] <= Wj83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[14] <= Hi83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[15] <= Ft83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[16] <= Sg83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[17] <= Df83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[18] <= Od83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[19] <= Zb83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[20] <= Rdg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[21] <= Ka83z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[22] <= V883z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[23] <= Ldf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[24] <= C183z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[25] <= Nz73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[26] <= Yx73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[27] <= Jw73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[28] <= An73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[29] <= Uu73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[30] <= Ft73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r2_o[31] <= Ll73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[0] <= Ii63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[1] <= Ug63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[2] <= Gf73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[3] <= Yx63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[4] <= Kw63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[5] <= Wu63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[6] <= It63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[7] <= Gf63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[8] <= Ii73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[9] <= Ug73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[10] <= Rd73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[11] <= Lsd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[12] <= Cc73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[13] <= Na73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[14] <= Y873z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[15] <= Wj73z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[16] <= J773z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[17] <= U573z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[18] <= F473z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[19] <= Q273z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[20] <= Gfg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[21] <= B173z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[22] <= Mz63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[23] <= Aff3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[24] <= Tr63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[25] <= Eq63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[26] <= Po63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[27] <= An63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[28] <= Rd63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[29] <= Ll63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[30] <= Wj63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r3_o[31] <= Cc63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[0] <= Rvu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[1] <= Duu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[2] <= Psv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[3] <= Hbv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[4] <= T9v2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[5] <= F8v2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[6] <= R6v2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[7] <= Psu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[8] <= Rvv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[9] <= Duv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[10] <= Arv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[11] <= I0e3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[12] <= Lpv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[13] <= Wnv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[14] <= Hmv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[15] <= Fxv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[16] <= Skv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[17] <= Djv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[18] <= Ohv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[19] <= Zfv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[20] <= Dng3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[21] <= Kev2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[22] <= Vcv2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[23] <= Xmf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[24] <= C5v2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[25] <= N3v2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[26] <= Y1v2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[27] <= J0v2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[28] <= Aru2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[29] <= Uyu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[30] <= Fxu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r4_o[31] <= Lpu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[0] <= Ejm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[1] <= Dtj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[2] <= Mhn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[3] <= H2m2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[4] <= S2r2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[5] <= Gip2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[6] <= Wqm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[7] <= Qml2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[8] <= Otr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[9] <= I4s2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[10] <= Z8s2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[11] <= X1e3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[12] <= Vdr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[13] <= Wor2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[14] <= B1q2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[15] <= Ccq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[16] <= Y6o2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[17] <= Zxo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[18] <= Psn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[19] <= Pap2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[20] <= Sog3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[21] <= Poq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[22] <= Y1n2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[23] <= Mof3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[24] <= Vmj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[25] <= Edl2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[26] <= K2k2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[27] <= Vgq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[28] <= Ggk2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[29] <= Ujo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[30] <= Gto2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r5_o[31] <= Glj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[0] <= Imt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[1] <= Ukt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[2] <= Gju2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[3] <= Y1u2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[4] <= K0u2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[5] <= Wyt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[6] <= Ixt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[7] <= Gjt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[8] <= Imu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[9] <= Uku2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[10] <= Rhu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[11] <= M3e3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[12] <= Cgu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[13] <= Neu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[14] <= Ycu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[15] <= Wnu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[16] <= Jbu2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[17] <= U9u2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[18] <= F8u2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[19] <= Q6u2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[20] <= Hqg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[21] <= B5u2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[22] <= M3u2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[23] <= Bqf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[24] <= Tvt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[25] <= Eut2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[26] <= Pst2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[27] <= Art2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[28] <= Rht2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[29] <= Lpt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[30] <= Wnt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r6_o[31] <= Cgt2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[0] <= Skm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[1] <= Ruj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[2] <= Ajn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[3] <= V3m2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[4] <= G4r2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[5] <= Ujp2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[6] <= Ksm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[7] <= Eol2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[8] <= Cvr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[9] <= W5s2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[10] <= Oas2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[11] <= B5e3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[12] <= Kfr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[13] <= Lqr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[14] <= Q2q2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[15] <= Rdq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[16] <= N8o2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[17] <= Ozo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[18] <= Eun2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[19] <= Ecp2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[20] <= Wrg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[21] <= Eqq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[22] <= N3n2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[23] <= Fpi2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[24] <= F9j2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[25] <= Tel2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[26] <= Z3k2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[27] <= Kiq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[28] <= Vhk2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[29] <= Jlo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[30] <= Vuo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r7_o[31] <= Isi2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[0] <= Z853z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[1] <= L753z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[2] <= X563z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[3] <= Po53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[4] <= Bn53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[5] <= Nl53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[6] <= Zj53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[7] <= X553z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[8] <= Z863z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[9] <= L763z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[10] <= I463z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[11] <= Aud3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[12] <= T263z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[13] <= E163z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[14] <= Pz53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[15] <= Na63z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[16] <= Ay53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[17] <= Lw53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[18] <= Wu53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[19] <= Ht53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[20] <= Vgg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[21] <= Sr53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[22] <= Dq53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[23] <= Pgf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[24] <= Ki53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[25] <= Vg53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[26] <= Gf53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[27] <= Rd53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[28] <= I453z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[29] <= Cc53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[30] <= Na53z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r8_o[31] <= T253z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[0] <= Qz33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[1] <= Cy33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[2] <= Ow43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[3] <= Gf43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[4] <= Sd43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[5] <= Ec43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[6] <= Qa43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[7] <= Ow33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[8] <= Qz43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[9] <= Cy43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[10] <= Zu43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[11] <= Pvd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[12] <= Kt43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[13] <= Vr43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[14] <= Gq43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[15] <= E153z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[16] <= Ro43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[17] <= Cn43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[18] <= Nl43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[19] <= Yj43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[20] <= Kig3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[21] <= Ji43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[22] <= Ug43z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[23] <= Eif3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[24] <= B943z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[25] <= M743z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[26] <= X543z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[27] <= I443z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[28] <= Zu33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[29] <= T243z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[30] <= E143z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r9_o[31] <= Kt33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[0] <= Hq23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[1] <= To23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[2] <= Fn33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[3] <= X533z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[4] <= J433z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[5] <= V233z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[6] <= H133z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[7] <= Fn23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[8] <= Hq33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[9] <= To33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[10] <= Ql33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[11] <= Exd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[12] <= Bk33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[13] <= Mi33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[14] <= Xg33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[15] <= Vr33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[16] <= If33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[17] <= Td33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[18] <= Ec33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[19] <= Pa33z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[20] <= Zjg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[21] <= A933z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[22] <= L733z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[23] <= Tjf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[24] <= Sz23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[25] <= Dy23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[26] <= Ow23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[27] <= Zu23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[28] <= Ql23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[29] <= Kt23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[30] <= Vr23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r10_o[31] <= Bk23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[0] <= Yg13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[1] <= Kf13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[2] <= Wd23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[3] <= Ow13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[4] <= Av13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[5] <= Mt13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[6] <= Yr13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[7] <= Wd13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[8] <= Yg23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[9] <= Kf23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[10] <= Hc23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[11] <= Tyd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[12] <= Sa23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[13] <= D923z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[14] <= O723z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[15] <= Mi23z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[16] <= Z523z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[17] <= K423z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[18] <= V223z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[19] <= G123z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[20] <= Olg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[21] <= Rz13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[22] <= Cy13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[23] <= Ilf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[24] <= Jq13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[25] <= Uo13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[26] <= Fn13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[27] <= Ql13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[28] <= Hc13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[29] <= Bk13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[30] <= Mi13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r11_o[31] <= Sa13z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[0] <= Knz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[1] <= Wlz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[2] <= Wa03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[3] <= Hyz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[4] <= Twz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[5] <= Fvz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[6] <= Rtz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[7] <= Ikz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[8] <= Kc03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[9] <= Rpe3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[10] <= H903z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[11] <= Q6e3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[12] <= S703z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[13] <= Vxf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[14] <= D603z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[15] <= Lph3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[16] <= O403z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[17] <= Z203z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[18] <= K103z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[19] <= Tvh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[20] <= Ltg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[21] <= A8h3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[22] <= Vzz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[23] <= Qrf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[24] <= Qji3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[25] <= Csz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[26] <= Nqz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[27] <= Djh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[28] <= Tiz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[29] <= Yoz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[30] <= J5i3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r12_o[31] <= Ehz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[0] <= Ek03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[1] <= Qi03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[2] <= Q713z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[3] <= Bv03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[4] <= Nt03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[5] <= Zr03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[6] <= Lq03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[7] <= Ch03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[8] <= E913z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[9] <= Fre3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[10] <= B613z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[11] <= F8e3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[12] <= M413z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[13] <= Kzf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[14] <= X213z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[15] <= Arh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[16] <= I113z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[17] <= Tz03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[18] <= Ey03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[19] <= Ixh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[20] <= Avg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[21] <= P9h3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[22] <= Pw03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[23] <= Ftf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[24] <= Fli3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[25] <= Wo03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[26] <= Hn03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[27] <= Skh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[28] <= Nf03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[29] <= Sl03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[30] <= Y6i3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_r14_o[31] <= Yd03z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[0] <= Okn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[1] <= J5m2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[2] <= U5r2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[3] <= Ilp2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[4] <= Ytm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[5] <= Cll2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[6] <= Qwr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[7] <= Tse3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[8] <= Dcs2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[9] <= U9e3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[10] <= Zgr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[11] <= Z0g3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[12] <= F4q2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[13] <= Psh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[14] <= Cao2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[15] <= D1p2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[16] <= Tvn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[17] <= Xyh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[18] <= Pwg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[19] <= Ebh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[20] <= C5n2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[21] <= M4j2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[22] <= Umi3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[23] <= Igl2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[24] <= O5k2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[25] <= Hmh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[26] <= Rek2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[27] <= Ymo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[28] <= N8i3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_msp_o[29] <= X2j2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[0] <= Cmn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[1] <= X6m2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[2] <= I7r2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[3] <= Wmp2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[4] <= Mvm2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[5] <= Mcz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[6] <= Eyr2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[7] <= Hue3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[8] <= Rds2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[9] <= Ibe3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[10] <= Oir2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[11] <= O2g3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[12] <= U5q2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[13] <= Euh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[14] <= Rbo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[15] <= S2p2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[16] <= Ixn2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[17] <= M0i3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[18] <= Eyg3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[19] <= Tch3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[20] <= R6n2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[21] <= Uuf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[22] <= Joi3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[23] <= Xhl2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[24] <= D7k2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[25] <= Wnh3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[26] <= Aez2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[27] <= Noo2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[28] <= Cai3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_psp_o[29] <= Pfz2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[0] <= Fcj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[1] <= J4x2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[2] <= G7x2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[3] <= R8x2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[4] <= Cax2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[5] <= Nbx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[6] <= Ycx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[7] <= Jex2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[8] <= V4d3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[9] <= Ufx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[10] <= Gmd3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[11] <= Fhx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[12] <= Tme3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[13] <= Rix2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[14] <= Jwf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[15] <= Dkx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[16] <= Plx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[17] <= Bnx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[18] <= Zjq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[19] <= B9g3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[20] <= Foe3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[21] <= Nox2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[22] <= Kaf3z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[23] <= Xyk2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[24] <= Zpx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[25] <= Lrx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[26] <= Xsx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[27] <= Jux2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[28] <= Vvx2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[29] <= Omk2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_pc_o[30] <= J0l2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_apsr_o[0] <= Idk2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_apsr_o[1] <= Zei2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_apsr_o[2] <= Igi2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_apsr_o[3] <= Gci2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_tbit_o <= Z7i2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_ipsr_o[0] <= R1w2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_ipsr_o[1] <= G0w2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_ipsr_o[2] <= Uaj2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_ipsr_o[3] <= Cam2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_ipsr_o[4] <= Trq2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_ipsr_o[5] <= Tdp2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_control_o <= Nen2z4.DB_MAX_OUTPUT_PORT_TYPE
-vis_primask_o <= Thm2z4.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1
-HCLK => mux_sel[0].CLK
-HCLK => mux_sel[1].CLK
-HCLK => mux_sel[2].CLK
-HRESETn => mux_sel[0].ACLR
-HRESETn => mux_sel[1].ACLR
-HRESETn => mux_sel[2].ACLR
-HADDR[0] => LessThan0.IN64
-HADDR[0] => LessThan1.IN64
-HADDR[1] => LessThan0.IN63
-HADDR[1] => LessThan1.IN63
-HADDR[2] => LessThan0.IN62
-HADDR[2] => LessThan1.IN62
-HADDR[3] => LessThan0.IN61
-HADDR[3] => LessThan1.IN61
-HADDR[4] => LessThan0.IN60
-HADDR[4] => LessThan1.IN60
-HADDR[5] => LessThan0.IN59
-HADDR[5] => LessThan1.IN59
-HADDR[6] => LessThan0.IN58
-HADDR[6] => LessThan1.IN58
-HADDR[7] => LessThan0.IN57
-HADDR[7] => LessThan1.IN57
-HADDR[8] => LessThan0.IN56
-HADDR[8] => LessThan1.IN56
-HADDR[9] => LessThan0.IN55
-HADDR[9] => LessThan1.IN55
-HADDR[10] => LessThan0.IN54
-HADDR[10] => LessThan1.IN54
-HADDR[11] => LessThan0.IN53
-HADDR[11] => LessThan1.IN53
-HADDR[12] => LessThan0.IN52
-HADDR[12] => LessThan1.IN52
-HADDR[13] => LessThan0.IN51
-HADDR[13] => LessThan1.IN51
-HADDR[14] => LessThan0.IN50
-HADDR[14] => LessThan1.IN50
-HADDR[15] => LessThan0.IN49
-HADDR[15] => LessThan1.IN49
-HADDR[16] => LessThan0.IN48
-HADDR[16] => LessThan1.IN48
-HADDR[17] => LessThan0.IN47
-HADDR[17] => LessThan1.IN47
-HADDR[18] => LessThan0.IN46
-HADDR[18] => LessThan1.IN46
-HADDR[19] => LessThan0.IN45
-HADDR[19] => LessThan1.IN45
-HADDR[20] => LessThan0.IN44
-HADDR[20] => LessThan1.IN44
-HADDR[21] => LessThan0.IN43
-HADDR[21] => LessThan1.IN43
-HADDR[22] => LessThan0.IN42
-HADDR[22] => LessThan1.IN42
-HADDR[23] => LessThan0.IN41
-HADDR[23] => LessThan1.IN41
-HADDR[24] => LessThan0.IN40
-HADDR[24] => LessThan1.IN40
-HADDR[25] => LessThan0.IN39
-HADDR[25] => LessThan1.IN39
-HADDR[26] => LessThan0.IN38
-HADDR[26] => LessThan1.IN38
-HADDR[27] => LessThan0.IN37
-HADDR[27] => LessThan1.IN37
-HADDR[28] => LessThan0.IN36
-HADDR[28] => LessThan1.IN36
-HADDR[29] => LessThan0.IN35
-HADDR[29] => LessThan1.IN35
-HADDR[30] => LessThan0.IN34
-HADDR[30] => LessThan1.IN34
-HADDR[31] => LessThan0.IN33
-HADDR[31] => LessThan1.IN33
-HSEL_SIGNALS[0] <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
-HSEL_SIGNALS[1] <= HSEL_SIGNALS.DB_MAX_OUTPUT_PORT_TYPE
-HSEL_SIGNALS[2] <= HSEL_SIGNALS.DB_MAX_OUTPUT_PORT_TYPE
-HREADYOUT_SIGNALS[0] => HREADY.DATAB
-HREADYOUT_SIGNALS[1] => HREADY.DATAB
-HREADYOUT_SIGNALS[2] => HREADY.DATAB
-HRDATA_SIGNALS[0][0] => HRDATA.DATAB
-HRDATA_SIGNALS[0][1] => HRDATA.DATAB
-HRDATA_SIGNALS[0][2] => HRDATA.DATAB
-HRDATA_SIGNALS[0][3] => HRDATA.DATAB
-HRDATA_SIGNALS[0][4] => HRDATA.DATAB
-HRDATA_SIGNALS[0][5] => HRDATA.DATAB
-HRDATA_SIGNALS[0][6] => HRDATA.DATAB
-HRDATA_SIGNALS[0][7] => HRDATA.DATAB
-HRDATA_SIGNALS[0][8] => HRDATA.DATAB
-HRDATA_SIGNALS[0][9] => HRDATA.DATAB
-HRDATA_SIGNALS[0][10] => HRDATA.DATAB
-HRDATA_SIGNALS[0][11] => HRDATA.DATAB
-HRDATA_SIGNALS[0][12] => HRDATA.DATAB
-HRDATA_SIGNALS[0][13] => HRDATA.DATAB
-HRDATA_SIGNALS[0][14] => HRDATA.DATAB
-HRDATA_SIGNALS[0][15] => HRDATA.DATAB
-HRDATA_SIGNALS[0][16] => HRDATA.DATAB
-HRDATA_SIGNALS[0][17] => HRDATA.DATAB
-HRDATA_SIGNALS[0][18] => HRDATA.DATAB
-HRDATA_SIGNALS[0][19] => HRDATA.DATAB
-HRDATA_SIGNALS[0][20] => HRDATA.DATAB
-HRDATA_SIGNALS[0][21] => HRDATA.DATAB
-HRDATA_SIGNALS[0][22] => HRDATA.DATAB
-HRDATA_SIGNALS[0][23] => HRDATA.DATAB
-HRDATA_SIGNALS[0][24] => HRDATA.DATAB
-HRDATA_SIGNALS[0][25] => HRDATA.DATAB
-HRDATA_SIGNALS[0][26] => HRDATA.DATAB
-HRDATA_SIGNALS[0][27] => HRDATA.DATAB
-HRDATA_SIGNALS[0][28] => HRDATA.DATAB
-HRDATA_SIGNALS[0][29] => HRDATA.DATAB
-HRDATA_SIGNALS[0][30] => HRDATA.DATAB
-HRDATA_SIGNALS[0][31] => HRDATA.DATAB
-HRDATA_SIGNALS[1][0] => HRDATA.DATAB
-HRDATA_SIGNALS[1][1] => HRDATA.DATAB
-HRDATA_SIGNALS[1][2] => HRDATA.DATAB
-HRDATA_SIGNALS[1][3] => HRDATA.DATAB
-HRDATA_SIGNALS[1][4] => HRDATA.DATAB
-HRDATA_SIGNALS[1][5] => HRDATA.DATAB
-HRDATA_SIGNALS[1][6] => HRDATA.DATAB
-HRDATA_SIGNALS[1][7] => HRDATA.DATAB
-HRDATA_SIGNALS[1][8] => HRDATA.DATAB
-HRDATA_SIGNALS[1][9] => HRDATA.DATAB
-HRDATA_SIGNALS[1][10] => HRDATA.DATAB
-HRDATA_SIGNALS[1][11] => HRDATA.DATAB
-HRDATA_SIGNALS[1][12] => HRDATA.DATAB
-HRDATA_SIGNALS[1][13] => HRDATA.DATAB
-HRDATA_SIGNALS[1][14] => HRDATA.DATAB
-HRDATA_SIGNALS[1][15] => HRDATA.DATAB
-HRDATA_SIGNALS[1][16] => HRDATA.DATAB
-HRDATA_SIGNALS[1][17] => HRDATA.DATAB
-HRDATA_SIGNALS[1][18] => HRDATA.DATAB
-HRDATA_SIGNALS[1][19] => HRDATA.DATAB
-HRDATA_SIGNALS[1][20] => HRDATA.DATAB
-HRDATA_SIGNALS[1][21] => HRDATA.DATAB
-HRDATA_SIGNALS[1][22] => HRDATA.DATAB
-HRDATA_SIGNALS[1][23] => HRDATA.DATAB
-HRDATA_SIGNALS[1][24] => HRDATA.DATAB
-HRDATA_SIGNALS[1][25] => HRDATA.DATAB
-HRDATA_SIGNALS[1][26] => HRDATA.DATAB
-HRDATA_SIGNALS[1][27] => HRDATA.DATAB
-HRDATA_SIGNALS[1][28] => HRDATA.DATAB
-HRDATA_SIGNALS[1][29] => HRDATA.DATAB
-HRDATA_SIGNALS[1][30] => HRDATA.DATAB
-HRDATA_SIGNALS[1][31] => HRDATA.DATAB
-HRDATA_SIGNALS[2][0] => HRDATA.DATAB
-HRDATA_SIGNALS[2][1] => HRDATA.DATAB
-HRDATA_SIGNALS[2][2] => HRDATA.DATAB
-HRDATA_SIGNALS[2][3] => HRDATA.DATAB
-HRDATA_SIGNALS[2][4] => HRDATA.DATAB
-HRDATA_SIGNALS[2][5] => HRDATA.DATAB
-HRDATA_SIGNALS[2][6] => HRDATA.DATAB
-HRDATA_SIGNALS[2][7] => HRDATA.DATAB
-HRDATA_SIGNALS[2][8] => HRDATA.DATAB
-HRDATA_SIGNALS[2][9] => HRDATA.DATAB
-HRDATA_SIGNALS[2][10] => HRDATA.DATAB
-HRDATA_SIGNALS[2][11] => HRDATA.DATAB
-HRDATA_SIGNALS[2][12] => HRDATA.DATAB
-HRDATA_SIGNALS[2][13] => HRDATA.DATAB
-HRDATA_SIGNALS[2][14] => HRDATA.DATAB
-HRDATA_SIGNALS[2][15] => HRDATA.DATAB
-HRDATA_SIGNALS[2][16] => HRDATA.DATAB
-HRDATA_SIGNALS[2][17] => HRDATA.DATAB
-HRDATA_SIGNALS[2][18] => HRDATA.DATAB
-HRDATA_SIGNALS[2][19] => HRDATA.DATAB
-HRDATA_SIGNALS[2][20] => HRDATA.DATAB
-HRDATA_SIGNALS[2][21] => HRDATA.DATAB
-HRDATA_SIGNALS[2][22] => HRDATA.DATAB
-HRDATA_SIGNALS[2][23] => HRDATA.DATAB
-HRDATA_SIGNALS[2][24] => HRDATA.DATAB
-HRDATA_SIGNALS[2][25] => HRDATA.DATAB
-HRDATA_SIGNALS[2][26] => HRDATA.DATAB
-HRDATA_SIGNALS[2][27] => HRDATA.DATAB
-HRDATA_SIGNALS[2][28] => HRDATA.DATAB
-HRDATA_SIGNALS[2][29] => HRDATA.DATAB
-HRDATA_SIGNALS[2][30] => HRDATA.DATAB
-HRDATA_SIGNALS[2][31] => HRDATA.DATAB
-HREADY <= HREADY.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[0] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[1] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[2] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[3] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[4] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[5] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[6] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[7] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[8] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[9] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[10] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[11] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[12] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[13] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[14] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[15] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[16] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[17] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[18] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[19] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[20] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[21] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[22] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[23] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[24] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[25] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[26] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[27] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[28] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[29] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[30] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[31] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1
-HSEL => always1.IN0
-HCLK => memory.we_a.CLK
-HCLK => memory.waddr_a[11].CLK
-HCLK => memory.waddr_a[10].CLK
-HCLK => memory.waddr_a[9].CLK
-HCLK => memory.waddr_a[8].CLK
-HCLK => memory.waddr_a[7].CLK
-HCLK => memory.waddr_a[6].CLK
-HCLK => memory.waddr_a[5].CLK
-HCLK => memory.waddr_a[4].CLK
-HCLK => memory.waddr_a[3].CLK
-HCLK => memory.waddr_a[2].CLK
-HCLK => memory.waddr_a[1].CLK
-HCLK => memory.waddr_a[0].CLK
-HCLK => memory.data_a[31].CLK
-HCLK => memory.data_a[30].CLK
-HCLK => memory.data_a[29].CLK
-HCLK => memory.data_a[28].CLK
-HCLK => memory.data_a[27].CLK
-HCLK => memory.data_a[26].CLK
-HCLK => memory.data_a[25].CLK
-HCLK => memory.data_a[24].CLK
-HCLK => memory.data_a[23].CLK
-HCLK => memory.data_a[22].CLK
-HCLK => memory.data_a[21].CLK
-HCLK => memory.data_a[20].CLK
-HCLK => memory.data_a[19].CLK
-HCLK => memory.data_a[18].CLK
-HCLK => memory.data_a[17].CLK
-HCLK => memory.data_a[16].CLK
-HCLK => memory.data_a[15].CLK
-HCLK => memory.data_a[14].CLK
-HCLK => memory.data_a[13].CLK
-HCLK => memory.data_a[12].CLK
-HCLK => memory.data_a[11].CLK
-HCLK => memory.data_a[10].CLK
-HCLK => memory.data_a[9].CLK
-HCLK => memory.data_a[8].CLK
-HCLK => memory.data_a[7].CLK
-HCLK => memory.data_a[6].CLK
-HCLK => memory.data_a[5].CLK
-HCLK => memory.data_a[4].CLK
-HCLK => memory.data_a[3].CLK
-HCLK => memory.data_a[2].CLK
-HCLK => memory.data_a[1].CLK
-HCLK => memory.data_a[0].CLK
-HCLK => data_from_memory[0].CLK
-HCLK => data_from_memory[1].CLK
-HCLK => data_from_memory[2].CLK
-HCLK => data_from_memory[3].CLK
-HCLK => data_from_memory[4].CLK
-HCLK => data_from_memory[5].CLK
-HCLK => data_from_memory[6].CLK
-HCLK => data_from_memory[7].CLK
-HCLK => data_from_memory[8].CLK
-HCLK => data_from_memory[9].CLK
-HCLK => data_from_memory[10].CLK
-HCLK => data_from_memory[11].CLK
-HCLK => data_from_memory[12].CLK
-HCLK => data_from_memory[13].CLK
-HCLK => data_from_memory[14].CLK
-HCLK => data_from_memory[15].CLK
-HCLK => data_from_memory[16].CLK
-HCLK => data_from_memory[17].CLK
-HCLK => data_from_memory[18].CLK
-HCLK => data_from_memory[19].CLK
-HCLK => data_from_memory[20].CLK
-HCLK => data_from_memory[21].CLK
-HCLK => data_from_memory[22].CLK
-HCLK => data_from_memory[23].CLK
-HCLK => data_from_memory[24].CLK
-HCLK => data_from_memory[25].CLK
-HCLK => data_from_memory[26].CLK
-HCLK => data_from_memory[27].CLK
-HCLK => data_from_memory[28].CLK
-HCLK => data_from_memory[29].CLK
-HCLK => data_from_memory[30].CLK
-HCLK => data_from_memory[31].CLK
-HCLK => byte_select[0].CLK
-HCLK => byte_select[1].CLK
-HCLK => byte_select[2].CLK
-HCLK => byte_select[3].CLK
-HCLK => saved_word_address[0].CLK
-HCLK => saved_word_address[1].CLK
-HCLK => saved_word_address[2].CLK
-HCLK => saved_word_address[3].CLK
-HCLK => saved_word_address[4].CLK
-HCLK => saved_word_address[5].CLK
-HCLK => saved_word_address[6].CLK
-HCLK => saved_word_address[7].CLK
-HCLK => saved_word_address[8].CLK
-HCLK => saved_word_address[9].CLK
-HCLK => saved_word_address[10].CLK
-HCLK => saved_word_address[11].CLK
-HCLK => read_cycle.CLK
-HCLK => write_cycle.CLK
-HCLK => memory.CLK0
-HRESETn => byte_select[0].ACLR
-HRESETn => byte_select[1].ACLR
-HRESETn => byte_select[2].ACLR
-HRESETn => byte_select[3].ACLR
-HRESETn => saved_word_address[0].ACLR
-HRESETn => saved_word_address[1].ACLR
-HRESETn => saved_word_address[2].ACLR
-HRESETn => saved_word_address[3].ACLR
-HRESETn => saved_word_address[4].ACLR
-HRESETn => saved_word_address[5].ACLR
-HRESETn => saved_word_address[6].ACLR
-HRESETn => saved_word_address[7].ACLR
-HRESETn => saved_word_address[8].ACLR
-HRESETn => saved_word_address[9].ACLR
-HRESETn => saved_word_address[10].ACLR
-HRESETn => saved_word_address[11].ACLR
-HRESETn => read_cycle.ACLR
-HRESETn => write_cycle.ACLR
-HREADY => always1.IN1
-HADDR[0] => Equal0.IN31
-HADDR[0] => Equal1.IN0
-HADDR[0] => Equal2.IN31
-HADDR[0] => Equal3.IN1
-HADDR[1] => Equal0.IN30
-HADDR[1] => Equal1.IN31
-HADDR[1] => Equal2.IN0
-HADDR[1] => Equal3.IN0
-HADDR[2] => memory.raddr_a[0].DATAB
-HADDR[2] => saved_word_address[0].DATAIN
-HADDR[3] => memory.raddr_a[1].DATAB
-HADDR[3] => saved_word_address[1].DATAIN
-HADDR[4] => memory.raddr_a[2].DATAB
-HADDR[4] => saved_word_address[2].DATAIN
-HADDR[5] => memory.raddr_a[3].DATAB
-HADDR[5] => saved_word_address[3].DATAIN
-HADDR[6] => memory.raddr_a[4].DATAB
-HADDR[6] => saved_word_address[4].DATAIN
-HADDR[7] => memory.raddr_a[5].DATAB
-HADDR[7] => saved_word_address[5].DATAIN
-HADDR[8] => memory.raddr_a[6].DATAB
-HADDR[8] => saved_word_address[6].DATAIN
-HADDR[9] => memory.raddr_a[7].DATAB
-HADDR[9] => saved_word_address[7].DATAIN
-HADDR[10] => memory.raddr_a[8].DATAB
-HADDR[10] => saved_word_address[8].DATAIN
-HADDR[11] => memory.raddr_a[9].DATAB
-HADDR[11] => saved_word_address[9].DATAIN
-HADDR[12] => memory.raddr_a[10].DATAB
-HADDR[12] => saved_word_address[10].DATAIN
-HADDR[13] => memory.raddr_a[11].DATAB
-HADDR[13] => saved_word_address[11].DATAIN
-HADDR[14] => ~NO_FANOUT~
-HADDR[15] => ~NO_FANOUT~
-HADDR[16] => ~NO_FANOUT~
-HADDR[17] => ~NO_FANOUT~
-HADDR[18] => ~NO_FANOUT~
-HADDR[19] => ~NO_FANOUT~
-HADDR[20] => ~NO_FANOUT~
-HADDR[21] => ~NO_FANOUT~
-HADDR[22] => ~NO_FANOUT~
-HADDR[23] => ~NO_FANOUT~
-HADDR[24] => ~NO_FANOUT~
-HADDR[25] => ~NO_FANOUT~
-HADDR[26] => ~NO_FANOUT~
-HADDR[27] => ~NO_FANOUT~
-HADDR[28] => ~NO_FANOUT~
-HADDR[29] => ~NO_FANOUT~
-HADDR[30] => ~NO_FANOUT~
-HADDR[31] => ~NO_FANOUT~
-HTRANS[0] => Equal4.IN1
-HTRANS[1] => Equal4.IN0
-HWRITE => write_cycle.DATAB
-HWRITE => read_cycle.DATAB
-HSIZE[0] => byte1.IN1
-HSIZE[0] => byte3.IN1
-HSIZE[1] => byte0.IN1
-HSIZE[1] => byte1.IN1
-HSIZE[1] => byte2.IN1
-HSIZE[1] => byte3.IN1
-HSIZE[2] => ~NO_FANOUT~
-HWDATA[0] => data_to_memory.DATAB
-HWDATA[1] => data_to_memory.DATAB
-HWDATA[2] => data_to_memory.DATAB
-HWDATA[3] => data_to_memory.DATAB
-HWDATA[4] => data_to_memory.DATAB
-HWDATA[5] => data_to_memory.DATAB
-HWDATA[6] => data_to_memory.DATAB
-HWDATA[7] => data_to_memory.DATAB
-HWDATA[8] => data_to_memory.DATAB
-HWDATA[9] => data_to_memory.DATAB
-HWDATA[10] => data_to_memory.DATAB
-HWDATA[11] => data_to_memory.DATAB
-HWDATA[12] => data_to_memory.DATAB
-HWDATA[13] => data_to_memory.DATAB
-HWDATA[14] => data_to_memory.DATAB
-HWDATA[15] => data_to_memory.DATAB
-HWDATA[16] => data_to_memory.DATAB
-HWDATA[17] => data_to_memory.DATAB
-HWDATA[18] => data_to_memory.DATAB
-HWDATA[19] => data_to_memory.DATAB
-HWDATA[20] => data_to_memory.DATAB
-HWDATA[21] => data_to_memory.DATAB
-HWDATA[22] => data_to_memory.DATAB
-HWDATA[23] => data_to_memory.DATAB
-HWDATA[24] => data_to_memory.DATAB
-HWDATA[25] => data_to_memory.DATAB
-HWDATA[26] => data_to_memory.DATAB
-HWDATA[27] => data_to_memory.DATAB
-HWDATA[28] => data_to_memory.DATAB
-HWDATA[29] => data_to_memory.DATAB
-HWDATA[30] => data_to_memory.DATAB
-HWDATA[31] => data_to_memory.DATAB
-HREADYOUT <= write_cycle.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[0] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[1] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[2] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[3] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[4] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[5] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[6] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[7] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[8] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[9] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[10] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[11] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[12] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[13] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[14] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[15] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[16] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[17] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[18] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[19] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[20] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[21] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[22] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[23] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[24] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[25] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[26] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[27] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[28] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[29] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[30] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[31] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-
-
-|de1_soc_wrapper|arm_soc:soc_inst|ahb_switches:switches_1
-HCLK => half_word_address[0].CLK
-HCLK => half_word_address[1].CLK
-HCLK => read_enable.CLK
-HCLK => DataValid[0].CLK
-HCLK => DataValid[1].CLK
-HCLK => last_buttons[0].CLK
-HCLK => last_buttons[1].CLK
-HCLK => switch_store[1][0].CLK
-HCLK => switch_store[1][1].CLK
-HCLK => switch_store[1][2].CLK
-HCLK => switch_store[1][3].CLK
-HCLK => switch_store[1][4].CLK
-HCLK => switch_store[1][5].CLK
-HCLK => switch_store[1][6].CLK
-HCLK => switch_store[1][7].CLK
-HCLK => switch_store[1][8].CLK
-HCLK => switch_store[1][9].CLK
-HCLK => switch_store[1][10].CLK
-HCLK => switch_store[1][11].CLK
-HCLK => switch_store[1][12].CLK
-HCLK => switch_store[1][13].CLK
-HCLK => switch_store[1][14].CLK
-HCLK => switch_store[1][15].CLK
-HCLK => switch_store[0][0].CLK
-HCLK => switch_store[0][1].CLK
-HCLK => switch_store[0][2].CLK
-HCLK => switch_store[0][3].CLK
-HCLK => switch_store[0][4].CLK
-HCLK => switch_store[0][5].CLK
-HCLK => switch_store[0][6].CLK
-HCLK => switch_store[0][7].CLK
-HCLK => switch_store[0][8].CLK
-HCLK => switch_store[0][9].CLK
-HCLK => switch_store[0][10].CLK
-HCLK => switch_store[0][11].CLK
-HCLK => switch_store[0][12].CLK
-HCLK => switch_store[0][13].CLK
-HCLK => switch_store[0][14].CLK
-HCLK => switch_store[0][15].CLK
-HRESETn => DataValid[0].ACLR
-HRESETn => DataValid[1].ACLR
-HRESETn => last_buttons[0].ACLR
-HRESETn => last_buttons[1].ACLR
-HRESETn => switch_store[1][0].ACLR
-HRESETn => switch_store[1][1].ACLR
-HRESETn => switch_store[1][2].ACLR
-HRESETn => switch_store[1][3].ACLR
-HRESETn => switch_store[1][4].ACLR
-HRESETn => switch_store[1][5].ACLR
-HRESETn => switch_store[1][6].ACLR
-HRESETn => switch_store[1][7].ACLR
-HRESETn => switch_store[1][8].ACLR
-HRESETn => switch_store[1][9].ACLR
-HRESETn => switch_store[1][10].ACLR
-HRESETn => switch_store[1][11].ACLR
-HRESETn => switch_store[1][12].ACLR
-HRESETn => switch_store[1][13].ACLR
-HRESETn => switch_store[1][14].ACLR
-HRESETn => switch_store[1][15].ACLR
-HRESETn => switch_store[0][0].ACLR
-HRESETn => switch_store[0][1].ACLR
-HRESETn => switch_store[0][2].ACLR
-HRESETn => switch_store[0][3].ACLR
-HRESETn => switch_store[0][4].ACLR
-HRESETn => switch_store[0][5].ACLR
-HRESETn => switch_store[0][6].ACLR
-HRESETn => switch_store[0][7].ACLR
-HRESETn => switch_store[0][8].ACLR
-HRESETn => switch_store[0][9].ACLR
-HRESETn => switch_store[0][10].ACLR
-HRESETn => switch_store[0][11].ACLR
-HRESETn => switch_store[0][12].ACLR
-HRESETn => switch_store[0][13].ACLR
-HRESETn => switch_store[0][14].ACLR
-HRESETn => switch_store[0][15].ACLR
-HRESETn => half_word_address[0].ACLR
-HRESETn => half_word_address[1].ACLR
-HRESETn => read_enable.ACLR
-HADDR[0] => ~NO_FANOUT~
-HADDR[1] => half_word_address.DATAB
-HADDR[2] => half_word_address.DATAB
-HADDR[3] => ~NO_FANOUT~
-HADDR[4] => ~NO_FANOUT~
-HADDR[5] => ~NO_FANOUT~
-HADDR[6] => ~NO_FANOUT~
-HADDR[7] => ~NO_FANOUT~
-HADDR[8] => ~NO_FANOUT~
-HADDR[9] => ~NO_FANOUT~
-HADDR[10] => ~NO_FANOUT~
-HADDR[11] => ~NO_FANOUT~
-HADDR[12] => ~NO_FANOUT~
-HADDR[13] => ~NO_FANOUT~
-HADDR[14] => ~NO_FANOUT~
-HADDR[15] => ~NO_FANOUT~
-HADDR[16] => ~NO_FANOUT~
-HADDR[17] => ~NO_FANOUT~
-HADDR[18] => ~NO_FANOUT~
-HADDR[19] => ~NO_FANOUT~
-HADDR[20] => ~NO_FANOUT~
-HADDR[21] => ~NO_FANOUT~
-HADDR[22] => ~NO_FANOUT~
-HADDR[23] => ~NO_FANOUT~
-HADDR[24] => ~NO_FANOUT~
-HADDR[25] => ~NO_FANOUT~
-HADDR[26] => ~NO_FANOUT~
-HADDR[27] => ~NO_FANOUT~
-HADDR[28] => ~NO_FANOUT~
-HADDR[29] => ~NO_FANOUT~
-HADDR[30] => ~NO_FANOUT~
-HADDR[31] => ~NO_FANOUT~
-HWDATA[0] => ~NO_FANOUT~
-HWDATA[1] => ~NO_FANOUT~
-HWDATA[2] => ~NO_FANOUT~
-HWDATA[3] => ~NO_FANOUT~
-HWDATA[4] => ~NO_FANOUT~
-HWDATA[5] => ~NO_FANOUT~
-HWDATA[6] => ~NO_FANOUT~
-HWDATA[7] => ~NO_FANOUT~
-HWDATA[8] => ~NO_FANOUT~
-HWDATA[9] => ~NO_FANOUT~
-HWDATA[10] => ~NO_FANOUT~
-HWDATA[11] => ~NO_FANOUT~
-HWDATA[12] => ~NO_FANOUT~
-HWDATA[13] => ~NO_FANOUT~
-HWDATA[14] => ~NO_FANOUT~
-HWDATA[15] => ~NO_FANOUT~
-HWDATA[16] => ~NO_FANOUT~
-HWDATA[17] => ~NO_FANOUT~
-HWDATA[18] => ~NO_FANOUT~
-HWDATA[19] => ~NO_FANOUT~
-HWDATA[20] => ~NO_FANOUT~
-HWDATA[21] => ~NO_FANOUT~
-HWDATA[22] => ~NO_FANOUT~
-HWDATA[23] => ~NO_FANOUT~
-HWDATA[24] => ~NO_FANOUT~
-HWDATA[25] => ~NO_FANOUT~
-HWDATA[26] => ~NO_FANOUT~
-HWDATA[27] => ~NO_FANOUT~
-HWDATA[28] => ~NO_FANOUT~
-HWDATA[29] => ~NO_FANOUT~
-HWDATA[30] => ~NO_FANOUT~
-HWDATA[31] => ~NO_FANOUT~
-HSIZE[0] => ~NO_FANOUT~
-HSIZE[1] => ~NO_FANOUT~
-HSIZE[2] => ~NO_FANOUT~
-HTRANS[0] => Equal2.IN1
-HTRANS[1] => Equal2.IN0
-HWRITE => read_enable.DATAB
-HREADY => always1.IN0
-HSEL => always1.IN1
-HRDATA[0] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[1] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[2] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[3] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[4] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[5] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[6] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[7] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[8] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[9] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[10] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[11] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[12] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[13] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[14] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[15] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[16] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[17] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[18] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[19] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[20] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[21] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[22] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[23] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[24] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[25] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[26] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[27] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[28] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[29] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[30] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[31] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HREADYOUT <= <VCC>
-Switches[0] => switch_store[0][0].DATAIN
-Switches[0] => switch_store[1][0].DATAIN
-Switches[1] => switch_store[0][1].DATAIN
-Switches[1] => switch_store[1][1].DATAIN
-Switches[2] => switch_store[0][2].DATAIN
-Switches[2] => switch_store[1][2].DATAIN
-Switches[3] => switch_store[0][3].DATAIN
-Switches[3] => switch_store[1][3].DATAIN
-Switches[4] => switch_store[0][4].DATAIN
-Switches[4] => switch_store[1][4].DATAIN
-Switches[5] => switch_store[0][5].DATAIN
-Switches[5] => switch_store[1][5].DATAIN
-Switches[6] => switch_store[0][6].DATAIN
-Switches[6] => switch_store[1][6].DATAIN
-Switches[7] => switch_store[0][7].DATAIN
-Switches[7] => switch_store[1][7].DATAIN
-Switches[8] => switch_store[0][8].DATAIN
-Switches[8] => switch_store[1][8].DATAIN
-Switches[9] => switch_store[0][9].DATAIN
-Switches[9] => switch_store[1][9].DATAIN
-Switches[10] => switch_store[0][10].DATAIN
-Switches[10] => switch_store[1][10].DATAIN
-Switches[11] => switch_store[0][11].DATAIN
-Switches[11] => switch_store[1][11].DATAIN
-Switches[12] => switch_store[0][12].DATAIN
-Switches[12] => switch_store[1][12].DATAIN
-Switches[13] => switch_store[0][13].DATAIN
-Switches[13] => switch_store[1][13].DATAIN
-Switches[14] => switch_store[0][14].DATAIN
-Switches[14] => switch_store[1][14].DATAIN
-Switches[15] => switch_store[0][15].DATAIN
-Switches[15] => switch_store[1][15].DATAIN
-Buttons[0] => always0.IN1
-Buttons[0] => last_buttons[0].DATAIN
-Buttons[1] => always0.IN1
-Buttons[1] => last_buttons[1].DATAIN
-
-
-|de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1
-HSEL => always0.IN0
-HCLK => memory.we_a.CLK
-HCLK => memory.waddr_a[18].CLK
-HCLK => memory.waddr_a[17].CLK
-HCLK => memory.waddr_a[16].CLK
-HCLK => memory.waddr_a[15].CLK
-HCLK => memory.waddr_a[14].CLK
-HCLK => memory.waddr_a[13].CLK
-HCLK => memory.waddr_a[12].CLK
-HCLK => memory.waddr_a[11].CLK
-HCLK => memory.waddr_a[10].CLK
-HCLK => memory.waddr_a[9].CLK
-HCLK => memory.waddr_a[8].CLK
-HCLK => memory.waddr_a[7].CLK
-HCLK => memory.waddr_a[6].CLK
-HCLK => memory.waddr_a[5].CLK
-HCLK => memory.waddr_a[4].CLK
-HCLK => memory.waddr_a[3].CLK
-HCLK => memory.waddr_a[2].CLK
-HCLK => memory.waddr_a[1].CLK
-HCLK => memory.waddr_a[0].CLK
-HCLK => memory.data_a[7].CLK
-HCLK => memory.data_a[6].CLK
-HCLK => memory.data_a[5].CLK
-HCLK => memory.data_a[4].CLK
-HCLK => memory.data_a[3].CLK
-HCLK => memory.data_a[2].CLK
-HCLK => memory.data_a[1].CLK
-HCLK => memory.data_a[0].CLK
-HCLK => word_address[0].CLK
-HCLK => word_address[1].CLK
-HCLK => word_address[2].CLK
-HCLK => word_address[3].CLK
-HCLK => word_address[4].CLK
-HCLK => word_address[5].CLK
-HCLK => word_address[6].CLK
-HCLK => word_address[7].CLK
-HCLK => word_address[8].CLK
-HCLK => word_address[9].CLK
-HCLK => word_address[10].CLK
-HCLK => word_address[11].CLK
-HCLK => word_address[12].CLK
-HCLK => word_address[13].CLK
-HCLK => word_address[14].CLK
-HCLK => word_address[15].CLK
-HCLK => word_address[16].CLK
-HCLK => word_address[17].CLK
-HCLK => word_address[18].CLK
-HCLK => read_enable.CLK
-HCLK => write_enable.CLK
-HCLK => memory.CLK0
-HRESETn => word_address[0].ACLR
-HRESETn => word_address[1].ACLR
-HRESETn => word_address[2].ACLR
-HRESETn => word_address[3].ACLR
-HRESETn => word_address[4].ACLR
-HRESETn => word_address[5].ACLR
-HRESETn => word_address[6].ACLR
-HRESETn => word_address[7].ACLR
-HRESETn => word_address[8].ACLR
-HRESETn => word_address[9].ACLR
-HRESETn => word_address[10].ACLR
-HRESETn => word_address[11].ACLR
-HRESETn => word_address[12].ACLR
-HRESETn => word_address[13].ACLR
-HRESETn => word_address[14].ACLR
-HRESETn => word_address[15].ACLR
-HRESETn => word_address[16].ACLR
-HRESETn => word_address[17].ACLR
-HRESETn => word_address[18].ACLR
-HRESETn => read_enable.ACLR
-HRESETn => write_enable.ACLR
-HREADY => always0.IN1
-HADDR[0] => ~NO_FANOUT~
-HADDR[1] => ~NO_FANOUT~
-HADDR[2] => word_address.DATAB
-HADDR[3] => word_address.DATAB
-HADDR[4] => word_address.DATAB
-HADDR[5] => word_address.DATAB
-HADDR[6] => word_address.DATAB
-HADDR[7] => word_address.DATAB
-HADDR[8] => word_address.DATAB
-HADDR[9] => word_address.DATAB
-HADDR[10] => word_address.DATAB
-HADDR[11] => word_address.DATAB
-HADDR[12] => word_address.DATAB
-HADDR[13] => word_address.DATAB
-HADDR[14] => word_address.DATAB
-HADDR[15] => word_address.DATAB
-HADDR[16] => word_address.DATAB
-HADDR[17] => word_address.DATAB
-HADDR[18] => word_address.DATAB
-HADDR[19] => word_address.DATAB
-HADDR[20] => word_address.DATAB
-HADDR[21] => ~NO_FANOUT~
-HADDR[22] => ~NO_FANOUT~
-HADDR[23] => ~NO_FANOUT~
-HADDR[24] => ~NO_FANOUT~
-HADDR[25] => ~NO_FANOUT~
-HADDR[26] => ~NO_FANOUT~
-HADDR[27] => ~NO_FANOUT~
-HADDR[28] => ~NO_FANOUT~
-HADDR[29] => ~NO_FANOUT~
-HADDR[30] => ~NO_FANOUT~
-HADDR[31] => ~NO_FANOUT~
-HTRANS[0] => Equal0.IN1
-HTRANS[1] => Equal0.IN0
-HWRITE => write_enable.DATAB
-HWRITE => read_enable.DATAB
-HSIZE[0] => ~NO_FANOUT~
-HSIZE[1] => ~NO_FANOUT~
-HSIZE[2] => ~NO_FANOUT~
-HWDATA[0] => memory.data_a[0].DATAIN
-HWDATA[0] => memory.DATAIN
-HWDATA[1] => memory.data_a[1].DATAIN
-HWDATA[1] => memory.DATAIN1
-HWDATA[2] => memory.data_a[2].DATAIN
-HWDATA[2] => memory.DATAIN2
-HWDATA[3] => memory.data_a[3].DATAIN
-HWDATA[3] => memory.DATAIN3
-HWDATA[4] => memory.data_a[4].DATAIN
-HWDATA[4] => memory.DATAIN4
-HWDATA[5] => memory.data_a[5].DATAIN
-HWDATA[5] => memory.DATAIN5
-HWDATA[6] => memory.data_a[6].DATAIN
-HWDATA[6] => memory.DATAIN6
-HWDATA[7] => memory.data_a[7].DATAIN
-HWDATA[7] => memory.DATAIN7
-HWDATA[8] => ~NO_FANOUT~
-HWDATA[9] => ~NO_FANOUT~
-HWDATA[10] => ~NO_FANOUT~
-HWDATA[11] => ~NO_FANOUT~
-HWDATA[12] => ~NO_FANOUT~
-HWDATA[13] => ~NO_FANOUT~
-HWDATA[14] => ~NO_FANOUT~
-HWDATA[15] => ~NO_FANOUT~
-HWDATA[16] => ~NO_FANOUT~
-HWDATA[17] => ~NO_FANOUT~
-HWDATA[18] => ~NO_FANOUT~
-HWDATA[19] => ~NO_FANOUT~
-HWDATA[20] => ~NO_FANOUT~
-HWDATA[21] => ~NO_FANOUT~
-HWDATA[22] => ~NO_FANOUT~
-HWDATA[23] => ~NO_FANOUT~
-HWDATA[24] => ~NO_FANOUT~
-HWDATA[25] => ~NO_FANOUT~
-HWDATA[26] => ~NO_FANOUT~
-HWDATA[27] => ~NO_FANOUT~
-HWDATA[28] => ~NO_FANOUT~
-HWDATA[29] => ~NO_FANOUT~
-HWDATA[30] => ~NO_FANOUT~
-HWDATA[31] => ~NO_FANOUT~
-pixel_x[0] => memory.RADDR
-pixel_x[1] => memory.RADDR1
-pixel_x[2] => memory.RADDR2
-pixel_x[3] => memory.RADDR3
-pixel_x[4] => memory.RADDR4
-pixel_x[5] => memory.RADDR5
-pixel_x[6] => memory.RADDR6
-pixel_x[7] => Add1.IN22
-pixel_x[8] => Add1.IN21
-pixel_x[9] => Add1.IN20
-pixel_y[0] => Add0.IN18
-pixel_y[0] => Add1.IN24
-pixel_y[1] => Add0.IN17
-pixel_y[1] => Add1.IN23
-pixel_y[2] => Add0.IN15
-pixel_y[2] => Add0.IN16
-pixel_y[3] => Add0.IN13
-pixel_y[3] => Add0.IN14
-pixel_y[4] => Add0.IN11
-pixel_y[4] => Add0.IN12
-pixel_y[5] => Add0.IN9
-pixel_y[5] => Add0.IN10
-pixel_y[6] => Add0.IN7
-pixel_y[6] => Add0.IN8
-pixel_y[7] => Add0.IN5
-pixel_y[7] => Add0.IN6
-pixel_y[8] => Add0.IN3
-pixel_y[8] => Add0.IN4
-HREADYOUT <= <VCC>
-HRDATA[0] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[1] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[2] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[3] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[4] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[5] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[6] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[7] <= HRDATA.DB_MAX_OUTPUT_PORT_TYPE
-HRDATA[8] <= <GND>
-HRDATA[9] <= <GND>
-HRDATA[10] <= <GND>
-HRDATA[11] <= <GND>
-HRDATA[12] <= <GND>
-HRDATA[13] <= <GND>
-HRDATA[14] <= <GND>
-HRDATA[15] <= <GND>
-HRDATA[16] <= <GND>
-HRDATA[17] <= <GND>
-HRDATA[18] <= <GND>
-HRDATA[19] <= <GND>
-HRDATA[20] <= <GND>
-HRDATA[21] <= <GND>
-HRDATA[22] <= <GND>
-HRDATA[23] <= <GND>
-HRDATA[24] <= <GND>
-HRDATA[25] <= <GND>
-HRDATA[26] <= <GND>
-HRDATA[27] <= <GND>
-HRDATA[28] <= <GND>
-HRDATA[29] <= <GND>
-HRDATA[30] <= <GND>
-HRDATA[31] <= <GND>
-pixel <= memory.DATAOUT
-
-
-|de1_soc_wrapper|razzle:raz_inst
-CLOCK_50 => VGA_VS~reg0.CLK
-CLOCK_50 => VGA_HS~reg0.CLK
-CLOCK_50 => pixel_y[0]~reg0.CLK
-CLOCK_50 => pixel_y[1]~reg0.CLK
-CLOCK_50 => pixel_y[2]~reg0.CLK
-CLOCK_50 => pixel_y[3]~reg0.CLK
-CLOCK_50 => pixel_y[4]~reg0.CLK
-CLOCK_50 => pixel_y[5]~reg0.CLK
-CLOCK_50 => pixel_y[6]~reg0.CLK
-CLOCK_50 => pixel_y[7]~reg0.CLK
-CLOCK_50 => pixel_y[8]~reg0.CLK
-CLOCK_50 => pixel_x[0]~reg0.CLK
-CLOCK_50 => pixel_x[1]~reg0.CLK
-CLOCK_50 => pixel_x[2]~reg0.CLK
-CLOCK_50 => pixel_x[3]~reg0.CLK
-CLOCK_50 => pixel_x[4]~reg0.CLK
-CLOCK_50 => pixel_x[5]~reg0.CLK
-CLOCK_50 => pixel_x[6]~reg0.CLK
-CLOCK_50 => pixel_x[7]~reg0.CLK
-CLOCK_50 => pixel_x[8]~reg0.CLK
-CLOCK_50 => pixel_x[9]~reg0.CLK
-CLOCK_50 => video_on_V.CLK
-CLOCK_50 => video_on_H.CLK
-CLOCK_50 => V_count[0].CLK
-CLOCK_50 => V_count[1].CLK
-CLOCK_50 => V_count[2].CLK
-CLOCK_50 => V_count[3].CLK
-CLOCK_50 => V_count[4].CLK
-CLOCK_50 => V_count[5].CLK
-CLOCK_50 => V_count[6].CLK
-CLOCK_50 => V_count[7].CLK
-CLOCK_50 => V_count[8].CLK
-CLOCK_50 => V_count[9].CLK
-CLOCK_50 => V_count[10].CLK
-CLOCK_50 => H_count[0].CLK
-CLOCK_50 => H_count[1].CLK
-CLOCK_50 => H_count[2].CLK
-CLOCK_50 => H_count[3].CLK
-CLOCK_50 => H_count[4].CLK
-CLOCK_50 => H_count[5].CLK
-CLOCK_50 => H_count[6].CLK
-CLOCK_50 => H_count[7].CLK
-CLOCK_50 => H_count[8].CLK
-CLOCK_50 => H_count[9].CLK
-CLOCK_50 => H_count[10].CLK
-CLOCK_50 => clock_enable.CLK
-CLOCK_50 => red_square.CLK
-KEY[0] => ~NO_FANOUT~
-KEY[1] => ~NO_FANOUT~
-KEY[2] => pixel_y[0]~reg0.ACLR
-KEY[2] => pixel_y[1]~reg0.ACLR
-KEY[2] => pixel_y[2]~reg0.ACLR
-KEY[2] => pixel_y[3]~reg0.ACLR
-KEY[2] => pixel_y[4]~reg0.ACLR
-KEY[2] => pixel_y[5]~reg0.ACLR
-KEY[2] => pixel_y[6]~reg0.ACLR
-KEY[2] => pixel_y[7]~reg0.ACLR
-KEY[2] => pixel_y[8]~reg0.ACLR
-KEY[2] => pixel_x[0]~reg0.ACLR
-KEY[2] => pixel_x[1]~reg0.ACLR
-KEY[2] => pixel_x[2]~reg0.ACLR
-KEY[2] => pixel_x[3]~reg0.ACLR
-KEY[2] => pixel_x[4]~reg0.ACLR
-KEY[2] => pixel_x[5]~reg0.ACLR
-KEY[2] => pixel_x[6]~reg0.ACLR
-KEY[2] => pixel_x[7]~reg0.ACLR
-KEY[2] => pixel_x[8]~reg0.ACLR
-KEY[2] => pixel_x[9]~reg0.ACLR
-KEY[2] => video_on_V.ACLR
-KEY[2] => video_on_H.ACLR
-KEY[2] => V_count[0].ACLR
-KEY[2] => V_count[1].ACLR
-KEY[2] => V_count[2].ACLR
-KEY[2] => V_count[3].ACLR
-KEY[2] => V_count[4].ACLR
-KEY[2] => V_count[5].ACLR
-KEY[2] => V_count[6].ACLR
-KEY[2] => V_count[7].ACLR
-KEY[2] => V_count[8].ACLR
-KEY[2] => V_count[9].ACLR
-KEY[2] => V_count[10].ACLR
-KEY[2] => H_count[0].ACLR
-KEY[2] => H_count[1].ACLR
-KEY[2] => H_count[2].ACLR
-KEY[2] => H_count[3].ACLR
-KEY[2] => H_count[4].ACLR
-KEY[2] => H_count[5].ACLR
-KEY[2] => H_count[6].ACLR
-KEY[2] => H_count[7].ACLR
-KEY[2] => H_count[8].ACLR
-KEY[2] => H_count[9].ACLR
-KEY[2] => H_count[10].ACLR
-KEY[2] => clock_enable.ACLR
-KEY[2] => red_square.ACLR
-KEY[2] => VGA_VS~reg0.ENA
-KEY[2] => VGA_HS~reg0.ENA
-KEY[3] => ~NO_FANOUT~
-pixel[0] => ~NO_FANOUT~
-pixel[1] => ~NO_FANOUT~
-pixel[2] => ~NO_FANOUT~
-pixel[3] => ~NO_FANOUT~
-pixel[4] => ~NO_FANOUT~
-pixel[5] => ~NO_FANOUT~
-pixel[6] => ~NO_FANOUT~
-pixel[7] => ~NO_FANOUT~
-pixel[8] => ~NO_FANOUT~
-pixel[9] => ~NO_FANOUT~
-VGA_R[0] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_R[1] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_R[2] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_R[3] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_R[4] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_R[5] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_R[6] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_R[7] <= Red.DB_MAX_OUTPUT_PORT_TYPE
-VGA_G[0] <= <GND>
-VGA_G[1] <= <GND>
-VGA_G[2] <= <GND>
-VGA_G[3] <= <GND>
-VGA_G[4] <= <GND>
-VGA_G[5] <= <GND>
-VGA_G[6] <= <GND>
-VGA_G[7] <= <GND>
-VGA_B[0] <= <GND>
-VGA_B[1] <= <GND>
-VGA_B[2] <= <GND>
-VGA_B[3] <= <GND>
-VGA_B[4] <= <GND>
-VGA_B[5] <= <GND>
-VGA_B[6] <= <GND>
-VGA_B[7] <= <GND>
-pixel_x[0] <= pixel_x[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[1] <= pixel_x[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[2] <= pixel_x[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[3] <= pixel_x[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[4] <= pixel_x[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[5] <= pixel_x[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[6] <= pixel_x[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[7] <= pixel_x[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[8] <= pixel_x[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_x[9] <= pixel_x[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[0] <= pixel_y[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[1] <= pixel_y[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[2] <= pixel_y[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[3] <= pixel_y[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[4] <= pixel_y[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[5] <= pixel_y[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[6] <= pixel_y[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[7] <= pixel_y[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-pixel_y[8] <= pixel_y[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
-VGA_HS <= VGA_HS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-VGA_VS <= VGA_VS~reg0.DB_MAX_OUTPUT_PORT_TYPE
-VGA_CLK <= clock_enable.DB_MAX_OUTPUT_PORT_TYPE
-VGA_BLANK_N <= video_on.DB_MAX_OUTPUT_PORT_TYPE
-
-
diff --git a/db/de1_soc_wrapper.hif b/db/de1_soc_wrapper.hif
deleted file mode 100644
index 18f7ce782fd015ed7aead7eddc11fab9ca6fdb81..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.hif and /dev/null differ
diff --git a/db/de1_soc_wrapper.lpc.html b/db/de1_soc_wrapper.lpc.html
deleted file mode 100644
index c85962ad77a46ef26973392c56923661e51abe85..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.lpc.html
+++ /dev/null
@@ -1,146 +0,0 @@
-<TABLE>
-<TR bgcolor="#C0C0C0">
-<TH>Hierarchy</TH>
-<TH>Input</TH>
-<TH>Constant Input</TH>
-<TH>Unused Input</TH>
-<TH>Floating Input</TH>
-<TH>Output</TH>
-<TH>Constant Output</TH>
-<TH>Unused Output</TH>
-<TH>Floating Output</TH>
-<TH>Bidir</TH>
-<TH>Constant Bidir</TH>
-<TH>Unused Bidir</TH>
-<TH>Input only Bidir</TH>
-<TH>Output only Bidir</TH>
-</TR>
-<TR >
-<TD >raz_inst</TD>
-<TD >15</TD>
-<TD >25</TD>
-<TD >4</TD>
-<TD >25</TD>
-<TD >47</TD>
-<TD >25</TD>
-<TD >25</TD>
-<TD >25</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >soc_inst|pix1</TD>
-<TD >93</TD>
-<TD >25</TD>
-<TD >40</TD>
-<TD >25</TD>
-<TD >34</TD>
-<TD >25</TD>
-<TD >25</TD>
-<TD >25</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >soc_inst|switches_1</TD>
-<TD >92</TD>
-<TD >1</TD>
-<TD >65</TD>
-<TD >1</TD>
-<TD >33</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >1</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >soc_inst|ram_1</TD>
-<TD >74</TD>
-<TD >0</TD>
-<TD >19</TD>
-<TD >0</TD>
-<TD >33</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >soc_inst|interconnect_1</TD>
-<TD >133</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >36</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >soc_inst|m0_1|u_logic</TD>
-<TD >54</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >7</TD>
-<TD >634</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >7</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >soc_inst|m0_1</TD>
-<TD >54</TD>
-<TD >30</TD>
-<TD >0</TD>
-<TD >30</TD>
-<TD >82</TD>
-<TD >30</TD>
-<TD >30</TD>
-<TD >30</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-<TR >
-<TD >soc_inst</TD>
-<TD >39</TD>
-<TD >6</TD>
-<TD >0</TD>
-<TD >6</TD>
-<TD >2</TD>
-<TD >6</TD>
-<TD >6</TD>
-<TD >6</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-<TD >0</TD>
-</TR>
-</TABLE>
diff --git a/db/de1_soc_wrapper.lpc.rdb b/db/de1_soc_wrapper.lpc.rdb
deleted file mode 100644
index d5e96ce75c7d54e6bf5bade568edc8094751e909..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.lpc.rdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.lpc.txt b/db/de1_soc_wrapper.lpc.txt
deleted file mode 100644
index 051ab7d8194eea41d9e11ea8cf18c552d6db0561..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.lpc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Legal Partition Candidates ;
-+-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
-+-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
-; raz_inst ; 15 ; 25 ; 4 ; 25 ; 47 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; soc_inst|pix1 ; 93 ; 25 ; 40 ; 25 ; 34 ; 25 ; 25 ; 25 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; soc_inst|switches_1 ; 92 ; 1 ; 65 ; 1 ; 33 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; soc_inst|ram_1 ; 74 ; 0 ; 19 ; 0 ; 33 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; soc_inst|interconnect_1 ; 133 ; 0 ; 0 ; 0 ; 36 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; soc_inst|m0_1|u_logic ; 54 ; 7 ; 0 ; 7 ; 634 ; 7 ; 7 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; soc_inst|m0_1 ; 54 ; 30 ; 0 ; 30 ; 82 ; 30 ; 30 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; soc_inst ; 39 ; 6 ; 0 ; 6 ; 2 ; 6 ; 6 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-+-------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
diff --git a/db/de1_soc_wrapper.map.ammdb b/db/de1_soc_wrapper.map.ammdb
deleted file mode 100644
index b60b62e8666708fc3428d703732d8c70421a348a..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.map.ammdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.map.bpm b/db/de1_soc_wrapper.map.bpm
deleted file mode 100644
index 0f348abbbd80dca4e9ba695cb86e3f72f32e366d..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.map.cdb b/db/de1_soc_wrapper.map.cdb
deleted file mode 100644
index de3fcd13a5bc7af612d3d9067a0c229605e7075d..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.map.hdb b/db/de1_soc_wrapper.map.hdb
deleted file mode 100644
index 531ea6130e226df051c2d68a2188db14341213d3..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.map.hdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.map.kpt b/db/de1_soc_wrapper.map.kpt
deleted file mode 100644
index 9baed469bad9f72b96c15c4a7c8e342c28738303..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.map.kpt and /dev/null differ
diff --git a/db/de1_soc_wrapper.map.qmsg b/db/de1_soc_wrapper.map.qmsg
deleted file mode 100644
index e5028fb94b184362a76b433c20dc67392058f37d..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.map.qmsg
+++ /dev/null
@@ -1,74 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1600361694624 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition " "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600361694626 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 17 17:54:54 2020 " "Processing started: Thu Sep 17 17:54:54 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600361694626 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361694626 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Msc_proj -c de1_soc_wrapper " "Command: quartus_map --read_settings_files=on --write_settings_files=off Msc_proj -c de1_soc_wrapper" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361694626 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1600361695071 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 24 " "Parallel compilation is enabled and will use 16 of the 24 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1600361695071 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/razzle.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/razzle.sv" { { "Info" "ISGN_ENTITY_NAME" "1 razzle " "Found entity 1: razzle" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 8 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704229 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704229 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/ahb_interconnect.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/ahb_interconnect.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ahb_interconnect " "Found entity 1: ahb_interconnect" { } { { "behavioural/ahb_interconnect.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704232 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704232 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/ahb_pixel_memory.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/ahb_pixel_memory.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ahb_pixel_memory " "Found entity 1: ahb_pixel_memory" { } { { "behavioural/ahb_pixel_memory.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv" 23 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704235 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704235 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/ahb_ram.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/ahb_ram.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ahb_ram " "Found entity 1: ahb_ram" { } { { "behavioural/ahb_ram.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_ram.sv" 24 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704238 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704238 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/ahb_switches.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/ahb_switches.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ahb_switches " "Found entity 1: ahb_switches" { } { { "behavioural/ahb_switches.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_switches.sv" 32 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704241 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704241 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/arm_soc.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/arm_soc.sv" { { "Info" "ISGN_ENTITY_NAME" "1 arm_soc " "Found entity 1: arm_soc" { } { { "behavioural/arm_soc.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/arm_soc.sv" 4 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704244 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704244 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/CORTEXM0DS.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/CORTEXM0DS.sv" { { "Info" "ISGN_ENTITY_NAME" "1 CORTEXM0DS " "Found entity 1: CORTEXM0DS" { } { { "behavioural/CORTEXM0DS.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704247 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704247 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/cortexm0ds_logic.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/cortexm0ds_logic.sv" { { "Info" "ISGN_ENTITY_NAME" "1 cortexm0ds_logic " "Found entity 1: cortexm0ds_logic" { } { { "behavioural/cortexm0ds_logic.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv" 27 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704290 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704290 ""}
-{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "de1_soc_wrapper.sv(64) " "Verilog HDL information at de1_soc_wrapper.sv(64): always construct contains both blocking and non-blocking assignments" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 64 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1600361704293 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "behavioural/de1_soc_wrapper.sv 1 1 " "Found 1 design units, including 1 entities, in source file behavioural/de1_soc_wrapper.sv" { { "Info" "ISGN_ENTITY_NAME" "1 de1_soc_wrapper " "Found entity 1: de1_soc_wrapper" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 8 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361704294 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361704294 ""}
-{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "Green_Data razzle.sv(45) " "Verilog HDL Implicit Net warning at razzle.sv(45): created implicit net for \"Green_Data\"" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 45 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704294 ""}
-{ "Warning" "WVRFX_L2_VERI_CREATED_IMPLICIT_NET" "Blue_Data razzle.sv(46) " "Verilog HDL Implicit Net warning at razzle.sv(46): created implicit net for \"Blue_Data\"" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 46 0 0 } } } 0 10236 "Verilog HDL Implicit Net warning at %2!s!: created implicit net for \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704294 ""}
-{ "Info" "ISGN_START_ELABORATION_TOP" "de1_soc_wrapper " "Elaborating entity \"de1_soc_wrapper\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1600361704490 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 de1_soc_wrapper.sv(75) " "Verilog HDL assignment warning at de1_soc_wrapper.sv(75): truncated value with size 32 to match size of target (26)" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 75 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361704493 "|de1_soc_wrapper"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 7 de1_soc_wrapper.sv(87) " "Verilog HDL assignment warning at de1_soc_wrapper.sv(87): truncated value with size 8 to match size of target (7)" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 87 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361704493 "|de1_soc_wrapper"}
-{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "LEDR de1_soc_wrapper.sv(15) " "Output port \"LEDR\" at de1_soc_wrapper.sv(15) has no driver" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 0 0 } } } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1600361704494 "|de1_soc_wrapper"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "arm_soc arm_soc:soc_inst " "Elaborating entity \"arm_soc\" for hierarchy \"arm_soc:soc_inst\"" { } { { "behavioural/de1_soc_wrapper.sv" "soc_inst" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 42 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704530 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CORTEXM0DS arm_soc:soc_inst\|CORTEXM0DS:m0_1 " "Elaborating entity \"CORTEXM0DS\" for hierarchy \"arm_soc:soc_inst\|CORTEXM0DS:m0_1\"" { } { { "behavioural/arm_soc.sv" "m0_1" { Text "/home/ks6n19/Documents/project/behavioural/arm_soc.sv" 56 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704549 ""}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cm0_msp CORTEXM0DS.sv(76) " "Verilog HDL or VHDL warning at CORTEXM0DS.sv(76): object \"cm0_msp\" assigned a value but never read" { } { { "behavioural/CORTEXM0DS.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 76 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704552 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cm0_psp CORTEXM0DS.sv(77) " "Verilog HDL or VHDL warning at CORTEXM0DS.sv(77): object \"cm0_psp\" assigned a value but never read" { } { { "behavioural/CORTEXM0DS.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 77 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704552 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cm0_pc CORTEXM0DS.sv(79) " "Verilog HDL or VHDL warning at CORTEXM0DS.sv(79): object \"cm0_pc\" assigned a value but never read" { } { { "behavioural/CORTEXM0DS.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 79 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704553 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cm0_xpsr CORTEXM0DS.sv(80) " "Verilog HDL or VHDL warning at CORTEXM0DS.sv(80): object \"cm0_xpsr\" assigned a value but never read" { } { { "behavioural/CORTEXM0DS.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 80 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704553 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cm0_control CORTEXM0DS.sv(81) " "Verilog HDL or VHDL warning at CORTEXM0DS.sv(81): object \"cm0_control\" assigned a value but never read" { } { { "behavioural/CORTEXM0DS.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 81 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704553 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cm0_primask CORTEXM0DS.sv(82) " "Verilog HDL or VHDL warning at CORTEXM0DS.sv(82): object \"cm0_primask\" assigned a value but never read" { } { { "behavioural/CORTEXM0DS.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 82 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704553 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cortexm0ds_logic arm_soc:soc_inst\|CORTEXM0DS:m0_1\|cortexm0ds_logic:u_logic " "Elaborating entity \"cortexm0ds_logic\" for hierarchy \"arm_soc:soc_inst\|CORTEXM0DS:m0_1\|cortexm0ds_logic:u_logic\"" { } { { "behavioural/CORTEXM0DS.sv" "u_logic" { Text "/home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv" 144 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704554 ""}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "N4i2z4 cortexm0ds_logic.sv(1133) " "Verilog HDL or VHDL warning at cortexm0ds_logic.sv(1133): object \"N4i2z4\" assigned a value but never read" { } { { "behavioural/cortexm0ds_logic.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv" 1133 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704586 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic"}
-{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "L5i2z4 cortexm0ds_logic.sv(1133) " "Verilog HDL or VHDL warning at cortexm0ds_logic.sv(1133): object \"L5i2z4\" assigned a value but never read" { } { { "behavioural/cortexm0ds_logic.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv" 1133 0 0 } } } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1600361704586 "|de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ahb_interconnect arm_soc:soc_inst\|ahb_interconnect:interconnect_1 " "Elaborating entity \"ahb_interconnect\" for hierarchy \"arm_soc:soc_inst\|ahb_interconnect:interconnect_1\"" { } { { "behavioural/arm_soc.sv" "interconnect_1" { Text "/home/ks6n19/Documents/project/behavioural/arm_soc.sv" 68 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704588 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 ahb_interconnect.sv(39) " "Verilog HDL assignment warning at ahb_interconnect.sv(39): truncated value with size 32 to match size of target (3)" { } { { "behavioural/ahb_interconnect.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361704591 "|de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 ahb_interconnect.sv(41) " "Verilog HDL assignment warning at ahb_interconnect.sv(41): truncated value with size 32 to match size of target (3)" { } { { "behavioural/ahb_interconnect.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv" 41 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361704591 "|de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 ahb_interconnect.sv(43) " "Verilog HDL assignment warning at ahb_interconnect.sv(43): truncated value with size 32 to match size of target (3)" { } { { "behavioural/ahb_interconnect.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv" 43 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361704591 "|de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ahb_ram arm_soc:soc_inst\|ahb_ram:ram_1 " "Elaborating entity \"ahb_ram\" for hierarchy \"arm_soc:soc_inst\|ahb_ram:ram_1\"" { } { { "behavioural/arm_soc.sv" "ram_1" { Text "/home/ks6n19/Documents/project/behavioural/arm_soc.sv" 79 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704592 ""}
-{ "Warning" "WVRFX_VERI_2111_UNCONVERTED" "199 0 4095 ahb_ram.sv(69) " "Verilog HDL warning at ahb_ram.sv(69): number of words (199) in memory file does not match the number of elements in the address range \[0:4095\]" { } { { "behavioural/ahb_ram.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_ram.sv" 69 0 0 } } } 0 10850 "Verilog HDL warning at %4!s!: number of words (%1!d!) in memory file does not match the number of elements in the address range \[%2!d!:%3!d!\]" 0 0 "Analysis & Synthesis" 0 -1 1600361704629 "|de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ahb_switches arm_soc:soc_inst\|ahb_switches:switches_1 " "Elaborating entity \"ahb_switches\" for hierarchy \"arm_soc:soc_inst\|ahb_switches:switches_1\"" { } { { "behavioural/arm_soc.sv" "switches_1" { Text "/home/ks6n19/Documents/project/behavioural/arm_soc.sv" 89 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361704992 ""}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ahb_pixel_memory arm_soc:soc_inst\|ahb_pixel_memory:pix1 " "Elaborating entity \"ahb_pixel_memory\" for hierarchy \"arm_soc:soc_inst\|ahb_pixel_memory:pix1\"" { } { { "behavioural/arm_soc.sv" "pix1" { Text "/home/ks6n19/Documents/project/behavioural/arm_soc.sv" 95 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361705011 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 ahb_pixel_memory.sv(94) " "Verilog HDL assignment warning at ahb_pixel_memory.sv(94): truncated value with size 32 to match size of target (8)" { } { { "behavioural/ahb_pixel_memory.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv" 94 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361706489 "|de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 19 ahb_pixel_memory.sv(98) " "Verilog HDL assignment warning at ahb_pixel_memory.sv(98): truncated value with size 32 to match size of target (19)" { } { { "behavioural/ahb_pixel_memory.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv" 98 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361706489 "|de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "8 1 ahb_pixel_memory.sv(102) " "Verilog HDL assignment warning at ahb_pixel_memory.sv(102): truncated value with size 8 to match size of target (1)" { } { { "behavioural/ahb_pixel_memory.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv" 102 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361706489 "|de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1"}
-{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "razzle razzle:raz_inst " "Elaborating entity \"razzle\" for hierarchy \"razzle:raz_inst\"" { } { { "behavioural/de1_soc_wrapper.sv" "raz_inst" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 49 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361707770 ""}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 razzle.sv(35) " "Verilog HDL assignment warning at razzle.sv(35): truncated value with size 32 to match size of target (8)" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 35 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361707770 "|de1_soc_wrapper|razzle:raz_inst"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 razzle.sv(36) " "Verilog HDL assignment warning at razzle.sv(36): truncated value with size 32 to match size of target (8)" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 36 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361707771 "|de1_soc_wrapper|razzle:raz_inst"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 razzle.sv(37) " "Verilog HDL assignment warning at razzle.sv(37): truncated value with size 32 to match size of target (8)" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 37 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361707771 "|de1_soc_wrapper|razzle:raz_inst"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 10 razzle.sv(112) " "Verilog HDL assignment warning at razzle.sv(112): truncated value with size 32 to match size of target (10)" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 112 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361707771 "|de1_soc_wrapper|razzle:raz_inst"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 razzle.sv(117) " "Verilog HDL assignment warning at razzle.sv(117): truncated value with size 32 to match size of target (11)" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 117 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361707771 "|de1_soc_wrapper|razzle:raz_inst"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 11 razzle.sv(134) " "Verilog HDL assignment warning at razzle.sv(134): truncated value with size 32 to match size of target (11)" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 134 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361707772 "|de1_soc_wrapper|razzle:raz_inst"}
-{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 razzle.sv(139) " "Verilog HDL assignment warning at razzle.sv(139): truncated value with size 32 to match size of target (9)" { } { { "behavioural/razzle.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/razzle.sv" 139 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1600361707772 "|de1_soc_wrapper|razzle:raz_inst"}
-{ "Warning" "WINFER_RAM_PASS_THROUGH_LOGIC_INSERTED_ALTSYNCRAM" "arm_soc:soc_inst\|ahb_pixel_memory:pix1\|memory_rtl_0 " "Inferred RAM node \"arm_soc:soc_inst\|ahb_pixel_memory:pix1\|memory_rtl_0\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." { } { } 0 276020 "Inferred RAM node \"%1!s!\" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design." 0 0 "Analysis & Synthesis" 0 -1 1600361708807 ""}
-{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "1 " "Found 1 instances of uninferred RAM logic" { { "Info" "IINFER_READ_LOGIC_IS_ASYNCHRONOUS" "arm_soc:soc_inst\|ahb_pixel_memory:pix1\|memory " "RAM logic \"arm_soc:soc_inst\|ahb_pixel_memory:pix1\|memory\" is uninferred due to asynchronous read logic" { } { { "behavioural/ahb_pixel_memory.sv" "memory" { Text "/home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv" 59 -1 0 } } } 0 276007 "RAM logic \"%1!s!\" is uninferred due to asynchronous read logic" 0 0 "Design Software" 0 -1 1600361708808 ""} } { } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1600361708808 ""}
-{ "Info" "IOPT_INFERENCING_SUMMARY" "2 " "Inferred 2 megafunctions from design logic" { { "Info" "IINFER_ALTSYNCRAM_INFERRED" "arm_soc:soc_inst\|ahb_pixel_memory:pix1\|memory_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"arm_soc:soc_inst\|ahb_pixel_memory:pix1\|memory_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 8 " "Parameter WIDTH_A set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 19 " "Parameter WIDTHAD_A set to 19" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 307200 " "Parameter NUMWORDS_A set to 307200" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 8 " "Parameter WIDTH_B set to 8" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 19 " "Parameter WIDTHAD_B set to 19" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 307200 " "Parameter NUMWORDS_B set to 307200" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "IINFER_ALTSYNCRAM_INFERRED" "arm_soc:soc_inst\|ahb_ram:ram_1\|memory_rtl_0 " "Inferred altsyncram megafunction from the following design logic: \"arm_soc:soc_inst\|ahb_ram:ram_1\|memory_rtl_0\" " { { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OPERATION_MODE DUAL_PORT " "Parameter OPERATION_MODE set to DUAL_PORT" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_A 32 " "Parameter WIDTH_A set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_A 12 " "Parameter WIDTHAD_A set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_A 4096 " "Parameter NUMWORDS_A set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTH_B 32 " "Parameter WIDTH_B set to 32" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WIDTHAD_B 12 " "Parameter WIDTHAD_B set to 12" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "NUMWORDS_B 4096 " "Parameter NUMWORDS_B set to 4096" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_A NONE " "Parameter ADDRESS_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_REG_B UNREGISTERED " "Parameter OUTDATA_REG_B set to UNREGISTERED" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_ACLR_B NONE " "Parameter ADDRESS_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "OUTDATA_ACLR_B NONE " "Parameter OUTDATA_ACLR_B set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "ADDRESS_REG_B CLOCK0 " "Parameter ADDRESS_REG_B set to CLOCK0" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INDATA_ACLR_A NONE " "Parameter INDATA_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "WRCONTROL_ACLR_A NONE " "Parameter WRCONTROL_ACLR_A set to NONE" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "INIT_FILE db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif " "Parameter INIT_FILE set to db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} { "Info" "ISUTIL_INFERRED_MEGAFUNCTION_PARAMETER" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA" { } { } 0 286033 "Parameter %1!s! set to %2!s!" 0 0 "Design Software" 0 -1 1600361711946 ""} } { } 0 276029 "Inferred altsyncram megafunction from the following design logic: \"%1!s!\" " 0 0 "Design Software" 0 -1 1600361711946 ""} } { } 0 19000 "Inferred %1!d! megafunctions from design logic" 0 0 "Analysis & Synthesis" 0 -1 1600361711946 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "arm_soc:soc_inst\|ahb_pixel_memory:pix1\|altsyncram:memory_rtl_0 " "Elaborated megafunction instantiation \"arm_soc:soc_inst\|ahb_pixel_memory:pix1\|altsyncram:memory_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361712445 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "arm_soc:soc_inst\|ahb_pixel_memory:pix1\|altsyncram:memory_rtl_0 " "Instantiated megafunction \"arm_soc:soc_inst\|ahb_pixel_memory:pix1\|altsyncram:memory_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 8 " "Parameter \"WIDTH_A\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 19 " "Parameter \"WIDTHAD_A\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 307200 " "Parameter \"NUMWORDS_A\" = \"307200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 8 " "Parameter \"WIDTH_B\" = \"8\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 19 " "Parameter \"WIDTHAD_B\" = \"19\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 307200 " "Parameter \"NUMWORDS_B\" = \"307200\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361712445 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1600361712445 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_40j1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_40j1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_40j1 " "Found entity 1: altsyncram_40j1" { } { { "db/altsyncram_40j1.tdf" "" { Text "/home/ks6n19/Documents/project/db/altsyncram_40j1.tdf" 34 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361712583 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361712583 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_3na.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_3na.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_3na " "Found entity 1: decode_3na" { } { { "db/decode_3na.tdf" "" { Text "/home/ks6n19/Documents/project/db/decode_3na.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361712879 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361712879 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_s2a.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_s2a.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_s2a " "Found entity 1: decode_s2a" { } { { "db/decode_s2a.tdf" "" { Text "/home/ks6n19/Documents/project/db/decode_s2a.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361712962 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361712962 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_jhb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_jhb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_jhb " "Found entity 1: mux_jhb" { } { { "db/mux_jhb.tdf" "" { Text "/home/ks6n19/Documents/project/db/mux_jhb.tdf" 23 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361713052 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361713052 ""}
-{ "Info" "ISGN_ELABORATION_HEADER" "arm_soc:soc_inst\|ahb_ram:ram_1\|altsyncram:memory_rtl_0 " "Elaborated megafunction instantiation \"arm_soc:soc_inst\|ahb_ram:ram_1\|altsyncram:memory_rtl_0\"" { } { } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361713129 ""}
-{ "Info" "ISGN_MEGAFN_PARAM_TOP" "arm_soc:soc_inst\|ahb_ram:ram_1\|altsyncram:memory_rtl_0 " "Instantiated megafunction \"arm_soc:soc_inst\|ahb_ram:ram_1\|altsyncram:memory_rtl_0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "OPERATION_MODE DUAL_PORT " "Parameter \"OPERATION_MODE\" = \"DUAL_PORT\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_A 32 " "Parameter \"WIDTH_A\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_A 12 " "Parameter \"WIDTHAD_A\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_A 4096 " "Parameter \"NUMWORDS_A\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTH_B 32 " "Parameter \"WIDTH_B\" = \"32\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WIDTHAD_B 12 " "Parameter \"WIDTHAD_B\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "NUMWORDS_B 4096 " "Parameter \"NUMWORDS_B\" = \"4096\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_A NONE " "Parameter \"ADDRESS_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_REG_B UNREGISTERED " "Parameter \"OUTDATA_REG_B\" = \"UNREGISTERED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_ACLR_B NONE " "Parameter \"ADDRESS_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "OUTDATA_ACLR_B NONE " "Parameter \"OUTDATA_ACLR_B\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ADDRESS_REG_B CLOCK0 " "Parameter \"ADDRESS_REG_B\" = \"CLOCK0\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INDATA_ACLR_A NONE " "Parameter \"INDATA_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "WRCONTROL_ACLR_A NONE " "Parameter \"WRCONTROL_ACLR_A\" = \"NONE\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "INIT_FILE db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif " "Parameter \"INIT_FILE\" = \"db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "READ_DURING_WRITE_MODE_MIXED_PORTS OLD_DATA " "Parameter \"READ_DURING_WRITE_MODE_MIXED_PORTS\" = \"OLD_DATA\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1600361713129 ""} } { } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1600361713129 ""}
-{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_nms1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_nms1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_nms1 " "Found entity 1: altsyncram_nms1" { } { { "db/altsyncram_nms1.tdf" "" { Text "/home/ks6n19/Documents/project/db/altsyncram_nms1.tdf" 28 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1600361713203 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361713203 ""}
-{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "/home/ks6n19/Documents/project/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"/home/ks6n19/Documents/project/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" { } { { "altsyncram.tdf" "" { Text "/srv/intelFPGA/16.1/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1600361713235 ""}
-{ "Warning" "WCDB_CDB_RAM_MIF_CONTAIN_DONT_CARE" "/home/ks6n19/Documents/project/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif " "Memory Initialization File or Hexadecimal (Intel-Format) File \"/home/ks6n19/Documents/project/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif\" contains \"don't care\" values -- overwriting them with 0s" { } { { "altsyncram.tdf" "" { Text "/srv/intelFPGA/16.1/quartus/libraries/megafunctions/altsyncram.tdf" 792 4 0 } } } 0 127007 "Memory Initialization File or Hexadecimal (Intel-Format) File \"%1!s!\" contains \"don't care\" values -- overwriting them with 0s" 0 0 "Analysis & Synthesis" 0 -1 1600361713239 ""}
-{ "Warning" "WSGN_CONNECTIVITY_WARNINGS" "1 " "1 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "%1!d! hierarchies have connectivity warnings - see the Connectivity Checks report folder" 0 0 "Analysis & Synthesis" 0 -1 1600361713779 ""}
-{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[0\] GND " "Pin \"LEDR\[0\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[1\] GND " "Pin \"LEDR\[1\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[2\] GND " "Pin \"LEDR\[2\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[3\] GND " "Pin \"LEDR\[3\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[4\] GND " "Pin \"LEDR\[4\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[5\] GND " "Pin \"LEDR\[5\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[6\] GND " "Pin \"LEDR\[6\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[7\] GND " "Pin \"LEDR\[7\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[8\] GND " "Pin \"LEDR\[8\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[8]"} { "Warning" "WMLS_MLS_STUCK_PIN" "LEDR\[9\] GND " "Pin \"LEDR\[9\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 15 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|LEDR[9]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[0\] VCC " "Pin \"HEX0\[0\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 16 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX0[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[1\] VCC " "Pin \"HEX0\[1\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 16 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX0[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX0\[5\] VCC " "Pin \"HEX0\[5\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 16 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX0[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[1\] VCC " "Pin \"HEX1\[1\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX1[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[2\] VCC " "Pin \"HEX1\[2\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX1[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[3\] VCC " "Pin \"HEX1\[3\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX1[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[4\] VCC " "Pin \"HEX1\[4\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[5\] VCC " "Pin \"HEX1\[5\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX1\[6\] VCC " "Pin \"HEX1\[6\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 17 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX1[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[0\] VCC " "Pin \"HEX2\[0\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 18 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX2[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[1\] VCC " "Pin \"HEX2\[1\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 18 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[2\] VCC " "Pin \"HEX2\[2\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 18 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[3\] VCC " "Pin \"HEX2\[3\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 18 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX2\[5\] VCC " "Pin \"HEX2\[5\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 18 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX2[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[0\] VCC " "Pin \"HEX3\[0\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 19 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX3[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[1\] VCC " "Pin \"HEX3\[1\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 19 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX3[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[2\] VCC " "Pin \"HEX3\[2\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 19 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "HEX3\[6\] VCC " "Pin \"HEX3\[6\]\" is stuck at VCC" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 19 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|HEX3[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[0\] GND " "Pin \"VGA_G\[0\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[1\] GND " "Pin \"VGA_G\[1\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[2\] GND " "Pin \"VGA_G\[2\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[3\] GND " "Pin \"VGA_G\[3\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[4\] GND " "Pin \"VGA_G\[4\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[5\] GND " "Pin \"VGA_G\[5\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[6\] GND " "Pin \"VGA_G\[6\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_G\[7\] GND " "Pin \"VGA_G\[7\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_G[7]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[0\] GND " "Pin \"VGA_B\[0\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[0]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[1\] GND " "Pin \"VGA_B\[1\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[2\] GND " "Pin \"VGA_B\[2\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[3\] GND " "Pin \"VGA_B\[3\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[4\] GND " "Pin \"VGA_B\[4\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[5\] GND " "Pin \"VGA_B\[5\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[6\] GND " "Pin \"VGA_B\[6\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "VGA_B\[7\] GND " "Pin \"VGA_B\[7\]\" is stuck at GND" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 20 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1600361717115 "|de1_soc_wrapper|VGA_B[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1600361717115 ""}
-{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" { } { } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1600361717358 ""}
-{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "17 " "17 registers lost all their fanouts during netlist optimizations." { } { } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1600361724800 ""}
-{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/ks6n19/Documents/project/output_files/de1_soc_wrapper.map.smsg " "Generated suppressed messages file /home/ks6n19/Documents/project/output_files/de1_soc_wrapper.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361725065 ""}
-{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1600361725650 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1600361725650 ""}
-{ "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN_HDR" "1 " "Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WCUT_CUT_UNNECESSARY_INPUT_PIN" "KEY\[3\] " "No output dependent on input pin \"KEY\[3\]\"" { } { { "behavioural/de1_soc_wrapper.sv" "" { Text "/home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv" 13 0 0 } } } 0 15610 "No output dependent on input pin \"%1!s!\"" 0 0 "Design Software" 0 -1 1600361726119 "|de1_soc_wrapper|KEY[3]"} } { } 0 21074 "Design contains %1!d! input pin(s) that do not drive logic" 0 0 "Analysis & Synthesis" 0 -1 1600361726119 ""}
-{ "Info" "ICUT_CUT_TM_SUMMARY" "4586 " "Implemented 4586 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1600361726132 ""} { "Info" "ICUT_CUT_TM_OPINS" "66 " "Implemented 66 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1600361726132 ""} { "Info" "ICUT_CUT_TM_LCELLS" "4169 " "Implemented 4169 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1600361726132 ""} { "Info" "ICUT_CUT_TM_RAMS" "336 " "Implemented 336 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1600361726132 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1600361726132 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 79 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 79 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1480 " "Peak virtual memory: 1480 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600361726170 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 17 17:55:26 2020 " "Processing ended: Thu Sep 17 17:55:26 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600361726170 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:32 " "Elapsed time: 00:00:32" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600361726170 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:45 " "Total CPU time (on all processors): 00:00:45" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600361726170 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1600361726170 ""}
diff --git a/db/de1_soc_wrapper.map.rdb b/db/de1_soc_wrapper.map.rdb
deleted file mode 100644
index f100b710bda686847afa3f34b6a5370f2f6ede22..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.map.rdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.map_bb.cdb b/db/de1_soc_wrapper.map_bb.cdb
deleted file mode 100644
index 8ecee30a7b50d9d8c8a22cc1d1deea7ad5a6e274..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.map_bb.cdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.map_bb.hdb b/db/de1_soc_wrapper.map_bb.hdb
deleted file mode 100644
index 110a8c5da11ff631226d5e5d2a8887107e7e9810..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.map_bb.hdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.npp.qmsg b/db/de1_soc_wrapper.npp.qmsg
deleted file mode 100644
index 0345ff7f042fbc4378f8f2aef0e334199c4b8fdf..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.npp.qmsg
+++ /dev/null
@@ -1,5 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1600362103177 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "Netlist Viewers Preprocess Quartus Prime " "Running Quartus Prime Netlist Viewers Preprocess" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition " "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600362103180 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 17 18:01:43 2020 " "Processing started: Thu Sep 17 18:01:43 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600362103180 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1600362103180 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_npp Msc_proj -c de1_soc_wrapper --netlist_type=sgate " "Command: quartus_npp Msc_proj -c de1_soc_wrapper --netlist_type=sgate" { } { } 0 0 "Command: %1!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1600362103180 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Netlist Viewers Preprocess" 0 -1 1600362103481 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "Netlist Viewers Preprocess 0 s 1 Quartus Prime " "Quartus Prime Netlist Viewers Preprocess was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "920 " "Peak virtual memory: 920 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600362103988 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 17 18:01:43 2020 " "Processing ended: Thu Sep 17 18:01:43 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600362103988 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600362103988 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600362103988 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Netlist Viewers Preprocess" 0 -1 1600362103988 ""}
diff --git a/db/de1_soc_wrapper.pre_map.hdb b/db/de1_soc_wrapper.pre_map.hdb
deleted file mode 100644
index f8aefe47e8ac87b759f8f52ef05f07d3923df766..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.pre_map.hdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif b/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif
deleted file mode 100644
index f0dc0cd3b887e2515682fa6fa2569ae197722985..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif
+++ /dev/null
@@ -1,4107 +0,0 @@
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diff --git a/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl_old.mif b/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl_old.mif
deleted file mode 100644
index f0dc0cd3b887e2515682fa6fa2569ae197722985..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl_old.mif
+++ /dev/null
@@ -1,4107 +0,0 @@
--- begin_signature
--- ahb_ram
--- end_signature
-WIDTH=32;
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-END;
diff --git a/db/de1_soc_wrapper.root_partition.map.reg_db.cdb b/db/de1_soc_wrapper.root_partition.map.reg_db.cdb
deleted file mode 100644
index 36f3afec794badaed2ed5aae17685472347d45a7..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.root_partition.map.reg_db.cdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.routing.rdb b/db/de1_soc_wrapper.routing.rdb
deleted file mode 100644
index 302a498873ceb265d47e4a3ba4f3f6172288fd94..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.routing.rdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.rtlv.hdb b/db/de1_soc_wrapper.rtlv.hdb
deleted file mode 100644
index 3dbecbe5dfd2db9b65f7af3c34355815d6d77604..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.rtlv.hdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.rtlv_sg.cdb b/db/de1_soc_wrapper.rtlv_sg.cdb
deleted file mode 100644
index e2d1814fb68ce2ddda06ce8d34f744fa06887a93..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.rtlv_sg.cdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.rtlv_sg_swap.cdb b/db/de1_soc_wrapper.rtlv_sg_swap.cdb
deleted file mode 100644
index 7362aef4cc3eca1dddd4cd2b5760566daa498019..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.rtlv_sg_swap.cdb and /dev/null differ
diff --git a/db/de1_soc_wrapper.sgate.nvd b/db/de1_soc_wrapper.sgate.nvd
deleted file mode 100644
index af143abf0e7b8f27f36acbedf2f295b418d7ced7..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.sgate.nvd and /dev/null differ
diff --git a/db/de1_soc_wrapper.sgate_sm.nvd b/db/de1_soc_wrapper.sgate_sm.nvd
deleted file mode 100644
index 88eaa3513d06ae427ecdd8a655ebb01616d8e6a5..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.sgate_sm.nvd and /dev/null differ
diff --git a/db/de1_soc_wrapper.sld_design_entry_dsc.sci b/db/de1_soc_wrapper.sld_design_entry_dsc.sci
deleted file mode 100644
index 3dd3ad2c2539a24d5e1c82f9f21c0ec357f60366..0000000000000000000000000000000000000000
Binary files a/db/de1_soc_wrapper.sld_design_entry_dsc.sci and /dev/null differ
diff --git a/db/de1_soc_wrapper.smart_action.txt b/db/de1_soc_wrapper.smart_action.txt
deleted file mode 100644
index c8e8a135c9291129f28f1fcaa018fa29a7cc96fe..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.smart_action.txt
+++ /dev/null
@@ -1 +0,0 @@
-DONE
diff --git a/db/de1_soc_wrapper.sta.qmsg b/db/de1_soc_wrapper.sta.qmsg
deleted file mode 100644
index a68eba93f3ad8f5a9e0823279e528981cb8b9a08..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.sta.qmsg
+++ /dev/null
@@ -1,52 +0,0 @@
-{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1600361930398 ""}
-{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus Prime " "Running Quartus Prime TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition " "Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1600361930400 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Sep 17 17:58:50 2020 " "Processing started: Thu Sep 17 17:58:50 2020" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1600361930400 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361930400 ""}
-{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Msc_proj -c de1_soc_wrapper " "Command: quartus_sta Msc_proj -c de1_soc_wrapper" { } { } 0 0 "Command: %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361930400 ""}
-{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "TimeQuest Timing Analyzer" 0 0 1600361930701 ""}
-{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361931624 ""}
-{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "16 24 " "Parallel compilation is enabled and will use 16 of the 24 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361931624 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361931669 ""}
-{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361931669 ""}
-{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "de1_soc_wrapper.sdc " "Synopsys Design Constraints File file not found: 'de1_soc_wrapper.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361932909 ""}
-{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361932910 ""}
-{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name CLOCK_50 CLOCK_50 " "create_clock -period 1.000 -name CLOCK_50 CLOCK_50" { } { } 0 332105 "%1!s!" 0 0 "Design Software" 0 -1 1600361932983 ""} } { } 0 332105 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361932983 ""}
-{ "Info" "ISTA_NO_CLOCK_UNCERTAINTY_FOUND_DERIVING" "\"derive_clock_uncertainty\" " "No user constrained clock uncertainty found in the design. Calling \"derive_clock_uncertainty\"" { } { } 0 332143 "No user constrained clock uncertainty found in the design. Calling %1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361933040 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361933040 ""}
-{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "TimeQuest Timing Analyzer" 0 0 1600361933044 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 85C Model" { } { } 0 0 "Analyzing Slow 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1600361933064 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1600361936686 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361936686 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -12.502 " "Worst-case setup slack is -12.502" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -12.502 -113780.122 CLOCK_50 " " -12.502 -113780.122 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936695 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361936695 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.357 " "Worst-case hold slack is 0.357" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936868 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.357 0.000 CLOCK_50 " " 0.357 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936868 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361936868 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361936878 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361936887 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936901 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -46900.052 CLOCK_50 " " -2.636 -46900.052 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361936901 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361936901 ""}
-{ "Info" "0" "" "Analyzing Slow 1100mV 0C Model" { } { } 0 0 "Analyzing Slow 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1600361936989 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361937050 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361939662 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361940367 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1600361940832 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361940832 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -12.353 " "Worst-case setup slack is -12.353" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361940840 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361940840 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -12.353 -110175.196 CLOCK_50 " " -12.353 -110175.196 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361940840 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361940840 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.353 " "Worst-case hold slack is 0.353" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361941011 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361941011 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.353 0.000 CLOCK_50 " " 0.353 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361941011 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361941011 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361941020 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361941027 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361941042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361941042 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -46925.515 CLOCK_50 " " -2.636 -46925.515 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361941042 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361941042 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 85C Model" { } { } 0 0 "Analyzing Fast 1100mV 85C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1600361941140 ""}
-{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361941354 ""}
-{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361943728 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361944316 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1600361944488 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361944488 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -7.389 " "Worst-case setup slack is -7.389" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944497 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944497 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -7.389 -65801.349 CLOCK_50 " " -7.389 -65801.349 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944497 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361944497 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.179 " "Worst-case hold slack is 0.179" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944665 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.179 0.000 CLOCK_50 " " 0.179 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944665 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361944665 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361944672 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361944680 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944695 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -46009.813 CLOCK_50 " " -2.636 -46009.813 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361944695 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361944695 ""}
-{ "Info" "0" "" "Analyzing Fast 1100mV 0C Model" { } { } 0 0 "Analyzing Fast 1100mV 0C Model" 0 0 "TimeQuest Timing Analyzer" 0 0 1600361944788 ""}
-{ "Info" "ISTA_DERIVE_CLOCK_UNCERTAINTY_INFO" "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties. " "Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties." { } { } 0 332123 "%1!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361945313 ""}
-{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { { "Info" "ISTA_TIMING_NOT_MET_USE_ADA" "" "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." { } { } 0 11105 "For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer." 0 0 "Design Software" 0 -1 1600361945478 ""} } { } 1 332148 "Timing requirements not met" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361945478 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "setup -6.467 " "Worst-case setup slack is -6.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945487 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945487 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -6.467 -56821.323 CLOCK_50 " " -6.467 -56821.323 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945487 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361945487 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.171 " "Worst-case hold slack is 0.171" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945654 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.171 0.000 CLOCK_50 " " 0.171 0.000 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945654 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361945654 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361945664 ""}
-{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361945671 ""}
-{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -2.636 " "Worst-case minimum pulse width slack is -2.636" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945691 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -2.636 -46024.842 CLOCK_50 " " -2.636 -46024.842 CLOCK_50 " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1600361945691 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361945691 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361947785 ""}
-{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361947789 ""}
-{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 6 s Quartus Prime " "Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1746 " "Peak virtual memory: 1746 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1600361947956 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Sep 17 17:59:07 2020 " "Processing ended: Thu Sep 17 17:59:07 2020" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1600361947956 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:17 " "Elapsed time: 00:00:17" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1600361947956 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:51 " "Total CPU time (on all processors): 00:00:51" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1600361947956 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "TimeQuest Timing Analyzer" 0 -1 1600361947956 ""}
diff --git a/db/de1_soc_wrapper.sta.rdb b/db/de1_soc_wrapper.sta.rdb
deleted file mode 100644
index d6e4bb61719e6c6a645938117ab5f9137a7a4249..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.sta_cmp.6_slow_1100mv_85c.tdb b/db/de1_soc_wrapper.sta_cmp.6_slow_1100mv_85c.tdb
deleted file mode 100644
index 8be30b39f5f5585c39daf23519b1563d52d5f2ce..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.tis_db_list.ddb b/db/de1_soc_wrapper.tis_db_list.ddb
deleted file mode 100644
index 219c1f43aac19cadc920736f88af2158d34b9171..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.tiscmp.fast_1100mv_0c.ddb b/db/de1_soc_wrapper.tiscmp.fast_1100mv_0c.ddb
deleted file mode 100644
index f2b27f55ce44140ae1a07bb30a74a98f928147c0..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.tiscmp.fast_1100mv_85c.ddb b/db/de1_soc_wrapper.tiscmp.fast_1100mv_85c.ddb
deleted file mode 100644
index e1c9f4891c0bde722421db366ba9ec7eea76cbc4..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.tiscmp.slow_1100mv_0c.ddb b/db/de1_soc_wrapper.tiscmp.slow_1100mv_0c.ddb
deleted file mode 100644
index 308cd8c2c89ed2e0db89e5711d62da33775d9a19..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.tiscmp.slow_1100mv_85c.ddb b/db/de1_soc_wrapper.tiscmp.slow_1100mv_85c.ddb
deleted file mode 100644
index 6c81741bb9459d3bfd75d5573905419ef78c1e86..0000000000000000000000000000000000000000
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diff --git a/db/de1_soc_wrapper.tmw_info b/db/de1_soc_wrapper.tmw_info
deleted file mode 100644
index 33f907ddf0a71c0b2a945ecd5a18e8cfd7168ee4..0000000000000000000000000000000000000000
--- a/db/de1_soc_wrapper.tmw_info
+++ /dev/null
@@ -1,7 +0,0 @@
-start_full_compilation:s:00:04:19
-start_analysis_synthesis:s:00:00:33-start_full_compilation
-start_analysis_elaboration:s-start_full_compilation
-start_fitter:s:00:03:09-start_full_compilation
-start_assembler:s:00:00:14-start_full_compilation
-start_timing_analyzer:s:00:00:19-start_full_compilation
-start_eda_netlist_writer:s:00:00:04-start_full_compilation
diff --git a/db/de1_soc_wrapper.vpr.ammdb b/db/de1_soc_wrapper.vpr.ammdb
deleted file mode 100644
index 4a7026c86d3dcf6f18998cf2df130cdfde90a5c0..0000000000000000000000000000000000000000
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diff --git a/incremental_db/README b/incremental_db/README
deleted file mode 100644
index 9f62dcda0512fec7b5b55c11a13d70f91548996f..0000000000000000000000000000000000000000
--- a/incremental_db/README
+++ /dev/null
@@ -1,11 +0,0 @@
-This folder contains data for incremental compilation.
-
-The compiled_partitions sub-folder contains previous compilation results for each partition.
-As long as this folder is preserved, incremental compilation results from earlier compiles
-can be re-used. To perform a clean compilation from source files for all partitions, both
-the db and incremental_db folder should be removed.
-
-The imported_partitions sub-folder contains the last imported QXP for each imported partition.
-As long as this folder is preserved, imported partitions will be automatically re-imported
-when the db or incremental_db/compiled_partitions folders are removed.
-
diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.db_info b/incremental_db/compiled_partitions/de1_soc_wrapper.db_info
deleted file mode 100644
index d94236f565fcb2333960e18b5eb9aa4aa07cf7ee..0000000000000000000000000000000000000000
--- a/incremental_db/compiled_partitions/de1_soc_wrapper.db_info
+++ /dev/null
@@ -1,3 +0,0 @@
-Quartus_Version = Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-Version_Index = 419482368
-Creation_Time = Thu Sep 17 17:55:08 2020
diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.ammdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.ammdb
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index 8a45d87cd99c3cba8bc5b6388ad63e77450e72a7..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.cdb
deleted file mode 100644
index 0bc75676ddb766fbfa13da0d35d9e2764bddd770..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.dfp b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.dfp
deleted file mode 100644
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hbdb.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hbdb.cdb
deleted file mode 100644
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hbdb.hdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hbdb.hdb
deleted file mode 100644
index 30271e879a6333911419057f5965f4c49fb0ba47..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hbdb.sig b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hbdb.sig
deleted file mode 100644
index af9b8e9aa113827749627f5921914b7bff5208a3..0000000000000000000000000000000000000000
--- a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.hdb
deleted file mode 100644
index 72eab70262fce09eb743197c59a0e839a8dab8eb..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.logdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.logdb
deleted file mode 100644
index 626799f0f85326a8c1fc522db584e86cdfccd51f..0000000000000000000000000000000000000000
--- a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.logdb
+++ /dev/null
@@ -1 +0,0 @@
-v1
diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.rcfdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.cmp.rcfdb
deleted file mode 100644
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.cdb
deleted file mode 100644
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.dpi b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.dpi
deleted file mode 100644
index dd6317008cffb05f8ba2a44b13411e6794c0daac..0000000000000000000000000000000000000000
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deleted file mode 100644
index 30702bd0e9231e49fec26c017c1a46806f05299c..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hbdb.hb_info b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hbdb.hb_info
deleted file mode 100644
index 8210c55998f9226aeba57897397a9e541102c45e..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hbdb.hdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hbdb.hdb
deleted file mode 100644
index a4e41a7f94c74231e6d7e8953665816405008518..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hbdb.sig b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hbdb.sig
deleted file mode 100644
index af9b8e9aa113827749627f5921914b7bff5208a3..0000000000000000000000000000000000000000
--- a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hbdb.sig
+++ /dev/null
@@ -1 +0,0 @@
-7aee213afbf8301ed5eefc8c827f49a3
\ No newline at end of file
diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.hdb
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.kpt b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.kpt
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.olf.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.olf.cdb
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index ddfe0382f06a8a12af16082515af5aa53c0a3e42..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.olm.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.olm.cdb
deleted file mode 100644
index 24fe9e23d98e21420cc5607889566e2e9e420b18..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.oln.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.oln.cdb
deleted file mode 100644
index 503e91f8275945b034e6f3e6aecf6e3597e7738a..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.opi b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.opi
deleted file mode 100644
index 56a6051ca2b02b04ef92d5150c9ef600403cb1de..0000000000000000000000000000000000000000
--- a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.opi
+++ /dev/null
@@ -1 +0,0 @@
-1
\ No newline at end of file
diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.orf.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.orf.cdb
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.orm.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.map.orm.cdb
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index de4ab23ec7628a65c8e7f9fc90ad92a68426362c..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.cdb
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.hbdb.cdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.hbdb.cdb
deleted file mode 100644
index 30702bd0e9231e49fec26c017c1a46806f05299c..0000000000000000000000000000000000000000
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.hbdb.hdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.hbdb.hdb
deleted file mode 100644
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.hdb b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.hdb
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diff --git a/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.kpt b/incremental_db/compiled_partitions/de1_soc_wrapper.root_partition.rrp.kpt
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index 3a734d628cc011a5f68252dc7563129e9e554647..0000000000000000000000000000000000000000
Binary files a/incremental_db/compiled_partitions/de1_soc_wrapper.rrs.cdb and /dev/null differ
diff --git a/output_files/de1_soc_wrapper.asm.rpt b/output_files/de1_soc_wrapper.asm.rpt
deleted file mode 100644
index 89720e11825987a0003e0744588cc1f7cad9ba9e..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.asm.rpt
+++ /dev/null
@@ -1,92 +0,0 @@
-Assembler report for de1_soc_wrapper
-Thu Sep 17 17:58:48 2020
-Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Assembler Summary
- 3. Assembler Settings
- 4. Assembler Generated Files
- 5. Assembler Device Options: de1_soc_wrapper.sof
- 6. Assembler Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------+
-; Assembler Summary ;
-+-----------------------+---------------------------------------+
-; Assembler Status ; Successful - Thu Sep 17 17:58:48 2020 ;
-; Revision Name ; de1_soc_wrapper ;
-; Top-level Entity Name ; de1_soc_wrapper ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-+-----------------------+---------------------------------------+
-
-
-+----------------------------------+
-; Assembler Settings ;
-+--------+---------+---------------+
-; Option ; Setting ; Default Value ;
-+--------+---------+---------------+
-
-
-+---------------------------+
-; Assembler Generated Files ;
-+---------------------------+
-; File Name ;
-+---------------------------+
-; de1_soc_wrapper.sof ;
-+---------------------------+
-
-
-+-----------------------------------------------+
-; Assembler Device Options: de1_soc_wrapper.sof ;
-+----------------+------------------------------+
-; Option ; Setting ;
-+----------------+------------------------------+
-; Device ; 5CSEMA5F31C6 ;
-; JTAG usercode ; 0x075B9DC8 ;
-; Checksum ; 0x075B9DC8 ;
-+----------------+------------------------------+
-
-
-+--------------------+
-; Assembler Messages ;
-+--------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Assembler
- Info: Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
- Info: Processing started: Thu Sep 17 17:58:36 2020
-Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (115030): Assembler is generating device programming files
-Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
- Info: Peak virtual memory: 1153 megabytes
- Info: Processing ended: Thu Sep 17 17:58:48 2020
- Info: Elapsed time: 00:00:12
- Info: Total CPU time (on all processors): 00:00:11
-
-
diff --git a/output_files/de1_soc_wrapper.done b/output_files/de1_soc_wrapper.done
deleted file mode 100644
index e69ea427c76cddf58b1698154b9b2645a90fa4f4..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.done
+++ /dev/null
@@ -1 +0,0 @@
-Thu Sep 17 18:01:44 2020
diff --git a/output_files/de1_soc_wrapper.eda.rpt b/output_files/de1_soc_wrapper.eda.rpt
deleted file mode 100644
index 2526561133ceb6923227a15a5b56016689029c6a..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.eda.rpt
+++ /dev/null
@@ -1,96 +0,0 @@
-EDA Netlist Writer report for de1_soc_wrapper
-Thu Sep 17 17:59:11 2020
-Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. EDA Netlist Writer Summary
- 3. Simulation Settings
- 4. Simulation Generated Files
- 5. EDA Netlist Writer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-------------------------------------------------------------------+
-; EDA Netlist Writer Summary ;
-+---------------------------+---------------------------------------+
-; EDA Netlist Writer Status ; Successful - Thu Sep 17 17:59:11 2020 ;
-; Revision Name ; de1_soc_wrapper ;
-; Top-level Entity Name ; de1_soc_wrapper ;
-; Family ; Cyclone V ;
-; Simulation Files Creation ; Successful ;
-+---------------------------+---------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------+
-; Simulation Settings ;
-+---------------------------------------------------------------------------------------------------+---------------------------------+
-; Option ; Setting ;
-+---------------------------------------------------------------------------------------------------+---------------------------------+
-; Tool Name ; ModelSim-Altera (SystemVerilog) ;
-; Generate functional simulation netlist ; Off ;
-; Time scale ; 1 ps ;
-; Truncate long hierarchy paths ; Off ;
-; Map illegal HDL characters ; Off ;
-; Flatten buses into individual nodes ; Off ;
-; Maintain hierarchy ; Off ;
-; Bring out device-wide set/reset signals as ports ; Off ;
-; Enable glitch filtering ; Off ;
-; Do not write top level VHDL entity ; Off ;
-; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ;
-; Architecture name in VHDL output netlist ; structure ;
-; Generate third-party EDA tool command script for RTL functional simulation ; Off ;
-; Generate third-party EDA tool command script for gate-level simulation ; Off ;
-+---------------------------------------------------------------------------------------------------+---------------------------------+
-
-
-+------------------------------------------------------------------------+
-; Simulation Generated Files ;
-+------------------------------------------------------------------------+
-; Generated Files ;
-+------------------------------------------------------------------------+
-; /home/ks6n19/Documents/project/simulation/modelsim/de1_soc_wrapper.svo ;
-+------------------------------------------------------------------------+
-
-
-+-----------------------------+
-; EDA Netlist Writer Messages ;
-+-----------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime EDA Netlist Writer
- Info: Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
- Info: Processing started: Thu Sep 17 17:59:09 2020
-Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Warning (10905): Generated the EDA functional simulation netlist because it is the only supported netlist type for this device.
-Info (204019): Generated file de1_soc_wrapper.svo in folder "/home/ks6n19/Documents/project/simulation/modelsim/" for EDA simulation tool
-Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 1355 megabytes
- Info: Processing ended: Thu Sep 17 17:59:12 2020
- Info: Elapsed time: 00:00:03
- Info: Total CPU time (on all processors): 00:00:03
-
-
diff --git a/output_files/de1_soc_wrapper.fit.rpt b/output_files/de1_soc_wrapper.fit.rpt
deleted file mode 100644
index bfa9cfe115f99aaaf6db3af256426b95f7e473bb..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.fit.rpt
+++ /dev/null
@@ -1,2723 +0,0 @@
-Fitter report for de1_soc_wrapper
-Thu Sep 17 17:58:32 2020
-Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Fitter Summary
- 3. Fitter Settings
- 4. Parallel Compilation
- 5. Fitter Netlist Optimizations
- 6. Incremental Compilation Preservation Summary
- 7. Incremental Compilation Partition Settings
- 8. Incremental Compilation Placement Preservation
- 9. Pin-Out File
- 10. Fitter Resource Usage Summary
- 11. Fitter Partition Statistics
- 12. Input Pins
- 13. Output Pins
- 14. I/O Bank Usage
- 15. All Package Pins
- 16. I/O Assignment Warnings
- 17. Fitter Resource Utilization by Entity
- 18. Delay Chain Summary
- 19. Pad To Core Delay Chain Fanout
- 20. Control Signals
- 21. Global & Other Fast Signals
- 22. Non-Global High Fan-Out Signals
- 23. Fitter RAM Summary
- 24. Routing Usage Summary
- 25. I/O Rules Summary
- 26. I/O Rules Details
- 27. I/O Rules Matrix
- 28. Fitter Device Options
- 29. Operating Settings and Conditions
- 30. Estimated Delay Added for Hold Timing Summary
- 31. Estimated Delay Added for Hold Timing Details
- 32. Fitter Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Fitter Summary ;
-+---------------------------------+-------------------------------------------------+
-; Fitter Status ; Successful - Thu Sep 17 17:58:32 2020 ;
-; Quartus Prime Version ; 16.1.2 Build 203 01/18/2017 SJ Standard Edition ;
-; Revision Name ; de1_soc_wrapper ;
-; Top-level Entity Name ; de1_soc_wrapper ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 2,241 / 32,070 ( 7 % ) ;
-; Total registers ; 1364 ;
-; Total pins ; 81 / 457 ( 18 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 2,588,672 / 4,065,280 ( 64 % ) ;
-; Total RAM Blocks ; 316 / 397 ( 80 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Settings ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Option ; Setting ; Default Value ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Minimum Core Junction Temperature ; 0 ; ;
-; Maximum Core Junction Temperature ; 85 ; ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Router Timing Optimization Level ; Normal ; Normal ;
-; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
-; Placement Effort Multiplier ; 1.0 ; 1.0 ;
-; Device initialization clock source ; INIT_INTOSC ; INIT_INTOSC ;
-; Optimize Hold Timing ; All Paths ; All Paths ;
-; Optimize Multi-Corner Timing ; On ; On ;
-; Auto RAM to MLAB Conversion ; On ; On ;
-; Equivalent RAM and MLAB Power Up ; Auto ; Auto ;
-; Equivalent RAM and MLAB Paused Read Capabilities ; Care ; Care ;
-; PowerPlay Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
-; SSN Optimization ; Off ; Off ;
-; Optimize Timing ; Normal compilation ; Normal compilation ;
-; Optimize Timing for ECOs ; Off ; Off ;
-; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
-; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
-; Final Placement Optimizations ; Automatically ; Automatically ;
-; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
-; Fitter Initial Placement Seed ; 1 ; 1 ;
-; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
-; Weak Pull-Up Resistor ; Off ; Off ;
-; Enable Bus-Hold Circuitry ; Off ; Off ;
-; Auto Packed Registers ; Auto ; Auto ;
-; Auto Delay Chains ; On ; On ;
-; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
-; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
-; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
-; Perform Register Duplication for Performance ; Off ; Off ;
-; Perform Register Retiming for Performance ; Off ; Off ;
-; Perform Asynchronous Signal Pipelining ; Off ; Off ;
-; Fitter Effort ; Auto Fit ; Auto Fit ;
-; Physical Synthesis Effort Level ; Normal ; Normal ;
-; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
-; Auto Register Duplication ; Auto ; Auto ;
-; Auto Global Clock ; On ; On ;
-; Auto Global Register Control Signals ; On ; On ;
-; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
-; Synchronizer Identification ; Auto ; Auto ;
-; Enable Beneficial Skew Optimization ; On ; On ;
-; Optimize Design for Metastability ; On ; On ;
-; Active Serial clock source ; FREQ_100MHz ; FREQ_100MHz ;
-; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
-; Clamping Diode ; Off ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
-; Advanced Physical Optimization ; On ; On ;
-+----------------------------------------------------------------------------+---------------------------------------+---------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 24 ;
-; Maximum allowed ; 16 ;
-; ; ;
-; Average used ; 1.34 ;
-; Maximum used ; 16 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 3.0% ;
-; Processor 3 ; 2.9% ;
-; Processor 4 ; 2.8% ;
-; Processor 5 ; 2.3% ;
-; Processor 6 ; 2.2% ;
-; Processor 7 ; 2.2% ;
-; Processor 8 ; 2.2% ;
-; Processor 9 ; 2.1% ;
-; Processor 10 ; 2.1% ;
-; Processor 11 ; 2.1% ;
-; Processor 12 ; 2.1% ;
-; Processor 13 ; 2.1% ;
-; Processor 14 ; 2.1% ;
-; Processor 15 ; 2.1% ;
-; Processor 16 ; 2.1% ;
-+----------------------------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Netlist Optimizations ;
-+------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------------------+------------------+-----------------------+
-; Node ; Action ; Operation ; Reason ; Node Port ; Node Port Name ; Destination Node ; Destination Port ; Destination Port Name ;
-+------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------------------+------------------+-----------------------+
-; CLOCK_50~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
-; KEY[2]~inputCLKENA0 ; Created ; Placement ; Fitter Periphery Placement ; ; ; ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A4t2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A4t2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A8h3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A8h3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A9p2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A9p2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A933z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|A933z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aff3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aff3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ajn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ajn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|An73z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|An73z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|An83z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|An83z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aok2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aok2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aqp2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aqp2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Arh3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Arh3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ark2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ark2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aru2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aru2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Asr2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Asr2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aud3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aud3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Auk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Auk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ay53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ay53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B5u2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B5u2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B6j2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B6j2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B9g3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B9g3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B173z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B173z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B613z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B613z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B943z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B943z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bf93z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bf93z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bjd3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bjd3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bk23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bk23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bmb3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bmb3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bus2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bus2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C4b3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C4b3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C5v2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C5v2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cai3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cai3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cam2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cam2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cao2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cao2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cc63z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cc63z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ccq2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ccq2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cgu2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cgu2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cps2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cps2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cxc3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cxc3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|D1p2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|D1p2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|D923z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|D923z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dcs2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dcs2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dhb3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dhb3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Djh3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Djh3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Djv2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Djv2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dks2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dks2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dkx2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dkx2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dtj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dtj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Duv2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Duv2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dvy2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dvy2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dwl2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dwl2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dy23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dy23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|E153z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|E153z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ec43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ec43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ecp2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ecp2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Edl2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Edl2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Efp2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Efp2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ejm2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ejm2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Euh3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Euh3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Eyg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Eyg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Eyr2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Eyr2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|F0y2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|F0y2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|F4c3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|F4c3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|F473z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|F473z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fcj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fcj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fed3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fed3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ffj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ffj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fhc3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fhc3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fij2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fij2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fn13z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fn13z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ft73z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ft73z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ftf3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ftf3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fxu2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fxu2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fzl2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fzl2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G0w2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G0w2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G8n2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G8n2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G123z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G123z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gcb3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gcb3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gf43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gf43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gf53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gf53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gf73z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gf73z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gfg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gfg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gfq2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gfq2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gjt2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gjt2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gmd3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gmd3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gmm2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gmm2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gto2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gto2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gza3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gza3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H2f3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H2f3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H3d3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H3d3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H9i2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H9i2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H783z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H783z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hak2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hak2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hi83z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hi83z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hmh3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hmh3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hmv2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hmv2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hnr2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hnr2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hq23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hq23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hq33z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hq33z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hqg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hqg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ht53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ht53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I2t2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I2t2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I7r2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I7r2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I113z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I113z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I453z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I453z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I463z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I463z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I793z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I793z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ibe3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ibe3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Idk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Idk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Igl2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Igl2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ilf3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ilf3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ilp2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ilp2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Imt2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Imt2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ipb3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ipb3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ipn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ipn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Iua3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Iua3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ixt2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ixt2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J0v2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J0v2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J5i3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J5i3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J5m2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J5m2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J9d3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J9d3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J773z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J773z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jbu2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jbu2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jca3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jca3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jky2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jky2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jl93z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jl93z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jux2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jux2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jw93z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jw93z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jxs2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jxs2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K1z2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K1z2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K6y2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K6y2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K9z2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K9z2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K423z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K423z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ka93z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ka93z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ki53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ki53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kjk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kjk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Knz2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Knz2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ksm2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ksm2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kss2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kss2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kt23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kt23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kt43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kt43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kyi2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kyi2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kzf3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kzf3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L8t2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L8t2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L733z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L733z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L753z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L753z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ll63z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ll63z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lny2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lny2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lph3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lph3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lpt2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lpt2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lpv2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lpv2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lq03z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lq03z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lsd3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lsd3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ltg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ltg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lw53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lw53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M0i3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M0i3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M1j2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M1j2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M2b3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M2b3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M3u2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M3u2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M5f3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M5f3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M9y2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M9y2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M413z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M413z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M743z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M743z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mhn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mhn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mi23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mi23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mi33z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mi33z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mof3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mof3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mzp2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mzp2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|N8o2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|N8o2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Na53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Na53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Na63z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Na63z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nag3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nag3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Naq2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Naq2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nbm2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nbm2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nl53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nl53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Npk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Npk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nsk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nsk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nt03z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nt03z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nz73z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nz73z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nz83z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nz83z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O2g3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O2g3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O5t2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O5t2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O723z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O723z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Oar2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Oar2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Okn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Okn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ow33z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ow33z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ow43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ow43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Owq2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Owq2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|P2a3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|P2a3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pa33z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pa33z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pab3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pab3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pbl2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pbl2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pdi2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pdi2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pet2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pet2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Po63z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Po63z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Po73z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Po73z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Po83z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Po83z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Poq2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Poq2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Psh3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Psh3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Psn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Psn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pst2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pst2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Psv2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Psv2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pty2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pty2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pvd3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pvd3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pwg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pwg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q2q2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q2q2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q7j2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q7j2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q713z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q713z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qa43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qa43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qdj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qdj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qem2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qem2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qg93z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qg93z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qi03z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qi03z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qml2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qml2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qwr2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qwr2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qz33z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qz33z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qz43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qz43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qzq2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qzq2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R0t2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R0t2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R1w2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R1w2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R6v2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R6v2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R8x2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R8x2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R283z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R283z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R293z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R293z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rd53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rd53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rd63z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rd63z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rdg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rdg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rix2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rix2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rni2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rni2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ruj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ruj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rvu2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rvu2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S2p2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S2p2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S4w2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S4w2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S8k2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S8k2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S703z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S703z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sa23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sa23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sgj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sgj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sjj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sjj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Skm2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Skm2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Skv2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Skv2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Svk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Svk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Svs2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Svs2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Swy2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Swy2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sz23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sz23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Szr2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Szr2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T1d3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T1d3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T8f3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T8f3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T9v2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T9v2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T253z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T253z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Taa3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Taa3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Td33z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Td33z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tdp2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tdp2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tel2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tel2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tib3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tib3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tki2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tki2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Trq2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Trq2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tse3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tse3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tvn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tvn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tvt2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tvt2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Twz2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Twz2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tyx2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tyx2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tzg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tzg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U2x2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U2x2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U9u2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U9u2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uaj2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uaj2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ufx2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ufx2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ujo2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ujo2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ujp2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ujp2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uku2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uku2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uo13z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uo13z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uu73z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uu73z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uu83z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uu83z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uup2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uup2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uyv2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Uyv2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|V4d3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|V4d3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|V223z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|V223z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|V883z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|V883z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vaw2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vaw2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vfd3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vfd3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vg53z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vg53z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vgg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vgg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vgs2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vgs2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vhk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vhk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vr43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vr43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vu93z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vu93z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vxf3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vxf3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vzz2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vzz2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W4y2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W4y2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W893z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W893z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wai2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wai2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wbk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wbk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wce3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wce3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wd23z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wd23z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wj63z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wj63z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wj73z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wj73z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wj83z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wj83z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wnh3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wnh3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wnt2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wnt2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wnu2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wnu2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wo03z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wo03z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wor2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wor2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wqd3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wqd3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wqm2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wqm2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wzy2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wzy2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X1e3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X1e3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X213z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X213z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X533z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X533z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X553z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|X553z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xdb3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xdb3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xg33z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xg33z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xly2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xly2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xx93z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xx93z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xyh3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xyh3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xyn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xyn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Y1u2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Y1u2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Y1v2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Y1v2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Y6o2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Y6o2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yaz2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yaz2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ycu2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ycu2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yd03z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yd03z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yfn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yfn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yr13z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yr13z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yx63z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yx63z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z2h3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z2h3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z4l2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z4l2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zcn2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zcn2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zjg3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zjg3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zkk2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zkk2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zoy2z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zoy2z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zu43z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zu43z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zva3z4 ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zva3z4~DUPLICATE ; ; ;
-; arm_soc:soc_inst|ahb_interconnect:interconnect_1|mux_sel[2] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|ahb_interconnect:interconnect_1|mux_sel[2]~DUPLICATE ; ; ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[8] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[8]~DUPLICATE ; ; ;
-; arm_soc:soc_inst|ahb_ram:ram_1|byte_select[1] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; arm_soc:soc_inst|ahb_ram:ram_1|byte_select[1]~DUPLICATE ; ; ;
-; razzle:raz_inst|H_count[0] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; razzle:raz_inst|H_count[0]~DUPLICATE ; ; ;
-; razzle:raz_inst|H_count[3] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; razzle:raz_inst|H_count[3]~DUPLICATE ; ; ;
-; razzle:raz_inst|pixel_y[5] ; Duplicated ; Router Logic Cell Insertion and Logic Duplication ; Routability optimization ; ; ; razzle:raz_inst|pixel_y[5]~DUPLICATE ; ; ;
-+------------------------------------------------------------------+------------+---------------------------------------------------+----------------------------+-----------+----------------+----------------------------------------------------------------------------+------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Incremental Compilation Preservation Summary ;
-+---------------------+---------------------+----------------------------+--------------------------+
-; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
-+---------------------+---------------------+----------------------------+--------------------------+
-; Placement (by node) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 4974 ) ; 0.00 % ( 0 / 4974 ) ; 0.00 % ( 0 / 4974 ) ;
-; -- Achieved ; 0.00 % ( 0 / 4974 ) ; 0.00 % ( 0 / 4974 ) ; 0.00 % ( 0 / 4974 ) ;
-; ; ; ; ;
-; Routing (by net) ; ; ; ;
-; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
-+---------------------+---------------------+----------------------------+--------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Partition Settings ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
-+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------+
-; Incremental Compilation Placement Preservation ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-; Top ; 0.00 % ( 0 / 4974 ) ; N/A ; Source File ; N/A ; ;
-; hard_block:auto_generated_inst ; 0.00 % ( 0 / 0 ) ; N/A ; Source File ; N/A ; ;
-+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
-
-
-+--------------+
-; Pin-Out File ;
-+--------------+
-The pin-out file can be found in /home/ks6n19/Documents/project/output_files/de1_soc_wrapper.pin.
-
-
-+---------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+-------------------------------------------------------------+-----------------------+-------+
-; Resource ; Usage ; % ;
-+-------------------------------------------------------------+-----------------------+-------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 2,241 / 32,070 ; 7 % ;
-; ALMs needed [=A-B+C] ; 2,241 ; ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 2,512 / 32,070 ; 8 % ;
-; [a] ALMs used for LUT logic and registers ; 215 ; ;
-; [b] ALMs used for LUT logic ; 1,998 ; ;
-; [c] ALMs used for registers ; 299 ; ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; ;
-; [B] Estimate of ALMs recoverable by dense packing ; 315 / 32,070 ; < 1 % ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 44 / 32,070 ; < 1 % ;
-; [a] Due to location constrained logic ; 0 ; ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; ;
-; [c] Due to LAB input limits ; 44 ; ;
-; [d] Due to virtual I/Os ; 0 ; ;
-; ; ; ;
-; Difficulty packing design ; Low ; ;
-; ; ; ;
-; Total LABs: partially or completely used ; 316 / 3,207 ; 10 % ;
-; -- Logic LABs ; 316 ; ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 3,449 ; ;
-; -- 7 input functions ; 30 ; ;
-; -- 6 input functions ; 1,157 ; ;
-; -- 5 input functions ; 730 ; ;
-; -- 4 input functions ; 772 ; ;
-; -- <=3 input functions ; 760 ; ;
-; Combinational ALUT usage for route-throughs ; 93 ; ;
-; ; ; ;
-; Dedicated logic registers ; 1,364 ; ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 1,027 / 64,140 ; 2 % ;
-; -- Secondary logic registers ; 337 / 64,140 ; < 1 % ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 1,027 ; ;
-; -- Routing optimization registers ; 337 ; ;
-; ; ; ;
-; Virtual pins ; 0 ; ;
-; I/O pins ; 81 / 457 ; 18 % ;
-; -- Clock pins ; 6 / 8 ; 75 % ;
-; -- Dedicated input pins ; 0 / 21 ; 0 % ;
-; ; ; ;
-; Hard processor system peripheral utilization ; ; ;
-; -- Boot from FPGA ; 0 / 1 ( 0 % ) ; ;
-; -- Clock resets ; 0 / 1 ( 0 % ) ; ;
-; -- Cross trigger ; 0 / 1 ( 0 % ) ; ;
-; -- S2F AXI ; 0 / 1 ( 0 % ) ; ;
-; -- F2S AXI ; 0 / 1 ( 0 % ) ; ;
-; -- AXI Lightweight ; 0 / 1 ( 0 % ) ; ;
-; -- SDRAM ; 0 / 1 ( 0 % ) ; ;
-; -- Interrupts ; 0 / 1 ( 0 % ) ; ;
-; -- JTAG ; 0 / 1 ( 0 % ) ; ;
-; -- Loan I/O ; 0 / 1 ( 0 % ) ; ;
-; -- MPU event standby ; 0 / 1 ( 0 % ) ; ;
-; -- MPU general purpose ; 0 / 1 ( 0 % ) ; ;
-; -- STM event ; 0 / 1 ( 0 % ) ; ;
-; -- TPIU trace ; 0 / 1 ( 0 % ) ; ;
-; -- DMA ; 0 / 1 ( 0 % ) ; ;
-; -- CAN ; 0 / 2 ( 0 % ) ; ;
-; -- EMAC ; 0 / 2 ( 0 % ) ; ;
-; -- I2C ; 0 / 4 ( 0 % ) ; ;
-; -- NAND Flash ; 0 / 1 ( 0 % ) ; ;
-; -- QSPI ; 0 / 1 ( 0 % ) ; ;
-; -- SDMMC ; 0 / 1 ( 0 % ) ; ;
-; -- SPI Master ; 0 / 2 ( 0 % ) ; ;
-; -- SPI Slave ; 0 / 2 ( 0 % ) ; ;
-; -- UART ; 0 / 2 ( 0 % ) ; ;
-; -- USB ; 0 / 2 ( 0 % ) ; ;
-; ; ; ;
-; M10K blocks ; 316 / 397 ; 80 % ;
-; Total MLAB memory bits ; 0 ; ;
-; Total block memory bits ; 2,588,672 / 4,065,280 ; 64 % ;
-; Total block memory implementation bits ; 3,235,840 / 4,065,280 ; 80 % ;
-; ; ; ;
-; Total DSP Blocks ; 0 / 87 ; 0 % ;
-; ; ; ;
-; Fractional PLLs ; 0 / 6 ; 0 % ;
-; Global signals ; 2 ; ;
-; -- Global clocks ; 2 / 16 ; 13 % ;
-; -- Quadrant clocks ; 0 / 66 ; 0 % ;
-; -- Horizontal periphery clocks ; 0 / 18 ; 0 % ;
-; SERDES Transmitters ; 0 / 100 ; 0 % ;
-; SERDES Receivers ; 0 / 100 ; 0 % ;
-; JTAGs ; 0 / 1 ; 0 % ;
-; ASMI blocks ; 0 / 1 ; 0 % ;
-; CRC blocks ; 0 / 1 ; 0 % ;
-; Remote update blocks ; 0 / 1 ; 0 % ;
-; Oscillator blocks ; 0 / 1 ; 0 % ;
-; Impedance control blocks ; 0 / 4 ; 0 % ;
-; Hard Memory Controllers ; 0 / 2 ; 0 % ;
-; Average interconnect usage (total/H/V) ; 6.2% / 6.1% / 6.7% ; ;
-; Peak interconnect usage (total/H/V) ; 48.7% / 47.5% / 52.8% ; ;
-; Maximum fan-out ; 1980 ; ;
-; Highest non-global fan-out ; 614 ; ;
-; Total fan-out ; 30298 ; ;
-; Average fan-out ; 5.63 ; ;
-+-------------------------------------------------------------+-----------------------+-------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Fitter Partition Statistics ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Statistic ; Top ; hard_block:auto_generated_inst ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-; Logic utilization (ALMs needed / total ALMs on device) ; 2241 / 32070 ( 7 % ) ; 0 / 32070 ( 0 % ) ;
-; ALMs needed [=A-B+C] ; 2241 ; 0 ;
-; [A] ALMs used in final placement [=a+b+c+d] ; 2512 / 32070 ( 8 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] ALMs used for LUT logic and registers ; 215 ; 0 ;
-; [b] ALMs used for LUT logic ; 1998 ; 0 ;
-; [c] ALMs used for registers ; 299 ; 0 ;
-; [d] ALMs used for memory (up to half of total ALMs) ; 0 ; 0 ;
-; [B] Estimate of ALMs recoverable by dense packing ; 315 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [C] Estimate of ALMs unavailable [=a+b+c+d] ; 44 / 32070 ( < 1 % ) ; 0 / 32070 ( 0 % ) ;
-; [a] Due to location constrained logic ; 0 ; 0 ;
-; [b] Due to LAB-wide signal conflicts ; 0 ; 0 ;
-; [c] Due to LAB input limits ; 44 ; 0 ;
-; [d] Due to virtual I/Os ; 0 ; 0 ;
-; ; ; ;
-; Difficulty packing design ; Low ; Low ;
-; ; ; ;
-; Total LABs: partially or completely used ; 316 / 3207 ( 10 % ) ; 0 / 3207 ( 0 % ) ;
-; -- Logic LABs ; 316 ; 0 ;
-; -- Memory LABs (up to half of total LABs) ; 0 ; 0 ;
-; ; ; ;
-; Combinational ALUT usage for logic ; 3449 ; 0 ;
-; -- 7 input functions ; 30 ; 0 ;
-; -- 6 input functions ; 1157 ; 0 ;
-; -- 5 input functions ; 730 ; 0 ;
-; -- 4 input functions ; 772 ; 0 ;
-; -- <=3 input functions ; 760 ; 0 ;
-; Combinational ALUT usage for route-throughs ; 93 ; 0 ;
-; Memory ALUT usage ; 0 ; 0 ;
-; -- 64-address deep ; 0 ; 0 ;
-; -- 32-address deep ; 0 ; 0 ;
-; ; ; ;
-; Dedicated logic registers ; 0 ; 0 ;
-; -- By type: ; ; ;
-; -- Primary logic registers ; 1027 / 64140 ( 2 % ) ; 0 / 64140 ( 0 % ) ;
-; -- Secondary logic registers ; 337 / 64140 ( < 1 % ) ; 0 / 64140 ( 0 % ) ;
-; -- By function: ; ; ;
-; -- Design implementation registers ; 1027 ; 0 ;
-; -- Routing optimization registers ; 337 ; 0 ;
-; ; ; ;
-; ; ; ;
-; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 81 ; 0 ;
-; I/O registers ; 0 ; 0 ;
-; Total block memory bits ; 2588672 ; 0 ;
-; Total block memory implementation bits ; 3235840 ; 0 ;
-; M10K block ; 316 / 397 ( 79 % ) ; 0 / 397 ( 0 % ) ;
-; Clock enable block ; 2 / 116 ( 1 % ) ; 0 / 116 ( 0 % ) ;
-; ; ; ;
-; Connections ; ; ;
-; -- Input Connections ; 0 ; 0 ;
-; -- Registered Input Connections ; 0 ; 0 ;
-; -- Output Connections ; 0 ; 0 ;
-; -- Registered Output Connections ; 0 ; 0 ;
-; ; ; ;
-; Internal Connections ; ; ;
-; -- Total Connections ; 35810 ; 0 ;
-; -- Registered Connections ; 11003 ; 0 ;
-; ; ; ;
-; External Connections ; ; ;
-; -- Top ; 0 ; 0 ;
-; -- hard_block:auto_generated_inst ; 0 ; 0 ;
-; ; ; ;
-; Partition Interface ; ; ;
-; -- Input Ports ; 15 ; 0 ;
-; -- Output Ports ; 66 ; 0 ;
-; -- Bidir Ports ; 0 ; 0 ;
-; ; ; ;
-; Registered Ports ; ; ;
-; -- Registered Input Ports ; 0 ; 0 ;
-; -- Registered Output Ports ; 0 ; 0 ;
-; ; ; ;
-; Port Connectivity ; ; ;
-; -- Input Ports driven by GND ; 0 ; 0 ;
-; -- Output Ports driven by GND ; 0 ; 0 ;
-; -- Input Ports driven by VCC ; 0 ; 0 ;
-; -- Output Ports driven by VCC ; 0 ; 0 ;
-; -- Input Ports with no Source ; 0 ; 0 ;
-; -- Output Ports with no Source ; 0 ; 0 ;
-; -- Input Ports with no Fanout ; 0 ; 0 ;
-; -- Output Ports with no Fanout ; 0 ; 0 ;
-+-------------------------------------------------------------+-----------------------+--------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Input Pins ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Termination Control Block ; Location assigned by ; Slew Rate ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-; CLOCK_50 ; AB27 ; 5B ; 89 ; 23 ; 20 ; 1980 ; 0 ; yes ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; KEY[0] ; AE17 ; 4A ; 50 ; 0 ; 40 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; KEY[1] ; AF16 ; 4A ; 52 ; 0 ; 51 ; 3 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; KEY[2] ; Y27 ; 5B ; 89 ; 25 ; 20 ; 1321 ; 0 ; yes ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; KEY[3] ; AH28 ; 5A ; 89 ; 4 ; 94 ; 0 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[0] ; AA14 ; 3B ; 36 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[1] ; AK7 ; 3B ; 28 ; 0 ; 34 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[2] ; AJ2 ; 3A ; 14 ; 0 ; 17 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[3] ; AG10 ; 3B ; 18 ; 0 ; 74 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[4] ; AJ10 ; 3B ; 34 ; 0 ; 91 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[5] ; AH4 ; 3A ; 6 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[6] ; AE13 ; 3B ; 22 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[7] ; AC14 ; 3B ; 28 ; 0 ; 17 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[8] ; AK4 ; 3B ; 22 ; 0 ; 51 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-; SW[9] ; AA13 ; 3B ; 20 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; Off ; 2.5 V ; Off ; -- ; Fitter ; no ;
-+----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+-----------------+----------+--------------+--------------+-------------+---------------------------+----------------------+-----------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Output Buffer Delay ; Output Buffer Delay Control ; Location assigned by ; Output Enable Source ; Output Enable Group ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-; HEX0[0] ; AE27 ; 5A ; 89 ; 11 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX0[1] ; AD20 ; 4A ; 82 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX0[2] ; AH8 ; 3B ; 32 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX0[3] ; AJ22 ; 4A ; 70 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX0[4] ; AH23 ; 4A ; 70 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX0[5] ; D4 ; 8A ; 10 ; 81 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX0[6] ; AB17 ; 4A ; 56 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX1[0] ; AF18 ; 4A ; 50 ; 0 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX1[1] ; W20 ; 5A ; 89 ; 6 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX1[2] ; AD27 ; 5A ; 89 ; 8 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX1[3] ; AH19 ; 4A ; 58 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX1[4] ; AF23 ; 4A ; 74 ; 0 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX1[5] ; E2 ; 8A ; 8 ; 81 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX1[6] ; AH30 ; 5A ; 89 ; 16 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX2[0] ; F14 ; 8A ; 36 ; 81 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX2[1] ; Y19 ; 4A ; 84 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX2[2] ; Y23 ; 5A ; 89 ; 13 ; 3 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX2[3] ; AF20 ; 4A ; 70 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX2[4] ; D10 ; 8A ; 34 ; 81 ; 57 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX2[5] ; K12 ; 8A ; 12 ; 81 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX2[6] ; A8 ; 8A ; 34 ; 81 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX3[0] ; AJ5 ; 3B ; 24 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX3[1] ; W19 ; 4A ; 80 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX3[2] ; Y17 ; 4A ; 68 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX3[3] ; AK12 ; 3B ; 36 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX3[4] ; AH10 ; 3B ; 34 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX3[5] ; AH15 ; 3B ; 38 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; HEX3[6] ; J14 ; 8A ; 32 ; 81 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[0] ; AC30 ; 5B ; 89 ; 25 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[1] ; AC27 ; 5A ; 89 ; 16 ; 20 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[2] ; E6 ; 8A ; 4 ; 81 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[3] ; AG8 ; 3A ; 8 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[4] ; AB25 ; 5A ; 89 ; 11 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[5] ; AH25 ; 4A ; 78 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[6] ; H12 ; 8A ; 20 ; 81 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[7] ; AD29 ; 5B ; 89 ; 23 ; 54 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[8] ; B1 ; 8A ; 16 ; 81 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; LEDR[9] ; G8 ; 8A ; 24 ; 81 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_BLANK_N ; AE22 ; 4A ; 78 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[0] ; AE26 ; 5A ; 89 ; 8 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[1] ; AE16 ; 4A ; 52 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[2] ; D9 ; 8A ; 30 ; 81 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[3] ; AE9 ; 3A ; 2 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[4] ; AG28 ; 5A ; 89 ; 13 ; 37 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[5] ; F10 ; 8A ; 6 ; 81 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[6] ; AG2 ; 3A ; 16 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_B[7] ; AG17 ; 4A ; 50 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_CLK ; AK22 ; 4A ; 68 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[0] ; B7 ; 8A ; 32 ; 81 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[1] ; Y16 ; 3B ; 40 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[2] ; C4 ; 8A ; 20 ; 81 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[3] ; AC25 ; 5A ; 89 ; 4 ; 60 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[4] ; AK29 ; 4A ; 82 ; 0 ; 91 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[5] ; AF5 ; 3A ; 8 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[6] ; G12 ; 8A ; 10 ; 81 ; 40 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_G[7] ; AE7 ; 3A ; 6 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_HS ; AD17 ; 4A ; 64 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[0] ; AK21 ; 4A ; 68 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[1] ; AK26 ; 4A ; 76 ; 0 ; 51 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[2] ; AC12 ; 3A ; 16 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[3] ; AC20 ; 4A ; 76 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[4] ; AD12 ; 3A ; 16 ; 0 ; 17 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[5] ; AJ24 ; 4A ; 74 ; 0 ; 74 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[6] ; AC18 ; 4A ; 64 ; 0 ; 0 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_R[7] ; AJ26 ; 4A ; 76 ; 0 ; 34 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-; VGA_VS ; AG27 ; 5A ; 89 ; 4 ; 77 ; no ; no ; 1 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; 0 ; Off ; Fitter ; - ; - ;
-+-------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+---------------------+-----------------------------+----------------------+----------------------+---------------------+
-
-
-+----------------------------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+------------------+---------------+--------------+---------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; VCCPD Voltage ;
-+----------+------------------+---------------+--------------+---------------+
-; B2L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; B1L ; 0 / 0 ( -- ) ; -- ; -- ; -- ;
-; 3A ; 9 / 32 ( 28 % ) ; 2.5V ; -- ; 2.5V ;
-; 3B ; 14 / 48 ( 29 % ) ; 2.5V ; -- ; 2.5V ;
-; 4A ; 26 / 80 ( 33 % ) ; 2.5V ; -- ; 2.5V ;
-; 5A ; 12 / 32 ( 38 % ) ; 2.5V ; -- ; 2.5V ;
-; 5B ; 4 / 16 ( 25 % ) ; 2.5V ; -- ; 2.5V ;
-; 6B ; 0 / 44 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 6A ; 0 / 56 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7A ; 0 / 19 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7B ; 0 / 22 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7C ; 0 / 12 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 7D ; 0 / 14 ( 0 % ) ; 2.5V ; -- ; 2.5V ;
-; 8A ; 16 / 80 ( 20 % ) ; 2.5V ; -- ; 2.5V ;
-+----------+------------------+---------------+--------------+---------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; All Package Pins ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-; A2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A3 ; 493 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A4 ; 491 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A5 ; 489 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A6 ; 487 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A7 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; A8 ; 473 ; 8A ; HEX2[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; A9 ; 471 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A10 ; 465 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A11 ; 463 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A13 ; 461 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A14 ; 455 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A15 ; 447 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A16 ; 439 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A18 ; 425 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A19 ; 423 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A20 ; 415 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A21 ; 411 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A23 ; 395 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A24 ; 391 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A25 ; 389 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; A26 ; 382 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; A27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; A28 ; 380 ; 7A ; ^HPS_TRST ; ; ; ; -- ; ; -- ; -- ;
-; A29 ; 378 ; 7A ; ^HPS_TMS ; ; ; ; -- ; ; -- ; -- ;
-; AA1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; AA6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA7 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AA8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA12 ; 74 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA13 ; 90 ; 3B ; SW[9] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AA14 ; 122 ; 3B ; SW[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AA15 ; 120 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA16 ; 146 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA17 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA18 ; 168 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA19 ; 176 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA20 ; 200 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA21 ; 210 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AA22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AA23 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AA24 ; 228 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA25 ; 224 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA26 ; 252 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA27 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AA28 ; 251 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AA29 ; ; 5B ; VREFB5BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AA30 ; 250 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AB5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB8 ; 43 ; 3A ; ^nCSO, DATA4 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AB9 ; 42 ; 3A ; #TDO ; output ; ; ; -- ; ; -- ; -- ;
-; AB10 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; AB11 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB12 ; 72 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB13 ; 88 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB14 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB15 ; 106 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB17 ; 144 ; 4A ; HEX0[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AB18 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB20 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB21 ; 208 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AB22 ; 225 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB23 ; 227 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB24 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AB25 ; 230 ; 5A ; LEDR[4] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AB26 ; 226 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB27 ; 254 ; 5B ; CLOCK_50 ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AB28 ; 249 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AB29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AB30 ; 248 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC5 ; 46 ; 3A ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
-; AC6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC7 ; 45 ; 3A ; ^AS_DATA3, DATA3 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AC8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC9 ; 58 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC10 ; ; 3A ; VCCPD3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC11 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC12 ; 82 ; 3A ; VGA_R[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AC13 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC14 ; 104 ; 3B ; SW[7] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AC15 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC17 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC18 ; 162 ; 4A ; VGA_R[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AC19 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC20 ; 186 ; 4A ; VGA_R[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AC21 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AC22 ; 207 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC23 ; 205 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AC24 ; ; 5A ; VREFB5AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AC25 ; 215 ; 5A ; VGA_G[3] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AC26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AC27 ; 242 ; 5A ; LEDR[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AC28 ; 245 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC29 ; 247 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AC30 ; 259 ; 5B ; LEDR[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AD1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD6 ; ; 3A ; VREFB3AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AD7 ; 62 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD8 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD9 ; 55 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD10 ; 56 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD11 ; 54 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD12 ; 80 ; 3A ; VGA_R[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AD13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD14 ; 98 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; AD16 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD17 ; 160 ; 4A ; VGA_HS ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AD18 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD19 ; 184 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD20 ; 199 ; 4A ; HEX0[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AD21 ; 197 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD22 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AD24 ; 211 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AD25 ; 213 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD26 ; 240 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AD27 ; 222 ; 5A ; HEX1[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AD28 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AD29 ; 255 ; 5B ; LEDR[7] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AD30 ; 257 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE5 ; 49 ; 3A ; ^AS_DATA1, DATA1 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE6 ; 51 ; 3A ; ^AS_DATA0, ASDO, DATA0 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE7 ; 60 ; 3A ; VGA_G[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AE8 ; 47 ; 3A ; ^AS_DATA2, DATA2 ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; AE9 ; 53 ; 3A ; VGA_B[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AE10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE11 ; 59 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE12 ; 52 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE13 ; 95 ; 3B ; SW[6] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AE14 ; 96 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE15 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AE16 ; 139 ; 4A ; VGA_B[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AE17 ; 135 ; 4A ; KEY[0] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AE18 ; 167 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE19 ; 165 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AE21 ; ; 3B, 4A ; VCCPD3B4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AE22 ; 191 ; 4A ; VGA_BLANK_N ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AE23 ; 189 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE24 ; 209 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AE25 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AE26 ; 220 ; 5A ; VGA_B[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AE27 ; 229 ; 5A ; HEX0[0] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AE28 ; 231 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE29 ; 253 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AE30 ; ; 5B ; VCCIO5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AF1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF4 ; 66 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF5 ; 64 ; 3A ; VGA_G[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AF6 ; 75 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF7 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AF8 ; 70 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF9 ; 67 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF10 ; 57 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF11 ; 87 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF13 ; 93 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF14 ; 114 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF15 ; 112 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF16 ; 137 ; 4A ; KEY[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AF17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF18 ; 133 ; 4A ; HEX1[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AF19 ; 159 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF20 ; 175 ; 4A ; HEX2[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AF21 ; 173 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF22 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AF23 ; 183 ; 4A ; HEX1[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AF24 ; 181 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF25 ; 206 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF26 ; 204 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AF27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AF28 ; 235 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF29 ; 237 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AF30 ; 239 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AG1 ; 71 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG2 ; 83 ; 3A ; VGA_B[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AG3 ; 63 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG4 ; ; 3A ; VCCIO3A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG5 ; 78 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG6 ; 73 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG7 ; 68 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG8 ; 65 ; 3A ; LEDR[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AG9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG10 ; 86 ; 3B ; SW[3] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AG11 ; 85 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG12 ; 103 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG13 ; 101 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG15 ; 127 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG16 ; 134 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG17 ; 132 ; 4A ; VGA_B[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AG18 ; 150 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG19 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG20 ; 157 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG21 ; 143 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG22 ; 166 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG23 ; 163 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AG25 ; 190 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG26 ; 203 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AG27 ; 212 ; 5A ; VGA_VS ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AG28 ; 233 ; 5A ; VGA_B[4] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AG29 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AG30 ; 243 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AH1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH2 ; 69 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH3 ; 81 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH4 ; 61 ; 3A ; SW[5] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AH5 ; 76 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH7 ; 115 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH8 ; 113 ; 3B ; HEX0[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AH9 ; 84 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH10 ; 118 ; 3B ; HEX3[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AH11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH12 ; 126 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH13 ; 111 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH14 ; 109 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH15 ; 125 ; 3B ; HEX3[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AH16 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH17 ; 147 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH18 ; 145 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH19 ; 148 ; 4A ; HEX1[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AH20 ; 141 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AH22 ; 164 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH23 ; 174 ; 4A ; HEX0[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AH24 ; 161 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH25 ; 188 ; 4A ; LEDR[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AH26 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AH27 ; 201 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AH28 ; 214 ; 5A ; KEY[3] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AH29 ; 218 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AH30 ; 241 ; 5A ; HEX1[6] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; AJ1 ; 79 ; 3A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ2 ; 77 ; 3A ; SW[2] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AJ3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ4 ; 94 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ5 ; 99 ; 3B ; HEX3[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AJ6 ; 102 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ7 ; 100 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ8 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AJ9 ; 110 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ10 ; 116 ; 3B ; SW[4] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AJ11 ; 119 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ12 ; 124 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ13 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AJ14 ; 131 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ15 ; ; 3B ; VREFB3BN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AJ16 ; 142 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ17 ; 151 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ19 ; 155 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ20 ; 158 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ21 ; 156 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ22 ; 172 ; 4A ; HEX0[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AJ23 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AJ24 ; 182 ; 4A ; VGA_R[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AJ25 ; 180 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ26 ; 187 ; 4A ; VGA_R[7] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AJ27 ; 195 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AJ28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AJ29 ; 216 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; AJ30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK2 ; 91 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK3 ; 89 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK4 ; 92 ; 3B ; SW[8] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AK5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK6 ; 97 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK7 ; 107 ; 3B ; SW[1] ; input ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AK8 ; 105 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK9 ; 108 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK10 ; ; 3B ; VCCIO3B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AK11 ; 117 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK12 ; 123 ; 3B ; HEX3[3] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AK13 ; 121 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK14 ; 129 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK16 ; 140 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK17 ; ; 4A ; VREFB4AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; AK18 ; 149 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK19 ; 153 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK20 ; ; 4A ; VCCIO4A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; AK21 ; 171 ; 4A ; VGA_R[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AK22 ; 169 ; 4A ; VGA_CLK ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AK23 ; 179 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK24 ; 177 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; AK26 ; 185 ; 4A ; VGA_R[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; AK27 ; 193 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK28 ; 198 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; AK29 ; 196 ; 4A ; VGA_G[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B1 ; 509 ; 8A ; LEDR[8] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B2 ; 507 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B3 ; 513 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B4 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; B5 ; 512 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B6 ; 510 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B7 ; 477 ; 8A ; VGA_G[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; B8 ; 481 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B10 ; ; 8A ; VREFB8AN0 ; power ; ; ; -- ; ; -- ; -- ;
-; B11 ; 469 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B12 ; 464 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B13 ; 459 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B15 ; 451 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B16 ; 441 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B17 ; 431 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B18 ; 418 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B20 ; 417 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B21 ; 413 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B22 ; 399 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B23 ; 397 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B25 ; 387 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B26 ; 386 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; B27 ; 381 ; 7A ; ^HPS_TDI ; ; ; ; -- ; ; -- ; -- ;
-; B28 ; 376 ; 7A ; ^HPS_TDO ; ; ; ; -- ; ; -- ; -- ;
-; B29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; B30 ; 365 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C2 ; 517 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C3 ; 511 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C4 ; 501 ; 8A ; VGA_G[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; C5 ; 497 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C7 ; 475 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C8 ; 479 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C9 ; 485 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C10 ; 483 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C11 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; C12 ; 467 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C13 ; 462 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C14 ; 448 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C15 ; 453 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C17 ; 433 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C18 ; 435 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C19 ; 427 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C20 ; 421 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C22 ; 396 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C23 ; 401 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C24 ; 393 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C25 ; 388 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; C26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; C27 ; 374 ; 7A ; ^HPS_nRST ; ; ; ; -- ; ; -- ; -- ;
-; C28 ; 369 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C29 ; 367 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; C30 ; 363 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D1 ; 529 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D2 ; 515 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D4 ; 521 ; 8A ; HEX0[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D5 ; 499 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D6 ; 495 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D7 ; 505 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D8 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D9 ; 480 ; 8A ; VGA_B[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D10 ; 472 ; 8A ; HEX2[4] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; D11 ; 470 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D12 ; 496 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D14 ; 446 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D15 ; 449 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D16 ; 445 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D17 ; 440 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D18 ; ; 7C ; VCCIO7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D19 ; 426 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D20 ; 420 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D21 ; 419 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D22 ; 402 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D23 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; D24 ; 404 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; D25 ; 384 ; 7A ; ^HPS_CLK1 ; ; ; ; -- ; ; -- ; -- ;
-; D26 ; 373 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; D27 ; 371 ; 6A ; HPS_RZQ_0 ; ; ; ; -- ; ; no ; On ;
-; D28 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; D29 ; 361 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; D30 ; 359 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E1 ; 527 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E2 ; 525 ; 8A ; HEX1[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; E3 ; 523 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E4 ; 519 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E5 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E6 ; 533 ; 8A ; LEDR[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; E7 ; 531 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E8 ; 503 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E9 ; 478 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E11 ; 504 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E12 ; 494 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E13 ; 488 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E14 ; 454 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E15 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E16 ; 443 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E17 ; 438 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E18 ; 437 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E19 ; 424 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E20 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; E21 ; 412 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E22 ; ; 7A, 7B, 7C, 7D ; VREFB7A7B7C7DN0_HPS ; power ; ; ; -- ; ; -- ; -- ;
-; E23 ; 394 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E24 ; 403 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; E25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; E26 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; E27 ; 357 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E28 ; 351 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E29 ; 353 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; E30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F1 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; F2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F3 ; 539 ; 9A ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
-; F4 ; 541 ; 9A ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
-; F5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F6 ; 537 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F8 ; 536 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F9 ; 534 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F10 ; 528 ; 8A ; VGA_B[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; F11 ; 502 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F12 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F13 ; 486 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F14 ; 468 ; 8A ; HEX2[0] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; F15 ; 466 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F16 ; 442 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F18 ; 430 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F19 ; 410 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F20 ; 407 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F21 ; 409 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; F22 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; F23 ; 375 ; 7A ; ^HPS_nPOR ; ; ; ; -- ; ; -- ; -- ;
-; F24 ; 383 ; 7A ; ^HPS_PORSEL ; ; ; ; -- ; ; -- ; -- ;
-; F25 ; 385 ; 7A ; ^HPS_CLK2 ; ; ; ; -- ; ; -- ; -- ;
-; F26 ; 341 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; F28 ; 345 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F29 ; 349 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; F30 ; 347 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G1 ; ; ; GND ; ; ; ; -- ; ; -- ; -- ;
-; G2 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; G3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G5 ; 542 ; 9A ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
-; G6 ; 543 ; 9A ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
-; G7 ; 535 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G8 ; 492 ; 8A ; LEDR[9] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; G9 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G10 ; 526 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G11 ; 520 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G12 ; 518 ; 8A ; VGA_G[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; G13 ; 484 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G14 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G15 ; 460 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G16 ; 444 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G17 ; 436 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G18 ; 432 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G19 ; ; 7B ; VCCIO7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G20 ; 416 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G21 ; 392 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G22 ; 400 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; G23 ; 377 ; 7A ; ^VCCRSTCLK_HPS ; ; ; ; -- ; ; -- ; -- ;
-; G24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; G25 ; 370 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G26 ; 362 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G27 ; 339 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; G28 ; 335 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; G29 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; G30 ; 343 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; H5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H6 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H7 ; 508 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H8 ; 490 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H9 ; ; -- ; VCCBAT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
-; H10 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; H12 ; 500 ; 8A ; LEDR[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; H13 ; 498 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H14 ; 482 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H15 ; 458 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H16 ; ; 7D ; VCCIO7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H17 ; 434 ; 7C ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H18 ; 422 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H19 ; 406 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H20 ; 398 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H21 ; ; 7A ; VCCIO7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H22 ; 379 ; 7A ; ^HPS_TCK ; ; ; ; -- ; ; -- ; -- ;
-; H23 ; 390 ; 7A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; H24 ; 364 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H25 ; 368 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H26 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; H27 ; 360 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H28 ; 333 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H29 ; 331 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; H30 ; 337 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J5 ; 545 ; 9A ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
-; J6 ; 547 ; 9A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J7 ; 506 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J9 ; 532 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J10 ; 530 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J11 ; ; -- ; VCCPGM ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J12 ; 516 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J13 ; ; 8A ; VCCIO8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J14 ; 476 ; 8A ; HEX3[6] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; J15 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; J16 ; ; -- ; VCC_AUX ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J17 ; ; 7C ; VCCPD7C_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J19 ; 408 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; J20 ; ; -- ; VCCRSTCLK_HPS ; power ; ; 1.8V/2.5V/3.0V/3.3V ; -- ; ; -- ; -- ;
-; J21 ; ; -- ; VCC_AUX_SHARED ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; J22 ; 372 ; 7A ; ^GND ; ; ; ; -- ; ; -- ; -- ;
-; J23 ; 354 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J24 ; 352 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J25 ; 344 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J26 ; 323 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J27 ; 346 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; J29 ; 327 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; J30 ; 329 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; K5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K6 ; 540 ; 9A ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
-; K7 ; 522 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K8 ; 524 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K9 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K11 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K12 ; 514 ; 8A ; HEX2[5] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; K13 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K14 ; 474 ; 8A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K16 ; ; 7D ; VCCPD7D_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K17 ; 414 ; 7B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; K18 ; ; 7B ; VCCPD7B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K19 ; ; 7A ; VCCPD7A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K21 ; 366 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K22 ; 336 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K23 ; 338 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; K25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; K26 ; 322 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K27 ; 319 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K28 ; 325 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K29 ; 321 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; K30 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L7 ; 544 ; 9A ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
-; L8 ; 538 ; 9A ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
-; L9 ; 546 ; 9A ; ^MSEL4 ; ; ; ; -- ; ; -- ; -- ;
-; L10 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L12 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L14 ; ; 8A ; VCCPD8A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; L21 ; ; -- ; VCCPLL_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; L23 ; 350 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L24 ; 328 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L25 ; 330 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L26 ; 320 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L27 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; L28 ; 313 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L29 ; 315 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; L30 ; 317 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; M5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; M16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M17 ; 450 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; M18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M19 ; 334 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M22 ; 308 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M23 ; 348 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M24 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; M25 ; 324 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M26 ; 314 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M27 ; 312 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M28 ; 309 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; M29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; M30 ; 311 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N16 ; 452 ; 7D ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; N17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N18 ; 332 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N20 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; N21 ; ; 6A ; VCCIO6A_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N22 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; N23 ; 310 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N24 ; 318 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N25 ; 316 ; 6A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N26 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; N27 ; 297 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N28 ; 303 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N29 ; 305 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; N30 ; 307 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P15 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; P20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; P21 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P22 ; 294 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P23 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P24 ; 290 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P25 ; 288 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P26 ; 298 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P27 ; 296 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P28 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; P29 ; 299 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; P30 ; 301 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R7 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; R17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; R18 ; 302 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R19 ; 300 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R20 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R21 ; 286 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R22 ; 284 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R23 ; ; 6A, 6B ; VCCPD6A6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R24 ; 272 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R25 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; R26 ; 280 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R27 ; 282 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R28 ; 293 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R29 ; 295 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; R30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; T5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T17 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T19 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T21 ; 278 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T22 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; T23 ; 270 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T24 ; 268 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T25 ; 266 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T26 ; 304 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T27 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; T28 ; 287 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T29 ; 289 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; T30 ; 291 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U7 ; 50 ; 3A ; ^DCLK ; ; ; ; Weak Pull Up ; ; -- ; On ;
-; U8 ; 48 ; 3A ; #TDI ; input ; ; ; -- ; ; -- ; -- ;
-; U9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U16 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U18 ; ; -- ; VCC_HPS ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U19 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U20 ; 276 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U21 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; U22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U23 ; ; 5B ; VCCPD5B ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; U24 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U25 ; 264 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U26 ; 306 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U27 ; 273 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U28 ; 285 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; U29 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; U30 ; 283 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
-; V1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; V5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V6 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V8 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V9 ; 44 ; 3A ; #TMS ; input ; ; ; -- ; ; -- ; -- ;
-; V10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V15 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; V16 ; 138 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V17 ; 154 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V18 ; 194 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; V19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V20 ; 292 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; V22 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V23 ; 236 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V24 ; ; 5A ; VCCPD5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V25 ; 246 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V26 ; ; 6B ; VCCIO6B_HPS ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; V27 ; 265 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V28 ; 271 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V29 ; 275 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; V30 ; 281 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W5 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W10 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W12 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W14 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; W15 ; 130 ; 3B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W16 ; 136 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W17 ; 152 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; W18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W19 ; 192 ; 4A ; HEX3[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; W20 ; 217 ; 5A ; HEX1[1] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; W21 ; 221 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W22 ; 223 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W23 ; ; 5A ; VCCIO5A ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; W24 ; 238 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W25 ; 244 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W26 ; 274 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W27 ; 261 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W28 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; W29 ; 279 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; W30 ; 277 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y3 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y4 ; ; ; DNU ; ; ; ; -- ; ; -- ; -- ;
-; Y5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y6 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y9 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y11 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y13 ; ; -- ; VCC ; power ; ; 1.1V ; -- ; ; -- ; -- ;
-; Y14 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y16 ; 128 ; 3B ; VGA_G[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; Y17 ; 170 ; 4A ; HEX3[2] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; Y18 ; 178 ; 4A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
-; Y19 ; 202 ; 4A ; HEX2[1] ; output ; 2.5 V ; ; Column I/O ; N ; no ; Off ;
-; Y20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y21 ; 219 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y22 ; ; -- ; VCCA_FPLL ; power ; ; 2.5V ; -- ; ; -- ; -- ;
-; Y23 ; 232 ; 5A ; HEX2[2] ; output ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; Y24 ; 234 ; 5A ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y25 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; Y26 ; 256 ; 5B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y27 ; 258 ; 5B ; KEY[2] ; input ; 2.5 V ; ; Row I/O ; N ; no ; Off ;
-; Y28 ; 269 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y29 ; 263 ; 6B ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
-; Y30 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-+----------+------------+----------------+---------------------------------+--------+--------------+---------------------+--------------+-----------------+----------+--------------+
-Note: Pin directions (input, output or bidir) are based on device operating in user mode.
-
-
-+---------------------------------------------+
-; I/O Assignment Warnings ;
-+-------------+-------------------------------+
-; Pin Name ; Reason ;
-+-------------+-------------------------------+
-; KEY[3] ; Incomplete set of assignments ;
-; LEDR[0] ; Incomplete set of assignments ;
-; LEDR[1] ; Incomplete set of assignments ;
-; LEDR[2] ; Incomplete set of assignments ;
-; LEDR[3] ; Incomplete set of assignments ;
-; LEDR[4] ; Incomplete set of assignments ;
-; LEDR[5] ; Incomplete set of assignments ;
-; LEDR[6] ; Incomplete set of assignments ;
-; LEDR[7] ; Incomplete set of assignments ;
-; LEDR[8] ; Incomplete set of assignments ;
-; LEDR[9] ; Incomplete set of assignments ;
-; HEX0[0] ; Incomplete set of assignments ;
-; HEX0[1] ; Incomplete set of assignments ;
-; HEX0[2] ; Incomplete set of assignments ;
-; HEX0[3] ; Incomplete set of assignments ;
-; HEX0[4] ; Incomplete set of assignments ;
-; HEX0[5] ; Incomplete set of assignments ;
-; HEX0[6] ; Incomplete set of assignments ;
-; HEX1[0] ; Incomplete set of assignments ;
-; HEX1[1] ; Incomplete set of assignments ;
-; HEX1[2] ; Incomplete set of assignments ;
-; HEX1[3] ; Incomplete set of assignments ;
-; HEX1[4] ; Incomplete set of assignments ;
-; HEX1[5] ; Incomplete set of assignments ;
-; HEX1[6] ; Incomplete set of assignments ;
-; HEX2[0] ; Incomplete set of assignments ;
-; HEX2[1] ; Incomplete set of assignments ;
-; HEX2[2] ; Incomplete set of assignments ;
-; HEX2[3] ; Incomplete set of assignments ;
-; HEX2[4] ; Incomplete set of assignments ;
-; HEX2[5] ; Incomplete set of assignments ;
-; HEX2[6] ; Incomplete set of assignments ;
-; HEX3[0] ; Incomplete set of assignments ;
-; HEX3[1] ; Incomplete set of assignments ;
-; HEX3[2] ; Incomplete set of assignments ;
-; HEX3[3] ; Incomplete set of assignments ;
-; HEX3[4] ; Incomplete set of assignments ;
-; HEX3[5] ; Incomplete set of assignments ;
-; HEX3[6] ; Incomplete set of assignments ;
-; VGA_R[0] ; Incomplete set of assignments ;
-; VGA_R[1] ; Incomplete set of assignments ;
-; VGA_R[2] ; Incomplete set of assignments ;
-; VGA_R[3] ; Incomplete set of assignments ;
-; VGA_R[4] ; Incomplete set of assignments ;
-; VGA_R[5] ; Incomplete set of assignments ;
-; VGA_R[6] ; Incomplete set of assignments ;
-; VGA_R[7] ; Incomplete set of assignments ;
-; VGA_G[0] ; Incomplete set of assignments ;
-; VGA_G[1] ; Incomplete set of assignments ;
-; VGA_G[2] ; Incomplete set of assignments ;
-; VGA_G[3] ; Incomplete set of assignments ;
-; VGA_G[4] ; Incomplete set of assignments ;
-; VGA_G[5] ; Incomplete set of assignments ;
-; VGA_G[6] ; Incomplete set of assignments ;
-; VGA_G[7] ; Incomplete set of assignments ;
-; VGA_B[0] ; Incomplete set of assignments ;
-; VGA_B[1] ; Incomplete set of assignments ;
-; VGA_B[2] ; Incomplete set of assignments ;
-; VGA_B[3] ; Incomplete set of assignments ;
-; VGA_B[4] ; Incomplete set of assignments ;
-; VGA_B[5] ; Incomplete set of assignments ;
-; VGA_B[6] ; Incomplete set of assignments ;
-; VGA_B[7] ; Incomplete set of assignments ;
-; VGA_HS ; Incomplete set of assignments ;
-; VGA_VS ; Incomplete set of assignments ;
-; VGA_CLK ; Incomplete set of assignments ;
-; VGA_BLANK_N ; Incomplete set of assignments ;
-; CLOCK_50 ; Incomplete set of assignments ;
-; KEY[2] ; Incomplete set of assignments ;
-; SW[7] ; Incomplete set of assignments ;
-; KEY[1] ; Incomplete set of assignments ;
-; KEY[0] ; Incomplete set of assignments ;
-; SW[2] ; Incomplete set of assignments ;
-; SW[9] ; Incomplete set of assignments ;
-; SW[1] ; Incomplete set of assignments ;
-; SW[4] ; Incomplete set of assignments ;
-; SW[3] ; Incomplete set of assignments ;
-; SW[5] ; Incomplete set of assignments ;
-; SW[8] ; Incomplete set of assignments ;
-; SW[0] ; Incomplete set of assignments ;
-; SW[6] ; Incomplete set of assignments ;
-; KEY[3] ; Missing location assignment ;
-; LEDR[0] ; Missing location assignment ;
-; LEDR[1] ; Missing location assignment ;
-; LEDR[2] ; Missing location assignment ;
-; LEDR[3] ; Missing location assignment ;
-; LEDR[4] ; Missing location assignment ;
-; LEDR[5] ; Missing location assignment ;
-; LEDR[6] ; Missing location assignment ;
-; LEDR[7] ; Missing location assignment ;
-; LEDR[8] ; Missing location assignment ;
-; LEDR[9] ; Missing location assignment ;
-; HEX0[0] ; Missing location assignment ;
-; HEX0[1] ; Missing location assignment ;
-; HEX0[2] ; Missing location assignment ;
-; HEX0[3] ; Missing location assignment ;
-; HEX0[4] ; Missing location assignment ;
-; HEX0[5] ; Missing location assignment ;
-; HEX0[6] ; Missing location assignment ;
-; HEX1[0] ; Missing location assignment ;
-; HEX1[1] ; Missing location assignment ;
-; HEX1[2] ; Missing location assignment ;
-; HEX1[3] ; Missing location assignment ;
-; HEX1[4] ; Missing location assignment ;
-; HEX1[5] ; Missing location assignment ;
-; HEX1[6] ; Missing location assignment ;
-; HEX2[0] ; Missing location assignment ;
-; HEX2[1] ; Missing location assignment ;
-; HEX2[2] ; Missing location assignment ;
-; HEX2[3] ; Missing location assignment ;
-; HEX2[4] ; Missing location assignment ;
-; HEX2[5] ; Missing location assignment ;
-; HEX2[6] ; Missing location assignment ;
-; HEX3[0] ; Missing location assignment ;
-; HEX3[1] ; Missing location assignment ;
-; HEX3[2] ; Missing location assignment ;
-; HEX3[3] ; Missing location assignment ;
-; HEX3[4] ; Missing location assignment ;
-; HEX3[5] ; Missing location assignment ;
-; HEX3[6] ; Missing location assignment ;
-; VGA_R[0] ; Missing location assignment ;
-; VGA_R[1] ; Missing location assignment ;
-; VGA_R[2] ; Missing location assignment ;
-; VGA_R[3] ; Missing location assignment ;
-; VGA_R[4] ; Missing location assignment ;
-; VGA_R[5] ; Missing location assignment ;
-; VGA_R[6] ; Missing location assignment ;
-; VGA_R[7] ; Missing location assignment ;
-; VGA_G[0] ; Missing location assignment ;
-; VGA_G[1] ; Missing location assignment ;
-; VGA_G[2] ; Missing location assignment ;
-; VGA_G[3] ; Missing location assignment ;
-; VGA_G[4] ; Missing location assignment ;
-; VGA_G[5] ; Missing location assignment ;
-; VGA_G[6] ; Missing location assignment ;
-; VGA_G[7] ; Missing location assignment ;
-; VGA_B[0] ; Missing location assignment ;
-; VGA_B[1] ; Missing location assignment ;
-; VGA_B[2] ; Missing location assignment ;
-; VGA_B[3] ; Missing location assignment ;
-; VGA_B[4] ; Missing location assignment ;
-; VGA_B[5] ; Missing location assignment ;
-; VGA_B[6] ; Missing location assignment ;
-; VGA_B[7] ; Missing location assignment ;
-; VGA_HS ; Missing location assignment ;
-; VGA_VS ; Missing location assignment ;
-; VGA_CLK ; Missing location assignment ;
-; VGA_BLANK_N ; Missing location assignment ;
-; CLOCK_50 ; Missing location assignment ;
-; KEY[2] ; Missing location assignment ;
-; SW[7] ; Missing location assignment ;
-; KEY[1] ; Missing location assignment ;
-; KEY[0] ; Missing location assignment ;
-; SW[2] ; Missing location assignment ;
-; SW[9] ; Missing location assignment ;
-; SW[1] ; Missing location assignment ;
-; SW[4] ; Missing location assignment ;
-; SW[3] ; Missing location assignment ;
-; SW[5] ; Missing location assignment ;
-; SW[8] ; Missing location assignment ;
-; SW[0] ; Missing location assignment ;
-; SW[6] ; Missing location assignment ;
-+-------------+-------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------+
-; Compilation Hierarchy Node ; ALMs needed [=A-B+C] ; [A] ALMs used in final placement ; [B] Estimate of ALMs recoverable by dense packing ; [C] Estimate of ALMs unavailable ; ALMs used for memory ; Combinational ALUTs ; Dedicated Logic Registers ; I/O Registers ; Block Memory Bits ; M10Ks ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------+
-; |de1_soc_wrapper ; 2241.0 (14.0) ; 2511.5 (15.0) ; 314.5 (1.0) ; 44.0 (0.0) ; 0.0 (0.0) ; 3449 (29) ; 1364 (28) ; 0 (0) ; 2588672 ; 316 ; 0 ; 81 ; 0 ; |de1_soc_wrapper ; de1_soc_wrapper ; work ;
-; |arm_soc:soc_inst| ; 2177.5 (0.0) ; 2447.5 (0.0) ; 312.5 (0.0) ; 42.5 (0.0) ; 0.0 (0.0) ; 3332 (0) ; 1287 (0) ; 0 (0) ; 2588672 ; 316 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst ; arm_soc ; work ;
-; |CORTEXM0DS:m0_1| ; 1903.8 (0.0) ; 2170.9 (0.0) ; 298.3 (0.0) ; 31.2 (0.0) ; 0.0 (0.0) ; 2968 (0) ; 1153 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1 ; CORTEXM0DS ; work ;
-; |cortexm0ds_logic:u_logic| ; 1903.8 (1903.8) ; 2170.9 (2170.9) ; 298.3 (298.3) ; 31.2 (31.2) ; 0.0 (0.0) ; 2968 (2968) ; 1153 (1153) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic ; cortexm0ds_logic ; work ;
-; |ahb_interconnect:interconnect_1| ; 41.9 (41.9) ; 44.0 (44.0) ; 3.2 (3.2) ; 1.0 (1.0) ; 0.0 (0.0) ; 75 (75) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1 ; ahb_interconnect ; work ;
-; |ahb_pixel_memory:pix1| ; 184.7 (41.4) ; 187.2 (46.6) ; 9.3 (7.8) ; 6.8 (2.5) ; 0.0 (0.0) ; 226 (34) ; 84 (78) ; 0 (0) ; 2457600 ; 300 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1 ; ahb_pixel_memory ; work ;
-; |altsyncram:memory_rtl_0| ; 143.4 (0.0) ; 140.6 (0.0) ; 1.5 (0.0) ; 4.3 (0.0) ; 0.0 (0.0) ; 192 (0) ; 6 (0) ; 0 (0) ; 2457600 ; 300 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0 ; altsyncram ; work ;
-; |altsyncram_40j1:auto_generated| ; 143.4 (1.8) ; 140.6 (1.8) ; 1.5 (0.0) ; 4.3 (0.0) ; 0.0 (0.0) ; 192 (0) ; 6 (6) ; 0 (0) ; 2457600 ; 300 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated ; altsyncram_40j1 ; work ;
-; |decode_3na:decode2| ; 21.4 (21.4) ; 21.8 (21.8) ; 0.3 (0.3) ; 0.0 (0.0) ; 0.0 (0.0) ; 44 (44) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2 ; decode_3na ; work ;
-; |decode_s2a:rden_decode_b| ; 23.2 (23.2) ; 23.8 (23.8) ; 0.8 (0.8) ; 0.2 (0.2) ; 0.0 (0.0) ; 46 (46) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b ; decode_s2a ; work ;
-; |mux_jhb:mux3| ; 96.9 (96.9) ; 93.2 (93.2) ; 0.3 (0.3) ; 4.1 (4.1) ; 0.0 (0.0) ; 102 (102) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|mux_jhb:mux3 ; mux_jhb ; work ;
-; |ahb_ram:ram_1| ; 33.7 (33.7) ; 32.5 (32.5) ; 1.7 (1.7) ; 2.9 (2.9) ; 0.0 (0.0) ; 52 (52) ; 19 (19) ; 0 (0) ; 131072 ; 16 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1 ; ahb_ram ; work ;
-; |altsyncram:memory_rtl_0| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 131072 ; 16 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0 ; altsyncram ; work ;
-; |altsyncram_nms1:auto_generated| ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0.0 (0.0) ; 0 (0) ; 0 (0) ; 0 (0) ; 131072 ; 16 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated ; altsyncram_nms1 ; work ;
-; |ahb_switches:switches_1| ; 13.4 (13.4) ; 12.9 (12.9) ; 0.1 (0.1) ; 0.5 (0.5) ; 0.0 (0.0) ; 11 (11) ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_switches:switches_1 ; ahb_switches ; work ;
-; |razzle:raz_inst| ; 49.5 (49.5) ; 49.0 (49.0) ; 1.0 (1.0) ; 1.5 (1.5) ; 0.0 (0.0) ; 88 (88) ; 49 (49) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|razzle:raz_inst ; razzle ; work ;
-+----------------------------------------------+----------------------+----------------------------------+---------------------------------------------------+----------------------------------+----------------------+---------------------+---------------------------+---------------+-------------------+-------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+----------------------------------------------------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; Name ; Pin Type ; D1 ; D3_0 ; D3_1 ; D4 ; D5 ; D5 OE ; D5 OCT ; T11 (Postamble Gating) ; T11 (Postamble Ungating) ;
-+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-; KEY[3] ; Input ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; LEDR[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[8] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; LEDR[9] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX0[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX1[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX2[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; HEX3[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_R[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_G[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[0] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[1] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[2] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[3] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[4] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[5] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[6] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_B[7] ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_HS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_VS ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_CLK ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; VGA_BLANK_N ; Output ; -- ; -- ; -- ; -- ; (0) ; (31) ; -- ; -- ; -- ;
-; CLOCK_50 ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[2] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[7] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[1] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; KEY[0] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[2] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[9] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[1] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[4] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[3] ; Input ; -- ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[5] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[8] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[0] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-; SW[6] ; Input ; -- ; (0) ; -- ; -- ; -- ; -- ; -- ; -- ; -- ;
-+-------------+----------+----+------+------+----+------+-------+--------+------------------------+--------------------------+
-
-
-+--------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+--------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+--------------------------------------------------------------------+-------------------+---------+
-; KEY[3] ; ; ;
-; CLOCK_50 ; ; ;
-; KEY[2] ; ; ;
-; - razzle:raz_inst|VGA_VS~0 ; 0 ; 0 ;
-; SW[7] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][7] ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][7] ; 1 ; 0 ;
-; KEY[1] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|always0~0 ; 0 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|DataValid~0 ; 0 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|last_buttons[1]~0 ; 0 ; 0 ;
-; KEY[0] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|always0~1 ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|DataValid~1 ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|last_buttons[0]~1 ; 1 ; 0 ;
-; SW[2] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][2] ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][2] ; 1 ; 0 ;
-; SW[9] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][9] ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][9] ; 1 ; 0 ;
-; SW[1] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][1] ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][1] ; 1 ; 0 ;
-; SW[4] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][4] ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][4] ; 1 ; 0 ;
-; SW[3] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][3] ; 1 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][3] ; 1 ; 0 ;
-; SW[5] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][5] ; 0 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][5] ; 0 ; 0 ;
-; SW[8] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][8] ; 0 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][8] ; 0 ; 0 ;
-; SW[0] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][0] ; 0 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][0] ; 0 ; 0 ;
-; SW[6] ; ; ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][6] ; 0 ; 0 ;
-; - arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][6] ; 0 ; 0 ;
-+--------------------------------------------------------------------+-------------------+---------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+------------------------------------------------------------------------------------------------------------------------------------------+----------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+------------------------------------------------------------------------------------------------------------------------------------------+----------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AB27 ; 1680 ; Clock ; yes ; Global Clock ; GCLK8 ; -- ;
-; KEY[2] ; PIN_Y27 ; 1320 ; Async. clear ; yes ; Global Clock ; GCLK10 ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ax1wx4~0 ; LABCELL_X37_Y11_N3 ; 42 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bpsvx4~0 ; LABCELL_X50_Y18_N3 ; 19 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C5ovx4 ; LABCELL_X37_Y26_N57 ; 27 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dv1wx4~0 ; LABCELL_X36_Y14_N6 ; 42 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Edovx4 ; LABCELL_X50_Y20_N15 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fw1wx4~1 ; LABCELL_X37_Y11_N30 ; 46 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G02wx4 ; MLABCELL_X39_Y15_N54 ; 40 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hfyvx4~2 ; LABCELL_X40_Y11_N30 ; 49 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hx1wx4~1 ; MLABCELL_X39_Y11_N0 ; 44 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I2uvx4~0 ; MLABCELL_X34_Y23_N42 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J5vvx4 ; MLABCELL_X47_Y16_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K6yvx4~10 ; LABCELL_X55_Y15_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kv1wx4~0 ; LABCELL_X35_Y11_N33 ; 47 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L0uvx4 ; LABCELL_X37_Y23_N45 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Meyvx4 ; LABCELL_X35_Y11_N15 ; 45 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mw1wx4~1 ; LABCELL_X35_Y11_N9 ; 49 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pu1wx4 ; MLABCELL_X39_Y15_N57 ; 44 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qztvx4 ; LABCELL_X36_Y24_N39 ; 13 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rfpvx4~5 ; LABCELL_X56_Y19_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rv1wx4~1 ; LABCELL_X35_Y11_N30 ; 46 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T5tvx4 ; LABCELL_X35_Y21_N0 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tw1wx4~1 ; LABCELL_X33_Y16_N12 ; 46 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U1uvx4 ; MLABCELL_X39_Y25_N24 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U5qvx4 ; LABCELL_X45_Y14_N54 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vytvx4 ; LABCELL_X37_Y23_N57 ; 13 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W2uvx4 ; MLABCELL_X39_Y22_N12 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wcyvx4~3 ; LABCELL_X40_Y11_N9 ; 46 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wu1wx4~1 ; LABCELL_X40_Y11_N54 ; 42 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yafwx4~5 ; LABCELL_X56_Y15_N42 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ydyvx4 ; LABCELL_X35_Y11_N21 ; 46 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yv1wx4~1 ; LABCELL_X37_Y11_N42 ; 44 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z0uvx4 ; LABCELL_X37_Y23_N9 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z9zvx4~0 ; MLABCELL_X52_Y21_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_interconnect:interconnect_1|HREADY~0 ; MLABCELL_X47_Y16_N6 ; 69 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2716w[3]~1 ; LABCELL_X43_Y24_N54 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2726w[3]~1 ; MLABCELL_X47_Y26_N15 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2736w[3]~1 ; LABCELL_X42_Y23_N57 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2746w[3]~1 ; MLABCELL_X47_Y26_N36 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2756w[3]~1 ; MLABCELL_X47_Y26_N33 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2766w[3]~0 ; MLABCELL_X47_Y26_N21 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2776w[3]~0 ; MLABCELL_X47_Y26_N54 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2799w[3]~0 ; LABCELL_X43_Y24_N33 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2810w[3]~0 ; LABCELL_X43_Y24_N3 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2820w[3]~0 ; MLABCELL_X47_Y26_N57 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2830w[3]~0 ; LABCELL_X46_Y24_N30 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2840w[3]~0 ; MLABCELL_X47_Y26_N42 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2850w[3]~0 ; MLABCELL_X47_Y26_N3 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2860w[3]~0 ; MLABCELL_X47_Y26_N51 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2870w[3]~0 ; LABCELL_X42_Y23_N39 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2892w[3]~0 ; LABCELL_X43_Y24_N39 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2903w[3]~0 ; LABCELL_X43_Y24_N51 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2913w[3]~0 ; MLABCELL_X47_Y26_N39 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2923w[3]~0 ; LABCELL_X42_Y23_N9 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2933w[3]~0 ; LABCELL_X42_Y23_N27 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2943w[3]~0 ; MLABCELL_X47_Y26_N6 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2953w[3]~0 ; MLABCELL_X47_Y26_N48 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2963w[3]~0 ; MLABCELL_X47_Y26_N30 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2985w[3]~0 ; LABCELL_X43_Y24_N57 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode2996w[3]~0 ; LABCELL_X43_Y24_N0 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3006w[3]~0 ; MLABCELL_X47_Y26_N24 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3016w[3]~0 ; LABCELL_X46_Y24_N0 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3026w[3]~0 ; MLABCELL_X47_Y26_N18 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3036w[3]~0 ; MLABCELL_X47_Y26_N27 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3046w[3]~0 ; LABCELL_X42_Y23_N54 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3056w[3]~0 ; MLABCELL_X47_Y26_N0 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3078w[3]~0 ; LABCELL_X42_Y23_N3 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3089w[3]~0 ; LABCELL_X42_Y23_N51 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3099w[3]~1 ; LABCELL_X42_Y23_N33 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3109w[3]~1 ; LABCELL_X42_Y23_N48 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3119w[3]~0 ; LABCELL_X42_Y23_N0 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2|w_anode3129w[3]~0 ; LABCELL_X42_Y23_N6 ; 4 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3460w[3]~0 ; LABCELL_X43_Y19_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3477w[3] ; LABCELL_X43_Y18_N33 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3487w[3] ; LABCELL_X42_Y20_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3497w[3]~0 ; LABCELL_X42_Y21_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3507w[3] ; LABCELL_X42_Y19_N36 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3517w[3]~2 ; LABCELL_X42_Y20_N30 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3527w[3]~1 ; LABCELL_X42_Y20_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3537w[3]~0 ; LABCELL_X42_Y22_N39 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3561w[3] ; LABCELL_X42_Y18_N36 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3572w[3]~1 ; LABCELL_X42_Y20_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3582w[3]~0 ; LABCELL_X43_Y18_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3592w[3]~1 ; LABCELL_X42_Y20_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3602w[3]~0 ; LABCELL_X43_Y18_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3612w[3]~1 ; LABCELL_X42_Y19_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3622w[3]~0 ; LABCELL_X43_Y18_N21 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3632w[3]~0 ; LABCELL_X43_Y19_N39 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3655w[3] ; LABCELL_X42_Y18_N39 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3666w[3]~0 ; LABCELL_X42_Y19_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3676w[3]~0 ; LABCELL_X43_Y18_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3686w[3]~0 ; LABCELL_X42_Y19_N57 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3696w[3]~0 ; LABCELL_X43_Y18_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3706w[3]~0 ; LABCELL_X42_Y19_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3716w[3]~0 ; LABCELL_X43_Y18_N18 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3726w[3]~1 ; LABCELL_X42_Y19_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3749w[3] ; LABCELL_X43_Y18_N3 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3760w[3]~0 ; LABCELL_X42_Y19_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3770w[3]~0 ; LABCELL_X43_Y18_N27 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3780w[3]~0 ; LABCELL_X42_Y19_N45 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3790w[3]~0 ; LABCELL_X43_Y18_N6 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3800w[3]~0 ; LABCELL_X42_Y19_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3810w[3]~0 ; LABCELL_X42_Y21_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3820w[3]~0 ; LABCELL_X43_Y19_N54 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3843w[3] ; LABCELL_X43_Y19_N48 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3854w[3]~0 ; LABCELL_X42_Y20_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3864w[3]~1 ; LABCELL_X42_Y22_N51 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3874w[3]~0 ; LABCELL_X42_Y20_N12 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3884w[3]~0 ; LABCELL_X42_Y22_N24 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b|w_anode3894w[3]~0 ; LABCELL_X42_Y20_N27 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|always0~0 ; LABCELL_X43_Y16_N36 ; 69 ; Sync. clear ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory~18 ; LABCELL_X43_Y24_N9 ; 8 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory~21 ; LABCELL_X43_Y24_N42 ; 8 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_ram:ram_1|always1~0 ; LABCELL_X27_Y16_N57 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_ram:ram_1|write_cycle ; FF_X27_Y18_N13 ; 61 ; Write enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_switches:switches_1|always0~0 ; LABCELL_X50_Y14_N36 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; arm_soc:soc_inst|ahb_switches:switches_1|always0~1 ; LABCELL_X50_Y14_N54 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
-; razzle:raz_inst|Equal2~2 ; LABCELL_X79_Y4_N54 ; 15 ; Sync. load ; no ; -- ; -- ; -- ;
-; razzle:raz_inst|LessThan0~0 ; LABCELL_X75_Y4_N42 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;
-; razzle:raz_inst|LessThan1~3 ; LABCELL_X79_Y4_N57 ; 18 ; Sync. clear ; no ; -- ; -- ; -- ;
-; razzle:raz_inst|LessThan6~0 ; LABCELL_X77_Y4_N30 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;
-; razzle:raz_inst|VGA_VS~0 ; LABCELL_X77_Y4_N54 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
-; razzle:raz_inst|always1~4 ; LABCELL_X80_Y4_N54 ; 13 ; Sync. clear ; no ; -- ; -- ; -- ;
-; tick_count[0] ; FF_X70_Y2_N29 ; 50 ; Clock enable ; no ; -- ; -- ; -- ;
-+------------------------------------------------------------------------------------------------------------------------------------------+----------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Global & Other Fast Signals ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-; CLOCK_50 ; PIN_AB27 ; 1680 ; Global Clock ; GCLK8 ; -- ;
-; KEY[2] ; PIN_Y27 ; 1320 ; Global Clock ; GCLK10 ; -- ;
-+----------+----------+---------+----------------------+------------------+---------------------------+
-
-
-+---------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals ;
-+-----------------------------------------------------------------------+---------+
-; Name ; Fan-Out ;
-+-----------------------------------------------------------------------+---------+
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o~4 ; 614 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o[7] ; 612 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o[1] ; 609 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o[2] ; 607 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o[4] ; 607 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o~19 ; 607 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o[5] ; 606 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|hwdata_o~20 ; 606 ;
-+-----------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter RAM Summary ;
-+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+--------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
-; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M10K blocks ; MLAB cells ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ;
-+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+--------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 307200 ; 8 ; 307200 ; 8 ; yes ; no ; yes ; no ; 2457600 ; 307200 ; 8 ; 307200 ; 8 ; 2457600 ; 300 ; 0 ; None ; M10K_X38_Y41_N0, M10K_X41_Y22_N0, M10K_X14_Y20_N0, M10K_X41_Y4_N0, M10K_X38_Y10_N0, M10K_X49_Y16_N0, M10K_X41_Y15_N0, M10K_X49_Y28_N0, M10K_X38_Y6_N0, M10K_X49_Y3_N0, M10K_X49_Y19_N0, M10K_X49_Y43_N0, M10K_X69_Y27_N0, M10K_X49_Y5_N0, M10K_X58_Y6_N0, M10K_X76_Y31_N0, M10K_X76_Y30_N0, M10K_X58_Y4_N0, M10K_X69_Y11_N0, M10K_X49_Y21_N0, M10K_X49_Y30_N0, M10K_X76_Y23_N0, M10K_X38_Y47_N0, M10K_X14_Y3_N0, M10K_X38_Y5_N0, M10K_X49_Y46_N0, M10K_X26_Y22_N0, M10K_X38_Y20_N0, M10K_X41_Y3_N0, M10K_X69_Y28_N0, M10K_X69_Y33_N0, M10K_X49_Y40_N0, M10K_X76_Y28_N0, M10K_X41_Y1_N0, M10K_X14_Y35_N0, M10K_X41_Y27_N0, M10K_X49_Y11_N0, M10K_X38_Y42_N0, M10K_X38_Y31_N0, M10K_X14_Y23_N0, M10K_X26_Y35_N0, M10K_X49_Y13_N0, M10K_X14_Y22_N0, M10K_X38_Y38_N0, M10K_X26_Y32_N0, M10K_X58_Y8_N0, M10K_X41_Y6_N0, M10K_X69_Y4_N0, M10K_X38_Y8_N0, M10K_X58_Y26_N0, M10K_X49_Y44_N0, M10K_X49_Y7_N0, M10K_X41_Y30_N0, M10K_X49_Y48_N0, M10K_X14_Y27_N0, M10K_X58_Y18_N0, M10K_X14_Y31_N0, M10K_X41_Y25_N0, M10K_X69_Y35_N0, M10K_X38_Y39_N0, M10K_X14_Y8_N0, M10K_X58_Y5_N0, M10K_X41_Y14_N0, M10K_X69_Y5_N0, M10K_X41_Y48_N0, M10K_X26_Y7_N0, M10K_X38_Y14_N0, M10K_X38_Y33_N0, M10K_X14_Y12_N0, M10K_X14_Y18_N0, M10K_X49_Y45_N0, M10K_X14_Y9_N0, M10K_X41_Y46_N0, M10K_X58_Y24_N0, M10K_X49_Y27_N0, M10K_X76_Y19_N0, M10K_X38_Y24_N0, M10K_X69_Y36_N0, M10K_X5_Y14_N0, M10K_X49_Y24_N0, M10K_X41_Y10_N0, M10K_X26_Y43_N0, M10K_X38_Y1_N0, M10K_X49_Y26_N0, M10K_X49_Y25_N0, M10K_X41_Y7_N0, M10K_X58_Y19_N0, M10K_X41_Y33_N0, M10K_X49_Y32_N0, M10K_X76_Y26_N0, M10K_X69_Y29_N0, M10K_X58_Y1_N0, M10K_X69_Y21_N0, M10K_X58_Y23_N0, M10K_X38_Y19_N0, M10K_X41_Y34_N0, M10K_X26_Y23_N0, M10K_X76_Y27_N0, M10K_X14_Y32_N0, M10K_X38_Y43_N0, M10K_X38_Y45_N0, M10K_X76_Y14_N0, M10K_X26_Y24_N0, M10K_X49_Y20_N0, M10K_X58_Y15_N0, M10K_X49_Y12_N0, M10K_X14_Y24_N0, M10K_X26_Y8_N0, M10K_X76_Y15_N0, M10K_X26_Y25_N0, M10K_X26_Y37_N0, M10K_X69_Y24_N0, M10K_X58_Y21_N0, M10K_X58_Y33_N0, M10K_X49_Y17_N0, M10K_X38_Y25_N0, M10K_X26_Y28_N0, M10K_X76_Y24_N0, M10K_X26_Y42_N0, M10K_X38_Y16_N0, M10K_X26_Y29_N0, M10K_X58_Y27_N0, M10K_X69_Y16_N0, M10K_X38_Y12_N0, M10K_X76_Y32_N0, M10K_X14_Y19_N0, M10K_X49_Y31_N0, M10K_X26_Y3_N0, M10K_X69_Y34_N0, M10K_X38_Y11_N0, M10K_X69_Y31_N0, M10K_X41_Y23_N0, M10K_X69_Y10_N0, M10K_X38_Y34_N0, M10K_X58_Y12_N0, M10K_X58_Y11_N0, M10K_X26_Y31_N0, M10K_X58_Y31_N0, M10K_X76_Y12_N0, M10K_X69_Y9_N0, M10K_X38_Y7_N0, M10K_X69_Y19_N0, M10K_X41_Y43_N0, M10K_X69_Y20_N0, M10K_X14_Y28_N0, M10K_X38_Y30_N0, M10K_X41_Y42_N0, M10K_X14_Y26_N0, M10K_X14_Y33_N0, M10K_X49_Y23_N0, M10K_X58_Y10_N0, M10K_X26_Y33_N0, M10K_X41_Y40_N0, M10K_X49_Y41_N0, M10K_X41_Y26_N0, M10K_X26_Y34_N0, M10K_X69_Y13_N0, M10K_X49_Y4_N0, M10K_X69_Y25_N0, M10K_X41_Y29_N0, M10K_X49_Y14_N0, M10K_X41_Y12_N0, M10K_X58_Y16_N0, M10K_X26_Y27_N0, M10K_X58_Y32_N0, M10K_X69_Y7_N0, M10K_X14_Y5_N0, M10K_X69_Y15_N0, M10K_X49_Y29_N0, M10K_X69_Y18_N0, M10K_X26_Y1_N0, M10K_X14_Y21_N0, M10K_X58_Y13_N0, M10K_X49_Y47_N0, M10K_X69_Y12_N0, M10K_X49_Y15_N0, M10K_X38_Y46_N0, M10K_X76_Y20_N0, M10K_X41_Y16_N0, M10K_X69_Y8_N0, M10K_X38_Y36_N0, M10K_X49_Y8_N0, M10K_X58_Y14_N0, M10K_X76_Y17_N0, M10K_X58_Y9_N0, M10K_X14_Y10_N0, M10K_X41_Y32_N0, M10K_X69_Y23_N0, M10K_X38_Y32_N0, M10K_X49_Y35_N0, M10K_X38_Y37_N0, M10K_X49_Y9_N0, M10K_X26_Y36_N0, M10K_X26_Y30_N0, M10K_X41_Y9_N0, M10K_X49_Y38_N0, M10K_X58_Y28_N0, M10K_X58_Y2_N0, M10K_X58_Y30_N0, M10K_X38_Y40_N0, M10K_X38_Y35_N0, M10K_X49_Y39_N0, M10K_X69_Y32_N0, M10K_X49_Y1_N0, M10K_X38_Y3_N0, M10K_X26_Y2_N0, M10K_X41_Y21_N0, M10K_X58_Y25_N0, M10K_X14_Y13_N0, M10K_X14_Y30_N0, M10K_X14_Y17_N0, M10K_X58_Y3_N0, M10K_X38_Y44_N0, M10K_X41_Y41_N0, M10K_X41_Y28_N0, M10K_X41_Y20_N0, M10K_X26_Y5_N0, M10K_X14_Y36_N0, M10K_X69_Y26_N0, M10K_X38_Y29_N0, M10K_X5_Y5_N0, M10K_X49_Y10_N0, M10K_X38_Y28_N0, M10K_X49_Y33_N0, M10K_X26_Y26_N0, M10K_X76_Y16_N0, M10K_X49_Y18_N0, M10K_X58_Y36_N0, M10K_X49_Y34_N0, M10K_X58_Y17_N0, M10K_X38_Y22_N0, M10K_X38_Y18_N0, M10K_X49_Y42_N0, M10K_X14_Y29_N0, M10K_X49_Y6_N0, M10K_X41_Y18_N0, M10K_X41_Y17_N0, M10K_X49_Y22_N0, M10K_X38_Y13_N0, M10K_X69_Y14_N0, M10K_X38_Y27_N0, M10K_X49_Y2_N0, M10K_X69_Y6_N0, M10K_X76_Y18_N0, M10K_X14_Y11_N0, M10K_X58_Y34_N0, M10K_X41_Y8_N0, M10K_X69_Y30_N0, M10K_X41_Y47_N0, M10K_X26_Y44_N0, M10K_X14_Y4_N0, M10K_X58_Y29_N0, M10K_X38_Y9_N0, M10K_X69_Y22_N0, M10K_X41_Y44_N0, M10K_X41_Y45_N0, M10K_X41_Y36_N0, M10K_X26_Y41_N0, M10K_X76_Y29_N0, M10K_X58_Y35_N0, M10K_X76_Y11_N0, M10K_X76_Y21_N0, M10K_X38_Y17_N0, M10K_X38_Y4_N0, M10K_X41_Y35_N0, M10K_X26_Y38_N0, M10K_X26_Y6_N0, M10K_X38_Y26_N0, M10K_X41_Y39_N0, M10K_X41_Y31_N0, M10K_X58_Y7_N0, M10K_X41_Y11_N0, M10K_X41_Y2_N0, M10K_X14_Y7_N0, M10K_X69_Y17_N0, M10K_X41_Y13_N0, M10K_X76_Y25_N0, M10K_X14_Y6_N0, M10K_X26_Y39_N0, M10K_X41_Y5_N0, M10K_X41_Y38_N0, M10K_X38_Y15_N0, M10K_X41_Y37_N0, M10K_X76_Y8_N0, M10K_X41_Y19_N0, M10K_X38_Y21_N0, M10K_X26_Y40_N0, M10K_X38_Y2_N0, M10K_X76_Y10_N0, M10K_X14_Y34_N0, M10K_X38_Y23_N0, M10K_X26_Y4_N0, M10K_X58_Y22_N0, M10K_X49_Y36_N0, M10K_X76_Y5_N0, M10K_X76_Y7_N0, M10K_X14_Y25_N0, M10K_X76_Y22_N0, M10K_X41_Y24_N0, M10K_X58_Y20_N0 ; Don't care ; New data ; New data ; Off ; No ; No - Address Too Wide ;
-; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 4096 ; 32 ; 4096 ; 32 ; yes ; no ; yes ; no ; 131072 ; 4096 ; 32 ; 4096 ; 32 ; 131072 ; 16 ; 0 ; db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif ; M10K_X26_Y11_N0, M10K_X14_Y16_N0, M10K_X26_Y12_N0, M10K_X26_Y20_N0, M10K_X14_Y14_N0, M10K_X26_Y17_N0, M10K_X26_Y18_N0, M10K_X26_Y13_N0, M10K_X26_Y14_N0, M10K_X26_Y19_N0, M10K_X26_Y21_N0, M10K_X14_Y15_N0, M10K_X26_Y16_N0, M10K_X26_Y15_N0, M10K_X26_Y9_N0, M10K_X26_Y10_N0 ; Old data ; New data ; New data ; Off ; No ; No - Address Too Wide ;
-+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+---------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+-------------+------------+--------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+-----------------+-----------------+----------+------------------------+-----------------------+
-Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
-
-
-+------------------------------------------------------------------------+
-; Routing Usage Summary ;
-+---------------------------------------------+--------------------------+
-; Routing Resource Type ; Usage ;
-+---------------------------------------------+--------------------------+
-; Block interconnects ; 18,040 / 289,320 ( 6 % ) ;
-; C12 interconnects ; 1,156 / 13,420 ( 9 % ) ;
-; C2 interconnects ; 6,144 / 119,108 ( 5 % ) ;
-; C4 interconnects ; 3,197 / 56,300 ( 6 % ) ;
-; DQS bus muxes ; 0 / 25 ( 0 % ) ;
-; DQS-18 I/O buses ; 0 / 25 ( 0 % ) ;
-; DQS-9 I/O buses ; 0 / 25 ( 0 % ) ;
-; Direct links ; 613 / 289,320 ( < 1 % ) ;
-; Global clocks ; 2 / 16 ( 13 % ) ;
-; HPS SDRAM PLL inputs ; 0 / 1 ( 0 % ) ;
-; HPS SDRAM PLL outputs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_BOOT_FROM_FPGA_INPUTs ; 0 / 9 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_INPUTs ; 0 / 7 ( 0 % ) ;
-; HPS_INTERFACE_CLOCKS_RESETS_OUTPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_INPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_CROSS_TRIGGER_OUTPUTs ; 0 / 24 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_INPUTs ; 0 / 37 ( 0 % ) ;
-; HPS_INTERFACE_DBG_APB_OUTPUTs ; 0 / 55 ( 0 % ) ;
-; HPS_INTERFACE_DMA_INPUTs ; 0 / 16 ( 0 % ) ;
-; HPS_INTERFACE_DMA_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_INPUTs ; 0 / 287 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2HPS_OUTPUTs ; 0 / 154 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_INPUTs ; 0 / 852 ( 0 % ) ;
-; HPS_INTERFACE_FPGA2SDRAM_OUTPUTs ; 0 / 408 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_INPUTs ; 0 / 165 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_INPUTs ; 0 / 67 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_LIGHT_WEIGHT_OUTPUTs ; 0 / 156 ( 0 % ) ;
-; HPS_INTERFACE_HPS2FPGA_OUTPUTs ; 0 / 282 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_INPUTs ; 0 / 64 ( 0 % ) ;
-; HPS_INTERFACE_INTERRUPTS_OUTPUTs ; 0 / 42 ( 0 % ) ;
-; HPS_INTERFACE_JTAG_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_INPUTs ; 0 / 142 ( 0 % ) ;
-; HPS_INTERFACE_LOAN_IO_OUTPUTs ; 0 / 85 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_INPUTs ; 0 / 1 ( 0 % ) ;
-; HPS_INTERFACE_MPU_EVENT_STANDBY_OUTPUTs ; 0 / 5 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_MPU_GENERAL_PURPOSE_OUTPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_CAN_OUTPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_INPUTs ; 0 / 32 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_EMAC_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_INPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_I2C_OUTPUTs ; 0 / 8 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_INPUTs ; 0 / 12 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_NAND_OUTPUTs ; 0 / 18 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_QSPI_OUTPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_INPUTs ; 0 / 13 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SDMMC_OUTPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_INPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_MASTER_OUTPUTs ; 0 / 14 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_INPUTs ; 0 / 6 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_SPI_SLAVE_OUTPUTs ; 0 / 4 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_INPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_UART_OUTPUTs ; 0 / 10 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_INPUTs ; 0 / 22 ( 0 % ) ;
-; HPS_INTERFACE_PERIPHERAL_USB_OUTPUTs ; 0 / 34 ( 0 % ) ;
-; HPS_INTERFACE_STM_EVENT_INPUTs ; 0 / 28 ( 0 % ) ;
-; HPS_INTERFACE_TEST_INPUTs ; 0 / 610 ( 0 % ) ;
-; HPS_INTERFACE_TEST_OUTPUTs ; 0 / 513 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_INPUTs ; 0 / 2 ( 0 % ) ;
-; HPS_INTERFACE_TPIU_TRACE_OUTPUTs ; 0 / 33 ( 0 % ) ;
-; Horizontal periphery clocks ; 0 / 72 ( 0 % ) ;
-; Local interconnects ; 1,948 / 84,580 ( 2 % ) ;
-; Quadrant clocks ; 0 / 66 ( 0 % ) ;
-; R14 interconnects ; 1,577 / 12,676 ( 12 % ) ;
-; R14/C12 interconnect drivers ; 2,223 / 20,720 ( 11 % ) ;
-; R3 interconnects ; 7,722 / 130,992 ( 6 % ) ;
-; R6 interconnects ; 12,582 / 266,960 ( 5 % ) ;
-; Spine clocks ; 17 / 360 ( 5 % ) ;
-; Wire stub REs ; 0 / 15,858 ( 0 % ) ;
-+---------------------------------------------+--------------------------+
-
-
-+------------------------------------------+
-; I/O Rules Summary ;
-+----------------------------------+-------+
-; I/O Rules Statistic ; Total ;
-+----------------------------------+-------+
-; Total I/O Rules ; 28 ;
-; Number of I/O Rules Passed ; 6 ;
-; Number of I/O Rules Failed ; 0 ;
-; Number of I/O Rules Unchecked ; 0 ;
-; Number of I/O Rules Inapplicable ; 22 ;
-+----------------------------------+-------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Details ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
-; Inapplicable ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
-; Inapplicable ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; No Location assignments found. ; I/O ; ;
-; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
-; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
-; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; No Location assignments found. ; I/O ; ;
-; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
-; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
-; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
-; Inapplicable ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Inapplicable ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; No Clamping Diode assignments found. ; I/O ; ;
-; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
-; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
-; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
-; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
-; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
-; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 0 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
-; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
-+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; I/O Rules Matrix ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Pin/Rules ; IO_000002 ; IO_000003 ; IO_000001 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000022 ; IO_000021 ; IO_000046 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000047 ; IO_000020 ; IO_000019 ; IO_000018 ; IO_000015 ; IO_000014 ; IO_000013 ; IO_000012 ; IO_000011 ; IO_000010 ; IO_000009 ; IO_000034 ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-; Total Pass ; 0 ; 0 ; 0 ; 0 ; 0 ; 81 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 66 ; 0 ; 0 ; 0 ; 0 ; 0 ; 66 ; 0 ; 0 ; 0 ; 0 ; 66 ; 0 ; 81 ; 81 ; 0 ;
-; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; Total Inapplicable ; 81 ; 81 ; 81 ; 81 ; 81 ; 0 ; 81 ; 81 ; 81 ; 81 ; 81 ; 81 ; 15 ; 81 ; 81 ; 81 ; 81 ; 81 ; 15 ; 81 ; 81 ; 81 ; 81 ; 15 ; 81 ; 0 ; 0 ; 81 ;
-; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
-; KEY[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; LEDR[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX0[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX0[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX0[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX0[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX0[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX0[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX0[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX1[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX1[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX1[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX1[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX1[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX1[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX1[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX2[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX2[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX2[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX2[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX2[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX2[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX2[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX3[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX3[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX3[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX3[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX3[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX3[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; HEX3[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_R[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_G[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_B[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_HS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_VS ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_CLK ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; VGA_BLANK_N ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; CLOCK_50 ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; KEY[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[7] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; KEY[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; KEY[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[2] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[9] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[1] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[4] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[3] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[5] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[8] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[0] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-; SW[6] ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ;
-+--------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+-----------+--------------+
-
-
-+------------------------------------------------------------------------------------------------+
-; Fitter Device Options ;
-+------------------------------------------------------------------+-----------------------------+
-; Option ; Setting ;
-+------------------------------------------------------------------+-----------------------------+
-; Enable user-supplied start-up clock (CLKUSR) ; Off ;
-; Enable device-wide reset (DEV_CLRn) ; Off ;
-; Enable device-wide output enable (DEV_OE) ; Off ;
-; Enable INIT_DONE output ; Off ;
-; Configuration scheme ; Passive Serial ;
-; Enable Error Detection CRC_ERROR pin ; Off ;
-; Enable CvP_CONFDONE pin ; Off ;
-; Enable open drain on CRC_ERROR pin ; On ;
-; Enable open drain on CvP_CONFDONE pin ; On ;
-; Enable open drain on INIT_DONE pin ; On ;
-; Enable open drain on Partial Reconfiguration pins ; Off ;
-; Enable open drain on nCEO pin ; On ;
-; Enable Partial Reconfiguration pins ; Off ;
-; Enable input tri-state on active configuration pins in user mode ; Off ;
-; Enable internal scrubbing ; Off ;
-; Active Serial clock source ; 100 MHz Internal Oscillator ;
-; Device initialization clock source ; Internal Oscillator ;
-; Configuration via Protocol ; Off ;
-; Configuration Voltage Level ; Auto ;
-; Force Configuration Voltage Level ; Off ;
-; Enable nCEO output ; Off ;
-; Data[15..8] ; Unreserved ;
-; Data[7..5] ; Unreserved ;
-; Base pin-out file on sameframe device ; Off ;
-+------------------------------------------------------------------+-----------------------------+
-
-
-+------------------------------------+
-; Operating Settings and Conditions ;
-+---------------------------+--------+
-; Setting ; Value ;
-+---------------------------+--------+
-; Nominal Core Voltage ; 1.10 V ;
-; Low Junction Temperature ; 0 °C ;
-; High Junction Temperature ; 85 °C ;
-+---------------------------+--------+
-
-
-+------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Summary ;
-+-----------------+----------------------+-------------------+
-; Source Clock(s) ; Destination Clock(s) ; Delay Added in ns ;
-+-----------------+----------------------+-------------------+
-; CLOCK_50 ; CLOCK_50 ; 135.2 ;
-+-----------------+----------------------+-------------------+
-Note: For more information on problematic transfers, consider running the Fitter again with the Optimize hold timing option (Settings Menu) turned off.
-This will disable optimization of problematic paths and expose them for further analysis using the TimeQuest Timing Analyzer.
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Estimated Delay Added for Hold Timing Details ;
-+------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------+
-; Source Register ; Destination Register ; Delay Added in ns ;
-+------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------+
-; razzle:raz_inst|H_count[7] ; razzle:raz_inst|VGA_HS ; 0.862 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[9] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a160~porta_address_reg0 ; 0.632 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z7i2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qem2z4 ; 0.619 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pet2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qem2z4 ; 0.562 ;
-; razzle:raz_inst|H_count[4] ; razzle:raz_inst|VGA_HS ; 0.542 ;
-; razzle:raz_inst|H_count[3] ; razzle:raz_inst|VGA_HS ; 0.542 ;
-; razzle:raz_inst|H_count[2] ; razzle:raz_inst|VGA_HS ; 0.542 ;
-; razzle:raz_inst|H_count[1] ; razzle:raz_inst|VGA_HS ; 0.542 ;
-; razzle:raz_inst|H_count[0] ; razzle:raz_inst|VGA_HS ; 0.542 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[1] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a175~porta_address_reg0 ; 0.516 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[7] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a160~porta_address_reg0 ; 0.488 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[11] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a160~porta_address_reg0 ; 0.488 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[3] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a160~porta_address_reg0 ; 0.460 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[0] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a237~porta_address_reg0 ; 0.446 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[10] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.433 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[2] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a6~porta_address_reg0 ; 0.427 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jhy2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bsy2z4 ; 0.425 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[5] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a264~porta_address_reg0 ; 0.417 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[12] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a185~porta_address_reg0 ; 0.415 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Joi3z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Umi3z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|B943z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ki53z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jq13z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sz23z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fli3z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qji3z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q7j2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tr63z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|F9j2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zpj2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C183z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tvt2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vmj2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C5v2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|ahb_ram:ram_1|write_cycle ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|ahb_ram:ram_1|byte_select[3] ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rr83z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hq33z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cvr2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Imu2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Eyr2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Otr2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Asr2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rvv2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qyc3z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|E913z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ii73z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qwr2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yg23z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qz43z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Szr2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z863z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Iwp2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qz33z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z853z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yg13z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hq23z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ii63z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Skm2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gmm2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Unm2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rr73z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Imt2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ejm2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rvu2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ek03z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Knz2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M1j2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kc03z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R293z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~portb_address_reg0 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H3d3z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Svk2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T1d3z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yaz2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Y9t2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Tki2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fij2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ark2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Npk2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sgj2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ffj2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Aok2z4 ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ram_block1a24~porta_datain_reg0 ; 0.411 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[8] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a77~porta_address_reg0 ; 0.407 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|word_address[6] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ram_block1a264~porta_address_reg0 ; 0.388 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G9w2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W7z2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I6z2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K9z2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K1z2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C3z2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I2t2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Auk2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cyq2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O5t2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L8t2z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Emi2z4 ; 0.378 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gcb3z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qem2z4 ; 0.363 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pab3z4 ; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qem2z4 ; 0.363 ;
-+------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------------------+
-Note: This table only shows the top 100 path(s) that have the largest delay added for hold.
-
-
-+-----------------+
-; Fitter Messages ;
-+-----------------+
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 16 of the 24 processors detected
-Info (119006): Selected device 5CSEMA5F31C6 for design "de1_soc_wrapper"
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
-Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
-Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Critical Warning (169085): No exact pin location assignment(s) for 81 pins of 81 total pins. For the list of pins please refer to the I/O Assignment Warnings table in the fitter report.
-Info (184020): Starting Fitter periphery placement operations
-Info (11178): Promoted 1 clock (1 global)
- Info (11162): CLOCK_50~inputCLKENA0 with 1667 fanout uses global clock CLKCTRL_G8
-Info (11191): Automatically promoted 1 clock (1 global)
- Info (11162): KEY[2]~inputCLKENA0 with 983 fanout uses global clock CLKCTRL_G10
-Info (184021): Fitter periphery placement operations ending: elapsed time is 00:00:00
-Info (176233): Starting register packing
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'de1_soc_wrapper.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332144): No user constrained base clocks found in the design
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time.
-Info (176235): Finished register packing
- Extra Info (176219): No registers were packed into other blocks
-Info (11798): Fitter preparation operations ending: elapsed time is 00:00:17
-Info (170189): Fitter placement preparation operations beginning
-Info (14951): The Fitter is using Advanced Physical Optimization.
-Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:17
-Info (170191): Fitter placement operations beginning
-Info (170137): Fitter placement was successful
-Info (170192): Fitter placement operations ending: elapsed time is 00:00:20
-Info (170193): Fitter routing operations beginning
-Info (170195): Router estimated average interconnect usage is 5% of the available device resources
- Info (170196): Router estimated peak interconnect usage is 43% of the available device resources in the region that extends from location X33_Y11 to location X44_Y22
-Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
- Info (170201): Optimizations that may affect the design's routability were skipped
-Info (170194): Fitter routing operations ending: elapsed time is 00:01:13
-Info (11888): Total time spent on timing analysis during the Fitter is 9.69 seconds.
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (11801): Fitter post-fit operations ending: elapsed time is 00:00:13
-Info: Quartus Prime Fitter was successful. 0 errors, 4 warnings
- Info: Peak virtual memory: 2695 megabytes
- Info: Processing ended: Thu Sep 17 17:58:34 2020
- Info: Elapsed time: 00:03:08
- Info: Total CPU time (on all processors): 00:15:08
-
-
diff --git a/output_files/de1_soc_wrapper.fit.summary b/output_files/de1_soc_wrapper.fit.summary
deleted file mode 100644
index 3d9b11fc2fc6f89cd70f7069d55643f799801b34..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.fit.summary
+++ /dev/null
@@ -1,20 +0,0 @@
-Fitter Status : Successful - Thu Sep 17 17:58:32 2020
-Quartus Prime Version : 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-Revision Name : de1_soc_wrapper
-Top-level Entity Name : de1_soc_wrapper
-Family : Cyclone V
-Device : 5CSEMA5F31C6
-Timing Models : Final
-Logic utilization (in ALMs) : 2,241 / 32,070 ( 7 % )
-Total registers : 1364
-Total pins : 81 / 457 ( 18 % )
-Total virtual pins : 0
-Total block memory bits : 2,588,672 / 4,065,280 ( 64 % )
-Total RAM Blocks : 316 / 397 ( 80 % )
-Total DSP Blocks : 0 / 87 ( 0 % )
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0 / 6 ( 0 % )
-Total DLLs : 0 / 4 ( 0 % )
diff --git a/output_files/de1_soc_wrapper.flow.rpt b/output_files/de1_soc_wrapper.flow.rpt
deleted file mode 100644
index 99a777a5372af93f8c1090725b50a59ad876bacd..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.flow.rpt
+++ /dev/null
@@ -1,132 +0,0 @@
-Flow report for de1_soc_wrapper
-Thu Sep 17 17:59:11 2020
-Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Flow Summary
- 3. Flow Settings
- 4. Flow Non-Default Global Settings
- 5. Flow Elapsed Time
- 6. Flow OS Summary
- 7. Flow Log
- 8. Flow Messages
- 9. Flow Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Flow Summary ;
-+---------------------------------+-------------------------------------------------+
-; Flow Status ; Successful - Thu Sep 17 17:59:11 2020 ;
-; Quartus Prime Version ; 16.1.2 Build 203 01/18/2017 SJ Standard Edition ;
-; Revision Name ; de1_soc_wrapper ;
-; Top-level Entity Name ; de1_soc_wrapper ;
-; Family ; Cyclone V ;
-; Device ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Logic utilization (in ALMs) ; 2,241 / 32,070 ( 7 % ) ;
-; Total registers ; 1364 ;
-; Total pins ; 81 / 457 ( 18 % ) ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 2,588,672 / 4,065,280 ( 64 % ) ;
-; Total DSP Blocks ; 0 / 87 ( 0 % ) ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 / 6 ( 0 % ) ;
-; Total DLLs ; 0 / 4 ( 0 % ) ;
-+---------------------------------+-------------------------------------------------+
-
-
-+-----------------------------------------+
-; Flow Settings ;
-+-------------------+---------------------+
-; Option ; Setting ;
-+-------------------+---------------------+
-; Start date & time ; 09/17/2020 17:54:54 ;
-; Main task ; Compilation ;
-; Revision Name ; de1_soc_wrapper ;
-+-------------------+---------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------+
-; Flow Non-Default Global Settings ;
-+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
-; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
-+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
-; COMPILER_SIGNATURE_ID ; 345050572627.160036169463856 ; -- ; -- ; -- ;
-; EDA_OUTPUT_DATA_FORMAT ; Systemverilog Hdl ; -- ; -- ; eda_simulation ;
-; EDA_SIMULATION_TOOL ; ModelSim-Altera (SystemVerilog) ; <None> ; -- ; -- ;
-; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
-; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
-; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
-; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; -- ; Top ;
-; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
-+-------------------------------------+----------------------------------------+---------------+-------------+----------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------+
-; Flow Elapsed Time ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-; Analysis & Synthesis ; 00:00:31 ; 1.0 ; 1480 MB ; 00:00:44 ;
-; Fitter ; 00:03:06 ; 1.3 ; 2695 MB ; 00:15:06 ;
-; Assembler ; 00:00:12 ; 1.0 ; 1153 MB ; 00:00:11 ;
-; TimeQuest Timing Analyzer ; 00:00:17 ; 3.9 ; 1746 MB ; 00:00:51 ;
-; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 1355 MB ; 00:00:03 ;
-; Total ; 00:04:08 ; -- ; -- ; 00:16:55 ;
-+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
-
-
-+--------------------------------------------------------------------------------------+
-; Flow OS Summary ;
-+---------------------------+------------------+---------+------------+----------------+
-; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
-+---------------------------+------------------+---------+------------+----------------+
-; Analysis & Synthesis ; srv02749 ; Red Hat ; Red Hat ; x86_64 ;
-; Fitter ; srv02749 ; Red Hat ; Red Hat ; x86_64 ;
-; Assembler ; srv02749 ; Red Hat ; Red Hat ; x86_64 ;
-; TimeQuest Timing Analyzer ; srv02749 ; Red Hat ; Red Hat ; x86_64 ;
-; EDA Netlist Writer ; srv02749 ; Red Hat ; Red Hat ; x86_64 ;
-+---------------------------+------------------+---------+------------+----------------+
-
-
-------------
-; Flow Log ;
-------------
-quartus_map --read_settings_files=on --write_settings_files=off Msc_proj -c de1_soc_wrapper
-quartus_fit --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper
-quartus_asm --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper
-quartus_sta Msc_proj -c de1_soc_wrapper
-quartus_eda --read_settings_files=off --write_settings_files=off Msc_proj -c de1_soc_wrapper
-
-
-
diff --git a/output_files/de1_soc_wrapper.jdi b/output_files/de1_soc_wrapper.jdi
deleted file mode 100644
index b6668f277a42bb1ad2e7aca3763580ce491c14fc..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.jdi
+++ /dev/null
@@ -1,8 +0,0 @@
-<sld_project_info>
- <project>
- <hash md5_digest_80b="4f3d6b7f0e221599f8fd"/>
- </project>
- <file_info>
- <file device="5CSEMA5F31C6" path="de1_soc_wrapper.sof" usercode="0xFFFFFFFF"/>
- </file_info>
-</sld_project_info>
diff --git a/output_files/de1_soc_wrapper.map.rpt b/output_files/de1_soc_wrapper.map.rpt
deleted file mode 100644
index 9a80934e28977c3893f8629581925c3edf2a162e..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.map.rpt
+++ /dev/null
@@ -1,1067 +0,0 @@
-Analysis & Synthesis report for de1_soc_wrapper
-Thu Sep 17 17:55:26 2020
-Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Parallel Compilation
- 5. Analysis & Synthesis Source Files Read
- 6. Analysis & Synthesis Resource Usage Summary
- 7. Analysis & Synthesis Resource Utilization by Entity
- 8. Analysis & Synthesis RAM Summary
- 9. Registers Removed During Synthesis
- 10. General Register Statistics
- 11. Inverted Register Statistics
- 12. Registers Added for RAM Pass-Through Logic
- 13. Registers Packed Into Inferred Megafunctions
- 14. Multiplexer Restructuring Statistics (Restructuring Performed)
- 15. Source assignments for arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated
- 16. Source assignments for arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated
- 17. Parameter Settings for User Entity Instance: arm_soc:soc_inst|ahb_interconnect:interconnect_1
- 18. Parameter Settings for User Entity Instance: arm_soc:soc_inst|ahb_ram:ram_1
- 19. Parameter Settings for Inferred Entity Instance: arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0
- 20. Parameter Settings for Inferred Entity Instance: arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0
- 21. altsyncram Parameter Settings by Entity Instance
- 22. Port Connectivity Checks: "razzle:raz_inst"
- 23. Port Connectivity Checks: "arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic"
- 24. Port Connectivity Checks: "arm_soc:soc_inst|CORTEXM0DS:m0_1"
- 25. Port Connectivity Checks: "arm_soc:soc_inst"
- 26. Post-Synthesis Netlist Statistics for Top Partition
- 27. Elapsed Time Per Partition
- 28. Analysis & Synthesis Messages
- 29. Analysis & Synthesis Suppressed Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+-----------------------------------------------------------------------------------+
-; Analysis & Synthesis Summary ;
-+---------------------------------+-------------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Thu Sep 17 17:55:25 2020 ;
-; Quartus Prime Version ; 16.1.2 Build 203 01/18/2017 SJ Standard Edition ;
-; Revision Name ; de1_soc_wrapper ;
-; Top-level Entity Name ; de1_soc_wrapper ;
-; Family ; Cyclone V ;
-; Logic utilization (in ALMs) ; N/A ;
-; Total registers ; 1027 ;
-; Total pins ; 81 ;
-; Total virtual pins ; 0 ;
-; Total block memory bits ; 2,588,672 ;
-; Total DSP Blocks ; 0 ;
-; Total HSSI RX PCSs ; 0 ;
-; Total HSSI PMA RX Deserializers ; 0 ;
-; Total HSSI TX PCSs ; 0 ;
-; Total HSSI PMA TX Serializers ; 0 ;
-; Total PLLs ; 0 ;
-; Total DLLs ; 0 ;
-+---------------------------------+-------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Settings ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Option ; Setting ; Default Value ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-; Device ; 5CSEMA5F31C6 ; ;
-; Top-level entity name ; de1_soc_wrapper ; de1_soc_wrapper ;
-; Family name ; Cyclone V ; Cyclone V ;
-; Use smart compilation ; Off ; Off ;
-; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ;
-; Enable compact report table ; Off ; Off ;
-; Restructure Multiplexers ; Auto ; Auto ;
-; MLAB Add Timing Constraints For Mixed-Port Feed-Through Mode Setting Don't Care ; Off ; Off ;
-; Create Debugging Nodes for IP Cores ; Off ; Off ;
-; Preserve fewer node names ; On ; On ;
-; OpenCore Plus hardware evaluation ; Enable ; Enable ;
-; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
-; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
-; State Machine Processing ; Auto ; Auto ;
-; Safe State Machine ; Off ; Off ;
-; Extract Verilog State Machines ; On ; On ;
-; Extract VHDL State Machines ; On ; On ;
-; Ignore Verilog initial constructs ; Off ; Off ;
-; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
-; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
-; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
-; Infer RAMs from Raw Logic ; On ; On ;
-; Parallel Synthesis ; On ; On ;
-; DSP Block Balancing ; Auto ; Auto ;
-; NOT Gate Push-Back ; On ; On ;
-; Power-Up Don't Care ; On ; On ;
-; Remove Redundant Logic Cells ; Off ; Off ;
-; Remove Duplicate Registers ; On ; On ;
-; Ignore CARRY Buffers ; Off ; Off ;
-; Ignore CASCADE Buffers ; Off ; Off ;
-; Ignore GLOBAL Buffers ; Off ; Off ;
-; Ignore ROW GLOBAL Buffers ; Off ; Off ;
-; Ignore LCELL Buffers ; Off ; Off ;
-; Ignore SOFT Buffers ; On ; On ;
-; Limit AHDL Integers to 32 Bits ; Off ; Off ;
-; Optimization Technique ; Balanced ; Balanced ;
-; Carry Chain Length ; 70 ; 70 ;
-; Auto Carry Chains ; On ; On ;
-; Auto Open-Drain Pins ; On ; On ;
-; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
-; Auto ROM Replacement ; On ; On ;
-; Auto RAM Replacement ; On ; On ;
-; Auto DSP Block Replacement ; On ; On ;
-; Auto Shift Register Replacement ; Auto ; Auto ;
-; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
-; Auto Clock Enable Replacement ; On ; On ;
-; Strict RAM Replacement ; Off ; Off ;
-; Allow Synchronous Control Signals ; On ; On ;
-; Force Use of Synchronous Clear Signals ; Off ; Off ;
-; Auto Resource Sharing ; Off ; Off ;
-; Allow Any RAM Size For Recognition ; Off ; Off ;
-; Allow Any ROM Size For Recognition ; Off ; Off ;
-; Allow Any Shift Register Size For Recognition ; Off ; Off ;
-; Use LogicLock Constraints during Resource Balancing ; On ; On ;
-; Ignore translate_off and synthesis_off directives ; Off ; Off ;
-; Timing-Driven Synthesis ; On ; On ;
-; Report Parameter Settings ; On ; On ;
-; Report Source Assignments ; On ; On ;
-; Report Connectivity Checks ; On ; On ;
-; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
-; Synchronization Register Chain Length ; 3 ; 3 ;
-; PowerPlay Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
-; HDL message level ; Level2 ; Level2 ;
-; Suppress Register Optimization Related Messages ; Off ; Off ;
-; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
-; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
-; Clock MUX Protection ; On ; On ;
-; Auto Gated Clock Conversion ; Off ; Off ;
-; Block Design Naming ; Auto ; Auto ;
-; SDC constraint protection ; Off ; Off ;
-; Synthesis Effort ; Auto ; Auto ;
-; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
-; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
-; Analysis & Synthesis Message Level ; Medium ; Medium ;
-; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
-; Resource Aware Inference For Block RAM ; On ; On ;
-; Automatic Parallel Synthesis ; On ; On ;
-; Partial Reconfiguration Bitstream ID ; Off ; Off ;
-+---------------------------------------------------------------------------------+--------------------+--------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 24 ;
-; Maximum allowed ; 16 ;
-; ; ;
-; Average used ; 1.00 ;
-; Maximum used ; 16 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 0.1% ;
-; Processor 3 ; 0.0% ;
-; Processor 4 ; 0.0% ;
-; Processor 5 ; 0.0% ;
-; Processor 6 ; 0.0% ;
-; Processor 7 ; 0.0% ;
-; Processor 8 ; 0.0% ;
-; Processor 9 ; 0.0% ;
-; Processor 10 ; 0.0% ;
-; Processor 11 ; 0.0% ;
-; Processor 12 ; 0.0% ;
-; Processor 13 ; 0.0% ;
-; Processor 14 ; 0.0% ;
-; Processor 15 ; 0.0% ;
-; Processor 16 ; 0.0% ;
-+----------------------------+-------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+--------------------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------------------+---------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
-+--------------------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------------------+---------+
-; behavioural/razzle.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/razzle.sv ; ;
-; behavioural/ahb_interconnect.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv ; ;
-; behavioural/ahb_pixel_memory.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv ; ;
-; behavioural/ahb_ram.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/ahb_ram.sv ; ;
-; behavioural/ahb_switches.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/ahb_switches.sv ; ;
-; behavioural/arm_soc.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/arm_soc.sv ; ;
-; behavioural/CORTEXM0DS.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv ; ;
-; behavioural/cortexm0ds_logic.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv ; ;
-; behavioural/de1_soc_wrapper.sv ; yes ; User SystemVerilog HDL File ; /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv ; ;
-; behavioural/code.hex ; yes ; Auto-Found Hexadecimal (Intel-Format) File ; /home/ks6n19/Documents/project/behavioural/code.hex ; ;
-; altsyncram.tdf ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
-; stratix_ram_block.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
-; lpm_mux.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
-; lpm_decode.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
-; aglobal161.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/aglobal161.inc ; ;
-; a_rdenreg.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
-; altrom.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/altrom.inc ; ;
-; altram.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/altram.inc ; ;
-; altdpram.inc ; yes ; Megafunction ; /srv/intelFPGA/16.1/quartus/libraries/megafunctions/altdpram.inc ; ;
-; db/altsyncram_40j1.tdf ; yes ; Auto-Generated Megafunction ; /home/ks6n19/Documents/project/db/altsyncram_40j1.tdf ; ;
-; db/decode_3na.tdf ; yes ; Auto-Generated Megafunction ; /home/ks6n19/Documents/project/db/decode_3na.tdf ; ;
-; db/decode_s2a.tdf ; yes ; Auto-Generated Megafunction ; /home/ks6n19/Documents/project/db/decode_s2a.tdf ; ;
-; db/mux_jhb.tdf ; yes ; Auto-Generated Megafunction ; /home/ks6n19/Documents/project/db/mux_jhb.tdf ; ;
-; db/altsyncram_nms1.tdf ; yes ; Auto-Generated Megafunction ; /home/ks6n19/Documents/project/db/altsyncram_nms1.tdf ; ;
-; db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/ks6n19/Documents/project/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif ; ;
-+--------------------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------------------+---------+
-
-
-+--------------------------------------------------------------+
-; Analysis & Synthesis Resource Usage Summary ;
-+---------------------------------------------+----------------+
-; Resource ; Usage ;
-+---------------------------------------------+----------------+
-; Estimate of Logic utilization (ALMs needed) ; 2350 ;
-; ; ;
-; Combinational ALUT usage for logic ; 3446 ;
-; -- 7 input functions ; 30 ;
-; -- 6 input functions ; 1157 ;
-; -- 5 input functions ; 730 ;
-; -- 4 input functions ; 772 ;
-; -- <=3 input functions ; 757 ;
-; ; ;
-; Dedicated logic registers ; 1027 ;
-; ; ;
-; I/O pins ; 81 ;
-; Total MLAB memory bits ; 0 ;
-; Total block memory bits ; 2588672 ;
-; ; ;
-; Total DSP Blocks ; 0 ;
-; ; ;
-; Maximum fan-out node ; CLOCK_50~input ;
-; Maximum fan-out ; 1363 ;
-; Total fan-out ; 29258 ;
-; Average fan-out ; 5.89 ;
-+---------------------------------------------+----------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------+
-; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Block Memory Bits ; DSP Blocks ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
-+----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------+
-; |de1_soc_wrapper ; 3446 (27) ; 1027 (28) ; 2588672 ; 0 ; 81 ; 0 ; |de1_soc_wrapper ; de1_soc_wrapper ; work ;
-; |arm_soc:soc_inst| ; 3331 (0) ; 953 (0) ; 2588672 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst ; arm_soc ; work ;
-; |CORTEXM0DS:m0_1| ; 2968 (0) ; 822 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1 ; CORTEXM0DS ; work ;
-; |cortexm0ds_logic:u_logic| ; 2968 (2968) ; 822 (822) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic ; cortexm0ds_logic ; work ;
-; |ahb_interconnect:interconnect_1| ; 75 (75) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1 ; ahb_interconnect ; work ;
-; |ahb_pixel_memory:pix1| ; 225 (33) ; 83 (77) ; 2457600 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1 ; ahb_pixel_memory ; work ;
-; |altsyncram:memory_rtl_0| ; 192 (0) ; 6 (0) ; 2457600 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0 ; altsyncram ; work ;
-; |altsyncram_40j1:auto_generated| ; 192 (0) ; 6 (6) ; 2457600 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated ; altsyncram_40j1 ; work ;
-; |decode_3na:decode2| ; 44 (44) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_3na:decode2 ; decode_3na ; work ;
-; |decode_s2a:rden_decode_b| ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|decode_s2a:rden_decode_b ; decode_s2a ; work ;
-; |mux_jhb:mux3| ; 102 (102) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|mux_jhb:mux3 ; mux_jhb ; work ;
-; |ahb_ram:ram_1| ; 52 (52) ; 18 (18) ; 131072 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1 ; ahb_ram ; work ;
-; |altsyncram:memory_rtl_0| ; 0 (0) ; 0 (0) ; 131072 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0 ; altsyncram ; work ;
-; |altsyncram_nms1:auto_generated| ; 0 (0) ; 0 (0) ; 131072 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated ; altsyncram_nms1 ; work ;
-; |ahb_switches:switches_1| ; 11 (11) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_switches:switches_1 ; ahb_switches ; work ;
-; |razzle:raz_inst| ; 88 (88) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; |de1_soc_wrapper|razzle:raz_inst ; razzle ; work ;
-+----------------------------------------------+---------------------+---------------------------+-------------------+------------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------+------------------+--------------+
-Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis RAM Summary ;
-+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+--------------------------------------------------+
-; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
-+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+--------------------------------------------------+
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 307200 ; 8 ; 307200 ; 8 ; 2457600 ; None ;
-; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 4096 ; 32 ; 4096 ; 32 ; 131072 ; db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif ;
-+----------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+---------+--------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+------------------------------------------------------------------+----------------------------------------+
-; Register name ; Reason for Removal ;
-+------------------------------------------------------------------+----------------------------------------+
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][15] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][14] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][13] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][12] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][11] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[0][10] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][15] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][14] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][13] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][12] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][11] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|ahb_switches:switches_1|switch_store[1][10] ; Stuck at GND due to stuck port data_in ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zqb3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|E9c3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yvb3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qsb3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rnb3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W5c3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O2c3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gzb3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C7f3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q0f3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qnn2z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jje3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W8r2z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Etq2z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Q4h3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I6h3z4 ; Lost fanout ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Mvi2z4 ; Lost fanout ;
-; razzle:raz_inst|clock_enable ; Merged with tick_count[0] ;
-; Total Number of Removed Registers = 30 ; ;
-+------------------------------------------------------------------+----------------------------------------+
-
-
-+------------------------------------------------------+
-; General Register Statistics ;
-+----------------------------------------------+-------+
-; Statistic ; Value ;
-+----------------------------------------------+-------+
-; Total registers ; 1027 ;
-; Number of registers using Synchronous Clear ; 81 ;
-; Number of registers using Synchronous Load ; 11 ;
-; Number of registers using Asynchronous Clear ; 983 ;
-; Number of registers using Asynchronous Load ; 0 ;
-; Number of registers using Clock Enable ; 716 ;
-; Number of registers using Preset ; 0 ;
-+----------------------------------------------+-------+
-
-
-+----------------------------------------------------------------------------+
-; Inverted Register Statistics ;
-+------------------------------------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+------------------------------------------------------------------+---------+
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|O5t2z4 ; 123 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G0w2z4 ; 23 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|R1w2z4 ; 32 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H9i2z4 ; 61 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hyy2z4 ; 59 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qdj2z4 ; 28 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U2x2z4 ; 62 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zoy2z4 ; 40 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Nqy2z4 ; 44 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Xly2z4 ; 16 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Lny2z4 ; 21 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Omk2z4 ; 5 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J0l2z4 ; 5 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jux2z4 ; 5 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vvx2z4 ; 5 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Swy2z4 ; 67 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qem2z4 ; 44 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Bsy2z4 ; 51 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pty2z4 ; 45 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dvy2z4 ; 54 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Viy2z4 ; 13 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yzi2z4 ; 15 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rxl2z4 ; 14 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jky2z4 ; 22 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|W7z2z4 ; 8 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K9z2z4 ; 7 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I6z2z4 ; 10 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cyq2z4 ; 22 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Auk2z4 ; 11 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|K1z2z4 ; 11 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|C3z2z4 ; 13 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I2t2z4 ; 15 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G9w2z4 ; 7 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|G7x2z4 ; 5 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wai2z4 ; 16 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Igi2z4 ; 4 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Pdi2z4 ; 73 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Jw73z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|T1d3z4 ; 188 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|H3d3z4 ; 189 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Svk2z4 ; 205 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yaz2z4 ; 205 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Art2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|J0v2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kiq2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ql13z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gfq2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|I443z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zu23z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rd53z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Vgq2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hak2z4 ; 4 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Skh3z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Djh3z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|M1j2z4 ; 53 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hmh3z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wnh3z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|An63z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yx83z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fgm2z4 ; 228 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wzy2z4 ; 239 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rni2z4 ; 229 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Sjj2z4 ; 241 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|S8k2z4 ; 4 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qzq2z4 ; 19 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fzl2z4 ; 17 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|U4z2z4 ; 4 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qi03z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ug63z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Fwj2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Txj2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dq73z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ruj2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ukt2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Dtj2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Duu2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Wlz2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Cy33z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|L753z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kf13z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|To23z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Iwp2z4 ; 4 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Zcn2z4 ; 15 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Qz33z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Z853z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Yg13z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Hq23z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ii63z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Skm2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Gmm2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Unm2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rr73z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Imt2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ejm2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Rvu2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ek03z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Knz2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Kw63z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|E1r2z4 ; 2 ;
-; arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic|Ka93z4 ; 2 ;
-; Total number of inverted registers = 704* ; ;
-+------------------------------------------------------------------+---------+
-* Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Registers Added for RAM Pass-Through Logic ;
-+----------------------------------------------------------------+-----------------------------------------------------+
-; Register Name ; RAM Name ;
-+----------------------------------------------------------------+-----------------------------------------------------+
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[0] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[1] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[2] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[3] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[4] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[5] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[6] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[7] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[8] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[9] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[10] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[11] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[12] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[13] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[14] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[15] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[16] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[17] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[18] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[19] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[20] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[21] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[22] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[23] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[24] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[25] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[26] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[27] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[28] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[29] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[30] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[31] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[32] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[33] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[34] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[35] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[36] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[37] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[38] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[39] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[40] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[41] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[42] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[43] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[44] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[45] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0_bypass[46] ; arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0 ;
-+----------------------------------------------------------------+-----------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------+
-; Registers Packed Into Inferred Megafunctions ;
-+--------------------------------------------------------+---------------------------------------------+------+
-; Register Name ; Megafunction ; Type ;
-+--------------------------------------------------------+---------------------------------------------+------+
-; arm_soc:soc_inst|ahb_ram:ram_1|data_from_memory[0..31] ; arm_soc:soc_inst|ahb_ram:ram_1|memory_rtl_0 ; RAM ;
-+--------------------------------------------------------+---------------------------------------------+------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Multiplexer Restructuring Statistics (Restructuring Performed) ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------+
-; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------+
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|data_to_memory[3] ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|data_to_memory[9] ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|data_to_memory[18] ;
-; 3:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_ram:ram_1|data_to_memory[24] ;
-; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; No ; |de1_soc_wrapper|razzle:raz_inst|V_count ;
-; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1|HRDATA[13] ;
-; 5:1 ; 6 bits ; 18 LEs ; 18 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1|HRDATA[29] ;
-; 7:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1|HRDATA[8] ;
-; 7:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1|HRDATA[25] ;
-; 7:1 ; 8 bits ; 32 LEs ; 32 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1|HRDATA[19] ;
-; 10:1 ; 6 bits ; 36 LEs ; 36 LEs ; 0 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1|HRDATA[6] ;
-; 12:1 ; 2 bits ; 16 LEs ; 14 LEs ; 2 LEs ; No ; |de1_soc_wrapper|arm_soc:soc_inst|ahb_interconnect:interconnect_1|HRDATA[1] ;
-+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------+
-; Source assignments for arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0|altsyncram_40j1:auto_generated ;
-+---------------------------------+--------------------+------+--------------------------------------------------------+
-; Assignment ; Value ; From ; To ;
-+---------------------------------+--------------------+------+--------------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
-+---------------------------------+--------------------+------+--------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------+
-; Source assignments for arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0|altsyncram_nms1:auto_generated ;
-+---------------------------------+--------------------+------+------------------------------------------------+
-; Assignment ; Value ; From ; To ;
-+---------------------------------+--------------------+------+------------------------------------------------+
-; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
-+---------------------------------+--------------------+------+------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: arm_soc:soc_inst|ahb_interconnect:interconnect_1 ;
-+----------------+-------+----------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+----------------------------------------------------------------------+
-; num_slaves ; 3 ; Signed Integer ;
-+----------------+-------+----------------------------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: arm_soc:soc_inst|ahb_ram:ram_1 ;
-+----------------+-------+----------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+----------------------------------------------------+
-; MEMWIDTH ; 14 ; Signed Integer ;
-+----------------+-------+----------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+-----------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0 ;
-+------------------------------------+----------------------+-----------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+------------------------------------+----------------------+-----------------------------------------------------+
-; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-; WIDTH_BYTEENA ; 1 ; Untyped ;
-; OPERATION_MODE ; DUAL_PORT ; Untyped ;
-; WIDTH_A ; 8 ; Untyped ;
-; WIDTHAD_A ; 19 ; Untyped ;
-; NUMWORDS_A ; 307200 ; Untyped ;
-; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
-; ADDRESS_ACLR_A ; NONE ; Untyped ;
-; OUTDATA_ACLR_A ; NONE ; Untyped ;
-; WRCONTROL_ACLR_A ; NONE ; Untyped ;
-; INDATA_ACLR_A ; NONE ; Untyped ;
-; BYTEENA_ACLR_A ; NONE ; Untyped ;
-; WIDTH_B ; 8 ; Untyped ;
-; WIDTHAD_B ; 19 ; Untyped ;
-; NUMWORDS_B ; 307200 ; Untyped ;
-; INDATA_REG_B ; CLOCK1 ; Untyped ;
-; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
-; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
-; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
-; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
-; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
-; INDATA_ACLR_B ; NONE ; Untyped ;
-; WRCONTROL_ACLR_B ; NONE ; Untyped ;
-; ADDRESS_ACLR_B ; NONE ; Untyped ;
-; OUTDATA_ACLR_B ; NONE ; Untyped ;
-; RDCONTROL_ACLR_B ; NONE ; Untyped ;
-; BYTEENA_ACLR_B ; NONE ; Untyped ;
-; WIDTH_BYTEENA_A ; 1 ; Untyped ;
-; WIDTH_BYTEENA_B ; 1 ; Untyped ;
-; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
-; BYTE_SIZE ; 8 ; Untyped ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; INIT_FILE ; UNUSED ; Untyped ;
-; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
-; MAXIMUM_DEPTH ; 0 ; Untyped ;
-; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
-; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
-; ENABLE_ECC ; FALSE ; Untyped ;
-; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
-; WIDTH_ECCSTATUS ; 3 ; Untyped ;
-; DEVICE_FAMILY ; Cyclone V ; Untyped ;
-; CBXI_PARAMETER ; altsyncram_40j1 ; Untyped ;
-+------------------------------------+----------------------+-----------------------------------------------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+---------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0 ;
-+------------------------------------+--------------------------------------------------+-----------------+
-; Parameter Name ; Value ; Type ;
-+------------------------------------+--------------------------------------------------+-----------------+
-; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
-; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
-; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
-; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
-; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
-; WIDTH_BYTEENA ; 1 ; Untyped ;
-; OPERATION_MODE ; DUAL_PORT ; Untyped ;
-; WIDTH_A ; 32 ; Untyped ;
-; WIDTHAD_A ; 12 ; Untyped ;
-; NUMWORDS_A ; 4096 ; Untyped ;
-; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
-; ADDRESS_ACLR_A ; NONE ; Untyped ;
-; OUTDATA_ACLR_A ; NONE ; Untyped ;
-; WRCONTROL_ACLR_A ; NONE ; Untyped ;
-; INDATA_ACLR_A ; NONE ; Untyped ;
-; BYTEENA_ACLR_A ; NONE ; Untyped ;
-; WIDTH_B ; 32 ; Untyped ;
-; WIDTHAD_B ; 12 ; Untyped ;
-; NUMWORDS_B ; 4096 ; Untyped ;
-; INDATA_REG_B ; CLOCK1 ; Untyped ;
-; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
-; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
-; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
-; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
-; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
-; INDATA_ACLR_B ; NONE ; Untyped ;
-; WRCONTROL_ACLR_B ; NONE ; Untyped ;
-; ADDRESS_ACLR_B ; NONE ; Untyped ;
-; OUTDATA_ACLR_B ; NONE ; Untyped ;
-; RDCONTROL_ACLR_B ; NONE ; Untyped ;
-; BYTEENA_ACLR_B ; NONE ; Untyped ;
-; WIDTH_BYTEENA_A ; 1 ; Untyped ;
-; WIDTH_BYTEENA_B ; 1 ; Untyped ;
-; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
-; BYTE_SIZE ; 8 ; Untyped ;
-; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
-; INIT_FILE ; db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif ; Untyped ;
-; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
-; MAXIMUM_DEPTH ; 0 ; Untyped ;
-; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
-; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
-; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
-; ENABLE_ECC ; FALSE ; Untyped ;
-; ECC_PIPELINE_STAGE_ENABLED ; FALSE ; Untyped ;
-; WIDTH_ECCSTATUS ; 3 ; Untyped ;
-; DEVICE_FAMILY ; Cyclone V ; Untyped ;
-; CBXI_PARAMETER ; altsyncram_nms1 ; Untyped ;
-+------------------------------------+--------------------------------------------------+-----------------+
-Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-
-
-+------------------------------------------------------------------------------------------------------------+
-; altsyncram Parameter Settings by Entity Instance ;
-+-------------------------------------------+----------------------------------------------------------------+
-; Name ; Value ;
-+-------------------------------------------+----------------------------------------------------------------+
-; Number of entity instances ; 2 ;
-; Entity Instance ; arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 8 ;
-; -- NUMWORDS_A ; 307200 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 8 ;
-; -- NUMWORDS_B ; 307200 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE ;
-; Entity Instance ; arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 4096 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 4096 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-+-------------------------------------------+----------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "razzle:raz_inst" ;
-+-------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+
-; pixel ; Input ; Warning ; Input port expression (1 bits) is smaller than the input port (10 bits) it drives. Extra input bit(s) "pixel[9..1]" will be connected to GND. ;
-+-------+-------+----------+------------------------------------------------------------------------------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic" ;
-+---------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+---------------+--------+----------+-------------------------------------------------------------------------------------+
-; vis_r0_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r1_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r2_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r3_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r4_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r5_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r6_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r7_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r8_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r9_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r10_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r11_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r12_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_msp_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_psp_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_r14_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_pc_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_apsr_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_tbit_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_ipsr_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_control_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; vis_primask_o ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+---------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "arm_soc:soc_inst|CORTEXM0DS:m0_1" ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; HBURST ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; HMASTLOCK ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; HPROT ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; HRESP ; Input ; Info ; Stuck at GND ;
-; NMI ; Input ; Info ; Stuck at GND ;
-; IRQ ; Input ; Info ; Stuck at GND ;
-; TXEV ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; RXEV ; Input ; Info ; Stuck at GND ;
-; SYSRESETREQ ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; SLEEPING ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+----------------------------------------------------+
-; Port Connectivity Checks: "arm_soc:soc_inst" ;
-+------------------+-------+----------+--------------+
-; Port ; Type ; Severity ; Details ;
-+------------------+-------+----------+--------------+
-; Switches[15..10] ; Input ; Info ; Stuck at GND ;
-+------------------+-------+----------+--------------+
-
-
-+-----------------------------------------------------+
-; Post-Synthesis Netlist Statistics for Top Partition ;
-+-----------------------+-----------------------------+
-; Type ; Count ;
-+-----------------------+-----------------------------+
-; arriav_ff ; 1027 ;
-; CLR ; 237 ;
-; CLR SCLR ; 40 ;
-; ENA ; 10 ;
-; ENA CLR ; 665 ;
-; ENA CLR SCLR ; 30 ;
-; ENA CLR SCLR SLD ; 11 ;
-; plain ; 34 ;
-; arriav_lcell_comb ; 3451 ;
-; arith ; 192 ;
-; 0 data inputs ; 1 ;
-; 1 data inputs ; 146 ;
-; 2 data inputs ; 12 ;
-; 4 data inputs ; 2 ;
-; 5 data inputs ; 31 ;
-; extend ; 30 ;
-; 7 data inputs ; 30 ;
-; normal ; 3229 ;
-; 0 data inputs ; 2 ;
-; 1 data inputs ; 25 ;
-; 2 data inputs ; 275 ;
-; 3 data inputs ; 301 ;
-; 4 data inputs ; 770 ;
-; 5 data inputs ; 699 ;
-; 6 data inputs ; 1157 ;
-; boundary_port ; 81 ;
-; stratixv_ram_block ; 336 ;
-; ; ;
-; Max LUT depth ; 14.00 ;
-; Average LUT depth ; 9.63 ;
-+-----------------------+-----------------------------+
-
-
-+-------------------------------+
-; Elapsed Time Per Partition ;
-+----------------+--------------+
-; Partition Name ; Elapsed Time ;
-+----------------+--------------+
-; Top ; 00:00:16 ;
-+----------------+--------------+
-
-
-+-------------------------------+
-; Analysis & Synthesis Messages ;
-+-------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime Analysis & Synthesis
- Info: Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
- Info: Processing started: Thu Sep 17 17:54:54 2020
-Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Msc_proj -c de1_soc_wrapper
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 16 of the 24 processors detected
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/razzle.sv
- Info (12023): Found entity 1: razzle File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 8
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/ahb_interconnect.sv
- Info (12023): Found entity 1: ahb_interconnect File: /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv Line: 1
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/ahb_pixel_memory.sv
- Info (12023): Found entity 1: ahb_pixel_memory File: /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv Line: 23
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/ahb_ram.sv
- Info (12023): Found entity 1: ahb_ram File: /home/ks6n19/Documents/project/behavioural/ahb_ram.sv Line: 24
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/ahb_switches.sv
- Info (12023): Found entity 1: ahb_switches File: /home/ks6n19/Documents/project/behavioural/ahb_switches.sv Line: 32
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/arm_soc.sv
- Info (12023): Found entity 1: arm_soc File: /home/ks6n19/Documents/project/behavioural/arm_soc.sv Line: 4
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/CORTEXM0DS.sv
- Info (12023): Found entity 1: CORTEXM0DS File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 27
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/cortexm0ds_logic.sv
- Info (12023): Found entity 1: cortexm0ds_logic File: /home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv Line: 27
-Info (12021): Found 1 design units, including 1 entities, in source file behavioural/de1_soc_wrapper.sv
- Info (12023): Found entity 1: de1_soc_wrapper File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 8
-Warning (10236): Verilog HDL Implicit Net warning at razzle.sv(45): created implicit net for "Green_Data" File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 45
-Warning (10236): Verilog HDL Implicit Net warning at razzle.sv(46): created implicit net for "Blue_Data" File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 46
-Info (12127): Elaborating entity "de1_soc_wrapper" for the top level hierarchy
-Warning (10230): Verilog HDL assignment warning at de1_soc_wrapper.sv(75): truncated value with size 32 to match size of target (26) File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 75
-Warning (10230): Verilog HDL assignment warning at de1_soc_wrapper.sv(87): truncated value with size 8 to match size of target (7) File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 87
-Warning (10034): Output port "LEDR" at de1_soc_wrapper.sv(15) has no driver File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
-Info (12128): Elaborating entity "arm_soc" for hierarchy "arm_soc:soc_inst" File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 42
-Info (12128): Elaborating entity "CORTEXM0DS" for hierarchy "arm_soc:soc_inst|CORTEXM0DS:m0_1" File: /home/ks6n19/Documents/project/behavioural/arm_soc.sv Line: 56
-Warning (10036): Verilog HDL or VHDL warning at CORTEXM0DS.sv(76): object "cm0_msp" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 76
-Warning (10036): Verilog HDL or VHDL warning at CORTEXM0DS.sv(77): object "cm0_psp" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 77
-Warning (10036): Verilog HDL or VHDL warning at CORTEXM0DS.sv(79): object "cm0_pc" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 79
-Warning (10036): Verilog HDL or VHDL warning at CORTEXM0DS.sv(80): object "cm0_xpsr" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 80
-Warning (10036): Verilog HDL or VHDL warning at CORTEXM0DS.sv(81): object "cm0_control" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 81
-Warning (10036): Verilog HDL or VHDL warning at CORTEXM0DS.sv(82): object "cm0_primask" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 82
-Info (12128): Elaborating entity "cortexm0ds_logic" for hierarchy "arm_soc:soc_inst|CORTEXM0DS:m0_1|cortexm0ds_logic:u_logic" File: /home/ks6n19/Documents/project/behavioural/CORTEXM0DS.sv Line: 144
-Warning (10036): Verilog HDL or VHDL warning at cortexm0ds_logic.sv(1133): object "N4i2z4" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv Line: 1133
-Warning (10036): Verilog HDL or VHDL warning at cortexm0ds_logic.sv(1133): object "L5i2z4" assigned a value but never read File: /home/ks6n19/Documents/project/behavioural/cortexm0ds_logic.sv Line: 1133
-Info (12128): Elaborating entity "ahb_interconnect" for hierarchy "arm_soc:soc_inst|ahb_interconnect:interconnect_1" File: /home/ks6n19/Documents/project/behavioural/arm_soc.sv Line: 68
-Warning (10230): Verilog HDL assignment warning at ahb_interconnect.sv(39): truncated value with size 32 to match size of target (3) File: /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv Line: 39
-Warning (10230): Verilog HDL assignment warning at ahb_interconnect.sv(41): truncated value with size 32 to match size of target (3) File: /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv Line: 41
-Warning (10230): Verilog HDL assignment warning at ahb_interconnect.sv(43): truncated value with size 32 to match size of target (3) File: /home/ks6n19/Documents/project/behavioural/ahb_interconnect.sv Line: 43
-Info (12128): Elaborating entity "ahb_ram" for hierarchy "arm_soc:soc_inst|ahb_ram:ram_1" File: /home/ks6n19/Documents/project/behavioural/arm_soc.sv Line: 79
-Warning (10850): Verilog HDL warning at ahb_ram.sv(69): number of words (199) in memory file does not match the number of elements in the address range [0:4095] File: /home/ks6n19/Documents/project/behavioural/ahb_ram.sv Line: 69
-Info (12128): Elaborating entity "ahb_switches" for hierarchy "arm_soc:soc_inst|ahb_switches:switches_1" File: /home/ks6n19/Documents/project/behavioural/arm_soc.sv Line: 89
-Info (12128): Elaborating entity "ahb_pixel_memory" for hierarchy "arm_soc:soc_inst|ahb_pixel_memory:pix1" File: /home/ks6n19/Documents/project/behavioural/arm_soc.sv Line: 95
-Warning (10230): Verilog HDL assignment warning at ahb_pixel_memory.sv(94): truncated value with size 32 to match size of target (8) File: /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv Line: 94
-Warning (10230): Verilog HDL assignment warning at ahb_pixel_memory.sv(98): truncated value with size 32 to match size of target (19) File: /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv Line: 98
-Warning (10230): Verilog HDL assignment warning at ahb_pixel_memory.sv(102): truncated value with size 8 to match size of target (1) File: /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv Line: 102
-Info (12128): Elaborating entity "razzle" for hierarchy "razzle:raz_inst" File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 49
-Warning (10230): Verilog HDL assignment warning at razzle.sv(35): truncated value with size 32 to match size of target (8) File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 35
-Warning (10230): Verilog HDL assignment warning at razzle.sv(36): truncated value with size 32 to match size of target (8) File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 36
-Warning (10230): Verilog HDL assignment warning at razzle.sv(37): truncated value with size 32 to match size of target (8) File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 37
-Warning (10230): Verilog HDL assignment warning at razzle.sv(112): truncated value with size 32 to match size of target (10) File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 112
-Warning (10230): Verilog HDL assignment warning at razzle.sv(117): truncated value with size 32 to match size of target (11) File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 117
-Warning (10230): Verilog HDL assignment warning at razzle.sv(134): truncated value with size 32 to match size of target (11) File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 134
-Warning (10230): Verilog HDL assignment warning at razzle.sv(139): truncated value with size 32 to match size of target (9) File: /home/ks6n19/Documents/project/behavioural/razzle.sv Line: 139
-Warning (276020): Inferred RAM node "arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0" from synchronous design logic. Pass-through logic has been added to match the read-during-write behavior of the original design.
-Info (276014): Found 1 instances of uninferred RAM logic
- Info (276007): RAM logic "arm_soc:soc_inst|ahb_pixel_memory:pix1|memory" is uninferred due to asynchronous read logic File: /home/ks6n19/Documents/project/behavioural/ahb_pixel_memory.sv Line: 59
-Info (19000): Inferred 2 megafunctions from design logic
- Info (276029): Inferred altsyncram megafunction from the following design logic: "arm_soc:soc_inst|ahb_pixel_memory:pix1|memory_rtl_0"
- Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
- Info (286033): Parameter WIDTH_A set to 8
- Info (286033): Parameter WIDTHAD_A set to 19
- Info (286033): Parameter NUMWORDS_A set to 307200
- Info (286033): Parameter WIDTH_B set to 8
- Info (286033): Parameter WIDTHAD_B set to 19
- Info (286033): Parameter NUMWORDS_B set to 307200
- Info (286033): Parameter ADDRESS_ACLR_A set to NONE
- Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
- Info (286033): Parameter ADDRESS_ACLR_B set to NONE
- Info (286033): Parameter OUTDATA_ACLR_B set to NONE
- Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
- Info (286033): Parameter INDATA_ACLR_A set to NONE
- Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
- Info (276029): Inferred altsyncram megafunction from the following design logic: "arm_soc:soc_inst|ahb_ram:ram_1|memory_rtl_0"
- Info (286033): Parameter OPERATION_MODE set to DUAL_PORT
- Info (286033): Parameter WIDTH_A set to 32
- Info (286033): Parameter WIDTHAD_A set to 12
- Info (286033): Parameter NUMWORDS_A set to 4096
- Info (286033): Parameter WIDTH_B set to 32
- Info (286033): Parameter WIDTHAD_B set to 12
- Info (286033): Parameter NUMWORDS_B set to 4096
- Info (286033): Parameter ADDRESS_ACLR_A set to NONE
- Info (286033): Parameter OUTDATA_REG_B set to UNREGISTERED
- Info (286033): Parameter ADDRESS_ACLR_B set to NONE
- Info (286033): Parameter OUTDATA_ACLR_B set to NONE
- Info (286033): Parameter ADDRESS_REG_B set to CLOCK0
- Info (286033): Parameter INDATA_ACLR_A set to NONE
- Info (286033): Parameter WRCONTROL_ACLR_A set to NONE
- Info (286033): Parameter INIT_FILE set to db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif
- Info (286033): Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
-Info (12130): Elaborated megafunction instantiation "arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0"
-Info (12133): Instantiated megafunction "arm_soc:soc_inst|ahb_pixel_memory:pix1|altsyncram:memory_rtl_0" with the following parameter:
- Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
- Info (12134): Parameter "WIDTH_A" = "8"
- Info (12134): Parameter "WIDTHAD_A" = "19"
- Info (12134): Parameter "NUMWORDS_A" = "307200"
- Info (12134): Parameter "WIDTH_B" = "8"
- Info (12134): Parameter "WIDTHAD_B" = "19"
- Info (12134): Parameter "NUMWORDS_B" = "307200"
- Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
- Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
- Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
- Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
- Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
- Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
- Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
-Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_40j1.tdf
- Info (12023): Found entity 1: altsyncram_40j1 File: /home/ks6n19/Documents/project/db/altsyncram_40j1.tdf Line: 34
-Info (12021): Found 1 design units, including 1 entities, in source file db/decode_3na.tdf
- Info (12023): Found entity 1: decode_3na File: /home/ks6n19/Documents/project/db/decode_3na.tdf Line: 23
-Info (12021): Found 1 design units, including 1 entities, in source file db/decode_s2a.tdf
- Info (12023): Found entity 1: decode_s2a File: /home/ks6n19/Documents/project/db/decode_s2a.tdf Line: 23
-Info (12021): Found 1 design units, including 1 entities, in source file db/mux_jhb.tdf
- Info (12023): Found entity 1: mux_jhb File: /home/ks6n19/Documents/project/db/mux_jhb.tdf Line: 23
-Info (12130): Elaborated megafunction instantiation "arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0"
-Info (12133): Instantiated megafunction "arm_soc:soc_inst|ahb_ram:ram_1|altsyncram:memory_rtl_0" with the following parameter:
- Info (12134): Parameter "OPERATION_MODE" = "DUAL_PORT"
- Info (12134): Parameter "WIDTH_A" = "32"
- Info (12134): Parameter "WIDTHAD_A" = "12"
- Info (12134): Parameter "NUMWORDS_A" = "4096"
- Info (12134): Parameter "WIDTH_B" = "32"
- Info (12134): Parameter "WIDTHAD_B" = "12"
- Info (12134): Parameter "NUMWORDS_B" = "4096"
- Info (12134): Parameter "ADDRESS_ACLR_A" = "NONE"
- Info (12134): Parameter "OUTDATA_REG_B" = "UNREGISTERED"
- Info (12134): Parameter "ADDRESS_ACLR_B" = "NONE"
- Info (12134): Parameter "OUTDATA_ACLR_B" = "NONE"
- Info (12134): Parameter "ADDRESS_REG_B" = "CLOCK0"
- Info (12134): Parameter "INDATA_ACLR_A" = "NONE"
- Info (12134): Parameter "WRCONTROL_ACLR_A" = "NONE"
- Info (12134): Parameter "INIT_FILE" = "db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif"
- Info (12134): Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
-Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_nms1.tdf
- Info (12023): Found entity 1: altsyncram_nms1 File: /home/ks6n19/Documents/project/db/altsyncram_nms1.tdf Line: 28
-Warning (127007): Memory Initialization File or Hexadecimal (Intel-Format) File "/home/ks6n19/Documents/project/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif" contains "don't care" values -- overwriting them with 0s File: /srv/intelFPGA/16.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792
-Warning (127007): Memory Initialization File or Hexadecimal (Intel-Format) File "/home/ks6n19/Documents/project/db/de1_soc_wrapper.ram0_ahb_ram_41fd0858.hdl.mif" contains "don't care" values -- overwriting them with 0s File: /srv/intelFPGA/16.1/quartus/libraries/megafunctions/altsyncram.tdf Line: 792
-Warning (12241): 1 hierarchies have connectivity warnings - see the Connectivity Checks report folder
-Warning (13024): Output pins are stuck at VCC or GND
- Warning (13410): Pin "LEDR[0]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[1]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[2]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[3]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[4]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[5]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[6]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[7]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[8]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "LEDR[9]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 15
- Warning (13410): Pin "HEX0[0]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 16
- Warning (13410): Pin "HEX0[1]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 16
- Warning (13410): Pin "HEX0[5]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 16
- Warning (13410): Pin "HEX1[1]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 17
- Warning (13410): Pin "HEX1[2]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 17
- Warning (13410): Pin "HEX1[3]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 17
- Warning (13410): Pin "HEX1[4]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 17
- Warning (13410): Pin "HEX1[5]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 17
- Warning (13410): Pin "HEX1[6]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 17
- Warning (13410): Pin "HEX2[0]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 18
- Warning (13410): Pin "HEX2[1]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 18
- Warning (13410): Pin "HEX2[2]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 18
- Warning (13410): Pin "HEX2[3]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 18
- Warning (13410): Pin "HEX2[5]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 18
- Warning (13410): Pin "HEX3[0]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 19
- Warning (13410): Pin "HEX3[1]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 19
- Warning (13410): Pin "HEX3[2]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 19
- Warning (13410): Pin "HEX3[6]" is stuck at VCC File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 19
- Warning (13410): Pin "VGA_G[0]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_G[1]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_G[2]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_G[3]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_G[4]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_G[5]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_G[6]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_G[7]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[0]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[1]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[2]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[3]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[4]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[5]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[6]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
- Warning (13410): Pin "VGA_B[7]" is stuck at GND File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 20
-Info (286030): Timing-Driven Synthesis is running
-Info (17049): 17 registers lost all their fanouts during netlist optimizations.
-Info (144001): Generated suppressed messages file /home/ks6n19/Documents/project/output_files/de1_soc_wrapper.map.smsg
-Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
- Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
-Warning (21074): Design contains 1 input pin(s) that do not drive logic
- Warning (15610): No output dependent on input pin "KEY[3]" File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 13
-Info (21057): Implemented 4586 device resources after synthesis - the final resource count might be different
- Info (21058): Implemented 15 input pins
- Info (21059): Implemented 66 output pins
- Info (21061): Implemented 4169 logic cells
- Info (21064): Implemented 336 RAM segments
-Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 79 warnings
- Info: Peak virtual memory: 1480 megabytes
- Info: Processing ended: Thu Sep 17 17:55:26 2020
- Info: Elapsed time: 00:00:32
- Info: Total CPU time (on all processors): 00:00:45
-
-
-+------------------------------------------+
-; Analysis & Synthesis Suppressed Messages ;
-+------------------------------------------+
-The suppressed messages can be found in /home/ks6n19/Documents/project/output_files/de1_soc_wrapper.map.smsg.
-
-
diff --git a/output_files/de1_soc_wrapper.map.smsg b/output_files/de1_soc_wrapper.map.smsg
deleted file mode 100644
index 37644580e675ec693dde070c11c98fd7a69e39e6..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.map.smsg
+++ /dev/null
@@ -1 +0,0 @@
-Warning (10268): Verilog HDL information at de1_soc_wrapper.sv(64): always construct contains both blocking and non-blocking assignments File: /home/ks6n19/Documents/project/behavioural/de1_soc_wrapper.sv Line: 64
diff --git a/output_files/de1_soc_wrapper.map.summary b/output_files/de1_soc_wrapper.map.summary
deleted file mode 100644
index 9b0c00b9059b9ca0980d6cdba6f1804caea50e63..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.map.summary
+++ /dev/null
@@ -1,17 +0,0 @@
-Analysis & Synthesis Status : Successful - Thu Sep 17 17:55:25 2020
-Quartus Prime Version : 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-Revision Name : de1_soc_wrapper
-Top-level Entity Name : de1_soc_wrapper
-Family : Cyclone V
-Logic utilization (in ALMs) : N/A
-Total registers : 1027
-Total pins : 81
-Total virtual pins : 0
-Total block memory bits : 2,588,672
-Total DSP Blocks : 0
-Total HSSI RX PCSs : 0
-Total HSSI PMA RX Deserializers : 0
-Total HSSI TX PCSs : 0
-Total HSSI PMA TX Serializers : 0
-Total PLLs : 0
-Total DLLs : 0
diff --git a/output_files/de1_soc_wrapper.pin b/output_files/de1_soc_wrapper.pin
deleted file mode 100644
index 869a742d6022b552e368790de6e4a56f1a6900c4..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.pin
+++ /dev/null
@@ -1,977 +0,0 @@
- -- Copyright (C) 2017 Intel Corporation. All rights reserved.
- -- Your use of Intel Corporation's design tools, logic functions
- -- and other software and tools, and its AMPP partner logic
- -- functions, and any output files from any of the foregoing
- -- (including device programming or simulation files), and any
- -- associated documentation or information are expressly subject
- -- to the terms and conditions of the Intel Program License
- -- Subscription Agreement, the Intel Quartus Prime License Agreement,
- -- the Intel MegaCore Function License Agreement, or other
- -- applicable license agreement, including, without limitation,
- -- that your use is for the sole purpose of programming logic
- -- devices manufactured by Intel and sold by Intel or its
- -- authorized distributors. Please refer to the applicable
- -- agreement for further details.
- --
- -- This is a Quartus Prime output file. It is for reporting purposes only, and is
- -- not intended for use as a Quartus Prime input file. This file cannot be used
- -- to make Quartus Prime pin assignments - for instructions on how to make pin
- -- assignments, please see Quartus Prime help.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- NC : No Connect. This pin has no internal connection to the device.
- -- DNU : Do Not Use. This pin MUST NOT be connected.
- -- VCCPGM : Dedicated power pin for configuration, which MUST be connected to 1.8V, 2.5V, 3.0V or 3.3V depending on the requirements of the configuration device.
- -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.1V).
- -- VCCIO : Dedicated power pin, which MUST be connected to VCC
- -- of its bank.
- -- Bank 3A: 2.5V
- -- Bank 3B: 2.5V
- -- Bank 4A: 2.5V
- -- Bank 5A: 2.5V
- -- Bank 5B: 2.5V
- -- Bank 6B: 2.5V
- -- Bank 6A: 2.5V
- -- Bank 7A: 2.5V
- -- Bank 7B: 2.5V
- -- Bank 7C: 2.5V
- -- Bank 7D: 2.5V
- -- Bank 8A: 2.5V
- -- Bank 9A: Dedicated configuration pins only, no VCCIO required.
- -- RREF : External reference resistor for the quad, MUST be connected to
- -- GND via a 2k Ohm resistor.
- -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND.
- -- It can also be used to report unused dedicated pins. The connection
- -- on the board for unused dedicated pins depends on whether this will
- -- be used in a future design. One example is device migration. When
- -- using device migration, refer to the device pin-tables. If it is a
- -- GND pin in the pin table or if it will not be used in a future design
- -- for another purpose the it MUST be connected to GND. If it is an unused
- -- dedicated pin, then it can be connected to a valid signal on the board
- -- (low, high, or toggling) if that signal is required for a different
- -- revision of the design.
- -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins.
- -- This pin should be connected to GND. It may also be connected to a
- -- valid signal on the board (low, high, or toggling) if that signal
- -- is required for a different revision of the design.
- -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND
- -- or leave it unconnected.
- -- RESERVED : Unused I/O pin, which MUST be left unconnected.
- -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board.
- -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor.
- -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry.
- -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high.
- -- GXB_NC : Unused GXB Transmitter or dedicated clock output pin. This pin
- -- must not be connected.
- ---------------------------------------------------------------------------------
-
-
-
- ---------------------------------------------------------------------------------
- -- Pin directions (input, output or bidir) are based on device operating in user mode.
- ---------------------------------------------------------------------------------
-
-Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-CHIP "de1_soc_wrapper" ASSIGNED TO AN: 5CSEMA5F31C6
-
-Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
--------------------------------------------------------------------------------------------------------------
-GND : A2 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A4 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A6 : : : : 8A :
-VCCIO8A : A7 : power : : 2.5V : 8A :
-HEX2[6] : A8 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : A9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A11 : : : : 8A :
-GND : A12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A16 : : : : 7C :
-GND : A17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A21 : : : : 7B :
-GND : A22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : A25 : : : : 7A :
-GND : A26 : : : : 7A :
-GND : A27 : gnd : : : :
-HPS_TRST : A28 : : : : 7A :
-HPS_TMS : A29 : : : : 7A :
-GND : AA1 : gnd : : : :
-GND : AA2 : gnd : : : :
-GND : AA3 : gnd : : : :
-GND : AA4 : gnd : : : :
-VCC : AA5 : power : : 1.1V : :
-GND : AA6 : gnd : : : :
-DNU : AA7 : : : : :
-VCCA_FPLL : AA8 : power : : 2.5V : :
-GND : AA9 : gnd : : : :
-VCCPD3A : AA10 : power : : 2.5V : 3A :
-GND : AA11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA12 : : : : 3A :
-SW[9] : AA13 : input : 2.5 V : : 3B : N
-SW[0] : AA14 : input : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA16 : : : : 4A :
-VCCIO4A : AA17 : power : : 2.5V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA21 : : : : 4A :
-GND : AA22 : gnd : : : :
-VCCPGM : AA23 : power : : 1.8V/2.5V/3.0V/3.3V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA24 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA25 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA26 : : : : 5B :
-VCCIO5B : AA27 : power : : 2.5V : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA28 : : : : 5B :
-VREFB5BN0 : AA29 : power : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AA30 : : : : 5B :
-GND : AB1 : gnd : : : :
-GND : AB2 : gnd : : : :
-DNU : AB3 : : : : :
-DNU : AB4 : : : : :
-GND : AB5 : gnd : : : :
-VCCA_FPLL : AB6 : power : : 2.5V : :
-GND : AB7 : gnd : : : :
-nCSO, DATA4 : AB8 : : : : 3A :
-TDO : AB9 : output : : : 3A :
-VCCPGM : AB10 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX : AB11 : power : : 2.5V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB12 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB13 : : : : 3B :
-VCCIO3B : AB14 : power : : 2.5V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB15 : : : : 3B :
-VCC_AUX : AB16 : power : : 2.5V : :
-HEX0[6] : AB17 : output : 2.5 V : : 4A : N
-VCCPD3B4A : AB18 : power : : 2.5V : 3B, 4A :
-GND : AB19 : gnd : : : :
-VCCPD3B4A : AB20 : power : : 2.5V : 3B, 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB22 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB23 : : : : 5A :
-VCCIO5A : AB24 : power : : 2.5V : 5A :
-LEDR[4] : AB25 : output : 2.5 V : : 5A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB26 : : : : 5A :
-CLOCK_50 : AB27 : input : 2.5 V : : 5B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB28 : : : : 5B :
-GND : AB29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AB30 : : : : 5B :
-GND : AC1 : gnd : : : :
-GND : AC2 : gnd : : : :
-GND : AC3 : gnd : : : :
-GND : AC4 : gnd : : : :
-TCK : AC5 : input : : : 3A :
-GND : AC6 : gnd : : : :
-AS_DATA3, DATA3 : AC7 : : : : 3A :
-GND : AC8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC9 : : : : 3A :
-VCCPD3A : AC10 : power : : 2.5V : 3A :
-VCCIO3A : AC11 : power : : 2.5V : 3A :
-VGA_R[2] : AC12 : output : 2.5 V : : 3A : N
-VCCPD3B4A : AC13 : power : : 2.5V : 3B, 4A :
-SW[7] : AC14 : input : 2.5 V : : 3B : N
-VCCPD3B4A : AC15 : power : : 2.5V : 3B, 4A :
-GND : AC16 : gnd : : : :
-VCCPD3B4A : AC17 : power : : 2.5V : 3B, 4A :
-VGA_R[6] : AC18 : output : 2.5 V : : 4A : N
-VCCPD3B4A : AC19 : power : : 2.5V : 3B, 4A :
-VGA_R[3] : AC20 : output : 2.5 V : : 4A : N
-VCCIO4A : AC21 : power : : 2.5V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC23 : : : : 4A :
-VREFB5AN0 : AC24 : power : : : 5A :
-VGA_G[3] : AC25 : output : 2.5 V : : 5A : N
-GND : AC26 : gnd : : : :
-LEDR[1] : AC27 : output : 2.5 V : : 5A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC28 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AC29 : : : : 5B :
-LEDR[0] : AC30 : output : 2.5 V : : 5B : N
-GND : AD1 : gnd : : : :
-GND : AD2 : gnd : : : :
-DNU : AD3 : : : : :
-DNU : AD4 : : : : :
-GND : AD5 : gnd : : : :
-VREFB3AN0 : AD6 : power : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD7 : : : : 3A :
-VCCIO3A : AD8 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD11 : : : : 3A :
-VGA_R[4] : AD12 : output : 2.5 V : : 3A : N
-VCCIO3B : AD13 : power : : 2.5V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD14 : : : : 3B :
-DNU : AD15 : : : : :
-VCCPD3B4A : AD16 : power : : 2.5V : 3B, 4A :
-VGA_HS : AD17 : output : 2.5 V : : 4A : N
-VCCIO4A : AD18 : power : : 2.5V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD19 : : : : 4A :
-HEX0[1] : AD20 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD21 : : : : 4A :
-VCC_AUX : AD22 : power : : 2.5V : :
-GND : AD23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD25 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD26 : : : : 5A :
-HEX1[2] : AD27 : output : 2.5 V : : 5A : N
-VCCIO5A : AD28 : power : : 2.5V : 5A :
-LEDR[7] : AD29 : output : 2.5 V : : 5B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AD30 : : : : 5B :
-GND : AE1 : gnd : : : :
-GND : AE2 : gnd : : : :
-GND : AE3 : gnd : : : :
-GND : AE4 : gnd : : : :
-AS_DATA1, DATA1 : AE5 : : : : 3A :
-AS_DATA0, ASDO, DATA0 : AE6 : : : : 3A :
-VGA_G[7] : AE7 : output : 2.5 V : : 3A : N
-AS_DATA2, DATA2 : AE8 : : : : 3A :
-VGA_B[3] : AE9 : output : 2.5 V : : 3A : N
-GND : AE10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE11 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE12 : : : : 3A :
-SW[6] : AE13 : input : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE14 : : : : 3B :
-VCCIO3B : AE15 : power : : 2.5V : 3B :
-VGA_B[1] : AE16 : output : 2.5 V : : 4A : N
-KEY[0] : AE17 : input : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE19 : : : : 4A :
-GND : AE20 : gnd : : : :
-VCCPD3B4A : AE21 : power : : 2.5V : 3B, 4A :
-VGA_BLANK_N : AE22 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE24 : : : : 4A :
-VCCIO4A : AE25 : power : : 2.5V : 4A :
-VGA_B[0] : AE26 : output : 2.5 V : : 5A : N
-HEX0[0] : AE27 : output : 2.5 V : : 5A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE28 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AE29 : : : : 5B :
-VCCIO5B : AE30 : power : : 2.5V : 5B :
-GND : AF1 : gnd : : : :
-GND : AF2 : gnd : : : :
-GND : AF3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF4 : : : : 3A :
-VGA_G[5] : AF5 : output : 2.5 V : : 3A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF6 : : : : 3A :
-VCCIO3A : AF7 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF8 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF9 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF10 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF11 : : : : 3B :
-GND : AF12 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF14 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF15 : : : : 3B :
-KEY[1] : AF16 : input : 2.5 V : : 4A : N
-GND : AF17 : gnd : : : :
-HEX1[0] : AF18 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF19 : : : : 4A :
-HEX2[3] : AF20 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF21 : : : : 4A :
-VCCIO4A : AF22 : power : : 2.5V : 4A :
-HEX1[4] : AF23 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF24 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF26 : : : : 4A :
-GND : AF27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF28 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF29 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AF30 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG1 : : : : 3A :
-VGA_B[6] : AG2 : output : 2.5 V : : 3A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG3 : : : : 3A :
-VCCIO3A : AG4 : power : : 2.5V : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG5 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG6 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG7 : : : : 3A :
-LEDR[3] : AG8 : output : 2.5 V : : 3A : N
-GND : AG9 : gnd : : : :
-SW[3] : AG10 : input : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG13 : : : : 3B :
-GND : AG14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG16 : : : : 4A :
-VGA_B[7] : AG17 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG18 : : : : 4A :
-VCCIO4A : AG19 : power : : 2.5V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG21 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG22 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG23 : : : : 4A :
-GND : AG24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG25 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG26 : : : : 4A :
-VGA_VS : AG27 : output : 2.5 V : : 5A : N
-VGA_B[4] : AG28 : output : 2.5 V : : 5A : N
-VCCIO5A : AG29 : power : : 2.5V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AG30 : : : : 5A :
-GND : AH1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH2 : : : : 3A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH3 : : : : 3A :
-SW[5] : AH4 : input : 2.5 V : : 3A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH5 : : : : 3A :
-GND : AH6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH7 : : : : 3B :
-HEX0[2] : AH8 : output : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH9 : : : : 3B :
-HEX3[4] : AH10 : output : 2.5 V : : 3B : N
-GND : AH11 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH12 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH14 : : : : 3B :
-HEX3[5] : AH15 : output : 2.5 V : : 3B : N
-VCCIO4A : AH16 : power : : 2.5V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH18 : : : : 4A :
-HEX1[3] : AH19 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH20 : : : : 4A :
-GND : AH21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH22 : : : : 4A :
-HEX0[4] : AH23 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH24 : : : : 4A :
-LEDR[5] : AH25 : output : 2.5 V : : 4A : N
-VCCIO4A : AH26 : power : : 2.5V : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH27 : : : : 4A :
-KEY[3] : AH28 : input : 2.5 V : : 5A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AH29 : : : : 5A :
-HEX1[6] : AH30 : output : 2.5 V : : 5A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ1 : : : : 3A :
-SW[2] : AJ2 : input : 2.5 V : : 3A : N
-GND : AJ3 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ4 : : : : 3B :
-HEX3[0] : AJ5 : output : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ6 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ7 : : : : 3B :
-VCCIO3B : AJ8 : power : : 2.5V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ9 : : : : 3B :
-SW[4] : AJ10 : input : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ11 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ12 : : : : 3B :
-VCCIO3B : AJ13 : power : : 2.5V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ14 : : : : 3B :
-VREFB3BN0 : AJ15 : power : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ17 : : : : 4A :
-GND : AJ18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ19 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ20 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ21 : : : : 4A :
-HEX0[3] : AJ22 : output : 2.5 V : : 4A : N
-VCCIO4A : AJ23 : power : : 2.5V : 4A :
-VGA_R[5] : AJ24 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ25 : : : : 4A :
-VGA_R[7] : AJ26 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ27 : : : : 4A :
-GND : AJ28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AJ29 : : : : 5A :
-GND : AJ30 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK2 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK3 : : : : 3B :
-SW[8] : AK4 : input : 2.5 V : : 3B : N
-GND : AK5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK6 : : : : 3B :
-SW[1] : AK7 : input : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK8 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK9 : : : : 3B :
-VCCIO3B : AK10 : power : : 2.5V : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK11 : : : : 3B :
-HEX3[3] : AK12 : output : 2.5 V : : 3B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK13 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK14 : : : : 3B :
-GND : AK15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK16 : : : : 4A :
-VREFB4AN0 : AK17 : power : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK18 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK19 : : : : 4A :
-VCCIO4A : AK20 : power : : 2.5V : 4A :
-VGA_R[0] : AK21 : output : 2.5 V : : 4A : N
-VGA_CLK : AK22 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK23 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK24 : : : : 4A :
-GND : AK25 : gnd : : : :
-VGA_R[1] : AK26 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK27 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : AK28 : : : : 4A :
-VGA_G[4] : AK29 : output : 2.5 V : : 4A : N
-LEDR[8] : B1 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : B2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B3 : : : : 8A :
-VCCIO8A : B4 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B6 : : : : 8A :
-VGA_G[0] : B7 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : B8 : : : : 8A :
-GND : B9 : gnd : : : :
-VREFB8AN0 : B10 : power : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B13 : : : : 8A :
-GND : B14 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B16 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B18 : : : : 7B :
-GND : B19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B23 : : : : 7A :
-GND : B24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B26 : : : : 7A :
-HPS_TDI : B27 : : : : 7A :
-HPS_TDO : B28 : : : : 7A :
-GND : B29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : B30 : : : : 6A :
-GND : C1 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C2 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : : : : 8A :
-VGA_G[2] : C4 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : C5 : : : : 8A :
-GND : C6 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C10 : : : : 8A :
-VCCIO8A : C11 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C15 : : : : 7D :
-GND : C16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C20 : : : : 7B :
-GND : C21 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C24 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C25 : : : : 7A :
-GND : C26 : gnd : : : :
-HPS_nRST : C27 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : C30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D1 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D2 : : : : 8A :
-GND : D3 : gnd : : : :
-HEX0[5] : D4 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : D5 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D6 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D7 : : : : 8A :
-VCCIO8A : D8 : power : : 2.5V : 8A :
-VGA_B[2] : D9 : output : 2.5 V : : 8A : N
-HEX2[4] : D10 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : D11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D12 : : : : 8A :
-GND : D13 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D14 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D15 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D17 : : : : 7C :
-VCCIO7C_HPS : D18 : power : : 2.5V : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D21 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D22 : : : : 7A :
-GND : D23 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D24 : : : : 7A :
-HPS_CLK1 : D25 : : : : 7A :
-GND : D26 : : : : 7A :
-HPS_RZQ_0 : D27 : : : : 6A :
-VCCIO6A_HPS : D28 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : D30 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E1 : : : : 8A :
-HEX1[5] : E2 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E3 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E4 : : : : 8A :
-VCCIO8A : E5 : power : : 2.5V : 8A :
-LEDR[2] : E6 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : E7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E9 : : : : 8A :
-GND : E10 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E11 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E12 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E14 : : : : 7D :
-VCCIO7D_HPS : E15 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E19 : : : : 7B :
-VCCIO7B_HPS : E20 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E21 : : : : 7B :
-VREFB7A7B7C7DN0_HPS : E22 : power : : : 7A, 7B, 7C, 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E24 : : : : 7A :
-GND : E25 : gnd : : : :
-DNU : E26 : : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : E29 : : : : 6A :
-GND : E30 : gnd : : : :
-DNU : F1 : : : : :
-GND : F2 : gnd : : : :
-CONF_DONE : F3 : : : : 9A :
-nSTATUS : F4 : : : : 9A :
-GND : F5 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F6 : : : : 8A :
-GND : F7 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F8 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F9 : : : : 8A :
-VGA_B[5] : F10 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F11 : : : : 8A :
-VCCIO8A : F12 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F13 : : : : 8A :
-HEX2[0] : F14 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : F15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F16 : : : : 7D :
-GND : F17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F18 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F21 : : : : 7B :
-VCCIO7A_HPS : F22 : power : : 2.5V : 7A :
-HPS_nPOR : F23 : : : : 7A :
-HPS_PORSEL : F24 : : : : 7A :
-HPS_CLK2 : F25 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F26 : : : : 6A :
-GND : F27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : F30 : : : : 6A :
-GND : G1 : : : : :
-DNU : G2 : : : : :
-GND : G3 : gnd : : : :
-GND : G4 : gnd : : : :
-nCE : G5 : : : : 9A :
-MSEL2 : G6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G7 : : : : 8A :
-LEDR[9] : G8 : output : 2.5 V : : 8A : N
-VCCIO8A : G9 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G10 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G11 : : : : 8A :
-VGA_G[6] : G12 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : G13 : : : : 8A :
-VCCIO8A : G14 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G15 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G16 : : : : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G18 : : : : 7C :
-VCCIO7B_HPS : G19 : power : : 2.5V : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G20 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G21 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G22 : : : : 7A :
-VCCRSTCLK_HPS : G23 : : : : 7A :
-GND : G24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G28 : : : : 6A :
-VCCIO6A_HPS : G29 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : G30 : : : : 6A :
-GND : H1 : gnd : : : :
-GND : H2 : gnd : : : :
-DNU : H3 : : : : :
-DNU : H4 : : : : :
-GND : H5 : gnd : : : :
-VCCIO8A : H6 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H8 : : : : 8A :
-VCCBAT : H9 : power : : 1.2V : :
-VCC_AUX : H10 : power : : 2.5V : :
-GND : H11 : gnd : : : :
-LEDR[6] : H12 : output : 2.5 V : : 8A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : H13 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H14 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H15 : : : : 8A :
-VCCIO7D_HPS : H16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H17 : : : : 7C :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H18 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H19 : : : : 7B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H20 : : : : 7A :
-VCCIO7A_HPS : H21 : power : : 2.5V : 7A :
-HPS_TCK : H22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H23 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H25 : : : : 6A :
-VCCIO6A_HPS : H26 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : H30 : : : : 6A :
-GND : J1 : gnd : : : :
-GND : J2 : gnd : : : :
-GND : J3 : gnd : : : :
-GND : J4 : gnd : : : :
-nCONFIG : J5 : : : : 9A :
-GND : J6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J7 : : : : 8A :
-GND : J8 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J9 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J10 : : : : 8A :
-VCCPGM : J11 : power : : 1.8V/2.5V/3.0V/3.3V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J12 : : : : 8A :
-VCCIO8A : J13 : power : : 2.5V : 8A :
-HEX3[6] : J14 : output : 2.5 V : : 8A : N
-DNU : J15 : : : : :
-VCC_AUX : J16 : power : : 2.5V : :
-VCCPD7C_HPS : J17 : power : : 2.5V : 7C :
-GND : J18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J19 : : : : 7B :
-VCCRSTCLK_HPS : J20 : power : : 1.8V/2.5V/3.0V/3.3V : :
-VCC_AUX_SHARED : J21 : power : : 2.5V : :
-GND : J22 : : : : 7A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J27 : : : : 6A :
-GND : J28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : J30 : : : : 6A :
-GND : K1 : gnd : : : :
-GND : K2 : gnd : : : :
-DNU : K3 : : : : :
-DNU : K4 : : : : :
-GND : K5 : gnd : : : :
-MSEL1 : K6 : : : : 9A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K7 : : : : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K8 : : : : 8A :
-VCCA_FPLL : K9 : power : : 2.5V : :
-GND : K10 : gnd : : : :
-VCCPD8A : K11 : power : : 2.5V : 8A :
-HEX2[5] : K12 : output : 2.5 V : : 8A : N
-VCCPD8A : K13 : power : : 2.5V : 8A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K14 : : : : 8A :
-GND : K15 : gnd : : : :
-VCCPD7D_HPS : K16 : power : : 2.5V : 7D :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K17 : : : : 7B :
-VCCPD7B_HPS : K18 : power : : 2.5V : 7B :
-VCCPD7A_HPS : K19 : power : : 2.5V : 7A :
-GND : K20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K21 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K23 : : : : 6A :
-VCCIO6A_HPS : K24 : power : : 2.5V : 6A :
-GND : K25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : K29 : : : : 6A :
-VCCIO6A_HPS : K30 : power : : 2.5V : 6A :
-GND : L1 : gnd : : : :
-GND : L2 : gnd : : : :
-GND : L3 : gnd : : : :
-GND : L4 : gnd : : : :
-VCC : L5 : power : : 1.1V : :
-GND : L6 : gnd : : : :
-MSEL3 : L7 : : : : 9A :
-MSEL0 : L8 : : : : 9A :
-MSEL4 : L9 : : : : 9A :
-VCCPD8A : L10 : power : : 2.5V : 8A :
-GND : L11 : gnd : : : :
-VCCPD8A : L12 : power : : 2.5V : 8A :
-GND : L13 : gnd : : : :
-VCCPD8A : L14 : power : : 2.5V : 8A :
-GND : L15 : gnd : : : :
-VCC_HPS : L16 : power : : 1.1V : :
-GND : L17 : gnd : : : :
-VCC_HPS : L18 : power : : 1.1V : :
-GND : L19 : gnd : : : :
-VCC_HPS : L20 : power : : 1.1V : :
-VCCPLL_HPS : L21 : power : : 2.5V : :
-GND : L22 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L26 : : : : 6A :
-VCCIO6A_HPS : L27 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L28 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L29 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : L30 : : : : 6A :
-GND : M1 : gnd : : : :
-GND : M2 : gnd : : : :
-DNU : M3 : : : : :
-DNU : M4 : : : : :
-GND : M5 : gnd : : : :
-VCC : M6 : power : : 1.1V : :
-GND : M7 : gnd : : : :
-GND : M8 : gnd : : : :
-VCC : M9 : power : : 1.1V : :
-GND : M10 : gnd : : : :
-VCC : M11 : power : : 1.1V : :
-GND : M12 : gnd : : : :
-VCC : M13 : power : : 1.1V : :
-GND : M14 : gnd : : : :
-VCC_HPS : M15 : power : : 1.1V : :
-GND : M16 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M17 : : : : 7D :
-GND : M18 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M19 : : : : 6A :
-GND : M20 : gnd : : : :
-VCCPD6A6B_HPS : M21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M22 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M23 : : : : 6A :
-VCCIO6A_HPS : M24 : power : : 2.5V : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M25 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M26 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M27 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M28 : : : : 6A :
-GND : M29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : M30 : : : : 6A :
-GND : N1 : gnd : : : :
-GND : N2 : gnd : : : :
-GND : N3 : gnd : : : :
-GND : N4 : gnd : : : :
-VCC : N5 : power : : 1.1V : :
-GND : N6 : gnd : : : :
-VCCA_FPLL : N7 : power : : 2.5V : :
-GND : N8 : gnd : : : :
-GND : N9 : gnd : : : :
-VCC : N10 : power : : 1.1V : :
-GND : N11 : gnd : : : :
-VCC : N12 : power : : 1.1V : :
-GND : N13 : gnd : : : :
-VCC : N14 : power : : 1.1V : :
-GND : N15 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N16 : : : : 7D :
-GND : N17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N18 : : : : 6A :
-GND : N19 : gnd : : : :
-VCC_HPS : N20 : power : : 1.1V : :
-VCCIO6A_HPS : N21 : power : : 2.5V : 6A :
-VCCPD6A6B_HPS : N22 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N23 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N24 : : : : 6A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N25 : : : : 6A :
-GND : N26 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : N30 : : : : 6B :
-GND : P1 : gnd : : : :
-GND : P2 : gnd : : : :
-DNU : P3 : : : : :
-DNU : P4 : : : : :
-GND : P5 : gnd : : : :
-VCCA_FPLL : P6 : power : : 2.5V : :
-GND : P7 : gnd : : : :
-GND : P8 : gnd : : : :
-GND : P9 : gnd : : : :
-GND : P10 : gnd : : : :
-VCC : P11 : power : : 1.1V : :
-GND : P12 : gnd : : : :
-VCC : P13 : power : : 1.1V : :
-GND : P14 : gnd : : : :
-VCC_HPS : P15 : power : : 1.1V : :
-GND : P16 : gnd : : : :
-VCC_HPS : P17 : power : : 1.1V : :
-GND : P18 : gnd : : : :
-VCC_HPS : P19 : power : : 1.1V : :
-GND : P20 : gnd : : : :
-VCCPD6A6B_HPS : P21 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P22 : : : : 6B :
-VCCIO6B_HPS : P23 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P27 : : : : 6B :
-VCCIO6B_HPS : P28 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : P30 : : : : 6B :
-GND : R1 : gnd : : : :
-GND : R2 : gnd : : : :
-GND : R3 : gnd : : : :
-GND : R4 : gnd : : : :
-VCC : R5 : power : : 1.1V : :
-GND : R6 : gnd : : : :
-VCCA_FPLL : R7 : power : : 2.5V : :
-GND : R8 : gnd : : : :
-GND : R9 : gnd : : : :
-VCC : R10 : power : : 1.1V : :
-GND : R11 : gnd : : : :
-VCC : R12 : power : : 1.1V : :
-GND : R13 : gnd : : : :
-VCC : R14 : power : : 1.1V : :
-GND : R15 : gnd : : : :
-VCC_HPS : R16 : power : : 1.1V : :
-GND : R17 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R18 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R19 : : : : 6B :
-VCCPD6A6B_HPS : R20 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R21 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R22 : : : : 6B :
-VCCPD6A6B_HPS : R23 : power : : 2.5V : 6A, 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R24 : : : : 6B :
-VCCIO6B_HPS : R25 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : R29 : : : : 6B :
-GND : R30 : gnd : : : :
-GND : T1 : gnd : : : :
-GND : T2 : gnd : : : :
-DNU : T3 : : : : :
-DNU : T4 : : : : :
-GND : T5 : gnd : : : :
-VCC : T6 : power : : 1.1V : :
-GND : T7 : gnd : : : :
-GND : T8 : gnd : : : :
-GND : T9 : gnd : : : :
-GND : T10 : gnd : : : :
-VCC : T11 : power : : 1.1V : :
-GND : T12 : gnd : : : :
-VCC : T13 : power : : 1.1V : :
-GND : T14 : gnd : : : :
-GND : T15 : gnd : : : :
-GND : T16 : gnd : : : :
-VCC_HPS : T17 : power : : 1.1V : :
-GND : T18 : gnd : : : :
-VCC_HPS : T19 : power : : 1.1V : :
-GND : T20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T21 : : : : 6B :
-VCCIO6B_HPS : T22 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T23 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T24 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T26 : : : : 6B :
-GND : T27 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : T30 : : : : 6B :
-GND : U1 : gnd : : : :
-GND : U2 : gnd : : : :
-GND : U3 : gnd : : : :
-GND : U4 : gnd : : : :
-VCC : U5 : power : : 1.1V : :
-GND : U6 : gnd : : : :
-DCLK : U7 : : : : 3A :
-TDI : U8 : input : : : 3A :
-GND : U9 : gnd : : : :
-VCC : U10 : power : : 1.1V : :
-GND : U11 : gnd : : : :
-VCC : U12 : power : : 1.1V : :
-GND : U13 : gnd : : : :
-VCC : U14 : power : : 1.1V : :
-GND : U15 : gnd : : : :
-VCC_HPS : U16 : power : : 1.1V : :
-GND : U17 : gnd : : : :
-VCC_HPS : U18 : power : : 1.1V : :
-VCCIO6B_HPS : U19 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U20 : : : : 6B :
-VCC : U21 : power : : 1.1V : :
-GND : U22 : gnd : : : :
-VCCPD5B : U23 : power : : 2.5V : 5B :
-GND : U24 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U25 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U28 : : : : 6B :
-GND : U29 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : U30 : : : : 6B :
-GND : V1 : gnd : : : :
-GND : V2 : gnd : : : :
-DNU : V3 : : : : :
-DNU : V4 : : : : :
-GND : V5 : gnd : : : :
-VCCA_FPLL : V6 : power : : 2.5V : :
-GND : V7 : gnd : : : :
-VCCA_FPLL : V8 : power : : 2.5V : :
-TMS : V9 : input : : : 3A :
-GND : V10 : gnd : : : :
-VCC : V11 : power : : 1.1V : :
-GND : V12 : gnd : : : :
-VCC : V13 : power : : 1.1V : :
-GND : V14 : gnd : : : :
-VCC : V15 : power : : 1.1V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V17 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V18 : : : : 4A :
-GND : V19 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V20 : : : : 6B :
-GND : V21 : gnd : : : :
-VCCPD5A : V22 : power : : 2.5V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V23 : : : : 5A :
-VCCPD5A : V24 : power : : 2.5V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V25 : : : : 5B :
-VCCIO6B_HPS : V26 : power : : 2.5V : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V27 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : V30 : : : : 6B :
-GND : W1 : gnd : : : :
-GND : W2 : gnd : : : :
-GND : W3 : gnd : : : :
-GND : W4 : gnd : : : :
-VCC : W5 : power : : 1.1V : :
-GND : W6 : gnd : : : :
-GND : W7 : gnd : : : :
-GND : W8 : gnd : : : :
-GND : W9 : gnd : : : :
-VCC : W10 : power : : 1.1V : :
-GND : W11 : gnd : : : :
-VCC : W12 : power : : 1.1V : :
-GND : W13 : gnd : : : :
-VCC : W14 : power : : 1.1V : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W15 : : : : 3B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W16 : : : : 4A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W17 : : : : 4A :
-GND : W18 : gnd : : : :
-HEX3[1] : W19 : output : 2.5 V : : 4A : N
-HEX1[1] : W20 : output : 2.5 V : : 5A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : W21 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W22 : : : : 5A :
-VCCIO5A : W23 : power : : 2.5V : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W24 : : : : 5A :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W25 : : : : 5B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W26 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W27 : : : : 6B :
-GND : W28 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W29 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : W30 : : : : 6B :
-GND : Y1 : gnd : : : :
-GND : Y2 : gnd : : : :
-DNU : Y3 : : : : :
-DNU : Y4 : : : : :
-GND : Y5 : gnd : : : :
-VCC : Y6 : power : : 1.1V : :
-GND : Y7 : gnd : : : :
-GND : Y8 : gnd : : : :
-VCC : Y9 : power : : 1.1V : :
-GND : Y10 : gnd : : : :
-VCC : Y11 : power : : 1.1V : :
-GND : Y12 : gnd : : : :
-VCC : Y13 : power : : 1.1V : :
-GND : Y14 : gnd : : : :
-GND : Y15 : gnd : : : :
-VGA_G[1] : Y16 : output : 2.5 V : : 3B : N
-HEX3[2] : Y17 : output : 2.5 V : : 4A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y18 : : : : 4A :
-HEX2[1] : Y19 : output : 2.5 V : : 4A : N
-GND : Y20 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y21 : : : : 5A :
-VCCA_FPLL : Y22 : power : : 2.5V : :
-HEX2[2] : Y23 : output : 2.5 V : : 5A : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y24 : : : : 5A :
-GND : Y25 : gnd : : : :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y26 : : : : 5B :
-KEY[2] : Y27 : input : 2.5 V : : 5B : N
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y28 : : : : 6B :
-RESERVED_INPUT_WITH_WEAK_PULLUP : Y29 : : : : 6B :
-GND : Y30 : gnd : : : :
diff --git a/output_files/de1_soc_wrapper.sld b/output_files/de1_soc_wrapper.sld
deleted file mode 100644
index f7d3ed7cc6abd95c50005b31855c0eec845cbeed..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.sld
+++ /dev/null
@@ -1 +0,0 @@
-<sld_project_info/>
diff --git a/output_files/de1_soc_wrapper.sof b/output_files/de1_soc_wrapper.sof
deleted file mode 100644
index 705fd37d9b68be69354ac514d49f119a1ec1fd1b..0000000000000000000000000000000000000000
Binary files a/output_files/de1_soc_wrapper.sof and /dev/null differ
diff --git a/output_files/de1_soc_wrapper.sta.rpt b/output_files/de1_soc_wrapper.sta.rpt
deleted file mode 100644
index 10483905b55b5515984b9702559e4d1d1f54b371..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.sta.rpt
+++ /dev/null
@@ -1,1006 +0,0 @@
-TimeQuest Timing Analyzer report for de1_soc_wrapper
-Thu Sep 17 17:59:07 2020
-Quartus Prime Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. TimeQuest Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Slow 1100mV 85C Model Fmax Summary
- 6. Timing Closure Recommendations
- 7. Slow 1100mV 85C Model Setup Summary
- 8. Slow 1100mV 85C Model Hold Summary
- 9. Slow 1100mV 85C Model Recovery Summary
- 10. Slow 1100mV 85C Model Removal Summary
- 11. Slow 1100mV 85C Model Minimum Pulse Width Summary
- 12. Slow 1100mV 85C Model Metastability Summary
- 13. Slow 1100mV 0C Model Fmax Summary
- 14. Slow 1100mV 0C Model Setup Summary
- 15. Slow 1100mV 0C Model Hold Summary
- 16. Slow 1100mV 0C Model Recovery Summary
- 17. Slow 1100mV 0C Model Removal Summary
- 18. Slow 1100mV 0C Model Minimum Pulse Width Summary
- 19. Slow 1100mV 0C Model Metastability Summary
- 20. Fast 1100mV 85C Model Setup Summary
- 21. Fast 1100mV 85C Model Hold Summary
- 22. Fast 1100mV 85C Model Recovery Summary
- 23. Fast 1100mV 85C Model Removal Summary
- 24. Fast 1100mV 85C Model Minimum Pulse Width Summary
- 25. Fast 1100mV 85C Model Metastability Summary
- 26. Fast 1100mV 0C Model Setup Summary
- 27. Fast 1100mV 0C Model Hold Summary
- 28. Fast 1100mV 0C Model Recovery Summary
- 29. Fast 1100mV 0C Model Removal Summary
- 30. Fast 1100mV 0C Model Minimum Pulse Width Summary
- 31. Fast 1100mV 0C Model Metastability Summary
- 32. Multicorner Timing Analysis Summary
- 33. Board Trace Model Assignments
- 34. Input Transition Times
- 35. Signal Integrity Metrics (Slow 1100mv 0c Model)
- 36. Signal Integrity Metrics (Slow 1100mv 85c Model)
- 37. Signal Integrity Metrics (Fast 1100mv 0c Model)
- 38. Signal Integrity Metrics (Fast 1100mv 85c Model)
- 39. Setup Transfers
- 40. Hold Transfers
- 41. Report TCCS
- 42. Report RSKM
- 43. Unconstrained Paths Summary
- 44. Clock Status Summary
- 45. Unconstrained Input Ports
- 46. Unconstrained Output Ports
- 47. Unconstrained Input Ports
- 48. Unconstrained Output Ports
- 49. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 2017 Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Intel Program License
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel MegaCore Function License Agreement, or other
-applicable license agreement, including, without limitation,
-that your use is for the sole purpose of programming logic
-devices manufactured by Intel and sold by Intel or its
-authorized distributors. Please refer to the applicable
-agreement for further details.
-
-
-
-+---------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary ;
-+-----------------------+---------------------------------------------------------+
-; Quartus Prime Version ; Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition ;
-; Timing Analyzer ; TimeQuest ;
-; Revision Name ; de1_soc_wrapper ;
-; Device Family ; Cyclone V ;
-; Device Name ; 5CSEMA5F31C6 ;
-; Timing Models ; Final ;
-; Delay Model ; Combined ;
-; Rise/Fall Delays ; Enabled ;
-+-----------------------+---------------------------------------------------------+
-
-
-+------------------------------------------+
-; Parallel Compilation ;
-+----------------------------+-------------+
-; Processors ; Number ;
-+----------------------------+-------------+
-; Number detected on machine ; 24 ;
-; Maximum allowed ; 16 ;
-; ; ;
-; Average used ; 3.95 ;
-; Maximum used ; 16 ;
-; ; ;
-; Usage by Processor ; % Time Used ;
-; Processor 1 ; 100.0% ;
-; Processor 2 ; 41.4% ;
-; Processor 3 ; 41.0% ;
-; Processor 4 ; 40.9% ;
-; Processor 5 ; 14.3% ;
-; Processor 6 ; 14.3% ;
-; Processor 7 ; 14.3% ;
-; Processor 8 ; 14.3% ;
-; Processor 9 ; 14.3% ;
-; Processor 10 ; 14.3% ;
-; Processor 11 ; 14.3% ;
-; Processor 12 ; 14.3% ;
-; Processor 13 ; 14.3% ;
-; Processor 14 ; 14.3% ;
-; Processor 15 ; 14.3% ;
-; Processor 16 ; 14.3% ;
-+----------------------------+-------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-; CLOCK_50 ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK_50 } ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+--------------+
-
-
-+-------------------------------------------------+
-; Slow 1100mV 85C Model Fmax Summary ;
-+-----------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 74.06 MHz ; 74.06 MHz ; CLOCK_50 ; ;
-+-----------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-----------------------------------
-; Timing Closure Recommendations ;
-----------------------------------
-HTML report is unavailable in plain text report export.
-
-
-+-------------------------------------+
-; Slow 1100mV 85C Model Setup Summary ;
-+----------+---------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+---------+----------------+
-; CLOCK_50 ; -12.502 ; -113780.122 ;
-+----------+---------+----------------+
-
-
-+------------------------------------+
-; Slow 1100mV 85C Model Hold Summary ;
-+----------+-------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+-----------------+
-; CLOCK_50 ; 0.357 ; 0.000 ;
-+----------+-------+-----------------+
-
-
-------------------------------------------
-; Slow 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Slow 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Slow 1100mV 85C Model Minimum Pulse Width Summary ;
-+----------+--------+-------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+-------------------------------+
-; CLOCK_50 ; -2.636 ; -46900.052 ;
-+----------+--------+-------------------------------+
-
-
------------------------------------------------
-; Slow 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+-------------------------------------------------+
-; Slow 1100mV 0C Model Fmax Summary ;
-+-----------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 74.89 MHz ; 74.89 MHz ; CLOCK_50 ; ;
-+-----------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+------------------------------------+
-; Slow 1100mV 0C Model Setup Summary ;
-+----------+---------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+---------+---------------+
-; CLOCK_50 ; -12.353 ; -110175.196 ;
-+----------+---------+---------------+
-
-
-+-----------------------------------+
-; Slow 1100mV 0C Model Hold Summary ;
-+----------+-------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+----------------+
-; CLOCK_50 ; 0.353 ; 0.000 ;
-+----------+-------+----------------+
-
-
------------------------------------------
-; Slow 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Slow 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Slow 1100mV 0C Model Minimum Pulse Width Summary ;
-+----------+--------+------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+------------------------------+
-; CLOCK_50 ; -2.636 ; -46925.515 ;
-+----------+--------+------------------------------+
-
-
-----------------------------------------------
-; Slow 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-------------------------------------+
-; Fast 1100mV 85C Model Setup Summary ;
-+----------+--------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+-----------------+
-; CLOCK_50 ; -7.389 ; -65801.349 ;
-+----------+--------+-----------------+
-
-
-+------------------------------------+
-; Fast 1100mV 85C Model Hold Summary ;
-+----------+-------+-----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+-----------------+
-; CLOCK_50 ; 0.179 ; 0.000 ;
-+----------+-------+-----------------+
-
-
-------------------------------------------
-; Fast 1100mV 85C Model Recovery Summary ;
-------------------------------------------
-No paths to report.
-
-
------------------------------------------
-; Fast 1100mV 85C Model Removal Summary ;
------------------------------------------
-No paths to report.
-
-
-+---------------------------------------------------+
-; Fast 1100mV 85C Model Minimum Pulse Width Summary ;
-+----------+--------+-------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+-------------------------------+
-; CLOCK_50 ; -2.636 ; -46009.813 ;
-+----------+--------+-------------------------------+
-
-
------------------------------------------------
-; Fast 1100mV 85C Model Metastability Summary ;
------------------------------------------------
-No synchronizer chains to report.
-
-
-+------------------------------------+
-; Fast 1100mV 0C Model Setup Summary ;
-+----------+--------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+----------------+
-; CLOCK_50 ; -6.467 ; -56821.323 ;
-+----------+--------+----------------+
-
-
-+-----------------------------------+
-; Fast 1100mV 0C Model Hold Summary ;
-+----------+-------+----------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+-------+----------------+
-; CLOCK_50 ; 0.171 ; 0.000 ;
-+----------+-------+----------------+
-
-
------------------------------------------
-; Fast 1100mV 0C Model Recovery Summary ;
------------------------------------------
-No paths to report.
-
-
-----------------------------------------
-; Fast 1100mV 0C Model Removal Summary ;
-----------------------------------------
-No paths to report.
-
-
-+--------------------------------------------------+
-; Fast 1100mV 0C Model Minimum Pulse Width Summary ;
-+----------+--------+------------------------------+
-; Clock ; Slack ; End Point TNS ;
-+----------+--------+------------------------------+
-; CLOCK_50 ; -2.636 ; -46024.842 ;
-+----------+--------+------------------------------+
-
-
-----------------------------------------------
-; Fast 1100mV 0C Model Metastability Summary ;
-----------------------------------------------
-No synchronizer chains to report.
-
-
-+-----------------------------------------------------------------------------------+
-; Multicorner Timing Analysis Summary ;
-+------------------+-------------+-------+----------+---------+---------------------+
-; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
-+------------------+-------------+-------+----------+---------+---------------------+
-; Worst-case Slack ; -12.502 ; 0.171 ; N/A ; N/A ; -2.636 ;
-; CLOCK_50 ; -12.502 ; 0.171 ; N/A ; N/A ; -2.636 ;
-; Design-wide TNS ; -113780.122 ; 0.0 ; 0.0 ; 0.0 ; -46925.515 ;
-; CLOCK_50 ; -113780.122 ; 0.000 ; N/A ; N/A ; -46925.515 ;
-+------------------+-------------+-------+----------+---------+---------------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Board Trace Model Assignments ;
-+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
-+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-; LEDR[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[8] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; LEDR[9] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX0[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX1[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX2[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; HEX3[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_R[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_G[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_B[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_HS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_VS ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_CLK ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-; VGA_BLANK_N ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ; n/a ; n/a ; n/a ;
-+-------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
-
-
-+-------------------------------------------------------------+
-; Input Transition Times ;
-+----------+--------------+-----------------+-----------------+
-; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
-+----------+--------------+-----------------+-----------------+
-; KEY[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; CLOCK_50 ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[7] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; KEY[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[2] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[9] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[1] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[4] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[3] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[5] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[8] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[0] ; 2.5 V ; 2000 ps ; 2000 ps ;
-; SW[6] ; 2.5 V ; 2000 ps ; 2000 ps ;
-+----------+--------------+-----------------+-----------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 0c Model) ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; HEX3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; HEX3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; HEX3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; HEX3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_R[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_R[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; VGA_R[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; VGA_R[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_R[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_R[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; VGA_R[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_G[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_G[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_G[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_G[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_G[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_G[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_G[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-; VGA_G[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_B[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_B[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_B[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_B[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_B[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_B[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_B[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_B[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_HS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ; 2.32 V ; 3.07e-07 V ; 2.36 V ; -0.0231 V ; 0.14 V ; 0.089 V ; 4.52e-10 s ; 4.35e-10 s ; No ; Yes ;
-; VGA_VS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0568 V ; 0.173 V ; 0.113 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ; 2.32 V ; 3.52e-07 V ; 2.42 V ; -0.0557 V ; 0.175 V ; 0.114 V ; 4.5e-10 s ; 4.35e-10 s ; No ; No ;
-; VGA_BLANK_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ; 2.32 V ; 3.6e-07 V ; 2.41 V ; -0.0463 V ; 0.201 V ; 0.131 V ; 4.61e-10 s ; 4.53e-10 s ; No ; Yes ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Slow 1100mv 85c Model) ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; HEX3[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; HEX3[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX3[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; HEX3[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; HEX3[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_R[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_R[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_R[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; VGA_R[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; VGA_R[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_R[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_R[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; VGA_R[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_G[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_G[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_G[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_G[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_G[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_G[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_G[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-; VGA_G[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_B[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_B[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_B[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_B[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_B[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_B[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_B[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_B[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_HS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ; 2.32 V ; 3.49e-05 V ; 2.34 V ; -0.0118 V ; 0.182 V ; 0.051 V ; 4.81e-10 s ; 4.83e-10 s ; Yes ; Yes ;
-; VGA_VS ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.0374 V ; 0.189 V ; 0.158 V ; 4.66e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_CLK ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ; 2.32 V ; 3.88e-05 V ; 2.39 V ; -0.037 V ; 0.188 V ; 0.158 V ; 4.67e-10 s ; 4.67e-10 s ; No ; Yes ;
-; VGA_BLANK_N ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ; 2.32 V ; 3.96e-05 V ; 2.38 V ; -0.0306 V ; 0.23 V ; 0.206 V ; 4.83e-10 s ; 5.01e-10 s ; No ; Yes ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 0c Model) ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; HEX3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; HEX3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX3[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; HEX3[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; HEX3[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_R[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_R[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; VGA_R[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; VGA_R[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_R[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_R[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; VGA_R[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_G[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_G[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_G[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_G[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_G[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_G[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_G[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-; VGA_G[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_B[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_B[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_B[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_B[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_B[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_B[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_B[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_B[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_HS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ; 2.75 V ; 3.54e-06 V ; 2.81 V ; -0.0578 V ; 0.303 V ; 0.28 V ; 2.93e-10 s ; 3.01e-10 s ; No ; No ;
-; VGA_VS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.119 V ; 0.326 V ; 0.298 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_CLK ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ; 2.75 V ; 4.14e-06 V ; 2.91 V ; -0.121 V ; 0.326 V ; 0.297 V ; 2.74e-10 s ; 2.8e-10 s ; No ; No ;
-; VGA_BLANK_N ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ; 2.75 V ; 4.25e-06 V ; 2.9 V ; -0.107 V ; 0.378 V ; 0.16 V ; 2.87e-10 s ; 4.28e-10 s ; No ; No ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Signal Integrity Metrics (Fast 1100mv 85c Model) ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-; LEDR[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; LEDR[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; LEDR[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; LEDR[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; LEDR[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; LEDR[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; LEDR[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; LEDR[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; LEDR[8] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; LEDR[9] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; HEX0[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX0[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX0[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX0[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX0[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX0[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX0[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; HEX1[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; HEX1[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX1[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX1[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX1[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX1[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX1[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX2[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; HEX2[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX2[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX2[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX2[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; HEX2[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX2[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX3[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX3[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; HEX3[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; HEX3[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX3[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; HEX3[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; HEX3[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_R[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_R[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_R[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; VGA_R[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; VGA_R[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_R[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_R[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; VGA_R[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_G[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_G[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_G[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_G[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_G[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_G[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_G[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-; VGA_G[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_B[0] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_B[1] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_B[2] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_B[3] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_B[4] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_B[5] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_B[6] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_B[7] ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_HS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ; 2.75 V ; 0.000213 V ; 2.79 V ; -0.0324 V ; 0.139 V ; 0.119 V ; 4.42e-10 s ; 4.33e-10 s ; No ; Yes ;
-; VGA_VS ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0805 V ; 0.358 V ; 0.156 V ; 3.01e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_CLK ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ; 2.75 V ; 0.000242 V ; 2.86 V ; -0.0814 V ; 0.36 V ; 0.156 V ; 3e-10 s ; 4.34e-10 s ; No ; No ;
-; VGA_BLANK_N ; 2.5 V ; 0 s ; 0 s ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ; 2.75 V ; 0.000247 V ; 2.85 V ; -0.0711 V ; 0.204 V ; 0.181 V ; 4.55e-10 s ; 4.49e-10 s ; No ; No ;
-+-------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
-
-
-+--------------------------------------------------------------------+
-; Setup Transfers ;
-+------------+----------+-----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+-----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 715488812 ; 0 ; 0 ; 0 ;
-+------------+----------+-----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+--------------------------------------------------------------------+
-; Hold Transfers ;
-+------------+----------+-----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+-----------+----------+----------+----------+
-; CLOCK_50 ; CLOCK_50 ; 715488812 ; 0 ; 0 ; 0 ;
-+------------+----------+-----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No non-DPA dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths Summary ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 13 ; 13 ;
-; Unconstrained Input Port Paths ; 1366 ; 1366 ;
-; Unconstrained Output Ports ; 22 ; 22 ;
-; Unconstrained Output Port Paths ; 367 ; 367 ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------------+
-; Clock Status Summary ;
-+----------+----------+------+-------------+
-; Target ; Clock ; Type ; Status ;
-+----------+----------+------+-------------+
-; CLOCK_50 ; CLOCK_50 ; Base ; Constrained ;
-+----------+----------+------+-------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_BLANK_N ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_CLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_HS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_VS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+---------------------------------------------------------------------------------------------------+
-; Unconstrained Input Ports ;
-+------------+--------------------------------------------------------------------------------------+
-; Input Port ; Comment ;
-+------------+--------------------------------------------------------------------------------------+
-; KEY[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; KEY[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[0] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[1] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[2] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[3] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[4] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[5] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[6] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[7] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[8] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; SW[9] ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+------------+--------------------------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------+
-; Unconstrained Output Ports ;
-+-------------+---------------------------------------------------------------------------------------+
-; Output Port ; Comment ;
-+-------------+---------------------------------------------------------------------------------------+
-; HEX0[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX0[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX1[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX2[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; HEX3[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_BLANK_N ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_CLK ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_HS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[0] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[1] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[2] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[3] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[4] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[5] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[6] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_R[7] ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-; VGA_VS ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
-+-------------+---------------------------------------------------------------------------------------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus Prime TimeQuest Timing Analyzer
- Info: Version 16.1.2 Build 203 01/18/2017 SJ Standard Edition
- Info: Processing started: Thu Sep 17 17:58:50 2020
-Info: Command: quartus_sta Msc_proj -c de1_soc_wrapper
-Info: qsta_default_script.tcl version: #1
-Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
-Info (20030): Parallel compilation is enabled and will use 16 of the 24 processors detected
-Info (21077): Low junction temperature is 0 degrees C
-Info (21077): High junction temperature is 85 degrees C
-Critical Warning (332012): Synopsys Design Constraints File file not found: 'de1_soc_wrapper.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info (332105): Deriving Clocks
- Info (332105): create_clock -period 1.000 -name CLOCK_50 CLOCK_50
-Info (332143): No user constrained clock uncertainty found in the design. Calling "derive_clock_uncertainty"
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
-Info: Analyzing Slow 1100mV 85C Model
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -12.502
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -12.502 -113780.122 CLOCK_50
-Info (332146): Worst-case hold slack is 0.357
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.357 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -2.636
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -2.636 -46900.052 CLOCK_50
-Info: Analyzing Slow 1100mV 0C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -12.353
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -12.353 -110175.196 CLOCK_50
-Info (332146): Worst-case hold slack is 0.353
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.353 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -2.636
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -2.636 -46925.515 CLOCK_50
-Info: Analyzing Fast 1100mV 85C Model
-Info (334003): Started post-fitting delay annotation
-Info (334004): Delay annotation completed successfully
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -7.389
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -7.389 -65801.349 CLOCK_50
-Info (332146): Worst-case hold slack is 0.179
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.179 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -2.636
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -2.636 -46009.813 CLOCK_50
-Info: Analyzing Fast 1100mV 0C Model
-Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
-Critical Warning (332148): Timing requirements not met
- Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
-Info (332146): Worst-case setup slack is -6.467
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -6.467 -56821.323 CLOCK_50
-Info (332146): Worst-case hold slack is 0.171
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): 0.171 0.000 CLOCK_50
-Info (332140): No Recovery paths to report
-Info (332140): No Removal paths to report
-Info (332146): Worst-case minimum pulse width slack is -2.636
- Info (332119): Slack End Point TNS Clock
- Info (332119): ========= =================== =====================
- Info (332119): -2.636 -46024.842 CLOCK_50
-Info (332102): Design is not fully constrained for setup requirements
-Info (332102): Design is not fully constrained for hold requirements
-Info: Quartus Prime TimeQuest Timing Analyzer was successful. 0 errors, 6 warnings
- Info: Peak virtual memory: 1746 megabytes
- Info: Processing ended: Thu Sep 17 17:59:07 2020
- Info: Elapsed time: 00:00:17
- Info: Total CPU time (on all processors): 00:00:51
-
-
diff --git a/output_files/de1_soc_wrapper.sta.summary b/output_files/de1_soc_wrapper.sta.summary
deleted file mode 100644
index 2360109764ab7596aaa56e988d1e40fa2ec73eec..0000000000000000000000000000000000000000
--- a/output_files/de1_soc_wrapper.sta.summary
+++ /dev/null
@@ -1,53 +0,0 @@
-------------------------------------------------------------
-TimeQuest Timing Analyzer Summary
-------------------------------------------------------------
-
-Type : Slow 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -12.502
-TNS : -113780.122
-
-Type : Slow 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.357
-TNS : 0.000
-
-Type : Slow 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -2.636
-TNS : -46900.052
-
-Type : Slow 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -12.353
-TNS : -110175.196
-
-Type : Slow 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.353
-TNS : 0.000
-
-Type : Slow 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -2.636
-TNS : -46925.515
-
-Type : Fast 1100mV 85C Model Setup 'CLOCK_50'
-Slack : -7.389
-TNS : -65801.349
-
-Type : Fast 1100mV 85C Model Hold 'CLOCK_50'
-Slack : 0.179
-TNS : 0.000
-
-Type : Fast 1100mV 85C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -2.636
-TNS : -46009.813
-
-Type : Fast 1100mV 0C Model Setup 'CLOCK_50'
-Slack : -6.467
-TNS : -56821.323
-
-Type : Fast 1100mV 0C Model Hold 'CLOCK_50'
-Slack : 0.171
-TNS : 0.000
-
-Type : Fast 1100mV 0C Model Minimum Pulse Width 'CLOCK_50'
-Slack : -2.636
-TNS : -46024.842
-
-------------------------------------------------------------