diff --git a/behavioural/ahb_out.sv b/behavioural/ahb_out.sv
index ba29b698ee2eedb62ea35c0a2dde9fcc359b72b7..e3b9de85321369681fb41b2be65bc210af2ccd6f 100644
--- a/behavioural/ahb_out.sv
+++ b/behavioural/ahb_out.sv
@@ -43,14 +43,14 @@ module ahb_out(
//Non-AHB signals
input logic [9:0] pixel_x ,
input logic [8:0] pixel_y ,
-
+ input logic [10:0] x1, x2, y1, y2, x3, y3,
// AHB Signals from Slave to Master
output logic [31:0] HRDATA,
output HREADYOUT,
//Non-AHB Signals
- output logic pixel,
- output logic [8:0] x1, x2, y1, y2, x3, y3
+ output logic pixel
+
);
timeunit 1ns;
@@ -155,27 +155,14 @@ memory = '{307200{0}};
pixel <= memory[pixel_address] ;
end
+// Read not allowed
-
- //read
- always_comb
- if ( ! read_enable )
- // (output of zero when not enabled for read is not necessary
- // but may help with debugging)
- HRDATA = '0;
- else
- case (word_address)
- 0 : HRDATA = { 23'd0, x1 };
- 1 : HRDATA = { 23'd0, y1 };
- 2 : HRDATA = { 23'd0, x2 };
- 3 : HRDATA = { 23'd0, y2 };
- 4 : HRDATA = { 23'd0, x3 };
- 5 : HRDATA = { 23'd0, y3 };
- // unused address - returns zero
- default : HRDATA = '0;
- endcase
- //Transfer Response
- assign HREADYOUT = '1; //Single cycle Write & Read. Zero Wait state operations
+assign HRDATA = '0; // read is not permitted mode
+
+
+
+//Transfer Response
+ assign HREADYOUT = '1; //Single Cycle Wait State for Write
endmodule
diff --git a/behavioural/ahb_pixel_memory.sv b/behavioural/ahb_pixel_memory.sv
deleted file mode 100644
index 37920028904aafe72ca046ffa0c5431e614291a8..0000000000000000000000000000000000000000
--- a/behavioural/ahb_pixel_memory.sv
+++ /dev/null
@@ -1,122 +0,0 @@
-// Example code for an M0 AHBLite System
-// Iain McNally
-// ECS, University of Soutampton
-//
-// This module is an AHB-Lite Slave containing a RAM
-// Since this loads a program it is for FPGA use only
-//
-// Number of addressable locations : 307200
-// Size of each addressable location : bits_per_pixel bits
-// Supported transfer sizes : Word
-// Alignment of base address : Word aligned
-//
-
-// Memory is synchronous which should suit block memory types
-// Read takes 1 cycle
-// Write takes 2 cycles (single wait state)
-//
-// Note this is not the most efficient design but works with
-// Xilinx and Altera(Intel) FPGAs
-//
-
-
-`define STRINGIFY(x) `"x`"
-
-module ahb_pixel_memory #(
- parameter MEMWIDTH = 22
-)(
- //AHBLITE INTERFACE
-
- //Slave Select Signal
- input HSEL,
- //Global Signals
- input HCLK,
- input HRESETn,
- //Address, Control & Write Data
- input HREADY,
- input [31:0] HADDR,
- input [1:0] HTRANS,
- input HWRITE,
- input [2:0] HSIZE,
- input [31:0] HWDATA,
- // Transfer Response & Read Data
- output HREADYOUT,
- output [31:0] HRDATA
-
-);
-
-timeunit 1ns;
-timeprecision 100ps;
-
-localparam No_Transfer = 2'b0;
-localparam bits_per_pixel = 1;
-
-// Memory Array
- logic [bits_per_pixel-1:0] memory[0:307199];
-
-// other declarations
- logic [31:0] data_from_memory, data_to_memory;
- logic write_cycle, read_cycle;
- logic [MEMWIDTH-2:0] word_address, saved_word_address;
- logic [3:0] byte_select;
-
-
-//Generate the control signals here:
-
- always_ff @(posedge HCLK, negedge HRESETn)
- if (! HRESETn )
- begin
- write_cycle <= '0;
- read_cycle <= '0;
- saved_word_address <= '0;
- end
- else
- begin
- if ( HREADY && HSEL && (HTRANS != No_Transfer) )
- begin
- write_cycle <= HWRITE;
- read_cycle <= ! HWRITE;
- saved_word_address <= HADDR[MEMWIDTH:2];
- end
- else
- begin
- write_cycle <= '0;
- read_cycle <= '0;
- end
- end
-
- // the word address is available in the address phase
- always_comb
- if ( HREADY && HSEL && (HTRANS != No_Transfer) && ! write_cycle )
- word_address = HADDR[MEMWIDTH:2];
- else
- word_address = saved_word_address;
-
-// model the memory here:
-
- // read and write are both synchronous
- // the code uses a simple format to ensure easy identification of RAM for synthesis
- always_ff @(posedge HCLK)
- begin
- data_from_memory <= memory[word_address];
- if ( write_cycle )
- memory[word_address] <= data_to_memory;
- end
-
-// deal with byte access here:
-
- always_comb
- if (write_cycle)
- data_to_memory= HWDATA;
- else
- data_to_memory = '0;
-
- // (output of zero when not enabled for read is not necessary but may help with debugging)
- assign HRDATA = read_cycle ? data_from_memory : '0;
-
-
-//Transfer Response
- assign HREADYOUT = ! write_cycle; //Single Cycle Wait State for Write
-
-
-endmodule
diff --git a/behavioural/arm_soc.sv b/behavioural/arm_soc.sv
index daef1056a08a3406269e6e505f9ed279c132b924..c3e0a6833de159d0e57970d859180948c8075f2c 100644
--- a/behavioural/arm_soc.sv
+++ b/behavioural/arm_soc.sv
@@ -4,10 +4,12 @@
module arm_soc(
input HCLK, HRESETn,
-
+ input logic [9:0] pixel_x ,
+ input logic [8:0] pixel_y,
+ input logic [10:0] x1, x2, y1, y2, x3, y3,
input [15:0] Switches,
input [1:0] Buttons,
- output logic [8:0] x1, x2, y1, y2,
+ output logic pixel,
output LOCKUP
);
@@ -92,7 +94,7 @@ timeprecision 100ps;
.HSEL(HSEL_DOUT),
.HRDATA(HRDATA_DOUT), .HREADYOUT(HREADYOUT_DOUT),
- .x1(x1), .x2(x2), .y1(y1), .y2(y2)
+ .x1(x1), .x2(x2), .y1(y1), .y2(y2), .x3(x3), .y3(y3) .pixel_x(pixel_x), .pixel_y(pixel_y) , .pixel(pixel)
);
diff --git a/behavioural/de1_soc_wrapper.sv b/behavioural/de1_soc_wrapper.sv
index 16ab7467ad945ae618c32c03cdc26a7d81f840a2..d9eaacf7674c0fca2200573882443558df5577f9 100644
--- a/behavioural/de1_soc_wrapper.sv
+++ b/behavioural/de1_soc_wrapper.sv
@@ -29,20 +29,24 @@ timeprecision 100ps;
localparam heartbeat_count_msb = 25;
- wire HCLK, HRESETn, LOCKUP, DataValid;
+ wire HCLK, HRESETn, LOCKUP;
wire [1:0] Buttons;
wire [15:0] Switches;
- logic[8:0] x1,x2,y1,y2 ;
+ logic pixel ;
+ logic [9:0] pixel_x ;
+ logic [8:0] pixel_y ;
assign Switches = { 6'd0, SW }; // DE1-SoC has just 10 switches
assign Buttons = ~KEY[1:0];
- arm_soc soc_inst(.HCLK, .HRESETn, .x1(x1), .x2(x2), .y1(y1), .y2(y2), .Switches, .Buttons, .LOCKUP);
- razzle raz_inst (.CLOCK_50(CLOCK_50),
- .KEY(KEY),
- .x1(x1), .x2(x2), .y1(y1), .y2(y2),
+ arm_soc soc_inst(.HCLK, .HRESETn, .Switches, .pixel(pixel), .pixel_x(pixel_x), .pixel_y(pixel_y), .Buttons, .LOCKUP);
+
+ razzle raz_inst (
+ .CLOCK_50(CLOCK_50), .KEY(KEY), .pixel_x(pixel_x), .pixel_y(pixel_y), .pixel(pixel),
.VGA_R(VGA_R),.VGA_G(VGA_G),.VGA_B(VGA_B),
- .VGA_HS(VGA_HS),.VGA_VS(VGA_VS), .VGA_CLK(VGA_CLK), .VGA_BLANK_N(VGA_BLANK_N));
+ .VGA_HS(VGA_HS),.VGA_VS(VGA_VS), .VGA_CLK(VGA_CLK),
+ .VGA_BLANK_N(VGA_BLANK_N)
+ );
// Drive HRESETn directly from active low CPU KEY[2] button
@@ -77,12 +81,7 @@ timeprecision 100ps;
assign HEX0 = (heartbeat) ? 7'b0100011 : '1;
// HEX1 is DataValid
- assign HEX1 = ~{!DataValid&&!LOCKUP,
- !DataValid&&!LOCKUP,
- !DataValid&&!LOCKUP,
- !LOCKUP,
- !LOCKUP,
- !DataValid&&!LOCKUP };
+ assign HEX1 = ~{!LOCKUP};
// running shows as r on HEX2
assign HEX2 = ~{1'b0,running,1'b0,running, 4'b000 };
diff --git a/behavioural/razzle.sv b/behavioural/razzle.sv
index a3391fca83e476dd6d8a26c0fbddcaa9e48f76c6..491c6684680849a984ff711133dd72eb85bee726 100644
--- a/behavioural/razzle.sv
+++ b/behavioural/razzle.sv
@@ -10,10 +10,10 @@ module razzle (
input logic CLOCK_50,
input logic [3:0] KEY,
input logic pixel,
- output logic [7:0] VGA_R,VGA_G,VGA_B,
+ output logic [7:0] VGA_R,VGA_G,VGA_B,
output logic [9:0] pixel_x,
output logic [8:0] pixel_y ,
- output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
+ output logic VGA_HS,VGA_VS, VGA_CLK, VGA_BLANK_N);
// Video Display Signals
logic [10:0] H_count,V_count;