makefile

#-----------------------------------------------------------------------------
# SoCDebug FPGA Flow Makefile 
# - Used for Packaging Up Socket IP
# A joint work commissioned on behalf of SoC Labs, under Arm Academic Access license.
#
# Contributors
#
# David Mapstone (d.a.mapstone@soton.ac.uk)
#
# Copyright (C) 2021-3, SoC Labs (www.soclabs.org)
#-----------------------------------------------------------------------------

IMPLEMENTATION_DIR   ?= $(SOCLABS_PROJECT_DIR)/imp/fpga
TEMP_RTL_SOCKET_DIR  := $(IMPLEMENTATION_DIR)/socket

RTL_SOCKET_DIR       := $(SOCLABS_SOCDEBUG_TECH_DIR)/socket/vivado_lib

package_adp_control:
	@echo Packaging Uart To AXI Master
	@mkdir -p $(TEMP_RTL_SOCKET_DIR)
	@cp -r $(RTL_SOCKET_DIR)/ADPcontrol_1.0 $(TEMP_RTL_SOCKET_DIR)/ADPcontrol_1.0
	
package_axi_stream_io:
	@echo Packaging Uart To AXI Master
	@mkdir -p $(TEMP_RTL_SOCKET_DIR)
	@cp -r $(RTL_SOCKET_DIR)/axi_stream_io_1.0 $(TEMP_RTL_SOCKET_DIR)/axi_stream_io_1.0
	
package_ft1248_to_stream:
	@echo Packaging FT1248 to AXI Stream
	@mkdir -p $(TEMP_RTL_SOCKET_DIR)
	@cp -r $(RTL_SOCKET_DIR)/ft1248x1_to_stream8_1.0 $(TEMP_RTL_SOCKET_DIR)/ft1248x1_to_stream8_1.0
	@cp -r $(RTL_SOCKET_DIR)/ft1248x1_to_axi_streamio_1.0 $(TEMP_RTL_SOCKET_DIR)/ft1248x1_to_axi_streamio_1.0
	
package_uart_to_axi:
	@echo Packaging Uart To AXI Master
	@mkdir -p $(TEMP_RTL_SOCKET_DIR)
	@cp -r $(RTL_SOCKET_DIR)/uart_to_AXI_master_1.0 $(TEMP_RTL_SOCKET_DIR)/uart_to_AXI_master_1.0

package_socket: clean_socket package_uart_to_axi package_ft1248_to_stream package_axi_stream_io package_adp_control

clean_socket:
	@echo Cleaning FPGA Implementation Socket Directory
	@rm -rf $(TEMP_RTL_SOCKET_DIR)