diff --git a/MSF/RTC/tb/rtc_tb.vhd b/MSF/RTC/tb/rtc_tb.vhd new file mode 100644 index 0000000000000000000000000000000000000000..e43813423f7e4a632316da65a7f403191fe30a23 --- /dev/null +++ b/MSF/RTC/tb/rtc_tb.vhd @@ -0,0 +1,97 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use std.textio.all; + +entity rtc_tb is +end entity rtc_tb; + +architecture behavioral of rtc_tb is + + --Module Ports-- + signal clk_crystal : std_logic := '0'; + signal rst : std_logic := '0'; + signal time_ready : std_logic := '0'; + + signal year_in : std_logic_vector (6 downto 0) := (others => '0'); + signal month_in : std_logic_vector (3 downto 0) := (others => '0'); + signal d_month_in : std_logic_vector (4 downto 0) := (others => '0'); + signal d_week_in : std_logic_vector (2 downto 0) := (others => '0'); + signal hour_in : std_logic_vector (4 downto 0) := (others => '0'); + signal minute_in : std_logic_vector (5 downto 0) := (others => '0'); + + signal hour_out : std_logic_vector (4 downto 0) := (others => '0'); + signal minute_out : std_logic_vector (5 downto 0) := (others => '0'); + signal second_out : std_logic_vector (5 downto 0) := (others => '0'); + + --Declare Component-- + component rtc is + port( + clk_crystal : in std_logic; + rst : in std_logic; + time_ready : in std_logic; + + year_in : in std_logic_vector (6 downto 0); + month_in : in std_logic_vector (3 downto 0); + d_month_in : in std_logic_vector (4 downto 0); + d_week_in : in std_logic_vector (2 downto 0); + hour_in : in std_logic_vector (4 downto 0); + minute_in : in std_logic_vector (5 downto 0); + + hour_out : out std_logic_vector (4 downto 0); + minute_out : out std_logic_vector (5 downto 0); + second_out : out std_logic_vector (5 downto 0) + ); + end component rtc; + + + begin + + CLOCK_CYCLE: process + begin + clk_crystal <= '0'; + wait for 50 us; + clk_crystal <= '1'; + wait for 50 us; + end process CLOCK_CYCLE; + + + DATA_INSERT: process + begin + wait for 10 ns; + rst <= '1'; + wait until rising_edge(clk_crystal); + wait for 10 ns; + rst <= '0'; + wait until rising_edge(clk_crystal); + year_in <= "0011000"; --2024 + month_in <= "1010"; --10 + d_month_in <= "11001"; --25th + d_week_in <= "101"; --Friday + hour_in <= "10000"; --16 + minute_in <= "011110"; --30 + wait until rising_edge(clk_crystal); + time_ready <= '1'; + wait; + end process DATA_INSERT; + + + + --Instance Component-- + RTC_0: component rtc + port map( + clk_crystal => clk_crystal, + rst => rst, + time_ready => time_ready, + year_in => year_in, + month_in => month_in, + d_month_in => d_month_in, + d_week_in => d_week_in, + hour_in => hour_in, + minute_in => minute_in, + hour_out => hour_out, + minute_out => minute_out, + second_out => second_out + ); + +end behavioral; \ No newline at end of file