From 1c70cd0556aa73e1ae2cf4b11d92351c14b1c743 Mon Sep 17 00:00:00 2001
From: Jack Driscoll <jd12g21@soton.ac.uk>
Date: Sat, 26 Oct 2024 13:05:42 +0000
Subject: [PATCH] includes all rtc ports, fast clock for fast simulation

---
 MSF/RTC/tb/rtc_tb.vhd | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/MSF/RTC/tb/rtc_tb.vhd b/MSF/RTC/tb/rtc_tb.vhd
index e438134..d66f16b 100644
--- a/MSF/RTC/tb/rtc_tb.vhd
+++ b/MSF/RTC/tb/rtc_tb.vhd
@@ -20,10 +20,15 @@ architecture behavioral of rtc_tb is
 	signal hour_in		: std_logic_vector (4 downto 0) := (others => '0');
 	signal minute_in	: std_logic_vector (5 downto 0) := (others => '0');
 
+	signal year_out		: std_logic_vector (6 downto 0) := (others => '0');
+	signal month_out	: std_logic_vector (3 downto 0) := (others => '0');
+	signal d_month_out	: std_logic_vector (4 downto 0) := (others => '0');
+	signal d_week_out	: std_logic_vector (2 downto 0) := (others => '0');
 	signal hour_out		: std_logic_vector (4 downto 0) := (others => '0');
 	signal minute_out	: std_logic_vector (5 downto 0) := (others => '0');
 	signal second_out	: std_logic_vector (5 downto 0) := (others => '0');
 	
+	
 	--Declare Component--
 	component rtc is
 		port(
@@ -38,6 +43,10 @@ architecture behavioral of rtc_tb is
 		hour_in		: in std_logic_vector (4 downto 0);
 		minute_in	: in std_logic_vector (5 downto 0);
 
+		year_out	: out std_logic_vector (6 downto 0);
+		month_out	: out std_logic_vector (3 downto 0);
+		d_month_out	: out std_logic_vector (4 downto 0);
+		d_week_out	: out std_logic_vector (2 downto 0);
 		hour_out	: out std_logic_vector (4 downto 0);
 		minute_out	: out std_logic_vector (5 downto 0);
 		second_out	: out std_logic_vector (5 downto 0)
@@ -50,18 +59,18 @@ architecture behavioral of rtc_tb is
 		CLOCK_CYCLE: process
 			begin
 				clk_crystal <= '0';
-				wait for 50 us;
+				wait for 10 ns;
 				clk_crystal <= '1';
-				wait for 50 us;
+				wait for 10 ns;
 		end process CLOCK_CYCLE;
 	
 		
 		DATA_INSERT: process
-			begin
-				wait for 10 ns;
+			begin 
+				wait for 5 ns;
 				rst <= '1';
 				wait until rising_edge(clk_crystal);
-				wait for 10 ns;
+				wait for 5 ns;
 				rst <= '0';
 				wait until rising_edge(clk_crystal);
 				year_in <= "0011000"; --2024
@@ -89,6 +98,10 @@ architecture behavioral of rtc_tb is
 			d_week_in => d_week_in,
 			hour_in => hour_in,
 			minute_in => minute_in,
+			year_out => year_out,
+			month_out => month_out,
+			d_month_out => d_month_out,
+			d_week_out => d_week_out,
 			hour_out => hour_out,
 			minute_out => minute_out,
 			second_out => second_out
-- 
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