design_import.tcl

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# File : Design Import Logic 
# Date : 22nd May 2022 
# Author : Srimanth Tenneti 
# Description : MMMC + Design Import 
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### Settting PG Nets 
set_db init_power_nets {VDD VDDIO VDDACC} 
set_db init_ground_nets {VSS VSSIO} 

### Processing MMMC 
read_mmmc nanosoc.mmmc 

# Set library paths 
# !! EDIT THIS TO YOUR PATHS IN YOUR ENVIRONMENT
set TECH_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/arm_tech/r2p0/lef/1p9m_6x2z/sc12_tech.lef
set BASE_LEF $::env(PHYS_IP)/arm/tsmc/cln65lp/sc12_base_rvt/r0p0/lef/sc12_cln65lp_base_rvt.lef

# !! THESE SHOULD BE CORRECT FOR ANY ENVIRONMENT AS THEY ARE GENERATED BY MAKEFILE
set RF_LEF $::env(SOCLABS_PROJECT_DIR)/memories/rf/rf_sp_hdf.lef
set ROM_LEF $::env(SOCLABS_PROJECT_DIR)/memories/bootrom/rom_via.lef

### Reading LEFs 
read_physical -lef [list ${TECH_LEF} ${BASE_LEF} ${RF_LEF} ${ROM_LEF}]

### Reading Netlist 
read_netlist $::env(SOCLABS_PROJECT_DIR)/imp/ASIC/nanosoc/netlist/nanosoc_chip_pads.vm

### Initializing the Design 
init_design

### Adjusting the GUI 
gui_fit 

ungroup u_nanosoc_chip_u_system

create_floorplan -site sc12_cln65lp -core_size 1500 1500 50 50 50 50 

read_power_intent -cpf nanosoc.cpf