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This repository instantiates Custom Accelerators, SoCLabs IP and Physical Libraries to create a custom SoC
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soclabs Arm Cortex-M0 based micro-controller design example(s)
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soclabs Arm Cortex-M0 based micro-controller design example(s)
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This Repository contains the RTL for the SLCore-M0, a SoC Labs Custom Wrapper around the Arm Cortex-M0 used in SoCs such as NanoSoC.
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This repository instantiates Custom Accelerators, SoCLabs IP and Physical Libraries to create a custom SoC
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Subsystem for basic cocoTB testing of an AXI system. Using an ARM NIC400, DMA350 and BP140.
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Minyong Li / Can
CERN Open Hardware Licence Version 2 - Weakly ReciprocalCan is a ChaCha20 cryptographic accelerator based on a No-Instruction-Set Computer (NISC) architecture.
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