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AHB QSPI core, including cache for XiP

SoC Labs developed Hostio controller (implemented in the SoC) and target (implemented in testbench, FPGA, RPi Pico dev board). This supports 4x byte-wide AXI-stream virtual channels over a 7-pin off-chip interface for nanosoc reference design

Can is a ChaCha20 cryptographic accelerator based on a No-Instruction-Set Computer (NISC) architecture.

D2 Directory with submitted Schematic and Layout files

soclabs Arm Cortex-M0 based micro-controller design example(s)