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Commit 8a9d2760 authored by dwf1m12's avatar dwf1m12
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Fix uart address in pz104 notebook

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Cortex-M0/soclabs_demo/systems/cortex_m0_mcu/fpga_imp/pynq_export/pz104/jupyter_notebooks/soclabs/soclabs_cm0sdk_mcu.ipynb
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%% Cell type:markdown id: tags: %% Cell type:markdown id: tags:
# SoCLabs cm0sdk mcu overlay # SoCLabs cm0sdk mcu overlay
This notebook demonstrates how to download the FPGA overlay and communicate with programmable logic state. This notebook demonstrates how to download the FPGA overlay and communicate with programmable logic state.
## 1. Instantiating an overlay ## 1. Instantiating an overlay
With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily. With the following overlay bundle present in the `overlays` folder, users can instantiate the overlay easily.
* A bitstream file (\*.bit). * A bitstream file (\*.bit).
* An hwh file (\*.hwh). * An hwh file (\*.hwh).
* A python class (\*.py). * A python class (\*.py).
For example, a `soclabs` overlay called `design_1` can be loaded by: For example, a `soclabs` overlay called `design_1` can be loaded by:
```python ```python
from pynq.overlays.base import BaseOverlay from pynq.overlays.base import BaseOverlay
overlay = BaseOverlay("soclabs/design_1.bit") overlay = BaseOverlay("soclabs/design_1.bit")
``` ```
A `drivers` directory is provided for device driver templates for comms channels. (uartlite example). A `drivers` directory is provided for device driver templates for comms channels. (uartlite example).
Users can also use the absolute file path of the bitstream to instantiate the overlay. Users can also use the absolute file path of the bitstream to instantiate the overlay.
In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times. In this notebook, we get the current bitstream loaded on PL, and try to download it multiple times.
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
import os, warnings import os, warnings
from pynq import PL from pynq import PL
from pynq import Overlay from pynq import Overlay
from pynq import MMIO from pynq import MMIO
import sys import sys
sys.path.insert(1, './driver') sys.path.insert(1, './driver')
from uartlite import * from uartlite import *
ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design_1.bit") ol = Overlay("/home/xilinx/pynq/overlays/soclabs/design_1.bit")
if not os.path.exists(PL.bitfile_name): if not os.path.exists(PL.bitfile_name):
warnings.warn('There is no overlay loaded after boot.', UserWarning) warnings.warn('There is no overlay loaded after boot.', UserWarning)
``` ```
%% Output %% Output
%% Cell type:markdown id: tags: %% Cell type:markdown id: tags:
**Note**: If you see a warning message in the above cell, it means that no overlay **Note**: If you see a warning message in the above cell, it means that no overlay
has been loaded after boot, hence the PL server is not aware of the has been loaded after boot, hence the PL server is not aware of the
current status of the PL. In that case you won't be able to run this notebook current status of the PL. In that case you won't be able to run this notebook
until you manually load an overlay at least once using: until you manually load an overlay at least once using:
```python ```python
from pynq import Overlay from pynq import Overlay
ol = Overlay('your_overlay.bit') ol = Overlay('your_overlay.bit')
``` ```
If you do not see any warning message, you can safely proceed. If you do not see any warning message, you can safely proceed.
Next try relative path: Next try relative path:
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
from pynq import Overlay from pynq import Overlay
ol = Overlay("soclabs/design_1.bit") ol = Overlay("soclabs/design_1.bit")
``` ```
%% Cell type:markdown id: tags: %% Cell type:markdown id: tags:
Now we can check the download timestamp for this overlay. Now we can check the download timestamp for this overlay.
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
ol.download() ol.download()
ol.timestamp ol.timestamp
``` ```
%% Output %% Output
'2022/7/12 13:24:34 +609181' '2022/7/12 13:24:34 +609181'
%% Cell type:markdown id: tags: %% Cell type:markdown id: tags:
## 2. Examining the PL state ## 2. Examining the PL state
While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL). While there can be multiple overlay instances in Python, there is only one bitstream that is currently loaded onto the programmable logic (PL).
This bitstream state is held in the singleton class, PL, and is available for user queries. This bitstream state is held in the singleton class, PL, and is available for user queries.
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
PL.bitfile_name PL.bitfile_name
``` ```
%% Output %% Output
'/usr/local/lib/python3.6/dist-packages/pynq/overlays/soclabs/design_1.bit' '/usr/local/lib/python3.6/dist-packages/pynq/overlays/soclabs/design_1.bit'
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
PL.timestamp PL.timestamp
``` ```
%% Output %% Output
'2022/7/12 13:24:34 +609181' '2022/7/12 13:24:34 +609181'
%% Cell type:markdown id: tags: %% Cell type:markdown id: tags:
Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method Users can verify whether an overlay instance is currently loaded using the Overlay is_loaded() method
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
ol.is_loaded() ol.is_loaded()
``` ```
%% Output %% Output
True True
%% Cell type:markdown id: tags: %% Cell type:markdown id: tags:
## 3. Establishing communications ## 3. Establishing communications
Next set up a serial channel (configured for 9600 baud clocking rate). Next set up a serial channel (configured for 9600 baud clocking rate).
Re-download image which also resets the MCU design in PL. Re-download image which also resets the MCU design in PL.
(No explicit to reinitialize the UART after HW reset, as preconfigured baud rate). (No explicit to reinitialize the UART after HW reset, as preconfigured baud rate).
Poll for start-up banner from MCU internal boot-ROM. Poll for start-up banner from MCU internal boot-ROM.
Expect a message of the form (sometimes characters are lost as uartlite has no no flow-control support) Expect a message of the form (sometimes characters are lost as uartlite has no no flow-control support)
```python ```python
SOCLABS: ARM Cortex-M0 SDK SOCLABS: ARM Cortex-M0 SDK
- load flash - load flash
``` ```
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
# Address of the uart core # Address of the uart core
ADDRESS = 0x80003000 ADDRESS = 0x80030000
uart = UartLite(ADDRESS) uart = UartLite(ADDRESS)
ol.download() ol.download()
# Setup AXI UART register # Setup AXI UART register
#uart.setupCtrlReg() #uart.setupCtrlReg()
#print(uart.readLine()) #print(uart.readLine())
#print(uart.readLine()) #print(uart.readLine())
#print(uart.readLine()) #print(uart.readLine())
print(uart.read(45,1)) print(uart.read(45,1))
``` ```
%% Output %% Output
SOCLABS: ARM Cortex-M0 SDK SOCLABS: ARM Cortex-M0 SDK
- load flash - load flash
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
print(uart.currentStatus()) print(uart.currentStatus())
``` ```
%% Output %% Output
{'RX_VALID': 0, 'RX_FULL': 0, 'TX_EMPTY': 1, 'TX_FULL': 0, 'IS_INTR': 0, 'OVERRUN_ERR': 0, 'FRAME_ERR': 0, 'PARITY_ERR': 0} {'RX_VALID': 0, 'RX_FULL': 0, 'TX_EMPTY': 1, 'TX_FULL': 0, 'IS_INTR': 0, 'OVERRUN_ERR': 0, 'FRAME_ERR': 0, 'PARITY_ERR': 0}
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
#ol.ip_dict #ol.ip_dict
``` ```
%% Cell type:markdown id: tags: %% Cell type:markdown id: tags:
## 3. Overlay downloading overhead ## 3. Overlay downloading overhead
Finally, using Python, we can see the bitstream download time over 50 downloads. Finally, using Python, we can see the bitstream download time over 50 downloads.
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
import time import time
import matplotlib.pyplot as plt import matplotlib.pyplot as plt
length = 50 length = 50
time_log = [] time_log = []
for i in range(length): for i in range(length):
start = time.time() start = time.time()
ol.download() ol.download()
end = time.time() end = time.time()
time_log.append((end-start)*1000) time_log.append((end-start)*1000)
%matplotlib inline %matplotlib inline
plt.plot(range(length), time_log, 'ro') plt.plot(range(length), time_log, 'ro')
plt.title('Bitstream loading time (ms)') plt.title('Bitstream loading time (ms)')
plt.axis([0, length, 0, 1000]) plt.axis([0, length, 0, 1000])
plt.show() plt.show()
``` ```
%% Output %% Output
%% Cell type:code id: tags: %% Cell type:code id: tags:
``` python ``` python
``` ```
......
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