From 21c57a27815f4ff872c85811647f94cbd255b9f0 Mon Sep 17 00:00:00 2001
From: Amy <milkdrop2000@protonmail.com>
Date: Fri, 13 May 2022 01:43:55 +0100
Subject: [PATCH] Added araknoid
---
arkanoid/CMakeLists.txt | 51 +
arkanoid/balls.c | 161 +
arkanoid/balls.h | 45 +
arkanoid/build/CMakeCache.txt | 367 +
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.../CMakeDirectoryInformation.cmake | 16 +
arkanoid/build/CMakeFiles/CMakeOutput.log | 232 +
arkanoid/build/CMakeFiles/Makefile.cmake | 48 +
arkanoid/build/CMakeFiles/Makefile2 | 106 +
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arkanoid/build/CMakeFiles/cmake.check_cache | 1 +
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.../build/CMakeFiles/main.elf.dir/link.txt | 1 +
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.../main.elf.dir/pico/boot2/boot2_w25q080.S.o | Bin 0 -> 1272 bytes
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.../main.elf.dir/pico/hardware/claim.c.o | Bin 0 -> 1856 bytes
.../main.elf.dir/pico/hardware/clocks.c.o | Bin 0 -> 3804 bytes
.../main.elf.dir/pico/hardware/dma.c.o | Bin 0 -> 2540 bytes
.../main.elf.dir/pico/hardware/exception.c.o | Bin 0 -> 1892 bytes
.../main.elf.dir/pico/hardware/flash.c.o | Bin 0 -> 3804 bytes
.../main.elf.dir/pico/hardware/gpio.c.o | Bin 0 -> 3436 bytes
.../main.elf.dir/pico/hardware/i2c.c.o | Bin 0 -> 3360 bytes
.../main.elf.dir/pico/hardware/interp.c.o | Bin 0 -> 1712 bytes
.../main.elf.dir/pico/hardware/irq.c.o | Bin 0 -> 5308 bytes
.../pico/hardware/irq_handler_chain.S.o | Bin 0 -> 936 bytes
.../main.elf.dir/pico/hardware/pio.c.o | Bin 0 -> 4872 bytes
.../main.elf.dir/pico/hardware/pll.c.o | Bin 0 -> 1764 bytes
.../main.elf.dir/pico/hardware/rtc.c.o | Bin 0 -> 2776 bytes
.../main.elf.dir/pico/hardware/spi.c.o | Bin 0 -> 2864 bytes
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.../pico/tinyusb/host/usbh_control.c.o | Bin 0 -> 752 bytes
.../main.elf.dir/pico/tinyusb/rp2040_usb.c.o | Bin 0 -> 2684 bytes
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.../main.elf.dir/pico/tinyusb/usbd.c.o | Bin 0 -> 10044 bytes
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arkanoid/build/cmake_install.cmake | 49 +
arkanoid/compile.sh | 3 +
arkanoid/elf2uf2 | Bin 0 -> 94024 bytes
arkanoid/fonts.c | 1615 ++
arkanoid/fonts.h | 10 +
arkanoid/install.sh | 19 +
arkanoid/levels.h | 91 +
arkanoid/main.c | 161 +
arkanoid/main.elf | Bin 0 -> 903020 bytes
arkanoid/main.uf2 | Bin 0 -> 265728 bytes
arkanoid/pico/binary_info.h | 31 +
arkanoid/pico/bit_ops.h | 44 +
arkanoid/pico/boot2/boot2_w25q080.S | 295 +
arkanoid/pico/boot2/copied_boot2.S.ignore | 22 +
arkanoid/pico/boot2/helpers/asm_helper.S | 32 +
arkanoid/pico/boot2/helpers/exit_from_boot2.S | 28 +
arkanoid/pico/boot2/helpers/read_flash_sreg.S | 30 +
arkanoid/pico/boot2/helpers/wait_ssi_ready.S | 26 +
arkanoid/pico/bootrom.c | 36 +
arkanoid/pico/bootrom.h | 162 +
arkanoid/pico/code.h | 141 +
arkanoid/pico/critical_section.c | 27 +
arkanoid/pico/critical_section.h | 88 +
arkanoid/pico/crt0.S | 338 +
arkanoid/pico/datetime.c | 41 +
arkanoid/pico/datetime.h | 34 +
arkanoid/pico/defs.h | 43 +
arkanoid/pico/divider.h | 322 +
arkanoid/pico/doc.h | 4 +
arkanoid/pico/driver.h | 24 +
arkanoid/pico/hardware/adc.c | 23 +
arkanoid/pico/hardware/adc.h | 257 +
arkanoid/pico/hardware/address_mapped.h | 165 +
arkanoid/pico/hardware/claim.c | 56 +
arkanoid/pico/hardware/claim.h | 109 +
arkanoid/pico/hardware/clocks.c | 390 +
arkanoid/pico/hardware/clocks.h | 194 +
arkanoid/pico/hardware/divider.h | 403 +
arkanoid/pico/hardware/dma.c | 94 +
arkanoid/pico/hardware/dma.h | 795 +
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arkanoid/pico/hardware/exception.h | 106 +
arkanoid/pico/hardware/flash.c | 176 +
arkanoid/pico/hardware/flash.h | 113 +
arkanoid/pico/hardware/gpio.c | 228 +
arkanoid/pico/hardware/gpio.h | 656 +
arkanoid/pico/hardware/i2c.c | 337 +
arkanoid/pico/hardware/i2c.h | 332 +
arkanoid/pico/hardware/interp.c | 68 +
arkanoid/pico/hardware/interp.h | 458 +
arkanoid/pico/hardware/irq.c | 413 +
arkanoid/pico/hardware/irq.h | 287 +
arkanoid/pico/hardware/irq_handler_chain.S | 70 +
arkanoid/pico/hardware/pio.c | 256 +
arkanoid/pico/hardware/pio.h | 1311 ++
arkanoid/pico/hardware/pio_instructions.h | 484 +
arkanoid/pico/hardware/platform_defs.h | 45 +
arkanoid/pico/hardware/pll.c | 77 +
arkanoid/pico/hardware/pll.h | 59 +
arkanoid/pico/hardware/pwm.h | 559 +
arkanoid/pico/hardware/regs/adc.h | 314 +
arkanoid/pico/hardware/regs/addressmap.h | 74 +
arkanoid/pico/hardware/regs/busctrl.h | 324 +
arkanoid/pico/hardware/regs/clocks.h | 2409 +++
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arkanoid/pico/hardware/regs/i2c.h | 2713 +++
arkanoid/pico/hardware/regs/intctrl.h | 63 +
arkanoid/pico/hardware/regs/io_bank0.h | 14937 ++++++++++++++++
arkanoid/pico/hardware/regs/io_qspi.h | 2931 +++
arkanoid/pico/hardware/regs/m0plus.h | 1149 ++
arkanoid/pico/hardware/regs/pads_bank0.h | 2300 +++
arkanoid/pico/hardware/regs/pads_qspi.h | 454 +
arkanoid/pico/hardware/regs/pio.h | 2764 +++
arkanoid/pico/hardware/regs/pll.h | 135 +
arkanoid/pico/hardware/regs/psm.h | 584 +
arkanoid/pico/hardware/regs/pwm.h | 1505 ++
arkanoid/pico/hardware/regs/resets.h | 637 +
arkanoid/pico/hardware/regs/rosc.h | 312 +
arkanoid/pico/hardware/regs/rtc.h | 398 +
arkanoid/pico/hardware/regs/sio.h | 1656 ++
arkanoid/pico/hardware/regs/spi.h | 521 +
arkanoid/pico/hardware/regs/ssi.h | 809 +
arkanoid/pico/hardware/regs/syscfg.h | 257 +
arkanoid/pico/hardware/regs/sysinfo.h | 77 +
arkanoid/pico/hardware/regs/tbman.h | 38 +
arkanoid/pico/hardware/regs/timer.h | 332 +
arkanoid/pico/hardware/regs/uart.h | 1148 ++
arkanoid/pico/hardware/regs/usb.h | 3603 ++++
.../pico/hardware/regs/usb_device_dpram.h | 6807 +++++++
.../pico/hardware/regs/vreg_and_chip_reset.h | 151 +
arkanoid/pico/hardware/regs/watchdog.h | 226 +
arkanoid/pico/hardware/regs/xip.h | 187 +
arkanoid/pico/hardware/regs/xosc.h | 160 +
arkanoid/pico/hardware/resets.h | 99 +
arkanoid/pico/hardware/rtc.c | 191 +
arkanoid/pico/hardware/rtc.h | 91 +
arkanoid/pico/hardware/spi.c | 212 +
arkanoid/pico/hardware/spi.h | 358 +
arkanoid/pico/hardware/structs/adc.h | 91 +
arkanoid/pico/hardware/structs/bus_ctrl.h | 77 +
arkanoid/pico/hardware/structs/clocks.h | 326 +
arkanoid/pico/hardware/structs/dma.h | 203 +
arkanoid/pico/hardware/structs/i2c.h | 333 +
arkanoid/pico/hardware/structs/interp.h | 82 +
arkanoid/pico/hardware/structs/iobank0.h | 216 +
arkanoid/pico/hardware/structs/ioqspi.h | 174 +
arkanoid/pico/hardware/structs/mpu.h | 61 +
arkanoid/pico/hardware/structs/pads_qspi.h | 47 +
arkanoid/pico/hardware/structs/padsbank0.h | 47 +
arkanoid/pico/hardware/structs/pio.h | 284 +
arkanoid/pico/hardware/structs/pll.h | 56 +
arkanoid/pico/hardware/structs/psm.h | 111 +
arkanoid/pico/hardware/structs/pwm.h | 126 +
arkanoid/pico/hardware/structs/resets.h | 116 +
arkanoid/pico/hardware/structs/rosc.h | 86 +
arkanoid/pico/hardware/structs/rtc.h | 114 +
arkanoid/pico/hardware/structs/scb.h | 69 +
arkanoid/pico/hardware/structs/sio.h | 176 +
arkanoid/pico/hardware/structs/spi.h | 100 +
arkanoid/pico/hardware/structs/ssi.h | 210 +
arkanoid/pico/hardware/structs/syscfg.h | 77 +
arkanoid/pico/hardware/structs/systick.h | 52 +
arkanoid/pico/hardware/structs/timer.h | 107 +
arkanoid/pico/hardware/structs/uart.h | 177 +
arkanoid/pico/hardware/structs/usb.h | 578 +
.../hardware/structs/vreg_and_chip_reset.h | 49 +
arkanoid/pico/hardware/structs/watchdog.h | 62 +
arkanoid/pico/hardware/structs/xip_ctrl.h | 72 +
arkanoid/pico/hardware/structs/xosc.h | 60 +
arkanoid/pico/hardware/sync.c | 64 +
arkanoid/pico/hardware/sync.h | 403 +
arkanoid/pico/hardware/timer.c | 230 +
arkanoid/pico/hardware/timer.h | 198 +
arkanoid/pico/hardware/uart.c | 116 +
arkanoid/pico/hardware/uart.h | 453 +
arkanoid/pico/hardware/vreg.c | 12 +
arkanoid/pico/hardware/vreg.h | 55 +
arkanoid/pico/hardware/watchdog.c | 106 +
arkanoid/pico/hardware/watchdog.h | 120 +
arkanoid/pico/hardware/xosc.c | 55 +
arkanoid/pico/hardware/xosc.h | 59 +
arkanoid/pico/junk/assert.h | 51 +
arkanoid/pico/junk/config.h | 131 +
arkanoid/pico/junk/error.h | 25 +
arkanoid/pico/junk/types.h | 94 +
arkanoid/pico/junk/version.h | 19 +
arkanoid/pico/lock_core.c | 13 +
arkanoid/pico/lock_core.h | 197 +
arkanoid/pico/malloc.h | 38 +
arkanoid/pico/memmap_default.ld | 252 +
arkanoid/pico/multicore.c | 269 +
arkanoid/pico/multicore.h | 310 +
arkanoid/pico/mutex.c | 184 +
arkanoid/pico/mutex.h | 297 +
arkanoid/pico/pheap.c | 134 +
arkanoid/pico/pheap.h | 291 +
arkanoid/pico/pico.h | 25 +
arkanoid/pico/pico4ml/screen.c | 270 +
arkanoid/pico/pico4ml/screen.h | 136 +
arkanoid/pico/pico_bootsel_via_double_reset.c | 85 +
arkanoid/pico/pico_malloc.c | 73 +
arkanoid/pico/platform.c | 39 +
arkanoid/pico/platform.h | 411 +
arkanoid/pico/queue.c | 119 +
arkanoid/pico/queue.h | 227 +
arkanoid/pico/reset_interface.c | 112 +
arkanoid/pico/reset_interface.h | 13 +
arkanoid/pico/runtime.c | 289 +
arkanoid/pico/runtime.h | 26 +
arkanoid/pico/sem.c | 79 +
arkanoid/pico/sem.h | 128 +
arkanoid/pico/sf_table.h | 50 +
arkanoid/pico/stdio.c | 346 +
arkanoid/pico/stdio.h | 120 +
arkanoid/pico/stdio_semihosting.c | 51 +
arkanoid/pico/stdio_semihosting.h | 42 +
arkanoid/pico/stdio_uart.c | 99 +
arkanoid/pico/stdio_uart.h | 70 +
arkanoid/pico/stdio_usb.c | 135 +
arkanoid/pico/stdio_usb.h | 127 +
arkanoid/pico/stdio_usb_descriptors.c | 151 +
arkanoid/pico/stdlib.c | 104 +
arkanoid/pico/stdlib.h | 140 +
arkanoid/pico/structure.h | 151 +
arkanoid/pico/sync.h | 19 +
arkanoid/pico/time.c | 413 +
arkanoid/pico/time.h | 716 +
arkanoid/pico/timeout_helper.c | 30 +
arkanoid/pico/timeout_helper.h | 30 +
arkanoid/pico/tinyusb/cdc/cdc.h | 409 +
arkanoid/pico/tinyusb/cdc/cdc_device.c | 484 +
arkanoid/pico/tinyusb/cdc/cdc_device.h | 260 +
arkanoid/pico/tinyusb/cdc/cdc_host.c | 249 +
arkanoid/pico/tinyusb/cdc/cdc_host.h | 134 +
arkanoid/pico/tinyusb/cdc/cdc_rndis.h | 301 +
arkanoid/pico/tinyusb/cdc/cdc_rndis_host.c | 279 +
arkanoid/pico/tinyusb/cdc/cdc_rndis_host.h | 63 +
arkanoid/pico/tinyusb/dcd.h | 190 +
arkanoid/pico/tinyusb/dcd_attr.h | 167 +
arkanoid/pico/tinyusb/dcd_rp2040.c | 494 +
arkanoid/pico/tinyusb/hcd_rp2040.c | 563 +
arkanoid/pico/tinyusb/host/hcd.h | 179 +
arkanoid/pico/tinyusb/host/hcd_attr.h | 105 +
arkanoid/pico/tinyusb/host/hub.c | 388 +
arkanoid/pico/tinyusb/host/hub.h | 196 +
arkanoid/pico/tinyusb/host/usbh.c | 1195 ++
arkanoid/pico/tinyusb/host/usbh.h | 99 +
arkanoid/pico/tinyusb/host/usbh_classdriver.h | 83 +
arkanoid/pico/tinyusb/host/usbh_control.c | 138 +
arkanoid/pico/tinyusb/osal.h | 111 +
arkanoid/pico/tinyusb/osal_freertos.h | 172 +
arkanoid/pico/tinyusb/osal_mynewt.h | 174 +
arkanoid/pico/tinyusb/osal_none.h | 204 +
arkanoid/pico/tinyusb/osal_pico.h | 187 +
arkanoid/pico/tinyusb/osal_rtthread.h | 130 +
arkanoid/pico/tinyusb/rp2040_usb.c | 323 +
arkanoid/pico/tinyusb/rp2040_usb.h | 96 +
arkanoid/pico/tinyusb/tusb.c | 246 +
arkanoid/pico/tinyusb/tusb.h | 140 +
arkanoid/pico/tinyusb/tusb_common.h | 434 +
arkanoid/pico/tinyusb/tusb_compiler.h | 218 +
arkanoid/pico/tinyusb/tusb_config.h | 40 +
arkanoid/pico/tinyusb/tusb_error.h | 75 +
arkanoid/pico/tinyusb/tusb_fifo.c | 1000 ++
arkanoid/pico/tinyusb/tusb_fifo.h | 151 +
arkanoid/pico/tinyusb/tusb_option.h | 358 +
arkanoid/pico/tinyusb/tusb_timeout.h | 80 +
arkanoid/pico/tinyusb/tusb_types.h | 549 +
arkanoid/pico/tinyusb/tusb_verify.h | 181 +
arkanoid/pico/tinyusb/usbd.c | 1416 ++
arkanoid/pico/tinyusb/usbd.h | 851 +
arkanoid/pico/tinyusb/usbd_control.c | 233 +
arkanoid/pico/tinyusb/usbd_pvt.h | 115 +
arkanoid/pico/unique_id.c | 39 +
arkanoid/pico/unique_id.h | 81 +
arkanoid/pico/usb_reset_interface.h | 28 +
arkanoid/pico_mountpoint/main.uf2 | Bin 0 -> 217600 bytes
arkanoid/utils.c | 23 +
arkanoid/utils.h | 14 +
simple-setup.zip | Bin 0 -> 1839031 bytes
simple-setup/O1_working.elf | Bin 789452 -> 0 bytes
simple-setup/O2_not_working.elf | Bin 797916 -> 0 bytes
simple-setup/O2_working_with_gunoi.elf | Bin 797976 -> 0 bytes
simple-setup/main.c | 14 +-
337 files changed, 104442 insertions(+), 7 deletions(-)
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create mode 100644 arkanoid/build/CMakeFiles/main.elf.dir/pico/boot2/boot2_w25q080.S.o
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create mode 100644 arkanoid/build/CMakeFiles/progress.marks
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create mode 100755 arkanoid/compile.sh
create mode 100755 arkanoid/elf2uf2
create mode 100755 arkanoid/fonts.c
create mode 100755 arkanoid/fonts.h
create mode 100755 arkanoid/install.sh
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create mode 100644 arkanoid/main.c
create mode 100755 arkanoid/main.elf
create mode 100644 arkanoid/main.uf2
create mode 100644 arkanoid/pico/binary_info.h
create mode 100644 arkanoid/pico/bit_ops.h
create mode 100644 arkanoid/pico/boot2/boot2_w25q080.S
create mode 100644 arkanoid/pico/boot2/copied_boot2.S.ignore
create mode 100644 arkanoid/pico/boot2/helpers/asm_helper.S
create mode 100644 arkanoid/pico/boot2/helpers/exit_from_boot2.S
create mode 100644 arkanoid/pico/boot2/helpers/read_flash_sreg.S
create mode 100644 arkanoid/pico/boot2/helpers/wait_ssi_ready.S
create mode 100644 arkanoid/pico/bootrom.c
create mode 100644 arkanoid/pico/bootrom.h
create mode 100644 arkanoid/pico/code.h
create mode 100644 arkanoid/pico/critical_section.c
create mode 100644 arkanoid/pico/critical_section.h
create mode 100644 arkanoid/pico/crt0.S
create mode 100644 arkanoid/pico/datetime.c
create mode 100644 arkanoid/pico/datetime.h
create mode 100644 arkanoid/pico/defs.h
create mode 100644 arkanoid/pico/divider.h
create mode 100644 arkanoid/pico/doc.h
create mode 100644 arkanoid/pico/driver.h
create mode 100644 arkanoid/pico/hardware/adc.c
create mode 100644 arkanoid/pico/hardware/adc.h
create mode 100644 arkanoid/pico/hardware/address_mapped.h
create mode 100644 arkanoid/pico/hardware/claim.c
create mode 100644 arkanoid/pico/hardware/claim.h
create mode 100644 arkanoid/pico/hardware/clocks.c
create mode 100644 arkanoid/pico/hardware/clocks.h
create mode 100644 arkanoid/pico/hardware/divider.h
create mode 100644 arkanoid/pico/hardware/dma.c
create mode 100644 arkanoid/pico/hardware/dma.h
create mode 100644 arkanoid/pico/hardware/exception.c
create mode 100644 arkanoid/pico/hardware/exception.h
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create mode 100644 arkanoid/pico/hardware/flash.h
create mode 100644 arkanoid/pico/hardware/gpio.c
create mode 100644 arkanoid/pico/hardware/gpio.h
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create mode 100644 arkanoid/pico/hardware/i2c.h
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create mode 100644 arkanoid/pico/hardware/interp.h
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create mode 100644 arkanoid/pico/hardware/irq.h
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create mode 100644 arkanoid/pico/hardware/pio_instructions.h
create mode 100644 arkanoid/pico/hardware/platform_defs.h
create mode 100644 arkanoid/pico/hardware/pll.c
create mode 100644 arkanoid/pico/hardware/pll.h
create mode 100644 arkanoid/pico/hardware/pwm.h
create mode 100644 arkanoid/pico/hardware/regs/adc.h
create mode 100644 arkanoid/pico/hardware/regs/addressmap.h
create mode 100644 arkanoid/pico/hardware/regs/busctrl.h
create mode 100644 arkanoid/pico/hardware/regs/clocks.h
create mode 100644 arkanoid/pico/hardware/regs/dma.h
create mode 100644 arkanoid/pico/hardware/regs/dreq.h
create mode 100644 arkanoid/pico/hardware/regs/i2c.h
create mode 100644 arkanoid/pico/hardware/regs/intctrl.h
create mode 100644 arkanoid/pico/hardware/regs/io_bank0.h
create mode 100644 arkanoid/pico/hardware/regs/io_qspi.h
create mode 100644 arkanoid/pico/hardware/regs/m0plus.h
create mode 100644 arkanoid/pico/hardware/regs/pads_bank0.h
create mode 100644 arkanoid/pico/hardware/regs/pads_qspi.h
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create mode 100644 arkanoid/pico/hardware/regs/pll.h
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create mode 100644 arkanoid/pico/hardware/regs/pwm.h
create mode 100644 arkanoid/pico/hardware/regs/resets.h
create mode 100644 arkanoid/pico/hardware/regs/rosc.h
create mode 100644 arkanoid/pico/hardware/regs/rtc.h
create mode 100644 arkanoid/pico/hardware/regs/sio.h
create mode 100644 arkanoid/pico/hardware/regs/spi.h
create mode 100644 arkanoid/pico/hardware/regs/ssi.h
create mode 100644 arkanoid/pico/hardware/regs/syscfg.h
create mode 100644 arkanoid/pico/hardware/regs/sysinfo.h
create mode 100644 arkanoid/pico/hardware/regs/tbman.h
create mode 100644 arkanoid/pico/hardware/regs/timer.h
create mode 100644 arkanoid/pico/hardware/regs/uart.h
create mode 100644 arkanoid/pico/hardware/regs/usb.h
create mode 100644 arkanoid/pico/hardware/regs/usb_device_dpram.h
create mode 100644 arkanoid/pico/hardware/regs/vreg_and_chip_reset.h
create mode 100644 arkanoid/pico/hardware/regs/watchdog.h
create mode 100644 arkanoid/pico/hardware/regs/xip.h
create mode 100644 arkanoid/pico/hardware/regs/xosc.h
create mode 100644 arkanoid/pico/hardware/resets.h
create mode 100644 arkanoid/pico/hardware/rtc.c
create mode 100644 arkanoid/pico/hardware/rtc.h
create mode 100644 arkanoid/pico/hardware/spi.c
create mode 100644 arkanoid/pico/hardware/spi.h
create mode 100644 arkanoid/pico/hardware/structs/adc.h
create mode 100644 arkanoid/pico/hardware/structs/bus_ctrl.h
create mode 100644 arkanoid/pico/hardware/structs/clocks.h
create mode 100644 arkanoid/pico/hardware/structs/dma.h
create mode 100644 arkanoid/pico/hardware/structs/i2c.h
create mode 100644 arkanoid/pico/hardware/structs/interp.h
create mode 100644 arkanoid/pico/hardware/structs/iobank0.h
create mode 100644 arkanoid/pico/hardware/structs/ioqspi.h
create mode 100644 arkanoid/pico/hardware/structs/mpu.h
create mode 100644 arkanoid/pico/hardware/structs/pads_qspi.h
create mode 100644 arkanoid/pico/hardware/structs/padsbank0.h
create mode 100644 arkanoid/pico/hardware/structs/pio.h
create mode 100644 arkanoid/pico/hardware/structs/pll.h
create mode 100644 arkanoid/pico/hardware/structs/psm.h
create mode 100644 arkanoid/pico/hardware/structs/pwm.h
create mode 100644 arkanoid/pico/hardware/structs/resets.h
create mode 100644 arkanoid/pico/hardware/structs/rosc.h
create mode 100644 arkanoid/pico/hardware/structs/rtc.h
create mode 100644 arkanoid/pico/hardware/structs/scb.h
create mode 100644 arkanoid/pico/hardware/structs/sio.h
create mode 100644 arkanoid/pico/hardware/structs/spi.h
create mode 100644 arkanoid/pico/hardware/structs/ssi.h
create mode 100644 arkanoid/pico/hardware/structs/syscfg.h
create mode 100644 arkanoid/pico/hardware/structs/systick.h
create mode 100644 arkanoid/pico/hardware/structs/timer.h
create mode 100644 arkanoid/pico/hardware/structs/uart.h
create mode 100644 arkanoid/pico/hardware/structs/usb.h
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create mode 100644 arkanoid/pico/hardware/structs/watchdog.h
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create mode 100644 arkanoid/pico/hardware/sync.h
create mode 100644 arkanoid/pico/hardware/timer.c
create mode 100644 arkanoid/pico/hardware/timer.h
create mode 100644 arkanoid/pico/hardware/uart.c
create mode 100644 arkanoid/pico/hardware/uart.h
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create mode 100644 arkanoid/pico/hardware/vreg.h
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create mode 100644 arkanoid/pico/hardware/xosc.h
create mode 100644 arkanoid/pico/junk/assert.h
create mode 100644 arkanoid/pico/junk/config.h
create mode 100644 arkanoid/pico/junk/error.h
create mode 100644 arkanoid/pico/junk/types.h
create mode 100644 arkanoid/pico/junk/version.h
create mode 100644 arkanoid/pico/lock_core.c
create mode 100644 arkanoid/pico/lock_core.h
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create mode 100644 arkanoid/pico/memmap_default.ld
create mode 100644 arkanoid/pico/multicore.c
create mode 100644 arkanoid/pico/multicore.h
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create mode 100644 arkanoid/pico/mutex.h
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create mode 100644 arkanoid/pico/pheap.h
create mode 100644 arkanoid/pico/pico.h
create mode 100644 arkanoid/pico/pico4ml/screen.c
create mode 100644 arkanoid/pico/pico4ml/screen.h
create mode 100644 arkanoid/pico/pico_bootsel_via_double_reset.c
create mode 100644 arkanoid/pico/pico_malloc.c
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create mode 100644 arkanoid/pico/platform.h
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create mode 100644 arkanoid/pico/queue.h
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create mode 100644 arkanoid/pico/reset_interface.h
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create mode 100644 arkanoid/pico/runtime.h
create mode 100644 arkanoid/pico/sem.c
create mode 100644 arkanoid/pico/sem.h
create mode 100644 arkanoid/pico/sf_table.h
create mode 100644 arkanoid/pico/stdio.c
create mode 100644 arkanoid/pico/stdio.h
create mode 100644 arkanoid/pico/stdio_semihosting.c
create mode 100644 arkanoid/pico/stdio_semihosting.h
create mode 100644 arkanoid/pico/stdio_uart.c
create mode 100644 arkanoid/pico/stdio_uart.h
create mode 100644 arkanoid/pico/stdio_usb.c
create mode 100644 arkanoid/pico/stdio_usb.h
create mode 100644 arkanoid/pico/stdio_usb_descriptors.c
create mode 100644 arkanoid/pico/stdlib.c
create mode 100644 arkanoid/pico/stdlib.h
create mode 100644 arkanoid/pico/structure.h
create mode 100644 arkanoid/pico/sync.h
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create mode 100644 arkanoid/pico/time.h
create mode 100644 arkanoid/pico/timeout_helper.c
create mode 100644 arkanoid/pico/timeout_helper.h
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc.h
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc_device.c
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc_device.h
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc_host.c
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc_host.h
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc_rndis.h
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc_rndis_host.c
create mode 100644 arkanoid/pico/tinyusb/cdc/cdc_rndis_host.h
create mode 100644 arkanoid/pico/tinyusb/dcd.h
create mode 100644 arkanoid/pico/tinyusb/dcd_attr.h
create mode 100644 arkanoid/pico/tinyusb/dcd_rp2040.c
create mode 100644 arkanoid/pico/tinyusb/hcd_rp2040.c
create mode 100644 arkanoid/pico/tinyusb/host/hcd.h
create mode 100644 arkanoid/pico/tinyusb/host/hcd_attr.h
create mode 100644 arkanoid/pico/tinyusb/host/hub.c
create mode 100644 arkanoid/pico/tinyusb/host/hub.h
create mode 100644 arkanoid/pico/tinyusb/host/usbh.c
create mode 100644 arkanoid/pico/tinyusb/host/usbh.h
create mode 100644 arkanoid/pico/tinyusb/host/usbh_classdriver.h
create mode 100644 arkanoid/pico/tinyusb/host/usbh_control.c
create mode 100644 arkanoid/pico/tinyusb/osal.h
create mode 100644 arkanoid/pico/tinyusb/osal_freertos.h
create mode 100644 arkanoid/pico/tinyusb/osal_mynewt.h
create mode 100644 arkanoid/pico/tinyusb/osal_none.h
create mode 100644 arkanoid/pico/tinyusb/osal_pico.h
create mode 100644 arkanoid/pico/tinyusb/osal_rtthread.h
create mode 100644 arkanoid/pico/tinyusb/rp2040_usb.c
create mode 100644 arkanoid/pico/tinyusb/rp2040_usb.h
create mode 100644 arkanoid/pico/tinyusb/tusb.c
create mode 100644 arkanoid/pico/tinyusb/tusb.h
create mode 100644 arkanoid/pico/tinyusb/tusb_common.h
create mode 100644 arkanoid/pico/tinyusb/tusb_compiler.h
create mode 100644 arkanoid/pico/tinyusb/tusb_config.h
create mode 100644 arkanoid/pico/tinyusb/tusb_error.h
create mode 100644 arkanoid/pico/tinyusb/tusb_fifo.c
create mode 100644 arkanoid/pico/tinyusb/tusb_fifo.h
create mode 100644 arkanoid/pico/tinyusb/tusb_option.h
create mode 100644 arkanoid/pico/tinyusb/tusb_timeout.h
create mode 100644 arkanoid/pico/tinyusb/tusb_types.h
create mode 100644 arkanoid/pico/tinyusb/tusb_verify.h
create mode 100644 arkanoid/pico/tinyusb/usbd.c
create mode 100644 arkanoid/pico/tinyusb/usbd.h
create mode 100644 arkanoid/pico/tinyusb/usbd_control.c
create mode 100644 arkanoid/pico/tinyusb/usbd_pvt.h
create mode 100644 arkanoid/pico/unique_id.c
create mode 100644 arkanoid/pico/unique_id.h
create mode 100644 arkanoid/pico/usb_reset_interface.h
create mode 100644 arkanoid/pico_mountpoint/main.uf2
create mode 100644 arkanoid/utils.c
create mode 100644 arkanoid/utils.h
create mode 100644 simple-setup.zip
delete mode 100755 simple-setup/O1_working.elf
delete mode 100755 simple-setup/O2_not_working.elf
delete mode 100755 simple-setup/O2_working_with_gunoi.elf
diff --git a/arkanoid/CMakeLists.txt b/arkanoid/CMakeLists.txt
new file mode 100644
index 0000000..0219088
--- /dev/null
+++ b/arkanoid/CMakeLists.txt
@@ -0,0 +1,51 @@
+cmake_minimum_required (VERSION 3.10)
+
+project (test C ASM)
+
+set(CMAKE_C_COMPILER arm-none-eabi-gcc)
+set(CMAKE_ASM_COMPILER arm-none-eabi-gcc)
+# -O2 bricks the screen!
+set(CMAKE_C_FLAGS "-O1 -mcpu=cortex-m0plus --specs=nosys.specs -Wl,--wrap,malloc -Wl,--wrap,calloc -Wl,--wrap,free -Wl,--wrap,vprintf -Wl,--wrap,vscanf")
+set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp")
+
+file (GLOB srcs
+ ${CMAKE_CURRENT_SOURCE_DIR}/*.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/*.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/*.S
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/boot2/*.S
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/tinyusb/*.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/tinyusb/cdc/*.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/tinyusb/host/*.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/hardware/*.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/hardware/*.S
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/hardware/regs/*.c
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/hardware/structs/*.c
+
+ ${CMAKE_CURRENT_SOURCE_DIR}/pico/pico4ml/*.c
+)
+
+#TUSB_OPT_DEVICE_ENABLED
+
+add_compile_definitions (
+ PICO_ON_DEVICE=1
+ CFG_TUSB_RHPORT0_MODE=OPT_OS_PICO
+ CFG_TUSB_MCU=OPT_MCU_RP2040
+ LIB_PICO_STDIO_USB
+)
+
+add_executable (main.elf ${srcs})
+target_link_libraries (main.elf m)
+
+target_link_options (main.elf PUBLIC -T ${CMAKE_CURRENT_SOURCE_DIR}/pico/memmap_default.ld)
+
+add_custom_command (
+ COMMAND ${CMAKE_CURRENT_SOURCE_DIR}/elf2uf2 ${CMAKE_CURRENT_SOURCE_DIR}/main.elf main.uf2
+ WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+ TARGET main.elf
+ COMMENT "Converting main.elf to flashable main.uf2..."
+)
+
+set_target_properties (main.elf PROPERTIES RUNTIME_OUTPUT_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR})
diff --git a/arkanoid/balls.c b/arkanoid/balls.c
new file mode 100644
index 0000000..ebbdffb
--- /dev/null
+++ b/arkanoid/balls.c
@@ -0,0 +1,161 @@
+#include <math.h>
+#include <stdlib.h>
+#include "pico/pico4ml/screen.h"
+#include <stdio.h>
+
+#include "balls.h"
+#include "utils.h"
+
+// http://rosettacode.org/wiki/Bitmap/Bresenham%27s_line_algorithm#C
+void drawCoordLine(int x0, int y0, int x1, int y1, int col) {
+
+ int dx = abs(x1-x0), sx = x0<x1 ? 1 : -1;
+ int dy = abs(y1-y0), sy = y0<y1 ? 1 : -1;
+ int err = (dx>dy ? dx : -dy)/2, e2;
+
+ for(;;){
+ ST7735_FillRectangle(x0, y0, 3, 3, col);
+
+ if (x0==x1 && y0==y1) break;
+ e2 = err;
+ if (e2 >-dx) { err -= dy; x0 += sx; }
+ if (e2 < dy) { err += dx; y0 += sy; }
+ }
+}
+
+void paddlePhysicsStep(Paddle *paddle) {
+ bool moved = false;
+ float old_x = paddle->pos.x;
+
+ if (gpio_get(20) == 0) {
+ paddle->pos.x -= paddle->moveSpeed;
+ moved = true;
+ }
+
+ if (gpio_get(21) == 0) {
+ paddle->pos.x += paddle->moveSpeed;
+ moved = true;
+ }
+
+ if (moved) {
+ if (paddle->pos.x < paddle->length / 2) {
+ paddle->pos.x = paddle->length / 2;
+ }
+
+ if (paddle->pos.x > 79 - paddle->length / 2) {
+ paddle->pos.x = 79 - paddle->length / 2;
+ }
+
+ ST7735_FillRectangle(old_x - paddle->length / 2, paddle->pos.y, paddle->length, 3, ST7735_BLACK);
+ drawPaddle(paddle);
+ }
+}
+
+void resetBallTrail(int x, int y, Ball *ball) {
+ for (int i=1; i<25; i++) {
+ drawCoordLine(ball->prevCoords[i].x, ball->prevCoords[i].y, ball->prevCoords[i-1].x, ball->prevCoords[i-1].y, ST7735_BLACK);
+ }
+
+ for (int i=0; i<25; i++) {
+ ball->prevCoords[i].x = x;
+ ball->prevCoords[i].y = y;
+ }
+}
+
+void resetBall(Ball *ball) {
+ ball->pos.x = 43;
+ ball->pos.y = 120;
+ resetBallTrail(43, 120, ball);
+ ball->speedY = ball->speed;
+ ball->speedX = 0;
+}
+
+// Update ball movement based on speed and do looping/bouncing
+int16_t ballPhysicsStep(Ball *ball, Paddle *paddle, uint16_t *blocks) {
+ int16_t hit_result = BALL_HIT_NOTHING;
+
+ ball->pos.x += ball->speedX;
+ ball->pos.y += ball->speedY;
+
+ ball->speedX *= ball->friction;
+ ball->speedY *= ball->friction;
+
+ if (ball->pos.y <= 0) {
+ ball->pos.y = 0;
+ ball->speedY *= -1;
+ } else if (ball->pos.y >= 200) {
+ resetBall(ball);
+ hit_result = BALL_DIED;
+ }
+
+ if (ball->pos.x <= 0) {
+ ball->pos.x = 0;
+ ball->speedX *= -1;
+ } else if (ball->pos.x >= 79) {
+ ball->pos.x = 79;
+ ball->speedX *= -1;
+ }
+
+ int paddle_halflen = paddle->length / 2;
+
+ //printf("ball: Y:%f X:%f, spd:%f | paddle: Y:%f X:%f %f\n", ball->pos.y, ball->pos.x, ball->speed, paddle->pos.y, paddle->pos.x - paddle_halflen, paddle->pos.x + paddle_halflen);
+
+
+ if (ball->pos.y >= paddle->pos.y - 2 && ball->pos.y <= paddle->pos.y + 4
+ && ball->pos.x >= paddle->pos.x - paddle_halflen && ball->pos.x <= paddle->pos.x + paddle_halflen) {
+ float angle = (((float) (ball->pos.x - paddle->pos.x) / paddle_halflen) * 45) * M_PI / 180;
+ //printf("ang %f %f\n", ((float) (ball->pos.x - paddle->pos.x) / paddle_halflen) * 45, angle);
+
+ ball->speedY = -cos(angle) * ball->speed;
+ ball->speedX = sin(angle) * ball->speed;
+ hit_result = BALL_HIT_PADDLE;
+ }
+
+ if (ball->pos.y <= 80) {
+ int block_y = ball->pos.y / 4;
+ int block_x = ball->pos.x / 10;
+ hit_result = block_y * 8 + block_x;
+
+ if (blocks[hit_result]) {
+ blocks[hit_result] = 0;
+ ball->speedY *= -1;
+ } else {
+ hit_result = BALL_HIT_NOTHING;
+ }
+ }
+
+ return hit_result;
+}
+
+void drawPaddle(Paddle *paddle) {
+ // Paddle has a center pos and a length. Extend half length in each direction
+ int left_x = paddle->pos.x - paddle->length / 2;
+
+ ST7735_FillRectangle(left_x, paddle->pos.y, paddle->length, 3, paddle->borderColor);
+ ST7735_FillRectangle(left_x + 1, paddle->pos.y + 1, paddle->length - 2, 1, paddle->color);
+}
+
+// Render ball position and update coordinate history
+void drawBallTrail(Ball *ball) {
+ for (int i=24; i>=0; i--) {
+ Coordinate coordT = ball->prevCoords[i];
+ Coordinate coordO = ball->prevCoords[i-1];
+ uint16_t color = (i == 0) ? ball->headCol : change_color(ball->tailCol, (1 - ((float) i / 24)));
+
+ if (coordT.y >= 150 && coordO.y <= 10) { // looping to the left (0), appearing on the right (159)
+ //drawCoordLine(coordO.x, coordO.y, coordT.x, 0, color);
+ //drawCoordLine(coordO.x, 159, coordT.x, coordT.y, color);
+ } else if (coordT.y <= 10 && coordO.y >= 150) { // lopoing to the right (159), appearing on the left (0)
+ //drawCoordLine(coordO.x, coordO.y, coordT.x, 159, color);
+ //drawCoordLine(coordO.x, 0, coordT.x, coordT.y, color);
+ } else {
+ drawCoordLine(ball->prevCoords[i].x, ball->prevCoords[i].y, ball->prevCoords[i-1].x, ball->prevCoords[i-1].y, color);
+ }
+ }
+
+ for (int i=24; i>0; i--) {
+ ball->prevCoords[i] = ball->prevCoords[i-1];
+ }
+
+ ball->prevCoords[0] = ball->pos;
+}
diff --git a/arkanoid/balls.h b/arkanoid/balls.h
new file mode 100644
index 0000000..199ee1c
--- /dev/null
+++ b/arkanoid/balls.h
@@ -0,0 +1,45 @@
+#ifndef BALLS_H
+#define BALLS_H
+#include <math.h>
+#include <stdlib.h>
+#include "pico/stdlib.h"
+#include "pico/pico4ml/screen.h"
+
+typedef struct {
+ float x;
+ float y;
+} Coordinate;
+
+typedef struct {
+ Coordinate pos;
+ Coordinate prevCoords[25];
+
+ float speedX;
+ float speedY;
+
+ float friction;
+
+ int headCol;
+ int tailCol;
+ float speed;
+} Ball;
+
+typedef struct {
+ Coordinate pos;
+
+ int length;
+ float moveSpeed;
+
+ uint16_t color;
+ uint16_t borderColor;
+} Paddle;
+
+void drawCoordLine(int x0, int y0, int x1, int y1, int col);
+void paddlePhysicsStep(Paddle *paddle);
+void resetBallTrail(int x, int y, Ball *ball);
+int16_t ballPhysicsStep(Ball *ball, Paddle *paddle, uint16_t *blocks);
+void drawPaddle(Paddle *paddle);
+void drawBallTrail(Ball *ball);
+void resetBall(Ball *ball);
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/build/CMakeCache.txt b/arkanoid/build/CMakeCache.txt
new file mode 100644
index 0000000..4774fbd
--- /dev/null
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diff --git a/arkanoid/build/CMakeFiles/3.16.3/CMakeASMCompiler.cmake b/arkanoid/build/CMakeFiles/3.16.3/CMakeASMCompiler.cmake
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+# define COMPILER_VERSION_MAJOR DEC(_RELEASE_MAJOR)
+# define COMPILER_VERSION_MINOR DEC(_RELEASE_MINOR)
+
+#elif defined(__TI_COMPILER_VERSION__)
+# define COMPILER_ID "TI"
+ /* __TI_COMPILER_VERSION__ = VVVRRRPPP */
+# define COMPILER_VERSION_MAJOR DEC(__TI_COMPILER_VERSION__/1000000)
+# define COMPILER_VERSION_MINOR DEC(__TI_COMPILER_VERSION__/1000 % 1000)
+# define COMPILER_VERSION_PATCH DEC(__TI_COMPILER_VERSION__ % 1000)
+
+#elif defined(__FUJITSU) || defined(__FCC_VERSION) || defined(__fcc_version)
+# define COMPILER_ID "Fujitsu"
+
+#elif defined(__ghs__)
+# define COMPILER_ID "GHS"
+/* __GHS_VERSION_NUMBER = VVVVRP */
+# ifdef __GHS_VERSION_NUMBER
+# define COMPILER_VERSION_MAJOR DEC(__GHS_VERSION_NUMBER / 100)
+# define COMPILER_VERSION_MINOR DEC(__GHS_VERSION_NUMBER / 10 % 10)
+# define COMPILER_VERSION_PATCH DEC(__GHS_VERSION_NUMBER % 10)
+# endif
+
+#elif defined(__TINYC__)
+# define COMPILER_ID "TinyCC"
+
+#elif defined(__BCC__)
+# define COMPILER_ID "Bruce"
+
+#elif defined(__SCO_VERSION__)
+# define COMPILER_ID "SCO"
+
+#elif defined(__ARMCC_VERSION) && !defined(__clang__)
+# define COMPILER_ID "ARMCC"
+#if __ARMCC_VERSION >= 1000000
+ /* __ARMCC_VERSION = VRRPPPP */
+ # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/1000000)
+ # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 100)
+ # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
+#else
+ /* __ARMCC_VERSION = VRPPPP */
+ # define COMPILER_VERSION_MAJOR DEC(__ARMCC_VERSION/100000)
+ # define COMPILER_VERSION_MINOR DEC(__ARMCC_VERSION/10000 % 10)
+ # define COMPILER_VERSION_PATCH DEC(__ARMCC_VERSION % 10000)
+#endif
+
+
+#elif defined(__clang__) && defined(__apple_build_version__)
+# define COMPILER_ID "AppleClang"
+# if defined(_MSC_VER)
+# define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+ /* _MSC_VER = VVRR */
+# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+# define COMPILER_VERSION_TWEAK DEC(__apple_build_version__)
+
+#elif defined(__clang__) && defined(__ARMCOMPILER_VERSION)
+# define COMPILER_ID "ARMClang"
+ # define COMPILER_VERSION_MAJOR DEC(__ARMCOMPILER_VERSION/1000000)
+ # define COMPILER_VERSION_MINOR DEC(__ARMCOMPILER_VERSION/10000 % 100)
+ # define COMPILER_VERSION_PATCH DEC(__ARMCOMPILER_VERSION % 10000)
+# define COMPILER_VERSION_INTERNAL DEC(__ARMCOMPILER_VERSION)
+
+#elif defined(__clang__)
+# define COMPILER_ID "Clang"
+# if defined(_MSC_VER)
+# define SIMULATE_ID "MSVC"
+# endif
+# define COMPILER_VERSION_MAJOR DEC(__clang_major__)
+# define COMPILER_VERSION_MINOR DEC(__clang_minor__)
+# define COMPILER_VERSION_PATCH DEC(__clang_patchlevel__)
+# if defined(_MSC_VER)
+ /* _MSC_VER = VVRR */
+# define SIMULATE_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define SIMULATE_VERSION_MINOR DEC(_MSC_VER % 100)
+# endif
+
+#elif defined(__GNUC__)
+# define COMPILER_ID "GNU"
+# define COMPILER_VERSION_MAJOR DEC(__GNUC__)
+# if defined(__GNUC_MINOR__)
+# define COMPILER_VERSION_MINOR DEC(__GNUC_MINOR__)
+# endif
+# if defined(__GNUC_PATCHLEVEL__)
+# define COMPILER_VERSION_PATCH DEC(__GNUC_PATCHLEVEL__)
+# endif
+
+#elif defined(_MSC_VER)
+# define COMPILER_ID "MSVC"
+ /* _MSC_VER = VVRR */
+# define COMPILER_VERSION_MAJOR DEC(_MSC_VER / 100)
+# define COMPILER_VERSION_MINOR DEC(_MSC_VER % 100)
+# if defined(_MSC_FULL_VER)
+# if _MSC_VER >= 1400
+ /* _MSC_FULL_VER = VVRRPPPPP */
+# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 100000)
+# else
+ /* _MSC_FULL_VER = VVRRPPPP */
+# define COMPILER_VERSION_PATCH DEC(_MSC_FULL_VER % 10000)
+# endif
+# endif
+# if defined(_MSC_BUILD)
+# define COMPILER_VERSION_TWEAK DEC(_MSC_BUILD)
+# endif
+
+#elif defined(__VISUALDSPVERSION__) || defined(__ADSPBLACKFIN__) || defined(__ADSPTS__) || defined(__ADSP21000__)
+# define COMPILER_ID "ADSP"
+#if defined(__VISUALDSPVERSION__)
+ /* __VISUALDSPVERSION__ = 0xVVRRPP00 */
+# define COMPILER_VERSION_MAJOR HEX(__VISUALDSPVERSION__>>24)
+# define COMPILER_VERSION_MINOR HEX(__VISUALDSPVERSION__>>16 & 0xFF)
+# define COMPILER_VERSION_PATCH HEX(__VISUALDSPVERSION__>>8 & 0xFF)
+#endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# define COMPILER_ID "IAR"
+# if defined(__VER__) && defined(__ICCARM__)
+# define COMPILER_VERSION_MAJOR DEC((__VER__) / 1000000)
+# define COMPILER_VERSION_MINOR DEC(((__VER__) / 1000) % 1000)
+# define COMPILER_VERSION_PATCH DEC((__VER__) % 1000)
+# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# elif defined(__VER__) && (defined(__ICCAVR__) || defined(__ICCRX__) || defined(__ICCRH850__) || defined(__ICCRL78__) || defined(__ICC430__) || defined(__ICCRISCV__) || defined(__ICCV850__) || defined(__ICC8051__))
+# define COMPILER_VERSION_MAJOR DEC((__VER__) / 100)
+# define COMPILER_VERSION_MINOR DEC((__VER__) - (((__VER__) / 100)*100))
+# define COMPILER_VERSION_PATCH DEC(__SUBVERSION__)
+# define COMPILER_VERSION_INTERNAL DEC(__IAR_SYSTEMS_ICC__)
+# endif
+
+#elif defined(__SDCC_VERSION_MAJOR) || defined(SDCC)
+# define COMPILER_ID "SDCC"
+# if defined(__SDCC_VERSION_MAJOR)
+# define COMPILER_VERSION_MAJOR DEC(__SDCC_VERSION_MAJOR)
+# define COMPILER_VERSION_MINOR DEC(__SDCC_VERSION_MINOR)
+# define COMPILER_VERSION_PATCH DEC(__SDCC_VERSION_PATCH)
+# else
+ /* SDCC = VRP */
+# define COMPILER_VERSION_MAJOR DEC(SDCC/100)
+# define COMPILER_VERSION_MINOR DEC(SDCC/10 % 10)
+# define COMPILER_VERSION_PATCH DEC(SDCC % 10)
+# endif
+
+
+/* These compilers are either not known or too old to define an
+ identification macro. Try to identify the platform and guess that
+ it is the native compiler. */
+#elif defined(__hpux) || defined(__hpua)
+# define COMPILER_ID "HP"
+
+#else /* unknown compiler */
+# define COMPILER_ID ""
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+ getting matched. Store it in a pointer rather than an array
+ because some compilers will just produce instructions to fill the
+ array rather than assigning a pointer to a static array. */
+char const* info_compiler = "INFO" ":" "compiler[" COMPILER_ID "]";
+#ifdef SIMULATE_ID
+char const* info_simulate = "INFO" ":" "simulate[" SIMULATE_ID "]";
+#endif
+
+#ifdef __QNXNTO__
+char const* qnxnto = "INFO" ":" "qnxnto[]";
+#endif
+
+#if defined(__CRAYXE) || defined(__CRAYXC)
+char const *info_cray = "INFO" ":" "compiler_wrapper[CrayPrgEnv]";
+#endif
+
+#define STRINGIFY_HELPER(X) #X
+#define STRINGIFY(X) STRINGIFY_HELPER(X)
+
+/* Identify known platforms by name. */
+#if defined(__linux) || defined(__linux__) || defined(linux)
+# define PLATFORM_ID "Linux"
+
+#elif defined(__CYGWIN__)
+# define PLATFORM_ID "Cygwin"
+
+#elif defined(__MINGW32__)
+# define PLATFORM_ID "MinGW"
+
+#elif defined(__APPLE__)
+# define PLATFORM_ID "Darwin"
+
+#elif defined(_WIN32) || defined(__WIN32__) || defined(WIN32)
+# define PLATFORM_ID "Windows"
+
+#elif defined(__FreeBSD__) || defined(__FreeBSD)
+# define PLATFORM_ID "FreeBSD"
+
+#elif defined(__NetBSD__) || defined(__NetBSD)
+# define PLATFORM_ID "NetBSD"
+
+#elif defined(__OpenBSD__) || defined(__OPENBSD)
+# define PLATFORM_ID "OpenBSD"
+
+#elif defined(__sun) || defined(sun)
+# define PLATFORM_ID "SunOS"
+
+#elif defined(_AIX) || defined(__AIX) || defined(__AIX__) || defined(__aix) || defined(__aix__)
+# define PLATFORM_ID "AIX"
+
+#elif defined(__hpux) || defined(__hpux__)
+# define PLATFORM_ID "HP-UX"
+
+#elif defined(__HAIKU__)
+# define PLATFORM_ID "Haiku"
+
+#elif defined(__BeOS) || defined(__BEOS__) || defined(_BEOS)
+# define PLATFORM_ID "BeOS"
+
+#elif defined(__QNX__) || defined(__QNXNTO__)
+# define PLATFORM_ID "QNX"
+
+#elif defined(__tru64) || defined(_tru64) || defined(__TRU64__)
+# define PLATFORM_ID "Tru64"
+
+#elif defined(__riscos) || defined(__riscos__)
+# define PLATFORM_ID "RISCos"
+
+#elif defined(__sinix) || defined(__sinix__) || defined(__SINIX__)
+# define PLATFORM_ID "SINIX"
+
+#elif defined(__UNIX_SV__)
+# define PLATFORM_ID "UNIX_SV"
+
+#elif defined(__bsdos__)
+# define PLATFORM_ID "BSDOS"
+
+#elif defined(_MPRAS) || defined(MPRAS)
+# define PLATFORM_ID "MP-RAS"
+
+#elif defined(__osf) || defined(__osf__)
+# define PLATFORM_ID "OSF1"
+
+#elif defined(_SCO_SV) || defined(SCO_SV) || defined(sco_sv)
+# define PLATFORM_ID "SCO_SV"
+
+#elif defined(__ultrix) || defined(__ultrix__) || defined(_ULTRIX)
+# define PLATFORM_ID "ULTRIX"
+
+#elif defined(__XENIX__) || defined(_XENIX) || defined(XENIX)
+# define PLATFORM_ID "Xenix"
+
+#elif defined(__WATCOMC__)
+# if defined(__LINUX__)
+# define PLATFORM_ID "Linux"
+
+# elif defined(__DOS__)
+# define PLATFORM_ID "DOS"
+
+# elif defined(__OS2__)
+# define PLATFORM_ID "OS2"
+
+# elif defined(__WINDOWS__)
+# define PLATFORM_ID "Windows3x"
+
+# else /* unknown platform */
+# define PLATFORM_ID
+# endif
+
+#elif defined(__INTEGRITY)
+# if defined(INT_178B)
+# define PLATFORM_ID "Integrity178"
+
+# else /* regular Integrity */
+# define PLATFORM_ID "Integrity"
+# endif
+
+#else /* unknown platform */
+# define PLATFORM_ID
+
+#endif
+
+/* For windows compilers MSVC and Intel we can determine
+ the architecture of the compiler being used. This is because
+ the compilers do not have flags that can change the architecture,
+ but rather depend on which compiler is being used
+*/
+#if defined(_WIN32) && defined(_MSC_VER)
+# if defined(_M_IA64)
+# define ARCHITECTURE_ID "IA64"
+
+# elif defined(_M_X64) || defined(_M_AMD64)
+# define ARCHITECTURE_ID "x64"
+
+# elif defined(_M_IX86)
+# define ARCHITECTURE_ID "X86"
+
+# elif defined(_M_ARM64)
+# define ARCHITECTURE_ID "ARM64"
+
+# elif defined(_M_ARM)
+# if _M_ARM == 4
+# define ARCHITECTURE_ID "ARMV4I"
+# elif _M_ARM == 5
+# define ARCHITECTURE_ID "ARMV5I"
+# else
+# define ARCHITECTURE_ID "ARMV" STRINGIFY(_M_ARM)
+# endif
+
+# elif defined(_M_MIPS)
+# define ARCHITECTURE_ID "MIPS"
+
+# elif defined(_M_SH)
+# define ARCHITECTURE_ID "SHx"
+
+# else /* unknown architecture */
+# define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__WATCOMC__)
+# if defined(_M_I86)
+# define ARCHITECTURE_ID "I86"
+
+# elif defined(_M_IX86)
+# define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+# define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__IAR_SYSTEMS_ICC__) || defined(__IAR_SYSTEMS_ICC)
+# if defined(__ICCARM__)
+# define ARCHITECTURE_ID "ARM"
+
+# elif defined(__ICCRX__)
+# define ARCHITECTURE_ID "RX"
+
+# elif defined(__ICCRH850__)
+# define ARCHITECTURE_ID "RH850"
+
+# elif defined(__ICCRL78__)
+# define ARCHITECTURE_ID "RL78"
+
+# elif defined(__ICCRISCV__)
+# define ARCHITECTURE_ID "RISCV"
+
+# elif defined(__ICCAVR__)
+# define ARCHITECTURE_ID "AVR"
+
+# elif defined(__ICC430__)
+# define ARCHITECTURE_ID "MSP430"
+
+# elif defined(__ICCV850__)
+# define ARCHITECTURE_ID "V850"
+
+# elif defined(__ICC8051__)
+# define ARCHITECTURE_ID "8051"
+
+# else /* unknown architecture */
+# define ARCHITECTURE_ID ""
+# endif
+
+#elif defined(__ghs__)
+# if defined(__PPC64__)
+# define ARCHITECTURE_ID "PPC64"
+
+# elif defined(__ppc__)
+# define ARCHITECTURE_ID "PPC"
+
+# elif defined(__ARM__)
+# define ARCHITECTURE_ID "ARM"
+
+# elif defined(__x86_64__)
+# define ARCHITECTURE_ID "x64"
+
+# elif defined(__i386__)
+# define ARCHITECTURE_ID "X86"
+
+# else /* unknown architecture */
+# define ARCHITECTURE_ID ""
+# endif
+#else
+# define ARCHITECTURE_ID
+#endif
+
+/* Convert integer to decimal digit literals. */
+#define DEC(n) \
+ ('0' + (((n) / 10000000)%10)), \
+ ('0' + (((n) / 1000000)%10)), \
+ ('0' + (((n) / 100000)%10)), \
+ ('0' + (((n) / 10000)%10)), \
+ ('0' + (((n) / 1000)%10)), \
+ ('0' + (((n) / 100)%10)), \
+ ('0' + (((n) / 10)%10)), \
+ ('0' + ((n) % 10))
+
+/* Convert integer to hex digit literals. */
+#define HEX(n) \
+ ('0' + ((n)>>28 & 0xF)), \
+ ('0' + ((n)>>24 & 0xF)), \
+ ('0' + ((n)>>20 & 0xF)), \
+ ('0' + ((n)>>16 & 0xF)), \
+ ('0' + ((n)>>12 & 0xF)), \
+ ('0' + ((n)>>8 & 0xF)), \
+ ('0' + ((n)>>4 & 0xF)), \
+ ('0' + ((n) & 0xF))
+
+/* Construct a string literal encoding the version number components. */
+#ifdef COMPILER_VERSION_MAJOR
+char const info_version[] = {
+ 'I', 'N', 'F', 'O', ':',
+ 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','[',
+ COMPILER_VERSION_MAJOR,
+# ifdef COMPILER_VERSION_MINOR
+ '.', COMPILER_VERSION_MINOR,
+# ifdef COMPILER_VERSION_PATCH
+ '.', COMPILER_VERSION_PATCH,
+# ifdef COMPILER_VERSION_TWEAK
+ '.', COMPILER_VERSION_TWEAK,
+# endif
+# endif
+# endif
+ ']','\0'};
+#endif
+
+/* Construct a string literal encoding the internal version number. */
+#ifdef COMPILER_VERSION_INTERNAL
+char const info_version_internal[] = {
+ 'I', 'N', 'F', 'O', ':',
+ 'c','o','m','p','i','l','e','r','_','v','e','r','s','i','o','n','_',
+ 'i','n','t','e','r','n','a','l','[',
+ COMPILER_VERSION_INTERNAL,']','\0'};
+#endif
+
+/* Construct a string literal encoding the version number components. */
+#ifdef SIMULATE_VERSION_MAJOR
+char const info_simulate_version[] = {
+ 'I', 'N', 'F', 'O', ':',
+ 's','i','m','u','l','a','t','e','_','v','e','r','s','i','o','n','[',
+ SIMULATE_VERSION_MAJOR,
+# ifdef SIMULATE_VERSION_MINOR
+ '.', SIMULATE_VERSION_MINOR,
+# ifdef SIMULATE_VERSION_PATCH
+ '.', SIMULATE_VERSION_PATCH,
+# ifdef SIMULATE_VERSION_TWEAK
+ '.', SIMULATE_VERSION_TWEAK,
+# endif
+# endif
+# endif
+ ']','\0'};
+#endif
+
+/* Construct the string literal in pieces to prevent the source from
+ getting matched. Store it in a pointer rather than an array
+ because some compilers will just produce instructions to fill the
+ array rather than assigning a pointer to a static array. */
+char const* info_platform = "INFO" ":" "platform[" PLATFORM_ID "]";
+char const* info_arch = "INFO" ":" "arch[" ARCHITECTURE_ID "]";
+
+
+
+
+#if !defined(__STDC__)
+# if (defined(_MSC_VER) && !defined(__clang__)) \
+ || (defined(__ibmxl__) || defined(__IBMC__))
+# define C_DIALECT "90"
+# else
+# define C_DIALECT
+# endif
+#elif __STDC_VERSION__ >= 201000L
+# define C_DIALECT "11"
+#elif __STDC_VERSION__ >= 199901L
+# define C_DIALECT "99"
+#else
+# define C_DIALECT "90"
+#endif
+const char* info_language_dialect_default =
+ "INFO" ":" "dialect_default[" C_DIALECT "]";
+
+/*--------------------------------------------------------------------------*/
+
+#ifdef ID_VOID_MAIN
+void main() {}
+#else
+# if defined(__CLASSIC_C__)
+int main(argc, argv) int argc; char *argv[];
+# else
+int main(int argc, char* argv[])
+# endif
+{
+ int require = 0;
+ require += info_compiler[argc];
+ require += info_platform[argc];
+ require += info_arch[argc];
+#ifdef COMPILER_VERSION_MAJOR
+ require += info_version[argc];
+#endif
+#ifdef COMPILER_VERSION_INTERNAL
+ require += info_version_internal[argc];
+#endif
+#ifdef SIMULATE_ID
+ require += info_simulate[argc];
+#endif
+#ifdef SIMULATE_VERSION_MAJOR
+ require += info_simulate_version[argc];
+#endif
+#if defined(__CRAYXE) || defined(__CRAYXC)
+ require += info_cray[argc];
+#endif
+ require += info_language_dialect_default[argc];
+ (void)argv;
+ return require;
+}
+#endif
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diff --git a/arkanoid/fonts.c b/arkanoid/fonts.c
new file mode 100755
index 0000000..3829052
--- /dev/null
+++ b/arkanoid/fonts.c
@@ -0,0 +1,1615 @@
+/* vim: set ai et ts=4 sw=4: */
+#include "fonts.h"
+const uint8_t plaao_logo[25608] = { 0X10,0X10,0X00,0X50,0X00,0XA0,0X01,0X1B,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0,
+0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0,
+0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0,
+0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60, 0x00, 0x60,
+0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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+0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0,
+0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
+0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40,
+0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40, 0x00, 0x40
+};
+
+// 97 numbers, 4 lines. This surely will not backfire.
+// Transposed font.
+const uint8_t Font4x6[] = {
+ 0b000000, 0b000000, 0b110000, 0b111010, 0b010010, 0b100001, 0b010101, 0b000000, 0b000000, 0b000000, 0b101000, 0b000000, 0b000000, 0b000000, 0b000000, 0b100000, 0b011110, 0b000000, 0b011001, 0b010110, 0b000100, 0b100110, 0b000110, 0b110000, 0b010110, 0b011110, 0b000000, 0b000000, 0b000000, 0b001010, 0b000100, 0b011000, 0b011110, 0b011111, 0b010110, 0b010010, 0b011110, 0b100001, 0b100000, 0b010111, 0b111111, 0b000000, 0b111110, 0b100011, 0b000001, 0b111111, 0b111111, 0b011110, 0b011000, 0b011101, 0b011011, 0b100110, 0b100000, 0b111110, 0b111110, 0b111111, 0b110111, 0b111000, 0b000000, 0b000000, 0b000001, 0b000000, 0b010000, 0b000001, 0b000000, 0b001111, 0b000110, 0b001010, 0b111111, 0b001101, 0b100000, 0b011110, 0b000111, 0b000000, 0b000000, 0b010001, 0b000000, 0b011111, 0b001111, 0b001110, 0b000000, 0b000000, 0b001000, 0b010010, 0b000001, 0b011110, 0b011110, 0b011111, 0b011011, 0b011110, 0b000000, 0b000000, 0b000000, 0b000100, 0b001000,
+ 0b000000, 0b000000, 0b000000, 0b010111, 0b111111, 0b011000, 0b100010, 0b110000, 0b100001, 0b011110, 0b010000, 0b000100, 0b000000, 0b000100, 0b000000, 0b011000, 0b101001, 0b000001, 0b100101, 0b101001, 0b111111, 0b101001, 0b101001, 0b101000, 0b101001, 0b100101, 0b000000, 0b000000, 0b010001, 0b001010, 0b001010, 0b100101, 0b101010, 0b100100, 0b101001, 0b100001, 0b100001, 0b101001, 0b101000, 0b100101, 0b001000, 0b100001, 0b100001, 0b010100, 0b000001, 0b010000, 0b001000, 0b100001, 0b100100, 0b100010, 0b100100, 0b101001, 0b100000, 0b000001, 0b000001, 0b000010, 0b001000, 0b000111, 0b110001, 0b100001, 0b000110, 0b111111, 0b100000, 0b000001, 0b000000, 0b010101, 0b001001, 0b010001, 0b001001, 0b010101, 0b101000, 0b010101, 0b001000, 0b000001, 0b101110, 0b001010, 0b000001, 0b001000, 0b010000, 0b010001, 0b001100, 0b011111, 0b010000, 0b010101, 0b010001, 0b000001, 0b000001, 0b000010, 0b000100, 0b000101, 0b011001, 0b100001, 0b111111, 0b011010, 0b000100,
+ 0b000000, 0b111101, 0b110000, 0b111010, 0b010101, 0b000110, 0b100101, 0b000000, 0b011110, 0b100001, 0b101000, 0b001110, 0b000011, 0b000100, 0b000010, 0b000110, 0b100101, 0b111111, 0b100101, 0b100001, 0b010100, 0b101001, 0b101001, 0b100111, 0b101001, 0b100101, 0b010010, 0b010011, 0b001010, 0b001010, 0b010001, 0b100000, 0b101111, 0b100100, 0b101001, 0b100001, 0b100001, 0b101001, 0b101000, 0b100001, 0b001000, 0b111111, 0b100001, 0b001000, 0b000001, 0b010000, 0b010000, 0b100001, 0b100100, 0b100001, 0b100100, 0b101001, 0b111111, 0b000001, 0b000010, 0b000010, 0b001000, 0b001000, 0b101101, 0b111111, 0b011000, 0b100001, 0b010000, 0b000001, 0b010000, 0b010101, 0b001001, 0b010001, 0b001001, 0b010101, 0b011111, 0b010101, 0b001000, 0b101111, 0b001001, 0b000100, 0b111111, 0b001000, 0b001000, 0b010001, 0b010010, 0b010010, 0b001000, 0b010101, 0b111110, 0b000001, 0b000010, 0b000010, 0b000100, 0b000101, 0b010101, 0b011010, 0b000000, 0b100001, 0b001000,
+ 0b000000, 0b000000, 0b000000, 0b010111, 0b001001, 0b100001, 0b011011, 0b000000, 0b000000, 0b000000, 0b000000, 0b000100, 0b000000, 0b000000, 0b000000, 0b000001, 0b011110, 0b010001, 0b010011, 0b010010, 0b001100, 0b111010, 0b011110, 0b100000, 0b010110, 0b011000, 0b000000, 0b000000, 0b000100, 0b001010, 0b000000, 0b000000, 0b010010, 0b011111, 0b111111, 0b011110, 0b111111, 0b111111, 0b111111, 0b011110, 0b111111, 0b100001, 0b000010, 0b111111, 0b111111, 0b111111, 0b111111, 0b011110, 0b111111, 0b011110, 0b111111, 0b010001, 0b100000, 0b111110, 0b111100, 0b111111, 0b110111, 0b110000, 0b100011, 0b000000, 0b100000, 0b000000, 0b000000, 0b000001, 0b100000, 0b000010, 0b111111, 0b001110, 0b000110, 0b001110, 0b001000, 0b001001, 0b111111, 0b001001, 0b000001, 0b111111, 0b100001, 0b011111, 0b011111, 0b001110, 0b011111, 0b001100, 0b011111, 0b001001, 0b010000, 0b011110, 0b011100, 0b011111, 0b011011, 0b011001, 0b010011, 0b000100, 0b000000, 0b000000, 0b000100
+};
+
+// !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~
diff --git a/arkanoid/fonts.h b/arkanoid/fonts.h
new file mode 100755
index 0000000..ebbccf0
--- /dev/null
+++ b/arkanoid/fonts.h
@@ -0,0 +1,10 @@
+/* vim: set ai et ts=4 sw=4: */
+#ifndef __FONTS_H__
+#define __FONTS_H__
+
+#include <stdint.h>
+
+extern const uint8_t plaao_logo[25608];
+extern const uint8_t Font4x6[];
+
+#endif // __FONTS_H__
diff --git a/arkanoid/install.sh b/arkanoid/install.sh
new file mode 100755
index 0000000..5a982e8
--- /dev/null
+++ b/arkanoid/install.sh
@@ -0,0 +1,19 @@
+#!/usr/bin/bash
+
+./compile.sh
+[[ $? -eq 0 ]] || exit
+
+i=0
+
+while true ; do
+ sudo mount /dev/sdb1 pico_mountpoint
+ [[ $? -ne 0 ]] || break
+ echo "Trying to mount... Try #$i"
+ ((i++))
+ sleep 0.5
+done
+
+echo "Flashing uf2..."
+sudo cp main.uf2 pico_mountpoint
+sudo umount pico_mountpoint
+echo "OK!"
\ No newline at end of file
diff --git a/arkanoid/levels.h b/arkanoid/levels.h
new file mode 100644
index 0000000..ca0c607
--- /dev/null
+++ b/arkanoid/levels.h
@@ -0,0 +1,91 @@
+#ifndef LEVELS_H
+#define LEVELS_H
+#include <stdint.h>
+
+#define col565(r, g, b) (((r & 0xF8) << 8) | ((g & 0xFC) << 3) | ((b & 0xF8) >> 3))
+#define c000 col565(0, 0, 0)
+#define c001 col565(0, 0, 192)
+#define c002 col565(0, 0, 255)
+
+#define c010 col565(0, 192, 0)
+#define c011 col565(0, 192, 192)
+#define c012 col565(0, 192, 255)
+
+#define c020 col565(0, 255, 0)
+#define c021 col565(0, 255, 192)
+#define c022 col565(0, 255, 255)
+
+#define c100 col565(192, 0, 0)
+#define c101 col565(192, 0, 192)
+#define c102 col565(192, 0, 255)
+
+#define c110 col565(192, 192, 0)
+#define c111 col565(192, 192, 192)
+#define c112 col565(192, 192, 255)
+
+#define c120 col565(192, 255, 0)
+#define c121 col565(192, 255, 192)
+#define c122 col565(192, 255, 255)
+
+#define c200 col565(255, 0, 0)
+#define c201 col565(255, 0, 192)
+#define c202 col565(255, 0, 255)
+
+#define c210 col565(255, 192, 0)
+#define c211 col565(255, 192, 192)
+#define c212 col565(255, 192, 255)
+
+#define c220 col565(255, 255, 0)
+#define c221 col565(255, 255, 192)
+#define c222 col565(255, 255, 255)
+
+#define MAX_LEVELS 2
+
+const static uint16_t levels[MAX_LEVELS][160] = {
+ {
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c000, c200, c200, c200, c200, c000, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c200, c000, c000, c000, c000, c200, c200,
+ c200, c200, c200, c000, c000, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c220, c220, c220, c220, c220, c220, c220, c220,
+ c221, c221, c221, c221, c221, c221, c221, c221,
+ c220, c220, c220, c220, c220, c220, c220, c220,
+ },
+
+ {
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c000, c000, c200, c200, c200,
+ c200, c200, c000, c000, c000, c000, c200, c200,
+ c200, c000, c000, c200, c200, c000, c000, c200,
+ c200, c000, c200, c200, c200, c200, c000, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c200, c200, c200, c200, c200, c200, c200, c200,
+ c220, c220, c220, c220, c220, c220, c220, c220,
+ c221, c221, c221, c221, c221, c221, c221, c221,
+ c220, c220, c220, c220, c220, c220, c220, c220,
+ }
+};
+#endif
diff --git a/arkanoid/main.c b/arkanoid/main.c
new file mode 100644
index 0000000..87e47b2
--- /dev/null
+++ b/arkanoid/main.c
@@ -0,0 +1,161 @@
+#include "pico/stdlib.h"
+#include "pico/pico4ml/screen.h"
+#include <math.h>
+#include <stdio.h>
+
+#include "pico/time.h"
+
+#include "balls.h"
+#include "fonts.h"
+#include "utils.h"
+#include "levels.h"
+
+// the size of the screen is 80x160. the size of the board is therefore 80x80 (the top half).
+// every block is 10x4 so the block size is 8x20 (160)
+uint16_t blocks[160];
+
+char score_text[30];
+char lives_text[30];
+
+int score = 0;
+int level = 1;
+int combo = 0;
+int lives = 5;
+int blocksLeft = 0;
+
+void draw_block(uint16_t blocks[], uint16_t block_index) {
+ uint8_t y = block_index / 8;
+ uint8_t x = block_index % 8;
+
+ uint16_t block = blocks[block_index];
+ if (block) {
+ ST7735_FillRectangle(x * 10, y * 4, 10, 4, change_color(block, 0.75));
+ ST7735_FillRectangle(x * 10 + 1, y * 4 + 1, 8, 2, block);
+ } else {
+ ST7735_FillRectangle(x * 10, y * 4, 10, 4, block);
+ }
+}
+
+void updateBottomText() {
+ if (combo >= 2) {
+ sprintf(score_text, "%dpts x%d", score, combo);
+ } else {
+ sprintf(score_text, "%dpts ", score);
+ }
+
+ sprintf(lives_text, "%d", lives);
+
+ ST7735_WriteString(2, 150, Font4x6, score_text, color32_to_16(0xf83800), ST7735_BLACK);
+ ST7735_WriteString(74, 150, Font4x6, lives_text, color32_to_16(0xf83800), ST7735_BLACK);
+}
+
+void set_level() {
+ printf("level size %d %d %d\n", sizeof(levels[0]), sizeof(levels[0][0]), sizeof(uint16_t));
+ memcpy(blocks, levels[(level - 1) % MAX_LEVELS], sizeof(blocks));
+
+ for (int i = 0; i < 160; i++) {
+ if (blocks[i]) {
+ blocksLeft += 1;
+ }
+
+ draw_block(blocks, i);
+ }
+}
+
+int main() {
+ stdio_init_all();
+ setvbuf ( stdout , NULL , _IONBF , 0 );
+ ST7735_Init();
+ ST7735_DrawImage(0, 0, 80, 160, plaao_logo);
+
+ printf("max levels %d\n", sizeof(levels));
+
+ const uint LED_PIN = 0;
+ const uint BUTTON1 = 20;
+ const uint BUTTON2 = 21;
+ const uint BUTTON3 = 22;
+
+ for (int i=18; i<28; i++) {
+ gpio_init(i);
+
+ if (i == 20 || i == 21 || i == 22) {
+ gpio_set_dir(i, GPIO_IN);
+ } else {
+ gpio_set_dir(i, GPIO_OUT);
+ }
+ }
+
+ ST7735_FillScreen(ST7735_BLACK);
+
+ set_level();
+
+ Ball playerBall = {
+ {43, 120},
+ {
+ {43, 120}, {43, 120}, {43, 120}, {43, 120}, {43, 120},
+ {43, 120}, {43, 120}, {43, 120}, {43, 120}, {43, 120},
+ {43, 120}, {43, 120}, {43, 120}, {43, 120}, {43, 120},
+ {43, 120}, {43, 120}, {43, 120}, {43, 120}, {43, 120},
+ {43, 120}, {43, 120}, {43, 120}, {43, 120}, {43, 120},
+ },
+ 0, 0.9, 1, ST7735_CYAN, ST7735_BLUE, 2.4
+ };
+
+ Paddle playerPaddle;
+ playerPaddle.pos.x = 40;
+ playerPaddle.pos.y = 140;
+ playerPaddle.color = color_to_rgb(192, 192, 192);
+ playerPaddle.borderColor = change_color(playerPaddle.color, 0.75);
+ playerPaddle.length = 24;
+ playerPaddle.moveSpeed = 2;
+
+ updateBottomText();
+
+ while (true) {
+ int16_t hit_status = ballPhysicsStep(&playerBall, &playerPaddle, blocks);
+ if (hit_status != BALL_HIT_NOTHING) {
+ if (hit_status == BALL_HIT_PADDLE) {
+ combo = 0;
+ } else if (hit_status == BALL_DIED) {
+ combo = 0;
+ lives -= 1;
+ } else {
+ draw_block(blocks, hit_status);
+ combo += 1;
+
+ if (combo >= 9) {
+ combo = 9;
+ }
+
+ score += 100 * level * combo;
+ blocksLeft -= 1;
+ }
+
+ updateBottomText();
+
+ if (lives <= 0) {
+ ST7735_FillRectangle(0, 72, 80, 10, ST7735_BLACK);
+ ST7735_WriteString(20, 75, Font4x6, "GAME END", color32_to_16(0xf83800), ST7735_BLACK);
+ break;
+ }
+
+ if (blocksLeft <= 10) {
+ ST7735_FillRectangle(0, 72, 80, 10, ST7735_BLACK);
+ ST7735_WriteString(10, 75, Font4x6, "LEVEL CLEARED", color32_to_16(0xf83800), ST7735_BLACK);
+ sleep_ms(2000);
+ ST7735_FillRectangle(0, 72, 80, 10, ST7735_BLACK);
+
+ resetBall(&playerBall);
+ level += 1;
+ set_level();
+ }
+ }
+
+ drawBallTrail(&playerBall);
+
+ paddlePhysicsStep(&playerPaddle);
+ drawPaddle(&playerPaddle);
+
+ sleep_us(1000000 / 60);
+ }
+}
\ No newline at end of file
diff --git a/arkanoid/main.elf b/arkanoid/main.elf
new file mode 100755
index 0000000000000000000000000000000000000000..06bd2da4ac174dde364fe35e693a054f4dd9d02f
GIT binary patch
literal 903020
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z(GVC7fzc2c4S~@R7!85Z5Eu=C(GVC7fzc2c4S~@R7!85Z5Eu=C(GVC7fzc2c4S~@R
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diff --git a/arkanoid/pico/binary_info.h b/arkanoid/pico/binary_info.h
new file mode 100644
index 0000000..730cfa5
--- /dev/null
+++ b/arkanoid/pico/binary_info.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_H
+#define _PICO_BINARY_INFO_H
+
+/** \file binary_info.h
+ * \defgroup pico_binary_info pico_binary_info
+ *
+ * Binary info is intended for embedding machine readable information with the binary in FLASH.
+ *
+ * Example uses include:
+ *
+ * - Program identification / information
+ * - Pin layouts
+ * - Included features
+ * - Identifying flash regions used as block devices/storage
+ */
+
+#include "defs.h"
+#include "structure.h"
+#if !PICO_ON_DEVICE && !defined(PICO_NO_BINARY_INFO)
+#define PICO_NO_BINARY_INFO 1
+#endif
+#if !PICO_NO_BINARY_INFO
+#include "code.h"
+#endif
+#endif
diff --git a/arkanoid/pico/bit_ops.h b/arkanoid/pico/bit_ops.h
new file mode 100644
index 0000000..7b63c1d
--- /dev/null
+++ b/arkanoid/pico/bit_ops.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BIT_OPS_H
+#define _PICO_BIT_OPS_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file bit_ops.h
+* \defgroup pico_bit_ops pico_bit_ops
+*
+* Optimized bit manipulation functions.
+* Additionally provides replacement implementations of the compiler built-ins __builtin_popcount, __builtin_clz
+* and __bulitin_ctz
+*/
+
+/*! \brief Reverse the bits in a 32 bit word
+ * \ingroup pico_bit_ops
+ *
+ * \param bits 32 bit input
+ * \return the 32 input bits reversed
+ */
+uint32_t __rev(uint32_t bits);
+
+/*! \brief Reverse the bits in a 64 bit double word
+ * \ingroup pico_bit_ops
+ *
+ * \param bits 64 bit input
+ * \return the 64 input bits reversed
+ */
+uint64_t __revll(uint64_t bits);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/boot2/boot2_w25q080.S b/arkanoid/pico/boot2/boot2_w25q080.S
new file mode 100644
index 0000000..51bc7e9
--- /dev/null
+++ b/arkanoid/pico/boot2/boot2_w25q080.S
@@ -0,0 +1,295 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device: Winbond W25Q080
+// Also supports W25Q16JV (which has some different SR instructions)
+// Also supports AT25SF081
+// Also supports S25FL132K0
+//
+// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode
+//
+// Details: * Check status register 2 to determine if QSPI mode is enabled,
+// and perform an SR2 programming cycle if necessary.
+// * Use SSI to perform a dummy 0xEB read command, with the mode
+// continuation bits set, so that the flash will not require
+// 0xEB instruction prefix on subsequent reads.
+// * Configure SSI to write address, mode bits, but no instruction.
+// SSI + flash are now jointly in a state where continuous reads
+// can take place.
+// * Jump to exit pointer passed in via lr. Bootrom passes null,
+// in which case this code uses a default 256 byte flash offset
+//
+// Building: * This code must be position-independent, and use stack only
+// * The code will be padded to a size of 256 bytes, including a
+// 4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "helpers/asm_helper.S"
+#include "../hardware/regs/addressmap.h"
+#include "../hardware/regs/ssi.h"
+#include "../hardware/regs/pads_qspi.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+#if PICO_FLASH_SPI_CLKDIV & 1
+#error PICO_FLASH_SPI_CLKDIV must be even
+#endif
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence.
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0xa0
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
+// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS2 0x35
+#define CMD_WRITE_STATUS 0x01
+#define SREG_DATA 0x02 // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.section .boot2, "ax" // TODO - was .text
+
+// The exit point is passed in lr. If entered from bootrom, this will be the
+// flash address immediately following this second stage (0x10000100).
+// Otherwise it will be a return address -- second stage being called as a
+// function by user code, after copying out of XIP region. r3 holds SSI base,
+// r0...2 used as temporaries. Other GPRs not used.
+.global _stage2_boot
+.type _stage2_boot,%function
+.thumb_func
+_stage2_boot:
+ push {lr}
+
+ // Set pad configuration:
+ // - SCLK 8mA drive, no slew limiting
+ // - SDx disable input Schmitt to reduce delay
+
+ ldr r3, =PADS_QSPI_BASE
+ movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
+ ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+ movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
+ bics r0, r1
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
+ str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
+
+ ldr r3, =XIP_SSI_BASE
+
+ // Disable SSI to allow further config
+ movs r1, #0
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+
+ // Set baud rate
+ movs r1, #PICO_FLASH_SPI_CLKDIV
+ str r1, [r3, #SSI_BAUDR_OFFSET]
+
+ // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
+ // if the flash launches data on SCLK posedge, we capture it at the time that
+ // the next SCLK posedge is launched. This is shortly before that posedge
+ // arrives at the flash, so data hold time should be ok. For
+ // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
+
+ movs r1, #1
+ movs r2, #SSI_RX_SAMPLE_DLY_OFFSET // == 0xf0 so need 8 bits of offset significance
+ str r1, [r3, r2]
+
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+ (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+ (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+ ldr r1, =(CTRL0_SPI_TXRX)
+ str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+ // Enable SSI and select slave 0
+ movs r1, #1
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+
+ // Check whether SR needs updating
+ movs r0, #CMD_READ_STATUS2
+ bl read_flash_sreg
+ movs r2, #SREG_DATA
+ cmp r0, r2
+ beq skip_sreg_programming
+
+ // Send write enable command
+ movs r1, #CMD_WRITE_ENABLE
+ str r1, [r3, #SSI_DR0_OFFSET]
+
+ // Poll for completion and discard RX
+ bl wait_ssi_ready
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+
+ // Send status write command followed by data bytes
+ movs r1, #CMD_WRITE_STATUS
+ str r1, [r3, #SSI_DR0_OFFSET]
+ movs r0, #0
+ str r0, [r3, #SSI_DR0_OFFSET]
+ str r2, [r3, #SSI_DR0_OFFSET]
+
+ bl wait_ssi_ready
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+ ldr r1, [r3, #SSI_DR0_OFFSET]
+
+ // Poll status register for write completion
+1:
+ movs r0, #CMD_READ_STATUS
+ bl read_flash_sreg
+ movs r1, #1
+ tst r0, r1
+ bne 1b
+
+skip_sreg_programming:
+
+ // Disable SSI again so that it can be reconfigured
+ movs r1, #0
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+// Currently the flash expects an 8 bit serial command prefix on every
+// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
+// command, with mode bits set such that the flash will not expect a serial
+// command prefix on *subsequent* transfers. We don't care about the results
+// of the read, the important part is the mode bits.
+
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+ (FRAME_FORMAT /* Quad I/O mode */ \
+ << SSI_CTRLR0_SPI_FRF_LSB) | \
+ (31 << SSI_CTRLR0_DFS_32_LSB) | /* 32 data bits */ \
+ (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ /* Send INST/ADDR, Receive Data */ \
+ << SSI_CTRLR0_TMOD_LSB)
+
+ ldr r1, =(CTRLR0_ENTER_XIP)
+ str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+ movs r1, #0x0 // NDF=0 (single 32b read)
+ str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+ (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Address + mode bits */ \
+ (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+ (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+ << SSI_SPI_CTRLR0_INST_L_LSB) | /* 8-bit instruction */ \
+ (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A /* Send Command in serial mode then address in Quad I/O mode */ \
+ << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+ ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+ ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET) // SPI_CTRL0 Register
+ str r1, [r0]
+
+ movs r1, #1 // Re-enable SSI
+ str r1, [r3, #SSI_SSIENR_OFFSET]
+
+ movs r1, #CMD_READ
+ str r1, [r3, #SSI_DR0_OFFSET] // Push SPI command into TX FIFO
+ movs r1, #MODE_CONTINUOUS_READ // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+ str r1, [r3, #SSI_DR0_OFFSET] // Push Address into TX FIFO - this will trigger the transaction
+
+ // Poll for completion
+ bl wait_ssi_ready
+
+// The flash is in a state where we can blast addresses in parallel, and get
+// parallel data back. Now configure the SSI to translate XIP bus accesses
+// into QSPI transfers of this form.
+
+ movs r1, #0
+ str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+// INST_L_0_BITS {ADDR[23:0],XIP_CMD[7:0]} Load "mode bits" into XIP_CMD
+// Anything else {XIP_CMD[7:0],ADDR[23:0]} Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+ (MODE_CONTINUOUS_READ /* Mode bits to keep flash in continuous read mode */ \
+ << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+ (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) | /* Total number of address + mode bits */ \
+ (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+ (SSI_SPI_CTRLR0_INST_L_VALUE_NONE /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+ << SSI_SPI_CTRLR0_INST_L_LSB) | \
+ (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+ << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+ ldr r1, =(SPI_CTRLR0_XIP)
+ ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+ str r1, [r0]
+
+ movs r1, #1
+ str r1, [r3, #SSI_SSIENR_OFFSET] // Re-enable SSI
+
+// Bus accesses to the XIP window will now be transparently serviced by the
+// external flash on cache miss. We are ready to run code from flash.
+
+// Pull in standard exit routine
+#include "helpers/exit_from_boot2.S"
+
+// Common functions
+#include "helpers/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "helpers/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+
+
+
+
+
+// TODO - copied pad+checksum
+.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a
+
+.end
diff --git a/arkanoid/pico/boot2/copied_boot2.S.ignore b/arkanoid/pico/boot2/copied_boot2.S.ignore
new file mode 100644
index 0000000..ec0419d
--- /dev/null
+++ b/arkanoid/pico/boot2/copied_boot2.S.ignore
@@ -0,0 +1,22 @@
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.section .rrr, "ax"
+
+.byte 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60
+.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61
+.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20
+.byte 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0
+.byte 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0
+.byte 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21
+.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60
+.byte 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21
+.byte 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60
+.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49
+.byte 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20
+.byte 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66
+.byte 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40
+.byte 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00
+.byte 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0
+.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a
diff --git a/arkanoid/pico/boot2/helpers/asm_helper.S b/arkanoid/pico/boot2/helpers/asm_helper.S
new file mode 100644
index 0000000..10bd2f5
--- /dev/null
+++ b/arkanoid/pico/boot2/helpers/asm_helper.S
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../../pico.h"
+
+// do not put align in here as it is used mid function sometimes
+.macro regular_func x
+.global \x
+.type \x,%function
+.thumb_func
+\x:
+.endm
+
+.macro regular_func_with_section x
+.section .text.\x
+regular_func \x
+.endm
+
+// do not put align in here as it is used mid function sometimes
+.macro wrapper_func x
+regular_func WRAPPER_FUNC_NAME(\x)
+.endm
+
+.macro __pre_init func, priority_string
+.section .preinit_array.\priority_string
+.align 2
+.word \func
+.endm
+
diff --git a/arkanoid/pico/boot2/helpers/exit_from_boot2.S b/arkanoid/pico/boot2/helpers/exit_from_boot2.S
new file mode 100644
index 0000000..d48d0bd
--- /dev/null
+++ b/arkanoid/pico/boot2/helpers/exit_from_boot2.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2
+#define _BOOT2_HELPER_EXIT_FROM_BOOT2
+
+#include "../../hardware/regs/m0plus.h"
+
+// If entered from the bootrom, lr (which we earlier pushed) will be 0,
+// and we vector through the table at the start of the main flash image.
+// Any regular function call will have a nonzero value for lr.
+check_return:
+ pop {r0}
+ cmp r0, #0
+ beq vector_into_flash
+ bx r0
+vector_into_flash:
+ ldr r0, =(XIP_BASE + 0x100)
+ ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
+ str r0, [r1]
+ ldmia r0, {r0, r1}
+ msr msp, r0
+ bx r1
+
+#endif
diff --git a/arkanoid/pico/boot2/helpers/read_flash_sreg.S b/arkanoid/pico/boot2/helpers/read_flash_sreg.S
new file mode 100644
index 0000000..1c68e49
--- /dev/null
+++ b/arkanoid/pico/boot2/helpers/read_flash_sreg.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_READ_FLASH_SREG
+#define _BOOT2_HELPER_READ_FLASH_SREG
+
+#include "wait_ssi_ready.S"
+
+// Pass status read cmd into r0.
+// Returns status value in r0.
+.global read_flash_sreg
+.type read_flash_sreg,%function
+.thumb_func
+read_flash_sreg:
+ push {r1, lr}
+ str r0, [r3, #SSI_DR0_OFFSET]
+ // Dummy byte:
+ str r0, [r3, #SSI_DR0_OFFSET]
+
+ bl wait_ssi_ready
+ // Discard first byte and combine the next two
+ ldr r0, [r3, #SSI_DR0_OFFSET]
+ ldr r0, [r3, #SSI_DR0_OFFSET]
+
+ pop {r1, pc}
+
+#endif
diff --git a/arkanoid/pico/boot2/helpers/wait_ssi_ready.S b/arkanoid/pico/boot2/helpers/wait_ssi_ready.S
new file mode 100644
index 0000000..2e49b64
--- /dev/null
+++ b/arkanoid/pico/boot2/helpers/wait_ssi_ready.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_WAIT_SSI_READY
+#define _BOOT2_HELPER_WAIT_SSI_READY
+
+wait_ssi_ready:
+ push {r0, r1, lr}
+
+ // Command is complete when there is nothing left to send
+ // (TX FIFO empty) and SSI is no longer busy (CSn deasserted)
+1:
+ ldr r1, [r3, #SSI_SR_OFFSET]
+ movs r0, #SSI_SR_TFE_BITS
+ tst r1, r0
+ beq 1b
+ movs r0, #SSI_SR_BUSY_BITS
+ tst r1, r0
+ bne 1b
+
+ pop {r0, r1, pc}
+
+#endif
diff --git a/arkanoid/pico/bootrom.c b/arkanoid/pico/bootrom.c
new file mode 100644
index 0000000..5a6c361
--- /dev/null
+++ b/arkanoid/pico/bootrom.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "bootrom.h"
+
+/// \tag::table_lookup[]
+
+// Bootrom function: rom_table_lookup
+// Returns the 32 bit pointer into the ROM if found or NULL otherwise.
+typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
+
+// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
+#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
+
+void *rom_func_lookup(uint32_t code) {
+ return rom_func_lookup_inline(code);
+}
+
+void *rom_data_lookup(uint32_t code) {
+ rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18);
+ uint16_t *data_table = (uint16_t *) rom_hword_as_ptr(0x16);
+ return rom_table_lookup(data_table, code);
+}
+/// \end::table_lookup[]
+
+bool rom_funcs_lookup(uint32_t *table, unsigned int count) {
+ bool ok = true;
+ for (unsigned int i = 0; i < count; i++) {
+ table[i] = (uintptr_t) rom_func_lookup(table[i]);
+ if (!table[i]) ok = false;
+ }
+ return ok;
+}
diff --git a/arkanoid/pico/bootrom.h b/arkanoid/pico/bootrom.h
new file mode 100644
index 0000000..e557893
--- /dev/null
+++ b/arkanoid/pico/bootrom.h
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_BOOTROM_H
+#define _PLATFORM_BOOTROM_H
+
+#include "pico.h"
+
+/** \file bootrom.h
+ * \defgroup pico_bootrom pico_bootrom
+ * Access to functions and data in the RP2040 bootrom
+ *
+ * This header may be included by assembly code
+ */
+
+// ROM FUNCTIONS
+
+#define ROM_FUNC_POPCOUNT32 ROM_TABLE_CODE('P', '3')
+#define ROM_FUNC_REVERSE32 ROM_TABLE_CODE('R', '3')
+#define ROM_FUNC_CLZ32 ROM_TABLE_CODE('L', '3')
+#define ROM_FUNC_CTZ32 ROM_TABLE_CODE('T', '3')
+#define ROM_FUNC_MEMSET ROM_TABLE_CODE('M', 'S')
+#define ROM_FUNC_MEMSET4 ROM_TABLE_CODE('S', '4')
+#define ROM_FUNC_MEMCPY ROM_TABLE_CODE('M', 'C')
+#define ROM_FUNC_MEMCPY44 ROM_TABLE_CODE('C', '4')
+#define ROM_FUNC_RESET_USB_BOOT ROM_TABLE_CODE('U', 'B')
+#define ROM_FUNC_CONNECT_INTERNAL_FLASH ROM_TABLE_CODE('I', 'F')
+#define ROM_FUNC_FLASH_EXIT_XIP ROM_TABLE_CODE('E', 'X')
+#define ROM_FUNC_FLASH_RANGE_ERASE ROM_TABLE_CODE('R', 'E')
+#define ROM_FUNC_FLASH_RANGE_PROGRAM ROM_TABLE_CODE('R', 'P')
+#define ROM_FUNC_FLASH_FLUSH_CACHE ROM_TABLE_CODE('F', 'C')
+#define ROM_FUNC_FLASH_ENTER_CMD_XIP ROM_TABLE_CODE('C', 'X')
+
+/*! \brief Return a bootrom lookup code based on two ASCII characters
+ * \ingroup pico_bootrom
+ *
+ * These codes are uses to lookup data or function addresses in the bootrom
+ *
+ * \param c1 the first character
+ * \param c2 the second character
+ * \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
+ */
+#define ROM_TABLE_CODE(c1, c2) ((c1) | ((c2) << 8))
+
+#ifndef __ASSEMBLER__
+
+// ROM FUNCTION SIGNATURES
+
+typedef uint32_t (*rom_popcount32_fn)(uint32_t);
+typedef uint32_t (*rom_reverse32_fn)(uint32_t);
+typedef uint32_t (*rom_clz32_fn)(uint32_t);
+typedef uint32_t (*rom_ctz32_fn)(uint32_t);
+typedef uint8_t *(*rom_memset_fn)(uint8_t *, uint8_t, uint32_t);
+typedef uint32_t *(*rom_memset4_fn)(uint32_t *, uint8_t, uint32_t);
+typedef uint32_t *(*rom_memcpy_fn)(uint8_t *, const uint8_t *, uint32_t);
+typedef uint32_t *(*rom_memcpy44_fn)(uint32_t *, const uint32_t *, uint32_t);
+typedef void __attribute__((noreturn)) (*rom_reset_usb_boot_fn)(uint32_t, uint32_t);
+typedef rom_reset_usb_boot_fn reset_usb_boot_fn; // kept for backwards compatibility
+typedef void (*rom_connect_internal_flash_fn)(void);
+typedef void (*rom_flash_exit_xip_fn)(void);
+typedef void (*rom_flash_range_erase_fn)(uint32_t, size_t, uint32_t, uint8_t);
+typedef void (*rom_flash_range_program_fn)(uint32_t, const uint8_t*, size_t);
+typedef void (*rom_flash_flush_cache_fn)(void);
+typedef void (*rom_flash_enter_cmd_xip_fn)(void);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Return a bootrom lookup code based on two ASCII characters
+ * \ingroup pico_bootrom
+ *
+ * These codes are uses to lookup data or function addresses in the bootrom
+ *
+ * \param c1 the first character
+ * \param c2 the second character
+ * \return the 'code' to use in rom_func_lookup() or rom_data_lookup()
+ */
+static inline uint32_t rom_table_code(uint8_t c1, uint8_t c2) {
+ return ROM_TABLE_CODE((uint32_t) c1, (uint32_t) c2);
+}
+
+/*!
+ * \brief Lookup a bootrom function by code
+ * \ingroup pico_bootrom
+ * \param code the code
+ * \return a pointer to the function, or NULL if the code does not match any bootrom function
+ */
+void *rom_func_lookup(uint32_t code);
+
+/*!
+ * \brief Lookup a bootrom address by code
+ * \ingroup pico_bootrom
+ * \param code the code
+ * \return a pointer to the data, or NULL if the code does not match any bootrom function
+ */
+void *rom_data_lookup(uint32_t code);
+
+/*!
+ * \brief Helper function to lookup the addresses of multiple bootrom functions
+ * \ingroup pico_bootrom
+ *
+ * This method looks up the 'codes' in the table, and convert each table entry to the looked up
+ * function pointer, if there is a function for that code in the bootrom.
+ *
+ * \param table an IN/OUT array, elements are codes on input, function pointers on success.
+ * \param count the number of elements in the table
+ * \return true if all the codes were found, and converted to function pointers, false otherwise
+ */
+bool rom_funcs_lookup(uint32_t *table, unsigned int count);
+
+// Bootrom function: rom_table_lookup
+// Returns the 32 bit pointer into the ROM if found or NULL otherwise.
+typedef void *(*rom_table_lookup_fn)(uint16_t *table, uint32_t code);
+
+// Convert a 16 bit pointer stored at the given rom address into a 32 bit pointer
+#define rom_hword_as_ptr(rom_address) (void *)(uintptr_t)(*(uint16_t *)rom_address)
+
+/*!
+ * \brief Lookup a bootrom function by code. This method is forceably inlined into the caller for FLASH/RAM sensitive code usage
+ * \ingroup pico_bootrom
+ * \param code the code
+ * \return a pointer to the function, or NULL if the code does not match any bootrom function
+ */
+static __force_inline void *rom_func_lookup_inline(uint32_t code) {
+ rom_table_lookup_fn rom_table_lookup = (rom_table_lookup_fn) rom_hword_as_ptr(0x18);
+ uint16_t *func_table = (uint16_t *) rom_hword_as_ptr(0x14);
+ return rom_table_lookup(func_table, code);
+}
+
+/*!
+ * \brief Reboot the device into BOOTSEL mode
+ * \ingroup pico_bootrom
+ *
+ * This function reboots the device into the BOOTSEL mode ('usb boot").
+ *
+ * Facilities are provided to enable an "activity light" via GPIO attached LED for the USB Mass Storage Device,
+ * and to limit the USB interfaces exposed.
+ *
+ * \param usb_activity_gpio_pin_mask 0 No pins are used as per a cold boot. Otherwise a single bit set indicating which
+ * GPIO pin should be set to output and raised whenever there is mass storage activity
+ * from the host.
+ * \param disable_interface_mask value to control exposed interfaces
+ * - 0 To enable both interfaces (as per a cold boot)
+ * - 1 To disable the USB Mass Storage Interface
+ * - 2 To disable the USB PICOBOOT Interface
+ */
+static inline void __attribute__((noreturn)) reset_usb_boot(uint32_t usb_activity_gpio_pin_mask,
+ uint32_t disable_interface_mask) {
+ rom_reset_usb_boot_fn func = (rom_reset_usb_boot_fn) rom_func_lookup(ROM_FUNC_RESET_USB_BOOT);
+ func(usb_activity_gpio_pin_mask, disable_interface_mask);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // !__ASSEMBLER__
+#endif
diff --git a/arkanoid/pico/code.h b/arkanoid/pico/code.h
new file mode 100644
index 0000000..63afdbc
--- /dev/null
+++ b/arkanoid/pico/code.h
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_CODE_H
+#define _PICO_BINARY_INFO_CODE_H
+
+#include "pico.h"
+#include "structure.h"
+
+#if !PICO_NO_BINARY_INFO
+#define __bi_decl(name, bi, section_prefix, attr) static const attr __attribute__((section(section_prefix __STRING(name)))) struct _binary_info_core *name = bi
+#define __bi_lineno_var_name __CONCAT(__bi_, __LINE__)
+#define __bi_ptr_lineno_var_name __CONCAT(__bi_ptr, __LINE__)
+#define __bi_enclosure_check_lineno_var_name __CONCAT(_error_bi_is_missing_enclosing_decl_,__LINE__)
+#define __bi_mark_enclosure static const __unused int __bi_enclosure_check_lineno_var_name=0;
+#if !defined(__GNUC__) || __cplusplus || __GNUC__ >= 8
+#define __bi_enclosure_check(x) (x + __bi_enclosure_check_lineno_var_name)
+#else
+// skip the version check on older GCC non C++, as it doesn't compile.. this is only here to catch the
+// user accidentally forgetting to enclose the binary item with bi_decl
+#define __bi_enclosure_check(x) (x)
+#endif
+/**
+ * Declare some binary information that will be included if the contain source file/line is compiled into the binary
+ * \ingroup pico_binary_info
+ */
+#define bi_decl(_decl) __bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used);
+/**
+ * Declare some binary information that will be included if the function containing the decl is linked into the binary.
+ * The SDK uses --gc-sections, so functions that are never called will be removed by the linker, and any associated
+ * binary information declared this way will also be stripped
+ * \ingroup pico_binary_info
+ */
+#define bi_decl_if_func_used(_decl) ({__bi_mark_enclosure _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;});
+
+#define bi_decl_with_attr(_decl, _attr) __bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.keep.", __used);
+#define bi_decl_if_func_used_with_attr(_decl, _attr) ({__bi_mark_enclosure _attr _decl; __bi_decl(__bi_ptr_lineno_var_name, &__bi_lineno_var_name.core, ".binary_info.", ); *(volatile uint8_t *)&__bi_ptr_lineno_var_name;});
+#else
+#define __bi_decl(bi, name, attr)
+#define bi_decl_with_attr(_decl, _attr)
+#define bi_decl(_decl)
+#define bi_decl_if_func_used_with_attr(_decl, _attr) ((void)0);
+#define bi_decl_if_func_used(_decl) ((void)0);
+#endif
+
+#define bi_int(_tag, _id, _value) \
+ static const struct _binary_info_id_and_int __bi_lineno_var_name = { \
+ .core = { \
+ .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_INT), \
+ .tag = _tag, \
+ },\
+ .id = _id, \
+ .value = _value \
+ };
+
+#define bi_string(_tag, _id, _value) \
+ static const struct _binary_info_id_and_string __bi_lineno_var_name = { \
+ .core = { \
+ .type = __bi_enclosure_check(BINARY_INFO_TYPE_ID_AND_STRING), \
+ .tag = _tag, \
+ },\
+ .id = _id, \
+ .value = _value, \
+ }
+
+#define bi_block_device(_tag, _name, _address, _size, _extra, _flags) \
+ static const struct _binary_info_block_device __bi_lineno_var_name = { \
+ .core = { \
+ .type = __bi_enclosure_check(BINARY_INFO_TYPE_BLOCK_DEVICE), \
+ .tag = _tag, \
+ },\
+ .name = _name, \
+ .address = _address, \
+ .size = _size, \
+ .extra = _extra, \
+ .flags = _flags, \
+ }
+
+#define __bi_encoded_pins_with_func(_encoding) \
+ static const struct _binary_info_pins_with_func __bi_lineno_var_name = { \
+ .core = { \
+ .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_FUNC), \
+ .tag = BINARY_INFO_TAG_RASPBERRY_PI, \
+ },\
+ .pin_encoding = _encoding \
+ }
+
+#define __bi_pins_with_name(_mask, _label) \
+ static const struct _binary_info_pins_with_name __bi_lineno_var_name = { \
+ .core = { \
+ .type = __bi_enclosure_check(BINARY_INFO_TYPE_PINS_WITH_NAME), \
+ .tag = BINARY_INFO_TAG_RASPBERRY_PI, \
+ },\
+ .pin_mask = _mask, \
+ .label = _label \
+ }
+
+#define __bi_named_group(_parent_tag, _parent_id, _group_tag, _group_id, _label, _flags) \
+static const struct _binary_info_named_group __bi_lineno_var_name = { \
+ .core = { \
+ .type = __bi_enclosure_check(BINARY_INFO_TYPE_NAMED_GROUP), \
+ .tag = _parent_tag, \
+ },\
+ .parent_id = _parent_id, \
+ .group_tag = _group_tag, \
+ .flags = _flags, \
+ .group_id = _group_id, \
+ .label = _label \
+ }
+
+#define bi_binary_end(end) bi_int(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_BINARY_END, end)
+#define bi_program_name(name) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_NAME, name)
+#define bi_program_description(description) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION, description)
+#define bi_program_version_string(version_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING, version_string)
+#define bi_program_build_date_string(date_string) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING, date_string)
+#define bi_program_url(url) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_URL, url)
+// multiple of these may be added
+#define bi_program_feature(feature) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, feature)
+#define bi_program_build_attribute(attr) bi_string(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE, attr)
+#define bi_program_feature_group(tag, id, name) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, 0)
+#define bi_program_feature_group_with_flags(tag, id, name, flags) __bi_named_group(BINARY_INFO_TAG_RASPBERRY_PI, BINARY_INFO_ID_RP_PROGRAM_FEATURE, tag, id, name, flags)
+
+#define bi_1pin_with_func(p0, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p0) << 12))
+#define bi_2pins_with_func(p0, p1, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p1) << 17))
+#define bi_3pins_with_func(p0, p1, p2, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p2) << 22))
+#define bi_4pins_with_func(p0, p1, p2, p3, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p3) << 27))
+#define bi_5pins_with_func(p0, p1, p2, p3, p4, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_MULTI | ((func << 3)) | ((p0) << 7) | ((p1) << 12) | ((p2) << 17) | ((p3) << 22) | ((p4) << 27))
+#define bi_pin_range_with_func(plo, phi, func) __bi_encoded_pins_with_func(BI_PINS_ENCODING_RANGE | ((func << 3)) | ((plo) << 7) | ((phi) << 12))
+
+#define bi_pin_mask_with_name(pmask, label) __bi_pins_with_name((pmask), (label))
+// names are sperated by | ... i.e. "name1|name2|name3"
+#define bi_pin_mask_with_names(pmask, label) __bi_pins_with_name((pmask), (label))
+#define bi_1pin_with_name(p0, name) bi_pin_mask_with_name(1u << (p0), name)
+#define bi_2pins_with_names(p0, name0, p1, name1) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)), name0 "|" name1)
+#define bi_3pins_with_names(p0, name0, p1, name1, p2, name2) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)), name0 "|" name1 "|" name2)
+#define bi_4pins_with_names(p0, name0, p1, name1, p2, name2, p3, name3) bi_pin_mask_with_names((1u << (p0)) | (1u << (p1)) | (1u << (p2)) | (1u << (p3)), name0 "|" name1 "|" name2 "|" name3)
+
+#endif
diff --git a/arkanoid/pico/critical_section.c b/arkanoid/pico/critical_section.c
new file mode 100644
index 0000000..bdbb5f1
--- /dev/null
+++ b/arkanoid/pico/critical_section.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "critical_section.h"
+
+#if !PICO_NO_HARDWARE
+static_assert(sizeof(critical_section_t) == 8, "");
+#endif
+
+void critical_section_init(critical_section_t *crit_sec) {
+ critical_section_init_with_lock_num(crit_sec, (uint)spin_lock_claim_unused(true));
+}
+
+void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num) {
+ crit_sec->spin_lock = spin_lock_instance(lock_num);
+ __mem_fence_release();
+}
+
+void critical_section_deinit(critical_section_t *crit_sec) {
+ spin_lock_unclaim(spin_lock_get_num(crit_sec->spin_lock));
+#ifndef NDEBUG
+ crit_sec->spin_lock = (spin_lock_t *)-1;
+#endif
+}
\ No newline at end of file
diff --git a/arkanoid/pico/critical_section.h b/arkanoid/pico/critical_section.h
new file mode 100644
index 0000000..bbc6d73
--- /dev/null
+++ b/arkanoid/pico/critical_section.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_CRITICAL_SECTION_H
+#define _PLATFORM_CRITICAL_SECTION_H
+
+#include "lock_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file critical_section.h
+ * \defgroup critical_section critical_section
+ * \ingroup pico_sync
+ * \brief Critical Section API for short-lived mutual exclusion safe for IRQ and multi-core
+ *
+ * A critical section is non-reentrant, and provides mutual exclusion using a spin-lock to prevent access
+ * from the other core, and from (higher priority) interrupts on the same core. It does the former
+ * using a spin lock and the latter by disabling interrupts on the calling core.
+ *
+ * Because interrupts are disabled when a critical_section is owned, uses of the critical_section
+ * should be as short as possible.
+ */
+
+typedef struct __packed_aligned critical_section {
+ spin_lock_t *spin_lock;
+ uint32_t save;
+} critical_section_t;
+
+/*! \brief Initialise a critical_section structure allowing the system to assign a spin lock number
+ * \ingroup critical_section
+ *
+ * The critical section is initialized ready for use, and will use a (possibly shared) spin lock
+ * number assigned by the system. Note that in general it is unlikely that you would be nesting
+ * critical sections, however if you do so you *must* use \ref critical_section_init_with_lock_num
+ * to ensure that the spin lock's used are different.
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+void critical_section_init(critical_section_t *crit_sec);
+
+/*! \brief Initialise a critical_section structure assigning a specific spin lock number
+ * \ingroup critical_section
+ * \param crit_sec Pointer to critical_section structure
+ * \param lock_num the specific spin lock number to use
+ */
+void critical_section_init_with_lock_num(critical_section_t *crit_sec, uint lock_num);
+
+/*! \brief Enter a critical_section
+ * \ingroup critical_section
+ *
+ * If the spin lock associated with this critical section is in use, then this
+ * method will block until it is released.
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+static inline void critical_section_enter_blocking(critical_section_t *crit_sec) {
+ crit_sec->save = spin_lock_blocking(crit_sec->spin_lock);
+}
+
+/*! \brief Release a critical_section
+ * \ingroup critical_section
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+static inline void critical_section_exit(critical_section_t *crit_sec) {
+ spin_unlock(crit_sec->spin_lock, crit_sec->save);
+}
+
+/*! \brief De-Initialise a critical_section created by the critical_section_init method
+ * \ingroup critical_section
+ *
+ * This method is only used to free the associated spin lock allocated via
+ * the critical_section_init method (it should not be used to de-initialize a spin lock
+ * created via critical_section_init_with_lock_num). After this call, the critical section is invalid
+ *
+ * \param crit_sec Pointer to critical_section structure
+ */
+void critical_section_deinit(critical_section_t *crit_sec);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/crt0.S b/arkanoid/pico/crt0.S
new file mode 100644
index 0000000..5f18fe5
--- /dev/null
+++ b/arkanoid/pico/crt0.S
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/regs/m0plus.h"
+#include "hardware/regs/addressmap.h"
+#include "hardware/regs/sio.h"
+#include "defs.h"
+
+#ifdef NDEBUG
+#ifndef COLLAPSE_IRQS
+#define COLLAPSE_IRQS
+#endif
+#endif
+
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.section .vectors, "ax"
+.align 2
+
+.global __vectors, __VECTOR_TABLE
+__VECTOR_TABLE:
+__vectors:
+.word __StackTop
+.word _reset_handler
+.word isr_nmi
+.word isr_hardfault
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_svcall
+.word isr_invalid // Reserved, should never fire
+.word isr_invalid // Reserved, should never fire
+.word isr_pendsv
+.word isr_systick
+.word isr_irq0
+.word isr_irq1
+.word isr_irq2
+.word isr_irq3
+.word isr_irq4
+.word isr_irq5
+.word isr_irq6
+.word isr_irq7
+.word isr_irq8
+.word isr_irq9
+.word isr_irq10
+.word isr_irq11
+.word isr_irq12
+.word isr_irq13
+.word isr_irq14
+.word isr_irq15
+.word isr_irq16
+.word isr_irq17
+.word isr_irq18
+.word isr_irq19
+.word isr_irq20
+.word isr_irq21
+.word isr_irq22
+.word isr_irq23
+.word isr_irq24
+.word isr_irq25
+.word isr_irq26
+.word isr_irq27
+.word isr_irq28
+.word isr_irq29
+.word isr_irq30
+.word isr_irq31
+
+// all default exception handlers do nothing, and we can check for them being set to our
+// default values by seeing if they point to somewhere between __defaults_isrs_start and __default_isrs_end
+.global __default_isrs_start
+__default_isrs_start:
+
+// Declare a weak symbol for each ISR.
+// By default, they will fall through to the undefined IRQ handler below (breakpoint),
+// but can be overridden by C functions with correct name.
+
+.macro decl_isr_bkpt name
+.weak \name
+.type \name,%function
+.thumb_func
+\name:
+ bkpt #0
+.endm
+
+// these are separated out for clarity
+decl_isr_bkpt isr_invalid
+decl_isr_bkpt isr_nmi
+decl_isr_bkpt isr_hardfault
+decl_isr_bkpt isr_svcall
+decl_isr_bkpt isr_pendsv
+decl_isr_bkpt isr_systick
+
+.global __default_isrs_end
+__default_isrs_end:
+
+.macro decl_isr name
+.weak \name
+.type \name,%function
+.thumb_func
+\name:
+.endm
+
+decl_isr isr_irq0
+decl_isr isr_irq1
+decl_isr isr_irq2
+decl_isr isr_irq3
+decl_isr isr_irq4
+decl_isr isr_irq5
+decl_isr isr_irq6
+decl_isr isr_irq7
+decl_isr isr_irq8
+decl_isr isr_irq9
+decl_isr isr_irq10
+decl_isr isr_irq11
+decl_isr isr_irq12
+decl_isr isr_irq13
+decl_isr isr_irq14
+decl_isr isr_irq15
+decl_isr isr_irq16
+decl_isr isr_irq17
+decl_isr isr_irq18
+decl_isr isr_irq19
+decl_isr isr_irq20
+decl_isr isr_irq21
+decl_isr isr_irq22
+decl_isr isr_irq23
+decl_isr isr_irq24
+decl_isr isr_irq25
+decl_isr isr_irq26
+decl_isr isr_irq27
+decl_isr isr_irq28
+decl_isr isr_irq29
+decl_isr isr_irq30
+decl_isr isr_irq31
+
+// All unhandled USER IRQs fall through to here
+.global __unhandled_user_irq
+.thumb_func
+__unhandled_user_irq:
+ bl __get_current_exception
+ subs r0, #16
+.global unhandled_user_irq_num_in_r0
+unhandled_user_irq_num_in_r0:
+ bkpt #0
+
+// ----------------------------------------------------------------------------
+
+.section .binary_info_header, "a"
+
+// Header must be in first 256 bytes of main image (i.e. excluding flash boot2).
+// For flash builds we put it immediately after vector table; for NO_FLASH the
+// vectors are at a +0x100 offset because the bootrom enters RAM images directly
+// at their lowest address, so we put the header in the VTOR alignment hole.
+
+#if !PICO_NO_BINARY_INFO
+binary_info_header:
+.word BINARY_INFO_MARKER_START
+.word __binary_info_start
+.word __binary_info_end
+.word data_cpy_table // we may need to decode pointers that are in RAM at runtime.
+.word BINARY_INFO_MARKER_END
+#endif
+
+// ----------------------------------------------------------------------------
+
+.section .reset, "ax"
+
+// On flash builds, the vector table comes first in the image (conventional).
+// On NO_FLASH builds, the reset handler section comes first, as the entry
+// point is at offset 0 (fixed due to bootrom), and VTOR is highly-aligned.
+// Image is entered in various ways:
+//
+// - NO_FLASH builds are entered from beginning by UF2 bootloader
+//
+// - Flash builds vector through the table into _reset_handler from boot2
+//
+// - Either type can be entered via _entry_point by the debugger, and flash builds
+// must then be sent back round the boot sequence to properly initialise flash
+
+// ELF entry point:
+.type _entry_point,%function
+.thumb_func
+.global _entry_point
+_entry_point:
+
+#if PICO_NO_FLASH
+ // Vector through our own table (SP, VTOR will not have been set up at
+ // this point). Same path for debugger entry and bootloader entry.
+ ldr r0, =__vectors
+#else
+ // Debugger tried to run code after loading, so SSI is in 03h-only mode.
+ // Go back through bootrom + boot2 to properly initialise flash.
+ movs r0, #0
+#endif
+ ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
+ str r0, [r1]
+ ldmia r0!, {r1, r2}
+ msr msp, r1
+ bx r2
+
+// Reset handler:
+// - initialises .data
+// - clears .bss
+// - calls runtime_init
+// - calls main
+// - calls exit (which should eventually hang the processor via _exit)
+
+.type _reset_handler,%function
+.thumb_func
+_reset_handler:
+ // Only core 0 should run the C runtime startup code; core 1 is normally
+ // sleeping in the bootrom at this point but check to be sure
+ ldr r0, =(SIO_BASE + SIO_CPUID_OFFSET)
+ ldr r0, [r0]
+ cmp r0, #0
+ bne hold_non_core0_in_bootrom
+
+ adr r4, data_cpy_table
+
+ // assume there is at least one entry
+1:
+ ldmia r4!, {r1-r3}
+ cmp r1, #0
+ beq 2f
+ bl data_cpy
+ b 1b
+2:
+
+ // Zero out the BSS
+ ldr r1, =__bss_start__
+ ldr r2, =__bss_end__
+ movs r0, #0
+ b bss_fill_test
+bss_fill_loop:
+ stm r1!, {r0}
+bss_fill_test:
+ cmp r1, r2
+ bne bss_fill_loop
+
+platform_entry: // symbol for stack traces
+ // Use 32-bit jumps, in case these symbols are moved out of branch range
+ // (e.g. if main is in SRAM and crt0 in flash)
+ ldr r1, =runtime_init
+ blx r1
+ ldr r1, =main
+ blx r1
+ ldr r1, =exit
+ blx r1
+ // exit should not return. If it does, hang the core.
+ // (fall thru into our hang _exit impl
+.weak _exit
+.type _exit,%function
+.thumb_func
+_exit:
+1: // separate label because _exit can be moved out of branch range
+ bkpt #0
+ b 1b
+
+data_cpy_loop:
+ ldm r1!, {r0}
+ stm r2!, {r0}
+data_cpy:
+ cmp r2, r3
+ blo data_cpy_loop
+ bx lr
+
+.align 2
+data_cpy_table:
+#if PICO_COPY_TO_RAM
+.word __ram_text_source__
+.word __ram_text_start__
+.word __ram_text_end__
+#endif
+.word __etext
+.word __data_start__
+.word __data_end__
+
+.word __scratch_x_source__
+.word __scratch_x_start__
+.word __scratch_x_end__
+
+.word __scratch_y_source__
+.word __scratch_y_start__
+.word __scratch_y_end__
+
+.word 0 // null terminator
+
+// ----------------------------------------------------------------------------
+// Provide safe defaults for _exit and runtime_init
+// Full implementations usually provided by platform.c
+
+.weak runtime_init
+.type runtime_init,%function
+.thumb_func
+runtime_init:
+ bx lr
+
+// ----------------------------------------------------------------------------
+// If core 1 somehow gets into crt0 due to a spectacular VTOR mishap, we need to
+// catch it and send back to the sleep-and-launch code in the bootrom. Shouldn't
+// happen (it should sleep in the ROM until given an entry point via the
+// cross-core FIFOs) but it's good to be defensive.
+
+hold_non_core0_in_bootrom:
+ ldr r0, = 'W' | ('V' << 8)
+ bl rom_func_lookup
+ bx r0
+
+.global __get_current_exception
+.thumb_func
+__get_current_exception:
+ mrs r0, ipsr
+ uxtb r0, r0
+ bx lr
+
+// ----------------------------------------------------------------------------
+// Stack/heap dummies to set size
+
+.section .stack
+// align to allow for memory protection (although this alignment is pretty much ignored by linker script)
+.align 5
+ .equ StackSize, PICO_STACK_SIZE
+.space StackSize
+
+.section .heap
+.align 2
+ .equ HeapSize, PICO_HEAP_SIZE
+.space HeapSize
diff --git a/arkanoid/pico/datetime.c b/arkanoid/pico/datetime.c
new file mode 100644
index 0000000..cef3ef5
--- /dev/null
+++ b/arkanoid/pico/datetime.c
@@ -0,0 +1,41 @@
+#include "datetime.h"
+
+#include <stdio.h>
+
+static const char *DATETIME_MONTHS[12] = {
+ "January",
+ "February",
+ "March",
+ "April",
+ "May",
+ "June",
+ "July",
+ "August",
+ "September",
+ "October",
+ "November",
+ "December"
+};
+
+static const char *DATETIME_DOWS[7] = {
+ "Sunday",
+ "Monday",
+ "Tuesday",
+ "Wednesday",
+ "Thursday",
+ "Friday",
+ "Saturday",
+};
+
+void datetime_to_str(char *buf, uint buf_size, const datetime_t *t) {
+ snprintf(buf,
+ buf_size,
+ "%s %d %s %d:%02d:%02d %d",
+ DATETIME_DOWS[t->dotw],
+ t->day,
+ DATETIME_MONTHS[t->month - 1],
+ t->hour,
+ t->min,
+ t->sec,
+ t->year);
+};
\ No newline at end of file
diff --git a/arkanoid/pico/datetime.h b/arkanoid/pico/datetime.h
new file mode 100644
index 0000000..bb32835
--- /dev/null
+++ b/arkanoid/pico/datetime.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_DATETIME_H
+#define _PICO_DATETIME_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file datetime.h
+ * \defgroup util_datetime datetime
+ * \brief Date/Time formatting
+ * \ingroup pico_util
+ */
+
+/*! \brief Convert a datetime_t structure to a string
+ * \ingroup util_datetime
+ *
+ * \param buf character buffer to accept generated string
+ * \param buf_size The size of the passed in buffer
+ * \param t The datetime to be converted.
+ */
+void datetime_to_str(char *buf, uint buf_size, const datetime_t *t);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/defs.h b/arkanoid/pico/defs.h
new file mode 100644
index 0000000..407c0ac
--- /dev/null
+++ b/arkanoid/pico/defs.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_DEFS_H
+#define _PICO_BINARY_INFO_DEFS_H
+
+// this file is for pre-processor definitions only
+
+// should be found within the first 256 bytes of the real binary (i.e. after the flash second stage if a flash binary)
+//
+// Note the layout is:
+//
+// addr : BINARY_INFO_MARKER_START
+// addr+0x04 : __binary_info_start
+// addr+0x08 : __binary_info_end
+// addr+0x0c : __address_mapping_table
+// addr+0x10 | BINARY_INFO_MARKER_END
+//
+// __binary_info_start to __binary_info_end are the start, end (non inclusive) of an array
+// of pointers to binary_info_t structures
+//
+// __address_mapping_table is an array of the following items:
+//
+// uint32_t source_addr_start
+// uint32_t dest_addr_start
+// uint32_t dest_addr_end
+//
+// representing a mapping from the stored address in the binary/flash to addresses at runtime.
+// The linker will store pointers within the binary using their runtime values, however because of
+// "AT" mapping in the link script these addresses actually correspond to a different address in the binary
+// image. This mapping (which in the case of crt0.S is simply the data copy table used at initialization
+// to copy data into it's runtime location) can be used by picotool or others to reverse the mapping to find data
+// within the binary.
+//
+// Note the above array is terminated with a NULL source_addr_start
+
+#define BINARY_INFO_MARKER_START 0x7188ebf2
+#define BINARY_INFO_MARKER_END 0xe71aa390
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/divider.h b/arkanoid/pico/divider.h
new file mode 100644
index 0000000..da4e783
--- /dev/null
+++ b/arkanoid/pico/divider.h
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_DIVIDER_H_
+#define _PICO_DIVIDER_H_
+
+#include "pico.h"
+#include "hardware/divider.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup pico_divider pico_divider
+ * Optimized 32 and 64 bit division functions accelerated by the RP2040 hardware divider.
+ * Additionally provides integration with the C `/` and `%` operators
+ */
+
+/** \file divider.h
+* \brief High level APIs including combined quotient and remainder functions for 32 and 64 bit accelerated by the hardware divider
+* \ingroup pico_divider
+*
+* These functions all call __aeabi_idiv0 or __aebi_ldiv0 on division by zero
+* passing the largest applicably signed value
+*
+* Functions with unsafe in their name do not save/restore divider state, so are unsafe to call from interrupts. Unsafe functions are slightly faster.
+*/
+
+/**
+ * \brief Integer divide of two signed 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient
+ */
+int32_t div_s32s32(int32_t a, int32_t b);
+
+/**
+ * \brief Integer divide of two signed 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+static inline int32_t divmod_s32s32_rem(int32_t a, int32_t b, int32_t *rem) {
+ divmod_result_t r = hw_divider_divmod_s32(a, b);
+ *rem = to_remainder_s32(r);
+ return to_quotient_s32(r);
+}
+
+/**
+ * \brief Integer divide of two signed 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ */
+divmod_result_t divmod_s32s32(int32_t a, int32_t b);
+
+/**
+ * \brief Integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ */
+uint32_t div_u32u32(uint32_t a, uint32_t b);
+
+/**
+ * \brief Integer divide of two unsigned 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+static inline uint32_t divmod_u32u32_rem(uint32_t a, uint32_t b, uint32_t *rem) {
+ divmod_result_t r = hw_divider_divmod_u32(a, b);
+ *rem = to_remainder_u32(r);
+ return to_quotient_u32(r);
+}
+
+/**
+ * \brief Integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ */
+divmod_result_t divmod_u32u32(uint32_t a, uint32_t b);
+
+/**
+ * \brief Integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ */
+int64_t div_s64s64(int64_t a, int64_t b);
+
+/**
+ * \brief Integer divide of two signed 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+int64_t divmod_s64s64_rem(int64_t a, int64_t b, int64_t *rem);
+
+/**
+ * \brief Integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ */
+int64_t divmod_s64s64(int64_t a, int64_t b);
+
+/**
+ * \brief Integer divide of two unsigned 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ */
+uint64_t div_u64u64(uint64_t a, uint64_t b);
+
+/**
+ * \brief Integer divide of two unsigned 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ */
+uint64_t divmod_u64u64_rem(uint64_t a, uint64_t b, uint64_t *rem);
+
+
+/**
+ * \brief Integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ */
+uint64_t divmod_u64u64(uint64_t a, uint64_t b);
+
+// -----------------------------------------------------------------------
+// these "unsafe" functions are slightly faster, but do not save the divider state,
+// so are not generally safe to be called from interrupts
+// -----------------------------------------------------------------------
+
+/**
+ * \brief Unsafe integer divide of two signed 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient
+ *
+ * Do not use in interrupts
+ */
+int32_t div_s32s32_unsafe(int32_t a, int32_t b);
+
+/**
+ * \brief Unsafe integer divide of two signed 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+int32_t divmod_s32s32_rem_unsafe(int32_t a, int32_t b, int32_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ *
+ * Do not use in interrupts
+ */
+int64_t divmod_s32s32_unsafe(int32_t a, int32_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ *
+ * Do not use in interrupts
+ */
+uint32_t div_u32u32_unsafe(uint32_t a, uint32_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+uint32_t divmod_u32u32_rem_unsafe(uint32_t a, uint32_t b, uint32_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 32-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in low word/r0, remainder in high word/r1
+ *
+ * Do not use in interrupts
+ */
+uint64_t divmod_u32u32_unsafe(uint32_t a, uint32_t b);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ *
+ * Do not use in interrupts
+ */
+int64_t div_s64s64_unsafe(int64_t a, int64_t b);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+int64_t divmod_s64s64_rem_unsafe(int64_t a, int64_t b, int64_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ *
+ * Do not use in interrupts
+ */
+int64_t divmod_s64s64_unsafe(int64_t a, int64_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return Quotient
+ *
+ * Do not use in interrupts
+ */
+uint64_t div_u64u64_unsafe(uint64_t a, uint64_t b);
+
+/**
+ * \brief Unsafe integer divide of two unsigned 64-bit values, with remainder
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \param [out] rem The remainder of dividend/divisor
+ * \return Quotient result of dividend/divisor
+ *
+ * Do not use in interrupts
+ */
+uint64_t divmod_u64u64_rem_unsafe(uint64_t a, uint64_t b, uint64_t *rem);
+
+/**
+ * \brief Unsafe integer divide of two signed 64-bit values
+ * \ingroup pico_divider
+ *
+ * \param a Dividend
+ * \param b Divisor
+ * \return quotient in result (r0,r1), remainder in regs (r2, r3)
+ *
+ * Do not use in interrupts
+ */
+uint64_t divmod_u64u64_unsafe(uint64_t a, uint64_t b);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/doc.h b/arkanoid/pico/doc.h
new file mode 100644
index 0000000..4485b5d
--- /dev/null
+++ b/arkanoid/pico/doc.h
@@ -0,0 +1,4 @@
+/**
+ * \defgroup pico_util pico_util
+ * \brief Useful data structures and utility functions
+ */
diff --git a/arkanoid/pico/driver.h b/arkanoid/pico/driver.h
new file mode 100644
index 0000000..2d2fe17
--- /dev/null
+++ b/arkanoid/pico/driver.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_DRIVER_H
+#define _PICO_STDIO_DRIVER_H
+
+#include "stdio.h"
+#include "platform.h"
+
+struct stdio_driver {
+ void (*out_chars)(const char *buf, int len);
+ void (*out_flush)(void);
+ int (*in_chars)(char *buf, int len);
+ stdio_driver_t *next;
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+ bool last_ended_with_cr;
+ bool crlf_enabled;
+#endif
+};
+
+#endif
diff --git a/arkanoid/pico/hardware/adc.c b/arkanoid/pico/hardware/adc.c
new file mode 100644
index 0000000..c867734
--- /dev/null
+++ b/arkanoid/pico/hardware/adc.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../pico.h"
+#include "adc.h"
+#include "resets.h"
+
+void adc_init(void) {
+ // ADC is in an unknown state. We should start by resetting it
+ reset_block(RESETS_RESET_ADC_BITS);
+ unreset_block_wait(RESETS_RESET_ADC_BITS);
+
+ // Now turn it back on. Staging of clock etc is handled internally
+ adc_hw->cs = ADC_CS_EN_BITS;
+
+ // Internal staging completes in a few cycles, but poll to be sure
+ while (!(adc_hw->cs & ADC_CS_READY_BITS)) {
+ tight_loop_contents();
+ }
+}
diff --git a/arkanoid/pico/hardware/adc.h b/arkanoid/pico/hardware/adc.h
new file mode 100644
index 0000000..20059ea
--- /dev/null
+++ b/arkanoid/pico/hardware/adc.h
@@ -0,0 +1,257 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_ADC_H_
+#define _HARDWARE_ADC_H_
+
+#include "../pico.h"
+#include "structs/adc.h"
+#include "gpio.h"
+
+/** \file adc.h
+ * \defgroup hardware_adc hardware_adc
+ *
+ * Analog to Digital Converter (ADC) API
+ *
+ * The RP2040 has an internal analogue-digital converter (ADC) with the following features:
+ * - SAR ADC
+ * - 500 kS/s (Using an independent 48MHz clock)
+ * - 12 bit (8.7 ENOB)
+ * - 5 input mux:
+ * - 4 inputs that are available on package pins shared with GPIO[29:26]
+ * - 1 input is dedicated to the internal temperature sensor
+ * - 4 element receive sample FIFO
+ * - Interrupt generation
+ * - DMA interface
+ *
+ * Although there is only one ADC you can specify the input to it using the adc_select_input() function.
+ * In round robin mode (adc_set_round_robin()), the ADC will use that input and move to the next one after a read.
+ *
+ * User ADC inputs are on 0-3 (GPIO 26-29), the temperature sensor is on input 4.
+ *
+ * Temperature sensor values can be approximated in centigrade as:
+ *
+ * T = 27 - (ADC_Voltage - 0.706)/0.001721
+ *
+ * The FIFO, if used, can contain up to 4 entries.
+ *
+ * \subsection adc_example Example
+ * \addtogroup hardware_adc
+ *
+ * \include hello_adc.c
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADC, Enable/disable assertions in the ADC module, type=bool, default=0, group=hardware_adc
+#ifndef PARAM_ASSERTIONS_ENABLED_ADC
+#define PARAM_ASSERTIONS_ENABLED_ADC 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Initialise the ADC HW
+ * \ingroup hardware_adc
+ *
+ */
+void adc_init(void);
+
+/*! \brief Initialise the gpio for use as an ADC pin
+ * \ingroup hardware_adc
+ *
+ * Prepare a GPIO for use with ADC by disabling all digital functions.
+ *
+ * \param gpio The GPIO number to use. Allowable GPIO numbers are 26 to 29 inclusive.
+ */
+static inline void adc_gpio_init(uint gpio) {
+ invalid_params_if(ADC, gpio < 26 || gpio > 29);
+ // Select NULL function to make output driver hi-Z
+ gpio_set_function(gpio, GPIO_FUNC_NULL);
+ // Also disable digital pulls and digital receiver
+ gpio_disable_pulls(gpio);
+ gpio_set_input_enabled(gpio, false);
+}
+
+/*! \brief ADC input select
+ * \ingroup hardware_adc
+ *
+ * Select an ADC input. 0...3 are GPIOs 26...29 respectively.
+ * Input 4 is the onboard temperature sensor.
+ *
+ * \param input Input to select.
+ */
+static inline void adc_select_input(uint input) {
+ valid_params_if(ADC, input < NUM_ADC_CHANNELS);
+ hw_write_masked(&adc_hw->cs, input << ADC_CS_AINSEL_LSB, ADC_CS_AINSEL_BITS);
+}
+
+/*! \brief Get the currently selected ADC input channel
+ * \ingroup hardware_adc
+ *
+ * \return The currently selected input channel. 0...3 are GPIOs 26...29 respectively. Input 4 is the onboard temperature sensor.
+ */
+static inline uint adc_get_selected_input(void) {
+ return (adc_hw->cs & ADC_CS_AINSEL_BITS) >> ADC_CS_AINSEL_LSB;
+}
+
+/*! \brief Round Robin sampling selector
+ * \ingroup hardware_adc
+ *
+ * This function sets which inputs are to be run through in round robin mode.
+ * Value between 0 and 0x1f (bit 0 to bit 4 for GPIO 26 to 29 and temperature sensor input respectively)
+ *
+ * \param input_mask A bit pattern indicating which of the 5 inputs are to be sampled. Write a value of 0 to disable round robin sampling.
+ */
+static inline void adc_set_round_robin(uint input_mask) {
+ invalid_params_if(ADC, input_mask & ~ADC_CS_RROBIN_BITS);
+ hw_write_masked(&adc_hw->cs, input_mask << ADC_CS_RROBIN_LSB, ADC_CS_RROBIN_BITS);
+}
+
+/*! \brief Enable the onboard temperature sensor
+ * \ingroup hardware_adc
+ *
+ * \param enable Set true to power on the onboard temperature sensor, false to power off.
+ *
+ */
+static inline void adc_set_temp_sensor_enabled(bool enable) {
+ if (enable)
+ hw_set_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS);
+ else
+ hw_clear_bits(&adc_hw->cs, ADC_CS_TS_EN_BITS);
+}
+
+/*! \brief Perform a single conversion
+ * \ingroup hardware_adc
+ *
+ * Performs an ADC conversion, waits for the result, and then returns it.
+ *
+ * \return Result of the conversion.
+ */
+static inline uint16_t adc_read(void) {
+ hw_set_bits(&adc_hw->cs, ADC_CS_START_ONCE_BITS);
+
+ while (!(adc_hw->cs & ADC_CS_READY_BITS))
+ tight_loop_contents();
+
+ return (uint16_t) adc_hw->result;
+}
+
+/*! \brief Enable or disable free-running sampling mode
+ * \ingroup hardware_adc
+ *
+ * \param run false to disable, true to enable free running conversion mode.
+ */
+static inline void adc_run(bool run) {
+ if (run)
+ hw_set_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS);
+ else
+ hw_clear_bits(&adc_hw->cs, ADC_CS_START_MANY_BITS);
+}
+
+/*! \brief Set the ADC Clock divisor
+ * \ingroup hardware_adc
+ *
+ * Period of samples will be (1 + div) cycles on average. Note it takes 96 cycles to perform a conversion,
+ * so any period less than that will be clamped to 96.
+ *
+ * \param clkdiv If non-zero, conversion will be started at intervals rather than back to back.
+ */
+static inline void adc_set_clkdiv(float clkdiv) {
+ invalid_params_if(ADC, clkdiv >= 1 << (ADC_DIV_INT_MSB - ADC_DIV_INT_LSB + 1));
+ adc_hw->div = (uint32_t)(clkdiv * (float) (1 << ADC_DIV_INT_LSB));
+}
+
+/*! \brief Setup the ADC FIFO
+ * \ingroup hardware_adc
+ *
+ * FIFO is 4 samples long, if a conversion is completed and the FIFO is full, the result is dropped.
+ *
+ * \param en Enables write each conversion result to the FIFO
+ * \param dreq_en Enable DMA requests when FIFO contains data
+ * \param dreq_thresh Threshold for DMA requests/FIFO IRQ if enabled.
+ * \param err_in_fifo If enabled, bit 15 of the FIFO contains error flag for each sample
+ * \param byte_shift Shift FIFO contents to be one byte in size (for byte DMA) - enables DMA to byte buffers.
+ */
+ static inline void adc_fifo_setup(bool en, bool dreq_en, uint16_t dreq_thresh, bool err_in_fifo, bool byte_shift) {
+ hw_write_masked(&adc_hw->fcs,
+ (bool_to_bit(en) << ADC_FCS_EN_LSB) |
+ (bool_to_bit(dreq_en) << ADC_FCS_DREQ_EN_LSB) |
+ (((uint)dreq_thresh) << ADC_FCS_THRESH_LSB) |
+ (bool_to_bit(err_in_fifo) << ADC_FCS_ERR_LSB) |
+ (bool_to_bit(byte_shift) << ADC_FCS_SHIFT_LSB),
+ ADC_FCS_EN_BITS |
+ ADC_FCS_DREQ_EN_BITS |
+ ADC_FCS_THRESH_BITS |
+ ADC_FCS_ERR_BITS |
+ ADC_FCS_SHIFT_BITS
+ );
+}
+
+/*! \brief Check FIFO empty state
+ * \ingroup hardware_adc
+ *
+ * \return Returns true if the FIFO is empty
+ */
+static inline bool adc_fifo_is_empty(void) {
+ return !!(adc_hw->fcs & ADC_FCS_EMPTY_BITS);
+}
+
+/*! \brief Get number of entries in the ADC FIFO
+ * \ingroup hardware_adc
+ *
+ * The ADC FIFO is 4 entries long. This function will return how many samples are currently present.
+ */
+static inline uint8_t adc_fifo_get_level(void) {
+ return (adc_hw->fcs & ADC_FCS_LEVEL_BITS) >> ADC_FCS_LEVEL_LSB;
+}
+
+/*! \brief Get ADC result from FIFO
+ * \ingroup hardware_adc
+ *
+ * Pops the latest result from the ADC FIFO.
+ */
+static inline uint16_t adc_fifo_get(void) {
+ return (uint16_t)adc_hw->fifo;
+}
+
+/*! \brief Wait for the ADC FIFO to have data.
+ * \ingroup hardware_adc
+ *
+ * Blocks until data is present in the FIFO
+ */
+static inline uint16_t adc_fifo_get_blocking(void) {
+ while (adc_fifo_is_empty())
+ tight_loop_contents();
+ return (uint16_t)adc_hw->fifo;
+}
+
+/*! \brief Drain the ADC FIFO
+ * \ingroup hardware_adc
+ *
+ * Will wait for any conversion to complete then drain the FIFO, discarding any results.
+ */
+static inline void adc_fifo_drain(void) {
+ // Potentially there is still a conversion in progress -- wait for this to complete before draining
+ while (!(adc_hw->cs & ADC_CS_READY_BITS))
+ tight_loop_contents();
+ while (!adc_fifo_is_empty())
+ (void) adc_fifo_get();
+}
+
+/*! \brief Enable/Disable ADC interrupts.
+ * \ingroup hardware_adc
+ *
+ * \param enabled Set to true to enable the ADC interrupts, false to disable
+ */
+static inline void adc_irq_set_enabled(bool enabled) {
+ adc_hw->inte = !!enabled;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/address_mapped.h b/arkanoid/pico/hardware/address_mapped.h
new file mode 100644
index 0000000..8f309da
--- /dev/null
+++ b/arkanoid/pico/hardware/address_mapped.h
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_ADDRESS_MAPPED_H
+#define _HARDWARE_ADDRESS_MAPPED_H
+
+#include "../pico.h"
+#include "regs/addressmap.h"
+
+/** \file address_mapped.h
+ * \defgroup hardware_base hardware_base
+ *
+ * Low-level types and (atomic) accessors for memory-mapped hardware registers
+ *
+ * `hardware_base` defines the low level types and access functions for memory mapped hardware registers. It is included
+ * by default by all other hardware libraries.
+ *
+ * The following register access typedefs codify the access type (read/write) and the bus size (8/16/32) of the hardware register.
+ * The register type names are formed by concatenating one from each of the 3 parts A, B, C
+
+ * A | B | C | Meaning
+ * ------|---|---|--------
+ * io_ | | | A Memory mapped IO register
+ * |ro_| | read-only access
+ * |rw_| | read-write access
+ * |wo_| | write-only access (can't actually be enforced via C API)
+ * | | 8| 8-bit wide access
+ * | | 16| 16-bit wide access
+ * | | 32| 32-bit wide access
+ *
+ * When dealing with these types, you will always use a pointer, i.e. `io_rw_32 *some_reg` is a pointer to a read/write
+ * 32 bit register that you can write with `*some_reg = value`, or read with `value = *some_reg`.
+ *
+ * RP2040 hardware is also aliased to provide atomic setting, clear or flipping of a subset of the bits within
+ * a hardware register so that concurrent access by two cores is always consistent with one atomic operation
+ * being performed first, followed by the second.
+ *
+ * See hw_set_bits(), hw_clear_bits() and hw_xor_bits() provide for atomic access via a pointer to a 32 bit register
+ *
+ * Additionally given a pointer to a structure representing a piece of hardware (e.g. `dma_hw_t *dma_hw` for the DMA controller), you can
+ * get an alias to the entire structure such that writing any member (register) within the structure is equivalent
+ * to an atomic operation via hw_set_alias(), hw_clear_alias() or hw_xor_alias()...
+ *
+ * For example `hw_set_alias(dma_hw)->inte1 = 0x80;` will set bit 7 of the INTE1 register of the DMA controller,
+ * leaving the other bits unchanged.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define check_hw_layout(type, member, offset) static_assert(offsetof(type, member) == (offset), "hw offset mismatch")
+#define check_hw_size(type, size) static_assert(sizeof(type) == (size), "hw size mismatch")
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS, Enable/disable assertions in memory address aliasing macros, type=bool, default=0, group=hardware_base
+#ifndef PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS
+#define PARAM_ASSERTIONS_ENABLED_ADDRESS_ALIAS 0
+#endif
+
+typedef volatile uint32_t io_rw_32;
+typedef const volatile uint32_t io_ro_32;
+typedef volatile uint32_t io_wo_32;
+typedef volatile uint16_t io_rw_16;
+typedef const volatile uint16_t io_ro_16;
+typedef volatile uint16_t io_wo_16;
+typedef volatile uint8_t io_rw_8;
+typedef const volatile uint8_t io_ro_8;
+typedef volatile uint8_t io_wo_8;
+
+typedef volatile uint8_t *const ioptr;
+typedef ioptr const const_ioptr;
+
+// A non-functional (empty) helper macro to help IDEs follow links from the autogenerated
+// hardware struct headers in structs/xxx.h to the raw register definitions
+// in regs/xxx.h. A preprocessor define such as TIMER_TIMEHW_OFFSET (a timer register offset)
+// is not generally clickable (in an IDE) if placed in a C comment, so _REG_(TIMER_TIMEHW_OFFSET) is
+// included outside of a comment instead
+#define _REG_(x)
+
+// Helper method used by hw_alias macros to optionally check input validity
+#define hw_alias_check_addr(addr) ((uintptr_t)(addr))
+// can't use the following impl as it breaks existing static declarations using hw_alias, so would be a backwards incompatibility
+//static __force_inline uint32_t hw_alias_check_addr(volatile void *addr) {
+// uint32_t rc = (uintptr_t)addr;
+// invalid_params_if(ADDRESS_ALIAS, rc < 0x40000000); // catch likely non HW pointer types
+// return rc;
+//}
+
+// Helper method used by xip_alias macros to optionally check input validity
+static __force_inline uint32_t xip_alias_check_addr(const void *addr) {
+ uint32_t rc = (uintptr_t)addr;
+ valid_params_if(ADDRESS_ALIAS, rc >= XIP_MAIN_BASE && rc < XIP_NOALLOC_BASE);
+ return rc;
+}
+
+// Untyped conversion alias pointer generation macros
+#define hw_set_alias_untyped(addr) ((void *)(REG_ALIAS_SET_BITS | hw_alias_check_addr(addr)))
+#define hw_clear_alias_untyped(addr) ((void *)(REG_ALIAS_CLR_BITS | hw_alias_check_addr(addr)))
+#define hw_xor_alias_untyped(addr) ((void *)(REG_ALIAS_XOR_BITS | hw_alias_check_addr(addr)))
+#define xip_noalloc_alias_untyped(addr) ((void *)(XIP_NOALLOC_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_alias_untyped(addr) ((void *)(XIP_NOCACHE_BASE | xip_alias_check_addr(addr)))
+#define xip_nocache_noalloc_alias_untyped(addr) ((void *)(XIP_NOCACHE_NOALLOC_BASE | xip_alias_check_addr(addr)))
+
+// Typed conversion alias pointer generation macros
+#define hw_set_alias(p) ((typeof(p))hw_set_alias_untyped(p))
+#define hw_clear_alias(p) ((typeof(p))hw_clear_alias_untyped(p))
+#define hw_xor_alias(p) ((typeof(p))hw_xor_alias_untyped(p))
+#define xip_noalloc_alias(p) ((typeof(p))xip_noalloc_alias_untyped(p))
+#define xip_nocache_alias(p) ((typeof(p))xip_nocache_alias_untyped(p))
+#define xip_nocache_noalloc_alias(p) ((typeof(p))xip_nocache_noalloc_alias_untyped(p))
+
+/*! \brief Atomically set the specified bits to 1 in a HW register
+ * \ingroup hardware_base
+ *
+ * \param addr Address of writable register
+ * \param mask Bit-mask specifying bits to set
+ */
+__force_inline static void hw_set_bits(io_rw_32 *addr, uint32_t mask) {
+ *(io_rw_32 *) hw_set_alias_untyped((volatile void *) addr) = mask;
+}
+
+/*! \brief Atomically clear the specified bits to 0 in a HW register
+ * \ingroup hardware_base
+ *
+ * \param addr Address of writable register
+ * \param mask Bit-mask specifying bits to clear
+ */
+__force_inline static void hw_clear_bits(io_rw_32 *addr, uint32_t mask) {
+ *(io_rw_32 *) hw_clear_alias_untyped((volatile void *) addr) = mask;
+}
+
+/*! \brief Atomically flip the specified bits in a HW register
+ * \ingroup hardware_base
+ *
+ * \param addr Address of writable register
+ * \param mask Bit-mask specifying bits to invert
+ */
+__force_inline static void hw_xor_bits(io_rw_32 *addr, uint32_t mask) {
+ *(io_rw_32 *) hw_xor_alias_untyped((volatile void *) addr) = mask;
+}
+
+/*! \brief Set new values for a sub-set of the bits in a HW register
+ * \ingroup hardware_base
+ *
+ * Sets destination bits to values specified in \p values, if and only if corresponding bit in \p write_mask is set
+ *
+ * Note: this method allows safe concurrent modification of *different* bits of
+ * a register, but multiple concurrent access to the same bits is still unsafe.
+ *
+ * \param addr Address of writable register
+ * \param values Bits values
+ * \param write_mask Mask of bits to change
+ */
+__force_inline static void hw_write_masked(io_rw_32 *addr, uint32_t values, uint32_t write_mask) {
+ hw_xor_bits(addr, (*addr ^ values) & write_mask);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/claim.c b/arkanoid/pico/hardware/claim.c
new file mode 100644
index 0000000..6ce1a49
--- /dev/null
+++ b/arkanoid/pico/hardware/claim.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "claim.h"
+
+uint32_t hw_claim_lock() {
+ return spin_lock_blocking(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM));
+}
+
+void hw_claim_unlock(uint32_t save) {
+ spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_HARDWARE_CLAIM), save);
+}
+
+inline bool hw_is_claimed(const uint8_t *bits, uint bit_index) {
+ return (bits[bit_index >> 3u] & (1u << (bit_index & 7u)));
+}
+
+void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message) {
+ uint32_t save = hw_claim_lock();
+ if (hw_is_claimed(bits, bit_index)) {
+ panic(message, bit_index);
+ } else {
+ bits[bit_index >> 3u] |= (uint8_t)(1u << (bit_index & 7u));
+ }
+ hw_claim_unlock(save);
+}
+
+int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message) {
+ // don't bother check lsb / msb order as if wrong, then it'll fail anyway
+ uint32_t save = hw_claim_lock();
+ int found_bit = -1;
+ for(uint bit=bit_lsb; bit <= bit_msb; bit++) {
+ if (!hw_is_claimed(bits, bit)) {
+ bits[bit >> 3u] |= (uint8_t)(1u << (bit & 7u));
+ found_bit = (int)bit;
+ break;
+ }
+ }
+ hw_claim_unlock(save);
+ if (found_bit < 0 && required) {
+ panic(message);
+ }
+ return found_bit;
+}
+
+void hw_claim_clear(uint8_t *bits, uint bit_index) {
+ uint32_t save = hw_claim_lock();
+ assert(hw_is_claimed(bits, bit_index));
+ bits[bit_index >> 3u] &= (uint8_t) ~(1u << (bit_index & 7u));
+ hw_claim_unlock(save);
+}
+
+
diff --git a/arkanoid/pico/hardware/claim.h b/arkanoid/pico/hardware/claim.h
new file mode 100644
index 0000000..e6f6354
--- /dev/null
+++ b/arkanoid/pico/hardware/claim.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_CLAIM_H
+#define _HARDWARE_CLAIM_H
+
+#include "../pico.h"
+#include "sync.h"
+
+/** \file claim.h
+ * \defgroup hardware_claim hardware_claim
+ *
+ * Lightweight hardware resource management
+ *
+ * `hardware_claim` provides a simple API for management of hardware resources at runtime.
+ *
+ * This API is usually called by other hardware specific _claiming_ APIs and provides simple
+ * multi-core safe methods to manipulate compact bit-sets representing hardware resources.
+ *
+ * This API allows any other library to cooperatively participate in a scheme by which
+ * both compile time and runtime allocation of resources can co-exist, and conflicts
+ * can be avoided or detected (depending on the use case) without the libraries having
+ * any other knowledge of each other.
+ *
+ * Facilities are providing for:
+ *
+ * 1. Claiming resources (and asserting if they are already claimed)
+ * 2. Freeing (unclaiming) resources
+ * 3. Finding unused resources
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Atomically claim a resource, panicking if it is already in use
+ * \ingroup hardware_claim
+ *
+ * The resource ownership is indicated by the bit_index bit in an array of bits.
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param bit_index resource to claim (bit index into array of bits)
+ * \param message string to display if the bit cannot be claimed; note this may have a single printf format "%d" for the bit
+ */
+void hw_claim_or_assert(uint8_t *bits, uint bit_index, const char *message);
+
+/*! \brief Atomically claim one resource out of a range of resources, optionally asserting if none are free
+ * \ingroup hardware_claim
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param required true if this method should panic if the resource is not free
+ * \param bit_lsb the lower bound (inclusive) of the resource range to claim from
+ * \param bit_msb the upper bound (inclusive) of the resource range to claim from
+ * \param message string to display if the bit cannot be claimed
+ * \return the bit index representing the claimed or -1 if none are available in the range, and required = false
+ */
+int hw_claim_unused_from_range(uint8_t *bits, bool required, uint bit_lsb, uint bit_msb, const char *message);
+
+/*! \brief Determine if a resource is claimed at the time of the call
+ * \ingroup hardware_claim
+ *
+ * The resource ownership is indicated by the bit_index bit in an array of bits.
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param bit_index resource to check (bit index into array of bits)
+ * \return true if the resource is claimed
+ */
+bool hw_is_claimed(const uint8_t *bits, uint bit_index);
+
+/*! \brief Atomically unclaim a resource
+ * \ingroup hardware_claim
+ *
+ * The resource ownership is indicated by the bit_index bit in an array of bits.
+ *
+ * \param bits pointer to an array of bits (8 bits per byte)
+ * \param bit_index resource to unclaim (bit index into array of bits)
+ */
+void hw_claim_clear(uint8_t *bits, uint bit_index);
+
+/*! \brief Acquire the runtime mutual exclusion lock provided by the `hardware_claim` library
+ * \ingroup hardware_claim
+ *
+ * This method is called automatically by the other `hw_claim_` methods, however it is provided as a convenience
+ * to code that might want to protect other hardware initialization code from concurrent use.
+ *
+ * \note hw_claim_lock() uses a spin lock internally, so disables interrupts on the calling core, and will deadlock
+ * if the calling core already owns the lock.
+ *
+ * \return a token to pass to hw_claim_unlock()
+ */
+uint32_t hw_claim_lock(void);
+
+/*! \brief Release the runtime mutual exclusion lock provided by the `hardware_claim` library
+ * \ingroup hardware_claim
+ *
+ * \note This method MUST be called from the same core that call hw_claim_lock()
+ *
+ * \param token the token returned by the corresponding call to hw_claim_lock()
+ */
+void hw_claim_unlock(uint32_t token);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/clocks.c b/arkanoid/pico/hardware/clocks.c
new file mode 100644
index 0000000..8ecd438
--- /dev/null
+++ b/arkanoid/pico/hardware/clocks.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../pico.h"
+#include "regs/clocks.h"
+#include "platform_defs.h"
+#include "clocks.h"
+#include "watchdog.h"
+#include "pll.h"
+#include "xosc.h"
+#include "irq.h"
+#include "gpio.h"
+
+check_hw_layout(clocks_hw_t, clk[clk_adc].selected, CLOCKS_CLK_ADC_SELECTED_OFFSET);
+check_hw_layout(clocks_hw_t, fc0.result, CLOCKS_FC0_RESULT_OFFSET);
+check_hw_layout(clocks_hw_t, ints, CLOCKS_INTS_OFFSET);
+
+static uint32_t configured_freq[CLK_COUNT];
+
+static resus_callback_t _resus_callback;
+
+// Clock muxing consists of two components:
+// - A glitchless mux, which can be switched freely, but whose inputs must be
+// free-running
+// - An auxiliary (glitchy) mux, whose output glitches when switched, but has
+// no constraints on its inputs
+// Not all clocks have both types of mux.
+static inline bool has_glitchless_mux(enum clock_index clk_index) {
+ return clk_index == clk_sys || clk_index == clk_ref;
+}
+
+void clock_stop(enum clock_index clk_index) {
+ clock_hw_t *clock = &clocks_hw->clk[clk_index];
+ hw_clear_bits(&clock->ctrl, CLOCKS_CLK_USB_CTRL_ENABLE_BITS);
+ configured_freq[clk_index] = 0;
+}
+
+/// \tag::clock_configure[]
+bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq) {
+ uint32_t div;
+
+ assert(src_freq >= freq);
+
+ if (freq > src_freq)
+ return false;
+
+ // Div register is 24.8 int.frac divider so multiply by 2^8 (left shift by 8)
+ div = (uint32_t) (((uint64_t) src_freq << 8) / freq);
+
+ clock_hw_t *clock = &clocks_hw->clk[clk_index];
+
+ // If increasing divisor, set divisor before source. Otherwise set source
+ // before divisor. This avoids a momentary overspeed when e.g. switching
+ // to a faster source and increasing divisor to compensate.
+ if (div > clock->div)
+ clock->div = div;
+
+ // If switching a glitchless slice (ref or sys) to an aux source, switch
+ // away from aux *first* to avoid passing glitches when changing aux mux.
+ // Assume (!!!) glitchless source 0 is no faster than the aux source.
+ if (has_glitchless_mux(clk_index) && src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) {
+ hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
+ while (!(clock->selected & 1u))
+ tight_loop_contents();
+ }
+ // If no glitchless mux, cleanly stop the clock to avoid glitches
+ // propagating when changing aux mux. Note it would be a really bad idea
+ // to do this on one of the glitchless clocks (clk_sys, clk_ref).
+ else {
+ // Disable clock. On clk_ref and clk_sys this does nothing,
+ // all other clocks have the ENABLE bit in the same position.
+ hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+ if (configured_freq[clk_index] > 0) {
+ // Delay for 3 cycles of the target clock, for ENABLE propagation.
+ // Note XOSC_COUNT is not helpful here because XOSC is not
+ // necessarily running, nor is timer... so, 3 cycles per loop:
+ uint delay_cyc = configured_freq[clk_sys] / configured_freq[clk_index] + 1;
+ asm volatile (
+ ".syntax unified \n\t"
+ "1: \n\t"
+ "subs %0, #1 \n\t"
+ "bne 1b"
+ : "+r" (delay_cyc)
+ );
+ }
+ }
+
+ // Set aux mux first, and then glitchless mux if this clock has one
+ hw_write_masked(&clock->ctrl,
+ (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB),
+ CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS
+ );
+
+ if (has_glitchless_mux(clk_index)) {
+ hw_write_masked(&clock->ctrl,
+ src << CLOCKS_CLK_REF_CTRL_SRC_LSB,
+ CLOCKS_CLK_REF_CTRL_SRC_BITS
+ );
+ while (!(clock->selected & (1u << src)))
+ tight_loop_contents();
+ }
+
+ // Enable clock. On clk_ref and clk_sys this does nothing,
+ // all other clocks have the ENABLE bit in the same position.
+ hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS);
+
+ // Now that the source is configured, we can trust that the user-supplied
+ // divisor is a safe value.
+ clock->div = div;
+
+ // Store the configured frequency
+ configured_freq[clk_index] = (uint32_t)(((uint64_t) src_freq << 8) / div);
+
+ return true;
+}
+/// \end::clock_configure[]
+
+void clocks_init(void) {
+ // Start tick in watchdog
+ watchdog_start_tick(XOSC_MHZ);
+
+ // Everything is 48MHz on FPGA apart from RTC. Otherwise set to 0 and will be set in clock configure
+ if (running_on_fpga()) {
+ for (uint i = 0; i < CLK_COUNT; i++) {
+ configured_freq[i] = 48 * MHZ;
+ }
+ configured_freq[clk_rtc] = 46875;
+ return;
+ }
+
+ // Disable resus that may be enabled from previous software
+ clocks_hw->resus.ctrl = 0;
+
+ // Enable the xosc
+ xosc_init();
+
+ // Before we touch PLLs, switch sys and ref cleanly away from their aux sources.
+ hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS);
+ while (clocks_hw->clk[clk_sys].selected != 0x1)
+ tight_loop_contents();
+ hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS);
+ while (clocks_hw->clk[clk_ref].selected != 0x1)
+ tight_loop_contents();
+
+ /// \tag::pll_settings[]
+ // Configure PLLs
+ // REF FBDIV VCO POSTDIV
+ // PLL SYS: 12 / 1 = 12MHz * 125 = 1500MHZ / 6 / 2 = 125MHz
+ // PLL USB: 12 / 1 = 12MHz * 40 = 480 MHz / 5 / 2 = 48MHz
+ /// \end::pll_settings[]
+
+ /// \tag::pll_init[]
+ pll_init(pll_sys, 1, 1500 * MHZ, 6, 2);
+ pll_init(pll_usb, 1, 480 * MHZ, 5, 2);
+ /// \end::pll_init[]
+
+ // Configure clocks
+ // CLK_REF = XOSC (12MHz) / 1 = 12MHz
+ clock_configure(clk_ref,
+ CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
+ 0, // No aux mux
+ 12 * MHZ,
+ 12 * MHZ);
+
+ /// \tag::configure_clk_sys[]
+ // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
+ clock_configure(clk_sys,
+ CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+ CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
+ 125 * MHZ,
+ 125 * MHZ);
+ /// \end::configure_clk_sys[]
+
+ // CLK USB = PLL USB (48MHz) / 1 = 48MHz
+ clock_configure(clk_usb,
+ 0, // No GLMUX
+ CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+ 48 * MHZ,
+ 48 * MHZ);
+
+ // CLK ADC = PLL USB (48MHZ) / 1 = 48MHz
+ clock_configure(clk_adc,
+ 0, // No GLMUX
+ CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+ 48 * MHZ,
+ 48 * MHZ);
+
+ // CLK RTC = PLL USB (48MHz) / 1024 = 46875Hz
+ clock_configure(clk_rtc,
+ 0, // No GLMUX
+ CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+ 48 * MHZ,
+ 46875);
+
+ // CLK PERI = clk_sys. Used as reference clock for Peripherals. No dividers so just select and enable
+ // Normally choose clk_sys or clk_usb
+ clock_configure(clk_peri,
+ 0,
+ CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS,
+ 125 * MHZ,
+ 125 * MHZ);
+}
+
+/// \tag::clock_get_hz[]
+uint32_t clock_get_hz(enum clock_index clk_index) {
+ return configured_freq[clk_index];
+}
+/// \end::clock_get_hz[]
+
+void clock_set_reported_hz(enum clock_index clk_index, uint hz) {
+ configured_freq[clk_index] = hz;
+}
+
+/// \tag::frequency_count_khz[]
+uint32_t frequency_count_khz(uint src) {
+ fc_hw_t *fc = &clocks_hw->fc0;
+
+ // If frequency counter is running need to wait for it. It runs even if the source is NULL
+ while(fc->status & CLOCKS_FC0_STATUS_RUNNING_BITS) {
+ tight_loop_contents();
+ }
+
+ // Set reference freq
+ fc->ref_khz = clock_get_hz(clk_ref) / 1000;
+
+ // FIXME: Don't pick random interval. Use best interval
+ fc->interval = 10;
+
+ // No min or max
+ fc->min_khz = 0;
+ fc->max_khz = 0xffffffff;
+
+ // Set SRC which automatically starts the measurement
+ fc->src = src;
+
+ while(!(fc->status & CLOCKS_FC0_STATUS_DONE_BITS)) {
+ tight_loop_contents();
+ }
+
+ // Return the result
+ return fc->result >> CLOCKS_FC0_RESULT_KHZ_LSB;
+}
+/// \end::frequency_count_khz[]
+
+static void clocks_handle_resus(void) {
+ // Set clk_sys back to the ref clock rather than it being forced to clk_ref
+ // by resus. Call the user's resus callback if they have set one
+
+ // CLK SYS = CLK_REF. Must be running for this code to be running
+ uint clk_ref_freq = clock_get_hz(clk_ref);
+ clock_configure(clk_sys,
+ CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF,
+ 0,
+ clk_ref_freq,
+ clk_ref_freq);
+
+ // Assert we have been resussed
+ assert(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS);
+
+ // Now we have fixed clk_sys we can safely remove the resus
+ hw_set_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS);
+ hw_clear_bits(&clocks_hw->resus.ctrl, CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS);
+
+ // Now we should no longer be resussed
+ assert(!(clocks_hw->resus.status & CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS));
+
+ // Call the user's callback to notify them of the resus event
+ if (_resus_callback) {
+ _resus_callback();
+ }
+}
+
+static void clocks_irq_handler(void) {
+ // Clocks interrupt handler. Only resus but handle irq
+ // defensively just in case.
+ uint32_t ints = clocks_hw->ints;
+
+ if (ints & CLOCKS_INTE_CLK_SYS_RESUS_BITS) {
+ ints &= ~CLOCKS_INTE_CLK_SYS_RESUS_BITS;
+ clocks_handle_resus();
+ }
+
+#ifndef NDEBUG
+ if (ints) {
+ panic("Unexpected clocks irq\n");
+ }
+#endif
+}
+
+void clocks_enable_resus(resus_callback_t resus_callback) {
+ // Restart clk_sys if it is stopped by forcing it
+ // to the default source of clk_ref. If clk_ref stops running this will
+ // not work.
+
+ // Store user's resus callback
+ _resus_callback = resus_callback;
+
+ irq_set_exclusive_handler(CLOCKS_IRQ, clocks_irq_handler);
+
+ // Enable the resus interrupt in clocks
+ clocks_hw->inte = CLOCKS_INTE_CLK_SYS_RESUS_BITS;
+
+ // Enable the clocks irq
+ irq_set_enabled(CLOCKS_IRQ, true);
+
+ // 2 * clk_ref freq / clk_sys_min_freq;
+ // assume clk_ref is 3MHz and we want clk_sys to be no lower than 1MHz
+ uint timeout = 2 * 3 * 1;
+
+ // Enable resus with the maximum timeout
+ clocks_hw->resus.ctrl = CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS | timeout;
+}
+
+void clock_gpio_init(uint gpio, uint src, uint div) {
+ // Bit messy but it's as much code to loop through a lookup
+ // table. The sources for each gpout generators are the same
+ // so just call with the sources from GP0
+ uint gpclk = 0;
+ if (gpio == 21) gpclk = clk_gpout0;
+ else if (gpio == 23) gpclk = clk_gpout1;
+ else if (gpio == 24) gpclk = clk_gpout2;
+ else if (gpio == 25) gpclk = clk_gpout3;
+ else {
+ invalid_params_if(CLOCKS, true);
+ }
+
+ // Set up the gpclk generator
+ clocks_hw->clk[gpclk].ctrl = (src << CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB) |
+ CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS;
+ clocks_hw->clk[gpclk].div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB;
+
+ // Set gpio pin to gpclock function
+ gpio_set_function(gpio, GPIO_FUNC_GPCK);
+}
+
+static const uint8_t gpin0_src[CLK_COUNT] = {
+ CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT0
+ CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT1
+ CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT2
+ CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_GPOUT3
+ CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_REF
+ CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_SYS
+ CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_PERI
+ CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_USB
+ CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_ADC
+ CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0, // CLK_RTC
+};
+
+// Assert GPIN1 is GPIN0 + 1
+static_assert(CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+static_assert(CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 == (CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 + 1), "hw mismatch");
+
+bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq) {
+ // Configure a clock to run from a GPIO input
+ uint gpin = 0;
+ if (gpio == 20) gpin = 0;
+ else if (gpio == 22) gpin = 1;
+ else {
+ invalid_params_if(CLOCKS, true);
+ }
+
+ // Work out sources. GPIN is always an auxsrc
+ uint src = 0;
+
+ // GPIN1 == GPIN0 + 1
+ uint auxsrc = gpin0_src[clk_index] + gpin;
+
+ if (has_glitchless_mux(clk_index)) {
+ // AUX src is always 1
+ src = 1;
+ }
+
+ // Set the GPIO function
+ gpio_set_function(gpio, GPIO_FUNC_GPCK);
+
+ // Now we have the src, auxsrc, and configured the gpio input
+ // call clock configure to run the clock from a gpio
+ return clock_configure(clk_index, src, auxsrc, src_freq, freq);
+}
diff --git a/arkanoid/pico/hardware/clocks.h b/arkanoid/pico/hardware/clocks.h
new file mode 100644
index 0000000..bed93ae
--- /dev/null
+++ b/arkanoid/pico/hardware/clocks.h
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_CLOCKS_H_
+#define _HARDWARE_CLOCKS_H_
+
+#include "../pico.h"
+#include "structs/clocks.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file clocks.h
+ * \defgroup hardware_clocks hardware_clocks
+ *
+ * Clock Management API
+ *
+ * This API provides a high level interface to the clock functions.
+ *
+ * The clocks block provides independent clocks to on-chip and external components. It takes inputs from a variety of clock
+ * sources allowing the user to trade off performance against cost, board area and power consumption. From these sources
+ * it uses multiple clock generators to provide the required clocks. This architecture allows the user flexibility to start and
+ * stop clocks independently and to vary some clock frequencies whilst maintaining others at their optimum frequencies
+ *
+ * Please refer to the datasheet for more details on the RP2040 clocks.
+ *
+ * The clock source depends on which clock you are attempting to configure. The first table below shows main clock sources. If
+ * you are not setting the Reference clock or the System clock, or you are specifying that one of those two will be using an auxiliary
+ * clock source, then you will need to use one of the entries from the subsequent tables.
+ *
+ * **Main Clock Sources**
+ *
+ * Source | Reference Clock | System Clock
+ * -------|-----------------|---------
+ * ROSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH | |
+ * Auxiliary | CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX
+ * XOSC | CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC | |
+ * Reference | | CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF
+ *
+ * **Auxiliary Clock Sources**
+ *
+ * The auxiliary clock sources available for use in the configure function depend on which clock is being configured. The following table
+ * describes the available values that can be used. Note that for clk_gpout[x], x can be 0-3.
+ *
+ *
+ * Aux Source | clk_gpout[x] | clk_ref | clk_sys
+ * -----------|------------|---------|--------
+ * System PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
+ * GPIO in 0 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
+ * GPIO in 1 | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
+ * USB PLL | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB| CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
+ * ROSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_ROSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC
+ * XOSC | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | | CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC
+ * System clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_SYS | | |
+ * USB Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_USB | | |
+ * ADC clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_ADC | | |
+ * RTC Clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_RTC | | |
+ * Ref clock | CLOCKS_CLK_GPOUTx_CTRL_AUXSRC_VALUE_CLK_REF | | |
+ *
+ * Aux Source | clk_peri | clk_usb | clk_adc
+ * -----------|-----------|---------|--------
+ * System PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
+ * GPIO in 0 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
+ * GPIO in 1 | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
+ * USB PLL | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
+ * ROSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
+ * XOSC | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC | CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
+ * System clock | CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS | | |
+ *
+ * Aux Source | clk_rtc
+ * -----------|----------
+ * System PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS
+ * GPIO in 0 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0
+ * GPIO in 1 | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1
+ * USB PLL | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB
+ * ROSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH
+ * XOSC | CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC
+
+ *
+ * \section clock_example Example
+ * \addtogroup hardware_clocks
+ * \include hello_48MHz.c
+ */
+
+#define KHZ 1000
+#define MHZ 1000000
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_CLOCKS, Enable/disable assertions in the clocks module, type=bool, default=0, group=hardware_clocks
+#ifndef PARAM_ASSERTIONS_ENABLED_CLOCKS
+#define PARAM_ASSERTIONS_ENABLED_CLOCKS 0
+#endif
+
+/*! \brief Initialise the clock hardware
+ * \ingroup hardware_clocks
+ *
+ * Must be called before any other clock function.
+ */
+void clocks_init(void);
+
+/*! \brief Configure the specified clock
+ * \ingroup hardware_clocks
+ *
+ * See the tables in the description for details on the possible values for clock sources.
+ *
+ * \param clk_index The clock to configure
+ * \param src The main clock source, can be 0.
+ * \param auxsrc The auxiliary clock source, which depends on which clock is being set. Can be 0
+ * \param src_freq Frequency of the input clock source
+ * \param freq Requested frequency
+ */
+bool clock_configure(enum clock_index clk_index, uint32_t src, uint32_t auxsrc, uint32_t src_freq, uint32_t freq);
+
+/*! \brief Stop the specified clock
+ * \ingroup hardware_clocks
+ *
+ * \param clk_index The clock to stop
+ */
+void clock_stop(enum clock_index clk_index);
+
+/*! \brief Get the current frequency of the specified clock
+ * \ingroup hardware_clocks
+ *
+ * \param clk_index Clock
+ * \return Clock frequency in Hz
+ */
+uint32_t clock_get_hz(enum clock_index clk_index);
+
+/*! \brief Measure a clocks frequency using the Frequency counter.
+ * \ingroup hardware_clocks
+ *
+ * Uses the inbuilt frequency counter to measure the specified clocks frequency.
+ * Currently, this function is accurate to +-1KHz. See the datasheet for more details.
+ */
+uint32_t frequency_count_khz(uint src);
+
+/*! \brief Set the "current frequency" of the clock as reported by clock_get_hz without actually changing the clock
+ * \ingroup hardware_clocks
+ *
+ * \see clock_get_hz()
+ */
+void clock_set_reported_hz(enum clock_index clk_index, uint hz);
+
+/// \tag::frequency_count_mhz[]
+static inline float frequency_count_mhz(uint src) {
+ return ((float) (frequency_count_khz(src))) / KHZ;
+}
+/// \end::frequency_count_mhz[]
+
+/*! \brief Resus callback function type.
+ * \ingroup hardware_clocks
+ *
+ * User provided callback for a resus event (when clk_sys is stopped by the programmer and is restarted for them).
+ */
+typedef void (*resus_callback_t)(void);
+
+/*! \brief Enable the resus function. Restarts clk_sys if it is accidentally stopped.
+ * \ingroup hardware_clocks
+ *
+ * The resuscitate function will restart the system clock if it falls below a certain speed (or stops). This
+ * could happen if the clock source the system clock is running from stops. For example if a PLL is stopped.
+ *
+ * \param resus_callback a function pointer provided by the user to call if a resus event happens.
+ */
+void clocks_enable_resus(resus_callback_t resus_callback);
+
+/*! \brief Output an optionally divided clock to the specified gpio pin.
+ * \ingroup hardware_clocks
+ *
+ * \param gpio The GPIO pin to output the clock to. Valid GPIOs are: 21, 23, 24, 25. These GPIOs are connected to the GPOUT0-3 clock generators.
+ * \param src The source clock. See the register field CLOCKS_CLK_GPOUT0_CTRL_AUXSRC for a full list. The list is the same for each GPOUT clock generator.
+ * \param div The amount to divide the source clock by. This is useful to not overwhelm the GPIO pin with a fast clock.
+ */
+void clock_gpio_init(uint gpio, uint src, uint div);
+
+/*! \brief Configure a clock to come from a gpio input
+ * \ingroup hardware_clocks
+ *
+ * \param clk_index The clock to configure
+ * \param gpio The GPIO pin to run the clock from. Valid GPIOs are: 20 and 22.
+ * \param src_freq Frequency of the input clock source
+ * \param freq Requested frequency
+ */
+bool clock_configure_gpin(enum clock_index clk_index, uint gpio, uint32_t src_freq, uint32_t freq);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/divider.h b/arkanoid/pico/hardware/divider.h
new file mode 100644
index 0000000..07b9ceb
--- /dev/null
+++ b/arkanoid/pico/hardware/divider.h
@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_DIVIDER_H
+#define _HARDWARE_DIVIDER_H
+
+#include "../pico.h"
+#include "hardware/structs/sio.h"
+
+/** \file hardware/divider.h
+ * \defgroup hardware_divider hardware_divider
+ *
+ * Low-level hardware-divider access
+ *
+ * The SIO contains an 8-cycle signed/unsigned divide/modulo circuit, per core. Calculation is started by writing a dividend
+ * and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient / and remainder % of
+ * this division over the next 8 cycles, and on the 9th cycle the results can be read from the two result registers
+ * DIV_QUOTIENT and DIV_REMAINDER. A 'ready' bit in register DIV_CSR can be polled to wait for the calculation to
+ * complete, or software can insert a fixed 8-cycle delay
+ *
+ * This header provides low level macros and inline functions for accessing the hardware dividers directly,
+ * and perhaps most usefully performing asynchronous divides. These functions however do not follow the regular
+ * SDK conventions for saving/restoring the divider state, so are not generally safe to call from interrupt handlers
+ *
+ * The pico_divider library provides a more user friendly set of APIs over the divider (and support for
+ * 64 bit divides), and of course by default regular C language integer divisions are redirected through that library, meaning
+ * you can just use C level `/` and `%` operators and gain the benefits of the fast hardware divider.
+ *
+ * @see pico_divider
+ *
+ * \subsection divider_example Example
+ * \addtogroup hardware_divider
+ * \include hello_divider.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef uint64_t divmod_result_t;
+
+/*! \brief Start a signed asynchronous divide
+ * \ingroup hardware_divider
+ *
+ * Start a divide of the specified signed parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
+ * (hw_divider_wait_ready()) prior to reading the results.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ */
+static inline void hw_divider_divmod_s32_start(int32_t a, int32_t b) {
+ check_hw_layout( sio_hw_t, div_sdividend, SIO_DIV_SDIVIDEND_OFFSET);
+ sio_hw->div_sdividend = (uint32_t)a;
+ sio_hw->div_sdivisor = (uint32_t)b;
+}
+
+/*! \brief Start an unsigned asynchronous divide
+ * \ingroup hardware_divider
+ *
+ * Start a divide of the specified unsigned parameters. You should wait for 8 cycles (__div_pause()) or wait for the ready bit to be set
+ * (hw_divider_wait_ready()) prior to reading the results.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ */
+static inline void hw_divider_divmod_u32_start(uint32_t a, uint32_t b) {
+ check_hw_layout(
+ sio_hw_t, div_udividend, SIO_DIV_UDIVIDEND_OFFSET);
+ sio_hw->div_udividend = a;
+ sio_hw->div_udivisor = b;
+}
+
+/*! \brief Wait for a divide to complete
+ * \ingroup hardware_divider
+ *
+ * Wait for a divide to complete
+ */
+static inline void hw_divider_wait_ready(void) {
+ // this is #1 in lsr below
+ static_assert(SIO_DIV_CSR_READY_BITS == 1, "");
+
+ // we use one less register and instruction than gcc which uses a TST instruction
+
+ uint32_t tmp; // allow compiler to pick scratch register
+ asm volatile (
+ "hw_divider_result_loop_%=:"
+ "ldr %0, [%1, %2]\n\t"
+ "lsr %0, #1\n\t"
+ "bcc hw_divider_result_loop_%=\n\t"
+ : "=&l" (tmp)
+ : "l" (sio_hw), "I" (SIO_DIV_CSR_OFFSET)
+ :
+ );
+}
+
+/*! \brief Return result of HW divide, nowait
+ * \ingroup hardware_divider
+ *
+ * \note This is UNSAFE in that the calculation may not have been completed.
+ *
+ * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
+ */
+static inline divmod_result_t hw_divider_result_nowait(void) {
+ // as ugly as this looks it is actually quite efficient
+ divmod_result_t rc = (((divmod_result_t) sio_hw->div_remainder) << 32u) | sio_hw->div_quotient;
+ return rc;
+}
+
+/*! \brief Return result of last asynchronous HW divide
+ * \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current result. Most significant 32 bits are the remainder, lower 32 bits are the quotient.
+ */
+static inline divmod_result_t hw_divider_result_wait(void) {
+ hw_divider_wait_ready();
+ return hw_divider_result_nowait();
+}
+
+/*! \brief Return result of last asynchronous HW divide, unsigned quotient only
+ * \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current unsigned quotient result.
+ */
+static inline uint32_t hw_divider_u32_quotient_wait(void) {
+ hw_divider_wait_ready();
+ return sio_hw->div_quotient;
+}
+
+/*! \brief Return result of last asynchronous HW divide, signed quotient only
+ * \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current signed quotient result.
+ */
+static inline int32_t hw_divider_s32_quotient_wait(void) {
+ hw_divider_wait_ready();
+ return (int32_t)sio_hw->div_quotient;
+}
+
+/*! \brief Return result of last asynchronous HW divide, unsigned remainder only
+ * \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current unsigned remainder result.
+ */
+static inline uint32_t hw_divider_u32_remainder_wait(void) {
+ hw_divider_wait_ready();
+ uint32_t rc = sio_hw->div_remainder;
+ sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+ return rc;
+}
+
+/*! \brief Return result of last asynchronous HW divide, signed remainder only
+ * \ingroup hardware_divider
+ *
+ * This function waits for the result to be ready by calling hw_divider_wait_ready().
+ *
+ * \return Current remainder results.
+ */
+static inline int32_t hw_divider_s32_remainder_wait(void) {
+ hw_divider_wait_ready();
+ int32_t rc = (int32_t)sio_hw->div_remainder;
+ sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+ return rc;
+}
+
+/*! \brief Do a signed HW divide and wait for result
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Results of divide as a 32p32 fixed point value.
+ */
+divmod_result_t hw_divider_divmod_s32(int32_t a, int32_t b);
+
+/*! \brief Do an unsigned HW divide and wait for result
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return result as a fixed point 32p32 value.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Results of divide as a 32p32 fixed point value.
+ */
+divmod_result_t hw_divider_divmod_u32(uint32_t a, uint32_t b);
+
+/*! \brief Efficient extraction of unsigned quotient from 32p32 fixed point
+ * \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned quotient
+ */
+inline static uint32_t to_quotient_u32(divmod_result_t r) {
+ return (uint32_t) r;
+}
+
+/*! \brief Efficient extraction of signed quotient from 32p32 fixed point
+ * \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned quotient
+ */
+inline static int32_t to_quotient_s32(divmod_result_t r) {
+ return (int32_t)(uint32_t)r;
+}
+
+/*! \brief Efficient extraction of unsigned remainder from 32p32 fixed point
+ * \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Unsigned remainder
+ *
+ * \note On Arm this is just a 32 bit register move or a nop
+ */
+inline static uint32_t to_remainder_u32(divmod_result_t r) {
+ return (uint32_t)(r >> 32u);
+}
+
+/*! \brief Efficient extraction of signed remainder from 32p32 fixed point
+ * \ingroup hardware_divider
+ *
+ * \param r 32p32 fixed point value.
+ * \return Signed remainder
+ *
+ * \note On arm this is just a 32 bit register move or a nop
+ */
+inline static int32_t to_remainder_s32(divmod_result_t r) {
+ return (int32_t)(r >> 32u);
+}
+
+/*! \brief Do an unsigned HW divide, wait for result, return quotient
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient results of the divide
+ */
+static inline uint32_t hw_divider_u32_quotient(uint32_t a, uint32_t b) {
+ return to_quotient_u32(hw_divider_divmod_u32(a, b));
+}
+
+/*! \brief Do an unsigned HW divide, wait for result, return remainder
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder results of the divide
+ */
+static inline uint32_t hw_divider_u32_remainder(uint32_t a, uint32_t b) {
+ return to_remainder_u32(hw_divider_divmod_u32(a, b));
+}
+
+/*! \brief Do a signed HW divide, wait for result, return quotient
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient results of the divide
+ */
+static inline int32_t hw_divider_quotient_s32(int32_t a, int32_t b) {
+ return to_quotient_s32(hw_divider_divmod_s32(a, b));
+}
+
+/*! \brief Do a signed HW divide, wait for result, return remainder
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder results of the divide
+ */
+static inline int32_t hw_divider_remainder_s32(int32_t a, int32_t b) {
+ return to_remainder_s32(hw_divider_divmod_s32(a, b));
+}
+
+/*! \brief Pause for exact amount of time needed for a asynchronous divide to complete
+ * \ingroup hardware_divider
+ */
+static inline void hw_divider_pause(void) {
+ asm volatile (
+ "b _1_%=\n"
+ "_1_%=:\n"
+ "b _2_%=\n"
+ "_2_%=:\n"
+ "b _3_%=\n"
+ "_3_%=:\n"
+ "b _4_%=\n"
+ "_4_%=:\n"
+ :: : );
+}
+
+/*! \brief Do a hardware unsigned HW divide, wait for result, return quotient
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient result of the divide
+ */
+static inline uint32_t hw_divider_u32_quotient_inlined(uint32_t a, uint32_t b) {
+ hw_divider_divmod_u32_start(a, b);
+ hw_divider_pause();
+ return sio_hw->div_quotient;
+}
+
+/*! \brief Do a hardware unsigned HW divide, wait for result, return remainder
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder result of the divide
+ */
+static inline uint32_t hw_divider_u32_remainder_inlined(uint32_t a, uint32_t b) {
+ hw_divider_divmod_u32_start(a, b);
+ hw_divider_pause();
+ uint32_t rc = sio_hw->div_remainder;
+ sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+ return rc;
+}
+
+/*! \brief Do a hardware signed HW divide, wait for result, return quotient
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return quotient.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Quotient result of the divide
+ */
+static inline int32_t hw_divider_s32_quotient_inlined(int32_t a, int32_t b) {
+ hw_divider_divmod_s32_start(a, b);
+ hw_divider_pause();
+ return (int32_t)sio_hw->div_quotient;
+}
+
+/*! \brief Do a hardware signed HW divide, wait for result, return remainder
+ * \ingroup hardware_divider
+ *
+ * Divide \p a by \p b, wait for calculation to complete, return remainder.
+ *
+ * \param a The dividend
+ * \param b The divisor
+ * \return Remainder result of the divide
+ */
+static inline int32_t hw_divider_s32_remainder_inlined(int32_t a, int32_t b) {
+ hw_divider_divmod_s32_start(a, b);
+ hw_divider_pause();
+ int32_t rc = (int32_t)sio_hw->div_remainder;
+ sio_hw->div_quotient; // must read quotient to cooperate with other SDK code
+ return rc;
+}
+
+typedef struct {
+ uint32_t values[4];
+} hw_divider_state_t;
+
+/*! \brief Save the calling cores hardware divider state
+ * \ingroup hardware_divider
+ *
+ * Copy the current core's hardware divider state into the provided structure. This method
+ * waits for the divider results to be stable, then copies them to memory.
+ * They can be restored via hw_divider_restore_state()
+ *
+ * \param dest the location to store the divider state
+ */
+void hw_divider_save_state(hw_divider_state_t *dest);
+
+/*! \brief Load a saved hardware divider state into the current core's hardware divider
+ * \ingroup hardware_divider
+ *
+ * Copy the passed hardware divider state into the hardware divider.
+ *
+ * \param src the location to load the divider state from
+ */
+
+void hw_divider_restore_state(hw_divider_state_t *src);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _HARDWARE_DIVIDER_H
diff --git a/arkanoid/pico/hardware/dma.c b/arkanoid/pico/hardware/dma.c
new file mode 100644
index 0000000..869a451
--- /dev/null
+++ b/arkanoid/pico/hardware/dma.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include "dma.h"
+#include "claim.h"
+
+#define DMA_CHAN_STRIDE (DMA_CH1_CTRL_TRIG_OFFSET - DMA_CH0_CTRL_TRIG_OFFSET)
+check_hw_size(dma_channel_hw_t, DMA_CHAN_STRIDE);
+check_hw_layout(dma_hw_t, abort, DMA_CHAN_ABORT_OFFSET);
+
+// sanity check
+static_assert(__builtin_offsetof(dma_hw_t, ch[0].ctrl_trig) == DMA_CH0_CTRL_TRIG_OFFSET, "hw mismatch");
+static_assert(__builtin_offsetof(dma_hw_t, ch[1].ctrl_trig) == DMA_CH1_CTRL_TRIG_OFFSET, "hw mismatch");
+
+static_assert(NUM_DMA_CHANNELS <= 16, "");
+static uint16_t _claimed;
+static uint8_t _timer_claimed;
+
+void dma_channel_claim(uint channel) {
+ check_dma_channel_param(channel);
+ hw_claim_or_assert((uint8_t *) &_claimed, channel, "DMA channel %d is already claimed");
+}
+
+void dma_claim_mask(uint32_t mask) {
+ for(uint i = 0; mask; i++, mask >>= 1u) {
+ if (mask & 1u) dma_channel_claim(i);
+ }
+}
+
+void dma_channel_unclaim(uint channel) {
+ check_dma_channel_param(channel);
+ hw_claim_clear((uint8_t *) &_claimed, channel);
+}
+
+int dma_claim_unused_channel(bool required) {
+ return hw_claim_unused_from_range((uint8_t*)&_claimed, required, 0, NUM_DMA_CHANNELS-1, "No DMA channels are available");
+}
+
+bool dma_channel_is_claimed(uint channel) {
+ check_dma_channel_param(channel);
+ return hw_is_claimed((uint8_t *) &_claimed, channel);
+}
+
+void dma_timer_claim(uint timer) {
+ check_dma_timer_param(timer);
+ hw_claim_or_assert(&_timer_claimed, timer, "DMA timer %d is already claimed");
+}
+
+void dma_timer_unclaim(uint timer) {
+ check_dma_timer_param(timer);
+ hw_claim_clear(&_timer_claimed, timer);
+}
+
+int dma_claim_unused_timer(bool required) {
+ return hw_claim_unused_from_range(&_timer_claimed, required, 0, NUM_DMA_TIMERS-1, "No DMA timers are available");
+}
+
+bool dma_timer_is_claimed(uint timer) {
+ check_dma_timer_param(timer);
+ return hw_is_claimed(&_timer_claimed, timer);
+}
+
+#ifndef NDEBUG
+
+void print_dma_ctrl(dma_channel_hw_t *channel) {
+ uint32_t ctrl = channel->ctrl_trig;
+ int rgsz = (ctrl & DMA_CH0_CTRL_TRIG_RING_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_RING_SIZE_LSB;
+ printf("(%08x) ber %d rer %d wer %d busy %d trq %d cto %d rgsl %d rgsz %d inw %d inr %d sz %d hip %d en %d",
+ (uint) ctrl,
+ ctrl & DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS ? 1 : 0,
+ ctrl & DMA_CH0_CTRL_TRIG_READ_ERROR_BITS ? 1 : 0,
+ ctrl & DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS ? 1 : 0,
+ ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS ? 1 : 0,
+ (int) ((ctrl & DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) >> DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB),
+ (int) ((ctrl & DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) >> DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB),
+ ctrl & DMA_CH0_CTRL_TRIG_RING_SEL_BITS ? 1 : 0,
+ rgsz ? (1 << rgsz) : 0,
+ ctrl & DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS ? 1 : 0,
+ ctrl & DMA_CH0_CTRL_TRIG_INCR_READ_BITS ? 1 : 0,
+ 1 << ((ctrl & DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) >> DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB),
+ ctrl & DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS ? 1 : 0,
+ ctrl & DMA_CH0_CTRL_TRIG_EN_BITS ? 1 : 0);
+}
+#endif
+
+#if PARAM_ASSERTIONS_ENABLED(DMA)
+void check_dma_channel_param_impl(uint __unused channel) {
+ valid_params_if(DMA, channel < NUM_DMA_CHANNELS);
+}
+#endif
diff --git a/arkanoid/pico/hardware/dma.h b/arkanoid/pico/hardware/dma.h
new file mode 100644
index 0000000..c704596
--- /dev/null
+++ b/arkanoid/pico/hardware/dma.h
@@ -0,0 +1,795 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_DMA_H_
+#define _HARDWARE_DMA_H_
+
+#include "../pico.h"
+#include "structs/dma.h"
+#include "regs/dreq.h"
+#include "assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file dma.h
+ * \defgroup hardware_dma hardware_dma
+ *
+ * DMA Controller API
+ *
+ * The RP2040 Direct Memory Access (DMA) master performs bulk data transfers on a processor’s
+ * behalf. This leaves processors free to attend to other tasks, or enter low-power sleep states. The
+ * data throughput of the DMA is also significantly higher than one of RP2040’s processors.
+ *
+ * The DMA can perform one read access and one write access, up to 32 bits in size, every clock cycle.
+ * There are 12 independent channels, which each supervise a sequence of bus transfers, usually in
+ * one of the following scenarios:
+ *
+ * * Memory to peripheral
+ * * Peripheral to memory
+ * * Memory to memory
+ */
+
+// these are not defined in generated dreq.h
+#define DREQ_DMA_TIMER0 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0
+#define DREQ_DMA_TIMER1 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1
+#define DREQ_DMA_TIMER2 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2
+#define DREQ_DMA_TIMER3 DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3
+#define DREQ_FORCE DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_DMA, Enable/disable DMA assertions, type=bool, default=0, group=hardware_dma
+#ifndef PARAM_ASSERTIONS_ENABLED_DMA
+#define PARAM_ASSERTIONS_ENABLED_DMA 0
+#endif
+
+static inline void check_dma_channel_param(__unused uint channel) {
+#if PARAM_ASSERTIONS_ENABLED(DMA)
+ // this method is used a lot by inline functions so avoid code bloat by deferring to function
+ extern void check_dma_channel_param_impl(uint channel);
+ check_dma_channel_param_impl(channel);
+#endif
+}
+
+static inline void check_dma_timer_param(__unused uint timer_num) {
+ valid_params_if(DMA, timer_num < NUM_DMA_TIMERS);
+}
+
+inline static dma_channel_hw_t *dma_channel_hw_addr(uint channel) {
+ check_dma_channel_param(channel);
+ return &dma_hw->ch[channel];
+}
+
+/*! \brief Mark a dma channel as used
+ * \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the channel
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param channel the dma channel
+ */
+void dma_channel_claim(uint channel);
+
+/*! \brief Mark multiple dma channels as used
+ * \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if any of the channels
+ * are already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param channel_mask Bitfield of all required channels to claim (bit 0 == channel 0, bit 1 == channel 1 etc)
+ */
+void dma_claim_mask(uint32_t channel_mask);
+
+/*! \brief Mark a dma channel as no longer used
+ * \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param channel the dma channel to release
+ */
+void dma_channel_unclaim(uint channel);
+
+/*! \brief Claim a free dma channel
+ * \ingroup hardware_dma
+ *
+ * \param required if true the function will panic if none are available
+ * \return the dma channel number or -1 if required was false, and none were free
+ */
+int dma_claim_unused_channel(bool required);
+
+/*! \brief Determine if a dma channel is claimed
+ * \ingroup hardware_dma
+ *
+ * \param channel the dma channel
+ * \return true if the channel is claimed, false otherwise
+ * \see dma_channel_claim
+ * \see dma_channel_claim_mask
+ */
+bool dma_channel_is_claimed(uint channel);
+
+/** \brief DMA channel configuration
+ * \defgroup channel_config channel_config
+ * \ingroup hardware_dma
+ *
+ * A DMA channel needs to be configured, these functions provide handy helpers to set up configuration
+ * structures. See \ref dma_channel_config
+ *
+ */
+
+/*! \brief Enumeration of available DMA channel transfer sizes.
+ * \ingroup hardware_dma
+ *
+ * Names indicate the number of bits.
+ */
+enum dma_channel_transfer_size {
+ DMA_SIZE_8 = 0, ///< Byte transfer (8 bits)
+ DMA_SIZE_16 = 1, ///< Half word transfer (16 bits)
+ DMA_SIZE_32 = 2 ///< Word transfer (32 bits)
+};
+
+typedef struct {
+ uint32_t ctrl;
+} dma_channel_config;
+
+/*! \brief Set DMA channel read increment
+ * \ingroup channel_config
+ *
+ * \param c Pointer to channel configuration data
+ * \param incr True to enable read address increments, if false, each read will be from the same address
+ * Usually disabled for peripheral to memory transfers
+ */
+static inline void channel_config_set_read_increment(dma_channel_config *c, bool incr) {
+ c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_READ_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_READ_BITS);
+}
+
+/*! \brief Set DMA channel write increment
+ * \ingroup channel_config
+ *
+ * \param c Pointer to channel configuration data
+ * \param incr True to enable write address increments, if false, each write will be to the same address
+ * Usually disabled for memory to peripheral transfers
+ * Usually disabled for memory to peripheral transfers
+ */
+static inline void channel_config_set_write_increment(dma_channel_config *c, bool incr) {
+ c->ctrl = incr ? (c->ctrl | DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS);
+}
+
+/*! \brief Select a transfer request signal
+ * \ingroup channel_config
+ *
+ * The channel uses the transfer request signal to pace its data transfer rate.
+ * Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+ * 0x0 to 0x3a -> select DREQ n as TREQ
+ * 0x3b -> Select Timer 0 as TREQ
+ * 0x3c -> Select Timer 1 as TREQ
+ * 0x3d -> Select Timer 2 as TREQ (Optional)
+ * 0x3e -> Select Timer 3 as TREQ (Optional)
+ * 0x3f -> Permanent request, for unpaced transfers.
+ *
+ * \param c Pointer to channel configuration data
+ * \param dreq Source (see description)
+ */
+static inline void channel_config_set_dreq(dma_channel_config *c, uint dreq) {
+ assert(dreq <= DREQ_FORCE);
+ c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS) | (dreq << DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB);
+}
+
+/*! \brief Set DMA channel completion channel
+ * \ingroup channel_config
+ *
+ * When this channel completes, it will trigger the channel indicated by chain_to. Disable by
+ * setting chain_to to itself (the same channel)
+ *
+ * \param c Pointer to channel configuration data
+ * \param chain_to Channel to trigger when this channel completes.
+ */
+static inline void channel_config_set_chain_to(dma_channel_config *c, uint chain_to) {
+ assert(chain_to <= NUM_DMA_CHANNELS);
+ c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS) | (chain_to << DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB);
+}
+
+/*! \brief Set the size of each DMA bus transfer
+ * \ingroup channel_config
+ *
+ * Set the size of each bus transfer (byte/halfword/word). The read and write addresses
+ * advance by the specific amount (1/2/4 bytes) with each transfer.
+ *
+ * \param c Pointer to channel configuration data
+ * \param size See enum for possible values.
+ */
+static inline void channel_config_set_transfer_data_size(dma_channel_config *c, enum dma_channel_transfer_size size) {
+ assert(size == DMA_SIZE_8 || size == DMA_SIZE_16 || size == DMA_SIZE_32);
+ c->ctrl = (c->ctrl & ~DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS) | (((uint)size) << DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB);
+}
+
+/*! \brief Set address wrapping parameters
+ * \ingroup channel_config
+ *
+ * Size of address wrap region. If 0, don’t wrap. For values n > 0, only the lower n bits of the address
+ * will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned
+ * ring buffers.
+ * Ring sizes between 2 and 32768 bytes are possible (size_bits from 1 - 15)
+ *
+ * 0x0 -> No wrapping.
+ *
+ * \param c Pointer to channel configuration data
+ * \param write True to apply to write addresses, false to apply to read addresses
+ * \param size_bits 0 to disable wrapping. Otherwise the size in bits of the changing part of the address.
+ * Effectively wraps the address on a (1 << size_bits) byte boundary.
+ */
+static inline void channel_config_set_ring(dma_channel_config *c, bool write, uint size_bits) {
+ assert(size_bits < 32);
+ c->ctrl = (c->ctrl & ~(DMA_CH0_CTRL_TRIG_RING_SIZE_BITS | DMA_CH0_CTRL_TRIG_RING_SEL_BITS)) |
+ (size_bits << DMA_CH0_CTRL_TRIG_RING_SIZE_LSB) |
+ (write ? DMA_CH0_CTRL_TRIG_RING_SEL_BITS : 0);
+}
+
+/*! \brief Set DMA byte swapping
+ * \ingroup channel_config
+ *
+ * No effect for byte data, for halfword data, the two bytes of each halfword are
+ * swapped. For word data, the four bytes of each word are swapped to reverse their order.
+ *
+ * \param c Pointer to channel configuration data
+ * \param bswap True to enable byte swapping
+ */
+static inline void channel_config_set_bswap(dma_channel_config *c, bool bswap) {
+ c->ctrl = bswap ? (c->ctrl | DMA_CH0_CTRL_TRIG_BSWAP_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_BSWAP_BITS);
+}
+
+/*! \brief Set IRQ quiet mode
+ * \ingroup channel_config
+ *
+ * In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead,
+ * an IRQ is raised when NULL is written to a trigger register, indicating the end of a control
+ * block chain.
+ *
+ * \param c Pointer to channel configuration data
+ * \param irq_quiet True to enable quiet mode, false to disable.
+ */
+static inline void channel_config_set_irq_quiet(dma_channel_config *c, bool irq_quiet) {
+ c->ctrl = irq_quiet ? (c->ctrl | DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS);
+}
+
+/*!
+ * \brief Enable/Disable the DMA channel
+ * \ingroup channel_config
+ *
+ * When false, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will
+ * remain high if already high)
+ *
+ * \param c Pointer to channel configuration data
+ * \param enable True to enable the DMA channel. When enabled, the channel will respond to triggering events, and start transferring data.
+ *
+ */
+static inline void channel_config_set_enable(dma_channel_config *c, bool enable) {
+ c->ctrl = enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_EN_BITS) : (c->ctrl & ~DMA_CH0_CTRL_TRIG_EN_BITS);
+}
+
+/*! \brief Enable access to channel by sniff hardware.
+ * \ingroup channel_config
+ *
+ * Sniff HW must be enabled and have this channel selected.
+ *
+ * \param c Pointer to channel configuration data
+ * \param sniff_enable True to enable the Sniff HW access to this DMA channel.
+ */
+static inline void channel_config_set_sniff_enable(dma_channel_config *c, bool sniff_enable) {
+ c->ctrl = sniff_enable ? (c->ctrl | DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS) : (c->ctrl &
+ ~DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
+}
+
+/*! \brief Get the default channel configuration for a given channel
+ * \ingroup channel_config
+ *
+ * Setting | Default
+ * --------|--------
+ * Read Increment | true
+ * Write Increment | false
+ * DReq | DREQ_FORCE
+ * Chain to | self
+ * Data size | DMA_SIZE_32
+ * Ring | write=false, size=0 (i.e. off)
+ * Byte Swap | false
+ * Quiet IRQs | false
+ * Channel Enable | true
+ * Sniff Enable | false
+ *
+ * \param channel DMA channel
+ * \return the default configuration which can then be modified.
+ */
+static inline dma_channel_config dma_channel_get_default_config(uint channel) {
+ dma_channel_config c = {0};
+ channel_config_set_read_increment(&c, true);
+ channel_config_set_write_increment(&c, false);
+ channel_config_set_dreq(&c, DREQ_FORCE);
+ channel_config_set_chain_to(&c, channel);
+ channel_config_set_transfer_data_size(&c, DMA_SIZE_32);
+ channel_config_set_ring(&c, false, 0);
+ channel_config_set_bswap(&c, false);
+ channel_config_set_irq_quiet(&c, false);
+ channel_config_set_enable(&c, true);
+ channel_config_set_sniff_enable(&c, false);
+ return c;
+}
+
+/*! \brief Get the current configuration for the specified channel.
+ * \ingroup channel_config
+ *
+ * \param channel DMA channel
+ * \return The current configuration as read from the HW register (not cached)
+ */
+static inline dma_channel_config dma_get_channel_config(uint channel) {
+ dma_channel_config c;
+ c.ctrl = dma_channel_hw_addr(channel)->ctrl_trig;
+ return c;
+}
+
+/*! \brief Get the raw configuration register from a channel configuration
+ * \ingroup channel_config
+ *
+ * \param config Pointer to a config structure.
+ * \return Register content
+ */
+static inline uint32_t channel_config_get_ctrl_value(const dma_channel_config *config) {
+ return config->ctrl;
+}
+
+/*! \brief Set a channel configuration
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param config Pointer to a config structure with required configuration
+ * \param trigger True to trigger the transfer immediately
+ */
+static inline void dma_channel_set_config(uint channel, const dma_channel_config *config, bool trigger) {
+ // Don't use CTRL_TRIG since we don't want to start a transfer
+ if (!trigger) {
+ dma_channel_hw_addr(channel)->al1_ctrl = channel_config_get_ctrl_value(config);
+ } else {
+ dma_channel_hw_addr(channel)->ctrl_trig = channel_config_get_ctrl_value(config);
+ }
+}
+
+/*! \brief Set the DMA initial read address.
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param read_addr Initial read address of transfer.
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_set_read_addr(uint channel, const volatile void *read_addr, bool trigger) {
+ if (!trigger) {
+ dma_channel_hw_addr(channel)->read_addr = (uintptr_t) read_addr;
+ } else {
+ dma_channel_hw_addr(channel)->al3_read_addr_trig = (uintptr_t) read_addr;
+ }
+}
+
+/*! \brief Set the DMA initial write address
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param write_addr Initial write address of transfer.
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_set_write_addr(uint channel, volatile void *write_addr, bool trigger) {
+ if (!trigger) {
+ dma_channel_hw_addr(channel)->write_addr = (uintptr_t) write_addr;
+ } else {
+ dma_channel_hw_addr(channel)->al2_write_addr_trig = (uintptr_t) write_addr;
+ }
+}
+
+/*! \brief Set the number of bus transfers the channel will do
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param trans_count The number of transfers (not NOT bytes, see channel_config_set_transfer_data_size)
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_set_trans_count(uint channel, uint32_t trans_count, bool trigger) {
+ if (!trigger) {
+ dma_channel_hw_addr(channel)->transfer_count = trans_count;
+ } else {
+ dma_channel_hw_addr(channel)->al1_transfer_count_trig = trans_count;
+ }
+}
+
+/*! \brief Configure all DMA parameters and optionally start transfer
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param config Pointer to DMA config structure
+ * \param write_addr Initial write address
+ * \param read_addr Initial read address
+ * \param transfer_count Number of transfers to perform
+ * \param trigger True to start the transfer immediately
+ */
+static inline void dma_channel_configure(uint channel, const dma_channel_config *config, volatile void *write_addr,
+ const volatile void *read_addr,
+ uint transfer_count, bool trigger) {
+ dma_channel_set_read_addr(channel, read_addr, false);
+ dma_channel_set_write_addr(channel, write_addr, false);
+ dma_channel_set_trans_count(channel, transfer_count, false);
+ dma_channel_set_config(channel, config, trigger);
+}
+
+/*! \brief Start a DMA transfer from a buffer immediately
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param read_addr Sets the initial read address
+ * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
+ */
+inline static void __attribute__((always_inline)) dma_channel_transfer_from_buffer_now(uint channel,
+ const volatile void *read_addr,
+ uint32_t transfer_count) {
+// check_dma_channel_param(channel);
+ dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
+ hw->read_addr = (uintptr_t) read_addr;
+ hw->al1_transfer_count_trig = transfer_count;
+}
+
+/*! \brief Start a DMA transfer to a buffer immediately
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param write_addr Sets the initial write address
+ * \param transfer_count Number of transfers to make. Not bytes, but the number of transfers of channel_config_set_transfer_data_size() to be sent.
+ */
+inline static void dma_channel_transfer_to_buffer_now(uint channel, volatile void *write_addr, uint32_t transfer_count) {
+ dma_channel_hw_t *hw = dma_channel_hw_addr(channel);
+ hw->write_addr = (uintptr_t) write_addr;
+ hw->al1_transfer_count_trig = transfer_count;
+}
+
+/*! \brief Start one or more channels simultaneously
+ * \ingroup hardware_dma
+ *
+ * \param chan_mask Bitmask of all the channels requiring starting. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ */
+static inline void dma_start_channel_mask(uint32_t chan_mask) {
+ valid_params_if(DMA, chan_mask && chan_mask < (1u << NUM_DMA_CHANNELS));
+ dma_hw->multi_channel_trigger = chan_mask;
+}
+
+/*! \brief Start a single DMA channel
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_start(uint channel) {
+ dma_start_channel_mask(1u << channel);
+}
+
+/*! \brief Stop a DMA transfer
+ * \ingroup hardware_dma
+ *
+ * Function will only return once the DMA has stopped.
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_abort(uint channel) {
+ check_dma_channel_param(channel);
+ dma_hw->abort = 1u << channel;
+ // Bit will go 0 once channel has reached safe state
+ // (i.e. any in-flight transfers have retired)
+ while (dma_hw->abort & (1ul << channel)) tight_loop_contents();
+}
+
+/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_0
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt 0 on specified channel, false to disable.
+ */
+static inline void dma_channel_set_irq0_enabled(uint channel, bool enabled) {
+ check_dma_channel_param(channel);
+ check_hw_layout(dma_hw_t, inte0, DMA_INTE0_OFFSET);
+ if (enabled)
+ hw_set_bits(&dma_hw->inte0, 1u << channel);
+ else
+ hw_clear_bits(&dma_hw->inte0, 1u << channel);
+}
+
+/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_0
+ * \ingroup hardware_dma
+ *
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_set_irq0_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
+ if (enabled) {
+ hw_set_bits(&dma_hw->inte0, channel_mask);
+ } else {
+ hw_clear_bits(&dma_hw->inte0, channel_mask);
+ }
+}
+
+/*! \brief Enable single DMA channel's interrupt via DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt 1 on specified channel, false to disable.
+ */
+static inline void dma_channel_set_irq1_enabled(uint channel, bool enabled) {
+ check_dma_channel_param(channel);
+ check_hw_layout(dma_hw_t, inte1, DMA_INTE1_OFFSET);
+ if (enabled)
+ hw_set_bits(&dma_hw->inte1, 1u << channel);
+ else
+ hw_clear_bits(&dma_hw->inte1, 1u << channel);
+}
+
+/*! \brief Enable multiple DMA channels' interrupts via DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_set_irq1_channel_mask_enabled(uint32_t channel_mask, bool enabled) {
+ if (enabled) {
+ hw_set_bits(&dma_hw->inte1, channel_mask);
+ } else {
+ hw_clear_bits(&dma_hw->inte1, channel_mask);
+ }
+}
+
+/*! \brief Enable single DMA channel interrupt on either DMA_IRQ_0 or DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \param enabled true to enable interrupt via irq_index for specified channel, false to disable.
+ */
+static inline void dma_irqn_set_channel_enabled(uint irq_index, uint channel, bool enabled) {
+ invalid_params_if(DMA, irq_index > 1);
+ if (irq_index) {
+ dma_channel_set_irq1_enabled(channel, enabled);
+ } else {
+ dma_channel_set_irq0_enabled(channel, enabled);
+ }
+}
+
+/*! \brief Enable multiple DMA channels' interrupt via either DMA_IRQ_0 or DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel_mask Bitmask of all the channels to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable all the interrupts specified in the mask, false to disable all the interrupts specified in the mask.
+ */
+static inline void dma_irqn_set_channel_mask_enabled(uint irq_index, uint32_t channel_mask, bool enabled) {
+ invalid_params_if(DMA, irq_index > 1);
+ if (irq_index) {
+ dma_set_irq1_channel_mask_enabled(channel_mask, enabled);
+ } else {
+ dma_set_irq0_channel_mask_enabled(channel_mask, enabled);
+ }
+}
+
+/*! \brief Determine if a particular channel is a cause of DMA_IRQ_0
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_0, false otherwise
+ */
+static inline bool dma_channel_get_irq0_status(uint channel) {
+ check_dma_channel_param(channel);
+ return dma_hw->ints0 & (1u << channel);
+}
+
+/*! \brief Determine if a particular channel is a cause of DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is a cause of DMA_IRQ_1, false otherwise
+ */
+static inline bool dma_channel_get_irq1_status(uint channel) {
+ check_dma_channel_param(channel);
+ return dma_hw->ints1 & (1u << channel);
+}
+
+/*! \brief Determine if a particular channel is a cause of DMA_IRQ_N
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ * \return true if the channel is a cause of the DMA_IRQ_N, false otherwise
+ */
+static inline bool dma_irqn_get_channel_status(uint irq_index, uint channel) {
+ invalid_params_if(DMA, irq_index > 1);
+ check_dma_channel_param(channel);
+ return (irq_index ? dma_hw->ints1 : dma_hw->ints0) & (1u << channel);
+}
+
+/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_0
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq0(uint channel) {
+ check_dma_channel_param(channel);
+ hw_set_bits(&dma_hw->ints0, (1u << channel));
+}
+
+/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_1
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+static inline void dma_channel_acknowledge_irq1(uint channel) {
+ check_dma_channel_param(channel);
+ hw_set_bits(&dma_hw->ints1, (1u << channel));
+}
+
+/*! \brief Acknowledge a channel IRQ, resetting it as the cause of DMA_IRQ_N
+ * \ingroup hardware_dma
+ *
+ * \param irq_index the IRQ index; either 0 or 1 for DMA_IRQ_0 or DMA_IRQ_1
+ * \param channel DMA channel
+ */
+static inline void dma_irqn_acknowledge_channel(uint irq_index, uint channel) {
+ invalid_params_if(DMA, irq_index > 1);
+ check_dma_channel_param(channel);
+ hw_set_bits(irq_index ? &dma_hw->ints1 : &dma_hw->ints0, (1u << channel));
+}
+
+/*! \brief Check if DMA channel is busy
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ * \return true if the channel is currently busy
+ */
+inline static bool dma_channel_is_busy(uint channel) {
+ check_dma_channel_param(channel);
+ return !!(dma_hw->ch[channel].al1_ctrl & DMA_CH0_CTRL_TRIG_BUSY_BITS);
+}
+
+/*! \brief Wait for a DMA channel transfer to complete
+ * \ingroup hardware_dma
+ *
+ * \param channel DMA channel
+ */
+inline static void dma_channel_wait_for_finish_blocking(uint channel) {
+ while (dma_channel_is_busy(channel)) tight_loop_contents();
+ // stop the compiler hoisting a non volatile buffer access above the DMA completion.
+ __compiler_memory_barrier();
+}
+
+/*! \brief Enable the DMA sniffing targeting the specified channel
+ * \ingroup hardware_dma
+ *
+ * The mode can be one of the following:
+ *
+ * Mode | Function
+ * -----|---------
+ * 0x0 | Calculate a CRC-32 (IEEE802.3 polynomial)
+ * 0x1 | Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data
+ * 0x2 | Calculate a CRC-16-CCITT
+ * 0x3 | Calculate a CRC-16-CCITT with bit reversed data
+ * 0xe | XOR reduction over all data. == 1 if the total 1 population count is odd.
+ * 0xf | Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)
+ *
+ * \param channel DMA channel
+ * \param mode See description
+ * \param force_channel_enable Set true to also turn on sniffing in the channel configuration (this
+ * is usually what you want, but sometimes you might have a chain DMA with only certain segments
+ * of the chain sniffed, in which case you might pass false).
+ */
+inline static void dma_sniffer_enable(uint channel, uint mode, bool force_channel_enable) {
+ check_dma_channel_param(channel);
+ check_hw_layout(dma_hw_t, sniff_ctrl, DMA_SNIFF_CTRL_OFFSET);
+ if (force_channel_enable) {
+ hw_set_bits(&dma_hw->ch[channel].al1_ctrl, DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS);
+ }
+ dma_hw->sniff_ctrl = ((channel << DMA_SNIFF_CTRL_DMACH_LSB) & DMA_SNIFF_CTRL_DMACH_BITS) |
+ ((mode << DMA_SNIFF_CTRL_CALC_LSB) & DMA_SNIFF_CTRL_CALC_BITS) |
+ DMA_SNIFF_CTRL_EN_BITS;
+}
+
+/*! \brief Enable the Sniffer byte swap function
+ * \ingroup hardware_dma
+ *
+ * Locally perform a byte reverse on the sniffed data, before feeding into checksum.
+ *
+ * Note that the sniff hardware is downstream of the DMA channel byteswap performed in the
+ * read master: if channel_config_set_bswap() and dma_sniffer_set_byte_swap_enabled() are both enabled,
+ * their effects cancel from the sniffer’s point of view.
+ *
+ * \param swap Set true to enable byte swapping
+ */
+inline static void dma_sniffer_set_byte_swap_enabled(bool swap) {
+ if (swap)
+ hw_set_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
+ else
+ hw_clear_bits(&dma_hw->sniff_ctrl, DMA_SNIFF_CTRL_BSWAP_BITS);
+}
+
+/*! \brief Disable the DMA sniffer
+ * \ingroup hardware_dma
+ *
+ */
+inline static void dma_sniffer_disable(void) {
+ dma_hw->sniff_ctrl = 0;
+}
+
+/*! \brief Mark a dma timer as used
+ * \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the timer
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param timer the dma timer
+ */
+void dma_timer_claim(uint timer);
+
+/*! \brief Mark a dma timer as no longer used
+ * \ingroup hardware_dma
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param timer the dma timer to release
+ */
+void dma_timer_unclaim(uint timer);
+
+/*! \brief Claim a free dma timer
+ * \ingroup hardware_dma
+ *
+ * \param required if true the function will panic if none are available
+ * \return the dma timer number or -1 if required was false, and none were free
+ */
+int dma_claim_unused_timer(bool required);
+
+/*! \brief Determine if a dma timer is claimed
+ * \ingroup hardware_dma
+ *
+ * \param timer the dma timer
+ * \return true if the timer is claimed, false otherwise
+ * \see dma_timer_claim
+ */
+bool dma_timer_is_claimed(uint timer);
+
+/*! \brief Set the divider for the given DMA timer
+ * \ingroup hardware_dma
+ *
+ * The timer will run at the system_clock_freq * numerator / denominator, so this is the speed
+ * that data elements will be transferred at via a DMA channel using this timer as a DREQ
+ *
+ * \param timer the dma timer
+ * \param numerator the fraction's numerator
+ * \param denominator the fraction's denominator
+ */
+static inline void dma_timer_set_fraction(uint timer, uint16_t numerator, uint16_t denominator) {
+ check_dma_timer_param(timer);
+ dma_hw->timer[timer] = (((uint32_t)numerator) << DMA_TIMER0_X_LSB) | (((uint32_t)denominator) << DMA_TIMER0_Y_LSB);
+}
+
+/*! \brief Return the DREQ number for a given DMA timer
+ * \ingroup hardware_dma
+ *
+ * \param timer_num DMA timer number 0-3
+ */
+static inline uint dma_get_timer_dreq(uint timer_num) {
+ static_assert(DREQ_DMA_TIMER1 == DREQ_DMA_TIMER0 + 1, "");
+ static_assert(DREQ_DMA_TIMER2 == DREQ_DMA_TIMER0 + 2, "");
+ static_assert(DREQ_DMA_TIMER3 == DREQ_DMA_TIMER0 + 3, "");
+ check_dma_timer_param(timer_num);
+ return DREQ_DMA_TIMER0 + timer_num;
+}
+
+#ifndef NDEBUG
+void print_dma_ctrl(dma_channel_hw_t *channel);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/exception.c b/arkanoid/pico/hardware/exception.c
new file mode 100644
index 0000000..fe8f3da
--- /dev/null
+++ b/arkanoid/pico/hardware/exception.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "exception.h"
+#include "regs/m0plus.h"
+#include "platform_defs.h"
+#include "structs/scb.h"
+
+#include "../mutex.h"
+#include "assert.h"
+
+#ifndef exception_is_compile_time_default
+static bool exception_is_compile_time_default(exception_handler_t handler) {
+ extern char __default_isrs_start;
+ extern char __default_isrs_end;
+ return ((uintptr_t)handler) >= (uintptr_t)&__default_isrs_start &&
+ ((uintptr_t)handler) < (uintptr_t)&__default_isrs_end;
+}
+#endif
+
+static inline exception_handler_t *get_vtable(void) {
+ return (exception_handler_t *) scb_hw->vtor;
+}
+
+static void set_raw_exception_handler_and_restore_interrupts(enum exception_number num, exception_handler_t handler, uint32_t save) {
+ // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness)
+ get_vtable()[16 + num] = handler;
+ __dmb();
+ restore_interrupts(save);
+}
+
+static inline void check_exception_param(__unused enum exception_number num) {
+ invalid_params_if(EXCEPTION, num < NMI_EXCEPTION || num >=0);
+}
+
+exception_handler_t exception_get_vtable_handler(enum exception_number num) {
+ check_exception_param(num);
+ return get_vtable()[16 + num];
+}
+
+exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler) {
+ check_exception_param(num);
+#if !PICO_NO_RAM_VECTOR_TABLE
+ uint32_t save = save_and_disable_interrupts();
+ exception_handler_t current = exception_get_vtable_handler(num);
+ hard_assert(handler == current || exception_is_compile_time_default(current));
+ set_raw_exception_handler_and_restore_interrupts(num, handler, save);
+#else
+ panic_unsupported();
+#endif
+ return current;
+}
+
+void exception_restore_handler(enum exception_number num, exception_handler_t original_handler) {
+ hard_assert(exception_is_compile_time_default(original_handler));
+#if !PICO_NO_RAM_VECTOR_TABLE
+ uint32_t save = save_and_disable_interrupts();
+ set_raw_exception_handler_and_restore_interrupts(num, original_handler, save);
+#else
+ panic_unsupported();
+#endif
+}
\ No newline at end of file
diff --git a/arkanoid/pico/hardware/exception.h b/arkanoid/pico/hardware/exception.h
new file mode 100644
index 0000000..5420a52
--- /dev/null
+++ b/arkanoid/pico/hardware/exception.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_EXCEPTION_H_
+#define _HARDWARE_EXCEPTION_H_
+
+#include "../pico.h"
+#include "address_mapped.h"
+#include "regs/m0plus.h"
+
+/** \file exception.h
+ * \defgroup hardware_exception hardware_exception
+ *
+ * Methods for setting processor exception handlers
+ *
+ * Exceptions are identified by a \ref exception_number which is a number from -15 to -1; these are the numbers relative to
+ * the index of the first IRQ vector in the vector table. (i.e. vector table index is exception_num plus 16)
+ *
+ * There is one set of exception handlers per core, so the exception handlers for each core as set by these methods are independent.
+ *
+ * \note That all exception APIs affect the executing core only (i.e. the core calling the function).
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_EXCEPTION, Enable/disable assertions in the exception module, type=bool, default=0, group=hardware_exception
+#ifndef PARAM_ASSERTIONS_ENABLED_EXCEPTION
+#define PARAM_ASSERTIONS_ENABLED_EXCEPTION 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Exception number definitions
+ *
+ * Note for consistency with irq numbers, these numbers are defined to be negative. The VTABLE index is
+ * the number here plus 16.
+ *
+ * Name | Value | Exception
+ * ---------------------|-------|----------
+ * NMI_EXCEPTION | -14 | Non Maskable Interrupt
+ * HARDFAULT_EXCEPTION | -13 | HardFault
+ * SVCALL_EXCEPTION | -5 | SV Call
+ * PENDSV_EXCEPTION | -2 | Pend SV
+ * SYSTICK_EXCEPTION | -1 | System Tick
+ *
+ * \ingroup hardware_exception
+ */
+enum exception_number {
+ NMI_EXCEPTION = -14, /* Non Maskable Interrupt */
+ HARDFAULT_EXCEPTION = -13, /* HardFault Interrupt */
+ SVCALL_EXCEPTION = -5, /* SV Call Interrupt */
+ PENDSV_EXCEPTION = -2, /* Pend SV Interrupt */
+ SYSTICK_EXCEPTION = -1, /* System Tick Interrupt */
+};
+
+/*! \brief Exception handler function type
+ * \ingroup hardware_exception
+ *
+ * All exception handlers should be of this type, and follow normal ARM EABI register saving conventions
+ */
+typedef void (*exception_handler_t)(void);
+
+/*! \brief Set the exception handler for an exception on the executing core.
+ * \ingroup hardware_exception
+ *
+ * This method will assert if an exception handler has been set for this exception number on this core via
+ * this method, without an intervening restore via exception_restore_handler.
+ *
+ * \note this method may not be used to override an exception handler that was specified at link time by
+ * providing a strong replacement for the weakly defined stub exception handlers. It will assert in this case too.
+ *
+ * \param num Exception number
+ * \param handler The handler to set
+ * \see exception_number
+ */
+exception_handler_t exception_set_exclusive_handler(enum exception_number num, exception_handler_t handler);
+
+/*! \brief Restore the original exception handler for an exception on this core
+ * \ingroup hardware_exception
+ *
+ * This method may be used to restore the exception handler for an exception on this core to the state
+ * prior to the call to exception_set_exclusive_handler(), so that exception_set_exclusive_handler()
+ * may be called again in the future.
+ *
+ * \param num Exception number \ref exception_number
+ * \param original_handler The original handler returned from \ref exception_set_exclusive_handler
+ * \see exception_set_exclusive_handler()
+ */
+void exception_restore_handler(enum exception_number num, exception_handler_t original_handler);
+
+/*! \brief Get the current exception handler for the specified exception from the currently installed vector table
+ * of the execution core
+ * \ingroup hardware_exception
+ *
+ * \param num Exception number
+ * \return the address stored in the VTABLE for the given exception number
+ */
+exception_handler_t exception_get_vtable_handler(enum exception_number num);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/flash.c b/arkanoid/pico/hardware/flash.c
new file mode 100644
index 0000000..697c756
--- /dev/null
+++ b/arkanoid/pico/hardware/flash.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "flash.h"
+#include "../bootrom.h"
+
+#include "structs/ssi.h"
+#include "structs/ioqspi.h"
+
+#define FLASH_BLOCK_ERASE_CMD 0xd8
+
+// Standard RUID instruction: 4Bh command prefix, 32 dummy bits, 64 data bits.
+#define FLASH_RUID_CMD 0x4b
+#define FLASH_RUID_DUMMY_BYTES 4
+#define FLASH_RUID_DATA_BYTES 8
+#define FLASH_RUID_TOTAL_BYTES (1 + FLASH_RUID_DUMMY_BYTES + FLASH_RUID_DATA_BYTES)
+
+//-----------------------------------------------------------------------------
+// Infrastructure for reentering XIP mode after exiting for programming (take
+// a copy of boot2 before XIP exit). Calling boot2 as a function works because
+// it accepts a return vector in LR (and doesn't trash r4-r7). Bootrom passes
+// NULL in LR, instructing boot2 to enter flash vector table's reset handler.
+
+#if !PICO_NO_FLASH
+
+#define BOOT2_SIZE_WORDS 64
+
+static uint32_t boot2_copyout[BOOT2_SIZE_WORDS];
+static bool boot2_copyout_valid = false;
+
+static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {
+ if (boot2_copyout_valid)
+ return;
+ for (int i = 0; i < BOOT2_SIZE_WORDS; ++i)
+ boot2_copyout[i] = ((uint32_t *)XIP_BASE)[i];
+ __compiler_memory_barrier();
+ boot2_copyout_valid = true;
+}
+
+static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
+ ((void (*)(void))boot2_copyout+1)();
+}
+
+#else
+
+static void __no_inline_not_in_flash_func(flash_init_boot2_copyout)(void) {}
+
+static void __no_inline_not_in_flash_func(flash_enable_xip_via_boot2)(void) {
+ // Set up XIP for 03h read on bus access (slow but generic)
+ rom_flash_enter_cmd_xip_fn flash_enter_cmd_xip = (rom_flash_enter_cmd_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_ENTER_CMD_XIP);
+ assert(flash_enter_cmd_xip);
+ flash_enter_cmd_xip();
+}
+
+#endif
+
+//-----------------------------------------------------------------------------
+// Actual flash programming shims (work whether or not PICO_NO_FLASH==1)
+
+void __no_inline_not_in_flash_func(flash_range_erase)(uint32_t flash_offs, size_t count) {
+#ifdef PICO_FLASH_SIZE_BYTES
+ hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES);
+#endif
+ invalid_params_if(FLASH, flash_offs & (FLASH_SECTOR_SIZE - 1));
+ invalid_params_if(FLASH, count & (FLASH_SECTOR_SIZE - 1));
+ rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+ rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+ rom_flash_range_erase_fn flash_range_erase = (rom_flash_range_erase_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_ERASE);
+ rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
+ assert(connect_internal_flash && flash_exit_xip && flash_range_erase && flash_flush_cache);
+ flash_init_boot2_copyout();
+
+ // No flash accesses after this point
+ __compiler_memory_barrier();
+
+ connect_internal_flash();
+ flash_exit_xip();
+ flash_range_erase(flash_offs, count, FLASH_BLOCK_SIZE, FLASH_BLOCK_ERASE_CMD);
+ flash_flush_cache(); // Note this is needed to remove CSn IO force as well as cache flushing
+ flash_enable_xip_via_boot2();
+}
+
+void __no_inline_not_in_flash_func(flash_range_program)(uint32_t flash_offs, const uint8_t *data, size_t count) {
+#ifdef PICO_FLASH_SIZE_BYTES
+ hard_assert(flash_offs + count <= PICO_FLASH_SIZE_BYTES);
+#endif
+ invalid_params_if(FLASH, flash_offs & (FLASH_PAGE_SIZE - 1));
+ invalid_params_if(FLASH, count & (FLASH_PAGE_SIZE - 1));
+ rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+ rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+ rom_flash_range_program_fn flash_range_program = (rom_flash_range_program_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_RANGE_PROGRAM);
+ rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
+ assert(connect_internal_flash && flash_exit_xip && flash_range_program && flash_flush_cache);
+ flash_init_boot2_copyout();
+
+ __compiler_memory_barrier();
+
+ connect_internal_flash();
+ flash_exit_xip();
+ flash_range_program(flash_offs, data, count);
+ flash_flush_cache(); // Note this is needed to remove CSn IO force as well as cache flushing
+ flash_enable_xip_via_boot2();
+}
+
+//-----------------------------------------------------------------------------
+// Lower-level flash access functions
+
+#if !PICO_NO_FLASH
+// Bitbanging the chip select using IO overrides, in case RAM-resident IRQs
+// are still running, and the FIFO bottoms out. (the bootrom does the same)
+static void __no_inline_not_in_flash_func(flash_cs_force)(bool high) {
+ uint32_t field_val = high ?
+ IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH :
+ IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW;
+ hw_write_masked(&ioqspi_hw->io[1].ctrl,
+ field_val << IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB,
+ IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS
+ );
+}
+
+void __no_inline_not_in_flash_func(flash_do_cmd)(const uint8_t *txbuf, uint8_t *rxbuf, size_t count) {
+ rom_connect_internal_flash_fn connect_internal_flash = (rom_connect_internal_flash_fn)rom_func_lookup_inline(ROM_FUNC_CONNECT_INTERNAL_FLASH);
+ rom_flash_exit_xip_fn flash_exit_xip = (rom_flash_exit_xip_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_EXIT_XIP);
+ rom_flash_flush_cache_fn flash_flush_cache = (rom_flash_flush_cache_fn)rom_func_lookup_inline(ROM_FUNC_FLASH_FLUSH_CACHE);
+ assert(connect_internal_flash && flash_exit_xip && flash_flush_cache);
+ flash_init_boot2_copyout();
+ __compiler_memory_barrier();
+ connect_internal_flash();
+ flash_exit_xip();
+
+ flash_cs_force(0);
+ size_t tx_remaining = count;
+ size_t rx_remaining = count;
+ // We may be interrupted -- don't want FIFO to overflow if we're distracted.
+ const size_t max_in_flight = 16 - 2;
+ while (tx_remaining || rx_remaining) {
+ uint32_t flags = ssi_hw->sr;
+ bool can_put = !!(flags & SSI_SR_TFNF_BITS);
+ bool can_get = !!(flags & SSI_SR_RFNE_BITS);
+ if (can_put && tx_remaining && rx_remaining - tx_remaining < max_in_flight) {
+ ssi_hw->dr0 = *txbuf++;
+ --tx_remaining;
+ }
+ if (can_get && rx_remaining) {
+ *rxbuf++ = (uint8_t)ssi_hw->dr0;
+ --rx_remaining;
+ }
+ }
+ flash_cs_force(1);
+
+ flash_flush_cache();
+ flash_enable_xip_via_boot2();
+}
+#endif
+
+// Use standard RUID command to get a unique identifier for the flash (and
+// hence the board)
+
+static_assert(FLASH_UNIQUE_ID_SIZE_BYTES == FLASH_RUID_DATA_BYTES, "");
+
+void flash_get_unique_id(uint8_t *id_out) {
+#if PICO_NO_FLASH
+ __unused uint8_t *ignore = id_out;
+ panic_unsupported();
+#else
+ uint8_t txbuf[FLASH_RUID_TOTAL_BYTES] = {0};
+ uint8_t rxbuf[FLASH_RUID_TOTAL_BYTES] = {0};
+ txbuf[0] = FLASH_RUID_CMD;
+ flash_do_cmd(txbuf, rxbuf, FLASH_RUID_TOTAL_BYTES);
+ for (int i = 0; i < FLASH_RUID_DATA_BYTES; i++)
+ id_out[i] = rxbuf[i + 1 + FLASH_RUID_DUMMY_BYTES];
+#endif
+}
diff --git a/arkanoid/pico/hardware/flash.h b/arkanoid/pico/hardware/flash.h
new file mode 100644
index 0000000..6c02f03
--- /dev/null
+++ b/arkanoid/pico/hardware/flash.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_FLASH_H
+#define _HARDWARE_FLASH_H
+
+#include "../pico.h"
+
+/** \file flash.h
+ * \defgroup hardware_flash hardware_flash
+ *
+ * Low level flash programming and erase API
+ *
+ * Note these functions are *unsafe* if you have two cores concurrently
+ * executing from flash. In this case you must perform your own
+ * synchronisation to make sure no XIP accesses take place during flash
+ * programming.
+ *
+ * Likewise they are *unsafe* if you have interrupt handlers or an interrupt
+ * vector table in flash, so you must disable interrupts before calling in
+ * this case.
+ *
+ * If PICO_NO_FLASH=1 is not defined (i.e. if the program is built to run from
+ * flash) then these functions will make a static copy of the second stage
+ * bootloader in SRAM, and use this to reenter execute-in-place mode after
+ * programming or erasing flash, so that they can safely be called from
+ * flash-resident code.
+ *
+ * \subsection flash_example Example
+ * \include flash_program.c
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_FLASH, Enable/disable assertions in the flash module, type=bool, default=0, group=hardware_flash
+#ifndef PARAM_ASSERTIONS_ENABLED_FLASH
+#define PARAM_ASSERTIONS_ENABLED_FLASH 0
+#endif
+
+#define FLASH_PAGE_SIZE (1u << 8)
+#define FLASH_SECTOR_SIZE (1u << 12)
+#define FLASH_BLOCK_SIZE (1u << 16)
+
+#define FLASH_UNIQUE_ID_SIZE_BYTES 8
+
+// PICO_CONFIG: PICO_FLASH_SIZE_BYTES, size of primary flash in bytes, type=int, group=hardware_flash
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Erase areas of flash
+ * \ingroup hardware_flash
+ *
+ * \param flash_offs Offset into flash, in bytes, to start the erase. Must be aligned to a 4096-byte flash sector.
+ * \param count Number of bytes to be erased. Must be a multiple of 4096 bytes (one sector).
+ */
+void flash_range_erase(uint32_t flash_offs, size_t count);
+
+/*! \brief Program flash
+ * \ingroup hardware_flash
+ *
+ * \param flash_offs Flash address of the first byte to be programmed. Must be aligned to a 256-byte flash page.
+ * \param data Pointer to the data to program into flash
+ * \param count Number of bytes to program. Must be a multiple of 256 bytes (one page).
+ */
+
+void flash_range_program(uint32_t flash_offs, const uint8_t *data, size_t count);
+
+/*! \brief Get flash unique 64 bit identifier
+ * \ingroup hardware_flash
+ *
+ * Use a standard 4Bh RUID instruction to retrieve the 64 bit unique
+ * identifier from a flash device attached to the QSPI interface. Since there
+ * is a 1:1 association between the MCU and this flash, this also serves as a
+ * unique identifier for the board.
+ *
+ * \param id_out Pointer to an 8-byte buffer to which the ID will be written
+ */
+void flash_get_unique_id(uint8_t *id_out);
+
+/*! \brief Execute bidirectional flash command
+ * \ingroup hardware_flash
+ *
+ * Low-level function to execute a serial command on a flash device attached
+ * to the QSPI interface. Bytes are simultaneously transmitted and received
+ * from txbuf and to rxbuf. Therefore, both buffers must be the same length,
+ * count, which is the length of the overall transaction. This is useful for
+ * reading metadata from the flash chip, such as device ID or SFDP
+ * parameters.
+ *
+ * The XIP cache is flushed following each command, in case flash state
+ * has been modified. Like other hardware_flash functions, the flash is not
+ * accessible for execute-in-place transfers whilst the command is in
+ * progress, so entering a flash-resident interrupt handler or executing flash
+ * code on the second core concurrently will be fatal. To avoid these pitfalls
+ * it is recommended that this function only be used to extract flash metadata
+ * during startup, before the main application begins to run: see the
+ * implementation of pico_get_unique_id() for an example of this.
+ *
+ * \param txbuf Pointer to a byte buffer which will be transmitted to the flash
+ * \param rxbuf Pointer to a byte buffer where data received from the flash will be written. txbuf and rxbuf may be the same buffer.
+ * \param count Length in bytes of txbuf and of rxbuf
+ */
+void flash_do_cmd(const uint8_t *txbuf, uint8_t *rxbuf, size_t count);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/gpio.c b/arkanoid/pico/hardware/gpio.c
new file mode 100644
index 0000000..e072b64
--- /dev/null
+++ b/arkanoid/pico/hardware/gpio.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "gpio.h"
+#include "sync.h"
+
+#include "structs/iobank0.h"
+#include "irq.h"
+
+#if LIB_PICO_BINARY_INFO
+#include "../binary_info.h"
+#endif
+
+static gpio_irq_callback_t _callbacks[NUM_CORES];
+
+// Get the raw value from the pin, bypassing any muxing or overrides.
+int gpio_get_pad(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+ return (iobank0_hw->io[gpio].status & IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS)
+ >> IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB;
+}
+
+/// \tag::gpio_set_function[]
+// Select function for this GPIO, and ensure input/output are enabled at the pad.
+// This also clears the input/output/irq override bits.
+void gpio_set_function(uint gpio, enum gpio_function fn) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ invalid_params_if(GPIO, ((uint32_t)fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB) & ~IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS);
+ // Set input enable on, output disable off
+ hw_write_masked(&padsbank0_hw->io[gpio],
+ PADS_BANK0_GPIO0_IE_BITS,
+ PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS
+ );
+ // Zero all fields apart from fsel; we want this IO to do what the peripheral tells it.
+ // This doesn't affect e.g. pullup/pulldown, as these are in pad controls.
+ iobank0_hw->io[gpio].ctrl = fn << IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB;
+}
+/// \end::gpio_set_function[]
+
+enum gpio_function gpio_get_function(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ return (enum gpio_function) ((iobank0_hw->io[gpio].ctrl & IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS) >> IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB);
+}
+
+// Note that, on RP2040, setting both pulls enables a "bus keep" function,
+// i.e. weak pull to whatever is current high/low state of GPIO.
+void gpio_set_pulls(uint gpio, bool up, bool down) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(
+ &padsbank0_hw->io[gpio],
+ (bool_to_bit(up) << PADS_BANK0_GPIO0_PUE_LSB) | (bool_to_bit(down) << PADS_BANK0_GPIO0_PDE_LSB),
+ PADS_BANK0_GPIO0_PUE_BITS | PADS_BANK0_GPIO0_PDE_BITS
+ );
+}
+
+// Direct override for per-GPIO IRQ signal
+void gpio_set_irqover(uint gpio, uint value) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+ value << IO_BANK0_GPIO0_CTRL_IRQOVER_LSB,
+ IO_BANK0_GPIO0_CTRL_IRQOVER_BITS
+ );
+}
+
+// Direct overrides for pad controls
+void gpio_set_inover(uint gpio, uint value) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+ value << IO_BANK0_GPIO0_CTRL_INOVER_LSB,
+ IO_BANK0_GPIO0_CTRL_INOVER_BITS
+ );
+}
+
+void gpio_set_outover(uint gpio, uint value) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+ value << IO_BANK0_GPIO0_CTRL_OUTOVER_LSB,
+ IO_BANK0_GPIO0_CTRL_OUTOVER_BITS
+ );
+}
+
+void gpio_set_oeover(uint gpio, uint value) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&iobank0_hw->io[gpio].ctrl,
+ value << IO_BANK0_GPIO0_CTRL_OEOVER_LSB,
+ IO_BANK0_GPIO0_CTRL_OEOVER_BITS
+ );
+}
+
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ if (enabled)
+ hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+ else
+ hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_SCHMITT_BITS);
+}
+
+
+bool gpio_is_input_hysteresis_enabled(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_SCHMITT_BITS) != 0;
+}
+
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&padsbank0_hw->io[gpio],
+ (uint)slew << PADS_BANK0_GPIO0_SLEWFAST_LSB,
+ PADS_BANK0_GPIO0_SLEWFAST_BITS
+ );
+}
+
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ return (enum gpio_slew_rate)((padsbank0_hw->io[gpio]
+ & PADS_BANK0_GPIO0_SLEWFAST_BITS)
+ >> PADS_BANK0_GPIO0_SLEWFAST_LSB);
+}
+
+
+// Enum encoding should match hardware encoding on RP2040
+static_assert(PADS_BANK0_GPIO0_DRIVE_VALUE_8MA == GPIO_DRIVE_STRENGTH_8MA, "");
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ hw_write_masked(&padsbank0_hw->io[gpio],
+ (uint)drive << PADS_BANK0_GPIO0_DRIVE_LSB,
+ PADS_BANK0_GPIO0_DRIVE_BITS
+ );
+}
+
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio) {
+ invalid_params_if(GPIO, gpio >= NUM_BANK0_GPIOS);
+ return (enum gpio_drive_strength)((padsbank0_hw->io[gpio]
+ & PADS_BANK0_GPIO0_DRIVE_BITS)
+ >> PADS_BANK0_GPIO0_DRIVE_LSB);
+}
+
+static void gpio_irq_handler(void) {
+ io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
+ &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+ for (uint gpio = 0; gpio < NUM_BANK0_GPIOS; gpio++) {
+ io_ro_32 *status_reg = &irq_ctrl_base->ints[gpio / 8];
+ uint events = (*status_reg >> 4 * (gpio % 8)) & 0xf;
+ if (events) {
+ // TODO: If both cores care about this event then the second core won't get the irq?
+ gpio_acknowledge_irq(gpio, events);
+ gpio_irq_callback_t callback = _callbacks[get_core_num()];
+ if (callback) {
+ callback(gpio, events);
+ }
+ }
+ }
+}
+
+static void _gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled, io_irq_ctrl_hw_t *irq_ctrl_base) {
+ // Clear stale events which might cause immediate spurious handler entry
+ gpio_acknowledge_irq(gpio, events);
+
+ io_rw_32 *en_reg = &irq_ctrl_base->inte[gpio / 8];
+ events <<= 4 * (gpio % 8);
+
+ if (enabled)
+ hw_set_bits(en_reg, events);
+ else
+ hw_clear_bits(en_reg, events);
+}
+
+void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled) {
+ // Separate mask/force/status per-core, so check which core called, and
+ // set the relevant IRQ controls.
+ io_irq_ctrl_hw_t *irq_ctrl_base = get_core_num() ?
+ &iobank0_hw->proc1_irq_ctrl : &iobank0_hw->proc0_irq_ctrl;
+ _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base);
+}
+
+void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback) {
+ gpio_set_irq_enabled(gpio, events, enabled);
+
+ // TODO: Do we want to support a callback per GPIO pin?
+ // Install IRQ handler
+ _callbacks[get_core_num()] = callback;
+ irq_set_exclusive_handler(IO_IRQ_BANK0, gpio_irq_handler);
+ irq_set_enabled(IO_IRQ_BANK0, true);
+}
+
+void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled) {
+ io_irq_ctrl_hw_t *irq_ctrl_base = &iobank0_hw->dormant_wake_irq_ctrl;
+ _gpio_set_irq_enabled(gpio, events, enabled, irq_ctrl_base);
+}
+
+void gpio_acknowledge_irq(uint gpio, uint32_t events) {
+ iobank0_hw->intr[gpio / 8] = events << 4 * (gpio % 8);
+}
+
+#define DEBUG_PIN_MASK (((1u << PICO_DEBUG_PIN_COUNT)-1) << PICO_DEBUG_PIN_BASE)
+void gpio_debug_pins_init() {
+ gpio_init_mask(DEBUG_PIN_MASK);
+ gpio_set_dir_masked(DEBUG_PIN_MASK, DEBUG_PIN_MASK);
+#if LIB_PICO_BINARY_INFO
+ bi_decl_if_func_used(bi_pin_mask_with_names(DEBUG_PIN_MASK, "Debug"));
+#endif
+}
+
+void gpio_set_input_enabled(uint gpio, bool enabled) {
+ if (enabled)
+ hw_set_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+ else
+ hw_clear_bits(&padsbank0_hw->io[gpio], PADS_BANK0_GPIO0_IE_BITS);
+}
+
+void gpio_init(uint gpio) {
+ sio_hw->gpio_oe_clr = 1ul << gpio;
+ sio_hw->gpio_clr = 1ul << gpio;
+ gpio_set_function(gpio, GPIO_FUNC_SIO);
+}
+
+void gpio_init_mask(uint gpio_mask) {
+ for(uint i=0;i<32;i++) {
+ if (gpio_mask & 1) {
+ gpio_init(i);
+ }
+ gpio_mask >>= 1;
+ }
+}
+
diff --git a/arkanoid/pico/hardware/gpio.h b/arkanoid/pico/hardware/gpio.h
new file mode 100644
index 0000000..c2405d7
--- /dev/null
+++ b/arkanoid/pico/hardware/gpio.h
@@ -0,0 +1,656 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_GPIO_H_
+#define _HARDWARE_GPIO_H_
+
+#include "../pico.h"
+#include "structs/sio.h"
+#include "structs/padsbank0.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_GPIO, Enable/disable assertions in the GPIO module, type=bool, default=0, group=hardware_gpio
+#ifndef PARAM_ASSERTIONS_ENABLED_GPIO
+#define PARAM_ASSERTIONS_ENABLED_GPIO 0
+#endif
+
+/** \file gpio.h
+ * \defgroup hardware_gpio hardware_gpio
+ *
+ * General Purpose Input/Output (GPIO) API
+ *
+ * RP2040 has 36 multi-functional General Purpose Input / Output (GPIO) pins, divided into two banks. In a typical use case,
+ * the pins in the QSPI bank (QSPI_SS, QSPI_SCLK and QSPI_SD0 to QSPI_SD3) are used to execute code from an external
+ * flash device, leaving the User bank (GPIO0 to GPIO29) for the programmer to use. All GPIOs support digital input and
+ * output, but GPIO26 to GPIO29 can also be used as inputs to the chip’s Analogue to Digital Converter (ADC). Each GPIO
+ * can be controlled directly by software running on the processors, or by a number of other functional blocks.
+ *
+ * The function allocated to each GPIO is selected by calling the \ref gpio_set_function function. \note Not all functions
+ * are available on all pins.
+ *
+ * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be selected on
+ * one _GPIO_ at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical OR of these
+ * GPIO inputs. Please refer to the datasheet for more information on GPIO function select.
+ *
+ * ### Function Select Table
+ *
+ * GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9
+ * -------|----------|-----------|----------|--------|-----|------|------|---------------|----
+ * 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN
+ * 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN
+ * 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN
+ * 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN
+ * 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN
+ * 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN
+ * 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN
+ * 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET
+ * 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET
+ * 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN
+ * 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET
+ * 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET
+ * 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN
+ * 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET
+ * 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET
+ * 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN
+
+ */
+
+/*! \brief GPIO function definitions for use with function select
+ * \ingroup hardware_gpio
+ * \brief GPIO function selectors
+ *
+ * Each GPIO can have one function selected at a time. Likewise, each peripheral input (e.g. UART0 RX) should only be
+ * selected on one GPIO at a time. If the same peripheral input is connected to multiple GPIOs, the peripheral sees the logical
+ * OR of these GPIO inputs.
+ *
+ * Please refer to the datsheet for more information on GPIO function selection.
+ */
+enum gpio_function {
+ GPIO_FUNC_XIP = 0,
+ GPIO_FUNC_SPI = 1,
+ GPIO_FUNC_UART = 2,
+ GPIO_FUNC_I2C = 3,
+ GPIO_FUNC_PWM = 4,
+ GPIO_FUNC_SIO = 5,
+ GPIO_FUNC_PIO0 = 6,
+ GPIO_FUNC_PIO1 = 7,
+ GPIO_FUNC_GPCK = 8,
+ GPIO_FUNC_USB = 9,
+ GPIO_FUNC_NULL = 0x1f,
+};
+
+#define GPIO_OUT 1
+#define GPIO_IN 0
+
+/*! \brief GPIO Interrupt level definitions
+ * \ingroup hardware_gpio
+ * \brief GPIO Interrupt levels
+ *
+ * An interrupt can be generated for every GPIO pin in 4 scenarios:
+ *
+ * * Level High: the GPIO pin is a logical 1
+ * * Level Low: the GPIO pin is a logical 0
+ * * Edge High: the GPIO has transitioned from a logical 0 to a logical 1
+ * * Edge Low: the GPIO has transitioned from a logical 1 to a logical 0
+ *
+ * The level interrupts are not latched. This means that if the pin is a logical 1 and the level high interrupt is active, it will
+ * become inactive as soon as the pin changes to a logical 0. The edge interrupts are stored in the INTR register and can be
+ * cleared by writing to the INTR register.
+ */
+enum gpio_irq_level {
+ GPIO_IRQ_LEVEL_LOW = 0x1u,
+ GPIO_IRQ_LEVEL_HIGH = 0x2u,
+ GPIO_IRQ_EDGE_FALL = 0x4u,
+ GPIO_IRQ_EDGE_RISE = 0x8u,
+};
+
+/*! Callback function type for GPIO events
+ * \ingroup hardware_gpio
+ *
+ * \param gpio Which GPIO caused this interrupt
+ * \param events Which events caused this interrupt. See \ref gpio_set_irq_enabled for details.
+ * \sa gpio_set_irq_enabled_with_callback()
+ */
+typedef void (*gpio_irq_callback_t)(uint gpio, uint32_t events);
+
+enum gpio_override {
+ GPIO_OVERRIDE_NORMAL = 0, ///< peripheral signal selected via \ref gpio_set_function
+ GPIO_OVERRIDE_INVERT = 1, ///< invert peripheral signal selected via \ref gpio_set_function
+ GPIO_OVERRIDE_LOW = 2, ///< drive low/disable output
+ GPIO_OVERRIDE_HIGH = 3, ///< drive high/enable output
+};
+
+/*! \brief Slew rate limiting levels for GPIO outputs
+ * \ingroup hardware_gpio
+ *
+ * Slew rate limiting increases the minimum rise/fall time when a GPIO output
+ * is lightly loaded, which can help to reduce electromagnetic emissions.
+ * \sa gpio_set_slew_rate
+ */
+enum gpio_slew_rate {
+ GPIO_SLEW_RATE_SLOW = 0, ///< Slew rate limiting enabled
+ GPIO_SLEW_RATE_FAST = 1 ///< Slew rate limiting disabled
+};
+
+/*! \brief Drive strength levels for GPIO outputs
+ * \ingroup hardware_gpio
+ *
+ * Drive strength levels for GPIO outputs.
+ * \sa gpio_set_drive_strength
+ */
+enum gpio_drive_strength {
+ GPIO_DRIVE_STRENGTH_2MA = 0, ///< 2 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_4MA = 1, ///< 4 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_8MA = 2, ///< 8 mA nominal drive strength
+ GPIO_DRIVE_STRENGTH_12MA = 3 ///< 12 mA nominal drive strength
+};
+
+// ----------------------------------------------------------------------------
+// Pad Controls + IO Muxing
+// ----------------------------------------------------------------------------
+// Declarations for gpio.c
+
+/*! \brief Select GPIO function
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param fn Which GPIO function select to use from list \ref gpio_function
+ */
+void gpio_set_function(uint gpio, enum gpio_function fn);
+
+/*! \brief Determine current GPIO function
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return Which GPIO function is currently selected from list \ref gpio_function
+ */
+enum gpio_function gpio_get_function(uint gpio);
+
+/*! \brief Select up and down pulls on specific GPIO
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param up If true set a pull up on the GPIO
+ * \param down If true set a pull down on the GPIO
+ *
+ * \note On the RP2040, setting both pulls enables a "bus keep" function,
+ * i.e. a weak pull to whatever is current high/low state of GPIO.
+ */
+void gpio_set_pulls(uint gpio, bool up, bool down);
+
+/*! \brief Set specified GPIO to be pulled up.
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ */
+static inline void gpio_pull_up(uint gpio) {
+ gpio_set_pulls(gpio, true, false);
+}
+
+/*! \brief Determine if the specified GPIO is pulled up.
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return true if the GPIO is pulled up
+ */
+static inline bool gpio_is_pulled_up(uint gpio) {
+ return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PUE_BITS) != 0;
+}
+
+/*! \brief Set specified GPIO to be pulled down.
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ */
+static inline void gpio_pull_down(uint gpio) {
+ gpio_set_pulls(gpio, false, true);
+}
+
+/*! \brief Determine if the specified GPIO is pulled down.
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return true if the GPIO is pulled down
+ */
+static inline bool gpio_is_pulled_down(uint gpio) {
+ return (padsbank0_hw->io[gpio] & PADS_BANK0_GPIO0_PDE_BITS) != 0;
+}
+
+/*! \brief Disable pulls on specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ */
+static inline void gpio_disable_pulls(uint gpio) {
+ gpio_set_pulls(gpio, false, false);
+}
+
+/*! \brief Set GPIO IRQ override
+ * \ingroup hardware_gpio
+ *
+ * Optionally invert a GPIO IRQ signal, or drive it high or low
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_irqover(uint gpio, uint value);
+
+/*! \brief Set GPIO output override
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_outover(uint gpio, uint value);
+
+/*! \brief Select GPIO input override
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_inover(uint gpio, uint value);
+
+/*! \brief Select GPIO output enable override
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value See \ref gpio_override
+ */
+void gpio_set_oeover(uint gpio, uint value);
+
+/*! \brief Enable GPIO input
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param enabled true to enable input on specified GPIO
+ */
+void gpio_set_input_enabled(uint gpio, bool enabled);
+
+/*! \brief Enable/disable GPIO input hysteresis (Schmitt trigger)
+ * \ingroup hardware_gpio
+ *
+ * Enable or disable the Schmitt trigger hysteresis on a given GPIO. This is
+ * enabled on all GPIOs by default. Disabling input hysteresis can lead to
+ * inconsistent readings when the input signal has very long rise or fall
+ * times, but slightly reduces the GPIO's input delay.
+ *
+ * \sa gpio_is_input_hysteresis_enabled
+ * \param gpio GPIO number
+ * \param enabled true to enable input hysteresis on specified GPIO
+ */
+void gpio_set_input_hysteresis_enabled(uint gpio, bool enabled);
+
+/*! \brief Determine whether input hysteresis is enabled on a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_set_input_hysteresis_enabled
+ * \param gpio GPIO number
+ */
+bool gpio_is_input_hysteresis_enabled(uint gpio);
+
+
+/*! \brief Set slew rate for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_get_slew_rate
+ * \param gpio GPIO number
+ * \param slew GPIO output slew rate
+ */
+void gpio_set_slew_rate(uint gpio, enum gpio_slew_rate slew);
+
+/*! \brief Determine current slew rate for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_set_slew_rate
+ * \param gpio GPIO number
+ * \return Current slew rate of that GPIO
+ */
+enum gpio_slew_rate gpio_get_slew_rate(uint gpio);
+
+/*! \brief Set drive strength for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_get_drive_strength
+ * \param gpio GPIO number
+ * \param drive GPIO output drive strength
+ */
+void gpio_set_drive_strength(uint gpio, enum gpio_drive_strength drive);
+
+/*! \brief Determine current slew rate for a specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \sa gpio_set_drive_strength
+ * \param gpio GPIO number
+ * \return Current drive strength of that GPIO
+ */
+enum gpio_drive_strength gpio_get_drive_strength(uint gpio);
+
+/*! \brief Enable or disable interrupts for specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \note The IO IRQs are independent per-processor. This configures IRQs for
+ * the processor that calls the function.
+ *
+ * \param gpio GPIO number
+ * \param events Which events will cause an interrupt
+ * \param enabled Enable or disable flag
+ *
+ * Events is a bitmask of the following:
+ *
+ * bit | interrupt
+ * ----|----------
+ * 0 | Low level
+ * 1 | High level
+ * 2 | Edge low
+ * 3 | Edge high
+ */
+void gpio_set_irq_enabled(uint gpio, uint32_t events, bool enabled);
+
+/*! \brief Enable interrupts for specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \note The IO IRQs are independent per-processor. This configures IRQs for
+ * the processor that calls the function.
+ *
+ * \param gpio GPIO number
+ * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details.
+ * \param enabled Enable or disable flag
+ * \param callback user function to call on GPIO irq. Note only one of these can be set per processor.
+ *
+ * \note Currently the GPIO parameter is ignored, and this callback will be called for any enabled GPIO IRQ on any pin.
+ *
+ */
+void gpio_set_irq_enabled_with_callback(uint gpio, uint32_t events, bool enabled, gpio_irq_callback_t callback);
+
+/*! \brief Enable dormant wake up interrupt for specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * This configures IRQs to restart the XOSC or ROSC when they are
+ * disabled in dormant mode
+ *
+ * \param gpio GPIO number
+ * \param events Which events will cause an interrupt. See \ref gpio_set_irq_enabled for details.
+ * \param enabled Enable/disable flag
+ */
+void gpio_set_dormant_irq_enabled(uint gpio, uint32_t events, bool enabled);
+
+/*! \brief Acknowledge a GPIO interrupt
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param events Bitmask of events to clear. See \ref gpio_set_irq_enabled for details.
+ *
+ */
+void gpio_acknowledge_irq(uint gpio, uint32_t events);
+
+/*! \brief Initialise a GPIO for (enabled I/O and set func to GPIO_FUNC_SIO)
+ * \ingroup hardware_gpio
+ *
+ * Clear the output enable (i.e. set to input).
+ * Clear any output value.
+ *
+ * \param gpio GPIO number
+ */
+void gpio_init(uint gpio);
+
+/*! \brief Initialise multiple GPIOs (enabled I/O and set func to GPIO_FUNC_SIO)
+ * \ingroup hardware_gpio
+ *
+ * Clear the output enable (i.e. set to input).
+ * Clear any output value.
+ *
+ * \param gpio_mask Mask with 1 bit per GPIO number to initialize
+ */
+void gpio_init_mask(uint gpio_mask);
+// ----------------------------------------------------------------------------
+// Input
+// ----------------------------------------------------------------------------
+
+/*! \brief Get state of a single specified GPIO
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return Current state of the GPIO. 0 for low, non-zero for high
+ */
+static inline bool gpio_get(uint gpio) {
+ return !!((1ul << gpio) & sio_hw->gpio_in);
+}
+
+/*! \brief Get raw value of all GPIOs
+ * \ingroup hardware_gpio
+ *
+ * \return Bitmask of raw GPIO values, as bits 0-29
+ */
+static inline uint32_t gpio_get_all(void) {
+ return sio_hw->gpio_in;
+}
+
+// ----------------------------------------------------------------------------
+// Output
+// ----------------------------------------------------------------------------
+
+/*! \brief Drive high every GPIO appearing in mask
+ * \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to set, as bits 0-29
+ */
+static inline void gpio_set_mask(uint32_t mask) {
+ sio_hw->gpio_set = mask;
+}
+
+/*! \brief Drive low every GPIO appearing in mask
+ * \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to clear, as bits 0-29
+ */
+static inline void gpio_clr_mask(uint32_t mask) {
+ sio_hw->gpio_clr = mask;
+}
+
+/*! \brief Toggle every GPIO appearing in mask
+ * \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to toggle, as bits 0-29
+ */
+static inline void gpio_xor_mask(uint32_t mask) {
+ sio_hw->gpio_togl = mask;
+}
+
+/*! \brief Drive GPIO high/low depending on parameters
+ * \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO values to change, as bits 0-29
+ * \param value Value to set
+ *
+ * For each 1 bit in \p mask, drive that pin to the value given by
+ * corresponding bit in \p value, leaving other pins unchanged.
+ * Since this uses the TOGL alias, it is concurrency-safe with e.g. an IRQ
+ * bashing different pins from the same core.
+ */
+static inline void gpio_put_masked(uint32_t mask, uint32_t value) {
+ sio_hw->gpio_togl = (sio_hw->gpio_out ^ value) & mask;
+}
+
+/*! \brief Drive all pins simultaneously
+ * \ingroup hardware_gpio
+ *
+ * \param value Bitmask of GPIO values to change, as bits 0-29
+ */
+static inline void gpio_put_all(uint32_t value) {
+ sio_hw->gpio_out = value;
+}
+
+/*! \brief Drive a single GPIO high/low
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param value If false clear the GPIO, otherwise set it.
+ */
+static inline void gpio_put(uint gpio, bool value) {
+ uint32_t mask = 1ul << gpio;
+ if (value)
+ gpio_set_mask(mask);
+ else
+ gpio_clr_mask(mask);
+}
+
+/*! \brief Determine whether a GPIO is currently driven high or low
+ * \ingroup hardware_gpio
+ *
+ * This function returns the high/low output level most recently assigned to a
+ * GPIO via gpio_put() or similar. This is the value that is presented outward
+ * to the IO muxing, *not* the input level back from the pad (which can be
+ * read using gpio_get()).
+ *
+ * To avoid races, this function must not be used for read-modify-write
+ * sequences when driving GPIOs -- instead functions like gpio_put() should be
+ * used to atomically update GPIOs. This accessor is intended for debug use
+ * only.
+ *
+ * \param gpio GPIO number
+ * \return true if the GPIO output level is high, false if low.
+ */
+static inline bool gpio_get_out_level(uint gpio) {
+ return !!(sio_hw->gpio_out & (1u << gpio));
+}
+
+// ----------------------------------------------------------------------------
+// Direction
+// ----------------------------------------------------------------------------
+
+/*! \brief Set a number of GPIOs to output
+ * \ingroup hardware_gpio
+ *
+ * Switch all GPIOs in "mask" to output
+ *
+ * \param mask Bitmask of GPIO to set to output, as bits 0-29
+ */
+static inline void gpio_set_dir_out_masked(uint32_t mask) {
+ sio_hw->gpio_oe_set = mask;
+}
+
+/*! \brief Set a number of GPIOs to input
+ * \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO to set to input, as bits 0-29
+ */
+static inline void gpio_set_dir_in_masked(uint32_t mask) {
+ sio_hw->gpio_oe_clr = mask;
+}
+
+/*! \brief Set multiple GPIO directions
+ * \ingroup hardware_gpio
+ *
+ * \param mask Bitmask of GPIO to set to input, as bits 0-29
+ * \param value Values to set
+ *
+ * For each 1 bit in "mask", switch that pin to the direction given by
+ * corresponding bit in "value", leaving other pins unchanged.
+ * E.g. gpio_set_dir_masked(0x3, 0x2); -> set pin 0 to input, pin 1 to output,
+ * simultaneously.
+ */
+static inline void gpio_set_dir_masked(uint32_t mask, uint32_t value) {
+ sio_hw->gpio_oe_togl = (sio_hw->gpio_oe ^ value) & mask;
+}
+
+/*! \brief Set direction of all pins simultaneously.
+ * \ingroup hardware_gpio
+ *
+ * \param values individual settings for each gpio; for GPIO N, bit N is 1 for out, 0 for in
+ */
+static inline void gpio_set_dir_all_bits(uint32_t values) {
+ sio_hw->gpio_oe = values;
+}
+
+/*! \brief Set a single GPIO direction
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \param out true for out, false for in
+ */
+static inline void gpio_set_dir(uint gpio, bool out) {
+ uint32_t mask = 1ul << gpio;
+ if (out)
+ gpio_set_dir_out_masked(mask);
+ else
+ gpio_set_dir_in_masked(mask);
+}
+
+/*! \brief Check if a specific GPIO direction is OUT
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return true if the direction for the pin is OUT
+ */
+static inline bool gpio_is_dir_out(uint gpio) {
+ return !!(sio_hw->gpio_oe & (1u << (gpio)));
+}
+
+/*! \brief Get a specific GPIO direction
+ * \ingroup hardware_gpio
+ *
+ * \param gpio GPIO number
+ * \return 1 for out, 0 for in
+ */
+static inline uint gpio_get_dir(uint gpio) {
+ return gpio_is_dir_out(gpio); // note GPIO_OUT is 1/true and GPIO_IN is 0/false anyway
+}
+
+extern void gpio_debug_pins_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+
+// PICO_CONFIG: PICO_DEBUG_PIN_BASE, First pin to use for debug output (if enabled), min=0, max=28, default=19, group=hardware_gpio
+#ifndef PICO_DEBUG_PIN_BASE
+#define PICO_DEBUG_PIN_BASE 19u
+#endif
+
+// PICO_CONFIG: PICO_DEBUG_PIN_COUNT, Number of pins to use for debug output (if enabled), min=1, max=28, default=3, group=hardware_gpio
+#ifndef PICO_DEBUG_PIN_COUNT
+#define PICO_DEBUG_PIN_COUNT 3u
+#endif
+
+#ifndef __cplusplus
+// note these two macros may only be used once per and only apply per compilation unit (hence the CU_)
+#define CU_REGISTER_DEBUG_PINS(...) enum __unused DEBUG_PIN_TYPE { _none = 0, __VA_ARGS__ }; static enum DEBUG_PIN_TYPE __selected_debug_pins;
+#define CU_SELECT_DEBUG_PINS(x) static enum DEBUG_PIN_TYPE __selected_debug_pins = (x);
+#define DEBUG_PINS_ENABLED(p) (__selected_debug_pins == (p))
+#else
+#define CU_REGISTER_DEBUG_PINS(p...) \
+ enum DEBUG_PIN_TYPE { _none = 0, p }; \
+ template <enum DEBUG_PIN_TYPE> class __debug_pin_settings { \
+ public: \
+ static inline bool enabled() { return false; } \
+ };
+#define CU_SELECT_DEBUG_PINS(x) template<> inline bool __debug_pin_settings<x>::enabled() { return true; };
+#define DEBUG_PINS_ENABLED(p) (__debug_pin_settings<p>::enabled())
+#endif
+#define DEBUG_PINS_SET(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_set_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
+#define DEBUG_PINS_CLR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_clr_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
+#define DEBUG_PINS_XOR(p, v) if (DEBUG_PINS_ENABLED(p)) gpio_xor_mask((unsigned)(v)<<PICO_DEBUG_PIN_BASE)
+
+#endif // _GPIO_H_
diff --git a/arkanoid/pico/hardware/i2c.c b/arkanoid/pico/hardware/i2c.c
new file mode 100644
index 0000000..ee0e779
--- /dev/null
+++ b/arkanoid/pico/hardware/i2c.c
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "i2c.h"
+#include "resets.h"
+#include "clocks.h"
+#include "../timeout_helper.h"
+
+check_hw_layout(i2c_hw_t, enable, I2C_IC_ENABLE_OFFSET);
+check_hw_layout(i2c_hw_t, clr_restart_det, I2C_IC_CLR_RESTART_DET_OFFSET);
+
+i2c_inst_t i2c0_inst = {i2c0_hw, false};
+i2c_inst_t i2c1_inst = {i2c1_hw, false};
+
+static inline void i2c_reset(i2c_inst_t *i2c) {
+ invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1);
+ reset_block(i2c == i2c0 ? RESETS_RESET_I2C0_BITS : RESETS_RESET_I2C1_BITS);
+}
+
+static inline void i2c_unreset(i2c_inst_t *i2c) {
+ invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1);
+ unreset_block_wait(i2c == i2c0 ? RESETS_RESET_I2C0_BITS : RESETS_RESET_I2C1_BITS);
+}
+
+// Addresses of the form 000 0xxx or 111 1xxx are reserved. No slave should
+// have these addresses.
+static inline bool i2c_reserved_addr(uint8_t addr) {
+ return (addr & 0x78) == 0 || (addr & 0x78) == 0x78;
+}
+
+uint i2c_init(i2c_inst_t *i2c, uint baudrate) {
+ i2c_reset(i2c);
+ i2c_unreset(i2c);
+ i2c->restart_on_next = false;
+
+ i2c->hw->enable = 0;
+
+ // Configure as a fast-mode master with RepStart support, 7-bit addresses
+ i2c->hw->con =
+ I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB |
+ I2C_IC_CON_MASTER_MODE_BITS |
+ I2C_IC_CON_IC_SLAVE_DISABLE_BITS |
+ I2C_IC_CON_IC_RESTART_EN_BITS |
+ I2C_IC_CON_TX_EMPTY_CTRL_BITS;
+
+ // Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0.
+ i2c->hw->tx_tl = 0;
+ i2c->hw->rx_tl = 0;
+
+ // Always enable the DREQ signalling -- harmless if DMA isn't listening
+ i2c->hw->dma_cr = I2C_IC_DMA_CR_TDMAE_BITS | I2C_IC_DMA_CR_RDMAE_BITS;
+
+ // Re-sets i2c->hw->enable upon returning:
+ return i2c_set_baudrate(i2c, baudrate);
+}
+
+void i2c_deinit(i2c_inst_t *i2c) {
+ i2c_reset(i2c);
+}
+
+uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate) {
+ invalid_params_if(I2C, baudrate == 0);
+ // I2C is synchronous design that runs from clk_sys
+ uint freq_in = clock_get_hz(clk_sys);
+
+ // TODO there are some subtleties to I2C timing which we are completely ignoring here
+ uint period = (freq_in + baudrate / 2) / baudrate;
+ uint lcnt = period * 3 / 5; // oof this one hurts
+ uint hcnt = period - lcnt;
+ // Check for out-of-range divisors:
+ invalid_params_if(I2C, hcnt > I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS);
+ invalid_params_if(I2C, lcnt > I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS);
+ invalid_params_if(I2C, hcnt < 8);
+ invalid_params_if(I2C, lcnt < 8);
+
+ // Per I2C-bus specification a device in standard or fast mode must
+ // internally provide a hold time of at least 300ns for the SDA signal to
+ // bridge the undefined region of the falling edge of SCL. A smaller hold
+ // time of 120ns is used for fast mode plus.
+ uint sda_tx_hold_count;
+ if (baudrate < 1000000) {
+ // sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns)
+ // Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint.
+ // Add 1 to avoid division truncation.
+ sda_tx_hold_count = ((freq_in * 3) / 10000000) + 1;
+ } else {
+ // sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns)
+ // Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint.
+ // Add 1 to avoid division truncation.
+ sda_tx_hold_count = ((freq_in * 3) / 25000000) + 1;
+ }
+ assert(sda_tx_hold_count <= lcnt - 2);
+
+ i2c->hw->enable = 0;
+ // Always use "fast" mode (<= 400 kHz, works fine for standard mode too)
+ hw_write_masked(&i2c->hw->con,
+ I2C_IC_CON_SPEED_VALUE_FAST << I2C_IC_CON_SPEED_LSB,
+ I2C_IC_CON_SPEED_BITS
+ );
+ i2c->hw->fs_scl_hcnt = hcnt;
+ i2c->hw->fs_scl_lcnt = lcnt;
+ i2c->hw->fs_spklen = lcnt < 16 ? 1 : lcnt / 16;
+ hw_write_masked(&i2c->hw->sda_hold,
+ sda_tx_hold_count << I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB,
+ I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS);
+
+ i2c->hw->enable = 1;
+ return freq_in / period;
+}
+
+void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr) {
+ invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
+ invalid_params_if(I2C, i2c_reserved_addr(addr));
+ i2c->hw->enable = 0;
+ uint32_t ctrl_set_if_master = I2C_IC_CON_MASTER_MODE_BITS | I2C_IC_CON_IC_SLAVE_DISABLE_BITS;
+ uint32_t ctrl_set_if_slave = I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS;
+ if (slave) {
+ hw_write_masked(&i2c->hw->con,
+ ctrl_set_if_slave,
+ ctrl_set_if_master | ctrl_set_if_slave
+ );
+ i2c->hw->sar = addr;
+ } else {
+ hw_write_masked(&i2c->hw->con,
+ ctrl_set_if_master,
+ ctrl_set_if_master | ctrl_set_if_slave
+ );
+ }
+ i2c->hw->enable = 1;
+}
+
+static int i2c_write_blocking_internal(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop,
+ check_timeout_fn timeout_check, struct timeout_state *ts) {
+ invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
+ invalid_params_if(I2C, i2c_reserved_addr(addr));
+ // Synopsys hw accepts start/stop flags alongside data items in the same
+ // FIFO word, so no 0 byte transfers.
+ invalid_params_if(I2C, len == 0);
+ invalid_params_if(I2C, ((int)len) < 0);
+
+ i2c->hw->enable = 0;
+ i2c->hw->tar = addr;
+ i2c->hw->enable = 1;
+
+ bool abort = false;
+ bool timeout = false;
+
+ uint32_t abort_reason = 0;
+ int byte_ctr;
+
+ int ilen = (int)len;
+ for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) {
+ bool first = byte_ctr == 0;
+ bool last = byte_ctr == ilen - 1;
+
+ i2c->hw->data_cmd =
+ bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
+ bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
+ *src++;
+
+ // Wait until the transmission of the address/data from the internal
+ // shift register has completed. For this to function correctly, the
+ // TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag
+ // was set in i2c_init.
+ do {
+ if (timeout_check) {
+ timeout = timeout_check(ts);
+ abort |= timeout;
+ }
+ tight_loop_contents();
+ } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS));
+
+ // If there was a timeout, don't attempt to do anything else.
+ if (!timeout) {
+ abort_reason = i2c->hw->tx_abrt_source;
+ if (abort_reason) {
+ // Note clearing the abort flag also clears the reason, and
+ // this instance of flag is clear-on-read! Note also the
+ // IC_CLR_TX_ABRT register always reads as 0.
+ i2c->hw->clr_tx_abrt;
+ abort = true;
+ }
+
+ if (abort || (last && !nostop)) {
+ // If the transaction was aborted or if it completed
+ // successfully wait until the STOP condition has occured.
+
+ // TODO Could there be an abort while waiting for the STOP
+ // condition here? If so, additional code would be needed here
+ // to take care of the abort.
+ do {
+ if (timeout_check) {
+ timeout = timeout_check(ts);
+ abort |= timeout;
+ }
+ tight_loop_contents();
+ } while (!timeout && !(i2c->hw->raw_intr_stat & I2C_IC_RAW_INTR_STAT_STOP_DET_BITS));
+
+ // If there was a timeout, don't attempt to do anything else.
+ if (!timeout) {
+ i2c->hw->clr_stop_det;
+ }
+ }
+ }
+
+ // Note the hardware issues a STOP automatically on an abort condition.
+ // Note also the hardware clears RX FIFO as well as TX on abort,
+ // because we set hwparam IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT to 0.
+ if (abort)
+ break;
+ }
+
+ int rval;
+
+ // A lot of things could have just happened due to the ingenious and
+ // creative design of I2C. Try to figure things out.
+ if (abort) {
+ if (timeout)
+ rval = PICO_ERROR_TIMEOUT;
+ else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) {
+ // No reported errors - seems to happen if there is nothing connected to the bus.
+ // Address byte not acknowledged
+ rval = PICO_ERROR_GENERIC;
+ } else if (abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS) {
+ // Address acknowledged, some data not acknowledged
+ rval = byte_ctr;
+ } else {
+ //panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason);
+ rval = PICO_ERROR_GENERIC;
+ }
+ } else {
+ rval = byte_ctr;
+ }
+
+ // nostop means we are now at the end of a *message* but not the end of a *transfer*
+ i2c->restart_on_next = nostop;
+ return rval;
+}
+
+int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop) {
+ return i2c_write_blocking_internal(i2c, addr, src, len, nostop, NULL, NULL);
+}
+
+int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop,
+ absolute_time_t until) {
+ timeout_state_t ts;
+ return i2c_write_blocking_internal(i2c, addr, src, len, nostop, init_single_timeout_until(&ts, until), &ts);
+}
+
+int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop,
+ uint timeout_per_char_us) {
+ timeout_state_t ts;
+ return i2c_write_blocking_internal(i2c, addr, src, len, nostop,
+ init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts);
+}
+
+static int i2c_read_blocking_internal(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop,
+ check_timeout_fn timeout_check, timeout_state_t *ts) {
+ invalid_params_if(I2C, addr >= 0x80); // 7-bit addresses
+ invalid_params_if(I2C, i2c_reserved_addr(addr));
+ invalid_params_if(I2C, len == 0);
+ invalid_params_if(I2C, ((int)len) < 0);
+
+ i2c->hw->enable = 0;
+ i2c->hw->tar = addr;
+ i2c->hw->enable = 1;
+
+ bool abort = false;
+ bool timeout = false;
+ uint32_t abort_reason;
+ int byte_ctr;
+ int ilen = (int)len;
+ for (byte_ctr = 0; byte_ctr < ilen; ++byte_ctr) {
+ bool first = byte_ctr == 0;
+ bool last = byte_ctr == ilen - 1;
+ while (!i2c_get_write_available(i2c))
+ tight_loop_contents();
+
+ i2c->hw->data_cmd =
+ bool_to_bit(first && i2c->restart_on_next) << I2C_IC_DATA_CMD_RESTART_LSB |
+ bool_to_bit(last && !nostop) << I2C_IC_DATA_CMD_STOP_LSB |
+ I2C_IC_DATA_CMD_CMD_BITS; // -> 1 for read
+
+ do {
+ abort_reason = i2c->hw->tx_abrt_source;
+ abort = (bool) i2c->hw->clr_tx_abrt;
+ if (timeout_check) {
+ timeout = timeout_check(ts);
+ abort |= timeout;
+ }
+ } while (!abort && !i2c_get_read_available(i2c));
+
+ if (abort)
+ break;
+
+ *dst++ = (uint8_t) i2c->hw->data_cmd;
+ }
+
+ int rval;
+
+ if (abort) {
+ if (timeout)
+ rval = PICO_ERROR_TIMEOUT;
+ else if (!abort_reason || abort_reason & I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS) {
+ // No reported errors - seems to happen if there is nothing connected to the bus.
+ // Address byte not acknowledged
+ rval = PICO_ERROR_GENERIC;
+ } else {
+// panic("Unknown abort from I2C instance @%08x: %08x\n", (uint32_t) i2c->hw, abort_reason);
+ rval = PICO_ERROR_GENERIC;
+ }
+ } else {
+ rval = byte_ctr;
+ }
+
+ i2c->restart_on_next = nostop;
+ return rval;
+}
+
+int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop) {
+ return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, NULL, NULL);
+}
+
+int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until) {
+ timeout_state_t ts;
+ return i2c_read_blocking_internal(i2c, addr, dst, len, nostop, init_single_timeout_until(&ts, until), &ts);
+}
+
+int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop,
+ uint timeout_per_char_us) {
+ timeout_state_t ts;
+ return i2c_read_blocking_internal(i2c, addr, dst, len, nostop,
+ init_per_iteration_timeout_us(&ts, timeout_per_char_us), &ts);
+}
diff --git a/arkanoid/pico/hardware/i2c.h b/arkanoid/pico/hardware/i2c.h
new file mode 100644
index 0000000..a8c0cbd
--- /dev/null
+++ b/arkanoid/pico/hardware/i2c.h
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_I2C_H
+#define _HARDWARE_I2C_H
+
+#include "../pico.h"
+#include "../time.h"
+#include "structs/i2c.h"
+#include "regs/dreq.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_I2C, Enable/disable assertions in the I2C module, type=bool, default=0, group=hardware_i2c
+#ifndef PARAM_ASSERTIONS_ENABLED_I2C
+#define PARAM_ASSERTIONS_ENABLED_I2C 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file i2c.h
+ * \defgroup hardware_i2c hardware_i2c
+ *
+ * I2C Controller API
+ *
+ * The I2C bus is a two-wire serial interface, consisting of a serial data line SDA and a serial clock SCL. These wires carry
+ * information between the devices connected to the bus. Each device is recognized by a unique 7-bit address and can operate as
+ * either a “transmitter” or “receiver”, depending on the function of the device. Devices can also be considered as masters or
+ * slaves when performing data transfers. A master is a device that initiates a data transfer on the bus and generates the
+ * clock signals to permit that transfer. The first byte in the data transfer always contains the 7-bit address and
+ * a read/write bit in the LSB position. This API takes care of toggling the read/write bit. After this, any device addressed
+ * is considered a slave.
+ *
+ * This API allows the controller to be set up as a master or a slave using the \ref i2c_set_slave_mode function.
+ *
+ * The external pins of each controller are connected to GPIO pins as defined in the GPIO muxing table in the datasheet. The muxing options
+ * give some IO flexibility, but each controller external pin should be connected to only one GPIO.
+ *
+ * Note that the controller does NOT support High speed mode or Ultra-fast speed mode, the fastest operation being fast mode plus
+ * at up to 1000Kb/s.
+ *
+ * See the datasheet for more information on the I2C controller and its usage.
+ *
+ * \subsection i2c_example Example
+ * \addtogroup hardware_i2c
+ * \include bus_scan.c
+ */
+
+typedef struct i2c_inst i2c_inst_t;
+
+// PICO_CONFIG: PICO_DEFAULT_I2C, Define the default I2C for a board, min=0, max=1, group=hardware_i2c
+// PICO_CONFIG: PICO_DEFAULT_I2C_SDA_PIN, Define the default I2C SDA pin, min=0, max=29, group=hardware_i2c
+// PICO_CONFIG: PICO_DEFAULT_I2C_SCL_PIN, Define the default I2C SCL pin, min=0, max=29, group=hardware_i2c
+
+/** The I2C identifiers for use in I2C functions.
+ *
+ * e.g. i2c_init(i2c0, 48000)
+ *
+ * \ingroup hardware_i2c
+ * @{
+ */
+extern i2c_inst_t i2c0_inst;
+extern i2c_inst_t i2c1_inst;
+
+#define i2c0 (&i2c0_inst) ///< Identifier for I2C HW Block 0
+#define i2c1 (&i2c1_inst) ///< Identifier for I2C HW Block 1
+
+#if !defined(PICO_DEFAULT_I2C_INSTANCE) && defined(PICO_DEFAULT_I2C)
+#define PICO_DEFAULT_I2C_INSTANCE (__CONCAT(i2c,PICO_DEFAULT_I2C))
+#endif
+
+#ifdef PICO_DEFAULT_I2C_INSTANCE
+#define i2c_default PICO_DEFAULT_I2C_INSTANCE
+#endif
+
+/** @} */
+
+// ----------------------------------------------------------------------------
+// Setup
+
+/*! \brief Initialise the I2C HW block
+ * \ingroup hardware_i2c
+ *
+ * Put the I2C hardware into a known state, and enable it. Must be called
+ * before other functions. By default, the I2C is configured to operate as a
+ * master.
+ *
+ * The I2C bus frequency is set as close as possible to requested, and
+ * the return actual rate set is returned
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000)
+ * \return Actual set baudrate
+ */
+uint i2c_init(i2c_inst_t *i2c, uint baudrate);
+
+/*! \brief Disable the I2C HW block
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ *
+ * Disable the I2C again if it is no longer used. Must be reinitialised before
+ * being used again.
+ */
+void i2c_deinit(i2c_inst_t *i2c);
+
+/*! \brief Set I2C baudrate
+ * \ingroup hardware_i2c
+ *
+ * Set I2C bus frequency as close as possible to requested, and return actual
+ * rate set.
+ * Baudrate may not be as exactly requested due to clocking limitations.
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param baudrate Baudrate in Hz (e.g. 100kHz is 100000)
+ * \return Actual set baudrate
+ */
+uint i2c_set_baudrate(i2c_inst_t *i2c, uint baudrate);
+
+/*! \brief Set I2C port to slave mode
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param slave true to use slave mode, false to use master mode
+ * \param addr If \p slave is true, set the slave address to this value
+ */
+void i2c_set_slave_mode(i2c_inst_t *i2c, bool slave, uint8_t addr);
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+struct i2c_inst {
+ i2c_hw_t *hw;
+ bool restart_on_next;
+};
+
+/*! \brief Convert I2C instance to hardware instance number
+ * \ingroup hardware_i2c
+ *
+ * \param i2c I2C instance
+ * \return Number of I2C, 0 or 1.
+ */
+static inline uint i2c_hw_index(i2c_inst_t *i2c) {
+ invalid_params_if(I2C, i2c != i2c0 && i2c != i2c1);
+ return i2c == i2c1 ? 1 : 0;
+}
+
+static inline i2c_hw_t *i2c_get_hw(i2c_inst_t *i2c) {
+ i2c_hw_index(i2c); // check it is a hw i2c
+ return i2c->hw;
+}
+
+/*! \brief Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached.
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to write to
+ * \param src Pointer to data to send
+ * \param len Length of data in bytes to send
+ * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ * and the next transfer will begin with a Restart rather than a Start.
+ * \param until The absolute time that the block will wait until the entire transaction is complete. Note, an individual timeout of
+ * this value divided by the length of data is applied for each byte transfer, so if the first or subsequent
+ * bytes fails to transfer within that sub timeout, the function will return with an error.
+ *
+ * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+int i2c_write_blocking_until(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, absolute_time_t until);
+
+/*! \brief Attempt to read specified number of bytes from address, blocking until the specified absolute time is reached.
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to read from
+ * \param dst Pointer to buffer to receive data
+ * \param len Length of data in bytes to receive
+ * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ * and the next transfer will begin with a Restart rather than a Start.
+ * \param until The absolute time that the block will wait until the entire transaction is complete.
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+int i2c_read_blocking_until(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, absolute_time_t until);
+
+/*! \brief Attempt to write specified number of bytes to address, with timeout
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to write to
+ * \param src Pointer to data to send
+ * \param len Length of data in bytes to send
+ * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ * and the next transfer will begin with a Restart rather than a Start.
+ * \param timeout_us The time that the function will wait for the entire transaction to complete. Note, an individual timeout of
+ * this value divided by the length of data is applied for each byte transfer, so if the first or subsequent
+ * bytes fails to transfer within that sub timeout, the function will return with an error.
+ *
+ * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+static inline int i2c_write_timeout_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_us) {
+ absolute_time_t t = make_timeout_time_us(timeout_us);
+ return i2c_write_blocking_until(i2c, addr, src, len, nostop, t);
+}
+
+int i2c_write_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop, uint timeout_per_char_us);
+
+/*! \brief Attempt to read specified number of bytes from address, with timeout
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to read from
+ * \param dst Pointer to buffer to receive data
+ * \param len Length of data in bytes to receive
+ * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ * and the next transfer will begin with a Restart rather than a Start.
+ * \param timeout_us The time that the function will wait for the entire transaction to complete
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged, no device present, or PICO_ERROR_TIMEOUT if a timeout occurred.
+ */
+static inline int i2c_read_timeout_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_us) {
+ absolute_time_t t = make_timeout_time_us(timeout_us);
+ return i2c_read_blocking_until(i2c, addr, dst, len, nostop, t);
+}
+
+int i2c_read_timeout_per_char_us(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop, uint timeout_per_char_us);
+
+/*! \brief Attempt to write specified number of bytes to address, blocking
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to write to
+ * \param src Pointer to data to send
+ * \param len Length of data in bytes to send
+ * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ * and the next transfer will begin with a Restart rather than a Start.
+ * \return Number of bytes written, or PICO_ERROR_GENERIC if address not acknowledged, no device present.
+ */
+int i2c_write_blocking(i2c_inst_t *i2c, uint8_t addr, const uint8_t *src, size_t len, bool nostop);
+
+/*! \brief Attempt to read specified number of bytes from address, blocking
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param addr 7-bit address of device to read from
+ * \param dst Pointer to buffer to receive data
+ * \param len Length of data in bytes to receive
+ * \param nostop If true, master retains control of the bus at the end of the transfer (no Stop is issued),
+ * and the next transfer will begin with a Restart rather than a Start.
+ * \return Number of bytes read, or PICO_ERROR_GENERIC if address not acknowledged or no device present.
+ */
+int i2c_read_blocking(i2c_inst_t *i2c, uint8_t addr, uint8_t *dst, size_t len, bool nostop);
+
+
+/*! \brief Determine non-blocking write space available
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \return 0 if no space is available in the I2C to write more data. If return is nonzero, at
+ * least that many bytes can be written without blocking.
+ */
+static inline size_t i2c_get_write_available(i2c_inst_t *i2c) {
+ const size_t IC_TX_BUFFER_DEPTH = 16;
+ return IC_TX_BUFFER_DEPTH - i2c_get_hw(i2c)->txflr;
+}
+
+/*! \brief Determine number of bytes received
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \return 0 if no data available, if return is nonzero at
+ * least that many bytes can be read without blocking.
+ */
+static inline size_t i2c_get_read_available(i2c_inst_t *i2c) {
+ return i2c_get_hw(i2c)->rxflr;
+}
+
+/*! \brief Write direct to TX FIFO
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param src Data to send
+ * \param len Number of bytes to send
+ *
+ * Writes directly to the I2C TX FIFO which is mainly useful for
+ * slave-mode operation.
+ */
+static inline void i2c_write_raw_blocking(i2c_inst_t *i2c, const uint8_t *src, size_t len) {
+ for (size_t i = 0; i < len; ++i) {
+ // TODO NACK or STOP on end?
+ while (!i2c_get_write_available(i2c))
+ tight_loop_contents();
+ i2c_get_hw(i2c)->data_cmd = *src++;
+ }
+}
+
+/*! \brief Read direct from RX FIFO
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param dst Buffer to accept data
+ * \param len Number of bytes to read
+ *
+ * Reads directly from the I2C RX FIFO which is mainly useful for
+ * slave-mode operation.
+ */
+static inline void i2c_read_raw_blocking(i2c_inst_t *i2c, uint8_t *dst, size_t len) {
+ for (size_t i = 0; i < len; ++i) {
+ while (!i2c_get_read_available(i2c))
+ tight_loop_contents();
+ *dst++ = (uint8_t)i2c_get_hw(i2c)->data_cmd;
+ }
+}
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular I2C instance
+ * \ingroup hardware_i2c
+ *
+ * \param i2c Either \ref i2c0 or \ref i2c1
+ * \param is_tx true for sending data to the I2C instance, false for receiving data from the I2C instance
+ */
+static inline uint i2c_get_dreq(i2c_inst_t *i2c, bool is_tx) {
+ static_assert(DREQ_I2C0_RX == DREQ_I2C0_TX + 1, "");
+ static_assert(DREQ_I2C1_RX == DREQ_I2C1_TX + 1, "");
+ static_assert(DREQ_I2C1_TX == DREQ_I2C0_TX + 2, "");
+ return DREQ_I2C0_TX + i2c_hw_index(i2c) * 2 + !is_tx;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/interp.c b/arkanoid/pico/hardware/interp.c
new file mode 100644
index 0000000..f270f03
--- /dev/null
+++ b/arkanoid/pico/hardware/interp.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "interp.h"
+#include "structs/sio.h"
+#include "claim.h"
+
+check_hw_size(interp_hw_t, SIO_INTERP1_ACCUM0_OFFSET - SIO_INTERP0_ACCUM0_OFFSET);
+
+check_hw_layout(sio_hw_t, interp, SIO_INTERP0_ACCUM0_OFFSET);
+
+static_assert(NUM_DMA_CHANNELS <= 16, "");
+
+static uint8_t _claimed;
+
+static inline uint interp_lane_bit(interp_hw_t * interp, uint lane) {
+ return (interp_index(interp) << 1u) | lane;
+}
+
+void interp_claim_lane(interp_hw_t *interp, uint lane) {
+ valid_params_if(INTERP, lane < 2);
+ hw_claim_or_assert((uint8_t *) &_claimed, interp_lane_bit(interp, lane), "Lane is already claimed");
+}
+
+void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask) {
+ valid_params_if(INTERP, lane_mask && lane_mask <= 0x3);
+ if (lane_mask & 1u) interp_claim_lane(interp, 0);
+ if (lane_mask & 2u) interp_claim_lane(interp, 1);
+}
+
+void interp_unclaim_lane(interp_hw_t *interp, uint lane) {
+ valid_params_if(INTERP, lane < 2);
+ hw_claim_clear((uint8_t *) &_claimed, interp_lane_bit(interp, lane));
+}
+
+bool interp_lane_is_claimed(interp_hw_t *interp, uint lane) {
+ valid_params_if(INTERP, lane < 2);
+ return hw_is_claimed((uint8_t *) &_claimed, interp_lane_bit(interp, lane));
+}
+
+void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask) {
+ valid_params_if(INTERP, lane_mask <= 0x3);
+ if (lane_mask & 1u) interp_unclaim_lane(interp, 0);
+ if (lane_mask & 2u) interp_unclaim_lane(interp, 1);
+}
+
+void interp_save(interp_hw_t *interp, interp_hw_save_t *saver) {
+ saver->accum[0] = interp->accum[0];
+ saver->accum[1] = interp->accum[1];
+ saver->base[0] = interp->base[0];
+ saver->base[1] = interp->base[1];
+ saver->base[2] = interp->base[2];
+ saver->ctrl[0] = interp->ctrl[0];
+ saver->ctrl[1] = interp->ctrl[1];
+}
+
+void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver) {
+ interp->accum[0] = saver->accum[0];
+ interp->accum[1] = saver->accum[1];
+ interp->base[0] = saver->base[0];
+ interp->base[1] = saver->base[1];
+ interp->base[2] = saver->base[2];
+ interp->ctrl[0] = saver->ctrl[0];
+ interp->ctrl[1] = saver->ctrl[1];
+}
diff --git a/arkanoid/pico/hardware/interp.h b/arkanoid/pico/hardware/interp.h
new file mode 100644
index 0000000..935e771
--- /dev/null
+++ b/arkanoid/pico/hardware/interp.h
@@ -0,0 +1,458 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_INTERP_H
+#define _HARDWARE_INTERP_H
+
+#include "../pico.h"
+#include "structs/interp.h"
+#include "regs/sio.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_INTERP, Enable/disable assertions in the interpolation module, type=bool, default=0, group=hardware_interp
+#ifndef PARAM_ASSERTIONS_ENABLED_INTERP
+#define PARAM_ASSERTIONS_ENABLED_INTERP 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file interp.h
+ * \defgroup hardware_interp hardware_interp
+ *
+ * Hardware Interpolator API
+ *
+ * Each core is equipped with two interpolators (INTERP0 and INTERP1) which can be used to accelerate
+ * tasks by combining certain pre-configured simple operations into a single processor cycle. Intended
+ * for cases where the pre-configured operation is repeated a large number of times, this results in
+ * code which uses both fewer CPU cycles and fewer CPU registers in the time critical sections of the
+ * code.
+ *
+ * The interpolators are used heavily to accelerate audio operations within the SDK, but their
+ * flexible configuration make it possible to optimise many other tasks such as quantization and
+ * dithering, table lookup address generation, affine texture mapping, decompression and linear feedback.
+ *
+ * Please refer to the RP2040 datasheet for more information on the HW interpolators and how they work.
+ */
+
+#define interp0 interp0_hw
+#define interp1 interp1_hw
+
+/** \brief Interpolator configuration
+ * \defgroup interp_config interp_config
+ * \ingroup hardware_interp
+ *
+ * Each interpolator needs to be configured, these functions provide handy helpers to set up configuration
+ * structures.
+ *
+ */
+
+typedef struct {
+ uint32_t ctrl;
+} interp_config;
+
+static inline uint interp_index(interp_hw_t *interp) {
+ valid_params_if(INTERP, interp == interp0 || interp == interp1);
+ return interp == interp1 ? 1 : 0;
+}
+
+/*! \brief Claim the interpolator lane specified
+ * \ingroup hardware_interp
+ *
+ * Use this function to claim exclusive access to the specified interpolator lane.
+ *
+ * This function will panic if the lane is already claimed.
+ *
+ * \param interp Interpolator on which to claim a lane. interp0 or interp1
+ * \param lane The lane number, 0 or 1.
+ */
+void interp_claim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_claim interp_claim_lane
+
+/*! \brief Claim the interpolator lanes specified in the mask
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator on which to claim lanes. interp0 or interp1
+ * \param lane_mask Bit pattern of lanes to claim (only bits 0 and 1 are valid)
+ */
+void interp_claim_lane_mask(interp_hw_t *interp, uint lane_mask);
+
+/*! \brief Release a previously claimed interpolator lane
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator on which to release a lane. interp0 or interp1
+ * \param lane The lane number, 0 or 1
+ */
+void interp_unclaim_lane(interp_hw_t *interp, uint lane);
+// The above really should be called this for consistency
+#define interp_lane_unclaim interp_unclaim_lane
+
+/*! \brief Determine if an interpolator lane is claimed
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator whose lane to check
+ * \param lane The lane number, 0 or 1
+ * \return true if claimed, false otherwise
+ * \see interp_claim_lane
+ * \see interp_claim_lane_mask
+ */
+bool interp_lane_is_claimed(interp_hw_t *interp, uint lane);
+
+/*! \brief Release previously claimed interpolator lanes \see interp_claim_lane_mask
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator on which to release lanes. interp0 or interp1
+ * \param lane_mask Bit pattern of lanes to unclaim (only bits 0 and 1 are valid)
+ */
+void interp_unclaim_lane_mask(interp_hw_t *interp, uint lane_mask);
+
+/*! \brief Set the interpolator shift value
+ * \ingroup interp_config
+ *
+ * Sets the number of bits the accumulator is shifted before masking, on each iteration.
+ *
+ * \param c Pointer to an interpolator config
+ * \param shift Number of bits
+ */
+static inline void interp_config_set_shift(interp_config *c, uint shift) {
+ valid_params_if(INTERP, shift < 32);
+ c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SHIFT_BITS) |
+ ((shift << SIO_INTERP0_CTRL_LANE0_SHIFT_LSB) & SIO_INTERP0_CTRL_LANE0_SHIFT_BITS);
+}
+
+/*! \brief Set the interpolator mask range
+ * \ingroup interp_config
+ *
+ * Sets the range of bits (least to most) that are allowed to pass through the interpolator
+ *
+ * \param c Pointer to interpolation config
+ * \param mask_lsb The least significant bit allowed to pass
+ * \param mask_msb The most significant bit allowed to pass
+ */
+static inline void interp_config_set_mask(interp_config *c, uint mask_lsb, uint mask_msb) {
+ valid_params_if(INTERP, mask_msb < 32);
+ valid_params_if(INTERP, mask_lsb <= mask_msb);
+ c->ctrl = (c->ctrl & ~(SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS | SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS)) |
+ ((mask_lsb << SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS) |
+ ((mask_msb << SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB) & SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS);
+}
+
+/*! \brief Enable cross input
+ * \ingroup interp_config
+ *
+ * Allows feeding of the accumulator content from the other lane back in to this lanes shift+mask hardware.
+ * This will take effect even if the interp_config_set_add_raw option is set as the cross input mux is before the
+ * shift+mask bypass
+ *
+ * \param c Pointer to interpolation config
+ * \param cross_input If true, enable the cross input.
+ */
+static inline void interp_config_set_cross_input(interp_config *c, bool cross_input) {
+ c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS) |
+ (cross_input ? SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS : 0);
+}
+
+/*! \brief Enable cross results
+ * \ingroup interp_config
+ *
+ * Allows feeding of the other lane’s result into this lane’s accumulator on a POP operation.
+ *
+ * \param c Pointer to interpolation config
+ * \param cross_result If true, enables the cross result
+ */
+static inline void interp_config_set_cross_result(interp_config *c, bool cross_result) {
+ c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS) |
+ (cross_result ? SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS : 0);
+}
+
+/*! \brief Set sign extension
+ * \ingroup interp_config
+ *
+ * Enables signed mode, where the shifted and masked accumulator value is sign-extended to 32 bits
+ * before adding to BASE1, and LANE1 PEEK/POP results appear extended to 32 bits when read by processor.
+ *
+ * \param c Pointer to interpolation config
+ * \param _signed If true, enables sign extension
+ */
+static inline void interp_config_set_signed(interp_config *c, bool _signed) {
+ c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_SIGNED_BITS) |
+ (_signed ? SIO_INTERP0_CTRL_LANE0_SIGNED_BITS : 0);
+}
+
+/*! \brief Set raw add option
+ * \ingroup interp_config
+ *
+ * When enabled, mask + shift is bypassed for LANE0 result. This does not affect the FULL result.
+ *
+ * \param c Pointer to interpolation config
+ * \param add_raw If true, enable raw add option.
+ */
+static inline void interp_config_set_add_raw(interp_config *c, bool add_raw) {
+ c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS) |
+ (add_raw ? SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS : 0);
+}
+
+/*! \brief Set blend mode
+ * \ingroup interp_config
+ *
+ * If enabled, LANE1 result is a linear interpolation between BASE0 and BASE1, controlled
+ * by the 8 LSBs of lane 1 shift and mask value (a fractional number between 0 and 255/256ths)
+ *
+ * LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
+ *
+ * FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)
+ *
+ * LANE1 SIGNED flag controls whether the interpolation is signed or unsig
+ *
+ * \param c Pointer to interpolation config
+ * \param blend Set true to enable blend mode.
+*/
+static inline void interp_config_set_blend(interp_config *c, bool blend) {
+ c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_BLEND_BITS) |
+ (blend ? SIO_INTERP0_CTRL_LANE0_BLEND_BITS : 0);
+}
+
+/*! \brief Set interpolator clamp mode (Interpolator 1 only)
+ * \ingroup interp_config
+ *
+ * Only present on INTERP1 on each core. If CLAMP mode is enabled:
+ * - LANE0 result is a shifted and masked ACCUM0, clamped by a lower bound of BASE0 and an upper bound of BASE1.
+ * - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
+ *
+ * \param c Pointer to interpolation config
+ * \param clamp Set true to enable clamp mode
+ */
+static inline void interp_config_set_clamp(interp_config *c, bool clamp) {
+ c->ctrl = (c->ctrl & ~SIO_INTERP1_CTRL_LANE0_CLAMP_BITS) |
+ (clamp ? SIO_INTERP1_CTRL_LANE0_CLAMP_BITS : 0);
+}
+
+/*! \brief Set interpolator Force bits
+ * \ingroup interp_config
+ *
+ * ORed into bits 29:28 of the lane result presented to the processor on the bus.
+ *
+ * No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
+ * of pointers into flash or SRAM
+ *
+ * \param c Pointer to interpolation config
+ * \param bits Sets the force bits to that specified. Range 0-3 (two bits)
+ */
+static inline void interp_config_set_force_bits(interp_config *c, uint bits) {
+ invalid_params_if(INTERP, bits > 3);
+ // note cannot use hw_set_bits on SIO
+ c->ctrl = (c->ctrl & ~SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS) |
+ (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
+}
+
+/*! \brief Get a default configuration
+ * \ingroup interp_config
+ *
+ * \return A default interpolation configuration
+ */
+static inline interp_config interp_default_config(void) {
+ interp_config c = {0};
+ // Just pass through everything
+ interp_config_set_mask(&c, 0, 31);
+ return c;
+}
+
+/*! \brief Send configuration to a lane
+ * \ingroup interp_config
+ *
+ * If an invalid configuration is specified (ie a lane specific item is set on wrong lane),
+ * depending on setup this function can panic.
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane to set
+ * \param config Pointer to interpolation config
+ */
+
+static inline void interp_set_config(interp_hw_t *interp, uint lane, interp_config *config) {
+ invalid_params_if(INTERP, lane > 1);
+ invalid_params_if(INTERP, config->ctrl & SIO_INTERP1_CTRL_LANE0_CLAMP_BITS &&
+ (!interp_index(interp) || lane)); // only interp1 lane 0 has clamp bit
+ invalid_params_if(INTERP, config->ctrl & SIO_INTERP0_CTRL_LANE0_BLEND_BITS &&
+ (interp_index(interp) || lane)); // only interp0 lane 0 has blend bit
+ interp->ctrl[lane] = config->ctrl;
+}
+
+/*! \brief Directly set the force bits on a specified lane
+ * \ingroup hardware_interp
+ *
+ * These bits are ORed into bits 29:28 of the lane result presented to the processor on the bus.
+ * There is no effect on the internal 32-bit datapath.
+ *
+ * Useful for using a lane to generate sequence of pointers into flash or SRAM, saving a subsequent
+ * OR or add operation.
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane to set
+ * \param bits The bits to set (bits 0 and 1, value range 0-3)
+ */
+static inline void interp_set_force_bits(interp_hw_t *interp, uint lane, uint bits) {
+ // note cannot use hw_set_bits on SIO
+ interp->ctrl[lane] |= (bits << SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB);
+}
+
+typedef struct {
+ uint32_t accum[2];
+ uint32_t base[3];
+ uint32_t ctrl[2];
+} interp_hw_save_t;
+
+/*! \brief Save the specified interpolator state
+ * \ingroup hardware_interp
+ *
+ * Can be used to save state if you need an interpolator for another purpose, state
+ * can then be recovered afterwards and continue from that point
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param saver Pointer to the save structure to fill in
+ */
+void interp_save(interp_hw_t *interp, interp_hw_save_t *saver);
+
+/*! \brief Restore an interpolator state
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param saver Pointer to save structure to reapply to the specified interpolator
+ */
+void interp_restore(interp_hw_t *interp, interp_hw_save_t *saver);
+
+/*! \brief Sets the interpolator base register by lane
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1 or 2
+ * \param val The value to apply to the register
+ */
+static inline void interp_set_base(interp_hw_t *interp, uint lane, uint32_t val) {
+ interp->base[lane] = val;
+}
+
+/*! \brief Gets the content of interpolator base register by lane
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1 or 2
+ * \return The current content of the lane base register
+ */
+static inline uint32_t interp_get_base(interp_hw_t *interp, uint lane) {
+ return interp->base[lane];
+}
+
+/*! \brief Sets the interpolator base registers simultaneously
+ * \ingroup hardware_interp
+ *
+ * The lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
+ * Each half is sign-extended to 32 bits if that lane’s SIGNED flag is set.
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param val The value to apply to the register
+ */
+static inline void interp_set_base_both(interp_hw_t *interp, uint32_t val) {
+ interp->base01 = val;
+}
+
+
+/*! \brief Sets the interpolator accumulator register by lane
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \param val The value to apply to the register
+ */
+static inline void interp_set_accumulator(interp_hw_t *interp, uint lane, uint32_t val) {
+ interp->accum[lane] = val;
+}
+
+/*! \brief Gets the content of the interpolator accumulator register by lane
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The current content of the register
+ */
+static inline uint32_t interp_get_accumulator(interp_hw_t *interp, uint lane) {
+ return interp->accum[lane];
+}
+
+/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The content of the lane result register
+ */
+static inline uint32_t interp_pop_lane_result(interp_hw_t *interp, uint lane) {
+ return interp->pop[lane];
+}
+
+/*! \brief Read lane result
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The content of the lane result register
+ */
+static inline uint32_t interp_peek_lane_result(interp_hw_t *interp, uint lane) {
+ return interp->peek[lane];
+}
+
+/*! \brief Read lane result, and write lane results to both accumulators to update the interpolator
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \return The content of the FULL register
+ */
+static inline uint32_t interp_pop_full_result(interp_hw_t *interp) {
+ return interp->pop[2];
+}
+
+/*! \brief Read lane result
+ * \ingroup hardware_interp
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \return The content of the FULL register
+ */
+static inline uint32_t interp_peek_full_result(interp_hw_t *interp) {
+ return interp->peek[2];
+}
+
+/*! \brief Add to accumulator
+ * \ingroup hardware_interp
+ *
+ * Atomically add the specified value to the accumulator on the specified lane
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \param val Value to add
+ * \return The content of the FULL register
+ */
+static inline void interp_add_accumulater(interp_hw_t *interp, uint lane, uint32_t val) {
+ interp->add_raw[lane] = val;
+}
+
+/*! \brief Get raw lane value
+ * \ingroup hardware_interp
+ *
+ * Returns the raw shift and mask value from the specified lane, BASE0 is NOT added
+ *
+ * \param interp Interpolator instance, interp0 or interp1.
+ * \param lane The lane number, 0 or 1
+ * \return The raw shift/mask value
+ */
+static inline uint32_t interp_get_raw(interp_hw_t *interp, uint lane) {
+ return interp->add_raw[lane];
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/irq.c b/arkanoid/pico/hardware/irq.c
new file mode 100644
index 0000000..7d0b262
--- /dev/null
+++ b/arkanoid/pico/hardware/irq.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "irq.h"
+#include "regs/m0plus.h"
+#include "platform_defs.h"
+#include "structs/scb.h"
+
+#include "../mutex.h"
+#include "../junk/assert.h"
+
+extern void __unhandled_user_irq(void);
+
+static inline irq_handler_t *get_vtable(void) {
+ return (irq_handler_t *) scb_hw->vtor;
+}
+
+static inline void *add_thumb_bit(void *addr) {
+ return (void *) (((uintptr_t) addr) | 0x1);
+}
+
+static inline void *remove_thumb_bit(void *addr) {
+ return (void *) (((uintptr_t) addr) & (uint)~0x1);
+}
+
+static void set_raw_irq_handler_and_unlock(uint num, irq_handler_t handler, uint32_t save) {
+ // update vtable (vtable_handler may be same or updated depending on cases, but we do it anyway for compactness)
+ get_vtable()[16 + num] = handler;
+ __dmb();
+ spin_unlock(spin_lock_instance(PICO_SPINLOCK_ID_IRQ), save);
+}
+
+void irq_set_enabled(uint num, bool enabled) {
+ check_irq_param(num);
+ irq_set_mask_enabled(1u << num, enabled);
+}
+
+bool irq_is_enabled(uint num) {
+ check_irq_param(num);
+ return 0 != ((1u << num) & *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)));
+}
+
+void irq_set_mask_enabled(uint32_t mask, bool enabled) {
+ if (enabled) {
+ // Clear pending before enable
+ // (if IRQ is actually asserted, it will immediately re-pend)
+ *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = mask;
+ *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISER_OFFSET)) = mask;
+ } else {
+ *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ICER_OFFSET)) = mask;
+ }
+}
+
+void irq_set_pending(uint num) {
+ check_irq_param(num);
+ *((io_rw_32 *) (PPB_BASE + M0PLUS_NVIC_ISPR_OFFSET)) = 1u << num;
+}
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+// limited by 8 bit relative links (and reality)
+static_assert(PICO_MAX_SHARED_IRQ_HANDLERS >= 1 && PICO_MAX_SHARED_IRQ_HANDLERS < 0x7f, "");
+
+// note these are not real functions, they are code fragments (i.e. don't call them)
+extern void irq_handler_chain_first_slot(void);
+extern void irq_handler_chain_remove_tail(void);
+
+extern struct irq_handler_chain_slot {
+ // first 3 half words are executable code (raw vtable handler points to one slot, and inst3 will jump to next
+ // in chain (or end of chain handler)
+ uint16_t inst1;
+ uint16_t inst2;
+ uint16_t inst3;
+ union {
+ // when a handler is removed while executing, it needs an extra instruction, which overwrites
+ // the link and the priority; this is ok because no one else is modifying the chain, as
+ // the chain is effectively core local, and the user code which might still need this link
+ // disable the IRQ in question before updating, which means we aren't executing!
+ struct {
+ int8_t link;
+ uint8_t priority;
+ };
+ uint16_t inst4;
+ };
+ irq_handler_t handler;
+} irq_handler_chain_slots[PICO_MAX_SHARED_IRQ_HANDLERS];
+
+static int8_t irq_hander_chain_free_slot_head;
+
+static inline bool is_shared_irq_raw_handler(irq_handler_t raw_handler) {
+ return (uintptr_t)raw_handler - (uintptr_t)irq_handler_chain_slots < sizeof(irq_handler_chain_slots);
+}
+#else
+#define is_shared_irq_raw_handler(h) false
+#endif
+
+irq_handler_t irq_get_vtable_handler(uint num) {
+ check_irq_param(num);
+ return get_vtable()[16 + num];
+}
+
+void irq_set_exclusive_handler(uint num, irq_handler_t handler) {
+ check_irq_param(num);
+#if !PICO_NO_RAM_VECTOR_TABLE
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+ uint32_t save = spin_lock_blocking(lock);
+ __unused irq_handler_t current = irq_get_vtable_handler(num);
+ hard_assert(current == __unhandled_user_irq || current == handler);
+ set_raw_irq_handler_and_unlock(num, handler, save);
+#else
+ panic_unsupported();
+#endif
+}
+
+irq_handler_t irq_get_exclusive_handler(uint num) {
+ check_irq_param(num);
+#if !PICO_NO_RAM_VECTOR_TABLE
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+ uint32_t save = spin_lock_blocking(lock);
+ irq_handler_t current = irq_get_vtable_handler(num);
+ spin_unlock(lock, save);
+ if (current == __unhandled_user_irq || is_shared_irq_raw_handler(current)) {
+ return NULL;
+ }
+ return current;
+#else
+ panic_unsupported();
+#endif
+}
+
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+static uint16_t make_branch(uint16_t *from, void *to) {
+ uint32_t ui_from = (uint32_t)from;
+ uint32_t ui_to = (uint32_t)to;
+ uint32_t delta = (ui_to - ui_from - 4) / 2;
+ assert(!(delta >> 11u));
+ return (uint16_t)(0xe000 | (delta & 0x7ff));
+}
+
+static void insert_branch_and_link(uint16_t *from, void *to) {
+ uint32_t ui_from = (uint32_t)from;
+ uint32_t ui_to = (uint32_t)to;
+ uint32_t delta = (ui_to - ui_from - 4) / 2;
+ assert(!(delta >> 11u));
+ from[0] = (uint16_t)(0xf000 | ((delta >> 11u) & 0x7ffu));
+ from[1] = (uint16_t)(0xf800 | (delta & 0x7ffu));
+}
+
+static inline void *resolve_branch(uint16_t *inst) {
+ assert(0x1c == (*inst)>>11u);
+ int32_t i_addr = (*inst) << 21u;
+ i_addr /= (int32_t)(1u<<21u);
+ return inst + 2 + i_addr;
+}
+
+// GCC produces horrible code for subtraction of pointers here, and it was bugging me
+static inline int8_t slot_diff(struct irq_handler_chain_slot *to, struct irq_handler_chain_slot *from) {
+ static_assert(sizeof(struct irq_handler_chain_slot) == 12, "");
+ int32_t result = 0xaaaa;
+ // return (to - from);
+ // note this implementation has limited range, but is fine for plenty more than -128->127 result
+ asm (".syntax unified\n"
+ "subs %1, %2\n"
+ "adcs %1, %1\n" // * 2 (and + 1 if negative for rounding)
+ "muls %0, %1\n"
+ "lsrs %0, 20\n"
+ : "+l" (result), "+l" (to)
+ : "l" (from)
+ :
+ );
+ return (int8_t)result;
+}
+
+static inline int8_t get_slot_index(struct irq_handler_chain_slot *slot) {
+ return slot_diff(slot, irq_handler_chain_slots);
+}
+#endif
+
+void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority) {
+ check_irq_param(num);
+#if PICO_NO_RAM_VECTOR_TABLE
+ panic_unsupported()
+#elif PICO_DISABLE_SHARED_IRQ_HANDLERS
+ irq_set_exclusive_handler(num, handler);
+#else
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+ uint32_t save = spin_lock_blocking(lock);
+ hard_assert(irq_hander_chain_free_slot_head >= 0); // we must have a slot
+ struct irq_handler_chain_slot *slot = &irq_handler_chain_slots[irq_hander_chain_free_slot_head];
+ int8_t slot_index = irq_hander_chain_free_slot_head;
+ irq_hander_chain_free_slot_head = slot->link;
+ irq_handler_t vtable_handler = get_vtable()[16 + num];
+ if (!is_shared_irq_raw_handler(vtable_handler)) {
+ // start new chain
+ hard_assert(vtable_handler == __unhandled_user_irq);
+ struct irq_handler_chain_slot slot_data = {
+ .inst1 = 0xa100, // add r1, pc, #0
+ .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot
+ .inst3 = 0xbd00, // pop {pc}
+ .link = -1,
+ .priority = order_priority,
+ .handler = handler
+ };
+ *slot = slot_data;
+ vtable_handler = (irq_handler_t)add_thumb_bit(slot);
+ } else {
+ assert(!((((uintptr_t)vtable_handler) - ((uintptr_t)irq_handler_chain_slots) - 1)%sizeof(struct irq_handler_chain_slot)));
+ struct irq_handler_chain_slot *prev_slot = NULL;
+ struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler);
+ struct irq_handler_chain_slot *cur_slot = existing_vtable_slot;
+ while (cur_slot->priority > order_priority) {
+ prev_slot = cur_slot;
+ if (cur_slot->link < 0) break;
+ cur_slot = &irq_handler_chain_slots[cur_slot->link];
+ }
+ if (prev_slot) {
+ // insert into chain
+ struct irq_handler_chain_slot slot_data = {
+ .inst1 = 0x4801, // ldr r0, [pc, #4]
+ .inst2 = 0x4780, // blx r0
+ .inst3 = prev_slot->link >= 0 ?
+ make_branch(&slot->inst3, resolve_branch(&prev_slot->inst3)) : // b next_slot
+ 0xbd00, // pop {pc}
+ .link = prev_slot->link,
+ .priority = order_priority,
+ .handler = handler
+ };
+ // update code and data links
+ prev_slot->inst3 = make_branch(&prev_slot->inst3, slot),
+ prev_slot->link = slot_index;
+ *slot = slot_data;
+ } else {
+ // update with new chain head
+ struct irq_handler_chain_slot slot_data = {
+ .inst1 = 0xa100, // add r1, pc, #0
+ .inst2 = make_branch(&slot->inst2, irq_handler_chain_first_slot), // b irq_handler_chain_first_slot
+ .inst3 = make_branch(&slot->inst3, existing_vtable_slot), // b existing_slot
+ .link = get_slot_index(existing_vtable_slot),
+ .priority = order_priority,
+ .handler = handler
+ };
+ *slot = slot_data;
+ // fixup previous head slot
+ existing_vtable_slot->inst1 = 0x4801; // ldr r0, [pc, #4]
+ existing_vtable_slot->inst2 = 0x4780; // blx r0
+ vtable_handler = (irq_handler_t)add_thumb_bit(slot);
+ }
+ }
+ set_raw_irq_handler_and_unlock(num, vtable_handler, save);
+#endif
+}
+
+void irq_remove_handler(uint num, irq_handler_t handler) {
+#if !PICO_NO_RAM_VECTOR_TABLE
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+ uint32_t save = spin_lock_blocking(lock);
+ irq_handler_t vtable_handler = get_vtable()[16 + num];
+ if (vtable_handler != __unhandled_user_irq && vtable_handler != handler) {
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+ if (is_shared_irq_raw_handler(vtable_handler)) {
+ // This is a bit tricky, as an executing IRQ handler doesn't take a lock.
+
+ // First thing to do is to disable the IRQ in question; that takes care of calls from user code.
+ // Note that a irq handler chain is local to our own core, so we don't need to worry about the other core
+ bool was_enabled = irq_is_enabled(num);
+ irq_set_enabled(num, false);
+ __dmb();
+
+ // It is possible we are being called while an IRQ for this chain is already in progress.
+ // The issue we have here is that we must not free a slot that is currently being executed, because
+ // inst3 is still to be executed, and inst3 might get overwritten if the slot is re-used.
+
+ // By disallowing other exceptions from removing an IRQ handler (which seems fair)
+ // we now only have to worry about removing a slot from a chain that is currently executing.
+
+ // Note we expect that the slot we are deleting is the one that is executing.
+ // In particular, bad things happen if the caller were to delete the handler in the chain
+ // before it. This is not an allowed use case though, and I can't imagine anyone wanting to in practice.
+ // Sadly this is not something we can detect.
+
+ uint exception = __get_current_exception();
+ hard_assert(!exception || exception == num + 16);
+
+ struct irq_handler_chain_slot *prev_slot = NULL;
+ struct irq_handler_chain_slot *existing_vtable_slot = remove_thumb_bit(vtable_handler);
+ struct irq_handler_chain_slot *to_free_slot = existing_vtable_slot;
+ int8_t to_free_slot_index = get_slot_index(to_free_slot);
+ while (to_free_slot->handler != handler) {
+ prev_slot = to_free_slot;
+ if (to_free_slot->link < 0) break;
+ to_free_slot = &irq_handler_chain_slots[to_free_slot->link];
+ }
+ if (to_free_slot->handler == handler) {
+ int8_t next_slot_index = to_free_slot->link;
+ if (next_slot_index >= 0) {
+ // There is another slot in the chain, so copy that over us, so that our inst3 points at something valid
+ // Note this only matters in the exception case anyway, and it that case, we will skip the next handler,
+ // however in that case it's IRQ cause should immediately cause re-entry of the IRQ and the only side
+ // effect will be that there was potentially brief out of priority order execution of the handlers
+ struct irq_handler_chain_slot *next_slot = &irq_handler_chain_slots[next_slot_index];
+ to_free_slot->handler = next_slot->handler;
+ to_free_slot->priority = next_slot->priority;
+ to_free_slot->link = next_slot->link;
+ to_free_slot->inst3 = next_slot->link >= 0 ?
+ make_branch(&to_free_slot->inst3, resolve_branch(&next_slot->inst3)) : // b mext_>slot->next_slot
+ 0xbd00; // pop {pc}
+
+ // add old next slot back to free list
+ next_slot->link = irq_hander_chain_free_slot_head;
+ irq_hander_chain_free_slot_head = next_slot_index;
+ } else {
+ // Slot being removed is at the end of the chain
+ if (!exception) {
+ // case when we're not in exception, we physically unlink now
+ if (prev_slot) {
+ // chain is not empty
+ prev_slot->link = -1;
+ prev_slot->inst3 = 0xbd00; // pop {pc}
+ } else {
+ // chain is not empty
+ vtable_handler = __unhandled_user_irq;
+ }
+ // add slot back to free list
+ to_free_slot->link = irq_hander_chain_free_slot_head;
+ irq_hander_chain_free_slot_head = to_free_slot_index;
+ } else {
+ // since we are the last slot we know that our inst3 hasn't executed yet, so we change
+ // it to bl to irq_handler_chain_remove_tail which will remove the slot.
+ // NOTE THAT THIS TRASHES PRIORITY AND LINK SINCE THIS IS A 4 BYTE INSTRUCTION
+ // BUT THEY ARE NOT NEEDED NOW
+ insert_branch_and_link(&to_free_slot->inst3, irq_handler_chain_remove_tail);
+ }
+ }
+ } else {
+ assert(false); // not found
+ }
+ irq_set_enabled(num, was_enabled);
+ }
+#else
+ assert(false); // not found
+#endif
+ } else {
+ vtable_handler = __unhandled_user_irq;
+ }
+ set_raw_irq_handler_and_unlock(num, vtable_handler, save);
+#else
+ panic_unsupported();
+#endif
+}
+
+void irq_set_priority(uint num, uint8_t hardware_priority) {
+ check_irq_param(num);
+
+ // note that only 32 bit writes are supported
+ io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
+ *p = (*p & ~(0xffu << (8 * (num & 3u)))) | (((uint32_t) hardware_priority) << (8 * (num & 3u)));
+}
+
+uint irq_get_priority(uint num) {
+ check_irq_param(num);
+
+ // note that only 32 bit reads are supported
+ io_rw_32 *p = (io_rw_32 *)((PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET) + (num & ~3u));
+ return (uint8_t)(*p >> (8 * (num & 3u)));
+}
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+// used by irq_handler_chain.S to remove the last link in a handler chain after it executes
+// note this must be called only with the last slot in a chain (and during the exception)
+void irq_add_tail_to_free_list(struct irq_handler_chain_slot *slot) {
+ irq_handler_t slot_handler = (irq_handler_t) add_thumb_bit(slot);
+ assert(is_shared_irq_raw_handler(slot_handler));
+
+ uint exception = __get_current_exception();
+ assert(exception);
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_IRQ);
+ uint32_t save = spin_lock_blocking(lock);
+ int8_t slot_index = get_slot_index(slot);
+ if (slot_handler == get_vtable()[exception]) {
+ get_vtable()[exception] = __unhandled_user_irq;
+ } else {
+ bool __unused found = false;
+ // need to find who points at the slot and update it
+ for(uint i=0;i<count_of(irq_handler_chain_slots);i++) {
+ if (irq_handler_chain_slots[i].link == slot_index) {
+ irq_handler_chain_slots[i].link = -1;
+ irq_handler_chain_slots[i].inst3 = 0xbd00; // pop {pc}
+ found = true;
+ break;
+ }
+ }
+ assert(found);
+ }
+ // add slot to free list
+ slot->link = irq_hander_chain_free_slot_head;
+ irq_hander_chain_free_slot_head = slot_index;
+ spin_unlock(lock, save);
+}
+#endif
+
+void irq_init_priorities() {
+#if PICO_DEFAULT_IRQ_PRIORITY != 0
+ static_assert(!(NUM_IRQS & 3), "");
+ uint32_t prio4 = (PICO_DEFAULT_IRQ_PRIORITY & 0xff) * 0x1010101u;
+ io_rw_32 * p = (io_rw_32 *)(PPB_BASE + M0PLUS_NVIC_IPR0_OFFSET);
+ for (uint i = 0; i < NUM_IRQS / 4; i++) {
+ *p++ = prio4;
+ }
+#endif
+}
diff --git a/arkanoid/pico/hardware/irq.h b/arkanoid/pico/hardware/irq.h
new file mode 100644
index 0000000..7665b8d
--- /dev/null
+++ b/arkanoid/pico/hardware/irq.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_IRQ_H_
+#define _HARDWARE_IRQ_H_
+
+// These two config items are also used by assembler, so keeping separate
+// PICO_CONFIG: PICO_MAX_SHARED_IRQ_HANDLERS, Maximum number of shared IRQ handlers, default=4, advanced=true, group=hardware_irq
+#ifndef PICO_MAX_SHARED_IRQ_HANDLERS
+#define PICO_MAX_SHARED_IRQ_HANDLERS 4u
+#endif
+
+// PICO_CONFIG: PICO_DISABLE_SHARED_IRQ_HANDLERS, Disable shared IRQ handlers, type=bool, default=0, group=hardware_irq
+#ifndef PICO_DISABLE_SHARED_IRQ_HANDLERS
+#define PICO_DISABLE_SHARED_IRQ_HANDLERS 0
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include "../pico.h"
+#include "address_mapped.h"
+#include "regs/intctrl.h"
+#include "regs/m0plus.h"
+
+/** \file irq.h
+ * \defgroup hardware_irq hardware_irq
+ *
+ * Hardware interrupt handling
+ *
+ * The RP2040 uses the standard ARM nested vectored interrupt controller (NVIC).
+ *
+ * Interrupts are identified by a number from 0 to 31.
+ *
+ * On the RP2040, only the lower 26 IRQ signals are connected on the NVIC; IRQs 26 to 31 are tied to zero (never firing).
+ *
+ * There is one NVIC per core, and each core's NVIC has the same hardware interrupt lines routed to it, with the exception of the IO interrupts
+ * where there is one IO interrupt per bank, per core. These are completely independent, so, for example, processor 0 can be
+ * interrupted by GPIO 0 in bank 0, and processor 1 by GPIO 1 in the same bank.
+ *
+ * \note That all IRQ APIs affect the executing core only (i.e. the core calling the function).
+ *
+ * \note You should not enable the same (shared) IRQ number on both cores, as this will lead to race conditions
+ * or starvation of one of the cores. Additionally, don't forget that disabling interrupts on one core does not disable interrupts
+ * on the other core.
+ *
+ * There are three different ways to set handlers for an IRQ:
+ * - Calling irq_add_shared_handler() at runtime to add a handler for a multiplexed interrupt (e.g. GPIO bank) on the current core. Each handler, should check and clear the relevant hardware interrupt source
+ * - Calling irq_set_exclusive_handler() at runtime to install a single handler for the interrupt on the current core
+ * - Defining the interrupt handler explicitly in your application (e.g. by defining void `isr_dma_0` will make that function the handler for the DMA_IRQ_0 on core 0, and
+ * you will not be able to change it using the above APIs at runtime). Using this method can cause link conflicts at runtime, and offers no runtime performance benefit (i.e, it should not generally be used).
+ *
+ * \note If an IRQ is enabled and fires with no handler installed, a breakpoint will be hit and the IRQ number will
+ * be in register r0.
+ *
+ * \section interrupt_nums Interrupt Numbers
+ *
+ * Interrupts are numbered as follows, a set of defines is available (intctrl.h) with these names to avoid using the numbers directly.
+ *
+ * IRQ | Interrupt Source
+ * ----|-----------------
+ * 0 | TIMER_IRQ_0
+ * 1 | TIMER_IRQ_1
+ * 2 | TIMER_IRQ_2
+ * 3 | TIMER_IRQ_3
+ * 4 | PWM_IRQ_WRAP
+ * 5 | USBCTRL_IRQ
+ * 6 | XIP_IRQ
+ * 7 | PIO0_IRQ_0
+ * 8 | PIO0_IRQ_1
+ * 9 | PIO1_IRQ_0
+ * 10 | PIO1_IRQ_1
+ * 11 | DMA_IRQ_0
+ * 12 | DMA_IRQ_1
+ * 13 | IO_IRQ_BANK0
+ * 14 | IO_IRQ_QSPI
+ * 15 | SIO_IRQ_PROC0
+ * 16 | SIO_IRQ_PROC1
+ * 17 | CLOCKS_IRQ
+ * 18 | SPI0_IRQ
+ * 19 | SPI1_IRQ
+ * 20 | UART0_IRQ
+ * 21 | UART1_IRQ
+ * 22 | ADC0_IRQ_FIFO
+ * 23 | I2C0_IRQ
+ * 24 | I2C1_IRQ
+ * 25 | RTC_IRQ
+ *
+ */
+
+// PICO_CONFIG: PICO_DEFAULT_IRQ_PRIORITY, Define the default IRQ priority, default=0x80, group=hardware_irq
+#ifndef PICO_DEFAULT_IRQ_PRIORITY
+#define PICO_DEFAULT_IRQ_PRIORITY 0x80
+#endif
+
+#define PICO_LOWEST_IRQ_PRIORITY 0xff
+#define PICO_HIGHEST_IRQ_PRIORITY 0x00
+
+// PICO_CONFIG: PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY, Set default shared IRQ order priority, default=0x80, group=hardware_irq
+#ifndef PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY
+#define PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY 0x80
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_IRQ, Enable/disable assertions in the IRQ module, type=bool, default=0, group=hardware_irq
+#ifndef PARAM_ASSERTIONS_ENABLED_IRQ
+#define PARAM_ASSERTIONS_ENABLED_IRQ 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Interrupt handler function type
+ * \ingroup hardware_irq
+ *
+ * All interrupts handlers should be of this type, and follow normal ARM EABI register saving conventions
+ */
+typedef void (*irq_handler_t)(void);
+
+static inline void check_irq_param(__unused uint num) {
+ invalid_params_if(IRQ, num >= NUM_IRQS);
+}
+
+/*! \brief Set specified interrupt's priority
+ * \ingroup hardware_irq
+ *
+ * \param num Interrupt number
+ * \param hardware_priority Priority to set.
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
+ */
+void irq_set_priority(uint num, uint8_t hardware_priority);
+
+/*! \brief Get specified interrupt's priority
+ * \ingroup hardware_irq
+ *
+ * Numerically-lower values indicate a higher priority. Hardware priorities
+ * range from 0 (highest priority) to 255 (lowest priority) though only the
+ * top 2 bits are significant on ARM Cortex-M0+. To make it easier to specify
+ * higher or lower priorities than the default, all IRQ priorities are
+ * initialized to PICO_DEFAULT_IRQ_PRIORITY by the SDK runtime at startup.
+ * PICO_DEFAULT_IRQ_PRIORITY defaults to 0x80
+ *
+ * \param num Interrupt number
+ * \return the IRQ priority
+ */
+uint irq_get_priority(uint num);
+
+/*! \brief Enable or disable a specific interrupt on the executing core
+ * \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param enabled true to enable the interrupt, false to disable
+ */
+void irq_set_enabled(uint num, bool enabled);
+
+/*! \brief Determine if a specific interrupt is enabled on the executing core
+ * \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return true if the interrupt is enabled
+ */
+bool irq_is_enabled(uint num);
+
+/*! \brief Enable/disable multiple interrupts on the executing core
+ * \ingroup hardware_irq
+ *
+ * \param mask 32-bit mask with one bits set for the interrupts to enable/disable
+ * \param enabled true to enable the interrupts, false to disable them.
+ */
+void irq_set_mask_enabled(uint32_t mask, bool enabled);
+
+/*! \brief Set an exclusive interrupt handler for an interrupt on the executing core.
+ * \ingroup hardware_irq
+ *
+ * Use this method to set a handler for single IRQ source interrupts, or when
+ * your code, use case or performance requirements dictate that there should
+ * no other handlers for the interrupt.
+ *
+ * This method will assert if there is already any sort of interrupt handler installed
+ * for the specified irq number.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param handler The handler to set. See \ref irq_handler_t
+ * \see irq_add_shared_handler()
+ */
+void irq_set_exclusive_handler(uint num, irq_handler_t handler);
+
+/*! \brief Get the exclusive interrupt handler for an interrupt on the executing core.
+ * \ingroup hardware_irq
+ *
+ * This method will return an exclusive IRQ handler set on this core
+ * by irq_set_exclusive_handler if there is one.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \see irq_set_exclusive_handler()
+ * \return handler The handler if an exclusive handler is set for the IRQ,
+ * NULL if no handler is set or shared/shareable handlers are installed
+ */
+irq_handler_t irq_get_exclusive_handler(uint num);
+
+/*! \brief Add a shared interrupt handler for an interrupt on the executing core
+ * \ingroup hardware_irq
+ *
+ * Use this method to add a handler on an irq number shared between multiple distinct hardware sources (e.g. GPIO, DMA or PIO IRQs).
+ * Handlers added by this method will all be called in sequence from highest order_priority to lowest. The
+ * irq_set_exclusive_handler() method should be used instead if you know there will or should only ever be one handler for the interrupt.
+ *
+ * This method will assert if there is an exclusive interrupt handler set for this irq number on this core, or if
+ * the (total across all IRQs on both cores) maximum (configurable via PICO_MAX_SHARED_IRQ_HANDLERS) number of shared handlers
+ * would be exceeded.
+ *
+ * \param num Interrupt number
+ * \param handler The handler to set. See \ref irq_handler_t
+ * \param order_priority The order priority controls the order that handlers for the same IRQ number on the core are called.
+ * The shared irq handlers for an interrupt are all called when an IRQ fires, however the order of the calls is based
+ * on the order_priority (higher priorities are called first, identical priorities are called in undefined order). A good
+ * rule of thumb is to use PICO_SHARED_IRQ_HANDLER_DEFAULT_ORDER_PRIORITY if you don't much care, as it is in the middle of
+ * the priority range by default.
+ *
+ * \see irq_set_exclusive_handler()
+ */
+void irq_add_shared_handler(uint num, irq_handler_t handler, uint8_t order_priority);
+
+/*! \brief Remove a specific interrupt handler for the given irq number on the executing core
+ * \ingroup hardware_irq
+ *
+ * This method may be used to remove an irq set via either irq_set_exclusive_handler() or
+ * irq_add_shared_handler(), and will assert if the handler is not currently installed for the given
+ * IRQ number
+ *
+ * \note This method may *only* be called from user (non IRQ code) or from within the handler
+ * itself (i.e. an IRQ handler may remove itself as part of handling the IRQ). Attempts to call
+ * from another IRQ will cause an assertion.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \param handler The handler to removed.
+ * \see irq_set_exclusive_handler()
+ * \see irq_add_shared_handler()
+ */
+void irq_remove_handler(uint num, irq_handler_t handler);
+
+/*! \brief Get the current IRQ handler for the specified IRQ from the currently installed hardware vector table (VTOR)
+ * of the execution core
+ * \ingroup hardware_irq
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ * \return the address stored in the VTABLE for the given irq number
+ */
+irq_handler_t irq_get_vtable_handler(uint num);
+
+/*! \brief Clear a specific interrupt on the executing core
+ * \ingroup hardware_irq
+ *
+ * \param int_num Interrupt number \ref interrupt_nums
+ */
+static inline void irq_clear(uint int_num) {
+ *((volatile uint32_t *) (PPB_BASE + M0PLUS_NVIC_ICPR_OFFSET)) = (1u << ((uint32_t) (int_num & 0x1F)));
+}
+
+/*! \brief Force an interrupt to be pending on the executing core
+ * \ingroup hardware_irq
+ *
+ * This should generally not be used for IRQs connected to hardware.
+ *
+ * \param num Interrupt number \ref interrupt_nums
+ */
+void irq_set_pending(uint num);
+
+
+/*! \brief Perform IRQ priority initialization for the current core
+ *
+ * \note This is an internal method and user should generally not call it.
+ */
+void irq_init_priorities(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+#endif
diff --git a/arkanoid/pico/hardware/irq_handler_chain.S b/arkanoid/pico/hardware/irq_handler_chain.S
new file mode 100644
index 0000000..2b5c3af
--- /dev/null
+++ b/arkanoid/pico/hardware/irq_handler_chain.S
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../pico.h"
+#include "irq.h"
+
+#if !PICO_DISABLE_SHARED_IRQ_HANDLERS
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+
+.data
+.align 2
+
+.global irq_handler_chain_slots
+
+.global irq_handler_chain_first_slot
+.global irq_handler_chain_remove_tail
+
+//
+// These Slots make up the code and structure of the handler chains; the only external information are the VTABLE entries
+// (obviously one set per core) and a free list head. Each individual handler chain starts with the VTABLE entry I
+// pointing at the address of slot S (with thumb bit set). Thus each slot which is part of a chain is executble.
+//
+// The execution jumps (via branch instruction) from one slot to the other, then jumps to the end of chain handler.
+// The entirety of the state needed to traverse the chain is contained within the slots of the chain, which is why
+// a VTABLE entry is all that is needed per chain (rather than requiring a separarte set of head pointers)
+//
+
+irq_handler_chain_slots:
+.set next_slot_number, 1
+.rept PICO_MAX_SHARED_IRQ_HANDLERS
+ // a slot is executable and is always 3 instructions long.
+ .hword 0 // inst1 (either: ldr r0, [pc, #4] or for the FIRST slot : add r1, pc, #0 )
+ .hword 0 // inst2 ( blx r0 b irq_handler_chain_first_slot )
+
+ .hword 0 // inst3 (either: b next_slot or for the LAST pop {pc} )
+
+ // next is a single byte index of next slot in chain (or -1 to end)
+.if next_slot_number == PICO_MAX_SHARED_IRQ_HANDLERS
+ .byte 0xff
+.else
+ .byte next_slot_number
+.endif
+ // next is the 8 bit unsigned priority
+ .byte 0x00
+1:
+ // and finally the handler function pointer
+ .word 0x00000000
+ .set next_slot_number, next_slot_number + 1
+.endr
+
+irq_handler_chain_first_slot:
+ push {lr}
+ ldr r0, [r1, #4]
+ adds r1, #1
+ mov lr, r1
+ bx r0
+irq_handler_chain_remove_tail:
+ mov r0, lr
+ subs r0, #9
+ ldr r1, =irq_add_tail_to_free_list
+ blx r1
+ pop {pc}
+
+
+#endif
diff --git a/arkanoid/pico/hardware/pio.c b/arkanoid/pico/hardware/pio.c
new file mode 100644
index 0000000..17d4d58
--- /dev/null
+++ b/arkanoid/pico/hardware/pio.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "claim.h"
+#include "pio.h"
+#include "pio_instructions.h"
+
+// sanity check
+check_hw_layout(pio_hw_t, sm[0].clkdiv, PIO_SM0_CLKDIV_OFFSET);
+check_hw_layout(pio_hw_t, sm[1].clkdiv, PIO_SM1_CLKDIV_OFFSET);
+check_hw_layout(pio_hw_t, instr_mem[0], PIO_INSTR_MEM0_OFFSET);
+check_hw_layout(pio_hw_t, inte0, PIO_IRQ0_INTE_OFFSET);
+check_hw_layout(pio_hw_t, txf[1], PIO_TXF1_OFFSET);
+check_hw_layout(pio_hw_t, rxf[3], PIO_RXF3_OFFSET);
+check_hw_layout(pio_hw_t, ints1, PIO_IRQ1_INTS_OFFSET);
+
+static_assert(NUM_PIO_STATE_MACHINES * NUM_PIOS <= 8, "");
+static uint8_t claimed;
+
+void pio_sm_claim(PIO pio, uint sm) {
+ check_sm_param(sm);
+ uint which = pio_get_index(pio);
+ if (which) {
+ hw_claim_or_assert(&claimed, NUM_PIO_STATE_MACHINES + sm, "PIO 1 SM (%d - 4) already claimed");
+ } else {
+ hw_claim_or_assert(&claimed, sm, "PIO 0 SM %d already claimed");
+ }
+}
+
+void pio_claim_sm_mask(PIO pio, uint sm_mask) {
+ for(uint i = 0; sm_mask; i++, sm_mask >>= 1u) {
+ if (sm_mask & 1u) pio_sm_claim(pio, i);
+ }
+}
+
+void pio_sm_unclaim(PIO pio, uint sm) {
+ check_sm_param(sm);
+ uint which = pio_get_index(pio);
+ hw_claim_clear(&claimed, which * NUM_PIO_STATE_MACHINES + sm);
+}
+
+int pio_claim_unused_sm(PIO pio, bool required) {
+ // PIO index is 0 or 1.
+ uint which = pio_get_index(pio);
+ uint base = which * NUM_PIO_STATE_MACHINES;
+ int index = hw_claim_unused_from_range((uint8_t*)&claimed, required, base,
+ base + NUM_PIO_STATE_MACHINES - 1, "No PIO state machines are available");
+ return index >= (int)base ? index - (int)base : -1;
+}
+
+bool pio_sm_is_claimed(PIO pio, uint sm) {
+ check_sm_param(sm);
+ uint which = pio_get_index(pio);
+ return hw_is_claimed(&claimed, which * NUM_PIO_STATE_MACHINES + sm);
+}
+
+static_assert(PIO_INSTRUCTION_COUNT <= 32, "");
+static uint32_t _used_instruction_space[2];
+
+static int _pio_find_offset_for_program(PIO pio, const pio_program_t *program) {
+ assert(program->length <= PIO_INSTRUCTION_COUNT);
+ uint32_t used_mask = _used_instruction_space[pio_get_index(pio)];
+ uint32_t program_mask = (1u << program->length) - 1;
+ if (program->origin >= 0) {
+ if (program->origin > 32 - program->length) return -1;
+ return used_mask & (program_mask << program->origin) ? -1 : program->origin;
+ } else {
+ // work down from the top always
+ for (int i = 32 - program->length; i >= 0; i--) {
+ if (!(used_mask & (program_mask << (uint) i))) {
+ return i;
+ }
+ }
+ return -1;
+ }
+}
+
+bool pio_can_add_program(PIO pio, const pio_program_t *program) {
+ uint32_t save = hw_claim_lock();
+ bool rc = -1 != _pio_find_offset_for_program(pio, program);
+ hw_claim_unlock(save);
+ return rc;
+}
+
+static bool _pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+ valid_params_if(PIO, offset < PIO_INSTRUCTION_COUNT);
+ valid_params_if(PIO, offset + program->length <= PIO_INSTRUCTION_COUNT);
+ if (program->origin >= 0 && (uint)program->origin != offset) return false;
+ uint32_t used_mask = _used_instruction_space[pio_get_index(pio)];
+ uint32_t program_mask = (1u << program->length) - 1;
+ return !(used_mask & (program_mask << offset));
+}
+
+bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+ uint32_t save = hw_claim_lock();
+ bool rc = _pio_can_add_program_at_offset(pio, program, offset);
+ hw_claim_unlock(save);
+ return rc;
+}
+
+static void _pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+ if (!_pio_can_add_program_at_offset(pio, program, offset)) {
+ panic("No program space");
+ }
+ for (uint i = 0; i < program->length; ++i) {
+ uint16_t instr = program->instructions[i];
+ pio->instr_mem[offset + i] = pio_instr_bits_jmp != _pio_major_instr_bits(instr) ? instr : instr + offset;
+ }
+ uint32_t program_mask = (1u << program->length) - 1;
+ _used_instruction_space[pio_get_index(pio)] |= program_mask << offset;
+}
+
+// these assert if unable
+uint pio_add_program(PIO pio, const pio_program_t *program) {
+ uint32_t save = hw_claim_lock();
+ int offset = _pio_find_offset_for_program(pio, program);
+ if (offset < 0) {
+ panic("No program space");
+ }
+ _pio_add_program_at_offset(pio, program, (uint)offset);
+ hw_claim_unlock(save);
+ return (uint)offset;
+}
+
+void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset) {
+ uint32_t save = hw_claim_lock();
+ _pio_add_program_at_offset(pio, program, offset);
+ hw_claim_unlock(save);
+}
+
+void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset) {
+ uint32_t program_mask = (1u << program->length) - 1;
+ program_mask <<= loaded_offset;
+ uint32_t save = hw_claim_lock();
+ assert(program_mask == (_used_instruction_space[pio_get_index(pio)] & program_mask));
+ _used_instruction_space[pio_get_index(pio)] &= ~program_mask;
+ hw_claim_unlock(save);
+}
+
+void pio_clear_instruction_memory(PIO pio) {
+ uint32_t save = hw_claim_lock();
+ _used_instruction_space[pio_get_index(pio)] = 0;
+ for(uint i=0;i<PIO_INSTRUCTION_COUNT;i++) {
+ pio->instr_mem[i] = pio_encode_jmp(i);
+ }
+ hw_claim_unlock(save);
+}
+
+// Set the value of all PIO pins. This is done by forcibly executing
+// instructions on a "victim" state machine, sm. Ideally you should choose one
+// which is not currently running a program. This is intended for one-time
+// setup of initial pin states.
+void pio_sm_set_pins(PIO pio, uint sm, uint32_t pins) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+ uint remaining = 32;
+ uint base = 0;
+ while (remaining) {
+ uint decrement = remaining > 5 ? 5 : remaining;
+ pio->sm[sm].pinctrl =
+ (decrement << PIO_SM0_PINCTRL_SET_COUNT_LSB) |
+ (base << PIO_SM0_PINCTRL_SET_BASE_LSB);
+ pio_sm_exec(pio, sm, pio_encode_set(pio_pins, pins & 0x1fu));
+ remaining -= decrement;
+ base += decrement;
+ pins >>= 5;
+ }
+ pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pinvals, uint32_t pin_mask) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+ while (pin_mask) {
+ uint base = (uint)__builtin_ctz(pin_mask);
+ pio->sm[sm].pinctrl =
+ (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) |
+ (base << PIO_SM0_PINCTRL_SET_BASE_LSB);
+ pio_sm_exec(pio, sm, pio_encode_set(pio_pins, (pinvals >> base) & 0x1u));
+ pin_mask &= pin_mask - 1;
+ }
+ pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pindirs, uint32_t pin_mask) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+ while (pin_mask) {
+ uint base = (uint)__builtin_ctz(pin_mask);
+ pio->sm[sm].pinctrl =
+ (1u << PIO_SM0_PINCTRL_SET_COUNT_LSB) |
+ (base << PIO_SM0_PINCTRL_SET_BASE_LSB);
+ pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, (pindirs >> base) & 0x1u));
+ pin_mask &= pin_mask - 1;
+ }
+ pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin, uint count, bool is_out) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ valid_params_if(PIO, pin < 32u);
+ uint32_t pinctrl_saved = pio->sm[sm].pinctrl;
+ uint pindir_val = is_out ? 0x1f : 0;
+ while (count > 5) {
+ pio->sm[sm].pinctrl = (5u << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB);
+ pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val));
+ count -= 5;
+ pin = (pin + 5) & 0x1f;
+ }
+ pio->sm[sm].pinctrl = (count << PIO_SM0_PINCTRL_SET_COUNT_LSB) | (pin << PIO_SM0_PINCTRL_SET_BASE_LSB);
+ pio_sm_exec(pio, sm, pio_encode_set(pio_pindirs, pindir_val));
+ pio->sm[sm].pinctrl = pinctrl_saved;
+}
+
+void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config) {
+ valid_params_if(PIO, initial_pc < PIO_INSTRUCTION_COUNT);
+ // Halt the machine, set some sensible defaults
+ pio_sm_set_enabled(pio, sm, false);
+
+ if (config) {
+ pio_sm_set_config(pio, sm, config);
+ } else {
+ pio_sm_config c = pio_get_default_sm_config();
+ pio_sm_set_config(pio, sm, &c);
+ }
+
+ pio_sm_clear_fifos(pio, sm);
+
+ // Clear FIFO debug flags
+ const uint32_t fdebug_sm_mask =
+ (1u << PIO_FDEBUG_TXOVER_LSB) |
+ (1u << PIO_FDEBUG_RXUNDER_LSB) |
+ (1u << PIO_FDEBUG_TXSTALL_LSB) |
+ (1u << PIO_FDEBUG_RXSTALL_LSB);
+ pio->fdebug = fdebug_sm_mask << sm;
+
+ // Finally, clear some internal SM state
+ pio_sm_restart(pio, sm);
+ pio_sm_clkdiv_restart(pio, sm);
+ pio_sm_exec(pio, sm, pio_encode_jmp(initial_pc));
+}
+
+void pio_sm_drain_tx_fifo(PIO pio, uint sm) {
+ uint instr = (pio->sm[sm].shiftctrl & PIO_SM0_SHIFTCTRL_AUTOPULL_BITS) ? pio_encode_out(pio_null, 32) :
+ pio_encode_pull(false, false);
+ while (!pio_sm_is_tx_fifo_empty(pio, sm)) {
+ pio_sm_exec(pio, sm, instr);
+ }
+}
diff --git a/arkanoid/pico/hardware/pio.h b/arkanoid/pico/hardware/pio.h
new file mode 100644
index 0000000..a629df8
--- /dev/null
+++ b/arkanoid/pico/hardware/pio.h
@@ -0,0 +1,1311 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PIO_H_
+#define _HARDWARE_PIO_H_
+
+#include "../pico.h"
+#include "address_mapped.h"
+#include "structs/pio.h"
+#include "gpio.h"
+#include "regs/dreq.h"
+#include "pio_instructions.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO, Enable/disable assertions in the PIO module, type=bool, default=0, group=hardware_pio
+#ifndef PARAM_ASSERTIONS_ENABLED_PIO
+#define PARAM_ASSERTIONS_ENABLED_PIO 0
+#endif
+
+/** \file pio.h
+ * \defgroup hardware_pio hardware_pio
+ *
+ * Programmable I/O (PIO) API
+ *
+ * A programmable input/output block (PIO) is a versatile hardware interface which
+ * can support a number of different IO standards. There are two PIO blocks in the RP2040.
+ *
+ * Each PIO is programmable in the same sense as a processor: the four state machines independently
+ * execute short, sequential programs, to manipulate GPIOs and transfer data. Unlike a general
+ * purpose processor, PIO state machines are highly specialised for IO, with a focus on determinism,
+ * precise timing, and close integration with fixed-function hardware. Each state machine is equipped
+ * with:
+ * * Two 32-bit shift registers – either direction, any shift count
+ * * Two 32-bit scratch registers
+ * * 4×32 bit bus FIFO in each direction (TX/RX), reconfigurable as 8×32 in a single direction
+ * * Fractional clock divider (16 integer, 8 fractional bits)
+ * * Flexible GPIO mapping
+ * * DMA interface, sustained throughput up to 1 word per clock from system DMA
+ * * IRQ flag set/clear/status
+ *
+ * Full details of the PIO can be found in the RP2040 datasheet.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+static_assert(PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB == PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB + 1, "");
+
+/** \brief FIFO join states
+ * \ingroup hardware_pio
+ */
+enum pio_fifo_join {
+ PIO_FIFO_JOIN_NONE = 0,
+ PIO_FIFO_JOIN_TX = 1,
+ PIO_FIFO_JOIN_RX = 2,
+};
+
+/** \brief MOV status types
+ * \ingroup hardware_pio
+ */
+enum pio_mov_status_type {
+ STATUS_TX_LESSTHAN = 0,
+ STATUS_RX_LESSTHAN = 1
+};
+
+typedef pio_hw_t *PIO;
+
+/** Identifier for the first (PIO 0) hardware PIO instance (for use in PIO functions).
+ *
+ * e.g. pio_gpio_init(pio0, 5)
+ *
+ * \ingroup hardware_pio
+ * @{
+ */
+#define pio0 pio0_hw
+/** @} */
+
+/** Identifier for the second (PIO 1) hardware PIO instance (for use in PIO functions).
+ *
+ * e.g. pio_gpio_init(pio1, 5)
+ *
+ * \ingroup hardware_pio
+ * @{
+ */
+#define pio1 pio1_hw
+/** @} */
+
+/** \brief PIO state machine configuration
+ * \defgroup sm_config sm_config
+ * \ingroup hardware_pio
+ *
+ * A PIO block needs to be configured, these functions provide helpers to set up configuration
+ * structures. See \ref pio_sm_set_config
+ *
+ */
+
+/** \brief PIO Configuration structure
+ * \ingroup sm_config
+ */
+typedef struct {
+ uint32_t clkdiv;
+ uint32_t execctrl;
+ uint32_t shiftctrl;
+ uint32_t pinctrl;
+} pio_sm_config;
+
+static inline void check_sm_param(__unused uint sm) {
+ valid_params_if(PIO, sm < NUM_PIO_STATE_MACHINES);
+}
+
+static inline void check_sm_mask(__unused uint mask) {
+ valid_params_if(PIO, mask < (1u << NUM_PIO_STATE_MACHINES));
+}
+
+
+static inline void check_pio_param(__unused PIO pio) {
+ valid_params_if(PIO, pio == pio0 || pio == pio1);
+}
+
+/*! \brief Set the 'out' pins in a state machine configuration
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'set' and 'sideset' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param out_base 0-31 First pin to set as output
+ * \param out_count 0-32 Number of pins to set.
+ */
+static inline void sm_config_set_out_pins(pio_sm_config *c, uint out_base, uint out_count) {
+ valid_params_if(PIO, out_base < 32);
+ valid_params_if(PIO, out_count <= 32);
+ c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) |
+ (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) |
+ (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
+}
+
+/*! \brief Set the 'set' pins in a state machine configuration
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'sideset' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param set_base 0-31 First pin to set as
+ * \param set_count 0-5 Number of pins to set.
+ */
+static inline void sm_config_set_set_pins(pio_sm_config *c, uint set_base, uint set_count) {
+ valid_params_if(PIO, set_base < 32);
+ valid_params_if(PIO, set_count <= 5);
+ c->pinctrl = (c->pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) |
+ (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) |
+ (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
+}
+
+/*! \brief Set the 'in' pins in a state machine configuration
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'out', ''set' and 'sideset' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param in_base 0-31 First pin to use as input
+ */
+static inline void sm_config_set_in_pins(pio_sm_config *c, uint in_base) {
+ valid_params_if(PIO, in_base < 32);
+ c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
+ (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB);
+}
+
+/*! \brief Set the 'sideset' pins in a state machine configuration
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'set' pins
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param sideset_base 0-31 base pin for 'side set'
+ */
+static inline void sm_config_set_sideset_pins(pio_sm_config *c, uint sideset_base) {
+ valid_params_if(PIO, sideset_base < 32);
+ c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
+ (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
+}
+
+/*! \brief Set the 'sideset' options in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param bit_count Number of bits to steal from delay field in the instruction for use of side set (max 5)
+ * \param optional True if the topmost side set bit is used as a flag for whether to apply side set on that instruction
+ * \param pindirs True if the side set affects pin directions rather than values
+ */
+static inline void sm_config_set_sideset(pio_sm_config *c, uint bit_count, bool optional, bool pindirs) {
+ valid_params_if(PIO, bit_count <= 5);
+ valid_params_if(PIO, !optional || bit_count >= 1);
+ c->pinctrl = (c->pinctrl & ~PIO_SM0_PINCTRL_SIDESET_COUNT_BITS) |
+ (bit_count << PIO_SM0_PINCTRL_SIDESET_COUNT_LSB);
+
+ c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_SIDE_EN_BITS | PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS)) |
+ (bool_to_bit(optional) << PIO_SM0_EXECCTRL_SIDE_EN_LSB) |
+ (bool_to_bit(pindirs) << PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB);
+}
+
+/*! \brief Set the state machine clock divider (from integer and fractional parts - 16:8) in a state machine configuration
+ * \ingroup sm_config
+ *
+ * The clock divider can slow the state machine's execution to some rate below
+ * the system clock frequency, by enabling the state machine on some cycles
+ * but not on others, in a regular pattern. This can be used to generate e.g.
+ * a given UART baud rate. See the datasheet for further detail.
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param div_int Integer part of the divisor
+ * \param div_frac Fractional part in 1/256ths
+ * \sa sm_config_set_clkdiv()
+ */
+static inline void sm_config_set_clkdiv_int_frac(pio_sm_config *c, uint16_t div_int, uint8_t div_frac) {
+ c->clkdiv =
+ (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
+ (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
+}
+
+static inline void pio_calculate_clkdiv_from_float(float div, uint16_t *div_int, uint8_t *div_frac) {
+ valid_params_if(PIO, div >= 1 && div <= 65536);
+ *div_int = (uint16_t)div;
+ if (*div_int == 0) {
+ *div_frac = 0;
+ } else {
+ *div_frac = (uint8_t)((div - (float)*div_int) * (1u << 8u));
+ }
+}
+
+/*! \brief Set the state machine clock divider (from a floating point value) in a state machine configuration
+ * \ingroup sm_config
+ *
+ * The clock divider slows the state machine's execution by masking the
+ * system clock on some cycles, in a repeating pattern, so that the state
+ * machine does not advance. Effectively this produces a slower clock for the
+ * state machine to run from, which can be used to generate e.g. a particular
+ * UART baud rate. See the datasheet for further detail.
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param div The fractional divisor to be set. 1 for full speed. An integer clock divisor of n
+ * will cause the state machine to run 1 cycle in every n.
+ * Note that for small n, the jitter introduced by a fractional divider (e.g. 2.5) may be unacceptable
+ * although it will depend on the use case.
+ */
+static inline void sm_config_set_clkdiv(pio_sm_config *c, float div) {
+ uint16_t div_int;
+ uint8_t div_frac;
+ pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
+ sm_config_set_clkdiv_int_frac(c, div_int, div_frac);
+}
+
+/*! \brief Set the wrap addresses in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param wrap_target the instruction memory address to wrap to
+ * \param wrap the instruction memory address after which to set the program counter to wrap_target
+ * if the instruction does not itself update the program_counter
+ */
+static inline void sm_config_set_wrap(pio_sm_config *c, uint wrap_target, uint wrap) {
+ valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT);
+ valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT);
+ c->execctrl = (c->execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
+ (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
+ (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
+}
+
+/*! \brief Set the 'jmp' pin in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param pin The raw GPIO pin number to use as the source for a `jmp pin` instruction
+ */
+static inline void sm_config_set_jmp_pin(pio_sm_config *c, uint pin) {
+ valid_params_if(PIO, pin < 32);
+ c->execctrl = (c->execctrl & ~PIO_SM0_EXECCTRL_JMP_PIN_BITS) |
+ (pin << PIO_SM0_EXECCTRL_JMP_PIN_LSB);
+}
+
+/*! \brief Setup 'in' shifting parameters in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param shift_right true to shift ISR to right, false to shift ISR to left
+ * \param autopush whether autopush is enabled
+ * \param push_threshold threshold in bits to shift in before auto/conditional re-pushing of the ISR
+ */
+static inline void sm_config_set_in_shift(pio_sm_config *c, bool shift_right, bool autopush, uint push_threshold) {
+ valid_params_if(PIO, push_threshold <= 32);
+ c->shiftctrl = (c->shiftctrl &
+ ~(PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS |
+ PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS |
+ PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS)) |
+ (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB) |
+ (bool_to_bit(autopush) << PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB) |
+ ((push_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB);
+}
+
+/*! \brief Setup 'out' shifting parameters in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param shift_right true to shift OSR to right, false to shift OSR to left
+ * \param autopull whether autopull is enabled
+ * \param pull_threshold threshold in bits to shift out before auto/conditional re-pulling of the OSR
+ */
+static inline void sm_config_set_out_shift(pio_sm_config *c, bool shift_right, bool autopull, uint pull_threshold) {
+ valid_params_if(PIO, pull_threshold <= 32);
+ c->shiftctrl = (c->shiftctrl &
+ ~(PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS |
+ PIO_SM0_SHIFTCTRL_AUTOPULL_BITS |
+ PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS)) |
+ (bool_to_bit(shift_right) << PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB) |
+ (bool_to_bit(autopull) << PIO_SM0_SHIFTCTRL_AUTOPULL_LSB) |
+ ((pull_threshold & 0x1fu) << PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB);
+}
+
+/*! \brief Setup the FIFO joining in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param join Specifies the join type. \see enum pio_fifo_join
+ */
+static inline void sm_config_set_fifo_join(pio_sm_config *c, enum pio_fifo_join join) {
+ valid_params_if(PIO, join == PIO_FIFO_JOIN_NONE || join == PIO_FIFO_JOIN_TX || join == PIO_FIFO_JOIN_RX);
+ c->shiftctrl = (c->shiftctrl & (uint)~(PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS | PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS)) |
+ (((uint)join) << PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB);
+}
+
+/*! \brief Set special 'out' operations in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param sticky to enable 'sticky' output (i.e. re-asserting most recent OUT/SET pin values on subsequent cycles)
+ * \param has_enable_pin true to enable auxiliary OUT enable pin
+ * \param enable_pin_index pin index for auxiliary OUT enable
+ */
+static inline void sm_config_set_out_special(pio_sm_config *c, bool sticky, bool has_enable_pin, uint enable_pin_index) {
+ c->execctrl = (c->execctrl &
+ (uint)~(PIO_SM0_EXECCTRL_OUT_STICKY_BITS | PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS |
+ PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS)) |
+ (bool_to_bit(sticky) << PIO_SM0_EXECCTRL_OUT_STICKY_LSB) |
+ (bool_to_bit(has_enable_pin) << PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB) |
+ ((enable_pin_index << PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB) & PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS);
+}
+
+/*! \brief Set source for 'mov status' in a state machine configuration
+ * \ingroup sm_config
+ *
+ * \param c Pointer to the configuration structure to modify
+ * \param status_sel the status operation selector. \see enum pio_mov_status_type
+ * \param status_n parameter for the mov status operation (currently a bit count)
+ */
+static inline void sm_config_set_mov_status(pio_sm_config *c, enum pio_mov_status_type status_sel, uint status_n) {
+ valid_params_if(PIO, status_sel == STATUS_TX_LESSTHAN || status_sel == STATUS_RX_LESSTHAN);
+ c->execctrl = (c->execctrl
+ & ~(PIO_SM0_EXECCTRL_STATUS_SEL_BITS | PIO_SM0_EXECCTRL_STATUS_N_BITS))
+ | ((((uint)status_sel) << PIO_SM0_EXECCTRL_STATUS_SEL_LSB) & PIO_SM0_EXECCTRL_STATUS_SEL_BITS)
+ | ((status_n << PIO_SM0_EXECCTRL_STATUS_N_LSB) & PIO_SM0_EXECCTRL_STATUS_N_BITS);
+}
+
+
+/*! \brief Get the default state machine configuration
+ * \ingroup sm_config
+ *
+ * Setting | Default
+ * --------|--------
+ * Out Pins | 32 starting at 0
+ * Set Pins | 0 starting at 0
+ * In Pins (base) | 0
+ * Side Set Pins (base) | 0
+ * Side Set | disabled
+ * Wrap | wrap=31, wrap_to=0
+ * In Shift | shift_direction=right, autopush=false, push_thrshold=32
+ * Out Shift | shift_direction=right, autopull=false, pull_thrshold=32
+ * Jmp Pin | 0
+ * Out Special | sticky=false, has_enable_pin=false, enable_pin_index=0
+ * Mov Status | status_sel=STATUS_TX_LESSTHAN, n=0
+ *
+ * \return the default state machine configuration which can then be modified.
+ */
+static inline pio_sm_config pio_get_default_sm_config(void) {
+ pio_sm_config c = {0, 0, 0, 0};
+ sm_config_set_clkdiv_int_frac(&c, 1, 0);
+ sm_config_set_wrap(&c, 0, 31);
+ sm_config_set_in_shift(&c, true, false, 32);
+ sm_config_set_out_shift(&c, true, false, 32);
+ return c;
+}
+
+/*! \brief Apply a state machine configuration to a state machine
+ * \ingroup hardware_pio
+ *
+ * \param pio Handle to PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param config the configuration to apply
+*/
+static inline void pio_sm_set_config(PIO pio, uint sm, const pio_sm_config *config) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio->sm[sm].clkdiv = config->clkdiv;
+ pio->sm[sm].execctrl = config->execctrl;
+ pio->sm[sm].shiftctrl = config->shiftctrl;
+ pio->sm[sm].pinctrl = config->pinctrl;
+}
+
+/*! \brief Return the instance number of a PIO instance
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \return the PIO instance number (either 0 or 1)
+ */
+static inline uint pio_get_index(PIO pio) {
+ check_pio_param(pio);
+ return pio == pio1 ? 1 : 0;
+}
+
+/*! \brief Setup the function select for a GPIO to use output from the given PIO instance
+ * \ingroup hardware_pio
+ *
+ * PIO appears as an alternate function in the GPIO muxing, just like an SPI
+ * or UART. This function configures that multiplexing to connect a given PIO
+ * instance to a GPIO. Note that this is not necessary for a state machine to
+ * be able to read the *input* value from a GPIO, but only for it to set the
+ * output value or output enable.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pin the GPIO pin whose function select to set
+ */
+static inline void pio_gpio_init(PIO pio, uint pin) {
+ check_pio_param(pio);
+ valid_params_if(PIO, pin < 32);
+ gpio_set_function(pin, pio == pio0 ? GPIO_FUNC_PIO0 : GPIO_FUNC_PIO1);
+}
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular state machine FIFO
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param is_tx true for sending data to the state machine, false for receiving data from the state machine
+ */
+static inline uint pio_get_dreq(PIO pio, uint sm, bool is_tx) {
+ static_assert(DREQ_PIO0_TX1 == DREQ_PIO0_TX0 + 1, "");
+ static_assert(DREQ_PIO0_TX2 == DREQ_PIO0_TX0 + 2, "");
+ static_assert(DREQ_PIO0_TX3 == DREQ_PIO0_TX0 + 3, "");
+ static_assert(DREQ_PIO0_RX0 == DREQ_PIO0_TX0 + NUM_PIO_STATE_MACHINES, "");
+ static_assert(DREQ_PIO1_RX0 == DREQ_PIO1_TX0 + NUM_PIO_STATE_MACHINES, "");
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return sm + (is_tx ? 0 : NUM_PIO_STATE_MACHINES) + (pio == pio0 ? DREQ_PIO0_TX0 : DREQ_PIO1_TX0);
+}
+
+typedef struct pio_program {
+ const uint16_t *instructions;
+ uint8_t length;
+ int8_t origin; // required instruction memory origin or -1
+} __packed pio_program_t;
+
+/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \return true if the program can be loaded; false if there is not suitable space in the instruction memory
+ */
+bool pio_can_add_program(PIO pio, const pio_program_t *program);
+
+/*! \brief Determine whether the given program can (at the time of the call) be loaded onto the PIO instance starting at a particular location
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \param offset the instruction memory offset wanted for the start of the program
+ * \return true if the program can be loaded at that location; false if there is not space in the instruction memory
+ */
+bool pio_can_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
+
+/*! \brief Attempt to load the program, panicking if not possible
+ * \ingroup hardware_pio
+ *
+ * \see pio_can_add_program() if you need to check whether the program can be loaded
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \return the instruction memory offset the program is loaded at
+ */
+uint pio_add_program(PIO pio, const pio_program_t *program);
+
+/*! \brief Attempt to load the program at the specified instruction memory offset, panicking if not possible
+ * \ingroup hardware_pio
+ *
+ * \see pio_can_add_program_at_offset() if you need to check whether the program can be loaded
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \param offset the instruction memory offset wanted for the start of the program
+ */
+void pio_add_program_at_offset(PIO pio, const pio_program_t *program, uint offset);
+
+/*! \brief Remove a program from a PIO instance's instruction memory
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param program the program definition
+ * \param loaded_offset the loaded offset returned when the program was added
+ */
+void pio_remove_program(PIO pio, const pio_program_t *program, uint loaded_offset);
+
+/*! \brief Clears all of a PIO instance's instruction memory
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ */
+void pio_clear_instruction_memory(PIO pio);
+
+/*! \brief Resets the state machine to a consistent state, and configures it
+ * \ingroup hardware_pio
+ *
+ * This method:
+ * - Disables the state machine (if running)
+ * - Clears the FIFOs
+ * - Applies the configuration specified by 'config'
+ * - Resets any internal state e.g. shift counters
+ * - Jumps to the initial program location given by 'initial_pc'
+ *
+ * The state machine is left disabled on return from this call.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param initial_pc the initial program memory offset to run from
+ * \param config the configuration to apply (or NULL to apply defaults)
+ */
+void pio_sm_init(PIO pio, uint sm, uint initial_pc, const pio_sm_config *config);
+
+/*! \brief Enable or disable a PIO state machine
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param enabled true to enable the state machine; false to disable
+ */
+static inline void pio_sm_set_enabled(PIO pio, uint sm, bool enabled) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio->ctrl = (pio->ctrl & ~(1u << sm)) | (bool_to_bit(enabled) << sm);
+}
+
+/*! \brief Enable or disable multiple PIO state machines
+ * \ingroup hardware_pio
+ *
+ * Note that this method just sets the enabled state of the state machine;
+ * if now enabled they continue exactly from where they left off.
+ *
+ * \see pio_enable_sm_mask_in_sync() if you wish to enable multiple state machines
+ * and ensure their clock dividers are in sync.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ * \param enabled true to enable the state machines; false to disable
+ */
+static inline void pio_set_sm_mask_enabled(PIO pio, uint32_t mask, bool enabled) {
+ check_pio_param(pio);
+ check_sm_mask(mask);
+ pio->ctrl = (pio->ctrl & ~mask) | (enabled ? mask : 0u);
+}
+
+/*! \brief Restart a state machine with a known state
+ * \ingroup hardware_pio
+ *
+ * This method clears the ISR, shift counters, clock divider counter
+ * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline void pio_sm_restart(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio->ctrl |= 1u << (PIO_CTRL_SM_RESTART_LSB + sm);
+}
+
+/*! \brief Restart multiple state machine with a known state
+ * \ingroup hardware_pio
+ *
+ * This method clears the ISR, shift counters, clock divider counter
+ * pin write flags, delay counter, latched EXEC instruction, and IRQ wait condition.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ */
+static inline void pio_restart_sm_mask(PIO pio, uint32_t mask) {
+ check_pio_param(pio);
+ check_sm_mask(mask);
+ pio->ctrl |= (mask << PIO_CTRL_SM_RESTART_LSB) & PIO_CTRL_SM_RESTART_BITS;
+}
+
+/*! \brief Restart a state machine's clock divider from a phase of 0
+ * \ingroup hardware_pio
+ *
+ * Each state machine's clock divider is a free-running piece of hardware,
+ * that generates a pattern of clock enable pulses for the state machine,
+ * based *only* on the configured integer/fractional divisor. The pattern of
+ * running/halted cycles slows the state machine's execution to some
+ * controlled rate.
+ *
+ * This function clears the divider's integer and fractional phase
+ * accumulators so that it restarts this pattern from the beginning. It is
+ * called automatically by pio_sm_init() but can also be called at a later
+ * time, when you enable the state machine, to ensure precisely consistent
+ * timing each time you load and run a given PIO program.
+ *
+ * More commonly this hardware mechanism is used to synchronise the execution
+ * clocks of multiple state machines -- see pio_clkdiv_restart_sm_mask().
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline void pio_sm_clkdiv_restart(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio->ctrl |= 1u << (PIO_CTRL_CLKDIV_RESTART_LSB + sm);
+}
+
+/*! \brief Restart multiple state machines' clock dividers from a phase of 0.
+ * \ingroup hardware_pio
+ *
+ * Each state machine's clock divider is a free-running piece of hardware,
+ * that generates a pattern of clock enable pulses for the state machine,
+ * based *only* on the configured integer/fractional divisor. The pattern of
+ * running/halted cycles slows the state machine's execution to some
+ * controlled rate.
+ *
+ * This function simultaneously clears the integer and fractional phase
+ * accumulators of multiple state machines' clock dividers. If these state
+ * machines all have the same integer and fractional divisors configured,
+ * their clock dividers will run in precise deterministic lockstep from this
+ * point.
+ *
+ * With their execution clocks synchronised in this way, it is then safe to
+ * e.g. have multiple state machines performing a 'wait irq' on the same flag,
+ * and all clear it on the same cycle.
+ *
+ * Also note that this function can be called whilst state machines are
+ * running (e.g. if you have just changed the clock divisors of some state
+ * machines and wish to resynchronise them), and that disabling a state
+ * machine does not halt its clock divider: that is, if multiple state
+ * machines have their clocks synchronised, you can safely disable and
+ * reenable one of the state machines without losing synchronisation.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ */
+static inline void pio_clkdiv_restart_sm_mask(PIO pio, uint32_t mask) {
+ check_pio_param(pio);
+ check_sm_mask(mask);
+ pio->ctrl |= (mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS;
+}
+
+/*! \brief Enable multiple PIO state machines synchronizing their clock dividers
+ * \ingroup hardware_pio
+ *
+ * This is equivalent to calling both pio_set_sm_mask_enabled() and
+ * pio_clkdiv_restart_sm_mask() on the *same* clock cycle. All state machines
+ * specified by 'mask' are started simultaneously and, assuming they have the
+ * same clock divisors, their divided clocks will stay precisely synchronised.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param mask bit mask of state machine indexes to modify the enabled state of
+ */
+static inline void pio_enable_sm_mask_in_sync(PIO pio, uint32_t mask) {
+ check_pio_param(pio);
+ check_sm_mask(mask);
+ pio->ctrl |= ((mask << PIO_CTRL_CLKDIV_RESTART_LSB) & PIO_CTRL_CLKDIV_RESTART_BITS) |
+ ((mask << PIO_CTRL_SM_ENABLE_LSB) & PIO_CTRL_SM_ENABLE_BITS);
+}
+
+/*! \brief PIO interrupt source numbers for pio related IRQs
+ * \ingroup hardware_pio
+ */
+enum pio_interrupt_source {
+ pis_interrupt0 = PIO_INTR_SM0_LSB,
+ pis_interrupt1 = PIO_INTR_SM1_LSB,
+ pis_interrupt2 = PIO_INTR_SM2_LSB,
+ pis_interrupt3 = PIO_INTR_SM3_LSB,
+ pis_sm0_tx_fifo_not_full = PIO_INTR_SM0_TXNFULL_LSB,
+ pis_sm1_tx_fifo_not_full = PIO_INTR_SM1_TXNFULL_LSB,
+ pis_sm2_tx_fifo_not_full = PIO_INTR_SM2_TXNFULL_LSB,
+ pis_sm3_tx_fifo_not_full = PIO_INTR_SM3_TXNFULL_LSB,
+ pis_sm0_rx_fifo_not_empty = PIO_INTR_SM0_RXNEMPTY_LSB,
+ pis_sm1_rx_fifo_not_empty = PIO_INTR_SM1_RXNEMPTY_LSB,
+ pis_sm2_rx_fifo_not_empty = PIO_INTR_SM2_RXNEMPTY_LSB,
+ pis_sm3_rx_fifo_not_empty = PIO_INTR_SM3_RXNEMPTY_LSB,
+};
+
+/*! \brief Enable/Disable a single source on a PIO's IRQ 0
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable IRQ 0 for the source, false to disable.
+ */
+static inline void pio_set_irq0_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source >= 12);
+ if (enabled)
+ hw_set_bits(&pio->inte0, 1u << source);
+ else
+ hw_clear_bits(&pio->inte0, 1u << source);
+}
+
+/*! \brief Enable/Disable a single source on a PIO's IRQ 1
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable IRQ 0 for the source, false to disable.
+ */
+static inline void pio_set_irq1_source_enabled(PIO pio, enum pio_interrupt_source source, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source >= 12);
+ if (enabled)
+ hw_set_bits(&pio->inte1, 1u << source);
+ else
+ hw_clear_bits(&pio->inte1, 1u << source);
+}
+
+/*! \brief Enable/Disable multiple sources on a PIO's IRQ 0
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on IRQ 0, false to disable all the sources specified in the mask on IRQ 0
+ */
+static inline void pio_set_irq0_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source_mask > PIO_INTR_BITS);
+ if (enabled) {
+ hw_set_bits(&pio->inte0, source_mask);
+ } else {
+ hw_clear_bits(&pio->inte0, source_mask);
+ }
+}
+
+/*! \brief Enable/Disable multiple sources on a PIO's IRQ 1
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on IRQ 1, false to disable all the source specified in the mask on IRQ 1
+ */
+static inline void pio_set_irq1_source_mask_enabled(PIO pio, uint32_t source_mask, bool enabled) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, source_mask > PIO_INTR_BITS);
+ if (enabled) {
+ hw_set_bits(&pio->inte1, source_mask);
+ } else {
+ hw_clear_bits(&pio->inte1, source_mask);
+ }
+}
+
+/*! \brief Enable/Disable a single source on a PIO's specified (0/1) IRQ index
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param irq_index the IRQ index; either 0 or 1
+ * \param source the source number (see \ref pio_interrupt_source)
+ * \param enabled true to enable the source on the specified IRQ, false to disable.
+ */
+static inline void pio_set_irqn_source_enabled(PIO pio, uint irq_index, enum pio_interrupt_source source, bool enabled) {
+ invalid_params_if(PIO, irq_index > 1);
+ if (irq_index) {
+ pio_set_irq1_source_enabled(pio, source, enabled);
+ } else {
+ pio_set_irq0_source_enabled(pio, source, enabled);
+ }
+}
+
+/*! \brief Enable/Disable multiple sources on a PIO's specified (0/1) IRQ index
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param irq_index the IRQ index; either 0 or 1
+ * \param source_mask Mask of bits, one for each source number (see \ref pio_interrupt_source) to affect
+ * \param enabled true to enable all the sources specified in the mask on the specified IRQ, false to disable all the sources specified in the mask on the specified IRQ
+ */
+static inline void pio_set_irqn_source_mask_enabled(PIO pio, uint irq_index, uint32_t source_mask, bool enabled) {
+ invalid_params_if(PIO, irq_index > 1);
+ if (irq_index) {
+ pio_set_irq0_source_mask_enabled(pio, source_mask, enabled);
+ } else {
+ pio_set_irq1_source_mask_enabled(pio, source_mask, enabled);
+ }
+}
+
+/*! \brief Determine if a particular PIO interrupt is set
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pio_interrupt_num the PIO interrupt number 0-7
+ * \return true if corresponding PIO interrupt is currently set
+ */
+static inline bool pio_interrupt_get(PIO pio, uint pio_interrupt_num) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, pio_interrupt_num >= 8);
+ return pio->irq & (1u << pio_interrupt_num);
+}
+
+/*! \brief Clear a particular PIO interrupt
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param pio_interrupt_num the PIO interrupt number 0-7
+ */
+static inline void pio_interrupt_clear(PIO pio, uint pio_interrupt_num) {
+ check_pio_param(pio);
+ invalid_params_if(PIO, pio_interrupt_num >= 8);
+ hw_set_bits(&pio->irq, (1u << pio_interrupt_num));
+}
+
+/*! \brief Return the current program counter for a state machine
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return the program counter
+ */
+static inline uint8_t pio_sm_get_pc(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return (uint8_t) pio->sm[sm].addr;
+}
+
+/*! \brief Immediately execute an instruction on a state machine
+ * \ingroup hardware_pio
+ *
+ * This instruction is executed instead of the next instruction in the normal control flow on the state machine.
+ * Subsequent calls to this method replace the previous executed
+ * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction
+ * is still running (i.e. it is stalled on some condition)
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param instr the encoded PIO instruction
+ */
+inline static void pio_sm_exec(PIO pio, uint sm, uint instr) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio->sm[sm].instr = instr;
+}
+
+/*! \brief Determine if an instruction set by pio_sm_exec() is stalled executing
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the executed instruction is still running (stalled)
+ */
+static inline bool pio_sm_is_exec_stalled(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return !!(pio->sm[sm].execctrl & PIO_SM0_EXECCTRL_EXEC_STALLED_BITS);
+}
+
+/*! \brief Immediately execute an instruction on a state machine and wait for it to complete
+ * \ingroup hardware_pio
+ *
+ * This instruction is executed instead of the next instruction in the normal control flow on the state machine.
+ * Subsequent calls to this method replace the previous executed
+ * instruction if it is still running. \see pio_sm_is_exec_stalled() to see if an executed instruction
+ * is still running (i.e. it is stalled on some condition)
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param instr the encoded PIO instruction
+ */
+static inline void pio_sm_exec_wait_blocking(PIO pio, uint sm, uint instr) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio_sm_exec(pio, sm, instr);
+ while (pio_sm_is_exec_stalled(pio, sm)) tight_loop_contents();
+}
+
+/*! \brief Set the current wrap configuration for a state machine
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param wrap_target the instruction memory address to wrap to
+ * \param wrap the instruction memory address after which to set the program counter to wrap_target
+ * if the instruction does not itself update the program_counter
+ */
+static inline void pio_sm_set_wrap(PIO pio, uint sm, uint wrap_target, uint wrap) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ valid_params_if(PIO, wrap < PIO_INSTRUCTION_COUNT);
+ valid_params_if(PIO, wrap_target < PIO_INSTRUCTION_COUNT);
+ pio->sm[sm].execctrl =
+ (pio->sm[sm].execctrl & ~(PIO_SM0_EXECCTRL_WRAP_TOP_BITS | PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS)) |
+ (wrap_target << PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB) |
+ (wrap << PIO_SM0_EXECCTRL_WRAP_TOP_LSB);
+}
+
+/*! \brief Set the current 'out' pins for a state machine
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'set' and 'sideset' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param out_base 0-31 First pin to set as output
+ * \param out_count 0-32 Number of pins to set.
+ */
+static inline void pio_sm_set_out_pins(PIO pio, uint sm, uint out_base, uint out_count) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ valid_params_if(PIO, out_base < 32);
+ valid_params_if(PIO, out_count <= 32);
+ pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_OUT_BASE_BITS | PIO_SM0_PINCTRL_OUT_COUNT_BITS)) |
+ (out_base << PIO_SM0_PINCTRL_OUT_BASE_LSB) |
+ (out_count << PIO_SM0_PINCTRL_OUT_COUNT_LSB);
+}
+
+
+/*! \brief Set the current 'set' pins for a state machine
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'sideset' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param set_base 0-31 First pin to set as
+ * \param set_count 0-5 Number of pins to set.
+ */
+static inline void pio_sm_set_set_pins(PIO pio, uint sm, uint set_base, uint set_count) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ valid_params_if(PIO, set_base < 32);
+ valid_params_if(PIO, set_count <= 5);
+ pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~(PIO_SM0_PINCTRL_SET_BASE_BITS | PIO_SM0_PINCTRL_SET_COUNT_BITS)) |
+ (set_base << PIO_SM0_PINCTRL_SET_BASE_LSB) |
+ (set_count << PIO_SM0_PINCTRL_SET_COUNT_LSB);
+}
+
+/*! \brief Set the current 'in' pins for a state machine
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'out', ''set' and 'sideset' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param in_base 0-31 First pin to use as input
+ */
+static inline void pio_sm_set_in_pins(PIO pio, uint sm, uint in_base) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ valid_params_if(PIO, in_base < 32);
+ pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_IN_BASE_BITS) |
+ (in_base << PIO_SM0_PINCTRL_IN_BASE_LSB);
+}
+
+/*! \brief Set the current 'sideset' pins for a state machine
+ * \ingroup sm_config
+ *
+ * Can overlap with the 'in', 'out' and 'set' pins
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param sideset_base 0-31 base pin for 'side set'
+ */
+static inline void pio_sm_set_sideset_pins(PIO pio, uint sm, uint sideset_base) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ valid_params_if(PIO, sideset_base < 32);
+ pio->sm[sm].pinctrl = (pio->sm[sm].pinctrl & ~PIO_SM0_PINCTRL_SIDESET_BASE_BITS) |
+ (sideset_base << PIO_SM0_PINCTRL_SIDESET_BASE_LSB);
+}
+
+/*! \brief Write a word of data to a state machine's TX FIFO
+ * \ingroup hardware_pio
+ *
+ * This is a raw FIFO access that does not check for fullness. If the FIFO is
+ * full, the FIFO contents and state are not affected by the write attempt.
+ * Hardware sets the TXOVER sticky flag for this FIFO in FDEBUG, to indicate
+ * that the system attempted to write to a full FIFO.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param data the 32 bit data value
+ *
+ * \sa pio_sm_put_blocking()
+ */
+static inline void pio_sm_put(PIO pio, uint sm, uint32_t data) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio->txf[sm] = data;
+}
+
+/*! \brief Read a word of data from a state machine's RX FIFO
+ * \ingroup hardware_pio
+ *
+ * This is a raw FIFO access that does not check for emptiness. If the FIFO is
+ * empty, the hardware ignores the attempt to read from the FIFO (the FIFO
+ * remains in an empty state following the read) and the sticky RXUNDER flag
+ * for this FIFO is set in FDEBUG to indicate that the system tried to read
+ * from this FIFO when empty. The data returned by this function is undefined
+ * when the FIFO is empty.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ *
+ * \sa pio_sm_get_blocking()
+ */
+static inline uint32_t pio_sm_get(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return pio->rxf[sm];
+}
+
+/*! \brief Determine if a state machine's RX FIFO is full
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the RX FIFO is full
+ */
+static inline bool pio_sm_is_rx_fifo_full(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return (pio->fstat & (1u << (PIO_FSTAT_RXFULL_LSB + sm))) != 0;
+}
+
+/*! \brief Determine if a state machine's RX FIFO is empty
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the RX FIFO is empty
+ */
+static inline bool pio_sm_is_rx_fifo_empty(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return (pio->fstat & (1u << (PIO_FSTAT_RXEMPTY_LSB + sm))) != 0;
+}
+
+/*! \brief Return the number of elements currently in a state machine's RX FIFO
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return the number of elements in the RX FIFO
+ */
+static inline uint pio_sm_get_rx_fifo_level(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ uint bitoffs = PIO_FLEVEL_RX0_LSB + sm * (PIO_FLEVEL_RX1_LSB - PIO_FLEVEL_RX0_LSB);
+ const uint32_t mask = PIO_FLEVEL_RX0_BITS >> PIO_FLEVEL_RX0_LSB;
+ return (pio->flevel >> bitoffs) & mask;
+}
+
+/*! \brief Determine if a state machine's TX FIFO is full
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the TX FIFO is full
+ */
+static inline bool pio_sm_is_tx_fifo_full(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return (pio->fstat & (1u << (PIO_FSTAT_TXFULL_LSB + sm))) != 0;
+}
+
+/*! \brief Determine if a state machine's TX FIFO is empty
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if the TX FIFO is empty
+ */
+static inline bool pio_sm_is_tx_fifo_empty(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ return (pio->fstat & (1u << (PIO_FSTAT_TXEMPTY_LSB + sm))) != 0;
+}
+
+/*! \brief Return the number of elements currently in a state machine's TX FIFO
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return the number of elements in the TX FIFO
+ */
+static inline uint pio_sm_get_tx_fifo_level(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ unsigned int bitoffs = PIO_FLEVEL_TX0_LSB + sm * (PIO_FLEVEL_TX1_LSB - PIO_FLEVEL_TX0_LSB);
+ const uint32_t mask = PIO_FLEVEL_TX0_BITS >> PIO_FLEVEL_TX0_LSB;
+ return (pio->flevel >> bitoffs) & mask;
+}
+
+/*! \brief Write a word of data to a state machine's TX FIFO, blocking if the FIFO is full
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param data the 32 bit data value
+ */
+static inline void pio_sm_put_blocking(PIO pio, uint sm, uint32_t data) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ while (pio_sm_is_tx_fifo_full(pio, sm)) tight_loop_contents();
+ pio_sm_put(pio, sm, data);
+}
+
+/*! \brief Read a word of data from a state machine's RX FIFO, blocking if the FIFO is empty
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline uint32_t pio_sm_get_blocking(PIO pio, uint sm) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ while (pio_sm_is_rx_fifo_empty(pio, sm)) tight_loop_contents();
+ return pio_sm_get(pio, sm);
+}
+
+/*! \brief Empty out a state machine's TX FIFO
+ * \ingroup hardware_pio
+ *
+ * This method executes `pull` instructions on the state machine until the TX
+ * FIFO is empty. This disturbs the contents of the OSR, so see also
+ * pio_sm_clear_fifos() which clears both FIFOs but leaves the state machine's
+ * internal state undisturbed.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ *
+ * \sa pio_sm_clear_fifos()
+ */
+void pio_sm_drain_tx_fifo(PIO pio, uint sm);
+
+/*! \brief set the current clock divider for a state machine using a 16:8 fraction
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param div_int the integer part of the clock divider
+ * \param div_frac the fractional part of the clock divider in 1/256s
+ */
+static inline void pio_sm_set_clkdiv_int_frac(PIO pio, uint sm, uint16_t div_int, uint8_t div_frac) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ pio->sm[sm].clkdiv =
+ (((uint)div_frac) << PIO_SM0_CLKDIV_FRAC_LSB) |
+ (((uint)div_int) << PIO_SM0_CLKDIV_INT_LSB);
+}
+
+/*! \brief set the current clock divider for a state machine
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \param div the floating point clock divider
+ */
+static inline void pio_sm_set_clkdiv(PIO pio, uint sm, float div) {
+ check_pio_param(pio);
+ check_sm_param(sm);
+ uint16_t div_int;
+ uint8_t div_frac;
+ pio_calculate_clkdiv_from_float(div, &div_int, &div_frac);
+ pio_sm_set_clkdiv_int_frac(pio, sm, div_int, div_frac);
+}
+
+/*! \brief Clear a state machine's TX and RX FIFOs
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+static inline void pio_sm_clear_fifos(PIO pio, uint sm) {
+ // changing the FIFO join state clears the fifo
+ check_pio_param(pio);
+ check_sm_param(sm);
+ hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
+ hw_xor_bits(&pio->sm[sm].shiftctrl, PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS);
+}
+
+/*! \brief Use a state machine to set a value on all pins for the PIO instance
+ * \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on all 32 pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_values the pin values to set
+ */
+void pio_sm_set_pins(PIO pio, uint sm, uint32_t pin_values);
+
+/*! \brief Use a state machine to set a value on multiple pins for the PIO instance
+ * \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set values on up to 32 pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin states, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_values the pin values to set (if the corresponding bit in pin_mask is set)
+ * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied.
+ */
+void pio_sm_set_pins_with_mask(PIO pio, uint sm, uint32_t pin_values, uint32_t pin_mask);
+
+/*! \brief Use a state machine to set the pin directions for multiple pins for the PIO instance
+ * \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set pin directions on up to 32 pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_dirs the pin directions to set - 1 = out, 0 = in (if the corresponding bit in pin_mask is set)
+ * \param pin_mask a bit for each pin to indicate whether the corresponding pin_value for that pin should be applied.
+ */
+void pio_sm_set_pindirs_with_mask(PIO pio, uint sm, uint32_t pin_dirs, uint32_t pin_mask);
+
+/*! \brief Use a state machine to set the same pin direction for multiple consecutive pins for the PIO instance
+ * \ingroup hardware_pio
+ *
+ * This method repeatedly reconfigures the target state machine's pin configuration and executes 'set' instructions to set the pin direction on consecutive pins,
+ * before restoring the state machine's pin configuration to what it was.
+ *
+ * This method is provided as a convenience to set initial pin directions, and should not be used against a state machine that is enabled.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3) to use
+ * \param pin_base the first pin to set a direction for
+ * \param pin_count the count of consecutive pins to set the direction for
+ * \param is_out the direction to set; true = out, false = in
+ */
+void pio_sm_set_consecutive_pindirs(PIO pio, uint sm, uint pin_base, uint pin_count, bool is_out);
+
+/*! \brief Mark a state machine as used
+ * \ingroup hardware_pio
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the state machine
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+void pio_sm_claim(PIO pio, uint sm);
+
+/*! \brief Mark multiple state machines as used
+ * \ingroup hardware_pio
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if any of the state machines
+ * are already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm_mask Mask of state machine indexes
+ */
+void pio_claim_sm_mask(PIO pio, uint sm_mask);
+
+/*! \brief Mark a state machine as no longer used
+ * \ingroup hardware_pio
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ */
+void pio_sm_unclaim(PIO pio, uint sm);
+
+/*! \brief Claim a free state machine on a PIO instance
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param required if true the function will panic if none are available
+ * \return the state machine index or -1 if required was false, and none were free
+ */
+int pio_claim_unused_sm(PIO pio, bool required);
+
+/*! \brief Determine if a PIO state machine is claimed
+ * \ingroup hardware_pio
+ *
+ * \param pio The PIO instance; either \ref pio0 or \ref pio1
+ * \param sm State machine index (0..3)
+ * \return true if claimed, false otherwise
+ * \see pio_sm_claim
+ * \see pio_claim_sm_mask
+ */
+bool pio_sm_is_claimed(PIO pio, uint sm);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // _PIO_H_
diff --git a/arkanoid/pico/hardware/pio_instructions.h b/arkanoid/pico/hardware/pio_instructions.h
new file mode 100644
index 0000000..3b34f2f
--- /dev/null
+++ b/arkanoid/pico/hardware/pio_instructions.h
@@ -0,0 +1,484 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PIO_INSTRUCTIONS_H_
+#define _HARDWARE_PIO_INSTRUCTIONS_H_
+
+#include "../pico.h"
+
+/** \brief PIO instruction encoding
+ * \defgroup pio_instructions pio_instructions
+ * \ingroup hardware_pio
+ *
+ * Functions for generating PIO instruction encodings programmatically. In debug builds
+ *`PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` can be set to 1 to enable validation of encoding function
+ * parameters.
+ *
+ * For fuller descriptions of the instructions in question see the "RP2040 Datasheet"
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS, Enable/disable assertions in the PIO instructions, type=bool, default=0, group=pio_instructions
+#ifndef PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS
+#define PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum pio_instr_bits {
+ pio_instr_bits_jmp = 0x0000,
+ pio_instr_bits_wait = 0x2000,
+ pio_instr_bits_in = 0x4000,
+ pio_instr_bits_out = 0x6000,
+ pio_instr_bits_push = 0x8000,
+ pio_instr_bits_pull = 0x8080,
+ pio_instr_bits_mov = 0xa000,
+ pio_instr_bits_irq = 0xc000,
+ pio_instr_bits_set = 0xe000,
+};
+
+#ifndef NDEBUG
+#define _PIO_INVALID_IN_SRC 0x08u
+#define _PIO_INVALID_OUT_DEST 0x10u
+#define _PIO_INVALID_SET_DEST 0x20u
+#define _PIO_INVALID_MOV_SRC 0x40u
+#define _PIO_INVALID_MOV_DEST 0x80u
+#else
+#define _PIO_INVALID_IN_SRC 0u
+#define _PIO_INVALID_OUT_DEST 0u
+#define _PIO_INVALID_SET_DEST 0u
+#define _PIO_INVALID_MOV_SRC 0u
+#define _PIO_INVALID_MOV_DEST 0u
+#endif
+
+/*! \brief Enumeration of values to pass for source/destination args for instruction encoding functions
+ * \ingroup pio_instructions
+ *
+ * \note Not all values are suitable for all functions. Validity is only checked in debug mode when
+ * `PARAM_ASSERTIONS_ENABLED_PIO_INSTRUCTIONS` is 1
+ */
+enum pio_src_dest {
+ pio_pins = 0u,
+ pio_x = 1u,
+ pio_y = 2u,
+ pio_null = 3u | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
+ pio_pindirs = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
+ pio_exec_mov = 4u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC,
+ pio_status = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_DEST,
+ pio_pc = 5u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC,
+ pio_isr = 6u | _PIO_INVALID_SET_DEST,
+ pio_osr = 7u | _PIO_INVALID_OUT_DEST | _PIO_INVALID_SET_DEST,
+ pio_exec_out = 7u | _PIO_INVALID_IN_SRC | _PIO_INVALID_SET_DEST | _PIO_INVALID_MOV_SRC | _PIO_INVALID_MOV_DEST,
+};
+
+static inline uint _pio_major_instr_bits(uint instr) {
+ return instr & 0xe000u;
+}
+
+static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) {
+ valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7);
+#if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS)
+ uint32_t major = _pio_major_instr_bits(instr_bits);
+ if (major == pio_instr_bits_in || major == pio_instr_bits_out) {
+ assert(arg2 && arg2 <= 32);
+ } else {
+ assert(arg2 <= 31);
+ }
+#endif
+ return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu);
+}
+
+static inline uint _pio_encode_instr_and_src_dest(enum pio_instr_bits instr_bits, enum pio_src_dest dest, uint value) {
+ return _pio_encode_instr_and_args(instr_bits, dest & 7u, value);
+}
+
+/*! \brief Encode just the delay slot bits of an instruction
+ * \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the delay
+ * slot suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_sideset and \ref pio_encode_sideset_opt
+ * as they share the same bits within the instruction encoding.
+ *
+ * \param cycles the number of cycles 0-31 (or less if side set is being used)
+ * \return the delay slot bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_delay(uint cycles) {
+ // note that the maximum cycles will be smaller if sideset_bit_count > 0
+ valid_params_if(PIO_INSTRUCTIONS, cycles <= 0x1f);
+ return cycles << 8u;
+}
+
+/*! \brief Encode just the side set bits of an instruction (in non optional side set mode)
+ * \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
+ * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
+ * within the instruction encoding.
+ *
+ * \param sideset_bit_count number of side set bits as would be specified via `.sideset` in pioasm
+ * \param value the value to sideset on the pins
+ * \return the side set bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_sideset(uint sideset_bit_count, uint value) {
+ valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 5);
+ valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
+ return value << (13u - sideset_bit_count);
+}
+
+/*! \brief Encode just the side set bits of an instruction (in optional -`opt` side set mode)
+ * \ingroup pio_instructions
+ *
+ * \note This function does not return a valid instruction encoding; instead it returns an encoding of the side set bits
+ * suitable for `OR`ing with the result of an encoding function for an actual instruction. Care should be taken when
+ * combining the results of this function with the results of \ref pio_encode_delay as they share the same bits
+ * within the instruction encoding.
+ *
+ * \param sideset_bit_count number of side set bits as would be specified via `.sideset <n> opt` in pioasm
+ * \param value the value to sideset on the pins
+ * \return the side set bits to be ORed with an instruction encoding
+ */
+static inline uint pio_encode_sideset_opt(uint sideset_bit_count, uint value) {
+ valid_params_if(PIO_INSTRUCTIONS, sideset_bit_count >= 1 && sideset_bit_count <= 4);
+ valid_params_if(PIO_INSTRUCTIONS, value <= ((1u << sideset_bit_count) - 1));
+ return 0x1000u | value << (12u - sideset_bit_count);
+}
+
+/*! \brief Encode an unconditional JMP instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X zero instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !X <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_x(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 1, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X non-zero (and post-decrement X) instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP X-- <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_x_dec(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 2, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch Y zero instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !Y <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_y(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 3, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch Y non-zero (and post-decrement Y) instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP Y-- <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_y_dec(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 4, addr);
+}
+
+/*! \brief Encode a conditional JMP if scratch X not equal scratch Y instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP X!=Y <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_x_ne_y(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 5, addr);
+}
+
+/*! \brief Encode a conditional JMP if input pin high instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP PIN <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_pin(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 6, addr);
+}
+
+/*! \brief Encode a conditional JMP if output shift register not empty instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `JMP !OSRE <addr>`
+ *
+ * \param addr The target address 0-31 (an absolute address within the PIO instruction memory)
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_jmp_not_osre(uint addr) {
+ return _pio_encode_instr_and_args(pio_instr_bits_jmp, 7, addr);
+}
+
+static inline uint _pio_encode_irq(bool relative, uint irq) {
+ valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
+ return (relative ? 0x10u : 0x0u) | irq;
+}
+
+/*! \brief Encode a WAIT for GPIO pin instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> GPIO <gpio>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param gpio The real GPIO number 0-31
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_gpio(bool polarity, uint gpio) {
+ return _pio_encode_instr_and_args(pio_instr_bits_wait, 0u | (polarity ? 4u : 0u), gpio);
+}
+
+/*! \brief Encode a WAIT for pin instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> PIN <pin>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param pin The pin number 0-31 relative to the executing SM's input pin mapping
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_pin(bool polarity, uint pin) {
+ return _pio_encode_instr_and_args(pio_instr_bits_wait, 1u | (polarity ? 4u : 0u), pin);
+}
+
+/*! \brief Encode a WAIT for IRQ instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `WAIT <polarity> IRQ <irq> <relative>`
+ *
+ * \param polarity true for `WAIT 1`, false for `WAIT 0`
+ * \param relative true for a `WAIT IRQ <irq> REL`, false for regular `WAIT IRQ <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_wait_irq(bool polarity, bool relative, uint irq) {
+ valid_params_if(PIO_INSTRUCTIONS, irq <= 7);
+ return _pio_encode_instr_and_args(pio_instr_bits_wait, 2u | (polarity ? 4u : 0u), _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode an IN instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `IN <src>, <count>`
+ *
+ * \param src The source to take data from
+ * \param count The number of bits 1-32
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_in(enum pio_src_dest src, uint count) {
+ valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_IN_SRC));
+ return _pio_encode_instr_and_src_dest(pio_instr_bits_in, src, count);
+}
+
+/*! \brief Encode an OUT instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `OUT <src>, <count>`
+ *
+ * \param dest The destination to write data to
+ * \param count The number of bits 1-32
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_out(enum pio_src_dest dest, uint count) {
+ valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_OUT_DEST));
+ return _pio_encode_instr_and_src_dest(pio_instr_bits_out, dest, count);
+}
+
+/*! \brief Encode a PUSH instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `PUSH <if_full>, <block>`
+ *
+ * \param if_full true for `PUSH IF_FULL ...`, false for `PUSH ...`
+ * \param block true for `PUSH ... BLOCK`, false for `PUSH ...`
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_push(bool if_full, bool block) {
+ return _pio_encode_instr_and_args(pio_instr_bits_push, (if_full ? 2u : 0u) | (block ? 1u : 0u), 0);
+}
+
+/*! \brief Encode a PULL instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `PULL <if_empty>, <block>`
+ *
+ * \param if_empty true for `PULL IF_EMPTY ...`, false for `PULL ...`
+ * \param block true for `PULL ... BLOCK`, false for `PULL ...`
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_pull(bool if_empty, bool block) {
+ return _pio_encode_instr_and_args(pio_instr_bits_pull, (if_empty ? 2u : 0u) | (block ? 1u : 0u), 0);
+}
+
+/*! \brief Encode a MOV instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, <src>`
+ *
+ * \param dest The destination to write data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov(enum pio_src_dest dest, enum pio_src_dest src) {
+ valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
+ valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
+ return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, src & 7u);
+}
+
+/*! \brief Encode a MOV instruction with bit invert
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, ~<src>`
+ *
+ * \param dest The destination to write inverted data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov_not(enum pio_src_dest dest, enum pio_src_dest src) {
+ valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
+ valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
+ return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (1u << 3u) | (src & 7u));
+}
+
+/*! \brief Encode a MOV instruction with bit reverse
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `MOV <dest>, ::<src>`
+ *
+ * \param dest The destination to write bit reversed data to
+ * \param src The source to take data from
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_mov_reverse(enum pio_src_dest dest, enum pio_src_dest src) {
+ valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_MOV_DEST));
+ valid_params_if(PIO_INSTRUCTIONS, !(src & _PIO_INVALID_MOV_SRC));
+ return _pio_encode_instr_and_src_dest(pio_instr_bits_mov, dest, (2u << 3u) | (src & 7u));
+}
+
+/*! \brief Encode a IRQ SET instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ SET <irq> <relative>`
+ *
+ * \param relative true for a `IRQ SET <irq> REL`, false for regular `IRQ SET <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_set(bool relative, uint irq) {
+ return _pio_encode_instr_and_args(pio_instr_bits_irq, 0, _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode a IRQ WAIT instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ WAIT <irq> <relative>`
+ *
+ * \param relative true for a `IRQ WAIT <irq> REL`, false for regular `IRQ WAIT <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_wait(bool relative, uint irq) {
+ return _pio_encode_instr_and_args(pio_instr_bits_irq, 1, _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode a IRQ CLEAR instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `IRQ CLEAR <irq> <relative>`
+ *
+ * \param relative true for a `IRQ CLEAR <irq> REL`, false for regular `IRQ CLEAR <irq>`
+ * \param irq the irq number 0-7
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_irq_clear(bool relative, uint irq) {
+ return _pio_encode_instr_and_args(pio_instr_bits_irq, 2, _pio_encode_irq(relative, irq));
+}
+
+/*! \brief Encode a SET instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `SET <dest>, <value>`
+ *
+ * \param dest The destination to apply the value to
+ * \param value The value 0-31
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_set(enum pio_src_dest dest, uint value) {
+ valid_params_if(PIO_INSTRUCTIONS, !(dest & _PIO_INVALID_SET_DEST));
+ return _pio_encode_instr_and_src_dest(pio_instr_bits_set, dest, value);
+}
+
+/*! \brief Encode a NOP instruction
+ * \ingroup pio_instructions
+ *
+ * This is the equivalent of `NOP` which is itself encoded as `MOV y, y`
+ *
+ * \return The instruction encoding with 0 delay and no side set value
+ * \see pio_encode_delay, pio_encode_sideset, pio_encode_sideset_opt
+ */
+static inline uint pio_encode_nop(void) {
+ return pio_encode_mov(pio_y, pio_y);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/platform_defs.h b/arkanoid/pico/hardware/platform_defs.h
new file mode 100644
index 0000000..08c7159
--- /dev/null
+++ b/arkanoid/pico/hardware/platform_defs.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PLATFORM_DEFS_H
+#define _HARDWARE_PLATFORM_DEFS_H
+
+// This header is included from C and assembler - intended mostly for #defines; guard other stuff with #ifdef __ASSEMBLER__
+
+#ifndef _u
+#ifdef __ASSEMBLER__
+#define _u(x) x
+#else
+#define _u(x) x ## u
+#endif
+#endif
+
+#define NUM_CORES _u(2)
+#define NUM_DMA_CHANNELS _u(12)
+#define NUM_DMA_TIMERS _u(4)
+#define NUM_IRQS _u(32)
+#define NUM_PIOS _u(2)
+#define NUM_PIO_STATE_MACHINES _u(4)
+#define NUM_PWM_SLICES _u(8)
+#define NUM_SPIN_LOCKS _u(32)
+#define NUM_UARTS _u(2)
+#define NUM_I2CS _u(2)
+#define NUM_SPIS _u(2)
+#define NUM_TIMERS _u(4)
+#define NUM_ADC_CHANNELS _u(5)
+
+#define NUM_BANK0_GPIOS _u(30)
+#define NUM_QSPI_GPIOS _u(6)
+
+#define PIO_INSTRUCTION_COUNT _u(32)
+
+// PICO_CONFIG: XOSC_MHZ, The crystal oscillator frequency in Mhz, type=int, default=12, advanced=true, group=hardware_base
+#ifndef XOSC_MHZ
+#define XOSC_MHZ _u(12)
+#endif
+
+#endif
+
diff --git a/arkanoid/pico/hardware/pll.c b/arkanoid/pico/hardware/pll.c
new file mode 100644
index 0000000..9fdd6f8
--- /dev/null
+++ b/arkanoid/pico/hardware/pll.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// For MHZ definitions etc
+#include "clocks.h"
+#include "pll.h"
+#include "resets.h"
+
+/// \tag::pll_init_calculations[]
+void pll_init(PLL pll, uint refdiv, uint vco_freq, uint post_div1, uint post_div2) {
+ uint32_t ref_mhz = XOSC_MHZ / refdiv;
+
+ // What are we multiplying the reference clock by to get the vco freq
+ // (The regs are called div, because you divide the vco output and compare it to the refclk)
+ uint32_t fbdiv = vco_freq / (ref_mhz * MHZ);
+/// \end::pll_init_calculations[]
+
+ // fbdiv
+ assert(fbdiv >= 16 && fbdiv <= 320);
+
+ // Check divider ranges
+ assert((post_div1 >= 1 && post_div1 <= 7) && (post_div2 >= 1 && post_div2 <= 7));
+
+ // post_div1 should be >= post_div2
+ // from appnote page 11
+ // postdiv1 is designed to operate with a higher input frequency
+ // than postdiv2
+ assert(post_div2 <= post_div1);
+
+ // Check that reference frequency is no greater than vco / 16
+ assert(ref_mhz <= (vco_freq / 16));
+
+ // div1 feeds into div2 so if div1 is 5 and div2 is 2 then you get a divide by 10
+ uint32_t pdiv = (post_div1 << PLL_PRIM_POSTDIV1_LSB) |
+ (post_div2 << PLL_PRIM_POSTDIV2_LSB);
+
+/// \tag::pll_init_finish[]
+ if ((pll->cs & PLL_CS_LOCK_BITS) &&
+ (refdiv == (pll->cs & PLL_CS_REFDIV_BITS)) &&
+ (fbdiv == (pll->fbdiv_int & PLL_FBDIV_INT_BITS)) &&
+ (pdiv == (pll->prim & (PLL_PRIM_POSTDIV1_BITS & PLL_PRIM_POSTDIV2_BITS)))) {
+ // do not disrupt PLL that is already correctly configured and operating
+ return;
+ }
+
+ uint32_t pll_reset = (pll_usb_hw == pll) ? RESETS_RESET_PLL_USB_BITS : RESETS_RESET_PLL_SYS_BITS;
+ reset_block(pll_reset);
+ unreset_block_wait(pll_reset);
+
+ // Load VCO-related dividers before starting VCO
+ pll->cs = refdiv;
+ pll->fbdiv_int = fbdiv;
+
+ // Turn on PLL
+ uint32_t power = PLL_PWR_PD_BITS | // Main power
+ PLL_PWR_VCOPD_BITS; // VCO Power
+
+ hw_clear_bits(&pll->pwr, power);
+
+ // Wait for PLL to lock
+ while (!(pll->cs & PLL_CS_LOCK_BITS)) tight_loop_contents();
+
+ // Set up post dividers
+ pll->prim = pdiv;
+
+ // Turn on post divider
+ hw_clear_bits(&pll->pwr, PLL_PWR_POSTDIVPD_BITS);
+/// \end::pll_init_finish[]
+}
+
+void pll_deinit(PLL pll) {
+ // todo: Make sure there are no sources running from this pll?
+ pll->pwr = PLL_PWR_BITS;
+}
diff --git a/arkanoid/pico/hardware/pll.h b/arkanoid/pico/hardware/pll.h
new file mode 100644
index 0000000..b7ab27e
--- /dev/null
+++ b/arkanoid/pico/hardware/pll.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PLL_H_
+#define _HARDWARE_PLL_H_
+
+#include "../pico.h"
+#include "structs/pll.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file pll.h
+ * \defgroup hardware_pll hardware_pll
+ *
+ * Phase Locked Loop control APIs
+ *
+ * There are two PLLs in RP2040. They are:
+ * - pll_sys - Used to generate up to a 133MHz system clock
+ * - pll_usb - Used to generate a 48MHz USB reference clock
+ *
+ * For details on how the PLL's are calculated, please refer to the RP2040 datasheet.
+ */
+
+typedef pll_hw_t *PLL;
+
+#define pll_sys pll_sys_hw
+#define pll_usb pll_usb_hw
+
+/*! \brief Initialise specified PLL.
+ * \ingroup hardware_pll
+ * \param pll pll_sys or pll_usb
+ * \param ref_div Input clock divider.
+ * \param vco_freq Requested output from the VCO (voltage controlled oscillator)
+ * \param post_div1 Post Divider 1 - range 1-7. Must be >= post_div2
+ * \param post_div2 Post Divider 2 - range 1-7
+ */
+void pll_init(PLL pll, uint ref_div, uint vco_freq, uint post_div1, uint post_div2);
+
+/*! \brief Release/uninitialise specified PLL.
+ * \ingroup hardware_pll
+ *
+ * This will turn off the power to the specified PLL. Note this function does not currently check if
+ * the PLL is in use before powering it off so should be used with care.
+ *
+ * \param pll pll_sys or pll_usb
+ */
+void pll_deinit(PLL pll);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/pwm.h b/arkanoid/pico/hardware/pwm.h
new file mode 100644
index 0000000..f17ebe8
--- /dev/null
+++ b/arkanoid/pico/hardware/pwm.h
@@ -0,0 +1,559 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_PWM_H
+#define _HARDWARE_PWM_H
+
+#include "../pico.h"
+#include "structs/pwm.h"
+#include "regs/dreq.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PWM, Enable/disable assertions in the PWM module, type=bool, default=0, group=hardware_pwm
+#ifndef PARAM_ASSERTIONS_ENABLED_PWM
+#define PARAM_ASSERTIONS_ENABLED_PWM 0
+#endif
+
+/** \file pwm.h
+ * \defgroup hardware_pwm hardware_pwm
+ *
+ * Hardware Pulse Width Modulation (PWM) API
+ *
+ * The RP2040 PWM block has 8 identical slices. Each slice can drive two PWM output signals, or
+ * measure the frequency or duty cycle of an input signal. This gives a total of up to 16 controllable
+ * PWM outputs. All 30 GPIOs can be driven by the PWM block.
+ *
+ * The PWM hardware functions by continuously comparing the input value to a free-running counter. This produces a
+ * toggling output where the amount of time spent at the high output level is proportional to the input value. The fraction of
+ * time spent at the high signal level is known as the duty cycle of the signal.
+ *
+ * The default behaviour of a PWM slice is to count upward until the wrap value (\ref pwm_config_set_wrap) is reached, and then
+ * immediately wrap to 0. PWM slices also offer a phase-correct mode, where the counter starts to count downward after
+ * reaching TOP, until it reaches 0 again.
+ *
+ * \subsection pwm_example Example
+ * \addtogroup hardware_pwm
+ * \include hello_pwm.c
+ */
+
+/** \brief PWM Divider mode settings
+ * \ingroup hardware_pwm
+ *
+ */
+enum pwm_clkdiv_mode
+{
+ PWM_DIV_FREE_RUNNING = 0, ///< Free-running counting at rate dictated by fractional divider
+ PWM_DIV_B_HIGH = 1, ///< Fractional divider is gated by the PWM B pin
+ PWM_DIV_B_RISING = 2, ///< Fractional divider advances with each rising edge of the PWM B pin
+ PWM_DIV_B_FALLING = 3 ///< Fractional divider advances with each falling edge of the PWM B pin
+};
+
+enum pwm_chan
+{
+ PWM_CHAN_A = 0,
+ PWM_CHAN_B = 1
+};
+
+typedef struct {
+ uint32_t csr;
+ uint32_t div;
+ uint32_t top;
+} pwm_config;
+
+static inline void check_slice_num_param(__unused uint slice_num) {
+ valid_params_if(PWM, slice_num < NUM_PWM_SLICES);
+}
+
+/** \brief Determine the PWM slice that is attached to the specified GPIO
+ * \ingroup hardware_pwm
+ *
+ * \return The PWM slice number that controls the specified GPIO.
+ */
+static inline uint pwm_gpio_to_slice_num(uint gpio) {
+ valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
+ return (gpio >> 1u) & 7u;
+}
+
+/** \brief Determine the PWM channel that is attached to the specified GPIO.
+ * \ingroup hardware_pwm
+ *
+ * Each slice 0 to 7 has two channels, A and B.
+ *
+ * \return The PWM channel that controls the specified GPIO.
+ */
+static inline uint pwm_gpio_to_channel(uint gpio) {
+ valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
+ return gpio & 1u;
+}
+
+/** \brief Set phase correction in a PWM configuration
+ * \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param phase_correct true to set phase correct modulation, false to set trailing edge
+ *
+ * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached,
+ * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled.
+ */
+static inline void pwm_config_set_phase_correct(pwm_config *c, bool phase_correct) {
+ c->csr = (c->csr & ~PWM_CH0_CSR_PH_CORRECT_BITS)
+ | (bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB);
+}
+
+/** \brief Set clock divider in a PWM configuration
+ * \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param div Value to divide counting rate by. Must be greater than or equal to 1.
+ *
+ * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
+ * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
+ * before passing them on to the PWM counter.
+ */
+static inline void pwm_config_set_clkdiv(pwm_config *c, float div) {
+ c->div = (uint32_t)(div * (float)(1u << PWM_CH0_DIV_INT_LSB));
+}
+
+/** \brief Set PWM clock divider in a PWM configuration
+ * \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param div Integer value to reduce counting rate by. Must be greater than or equal to 1.
+ *
+ * If the divide mode is free-running, the PWM counter runs at clk_sys / div.
+ * Otherwise, the divider reduces the rate of events seen on the B pin input (level or edge)
+ * before passing them on to the PWM counter.
+ */
+static inline void pwm_config_set_clkdiv_int(pwm_config *c, uint div) {
+ c->div = div << PWM_CH0_DIV_INT_LSB;
+}
+
+/** \brief Set PWM counting mode in a PWM configuration
+ * \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param mode PWM divide/count mode
+ *
+ * Configure which event gates the operation of the fractional divider.
+ * The default is always-on (free-running PWM). Can also be configured to count on
+ * high level, rising edge or falling edge of the B pin input.
+ */
+static inline void pwm_config_set_clkdiv_mode(pwm_config *c, enum pwm_clkdiv_mode mode) {
+ valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING ||
+ mode == PWM_DIV_B_RISING ||
+ mode == PWM_DIV_B_HIGH ||
+ mode == PWM_DIV_B_FALLING);
+ c->csr = (c->csr & ~PWM_CH0_CSR_DIVMODE_BITS)
+ | (((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB);
+}
+
+/** \brief Set output polarity in a PWM configuration
+ * \ingroup hardware_pwm
+ *
+ * \param c PWM configuration struct to modify
+ * \param a true to invert output A
+ * \param b true to invert output B
+ */
+static inline void pwm_config_set_output_polarity(pwm_config *c, bool a, bool b) {
+ c->csr = (c->csr & ~(PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS))
+ | ((bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB) | (bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB));
+}
+
+/** \brief Set PWM counter wrap value in a PWM configuration
+ * \ingroup hardware_pwm
+ *
+ * Set the highest value the counter will reach before returning to 0. Also known as TOP.
+ *
+ * \param c PWM configuration struct to modify
+ * \param wrap Value to set wrap to
+ */
+static inline void pwm_config_set_wrap(pwm_config *c, uint16_t wrap) {
+ c->top = wrap;
+}
+
+/** \brief Initialise a PWM with settings from a configuration object
+ * \ingroup hardware_pwm
+ *
+ * Use the \ref pwm_get_default_config() function to initialise a config structure, make changes as
+ * needed using the pwm_config_* functions, then call this function to set up the PWM.
+ *
+ * \param slice_num PWM slice number
+ * \param c The configuration to use
+ * \param start If true the PWM will be started running once configured. If false you will need to start
+ * manually using \ref pwm_set_enabled() or \ref pwm_set_mask_enabled()
+ */
+static inline void pwm_init(uint slice_num, pwm_config *c, bool start) {
+ check_slice_num_param(slice_num);
+ pwm_hw->slice[slice_num].csr = 0;
+
+ pwm_hw->slice[slice_num].ctr = PWM_CH0_CTR_RESET;
+ pwm_hw->slice[slice_num].cc = PWM_CH0_CC_RESET;
+ pwm_hw->slice[slice_num].top = c->top;
+ pwm_hw->slice[slice_num].div = c->div;
+ pwm_hw->slice[slice_num].csr = c->csr | (bool_to_bit(start) << PWM_CH0_CSR_EN_LSB);
+}
+
+/** \brief Get a set of default values for PWM configuration
+ * \ingroup hardware_pwm
+ *
+ * PWM config is free-running at system clock speed, no phase correction, wrapping at 0xffff,
+ * with standard polarities for channels A and B.
+ *
+ * \return Set of default values.
+ */
+static inline pwm_config pwm_get_default_config(void) {
+ pwm_config c = {0, 0, 0};
+ pwm_config_set_phase_correct(&c, false);
+ pwm_config_set_clkdiv_int(&c, 1);
+ pwm_config_set_clkdiv_mode(&c, PWM_DIV_FREE_RUNNING);
+ pwm_config_set_output_polarity(&c, false, false);
+ pwm_config_set_wrap(&c, 0xffffu);
+ return c;
+}
+
+/** \brief Set the current PWM counter wrap value
+ * \ingroup hardware_pwm
+ *
+ * Set the highest value the counter will reach before returning to 0. Also
+ * known as TOP.
+ *
+ * The counter wrap value is double-buffered in hardware. This means that,
+ * when the PWM is running, a write to the counter wrap value does not take
+ * effect until after the next time the PWM slice wraps (or, in phase-correct
+ * mode, the next time the slice reaches 0). If the PWM is not running, the
+ * write is latched in immediately.
+ *
+ * \param slice_num PWM slice number
+ * \param wrap Value to set wrap to
+ */
+static inline void pwm_set_wrap(uint slice_num, uint16_t wrap) {
+ check_slice_num_param(slice_num);
+ pwm_hw->slice[slice_num].top = wrap;
+}
+
+/** \brief Set the current PWM counter compare value for one channel
+ * \ingroup hardware_pwm
+ *
+ * Set the value of the PWM counter compare value, for either channel A or channel B.
+ *
+ * The counter compare register is double-buffered in hardware. This means
+ * that, when the PWM is running, a write to the counter compare values does
+ * not take effect until the next time the PWM slice wraps (or, in
+ * phase-correct mode, the next time the slice reaches 0). If the PWM is not
+ * running, the write is latched in immediately.
+ *
+ * \param slice_num PWM slice number
+ * \param chan Which channel to update. 0 for A, 1 for B.
+ * \param level new level for the selected output
+ */
+static inline void pwm_set_chan_level(uint slice_num, uint chan, uint16_t level) {
+ check_slice_num_param(slice_num);
+ hw_write_masked(
+ &pwm_hw->slice[slice_num].cc,
+ ((uint)level) << (chan ? PWM_CH0_CC_B_LSB : PWM_CH0_CC_A_LSB),
+ chan ? PWM_CH0_CC_B_BITS : PWM_CH0_CC_A_BITS
+ );
+}
+
+/** \brief Set PWM counter compare values
+ * \ingroup hardware_pwm
+ *
+ * Set the value of the PWM counter compare values, A and B.
+ *
+ * The counter compare register is double-buffered in hardware. This means
+ * that, when the PWM is running, a write to the counter compare values does
+ * not take effect until the next time the PWM slice wraps (or, in
+ * phase-correct mode, the next time the slice reaches 0). If the PWM is not
+ * running, the write is latched in immediately.
+ *
+ * \param slice_num PWM slice number
+ * \param level_a Value to set compare A to. When the counter reaches this value the A output is deasserted
+ * \param level_b Value to set compare B to. When the counter reaches this value the B output is deasserted
+ */
+static inline void pwm_set_both_levels(uint slice_num, uint16_t level_a, uint16_t level_b) {
+ check_slice_num_param(slice_num);
+ pwm_hw->slice[slice_num].cc = (((uint)level_b) << PWM_CH0_CC_B_LSB) | (((uint)level_a) << PWM_CH0_CC_A_LSB);
+}
+
+/** \brief Helper function to set the PWM level for the slice and channel associated with a GPIO.
+ * \ingroup hardware_pwm
+ *
+ * Look up the correct slice (0 to 7) and channel (A or B) for a given GPIO, and update the corresponding
+ * counter compare field.
+ *
+ * This PWM slice should already have been configured and set running. Also be careful of multiple GPIOs
+ * mapping to the same slice and channel (if GPIOs have a difference of 16).
+ *
+ * The counter compare register is double-buffered in hardware. This means
+ * that, when the PWM is running, a write to the counter compare values does
+ * not take effect until the next time the PWM slice wraps (or, in
+ * phase-correct mode, the next time the slice reaches 0). If the PWM is not
+ * running, the write is latched in immediately.
+ *
+ * \param gpio GPIO to set level of
+ * \param level PWM level for this GPIO
+ */
+static inline void pwm_set_gpio_level(uint gpio, uint16_t level) {
+ valid_params_if(PWM, gpio < NUM_BANK0_GPIOS);
+ pwm_set_chan_level(pwm_gpio_to_slice_num(gpio), pwm_gpio_to_channel(gpio), level);
+}
+
+/** \brief Get PWM counter
+ * \ingroup hardware_pwm
+ *
+ * Get current value of PWM counter
+ *
+ * \param slice_num PWM slice number
+ * \return Current value of the PWM counter
+ */
+static inline uint16_t pwm_get_counter(uint slice_num) {
+ check_slice_num_param(slice_num);
+ return (uint16_t)(pwm_hw->slice[slice_num].ctr);
+}
+
+/** \brief Set PWM counter
+ * \ingroup hardware_pwm
+ *
+ * Set the value of the PWM counter
+ *
+ * \param slice_num PWM slice number
+ * \param c Value to set the PWM counter to
+ *
+ */
+static inline void pwm_set_counter(uint slice_num, uint16_t c) {
+ check_slice_num_param(slice_num);
+ pwm_hw->slice[slice_num].ctr = c;
+}
+
+/** \brief Advance PWM count
+ * \ingroup hardware_pwm
+ *
+ * Advance the phase of a running the counter by 1 count.
+ *
+ * This function will return once the increment is complete.
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_advance_count(uint slice_num) {
+ check_slice_num_param(slice_num);
+ hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_ADV_BITS);
+ while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_ADV_BITS) {
+ tight_loop_contents();
+ }
+}
+
+/** \brief Retard PWM count
+ * \ingroup hardware_pwm
+ *
+ * Retard the phase of a running counter by 1 count
+ *
+ * This function will return once the retardation is complete.
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_retard_count(uint slice_num) {
+ check_slice_num_param(slice_num);
+ hw_set_bits(&pwm_hw->slice[slice_num].csr, PWM_CH0_CSR_PH_RET_BITS);
+ while (pwm_hw->slice[slice_num].csr & PWM_CH0_CSR_PH_RET_BITS) {
+ tight_loop_contents();
+ }
+}
+
+/** \brief Set PWM clock divider using an 8:4 fractional value
+ * \ingroup hardware_pwm
+ *
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
+ *
+ * \param slice_num PWM slice number
+ * \param integer 8 bit integer part of the clock divider
+ * \param fract 4 bit fractional part of the clock divider
+ */
+static inline void pwm_set_clkdiv_int_frac(uint slice_num, uint8_t integer, uint8_t fract) {
+ check_slice_num_param(slice_num);
+ valid_params_if(PWM, fract < 16);
+ pwm_hw->slice[slice_num].div = (((uint)integer) << PWM_CH0_DIV_INT_LSB) | (((uint)fract) << PWM_CH0_DIV_FRAC_LSB);
+}
+
+/** \brief Set PWM clock divider
+ * \ingroup hardware_pwm
+ *
+ * Set the clock divider. Counter increment will be on sysclock divided by this value, taking into account the gating.
+ *
+ * \param slice_num PWM slice number
+ * \param divider Floating point clock divider, 1.f <= value < 256.f
+ */
+static inline void pwm_set_clkdiv(uint slice_num, float divider) {
+ check_slice_num_param(slice_num);
+ valid_params_if(PWM, divider >= 1.f && divider < 256.f);
+ uint8_t i = (uint8_t)divider;
+ uint8_t f = (uint8_t)((divider - i) * (0x01 << 4));
+ pwm_set_clkdiv_int_frac(slice_num, i, f);
+}
+
+/** \brief Set PWM output polarity
+ * \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ * \param a true to invert output A
+ * \param b true to invert output B
+ */
+static inline void pwm_set_output_polarity(uint slice_num, bool a, bool b) {
+ check_slice_num_param(slice_num);
+ hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(a) << PWM_CH0_CSR_A_INV_LSB | bool_to_bit(b) << PWM_CH0_CSR_B_INV_LSB,
+ PWM_CH0_CSR_A_INV_BITS | PWM_CH0_CSR_B_INV_BITS);
+}
+
+
+/** \brief Set PWM divider mode
+ * \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ * \param mode Required divider mode
+ */
+static inline void pwm_set_clkdiv_mode(uint slice_num, enum pwm_clkdiv_mode mode) {
+ check_slice_num_param(slice_num);
+ valid_params_if(PWM, mode == PWM_DIV_FREE_RUNNING ||
+ mode == PWM_DIV_B_RISING ||
+ mode == PWM_DIV_B_HIGH ||
+ mode == PWM_DIV_B_FALLING);
+ hw_write_masked(&pwm_hw->slice[slice_num].csr, ((uint)mode) << PWM_CH0_CSR_DIVMODE_LSB, PWM_CH0_CSR_DIVMODE_BITS);
+}
+
+/** \brief Set PWM phase correct on/off
+ * \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ * \param phase_correct true to set phase correct modulation, false to set trailing edge
+ *
+ * Setting phase control to true means that instead of wrapping back to zero when the wrap point is reached,
+ * the PWM starts counting back down. The output frequency is halved when phase-correct mode is enabled.
+ */
+static inline void pwm_set_phase_correct(uint slice_num, bool phase_correct) {
+ check_slice_num_param(slice_num);
+ hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(phase_correct) << PWM_CH0_CSR_PH_CORRECT_LSB, PWM_CH0_CSR_PH_CORRECT_BITS);
+}
+
+/** \brief Enable/Disable PWM
+ * \ingroup hardware_pwm
+ *
+ * When a PWM is disabled, it halts its counter, and the output pins are left
+ * high or low depending on exactly when the counter is halted. When
+ * re-enabled the PWM resumes immediately from where it left off.
+ *
+ * If the PWM's output pins need to be low when halted:
+ *
+ * - The counter compare can be set to zero whilst the PWM is enabled, and
+ * then the PWM disabled once both pins are seen to be low
+ *
+ * - The GPIO output overrides can be used to force the actual pins low
+ *
+ * - The PWM can be run for one cycle (i.e. enabled then immediately disabled)
+ * with a TOP of 0, count of 0 and counter compare of 0, to force the pins
+ * low when the PWM has already been halted. The same method can be used
+ * with a counter compare value of 1 to force a pin high.
+ *
+ * Note that, when disabled, the PWM can still be advanced one count at a time
+ * by pulsing the PH_ADV bit in its CSR. The output pins transition as though
+ * the PWM were enabled.
+ *
+ * \param slice_num PWM slice number
+ * \param enabled true to enable the specified PWM, false to disable.
+ */
+static inline void pwm_set_enabled(uint slice_num, bool enabled) {
+ check_slice_num_param(slice_num);
+ hw_write_masked(&pwm_hw->slice[slice_num].csr, bool_to_bit(enabled) << PWM_CH0_CSR_EN_LSB, PWM_CH0_CSR_EN_BITS);
+}
+
+/** \brief Enable/Disable multiple PWM slices simultaneously
+ * \ingroup hardware_pwm
+ *
+ * \param mask Bitmap of PWMs to enable/disable. Bits 0 to 7 enable slices 0-7 respectively
+ */
+static inline void pwm_set_mask_enabled(uint32_t mask) {
+ pwm_hw->en = mask;
+}
+
+/*! \brief Enable PWM instance interrupt
+ * \ingroup hardware_pwm
+ *
+ * Used to enable a single PWM instance interrupt.
+ *
+ * \param slice_num PWM block to enable/disable
+ * \param enabled true to enable, false to disable
+ */
+static inline void pwm_set_irq_enabled(uint slice_num, bool enabled) {
+ check_slice_num_param(slice_num);
+ if (enabled) {
+ hw_set_bits(&pwm_hw->inte, 1u << slice_num);
+ } else {
+ hw_clear_bits(&pwm_hw->inte, 1u << slice_num);
+ }
+}
+
+/*! \brief Enable multiple PWM instance interrupts
+ * \ingroup hardware_pwm
+ *
+ * Use this to enable multiple PWM interrupts at once.
+ *
+ * \param slice_mask Bitmask of all the blocks to enable/disable. Channel 0 = bit 0, channel 1 = bit 1 etc.
+ * \param enabled true to enable, false to disable
+ */
+static inline void pwm_set_irq_mask_enabled(uint32_t slice_mask, bool enabled) {
+ valid_params_if(PWM, slice_mask < 256);
+ if (enabled) {
+ hw_set_bits(&pwm_hw->inte, slice_mask);
+ } else {
+ hw_clear_bits(&pwm_hw->inte, slice_mask);
+ }
+}
+
+/*! \brief Clear a single PWM channel interrupt
+ * \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_clear_irq(uint slice_num) {
+ pwm_hw->intr = 1u << slice_num;
+}
+
+/*! \brief Get PWM interrupt status, raw
+ * \ingroup hardware_pwm
+ *
+ * \return Bitmask of all PWM interrupts currently set
+ */
+static inline uint32_t pwm_get_irq_status_mask(void) {
+ return pwm_hw->ints;
+}
+
+/*! \brief Force PWM interrupt
+ * \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ */
+static inline void pwm_force_irq(uint slice_num) {
+ pwm_hw->intf = 1u << slice_num;
+}
+
+/*! \brief Return the DREQ to use for pacing transfers to a particular PWM slice
+ * \ingroup hardware_pwm
+ *
+ * \param slice_num PWM slice number
+ */
+static inline uint pwm_get_dreq(uint slice_num) {
+ static_assert(DREQ_PWM_WRAP1 == DREQ_PWM_WRAP0 + 1, "");
+ static_assert(DREQ_PWM_WRAP7 == DREQ_PWM_WRAP0 + 7, "");
+ check_slice_num_param(slice_num);
+ return DREQ_PWM_WRAP0 + slice_num;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/regs/adc.h b/arkanoid/pico/hardware/regs/adc.h
new file mode 100644
index 0000000..47510be
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/adc.h
@@ -0,0 +1,314 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : ADC
+// Version : 2
+// Bus type : apb
+// Description : Control and data interface to SAR ADC
+// =============================================================================
+#ifndef HARDWARE_REGS_ADC_DEFINED
+#define HARDWARE_REGS_ADC_DEFINED
+// =============================================================================
+// Register : ADC_CS
+// Description : ADC Control and Status
+#define ADC_CS_OFFSET _u(0x00000000)
+#define ADC_CS_BITS _u(0x001f770f)
+#define ADC_CS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_RROBIN
+// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
+// disable.
+// Otherwise, the ADC will cycle through each enabled channel in a
+// round-robin fashion.
+// The first channel to be sampled will be the one currently
+// indicated by AINSEL.
+// AINSEL will be updated after each conversion with the
+// newly-selected channel.
+#define ADC_CS_RROBIN_RESET _u(0x00)
+#define ADC_CS_RROBIN_BITS _u(0x001f0000)
+#define ADC_CS_RROBIN_MSB _u(20)
+#define ADC_CS_RROBIN_LSB _u(16)
+#define ADC_CS_RROBIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_AINSEL
+// Description : Select analog mux input. Updated automatically in round-robin
+// mode.
+#define ADC_CS_AINSEL_RESET _u(0x0)
+#define ADC_CS_AINSEL_BITS _u(0x00007000)
+#define ADC_CS_AINSEL_MSB _u(14)
+#define ADC_CS_AINSEL_LSB _u(12)
+#define ADC_CS_AINSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_ERR_STICKY
+// Description : Some past ADC conversion encountered an error. Write 1 to
+// clear.
+#define ADC_CS_ERR_STICKY_RESET _u(0x0)
+#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
+#define ADC_CS_ERR_STICKY_MSB _u(10)
+#define ADC_CS_ERR_STICKY_LSB _u(10)
+#define ADC_CS_ERR_STICKY_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_ERR
+// Description : The most recent ADC conversion encountered an error; result is
+// undefined or noisy.
+#define ADC_CS_ERR_RESET _u(0x0)
+#define ADC_CS_ERR_BITS _u(0x00000200)
+#define ADC_CS_ERR_MSB _u(9)
+#define ADC_CS_ERR_LSB _u(9)
+#define ADC_CS_ERR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_READY
+// Description : 1 if the ADC is ready to start a new conversion. Implies any
+// previous conversion has completed.
+// 0 whilst conversion in progress.
+#define ADC_CS_READY_RESET _u(0x0)
+#define ADC_CS_READY_BITS _u(0x00000100)
+#define ADC_CS_READY_MSB _u(8)
+#define ADC_CS_READY_LSB _u(8)
+#define ADC_CS_READY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_START_MANY
+// Description : Continuously perform conversions whilst this bit is 1. A new
+// conversion will start immediately after the previous finishes.
+#define ADC_CS_START_MANY_RESET _u(0x0)
+#define ADC_CS_START_MANY_BITS _u(0x00000008)
+#define ADC_CS_START_MANY_MSB _u(3)
+#define ADC_CS_START_MANY_LSB _u(3)
+#define ADC_CS_START_MANY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_START_ONCE
+// Description : Start a single conversion. Self-clearing. Ignored if start_many
+// is asserted.
+#define ADC_CS_START_ONCE_RESET _u(0x0)
+#define ADC_CS_START_ONCE_BITS _u(0x00000004)
+#define ADC_CS_START_ONCE_MSB _u(2)
+#define ADC_CS_START_ONCE_LSB _u(2)
+#define ADC_CS_START_ONCE_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_TS_EN
+// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
+#define ADC_CS_TS_EN_RESET _u(0x0)
+#define ADC_CS_TS_EN_BITS _u(0x00000002)
+#define ADC_CS_TS_EN_MSB _u(1)
+#define ADC_CS_TS_EN_LSB _u(1)
+#define ADC_CS_TS_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_CS_EN
+// Description : Power on ADC and enable its clock.
+// 1 - enabled. 0 - disabled.
+#define ADC_CS_EN_RESET _u(0x0)
+#define ADC_CS_EN_BITS _u(0x00000001)
+#define ADC_CS_EN_MSB _u(0)
+#define ADC_CS_EN_LSB _u(0)
+#define ADC_CS_EN_ACCESS "RW"
+// =============================================================================
+// Register : ADC_RESULT
+// Description : Result of most recent ADC conversion
+#define ADC_RESULT_OFFSET _u(0x00000004)
+#define ADC_RESULT_BITS _u(0x00000fff)
+#define ADC_RESULT_RESET _u(0x00000000)
+#define ADC_RESULT_MSB _u(11)
+#define ADC_RESULT_LSB _u(0)
+#define ADC_RESULT_ACCESS "RO"
+// =============================================================================
+// Register : ADC_FCS
+// Description : FIFO control and status
+#define ADC_FCS_OFFSET _u(0x00000008)
+#define ADC_FCS_BITS _u(0x0f0f0f0f)
+#define ADC_FCS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_THRESH
+// Description : DREQ/IRQ asserted when level >= threshold
+#define ADC_FCS_THRESH_RESET _u(0x0)
+#define ADC_FCS_THRESH_BITS _u(0x0f000000)
+#define ADC_FCS_THRESH_MSB _u(27)
+#define ADC_FCS_THRESH_LSB _u(24)
+#define ADC_FCS_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_LEVEL
+// Description : The number of conversion results currently waiting in the FIFO
+#define ADC_FCS_LEVEL_RESET _u(0x0)
+#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
+#define ADC_FCS_LEVEL_MSB _u(19)
+#define ADC_FCS_LEVEL_LSB _u(16)
+#define ADC_FCS_LEVEL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_OVER
+// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
+#define ADC_FCS_OVER_RESET _u(0x0)
+#define ADC_FCS_OVER_BITS _u(0x00000800)
+#define ADC_FCS_OVER_MSB _u(11)
+#define ADC_FCS_OVER_LSB _u(11)
+#define ADC_FCS_OVER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_UNDER
+// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
+#define ADC_FCS_UNDER_RESET _u(0x0)
+#define ADC_FCS_UNDER_BITS _u(0x00000400)
+#define ADC_FCS_UNDER_MSB _u(10)
+#define ADC_FCS_UNDER_LSB _u(10)
+#define ADC_FCS_UNDER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_FULL
+// Description : None
+#define ADC_FCS_FULL_RESET _u(0x0)
+#define ADC_FCS_FULL_BITS _u(0x00000200)
+#define ADC_FCS_FULL_MSB _u(9)
+#define ADC_FCS_FULL_LSB _u(9)
+#define ADC_FCS_FULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_EMPTY
+// Description : None
+#define ADC_FCS_EMPTY_RESET _u(0x0)
+#define ADC_FCS_EMPTY_BITS _u(0x00000100)
+#define ADC_FCS_EMPTY_MSB _u(8)
+#define ADC_FCS_EMPTY_LSB _u(8)
+#define ADC_FCS_EMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_DREQ_EN
+// Description : If 1: assert DMA requests when FIFO contains data
+#define ADC_FCS_DREQ_EN_RESET _u(0x0)
+#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
+#define ADC_FCS_DREQ_EN_MSB _u(3)
+#define ADC_FCS_DREQ_EN_LSB _u(3)
+#define ADC_FCS_DREQ_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_ERR
+// Description : If 1: conversion error bit appears in the FIFO alongside the
+// result
+#define ADC_FCS_ERR_RESET _u(0x0)
+#define ADC_FCS_ERR_BITS _u(0x00000004)
+#define ADC_FCS_ERR_MSB _u(2)
+#define ADC_FCS_ERR_LSB _u(2)
+#define ADC_FCS_ERR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_SHIFT
+// Description : If 1: FIFO results are right-shifted to be one byte in size.
+// Enables DMA to byte buffers.
+#define ADC_FCS_SHIFT_RESET _u(0x0)
+#define ADC_FCS_SHIFT_BITS _u(0x00000002)
+#define ADC_FCS_SHIFT_MSB _u(1)
+#define ADC_FCS_SHIFT_LSB _u(1)
+#define ADC_FCS_SHIFT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_FCS_EN
+// Description : If 1: write result to the FIFO after each conversion.
+#define ADC_FCS_EN_RESET _u(0x0)
+#define ADC_FCS_EN_BITS _u(0x00000001)
+#define ADC_FCS_EN_MSB _u(0)
+#define ADC_FCS_EN_LSB _u(0)
+#define ADC_FCS_EN_ACCESS "RW"
+// =============================================================================
+// Register : ADC_FIFO
+// Description : Conversion result FIFO
+#define ADC_FIFO_OFFSET _u(0x0000000c)
+#define ADC_FIFO_BITS _u(0x00008fff)
+#define ADC_FIFO_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_FIFO_ERR
+// Description : 1 if this particular sample experienced a conversion error.
+// Remains in the same location if the sample is shifted.
+#define ADC_FIFO_ERR_RESET "-"
+#define ADC_FIFO_ERR_BITS _u(0x00008000)
+#define ADC_FIFO_ERR_MSB _u(15)
+#define ADC_FIFO_ERR_LSB _u(15)
+#define ADC_FIFO_ERR_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field : ADC_FIFO_VAL
+// Description : None
+#define ADC_FIFO_VAL_RESET "-"
+#define ADC_FIFO_VAL_BITS _u(0x00000fff)
+#define ADC_FIFO_VAL_MSB _u(11)
+#define ADC_FIFO_VAL_LSB _u(0)
+#define ADC_FIFO_VAL_ACCESS "RF"
+// =============================================================================
+// Register : ADC_DIV
+// Description : Clock divider. If non-zero, CS_START_MANY will start
+// conversions
+// at regular intervals rather than back-to-back.
+// The divider is reset when either of these fields are written.
+// Total period is 1 + INT + FRAC / 256
+#define ADC_DIV_OFFSET _u(0x00000010)
+#define ADC_DIV_BITS _u(0x00ffffff)
+#define ADC_DIV_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_DIV_INT
+// Description : Integer part of clock divisor.
+#define ADC_DIV_INT_RESET _u(0x0000)
+#define ADC_DIV_INT_BITS _u(0x00ffff00)
+#define ADC_DIV_INT_MSB _u(23)
+#define ADC_DIV_INT_LSB _u(8)
+#define ADC_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ADC_DIV_FRAC
+// Description : Fractional part of clock divisor. First-order delta-sigma.
+#define ADC_DIV_FRAC_RESET _u(0x00)
+#define ADC_DIV_FRAC_BITS _u(0x000000ff)
+#define ADC_DIV_FRAC_MSB _u(7)
+#define ADC_DIV_FRAC_LSB _u(0)
+#define ADC_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : ADC_INTR
+// Description : Raw Interrupts
+#define ADC_INTR_OFFSET _u(0x00000014)
+#define ADC_INTR_BITS _u(0x00000001)
+#define ADC_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_INTR_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+// This level can be programmed via the FCS_THRESH field.
+#define ADC_INTR_FIFO_RESET _u(0x0)
+#define ADC_INTR_FIFO_BITS _u(0x00000001)
+#define ADC_INTR_FIFO_MSB _u(0)
+#define ADC_INTR_FIFO_LSB _u(0)
+#define ADC_INTR_FIFO_ACCESS "RO"
+// =============================================================================
+// Register : ADC_INTE
+// Description : Interrupt Enable
+#define ADC_INTE_OFFSET _u(0x00000018)
+#define ADC_INTE_BITS _u(0x00000001)
+#define ADC_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_INTE_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+// This level can be programmed via the FCS_THRESH field.
+#define ADC_INTE_FIFO_RESET _u(0x0)
+#define ADC_INTE_FIFO_BITS _u(0x00000001)
+#define ADC_INTE_FIFO_MSB _u(0)
+#define ADC_INTE_FIFO_LSB _u(0)
+#define ADC_INTE_FIFO_ACCESS "RW"
+// =============================================================================
+// Register : ADC_INTF
+// Description : Interrupt Force
+#define ADC_INTF_OFFSET _u(0x0000001c)
+#define ADC_INTF_BITS _u(0x00000001)
+#define ADC_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_INTF_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+// This level can be programmed via the FCS_THRESH field.
+#define ADC_INTF_FIFO_RESET _u(0x0)
+#define ADC_INTF_FIFO_BITS _u(0x00000001)
+#define ADC_INTF_FIFO_MSB _u(0)
+#define ADC_INTF_FIFO_LSB _u(0)
+#define ADC_INTF_FIFO_ACCESS "RW"
+// =============================================================================
+// Register : ADC_INTS
+// Description : Interrupt status after masking & forcing
+#define ADC_INTS_OFFSET _u(0x00000020)
+#define ADC_INTS_BITS _u(0x00000001)
+#define ADC_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ADC_INTS_FIFO
+// Description : Triggered when the sample FIFO reaches a certain level.
+// This level can be programmed via the FCS_THRESH field.
+#define ADC_INTS_FIFO_RESET _u(0x0)
+#define ADC_INTS_FIFO_BITS _u(0x00000001)
+#define ADC_INTS_FIFO_MSB _u(0)
+#define ADC_INTS_FIFO_LSB _u(0)
+#define ADC_INTS_FIFO_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_ADC_DEFINED
diff --git a/arkanoid/pico/hardware/regs/addressmap.h b/arkanoid/pico/hardware/regs/addressmap.h
new file mode 100644
index 0000000..b3b5ac0
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/addressmap.h
@@ -0,0 +1,74 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _ADDRESSMAP_H_
+#define _ADDRESSMAP_H_
+
+#include "../platform_defs.h"
+
+// Register address offsets for atomic RMW aliases
+#define REG_ALIAS_RW_BITS (0x0u << 12u)
+#define REG_ALIAS_XOR_BITS (0x1u << 12u)
+#define REG_ALIAS_SET_BITS (0x2u << 12u)
+#define REG_ALIAS_CLR_BITS (0x3u << 12u)
+
+#define ROM_BASE _u(0x00000000)
+#define XIP_BASE _u(0x10000000)
+#define XIP_MAIN_BASE _u(0x10000000)
+#define XIP_NOALLOC_BASE _u(0x11000000)
+#define XIP_NOCACHE_BASE _u(0x12000000)
+#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000)
+#define XIP_CTRL_BASE _u(0x14000000)
+#define XIP_SRAM_BASE _u(0x15000000)
+#define XIP_SRAM_END _u(0x15004000)
+#define XIP_SSI_BASE _u(0x18000000)
+#define SRAM_BASE _u(0x20000000)
+#define SRAM_STRIPED_BASE _u(0x20000000)
+#define SRAM_STRIPED_END _u(0x20040000)
+#define SRAM4_BASE _u(0x20040000)
+#define SRAM5_BASE _u(0x20041000)
+#define SRAM_END _u(0x20042000)
+#define SRAM0_BASE _u(0x21000000)
+#define SRAM1_BASE _u(0x21010000)
+#define SRAM2_BASE _u(0x21020000)
+#define SRAM3_BASE _u(0x21030000)
+#define SYSINFO_BASE _u(0x40000000)
+#define SYSCFG_BASE _u(0x40004000)
+#define CLOCKS_BASE _u(0x40008000)
+#define RESETS_BASE _u(0x4000c000)
+#define PSM_BASE _u(0x40010000)
+#define IO_BANK0_BASE _u(0x40014000)
+#define IO_QSPI_BASE _u(0x40018000)
+#define PADS_BANK0_BASE _u(0x4001c000)
+#define PADS_QSPI_BASE _u(0x40020000)
+#define XOSC_BASE _u(0x40024000)
+#define PLL_SYS_BASE _u(0x40028000)
+#define PLL_USB_BASE _u(0x4002c000)
+#define BUSCTRL_BASE _u(0x40030000)
+#define UART0_BASE _u(0x40034000)
+#define UART1_BASE _u(0x40038000)
+#define SPI0_BASE _u(0x4003c000)
+#define SPI1_BASE _u(0x40040000)
+#define I2C0_BASE _u(0x40044000)
+#define I2C1_BASE _u(0x40048000)
+#define ADC_BASE _u(0x4004c000)
+#define PWM_BASE _u(0x40050000)
+#define TIMER_BASE _u(0x40054000)
+#define WATCHDOG_BASE _u(0x40058000)
+#define RTC_BASE _u(0x4005c000)
+#define ROSC_BASE _u(0x40060000)
+#define VREG_AND_CHIP_RESET_BASE _u(0x40064000)
+#define TBMAN_BASE _u(0x4006c000)
+#define DMA_BASE _u(0x50000000)
+#define USBCTRL_DPRAM_BASE _u(0x50100000)
+#define USBCTRL_BASE _u(0x50100000)
+#define USBCTRL_REGS_BASE _u(0x50110000)
+#define PIO0_BASE _u(0x50200000)
+#define PIO1_BASE _u(0x50300000)
+#define XIP_AUX_BASE _u(0x50400000)
+#define SIO_BASE _u(0xd0000000)
+#define PPB_BASE _u(0xe0000000)
+
+#endif // _ADDRESSMAP_H_
diff --git a/arkanoid/pico/hardware/regs/busctrl.h b/arkanoid/pico/hardware/regs/busctrl.h
new file mode 100644
index 0000000..8be0d86
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/busctrl.h
@@ -0,0 +1,324 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : BUSCTRL
+// Version : 1
+// Bus type : apb
+// Description : Register block for busfabric control signals and performance
+// counters
+// =============================================================================
+#ifndef HARDWARE_REGS_BUSCTRL_DEFINED
+#define HARDWARE_REGS_BUSCTRL_DEFINED
+// =============================================================================
+// Register : BUSCTRL_BUS_PRIORITY
+// Description : Set the priority of each master for bus arbitration.
+#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
+#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
+#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : BUSCTRL_BUS_PRIORITY_DMA_W
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
+#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : BUSCTRL_BUS_PRIORITY_DMA_R
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
+#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : BUSCTRL_BUS_PRIORITY_PROC1
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
+#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
+#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
+#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : BUSCTRL_BUS_PRIORITY_PROC0
+// Description : 0 - low priority, 1 - high priority
+#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
+#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
+#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
+// =============================================================================
+// Register : BUSCTRL_BUS_PRIORITY_ACK
+// Description : Bus priority acknowledge
+// Goes to 1 once all arbiters have registered the new global
+// priority levels.
+// Arbiters update their local priority when servicing a new
+// nonsequential access.
+// In normal circumstances this will happen almost immediately.
+#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
+#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
+#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
+#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
+#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
+#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
+// =============================================================================
+// Register : BUSCTRL_PERFCTR0
+// Description : Bus fabric performance counter 0
+// Busfabric saturating performance counter 0
+// Count some event signal from the busfabric arbiters.
+// Write any value to clear. Select an event to count using
+// PERFSEL0
+#define BUSCTRL_PERFCTR0_OFFSET _u(0x00000008)
+#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR0_MSB _u(23)
+#define BUSCTRL_PERFCTR0_LSB _u(0)
+#define BUSCTRL_PERFCTR0_ACCESS "WC"
+// =============================================================================
+// Register : BUSCTRL_PERFSEL0
+// Description : Bus fabric performance event select for PERFCTR0
+// Select an event for PERFCTR0. Count either contested accesses,
+// or all accesses, on a downstream port of the main crossbar.
+// 0x00 -> apb_contested
+// 0x01 -> apb
+// 0x02 -> fastperi_contested
+// 0x03 -> fastperi
+// 0x04 -> sram5_contested
+// 0x05 -> sram5
+// 0x06 -> sram4_contested
+// 0x07 -> sram4
+// 0x08 -> sram3_contested
+// 0x09 -> sram3
+// 0x0a -> sram2_contested
+// 0x0b -> sram2
+// 0x0c -> sram1_contested
+// 0x0d -> sram1
+// 0x0e -> sram0_contested
+// 0x0f -> sram0
+// 0x10 -> xip_main_contested
+// 0x11 -> xip_main
+// 0x12 -> rom_contested
+// 0x13 -> rom
+#define BUSCTRL_PERFSEL0_OFFSET _u(0x0000000c)
+#define BUSCTRL_PERFSEL0_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL0_MSB _u(4)
+#define BUSCTRL_PERFSEL0_LSB _u(0)
+#define BUSCTRL_PERFSEL0_ACCESS "RW"
+#define BUSCTRL_PERFSEL0_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL0_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL0_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL0_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL0_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL0_VALUE_ROM _u(0x13)
+// =============================================================================
+// Register : BUSCTRL_PERFCTR1
+// Description : Bus fabric performance counter 1
+// Busfabric saturating performance counter 1
+// Count some event signal from the busfabric arbiters.
+// Write any value to clear. Select an event to count using
+// PERFSEL1
+#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000010)
+#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR1_MSB _u(23)
+#define BUSCTRL_PERFCTR1_LSB _u(0)
+#define BUSCTRL_PERFCTR1_ACCESS "WC"
+// =============================================================================
+// Register : BUSCTRL_PERFSEL1
+// Description : Bus fabric performance event select for PERFCTR1
+// Select an event for PERFCTR1. Count either contested accesses,
+// or all accesses, on a downstream port of the main crossbar.
+// 0x00 -> apb_contested
+// 0x01 -> apb
+// 0x02 -> fastperi_contested
+// 0x03 -> fastperi
+// 0x04 -> sram5_contested
+// 0x05 -> sram5
+// 0x06 -> sram4_contested
+// 0x07 -> sram4
+// 0x08 -> sram3_contested
+// 0x09 -> sram3
+// 0x0a -> sram2_contested
+// 0x0b -> sram2
+// 0x0c -> sram1_contested
+// 0x0d -> sram1
+// 0x0e -> sram0_contested
+// 0x0f -> sram0
+// 0x10 -> xip_main_contested
+// 0x11 -> xip_main
+// 0x12 -> rom_contested
+// 0x13 -> rom
+#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000014)
+#define BUSCTRL_PERFSEL1_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL1_MSB _u(4)
+#define BUSCTRL_PERFSEL1_LSB _u(0)
+#define BUSCTRL_PERFSEL1_ACCESS "RW"
+#define BUSCTRL_PERFSEL1_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL1_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL1_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL1_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL1_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL1_VALUE_ROM _u(0x13)
+// =============================================================================
+// Register : BUSCTRL_PERFCTR2
+// Description : Bus fabric performance counter 2
+// Busfabric saturating performance counter 2
+// Count some event signal from the busfabric arbiters.
+// Write any value to clear. Select an event to count using
+// PERFSEL2
+#define BUSCTRL_PERFCTR2_OFFSET _u(0x00000018)
+#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR2_MSB _u(23)
+#define BUSCTRL_PERFCTR2_LSB _u(0)
+#define BUSCTRL_PERFCTR2_ACCESS "WC"
+// =============================================================================
+// Register : BUSCTRL_PERFSEL2
+// Description : Bus fabric performance event select for PERFCTR2
+// Select an event for PERFCTR2. Count either contested accesses,
+// or all accesses, on a downstream port of the main crossbar.
+// 0x00 -> apb_contested
+// 0x01 -> apb
+// 0x02 -> fastperi_contested
+// 0x03 -> fastperi
+// 0x04 -> sram5_contested
+// 0x05 -> sram5
+// 0x06 -> sram4_contested
+// 0x07 -> sram4
+// 0x08 -> sram3_contested
+// 0x09 -> sram3
+// 0x0a -> sram2_contested
+// 0x0b -> sram2
+// 0x0c -> sram1_contested
+// 0x0d -> sram1
+// 0x0e -> sram0_contested
+// 0x0f -> sram0
+// 0x10 -> xip_main_contested
+// 0x11 -> xip_main
+// 0x12 -> rom_contested
+// 0x13 -> rom
+#define BUSCTRL_PERFSEL2_OFFSET _u(0x0000001c)
+#define BUSCTRL_PERFSEL2_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL2_MSB _u(4)
+#define BUSCTRL_PERFSEL2_LSB _u(0)
+#define BUSCTRL_PERFSEL2_ACCESS "RW"
+#define BUSCTRL_PERFSEL2_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL2_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL2_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL2_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL2_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL2_VALUE_ROM _u(0x13)
+// =============================================================================
+// Register : BUSCTRL_PERFCTR3
+// Description : Bus fabric performance counter 3
+// Busfabric saturating performance counter 3
+// Count some event signal from the busfabric arbiters.
+// Write any value to clear. Select an event to count using
+// PERFSEL3
+#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000020)
+#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
+#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
+#define BUSCTRL_PERFCTR3_MSB _u(23)
+#define BUSCTRL_PERFCTR3_LSB _u(0)
+#define BUSCTRL_PERFCTR3_ACCESS "WC"
+// =============================================================================
+// Register : BUSCTRL_PERFSEL3
+// Description : Bus fabric performance event select for PERFCTR3
+// Select an event for PERFCTR3. Count either contested accesses,
+// or all accesses, on a downstream port of the main crossbar.
+// 0x00 -> apb_contested
+// 0x01 -> apb
+// 0x02 -> fastperi_contested
+// 0x03 -> fastperi
+// 0x04 -> sram5_contested
+// 0x05 -> sram5
+// 0x06 -> sram4_contested
+// 0x07 -> sram4
+// 0x08 -> sram3_contested
+// 0x09 -> sram3
+// 0x0a -> sram2_contested
+// 0x0b -> sram2
+// 0x0c -> sram1_contested
+// 0x0d -> sram1
+// 0x0e -> sram0_contested
+// 0x0f -> sram0
+// 0x10 -> xip_main_contested
+// 0x11 -> xip_main
+// 0x12 -> rom_contested
+// 0x13 -> rom
+#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000024)
+#define BUSCTRL_PERFSEL3_BITS _u(0x0000001f)
+#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
+#define BUSCTRL_PERFSEL3_MSB _u(4)
+#define BUSCTRL_PERFSEL3_LSB _u(0)
+#define BUSCTRL_PERFSEL3_ACCESS "RW"
+#define BUSCTRL_PERFSEL3_VALUE_APB_CONTESTED _u(0x00)
+#define BUSCTRL_PERFSEL3_VALUE_APB _u(0x01)
+#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_CONTESTED _u(0x02)
+#define BUSCTRL_PERFSEL3_VALUE_FASTPERI _u(0x03)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM5_CONTESTED _u(0x04)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM5 _u(0x05)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM4_CONTESTED _u(0x06)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM4 _u(0x07)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM3_CONTESTED _u(0x08)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM3 _u(0x09)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM2_CONTESTED _u(0x0a)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM2 _u(0x0b)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM1_CONTESTED _u(0x0c)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM1 _u(0x0d)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM0_CONTESTED _u(0x0e)
+#define BUSCTRL_PERFSEL3_VALUE_SRAM0 _u(0x0f)
+#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN_CONTESTED _u(0x10)
+#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN _u(0x11)
+#define BUSCTRL_PERFSEL3_VALUE_ROM_CONTESTED _u(0x12)
+#define BUSCTRL_PERFSEL3_VALUE_ROM _u(0x13)
+// =============================================================================
+#endif // HARDWARE_REGS_BUSCTRL_DEFINED
diff --git a/arkanoid/pico/hardware/regs/clocks.h b/arkanoid/pico/hardware/regs/clocks.h
new file mode 100644
index 0000000..c0d2eab
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/clocks.h
@@ -0,0 +1,2409 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : CLOCKS
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_CLOCKS_DEFINED
+#define HARDWARE_REGS_CLOCKS_DEFINED
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT0_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT0_CTRL_OFFSET _u(0x00000000)
+#define CLOCKS_CLK_GPOUT0_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT0_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+// cycle of the input clock
+// This can be done at any time
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_LSB _u(20)
+#define CLOCKS_CLK_GPOUT0_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+// clock
+// This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_LSB _u(16)
+#define CLOCKS_CLK_GPOUT0_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_LSB _u(12)
+#define CLOCKS_CLK_GPOUT0_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_GPOUT0_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_GPOUT0_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_sys
+// 0x1 -> clksrc_gpin0
+// 0x2 -> clksrc_gpin1
+// 0x3 -> clksrc_pll_usb
+// 0x4 -> rosc_clksrc
+// 0x5 -> xosc_clksrc
+// 0x6 -> clk_sys
+// 0x7 -> clk_usb
+// 0x8 -> clk_adc
+// 0x9 -> clk_rtc
+// 0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT0_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT0_DIV_OFFSET _u(0x00000004)
+#define CLOCKS_CLK_GPOUT0_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT0_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT0_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_GPOUT0_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT0_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_LSB _u(0)
+#define CLOCKS_CLK_GPOUT0_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT0_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_GPOUT0_SELECTED_OFFSET _u(0x00000008)
+#define CLOCKS_CLK_GPOUT0_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT0_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT0_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT0_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_GPOUT0_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT1_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT1_CTRL_OFFSET _u(0x0000000c)
+#define CLOCKS_CLK_GPOUT1_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT1_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+// cycle of the input clock
+// This can be done at any time
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_LSB _u(20)
+#define CLOCKS_CLK_GPOUT1_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+// clock
+// This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_LSB _u(16)
+#define CLOCKS_CLK_GPOUT1_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_LSB _u(12)
+#define CLOCKS_CLK_GPOUT1_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_GPOUT1_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_GPOUT1_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_sys
+// 0x1 -> clksrc_gpin0
+// 0x2 -> clksrc_gpin1
+// 0x3 -> clksrc_pll_usb
+// 0x4 -> rosc_clksrc
+// 0x5 -> xosc_clksrc
+// 0x6 -> clk_sys
+// 0x7 -> clk_usb
+// 0x8 -> clk_adc
+// 0x9 -> clk_rtc
+// 0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x4)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT1_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT1_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT1_DIV_OFFSET _u(0x00000010)
+#define CLOCKS_CLK_GPOUT1_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT1_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT1_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_GPOUT1_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT1_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_LSB _u(0)
+#define CLOCKS_CLK_GPOUT1_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT1_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_GPOUT1_SELECTED_OFFSET _u(0x00000014)
+#define CLOCKS_CLK_GPOUT1_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT1_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT1_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT1_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_GPOUT1_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT2_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT2_CTRL_OFFSET _u(0x00000018)
+#define CLOCKS_CLK_GPOUT2_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT2_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+// cycle of the input clock
+// This can be done at any time
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_LSB _u(20)
+#define CLOCKS_CLK_GPOUT2_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+// clock
+// This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_LSB _u(16)
+#define CLOCKS_CLK_GPOUT2_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_LSB _u(12)
+#define CLOCKS_CLK_GPOUT2_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_GPOUT2_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_GPOUT2_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_sys
+// 0x1 -> clksrc_gpin0
+// 0x2 -> clksrc_gpin1
+// 0x3 -> clksrc_pll_usb
+// 0x4 -> rosc_clksrc_ph
+// 0x5 -> xosc_clksrc
+// 0x6 -> clk_sys
+// 0x7 -> clk_usb
+// 0x8 -> clk_adc
+// 0x9 -> clk_rtc
+// 0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT2_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT2_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT2_DIV_OFFSET _u(0x0000001c)
+#define CLOCKS_CLK_GPOUT2_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT2_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT2_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_GPOUT2_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT2_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_LSB _u(0)
+#define CLOCKS_CLK_GPOUT2_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT2_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_GPOUT2_SELECTED_OFFSET _u(0x00000020)
+#define CLOCKS_CLK_GPOUT2_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT2_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT2_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT2_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_GPOUT2_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT3_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_GPOUT3_CTRL_OFFSET _u(0x00000024)
+#define CLOCKS_CLK_GPOUT3_CTRL_BITS _u(0x00131de0)
+#define CLOCKS_CLK_GPOUT3_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+// cycle of the input clock
+// This can be done at any time
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_LSB _u(20)
+#define CLOCKS_CLK_GPOUT3_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+// clock
+// This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_LSB _u(16)
+#define CLOCKS_CLK_GPOUT3_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_CTRL_DC50
+// Description : Enables duty cycle correction for odd divisors
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_BITS _u(0x00001000)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_MSB _u(12)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_LSB _u(12)
+#define CLOCKS_CLK_GPOUT3_CTRL_DC50_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_GPOUT3_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_GPOUT3_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_sys
+// 0x1 -> clksrc_gpin0
+// 0x2 -> clksrc_gpin1
+// 0x3 -> clksrc_pll_usb
+// 0x4 -> rosc_clksrc_ph
+// 0x5 -> xosc_clksrc
+// 0x6 -> clk_sys
+// 0x7 -> clk_usb
+// 0x8 -> clk_adc
+// 0x9 -> clk_rtc
+// 0xa -> clk_ref
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_BITS _u(0x000001e0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_MSB _u(8)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x3)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x4)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x5)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x6)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_USB _u(0x7)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_ADC _u(0x8)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_RTC _u(0x9)
+#define CLOCKS_CLK_GPOUT3_CTRL_AUXSRC_VALUE_CLK_REF _u(0xa)
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT3_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_GPOUT3_DIV_OFFSET _u(0x00000028)
+#define CLOCKS_CLK_GPOUT3_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT3_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_GPOUT3_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_GPOUT3_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_GPOUT3_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_LSB _u(0)
+#define CLOCKS_CLK_GPOUT3_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_GPOUT3_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_GPOUT3_SELECTED_OFFSET _u(0x0000002c)
+#define CLOCKS_CLK_GPOUT3_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_GPOUT3_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_GPOUT3_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_GPOUT3_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_GPOUT3_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_REF_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_REF_CTRL_OFFSET _u(0x00000030)
+#define CLOCKS_CLK_REF_CTRL_BITS _u(0x00000063)
+#define CLOCKS_CLK_REF_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_REF_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_usb
+// 0x1 -> clksrc_gpin0
+// 0x2 -> clksrc_gpin1
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_BITS _u(0x00000060)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_MSB _u(6)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x1)
+#define CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_REF_CTRL_SRC
+// Description : Selects the clock source glitchlessly, can be changed
+// on-the-fly
+// 0x0 -> rosc_clksrc_ph
+// 0x1 -> clksrc_clk_ref_aux
+// 0x2 -> xosc_clksrc
+#define CLOCKS_CLK_REF_CTRL_SRC_RESET "-"
+#define CLOCKS_CLK_REF_CTRL_SRC_BITS _u(0x00000003)
+#define CLOCKS_CLK_REF_CTRL_SRC_MSB _u(1)
+#define CLOCKS_CLK_REF_CTRL_SRC_LSB _u(0)
+#define CLOCKS_CLK_REF_CTRL_SRC_ACCESS "RW"
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_ROSC_CLKSRC_PH _u(0x0)
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX _u(0x1)
+#define CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC _u(0x2)
+// =============================================================================
+// Register : CLOCKS_CLK_REF_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_REF_DIV_OFFSET _u(0x00000034)
+#define CLOCKS_CLK_REF_DIV_BITS _u(0x00000300)
+#define CLOCKS_CLK_REF_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_REF_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_REF_DIV_INT_RESET _u(0x1)
+#define CLOCKS_CLK_REF_DIV_INT_BITS _u(0x00000300)
+#define CLOCKS_CLK_REF_DIV_INT_MSB _u(9)
+#define CLOCKS_CLK_REF_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_REF_DIV_INT_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_REF_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// The glitchless multiplexer does not switch instantaneously (to
+// avoid glitches), so software should poll this register to wait
+// for the switch to complete. This register contains one decoded
+// bit for each of the clock sources enumerated in the CTRL SRC
+// field. At most one of these bits will be set at any time,
+// indicating that clock is currently present at the output of the
+// glitchless mux. Whilst switching is in progress, this register
+// may briefly show all-0s.
+#define CLOCKS_CLK_REF_SELECTED_OFFSET _u(0x00000038)
+#define CLOCKS_CLK_REF_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_REF_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_REF_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_REF_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_REF_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_SYS_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_SYS_CTRL_OFFSET _u(0x0000003c)
+#define CLOCKS_CLK_SYS_CTRL_BITS _u(0x000000e1)
+#define CLOCKS_CLK_SYS_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_sys
+// 0x1 -> clksrc_pll_usb
+// 0x2 -> rosc_clksrc
+// 0x3 -> xosc_clksrc
+// 0x4 -> clksrc_gpin0
+// 0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x1)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_ROSC_CLKSRC _u(0x2)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_CTRL_SRC
+// Description : Selects the clock source glitchlessly, can be changed
+// on-the-fly
+// 0x0 -> clk_ref
+// 0x1 -> clksrc_clk_sys_aux
+#define CLOCKS_CLK_SYS_CTRL_SRC_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_BITS _u(0x00000001)
+#define CLOCKS_CLK_SYS_CTRL_SRC_MSB _u(0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_LSB _u(0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_ACCESS "RW"
+#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLK_REF _u(0x0)
+#define CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX _u(0x1)
+// =============================================================================
+// Register : CLOCKS_CLK_SYS_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_SYS_DIV_OFFSET _u(0x00000040)
+#define CLOCKS_CLK_SYS_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_SYS_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_SYS_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_SYS_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_SYS_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_SYS_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_SYS_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_SYS_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_SYS_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_SYS_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_SYS_DIV_FRAC_LSB _u(0)
+#define CLOCKS_CLK_SYS_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_SYS_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// The glitchless multiplexer does not switch instantaneously (to
+// avoid glitches), so software should poll this register to wait
+// for the switch to complete. This register contains one decoded
+// bit for each of the clock sources enumerated in the CTRL SRC
+// field. At most one of these bits will be set at any time,
+// indicating that clock is currently present at the output of the
+// glitchless mux. Whilst switching is in progress, this register
+// may briefly show all-0s.
+#define CLOCKS_CLK_SYS_SELECTED_OFFSET _u(0x00000044)
+#define CLOCKS_CLK_SYS_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_SYS_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_SYS_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_SYS_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_SYS_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_PERI_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_PERI_CTRL_OFFSET _u(0x00000048)
+#define CLOCKS_CLK_PERI_CTRL_BITS _u(0x00000ce0)
+#define CLOCKS_CLK_PERI_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_PERI_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_PERI_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_PERI_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_PERI_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_PERI_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_PERI_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_PERI_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_PERI_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clk_sys
+// 0x1 -> clksrc_pll_sys
+// 0x2 -> clksrc_pll_usb
+// 0x3 -> rosc_clksrc_ph
+// 0x4 -> xosc_clksrc
+// 0x5 -> clksrc_gpin0
+// 0x6 -> clksrc_gpin1
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS _u(0x0)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x2)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x3)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x4)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x5)
+#define CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x6)
+// =============================================================================
+// Register : CLOCKS_CLK_PERI_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_PERI_SELECTED_OFFSET _u(0x00000050)
+#define CLOCKS_CLK_PERI_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_PERI_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_PERI_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_PERI_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_PERI_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_USB_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_USB_CTRL_OFFSET _u(0x00000054)
+#define CLOCKS_CLK_USB_CTRL_BITS _u(0x00130ce0)
+#define CLOCKS_CLK_USB_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_USB_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+// cycle of the input clock
+// This can be done at any time
+#define CLOCKS_CLK_USB_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_LSB _u(20)
+#define CLOCKS_CLK_USB_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_USB_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+// clock
+// This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_USB_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_USB_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_USB_CTRL_PHASE_LSB _u(16)
+#define CLOCKS_CLK_USB_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_USB_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_USB_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_USB_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_USB_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_USB_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_USB_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_USB_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_USB_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_USB_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_usb
+// 0x1 -> clksrc_pll_sys
+// 0x2 -> rosc_clksrc_ph
+// 0x3 -> xosc_clksrc
+// 0x4 -> clksrc_gpin0
+// 0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
+// =============================================================================
+// Register : CLOCKS_CLK_USB_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_USB_DIV_OFFSET _u(0x00000058)
+#define CLOCKS_CLK_USB_DIV_BITS _u(0x00000300)
+#define CLOCKS_CLK_USB_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_USB_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_USB_DIV_INT_RESET _u(0x1)
+#define CLOCKS_CLK_USB_DIV_INT_BITS _u(0x00000300)
+#define CLOCKS_CLK_USB_DIV_INT_MSB _u(9)
+#define CLOCKS_CLK_USB_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_USB_DIV_INT_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_USB_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_USB_SELECTED_OFFSET _u(0x0000005c)
+#define CLOCKS_CLK_USB_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_USB_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_USB_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_USB_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_USB_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_ADC_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_ADC_CTRL_OFFSET _u(0x00000060)
+#define CLOCKS_CLK_ADC_CTRL_BITS _u(0x00130ce0)
+#define CLOCKS_CLK_ADC_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_ADC_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+// cycle of the input clock
+// This can be done at any time
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_LSB _u(20)
+#define CLOCKS_CLK_ADC_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_ADC_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+// clock
+// This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_ADC_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_LSB _u(16)
+#define CLOCKS_CLK_ADC_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_ADC_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_ADC_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_ADC_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_ADC_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_ADC_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_ADC_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_ADC_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_ADC_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_usb
+// 0x1 -> clksrc_pll_sys
+// 0x2 -> rosc_clksrc_ph
+// 0x3 -> xosc_clksrc
+// 0x4 -> clksrc_gpin0
+// 0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
+// =============================================================================
+// Register : CLOCKS_CLK_ADC_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_ADC_DIV_OFFSET _u(0x00000064)
+#define CLOCKS_CLK_ADC_DIV_BITS _u(0x00000300)
+#define CLOCKS_CLK_ADC_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_ADC_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_ADC_DIV_INT_RESET _u(0x1)
+#define CLOCKS_CLK_ADC_DIV_INT_BITS _u(0x00000300)
+#define CLOCKS_CLK_ADC_DIV_INT_MSB _u(9)
+#define CLOCKS_CLK_ADC_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_ADC_DIV_INT_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_ADC_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_ADC_SELECTED_OFFSET _u(0x00000068)
+#define CLOCKS_CLK_ADC_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_ADC_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_ADC_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_ADC_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_ADC_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_RTC_CTRL
+// Description : Clock control, can be changed on-the-fly (except for auxsrc)
+#define CLOCKS_CLK_RTC_CTRL_OFFSET _u(0x0000006c)
+#define CLOCKS_CLK_RTC_CTRL_BITS _u(0x00130ce0)
+#define CLOCKS_CLK_RTC_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_RTC_CTRL_NUDGE
+// Description : An edge on this signal shifts the phase of the output by 1
+// cycle of the input clock
+// This can be done at any time
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_BITS _u(0x00100000)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_MSB _u(20)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_LSB _u(20)
+#define CLOCKS_CLK_RTC_CTRL_NUDGE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_RTC_CTRL_PHASE
+// Description : This delays the enable signal by up to 3 cycles of the input
+// clock
+// This must be set before the clock is enabled to have any effect
+#define CLOCKS_CLK_RTC_CTRL_PHASE_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_BITS _u(0x00030000)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_MSB _u(17)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_LSB _u(16)
+#define CLOCKS_CLK_RTC_CTRL_PHASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_RTC_CTRL_ENABLE
+// Description : Starts and stops the clock generator cleanly
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_BITS _u(0x00000800)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_MSB _u(11)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_LSB _u(11)
+#define CLOCKS_CLK_RTC_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_RTC_CTRL_KILL
+// Description : Asynchronously kills the clock generator
+#define CLOCKS_CLK_RTC_CTRL_KILL_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_KILL_BITS _u(0x00000400)
+#define CLOCKS_CLK_RTC_CTRL_KILL_MSB _u(10)
+#define CLOCKS_CLK_RTC_CTRL_KILL_LSB _u(10)
+#define CLOCKS_CLK_RTC_CTRL_KILL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_RTC_CTRL_AUXSRC
+// Description : Selects the auxiliary clock source, will glitch when switching
+// 0x0 -> clksrc_pll_usb
+// 0x1 -> clksrc_pll_sys
+// 0x2 -> rosc_clksrc_ph
+// 0x3 -> xosc_clksrc
+// 0x4 -> clksrc_gpin0
+// 0x5 -> clksrc_gpin1
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_RESET _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_BITS _u(0x000000e0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_MSB _u(7)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_LSB _u(5)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_ACCESS "RW"
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB _u(0x0)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS _u(0x1)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_ROSC_CLKSRC_PH _u(0x2)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_XOSC_CLKSRC _u(0x3)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN0 _u(0x4)
+#define CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_GPIN1 _u(0x5)
+// =============================================================================
+// Register : CLOCKS_CLK_RTC_DIV
+// Description : Clock divisor, can be changed on-the-fly
+#define CLOCKS_CLK_RTC_DIV_OFFSET _u(0x00000070)
+#define CLOCKS_CLK_RTC_DIV_BITS _u(0xffffffff)
+#define CLOCKS_CLK_RTC_DIV_RESET _u(0x00000100)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_RTC_DIV_INT
+// Description : Integer component of the divisor, 0 -> divide by 2^16
+#define CLOCKS_CLK_RTC_DIV_INT_RESET _u(0x000001)
+#define CLOCKS_CLK_RTC_DIV_INT_BITS _u(0xffffff00)
+#define CLOCKS_CLK_RTC_DIV_INT_MSB _u(31)
+#define CLOCKS_CLK_RTC_DIV_INT_LSB _u(8)
+#define CLOCKS_CLK_RTC_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_RTC_DIV_FRAC
+// Description : Fractional component of the divisor
+#define CLOCKS_CLK_RTC_DIV_FRAC_RESET _u(0x00)
+#define CLOCKS_CLK_RTC_DIV_FRAC_BITS _u(0x000000ff)
+#define CLOCKS_CLK_RTC_DIV_FRAC_MSB _u(7)
+#define CLOCKS_CLK_RTC_DIV_FRAC_LSB _u(0)
+#define CLOCKS_CLK_RTC_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_RTC_SELECTED
+// Description : Indicates which SRC is currently selected by the glitchless mux
+// (one-hot).
+// This slice does not have a glitchless mux (only the AUX_SRC
+// field is present, not SRC) so this register is hardwired to
+// 0x1.
+#define CLOCKS_CLK_RTC_SELECTED_OFFSET _u(0x00000074)
+#define CLOCKS_CLK_RTC_SELECTED_BITS _u(0xffffffff)
+#define CLOCKS_CLK_RTC_SELECTED_RESET _u(0x00000001)
+#define CLOCKS_CLK_RTC_SELECTED_MSB _u(31)
+#define CLOCKS_CLK_RTC_SELECTED_LSB _u(0)
+#define CLOCKS_CLK_RTC_SELECTED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_CLK_SYS_RESUS_CTRL
+// Description : None
+#define CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET _u(0x00000078)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_BITS _u(0x000111ff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_RESET _u(0x000000ff)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR
+// Description : For clearing the resus after the fault that triggered it has
+// been corrected
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_BITS _u(0x00010000)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_MSB _u(16)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_LSB _u(16)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_CLEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_RESUS_CTRL_FRCE
+// Description : Force a resus, for test purposes only
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_BITS _u(0x00001000)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_MSB _u(12)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_LSB _u(12)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_FRCE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE
+// Description : Enable resus
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_BITS _u(0x00000100)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_MSB _u(8)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_LSB _u(8)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT
+// Description : This is expressed as a number of clk_ref cycles
+// and must be >= 2x clk_ref_freq/min_clk_tst_freq
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_RESET _u(0xff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_BITS _u(0x000000ff)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_MSB _u(7)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_LSB _u(0)
+#define CLOCKS_CLK_SYS_RESUS_CTRL_TIMEOUT_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_CLK_SYS_RESUS_STATUS
+// Description : None
+#define CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET _u(0x0000007c)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_BITS _u(0x00000001)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED
+// Description : Clock has been resuscitated, correct the error then send
+// ctrl_clear=1
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_RESET _u(0x0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_BITS _u(0x00000001)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_MSB _u(0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_LSB _u(0)
+#define CLOCKS_CLK_SYS_RESUS_STATUS_RESUSSED_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_FC0_REF_KHZ
+// Description : Reference clock frequency in kHz
+#define CLOCKS_FC0_REF_KHZ_OFFSET _u(0x00000080)
+#define CLOCKS_FC0_REF_KHZ_BITS _u(0x000fffff)
+#define CLOCKS_FC0_REF_KHZ_RESET _u(0x00000000)
+#define CLOCKS_FC0_REF_KHZ_MSB _u(19)
+#define CLOCKS_FC0_REF_KHZ_LSB _u(0)
+#define CLOCKS_FC0_REF_KHZ_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_FC0_MIN_KHZ
+// Description : Minimum pass frequency in kHz. This is optional. Set to 0 if
+// you are not using the pass/fail flags
+#define CLOCKS_FC0_MIN_KHZ_OFFSET _u(0x00000084)
+#define CLOCKS_FC0_MIN_KHZ_BITS _u(0x01ffffff)
+#define CLOCKS_FC0_MIN_KHZ_RESET _u(0x00000000)
+#define CLOCKS_FC0_MIN_KHZ_MSB _u(24)
+#define CLOCKS_FC0_MIN_KHZ_LSB _u(0)
+#define CLOCKS_FC0_MIN_KHZ_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_FC0_MAX_KHZ
+// Description : Maximum pass frequency in kHz. This is optional. Set to
+// 0x1ffffff if you are not using the pass/fail flags
+#define CLOCKS_FC0_MAX_KHZ_OFFSET _u(0x00000088)
+#define CLOCKS_FC0_MAX_KHZ_BITS _u(0x01ffffff)
+#define CLOCKS_FC0_MAX_KHZ_RESET _u(0x01ffffff)
+#define CLOCKS_FC0_MAX_KHZ_MSB _u(24)
+#define CLOCKS_FC0_MAX_KHZ_LSB _u(0)
+#define CLOCKS_FC0_MAX_KHZ_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_FC0_DELAY
+// Description : Delays the start of frequency counting to allow the mux to
+// settle
+// Delay is measured in multiples of the reference clock period
+#define CLOCKS_FC0_DELAY_OFFSET _u(0x0000008c)
+#define CLOCKS_FC0_DELAY_BITS _u(0x00000007)
+#define CLOCKS_FC0_DELAY_RESET _u(0x00000001)
+#define CLOCKS_FC0_DELAY_MSB _u(2)
+#define CLOCKS_FC0_DELAY_LSB _u(0)
+#define CLOCKS_FC0_DELAY_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_FC0_INTERVAL
+// Description : The test interval is 0.98us * 2**interval, but let's call it
+// 1us * 2**interval
+// The default gives a test interval of 250us
+#define CLOCKS_FC0_INTERVAL_OFFSET _u(0x00000090)
+#define CLOCKS_FC0_INTERVAL_BITS _u(0x0000000f)
+#define CLOCKS_FC0_INTERVAL_RESET _u(0x00000008)
+#define CLOCKS_FC0_INTERVAL_MSB _u(3)
+#define CLOCKS_FC0_INTERVAL_LSB _u(0)
+#define CLOCKS_FC0_INTERVAL_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_FC0_SRC
+// Description : Clock sent to frequency counter, set to 0 when not required
+// Writing to this register initiates the frequency count
+// 0x00 -> NULL
+// 0x01 -> pll_sys_clksrc_primary
+// 0x02 -> pll_usb_clksrc_primary
+// 0x03 -> rosc_clksrc
+// 0x04 -> rosc_clksrc_ph
+// 0x05 -> xosc_clksrc
+// 0x06 -> clksrc_gpin0
+// 0x07 -> clksrc_gpin1
+// 0x08 -> clk_ref
+// 0x09 -> clk_sys
+// 0x0a -> clk_peri
+// 0x0b -> clk_usb
+// 0x0c -> clk_adc
+// 0x0d -> clk_rtc
+#define CLOCKS_FC0_SRC_OFFSET _u(0x00000094)
+#define CLOCKS_FC0_SRC_BITS _u(0x000000ff)
+#define CLOCKS_FC0_SRC_RESET _u(0x00000000)
+#define CLOCKS_FC0_SRC_MSB _u(7)
+#define CLOCKS_FC0_SRC_LSB _u(0)
+#define CLOCKS_FC0_SRC_ACCESS "RW"
+#define CLOCKS_FC0_SRC_VALUE_NULL _u(0x00)
+#define CLOCKS_FC0_SRC_VALUE_PLL_SYS_CLKSRC_PRIMARY _u(0x01)
+#define CLOCKS_FC0_SRC_VALUE_PLL_USB_CLKSRC_PRIMARY _u(0x02)
+#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC _u(0x03)
+#define CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC_PH _u(0x04)
+#define CLOCKS_FC0_SRC_VALUE_XOSC_CLKSRC _u(0x05)
+#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN0 _u(0x06)
+#define CLOCKS_FC0_SRC_VALUE_CLKSRC_GPIN1 _u(0x07)
+#define CLOCKS_FC0_SRC_VALUE_CLK_REF _u(0x08)
+#define CLOCKS_FC0_SRC_VALUE_CLK_SYS _u(0x09)
+#define CLOCKS_FC0_SRC_VALUE_CLK_PERI _u(0x0a)
+#define CLOCKS_FC0_SRC_VALUE_CLK_USB _u(0x0b)
+#define CLOCKS_FC0_SRC_VALUE_CLK_ADC _u(0x0c)
+#define CLOCKS_FC0_SRC_VALUE_CLK_RTC _u(0x0d)
+// =============================================================================
+// Register : CLOCKS_FC0_STATUS
+// Description : Frequency counter status
+#define CLOCKS_FC0_STATUS_OFFSET _u(0x00000098)
+#define CLOCKS_FC0_STATUS_BITS _u(0x11111111)
+#define CLOCKS_FC0_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_DIED
+// Description : Test clock stopped during test
+#define CLOCKS_FC0_STATUS_DIED_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_DIED_BITS _u(0x10000000)
+#define CLOCKS_FC0_STATUS_DIED_MSB _u(28)
+#define CLOCKS_FC0_STATUS_DIED_LSB _u(28)
+#define CLOCKS_FC0_STATUS_DIED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_FAST
+// Description : Test clock faster than expected, only valid when status_done=1
+#define CLOCKS_FC0_STATUS_FAST_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_FAST_BITS _u(0x01000000)
+#define CLOCKS_FC0_STATUS_FAST_MSB _u(24)
+#define CLOCKS_FC0_STATUS_FAST_LSB _u(24)
+#define CLOCKS_FC0_STATUS_FAST_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_SLOW
+// Description : Test clock slower than expected, only valid when status_done=1
+#define CLOCKS_FC0_STATUS_SLOW_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_SLOW_BITS _u(0x00100000)
+#define CLOCKS_FC0_STATUS_SLOW_MSB _u(20)
+#define CLOCKS_FC0_STATUS_SLOW_LSB _u(20)
+#define CLOCKS_FC0_STATUS_SLOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_FAIL
+// Description : Test failed
+#define CLOCKS_FC0_STATUS_FAIL_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_FAIL_BITS _u(0x00010000)
+#define CLOCKS_FC0_STATUS_FAIL_MSB _u(16)
+#define CLOCKS_FC0_STATUS_FAIL_LSB _u(16)
+#define CLOCKS_FC0_STATUS_FAIL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_WAITING
+// Description : Waiting for test clock to start
+#define CLOCKS_FC0_STATUS_WAITING_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_WAITING_BITS _u(0x00001000)
+#define CLOCKS_FC0_STATUS_WAITING_MSB _u(12)
+#define CLOCKS_FC0_STATUS_WAITING_LSB _u(12)
+#define CLOCKS_FC0_STATUS_WAITING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_RUNNING
+// Description : Test running
+#define CLOCKS_FC0_STATUS_RUNNING_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_RUNNING_BITS _u(0x00000100)
+#define CLOCKS_FC0_STATUS_RUNNING_MSB _u(8)
+#define CLOCKS_FC0_STATUS_RUNNING_LSB _u(8)
+#define CLOCKS_FC0_STATUS_RUNNING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_DONE
+// Description : Test complete
+#define CLOCKS_FC0_STATUS_DONE_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_DONE_BITS _u(0x00000010)
+#define CLOCKS_FC0_STATUS_DONE_MSB _u(4)
+#define CLOCKS_FC0_STATUS_DONE_LSB _u(4)
+#define CLOCKS_FC0_STATUS_DONE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_STATUS_PASS
+// Description : Test passed
+#define CLOCKS_FC0_STATUS_PASS_RESET _u(0x0)
+#define CLOCKS_FC0_STATUS_PASS_BITS _u(0x00000001)
+#define CLOCKS_FC0_STATUS_PASS_MSB _u(0)
+#define CLOCKS_FC0_STATUS_PASS_LSB _u(0)
+#define CLOCKS_FC0_STATUS_PASS_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_FC0_RESULT
+// Description : Result of frequency measurement, only valid when status_done=1
+#define CLOCKS_FC0_RESULT_OFFSET _u(0x0000009c)
+#define CLOCKS_FC0_RESULT_BITS _u(0x3fffffff)
+#define CLOCKS_FC0_RESULT_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_RESULT_KHZ
+// Description : None
+#define CLOCKS_FC0_RESULT_KHZ_RESET _u(0x0000000)
+#define CLOCKS_FC0_RESULT_KHZ_BITS _u(0x3fffffe0)
+#define CLOCKS_FC0_RESULT_KHZ_MSB _u(29)
+#define CLOCKS_FC0_RESULT_KHZ_LSB _u(5)
+#define CLOCKS_FC0_RESULT_KHZ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_FC0_RESULT_FRAC
+// Description : None
+#define CLOCKS_FC0_RESULT_FRAC_RESET _u(0x00)
+#define CLOCKS_FC0_RESULT_FRAC_BITS _u(0x0000001f)
+#define CLOCKS_FC0_RESULT_FRAC_MSB _u(4)
+#define CLOCKS_FC0_RESULT_FRAC_LSB _u(0)
+#define CLOCKS_FC0_RESULT_FRAC_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_WAKE_EN0
+// Description : enable clock in wake mode
+#define CLOCKS_WAKE_EN0_OFFSET _u(0x000000a0)
+#define CLOCKS_WAKE_EN0_BITS _u(0xffffffff)
+#define CLOCKS_WAKE_EN0_RESET _u(0xffffffff)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM3
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_MSB _u(31)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_LSB _u(31)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM2
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_MSB _u(30)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_LSB _u(30)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_MSB _u(29)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_LSB _u(29)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_SRAM0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_MSB _u(28)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_LSB _u(28)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS _u(0x08000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_MSB _u(27)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_LSB _u(27)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS _u(0x04000000)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_MSB _u(26)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_LSB _u(26)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_SPI0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS _u(0x02000000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_MSB _u(25)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_LSB _u(25)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_PERI_SPI0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS _u(0x01000000)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_MSB _u(24)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_LSB _u(24)
+#define CLOCKS_WAKE_EN0_CLK_PERI_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_SIO
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS _u(0x00800000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_MSB _u(23)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_LSB _u(23)
+#define CLOCKS_WAKE_EN0_CLK_SYS_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_RTC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_BITS _u(0x00400000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_MSB _u(22)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_LSB _u(22)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_RTC_RTC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_BITS _u(0x00200000)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_MSB _u(21)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_LSB _u(21)
+#define CLOCKS_WAKE_EN0_CLK_RTC_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROSC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS _u(0x00100000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_MSB _u(20)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_LSB _u(20)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_ROM
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS _u(0x00080000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_MSB _u(19)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_LSB _u(19)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_RESETS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS _u(0x00040000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_MSB _u(18)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_LSB _u(18)
+#define CLOCKS_WAKE_EN0_CLK_SYS_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_PWM
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_BITS _u(0x00020000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_MSB _u(17)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_LSB _u(17)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_PSM
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS _u(0x00010000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_MSB _u(16)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_LSB _u(16)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PSM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_MSB _u(15)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_LSB _u(15)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_MSB _u(14)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_LSB _u(14)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_BITS _u(0x00002000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_MSB _u(13)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_LSB _u(13)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_PIO0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_BITS _u(0x00001000)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_MSB _u(12)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_LSB _u(12)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_PADS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS _u(0x00000800)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_MSB _u(11)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_LSB _u(11)
+#define CLOCKS_WAKE_EN0_CLK_SYS_PADS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10)
+#define CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_JTAG
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_BITS _u(0x00000200)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_MSB _u(9)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_LSB _u(9)
+#define CLOCKS_WAKE_EN0_CLK_SYS_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_IO
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS _u(0x00000100)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_MSB _u(8)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_LSB _u(8)
+#define CLOCKS_WAKE_EN0_CLK_SYS_IO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C1
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_BITS _u(0x00000080)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_MSB _u(7)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_LSB _u(7)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_I2C0
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_BITS _u(0x00000040)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_MSB _u(6)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_LSB _u(6)
+#define CLOCKS_WAKE_EN0_CLK_SYS_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_DMA
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS _u(0x00000020)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_MSB _u(5)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_LSB _u(5)
+#define CLOCKS_WAKE_EN0_CLK_SYS_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_MSB _u(4)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_LSB _u(4)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_MSB _u(3)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_LSB _u(3)
+#define CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_ADC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_BITS _u(0x00000004)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_MSB _u(2)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_LSB _u(2)
+#define CLOCKS_WAKE_EN0_CLK_SYS_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_ADC_ADC
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_BITS _u(0x00000002)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_MSB _u(1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_LSB _u(1)
+#define CLOCKS_WAKE_EN0_CLK_ADC_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS
+// Description : None
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_RESET _u(0x1)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_MSB _u(0)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_LSB _u(0)
+#define CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_WAKE_EN1
+// Description : enable clock in wake mode
+#define CLOCKS_WAKE_EN1_OFFSET _u(0x000000a4)
+#define CLOCKS_WAKE_EN1_BITS _u(0x00007fff)
+#define CLOCKS_WAKE_EN1_RESET _u(0x00007fff)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_XOSC
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS _u(0x00004000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_MSB _u(14)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_LSB _u(14)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_XIP
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS _u(0x00002000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_MSB _u(13)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_LSB _u(13)
+#define CLOCKS_WAKE_EN1_CLK_SYS_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_MSB _u(12)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_LSB _u(12)
+#define CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_USB_USBCTRL
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_MSB _u(11)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_LSB _u(11)
+#define CLOCKS_WAKE_EN1_CLK_USB_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_MSB _u(10)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_LSB _u(10)
+#define CLOCKS_WAKE_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART1
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS _u(0x00000200)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_MSB _u(9)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_LSB _u(9)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART1
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS _u(0x00000100)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_MSB _u(8)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_LSB _u(8)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_UART0
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS _u(0x00000080)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_MSB _u(7)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_LSB _u(7)
+#define CLOCKS_WAKE_EN1_CLK_SYS_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_PERI_UART0
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS _u(0x00000040)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_MSB _u(6)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_LSB _u(6)
+#define CLOCKS_WAKE_EN1_CLK_PERI_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_TIMER
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS _u(0x00000020)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_MSB _u(5)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_LSB _u(5)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_TBMAN
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_MSB _u(4)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_LSB _u(4)
+#define CLOCKS_WAKE_EN1_CLK_SYS_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_MSB _u(3)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_LSB _u(3)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_MSB _u(2)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_LSB _u(2)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM5
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_MSB _u(1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_LSB _u(1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_WAKE_EN1_CLK_SYS_SRAM4
+// Description : None
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_RESET _u(0x1)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_MSB _u(0)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_LSB _u(0)
+#define CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_SLEEP_EN0
+// Description : enable clock in sleep mode
+#define CLOCKS_SLEEP_EN0_OFFSET _u(0x000000a8)
+#define CLOCKS_SLEEP_EN0_BITS _u(0xffffffff)
+#define CLOCKS_SLEEP_EN0_RESET _u(0xffffffff)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_BITS _u(0x80000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_MSB _u(31)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_LSB _u(31)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_BITS _u(0x40000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_MSB _u(30)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_LSB _u(30)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_BITS _u(0x20000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_MSB _u(29)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_LSB _u(29)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_BITS _u(0x10000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_MSB _u(28)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_LSB _u(28)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS _u(0x08000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_MSB _u(27)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_LSB _u(27)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS _u(0x04000000)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_MSB _u(26)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_LSB _u(26)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SPI0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS _u(0x02000000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_MSB _u(25)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_LSB _u(25)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_PERI_SPI0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS _u(0x01000000)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_MSB _u(24)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_LSB _u(24)
+#define CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_SIO
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_BITS _u(0x00800000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_MSB _u(23)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_LSB _u(23)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RTC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_BITS _u(0x00400000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_MSB _u(22)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_LSB _u(22)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_RTC_RTC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_BITS _u(0x00200000)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_MSB _u(21)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_LSB _u(21)
+#define CLOCKS_SLEEP_EN0_CLK_RTC_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROSC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_BITS _u(0x00100000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_MSB _u(20)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_LSB _u(20)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ROM
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_BITS _u(0x00080000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_MSB _u(19)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_LSB _u(19)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_RESETS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_BITS _u(0x00040000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_MSB _u(18)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_LSB _u(18)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PWM
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_BITS _u(0x00020000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_MSB _u(17)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_LSB _u(17)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PSM
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_BITS _u(0x00010000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_MSB _u(16)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_LSB _u(16)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PSM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_BITS _u(0x00008000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_MSB _u(15)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_LSB _u(15)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_BITS _u(0x00004000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_MSB _u(14)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_LSB _u(14)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_BITS _u(0x00002000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_MSB _u(13)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_LSB _u(13)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PIO0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_BITS _u(0x00001000)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_MSB _u(12)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_LSB _u(12)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_PADS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_BITS _u(0x00000800)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_MSB _u(11)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_LSB _u(11)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_PADS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_JTAG
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_BITS _u(0x00000200)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_MSB _u(9)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_LSB _u(9)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_IO
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_BITS _u(0x00000100)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_MSB _u(8)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_LSB _u(8)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_IO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C1
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_BITS _u(0x00000080)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_MSB _u(7)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_LSB _u(7)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_I2C0
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_BITS _u(0x00000040)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_MSB _u(6)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_LSB _u(6)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_DMA
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS _u(0x00000020)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_MSB _u(5)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_LSB _u(5)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_MSB _u(4)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_LSB _u(4)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_BITS _u(0x00000008)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_MSB _u(3)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_LSB _u(3)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_ADC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_BITS _u(0x00000004)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_MSB _u(2)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_LSB _u(2)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_ADC_ADC
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_BITS _u(0x00000002)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_MSB _u(1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_LSB _u(1)
+#define CLOCKS_SLEEP_EN0_CLK_ADC_ADC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS
+// Description : None
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_BITS _u(0x00000001)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_MSB _u(0)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_LSB _u(0)
+#define CLOCKS_SLEEP_EN0_CLK_SYS_CLOCKS_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_SLEEP_EN1
+// Description : enable clock in sleep mode
+#define CLOCKS_SLEEP_EN1_OFFSET _u(0x000000ac)
+#define CLOCKS_SLEEP_EN1_BITS _u(0x00007fff)
+#define CLOCKS_SLEEP_EN1_RESET _u(0x00007fff)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XOSC
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_BITS _u(0x00004000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_MSB _u(14)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_LSB _u(14)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_XIP
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_BITS _u(0x00002000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_MSB _u(13)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_LSB _u(13)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_BITS _u(0x00001000)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_MSB _u(12)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_LSB _u(12)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_WATCHDOG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_BITS _u(0x00000800)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_MSB _u(11)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_LSB _u(11)
+#define CLOCKS_SLEEP_EN1_CLK_USB_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_BITS _u(0x00000400)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_MSB _u(10)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_LSB _u(10)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART1
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS _u(0x00000200)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_MSB _u(9)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_LSB _u(9)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART1
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS _u(0x00000100)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_MSB _u(8)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_LSB _u(8)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_UART0
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS _u(0x00000080)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_MSB _u(7)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_LSB _u(7)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_PERI_UART0
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS _u(0x00000040)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_MSB _u(6)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_LSB _u(6)
+#define CLOCKS_SLEEP_EN1_CLK_PERI_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TIMER
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS _u(0x00000020)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_MSB _u(5)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_LSB _u(5)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_BITS _u(0x00000010)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_MSB _u(4)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_LSB _u(4)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_BITS _u(0x00000008)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_MSB _u(3)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_LSB _u(3)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_BITS _u(0x00000004)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_MSB _u(2)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_LSB _u(2)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_BITS _u(0x00000002)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_MSB _u(1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_LSB _u(1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4
+// Description : None
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_RESET _u(0x1)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_BITS _u(0x00000001)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_MSB _u(0)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_LSB _u(0)
+#define CLOCKS_SLEEP_EN1_CLK_SYS_SRAM4_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_ENABLED0
+// Description : indicates the state of the clock enable
+#define CLOCKS_ENABLED0_OFFSET _u(0x000000b0)
+#define CLOCKS_ENABLED0_BITS _u(0xffffffff)
+#define CLOCKS_ENABLED0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM3
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_BITS _u(0x80000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_MSB _u(31)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_LSB _u(31)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM2
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_BITS _u(0x40000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_MSB _u(30)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_LSB _u(30)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_BITS _u(0x20000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_MSB _u(29)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_LSB _u(29)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_SRAM0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_BITS _u(0x10000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_MSB _u(28)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_LSB _u(28)
+#define CLOCKS_ENABLED0_CLK_SYS_SRAM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_SPI1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_BITS _u(0x08000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_MSB _u(27)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_LSB _u(27)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_PERI_SPI1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_BITS _u(0x04000000)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_MSB _u(26)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_LSB _u(26)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_SPI0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_BITS _u(0x02000000)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_MSB _u(25)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_LSB _u(25)
+#define CLOCKS_ENABLED0_CLK_SYS_SPI0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_PERI_SPI0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_BITS _u(0x01000000)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_MSB _u(24)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_LSB _u(24)
+#define CLOCKS_ENABLED0_CLK_PERI_SPI0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_SIO
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_BITS _u(0x00800000)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_MSB _u(23)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_LSB _u(23)
+#define CLOCKS_ENABLED0_CLK_SYS_SIO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_RTC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_BITS _u(0x00400000)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_MSB _u(22)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_LSB _u(22)
+#define CLOCKS_ENABLED0_CLK_SYS_RTC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_RTC_RTC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_BITS _u(0x00200000)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_MSB _u(21)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_LSB _u(21)
+#define CLOCKS_ENABLED0_CLK_RTC_RTC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_ROSC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_BITS _u(0x00100000)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_MSB _u(20)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_LSB _u(20)
+#define CLOCKS_ENABLED0_CLK_SYS_ROSC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_ROM
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_BITS _u(0x00080000)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_MSB _u(19)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_LSB _u(19)
+#define CLOCKS_ENABLED0_CLK_SYS_ROM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_RESETS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_BITS _u(0x00040000)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_MSB _u(18)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_LSB _u(18)
+#define CLOCKS_ENABLED0_CLK_SYS_RESETS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_PWM
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_BITS _u(0x00020000)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_MSB _u(17)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_LSB _u(17)
+#define CLOCKS_ENABLED0_CLK_SYS_PWM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_PSM
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_BITS _u(0x00010000)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_MSB _u(16)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_LSB _u(16)
+#define CLOCKS_ENABLED0_CLK_SYS_PSM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_USB
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_BITS _u(0x00008000)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_MSB _u(15)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_LSB _u(15)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_USB_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_PLL_SYS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_BITS _u(0x00004000)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_MSB _u(14)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_LSB _u(14)
+#define CLOCKS_ENABLED0_CLK_SYS_PLL_SYS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_PIO1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_BITS _u(0x00002000)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_MSB _u(13)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_LSB _u(13)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_PIO0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_BITS _u(0x00001000)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_MSB _u(12)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_LSB _u(12)
+#define CLOCKS_ENABLED0_CLK_SYS_PIO0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_PADS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_BITS _u(0x00000800)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_MSB _u(11)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_LSB _u(11)
+#define CLOCKS_ENABLED0_CLK_SYS_PADS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_BITS _u(0x00000400)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_MSB _u(10)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_LSB _u(10)
+#define CLOCKS_ENABLED0_CLK_SYS_VREG_AND_CHIP_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_JTAG
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_BITS _u(0x00000200)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_MSB _u(9)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_LSB _u(9)
+#define CLOCKS_ENABLED0_CLK_SYS_JTAG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_IO
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_IO_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_BITS _u(0x00000100)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_MSB _u(8)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_LSB _u(8)
+#define CLOCKS_ENABLED0_CLK_SYS_IO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_I2C1
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_BITS _u(0x00000080)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_MSB _u(7)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_LSB _u(7)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_I2C0
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_BITS _u(0x00000040)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_MSB _u(6)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_LSB _u(6)
+#define CLOCKS_ENABLED0_CLK_SYS_I2C0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_DMA
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_BITS _u(0x00000020)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_MSB _u(5)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_LSB _u(5)
+#define CLOCKS_ENABLED0_CLK_SYS_DMA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_BITS _u(0x00000010)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_MSB _u(4)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_LSB _u(4)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSFABRIC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_BUSCTRL
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_BITS _u(0x00000008)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_MSB _u(3)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_LSB _u(3)
+#define CLOCKS_ENABLED0_CLK_SYS_BUSCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_ADC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_BITS _u(0x00000004)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_MSB _u(2)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_LSB _u(2)
+#define CLOCKS_ENABLED0_CLK_SYS_ADC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_ADC_ADC
+// Description : None
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_BITS _u(0x00000002)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_MSB _u(1)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_LSB _u(1)
+#define CLOCKS_ENABLED0_CLK_ADC_ADC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED0_CLK_SYS_CLOCKS
+// Description : None
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_RESET _u(0x0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_BITS _u(0x00000001)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_MSB _u(0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_LSB _u(0)
+#define CLOCKS_ENABLED0_CLK_SYS_CLOCKS_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_ENABLED1
+// Description : indicates the state of the clock enable
+#define CLOCKS_ENABLED1_OFFSET _u(0x000000b4)
+#define CLOCKS_ENABLED1_BITS _u(0x00007fff)
+#define CLOCKS_ENABLED1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_XOSC
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_BITS _u(0x00004000)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_MSB _u(14)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_LSB _u(14)
+#define CLOCKS_ENABLED1_CLK_SYS_XOSC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_XIP
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_BITS _u(0x00002000)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_MSB _u(13)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_LSB _u(13)
+#define CLOCKS_ENABLED1_CLK_SYS_XIP_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_WATCHDOG
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_BITS _u(0x00001000)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_MSB _u(12)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_LSB _u(12)
+#define CLOCKS_ENABLED1_CLK_SYS_WATCHDOG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_USB_USBCTRL
+// Description : None
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_BITS _u(0x00000800)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_MSB _u(11)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_LSB _u(11)
+#define CLOCKS_ENABLED1_CLK_USB_USBCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_USBCTRL
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_BITS _u(0x00000400)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_MSB _u(10)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_LSB _u(10)
+#define CLOCKS_ENABLED1_CLK_SYS_USBCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_UART1
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_BITS _u(0x00000200)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_MSB _u(9)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_LSB _u(9)
+#define CLOCKS_ENABLED1_CLK_SYS_UART1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_PERI_UART1
+// Description : None
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_BITS _u(0x00000100)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_MSB _u(8)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_LSB _u(8)
+#define CLOCKS_ENABLED1_CLK_PERI_UART1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_UART0
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_BITS _u(0x00000080)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_MSB _u(7)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_LSB _u(7)
+#define CLOCKS_ENABLED1_CLK_SYS_UART0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_PERI_UART0
+// Description : None
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_BITS _u(0x00000040)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_MSB _u(6)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_LSB _u(6)
+#define CLOCKS_ENABLED1_CLK_PERI_UART0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_TIMER
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_BITS _u(0x00000020)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_MSB _u(5)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_LSB _u(5)
+#define CLOCKS_ENABLED1_CLK_SYS_TIMER_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_TBMAN
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_BITS _u(0x00000010)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_MSB _u(4)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_LSB _u(4)
+#define CLOCKS_ENABLED1_CLK_SYS_TBMAN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_SYSINFO
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_BITS _u(0x00000008)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_MSB _u(3)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_LSB _u(3)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSINFO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_SYSCFG
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_BITS _u(0x00000004)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_MSB _u(2)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_LSB _u(2)
+#define CLOCKS_ENABLED1_CLK_SYS_SYSCFG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM5
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_BITS _u(0x00000002)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_MSB _u(1)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_LSB _u(1)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM5_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_ENABLED1_CLK_SYS_SRAM4
+// Description : None
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_RESET _u(0x0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_BITS _u(0x00000001)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_MSB _u(0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_LSB _u(0)
+#define CLOCKS_ENABLED1_CLK_SYS_SRAM4_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_INTR
+// Description : Raw Interrupts
+#define CLOCKS_INTR_OFFSET _u(0x000000b8)
+#define CLOCKS_INTR_BITS _u(0x00000001)
+#define CLOCKS_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_INTR_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTR_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTR_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_LSB _u(0)
+#define CLOCKS_INTR_CLK_SYS_RESUS_ACCESS "RO"
+// =============================================================================
+// Register : CLOCKS_INTE
+// Description : Interrupt Enable
+#define CLOCKS_INTE_OFFSET _u(0x000000bc)
+#define CLOCKS_INTE_BITS _u(0x00000001)
+#define CLOCKS_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_INTE_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTE_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTE_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_LSB _u(0)
+#define CLOCKS_INTE_CLK_SYS_RESUS_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_INTF
+// Description : Interrupt Force
+#define CLOCKS_INTF_OFFSET _u(0x000000c0)
+#define CLOCKS_INTF_BITS _u(0x00000001)
+#define CLOCKS_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_INTF_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTF_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTF_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_LSB _u(0)
+#define CLOCKS_INTF_CLK_SYS_RESUS_ACCESS "RW"
+// =============================================================================
+// Register : CLOCKS_INTS
+// Description : Interrupt status after masking & forcing
+#define CLOCKS_INTS_OFFSET _u(0x000000c4)
+#define CLOCKS_INTS_BITS _u(0x00000001)
+#define CLOCKS_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : CLOCKS_INTS_CLK_SYS_RESUS
+// Description : None
+#define CLOCKS_INTS_CLK_SYS_RESUS_RESET _u(0x0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_BITS _u(0x00000001)
+#define CLOCKS_INTS_CLK_SYS_RESUS_MSB _u(0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_LSB _u(0)
+#define CLOCKS_INTS_CLK_SYS_RESUS_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_CLOCKS_DEFINED
diff --git a/arkanoid/pico/hardware/regs/dma.h b/arkanoid/pico/hardware/regs/dma.h
new file mode 100644
index 0000000..042c3c1
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/dma.h
@@ -0,0 +1,5313 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : DMA
+// Version : 1
+// Bus type : apb
+// Description : DMA with separate read and write masters
+// =============================================================================
+#ifndef HARDWARE_REGS_DMA_DEFINED
+#define HARDWARE_REGS_DMA_DEFINED
+// =============================================================================
+// Register : DMA_CH0_READ_ADDR
+// Description : DMA Channel 0 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000)
+#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH0_READ_ADDR_MSB _u(31)
+#define DMA_CH0_READ_ADDR_LSB _u(0)
+#define DMA_CH0_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_WRITE_ADDR
+// Description : DMA Channel 0 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004)
+#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH0_WRITE_ADDR_MSB _u(31)
+#define DMA_CH0_WRITE_ADDR_LSB _u(0)
+#define DMA_CH0_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_TRANS_COUNT
+// Description : DMA Channel 0 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008)
+#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH0_TRANS_COUNT_MSB _u(31)
+#define DMA_CH0_TRANS_COUNT_LSB _u(0)
+#define DMA_CH0_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_CTRL_TRIG
+// Description : DMA Channel 0 Control and Status
+#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c)
+#define DMA_CH0_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (0).
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH0_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL1_CTRL
+// Description : Alias for channel 0 CTRL register
+#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010)
+#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH0_AL1_CTRL_RESET "-"
+#define DMA_CH0_AL1_CTRL_MSB _u(31)
+#define DMA_CH0_AL1_CTRL_LSB _u(0)
+#define DMA_CH0_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL1_READ_ADDR
+// Description : Alias for channel 0 READ_ADDR register
+#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014)
+#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_AL1_READ_ADDR_RESET "-"
+#define DMA_CH0_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH0_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL1_WRITE_ADDR
+// Description : Alias for channel 0 WRITE_ADDR register
+#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018)
+#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 0 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL2_CTRL
+// Description : Alias for channel 0 CTRL register
+#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020)
+#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH0_AL2_CTRL_RESET "-"
+#define DMA_CH0_AL2_CTRL_MSB _u(31)
+#define DMA_CH0_AL2_CTRL_LSB _u(0)
+#define DMA_CH0_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL2_TRANS_COUNT
+// Description : Alias for channel 0 TRANS_COUNT register
+#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024)
+#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH0_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL2_READ_ADDR
+// Description : Alias for channel 0 READ_ADDR register
+#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028)
+#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_AL2_READ_ADDR_RESET "-"
+#define DMA_CH0_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH0_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 0 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL3_CTRL
+// Description : Alias for channel 0 CTRL register
+#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030)
+#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH0_AL3_CTRL_RESET "-"
+#define DMA_CH0_AL3_CTRL_MSB _u(31)
+#define DMA_CH0_AL3_CTRL_LSB _u(0)
+#define DMA_CH0_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL3_WRITE_ADDR
+// Description : Alias for channel 0 WRITE_ADDR register
+#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034)
+#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH0_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL3_TRANS_COUNT
+// Description : Alias for channel 0 TRANS_COUNT register
+#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038)
+#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH0_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH0_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 0 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_READ_ADDR
+// Description : DMA Channel 1 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040)
+#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH1_READ_ADDR_MSB _u(31)
+#define DMA_CH1_READ_ADDR_LSB _u(0)
+#define DMA_CH1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_WRITE_ADDR
+// Description : DMA Channel 1 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044)
+#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_TRANS_COUNT
+// Description : DMA Channel 1 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048)
+#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH1_TRANS_COUNT_MSB _u(31)
+#define DMA_CH1_TRANS_COUNT_LSB _u(0)
+#define DMA_CH1_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_CTRL_TRIG
+// Description : DMA Channel 1 Control and Status
+#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c)
+#define DMA_CH1_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000800)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (1).
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x1)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH1_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL1_CTRL
+// Description : Alias for channel 1 CTRL register
+#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050)
+#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH1_AL1_CTRL_RESET "-"
+#define DMA_CH1_AL1_CTRL_MSB _u(31)
+#define DMA_CH1_AL1_CTRL_LSB _u(0)
+#define DMA_CH1_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL1_READ_ADDR
+// Description : Alias for channel 1 READ_ADDR register
+#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054)
+#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_AL1_READ_ADDR_RESET "-"
+#define DMA_CH1_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH1_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL1_WRITE_ADDR
+// Description : Alias for channel 1 WRITE_ADDR register
+#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058)
+#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 1 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL2_CTRL
+// Description : Alias for channel 1 CTRL register
+#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060)
+#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH1_AL2_CTRL_RESET "-"
+#define DMA_CH1_AL2_CTRL_MSB _u(31)
+#define DMA_CH1_AL2_CTRL_LSB _u(0)
+#define DMA_CH1_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL2_TRANS_COUNT
+// Description : Alias for channel 1 TRANS_COUNT register
+#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064)
+#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH1_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL2_READ_ADDR
+// Description : Alias for channel 1 READ_ADDR register
+#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068)
+#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_AL2_READ_ADDR_RESET "-"
+#define DMA_CH1_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH1_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 1 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL3_CTRL
+// Description : Alias for channel 1 CTRL register
+#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070)
+#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH1_AL3_CTRL_RESET "-"
+#define DMA_CH1_AL3_CTRL_MSB _u(31)
+#define DMA_CH1_AL3_CTRL_LSB _u(0)
+#define DMA_CH1_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL3_WRITE_ADDR
+// Description : Alias for channel 1 WRITE_ADDR register
+#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074)
+#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH1_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL3_TRANS_COUNT
+// Description : Alias for channel 1 TRANS_COUNT register
+#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078)
+#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH1_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH1_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 1 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_READ_ADDR
+// Description : DMA Channel 2 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080)
+#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH2_READ_ADDR_MSB _u(31)
+#define DMA_CH2_READ_ADDR_LSB _u(0)
+#define DMA_CH2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_WRITE_ADDR
+// Description : DMA Channel 2 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084)
+#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH2_WRITE_ADDR_MSB _u(31)
+#define DMA_CH2_WRITE_ADDR_LSB _u(0)
+#define DMA_CH2_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_TRANS_COUNT
+// Description : DMA Channel 2 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088)
+#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_CTRL_TRIG
+// Description : DMA Channel 2 Control and Status
+#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c)
+#define DMA_CH2_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH2_CTRL_TRIG_RESET _u(0x00001000)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (2).
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x2)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH2_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL1_CTRL
+// Description : Alias for channel 2 CTRL register
+#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090)
+#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH2_AL1_CTRL_RESET "-"
+#define DMA_CH2_AL1_CTRL_MSB _u(31)
+#define DMA_CH2_AL1_CTRL_LSB _u(0)
+#define DMA_CH2_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL1_READ_ADDR
+// Description : Alias for channel 2 READ_ADDR register
+#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094)
+#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_AL1_READ_ADDR_RESET "-"
+#define DMA_CH2_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH2_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL1_WRITE_ADDR
+// Description : Alias for channel 2 WRITE_ADDR register
+#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098)
+#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 2 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL2_CTRL
+// Description : Alias for channel 2 CTRL register
+#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0)
+#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH2_AL2_CTRL_RESET "-"
+#define DMA_CH2_AL2_CTRL_MSB _u(31)
+#define DMA_CH2_AL2_CTRL_LSB _u(0)
+#define DMA_CH2_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL2_TRANS_COUNT
+// Description : Alias for channel 2 TRANS_COUNT register
+#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4)
+#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH2_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL2_READ_ADDR
+// Description : Alias for channel 2 READ_ADDR register
+#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8)
+#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_AL2_READ_ADDR_RESET "-"
+#define DMA_CH2_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH2_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 2 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL3_CTRL
+// Description : Alias for channel 2 CTRL register
+#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0)
+#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH2_AL3_CTRL_RESET "-"
+#define DMA_CH2_AL3_CTRL_MSB _u(31)
+#define DMA_CH2_AL3_CTRL_LSB _u(0)
+#define DMA_CH2_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL3_WRITE_ADDR
+// Description : Alias for channel 2 WRITE_ADDR register
+#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4)
+#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH2_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL3_TRANS_COUNT
+// Description : Alias for channel 2 TRANS_COUNT register
+#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8)
+#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH2_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH2_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 2 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_READ_ADDR
+// Description : DMA Channel 3 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0)
+#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH3_READ_ADDR_MSB _u(31)
+#define DMA_CH3_READ_ADDR_LSB _u(0)
+#define DMA_CH3_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_WRITE_ADDR
+// Description : DMA Channel 3 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4)
+#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_TRANS_COUNT
+// Description : DMA Channel 3 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8)
+#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_CTRL_TRIG
+// Description : DMA Channel 3 Control and Status
+#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc)
+#define DMA_CH3_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH3_CTRL_TRIG_RESET _u(0x00001800)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (3).
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x3)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH3_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL1_CTRL
+// Description : Alias for channel 3 CTRL register
+#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0)
+#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH3_AL1_CTRL_RESET "-"
+#define DMA_CH3_AL1_CTRL_MSB _u(31)
+#define DMA_CH3_AL1_CTRL_LSB _u(0)
+#define DMA_CH3_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL1_READ_ADDR
+// Description : Alias for channel 3 READ_ADDR register
+#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4)
+#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_AL1_READ_ADDR_RESET "-"
+#define DMA_CH3_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH3_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL1_WRITE_ADDR
+// Description : Alias for channel 3 WRITE_ADDR register
+#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8)
+#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 3 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL2_CTRL
+// Description : Alias for channel 3 CTRL register
+#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0)
+#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH3_AL2_CTRL_RESET "-"
+#define DMA_CH3_AL2_CTRL_MSB _u(31)
+#define DMA_CH3_AL2_CTRL_LSB _u(0)
+#define DMA_CH3_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL2_TRANS_COUNT
+// Description : Alias for channel 3 TRANS_COUNT register
+#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4)
+#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH3_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL2_READ_ADDR
+// Description : Alias for channel 3 READ_ADDR register
+#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8)
+#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_AL2_READ_ADDR_RESET "-"
+#define DMA_CH3_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH3_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 3 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL3_CTRL
+// Description : Alias for channel 3 CTRL register
+#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0)
+#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH3_AL3_CTRL_RESET "-"
+#define DMA_CH3_AL3_CTRL_MSB _u(31)
+#define DMA_CH3_AL3_CTRL_LSB _u(0)
+#define DMA_CH3_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL3_WRITE_ADDR
+// Description : Alias for channel 3 WRITE_ADDR register
+#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4)
+#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH3_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL3_TRANS_COUNT
+// Description : Alias for channel 3 TRANS_COUNT register
+#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8)
+#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH3_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH3_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 3 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_READ_ADDR
+// Description : DMA Channel 4 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100)
+#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH4_READ_ADDR_MSB _u(31)
+#define DMA_CH4_READ_ADDR_LSB _u(0)
+#define DMA_CH4_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_WRITE_ADDR
+// Description : DMA Channel 4 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104)
+#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH4_WRITE_ADDR_MSB _u(31)
+#define DMA_CH4_WRITE_ADDR_LSB _u(0)
+#define DMA_CH4_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_TRANS_COUNT
+// Description : DMA Channel 4 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108)
+#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH4_TRANS_COUNT_MSB _u(31)
+#define DMA_CH4_TRANS_COUNT_LSB _u(0)
+#define DMA_CH4_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_CTRL_TRIG
+// Description : DMA Channel 4 Control and Status
+#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c)
+#define DMA_CH4_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH4_CTRL_TRIG_RESET _u(0x00002000)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (4).
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x4)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH4_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL1_CTRL
+// Description : Alias for channel 4 CTRL register
+#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110)
+#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH4_AL1_CTRL_RESET "-"
+#define DMA_CH4_AL1_CTRL_MSB _u(31)
+#define DMA_CH4_AL1_CTRL_LSB _u(0)
+#define DMA_CH4_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL1_READ_ADDR
+// Description : Alias for channel 4 READ_ADDR register
+#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114)
+#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_AL1_READ_ADDR_RESET "-"
+#define DMA_CH4_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH4_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL1_WRITE_ADDR
+// Description : Alias for channel 4 WRITE_ADDR register
+#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118)
+#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 4 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL2_CTRL
+// Description : Alias for channel 4 CTRL register
+#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120)
+#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH4_AL2_CTRL_RESET "-"
+#define DMA_CH4_AL2_CTRL_MSB _u(31)
+#define DMA_CH4_AL2_CTRL_LSB _u(0)
+#define DMA_CH4_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL2_TRANS_COUNT
+// Description : Alias for channel 4 TRANS_COUNT register
+#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124)
+#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH4_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL2_READ_ADDR
+// Description : Alias for channel 4 READ_ADDR register
+#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128)
+#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_AL2_READ_ADDR_RESET "-"
+#define DMA_CH4_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH4_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 4 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL3_CTRL
+// Description : Alias for channel 4 CTRL register
+#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130)
+#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH4_AL3_CTRL_RESET "-"
+#define DMA_CH4_AL3_CTRL_MSB _u(31)
+#define DMA_CH4_AL3_CTRL_LSB _u(0)
+#define DMA_CH4_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL3_WRITE_ADDR
+// Description : Alias for channel 4 WRITE_ADDR register
+#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134)
+#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH4_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL3_TRANS_COUNT
+// Description : Alias for channel 4 TRANS_COUNT register
+#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138)
+#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH4_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH4_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 4 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_READ_ADDR
+// Description : DMA Channel 5 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140)
+#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH5_READ_ADDR_MSB _u(31)
+#define DMA_CH5_READ_ADDR_LSB _u(0)
+#define DMA_CH5_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_WRITE_ADDR
+// Description : DMA Channel 5 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144)
+#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH5_WRITE_ADDR_MSB _u(31)
+#define DMA_CH5_WRITE_ADDR_LSB _u(0)
+#define DMA_CH5_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_TRANS_COUNT
+// Description : DMA Channel 5 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148)
+#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH5_TRANS_COUNT_MSB _u(31)
+#define DMA_CH5_TRANS_COUNT_LSB _u(0)
+#define DMA_CH5_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_CTRL_TRIG
+// Description : DMA Channel 5 Control and Status
+#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c)
+#define DMA_CH5_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH5_CTRL_TRIG_RESET _u(0x00002800)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (5).
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x5)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH5_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL1_CTRL
+// Description : Alias for channel 5 CTRL register
+#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150)
+#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH5_AL1_CTRL_RESET "-"
+#define DMA_CH5_AL1_CTRL_MSB _u(31)
+#define DMA_CH5_AL1_CTRL_LSB _u(0)
+#define DMA_CH5_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL1_READ_ADDR
+// Description : Alias for channel 5 READ_ADDR register
+#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154)
+#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_AL1_READ_ADDR_RESET "-"
+#define DMA_CH5_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH5_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL1_WRITE_ADDR
+// Description : Alias for channel 5 WRITE_ADDR register
+#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158)
+#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 5 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL2_CTRL
+// Description : Alias for channel 5 CTRL register
+#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160)
+#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH5_AL2_CTRL_RESET "-"
+#define DMA_CH5_AL2_CTRL_MSB _u(31)
+#define DMA_CH5_AL2_CTRL_LSB _u(0)
+#define DMA_CH5_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL2_TRANS_COUNT
+// Description : Alias for channel 5 TRANS_COUNT register
+#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164)
+#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH5_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL2_READ_ADDR
+// Description : Alias for channel 5 READ_ADDR register
+#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168)
+#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_AL2_READ_ADDR_RESET "-"
+#define DMA_CH5_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH5_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 5 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL3_CTRL
+// Description : Alias for channel 5 CTRL register
+#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170)
+#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH5_AL3_CTRL_RESET "-"
+#define DMA_CH5_AL3_CTRL_MSB _u(31)
+#define DMA_CH5_AL3_CTRL_LSB _u(0)
+#define DMA_CH5_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL3_WRITE_ADDR
+// Description : Alias for channel 5 WRITE_ADDR register
+#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174)
+#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH5_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL3_TRANS_COUNT
+// Description : Alias for channel 5 TRANS_COUNT register
+#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178)
+#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH5_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH5_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 5 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_READ_ADDR
+// Description : DMA Channel 6 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180)
+#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH6_READ_ADDR_MSB _u(31)
+#define DMA_CH6_READ_ADDR_LSB _u(0)
+#define DMA_CH6_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_WRITE_ADDR
+// Description : DMA Channel 6 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184)
+#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH6_WRITE_ADDR_MSB _u(31)
+#define DMA_CH6_WRITE_ADDR_LSB _u(0)
+#define DMA_CH6_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_TRANS_COUNT
+// Description : DMA Channel 6 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188)
+#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH6_TRANS_COUNT_MSB _u(31)
+#define DMA_CH6_TRANS_COUNT_LSB _u(0)
+#define DMA_CH6_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_CTRL_TRIG
+// Description : DMA Channel 6 Control and Status
+#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c)
+#define DMA_CH6_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH6_CTRL_TRIG_RESET _u(0x00003000)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (6).
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x6)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH6_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL1_CTRL
+// Description : Alias for channel 6 CTRL register
+#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190)
+#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH6_AL1_CTRL_RESET "-"
+#define DMA_CH6_AL1_CTRL_MSB _u(31)
+#define DMA_CH6_AL1_CTRL_LSB _u(0)
+#define DMA_CH6_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL1_READ_ADDR
+// Description : Alias for channel 6 READ_ADDR register
+#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194)
+#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_AL1_READ_ADDR_RESET "-"
+#define DMA_CH6_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH6_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL1_WRITE_ADDR
+// Description : Alias for channel 6 WRITE_ADDR register
+#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198)
+#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 6 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL2_CTRL
+// Description : Alias for channel 6 CTRL register
+#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0)
+#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH6_AL2_CTRL_RESET "-"
+#define DMA_CH6_AL2_CTRL_MSB _u(31)
+#define DMA_CH6_AL2_CTRL_LSB _u(0)
+#define DMA_CH6_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL2_TRANS_COUNT
+// Description : Alias for channel 6 TRANS_COUNT register
+#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4)
+#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH6_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL2_READ_ADDR
+// Description : Alias for channel 6 READ_ADDR register
+#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8)
+#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_AL2_READ_ADDR_RESET "-"
+#define DMA_CH6_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH6_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 6 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL3_CTRL
+// Description : Alias for channel 6 CTRL register
+#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0)
+#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH6_AL3_CTRL_RESET "-"
+#define DMA_CH6_AL3_CTRL_MSB _u(31)
+#define DMA_CH6_AL3_CTRL_LSB _u(0)
+#define DMA_CH6_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL3_WRITE_ADDR
+// Description : Alias for channel 6 WRITE_ADDR register
+#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4)
+#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH6_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL3_TRANS_COUNT
+// Description : Alias for channel 6 TRANS_COUNT register
+#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8)
+#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH6_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH6_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 6 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_READ_ADDR
+// Description : DMA Channel 7 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0)
+#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH7_READ_ADDR_MSB _u(31)
+#define DMA_CH7_READ_ADDR_LSB _u(0)
+#define DMA_CH7_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_WRITE_ADDR
+// Description : DMA Channel 7 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4)
+#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH7_WRITE_ADDR_MSB _u(31)
+#define DMA_CH7_WRITE_ADDR_LSB _u(0)
+#define DMA_CH7_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_TRANS_COUNT
+// Description : DMA Channel 7 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8)
+#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH7_TRANS_COUNT_MSB _u(31)
+#define DMA_CH7_TRANS_COUNT_LSB _u(0)
+#define DMA_CH7_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_CTRL_TRIG
+// Description : DMA Channel 7 Control and Status
+#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc)
+#define DMA_CH7_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH7_CTRL_TRIG_RESET _u(0x00003800)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (7).
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x7)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH7_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL1_CTRL
+// Description : Alias for channel 7 CTRL register
+#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0)
+#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH7_AL1_CTRL_RESET "-"
+#define DMA_CH7_AL1_CTRL_MSB _u(31)
+#define DMA_CH7_AL1_CTRL_LSB _u(0)
+#define DMA_CH7_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL1_READ_ADDR
+// Description : Alias for channel 7 READ_ADDR register
+#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4)
+#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_AL1_READ_ADDR_RESET "-"
+#define DMA_CH7_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH7_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL1_WRITE_ADDR
+// Description : Alias for channel 7 WRITE_ADDR register
+#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8)
+#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 7 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL2_CTRL
+// Description : Alias for channel 7 CTRL register
+#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0)
+#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH7_AL2_CTRL_RESET "-"
+#define DMA_CH7_AL2_CTRL_MSB _u(31)
+#define DMA_CH7_AL2_CTRL_LSB _u(0)
+#define DMA_CH7_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL2_TRANS_COUNT
+// Description : Alias for channel 7 TRANS_COUNT register
+#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4)
+#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH7_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL2_READ_ADDR
+// Description : Alias for channel 7 READ_ADDR register
+#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8)
+#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_AL2_READ_ADDR_RESET "-"
+#define DMA_CH7_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH7_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 7 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL3_CTRL
+// Description : Alias for channel 7 CTRL register
+#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0)
+#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH7_AL3_CTRL_RESET "-"
+#define DMA_CH7_AL3_CTRL_MSB _u(31)
+#define DMA_CH7_AL3_CTRL_LSB _u(0)
+#define DMA_CH7_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL3_WRITE_ADDR
+// Description : Alias for channel 7 WRITE_ADDR register
+#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4)
+#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH7_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL3_TRANS_COUNT
+// Description : Alias for channel 7 TRANS_COUNT register
+#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8)
+#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH7_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH7_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 7 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_READ_ADDR
+// Description : DMA Channel 8 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200)
+#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH8_READ_ADDR_MSB _u(31)
+#define DMA_CH8_READ_ADDR_LSB _u(0)
+#define DMA_CH8_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_WRITE_ADDR
+// Description : DMA Channel 8 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204)
+#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH8_WRITE_ADDR_MSB _u(31)
+#define DMA_CH8_WRITE_ADDR_LSB _u(0)
+#define DMA_CH8_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_TRANS_COUNT
+// Description : DMA Channel 8 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208)
+#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH8_TRANS_COUNT_MSB _u(31)
+#define DMA_CH8_TRANS_COUNT_LSB _u(0)
+#define DMA_CH8_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_CTRL_TRIG
+// Description : DMA Channel 8 Control and Status
+#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c)
+#define DMA_CH8_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH8_CTRL_TRIG_RESET _u(0x00004000)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (8).
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x8)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH8_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL1_CTRL
+// Description : Alias for channel 8 CTRL register
+#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210)
+#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH8_AL1_CTRL_RESET "-"
+#define DMA_CH8_AL1_CTRL_MSB _u(31)
+#define DMA_CH8_AL1_CTRL_LSB _u(0)
+#define DMA_CH8_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL1_READ_ADDR
+// Description : Alias for channel 8 READ_ADDR register
+#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214)
+#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_AL1_READ_ADDR_RESET "-"
+#define DMA_CH8_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH8_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL1_WRITE_ADDR
+// Description : Alias for channel 8 WRITE_ADDR register
+#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218)
+#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 8 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL2_CTRL
+// Description : Alias for channel 8 CTRL register
+#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220)
+#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH8_AL2_CTRL_RESET "-"
+#define DMA_CH8_AL2_CTRL_MSB _u(31)
+#define DMA_CH8_AL2_CTRL_LSB _u(0)
+#define DMA_CH8_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL2_TRANS_COUNT
+// Description : Alias for channel 8 TRANS_COUNT register
+#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224)
+#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH8_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL2_READ_ADDR
+// Description : Alias for channel 8 READ_ADDR register
+#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228)
+#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_AL2_READ_ADDR_RESET "-"
+#define DMA_CH8_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH8_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 8 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL3_CTRL
+// Description : Alias for channel 8 CTRL register
+#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230)
+#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH8_AL3_CTRL_RESET "-"
+#define DMA_CH8_AL3_CTRL_MSB _u(31)
+#define DMA_CH8_AL3_CTRL_LSB _u(0)
+#define DMA_CH8_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL3_WRITE_ADDR
+// Description : Alias for channel 8 WRITE_ADDR register
+#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234)
+#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH8_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL3_TRANS_COUNT
+// Description : Alias for channel 8 TRANS_COUNT register
+#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238)
+#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH8_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH8_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 8 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_READ_ADDR
+// Description : DMA Channel 9 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240)
+#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH9_READ_ADDR_MSB _u(31)
+#define DMA_CH9_READ_ADDR_LSB _u(0)
+#define DMA_CH9_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_WRITE_ADDR
+// Description : DMA Channel 9 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244)
+#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH9_WRITE_ADDR_MSB _u(31)
+#define DMA_CH9_WRITE_ADDR_LSB _u(0)
+#define DMA_CH9_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_TRANS_COUNT
+// Description : DMA Channel 9 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248)
+#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH9_TRANS_COUNT_MSB _u(31)
+#define DMA_CH9_TRANS_COUNT_LSB _u(0)
+#define DMA_CH9_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_CTRL_TRIG
+// Description : DMA Channel 9 Control and Status
+#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c)
+#define DMA_CH9_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH9_CTRL_TRIG_RESET _u(0x00004800)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (9).
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x9)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH9_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL1_CTRL
+// Description : Alias for channel 9 CTRL register
+#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250)
+#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH9_AL1_CTRL_RESET "-"
+#define DMA_CH9_AL1_CTRL_MSB _u(31)
+#define DMA_CH9_AL1_CTRL_LSB _u(0)
+#define DMA_CH9_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL1_READ_ADDR
+// Description : Alias for channel 9 READ_ADDR register
+#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254)
+#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_AL1_READ_ADDR_RESET "-"
+#define DMA_CH9_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH9_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL1_WRITE_ADDR
+// Description : Alias for channel 9 WRITE_ADDR register
+#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258)
+#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 9 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL2_CTRL
+// Description : Alias for channel 9 CTRL register
+#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260)
+#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH9_AL2_CTRL_RESET "-"
+#define DMA_CH9_AL2_CTRL_MSB _u(31)
+#define DMA_CH9_AL2_CTRL_LSB _u(0)
+#define DMA_CH9_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL2_TRANS_COUNT
+// Description : Alias for channel 9 TRANS_COUNT register
+#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264)
+#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH9_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL2_READ_ADDR
+// Description : Alias for channel 9 READ_ADDR register
+#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268)
+#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_AL2_READ_ADDR_RESET "-"
+#define DMA_CH9_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH9_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 9 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL3_CTRL
+// Description : Alias for channel 9 CTRL register
+#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270)
+#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH9_AL3_CTRL_RESET "-"
+#define DMA_CH9_AL3_CTRL_MSB _u(31)
+#define DMA_CH9_AL3_CTRL_LSB _u(0)
+#define DMA_CH9_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL3_WRITE_ADDR
+// Description : Alias for channel 9 WRITE_ADDR register
+#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274)
+#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH9_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL3_TRANS_COUNT
+// Description : Alias for channel 9 TRANS_COUNT register
+#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278)
+#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH9_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH9_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 9 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_READ_ADDR
+// Description : DMA Channel 10 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280)
+#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH10_READ_ADDR_MSB _u(31)
+#define DMA_CH10_READ_ADDR_LSB _u(0)
+#define DMA_CH10_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_WRITE_ADDR
+// Description : DMA Channel 10 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284)
+#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH10_WRITE_ADDR_MSB _u(31)
+#define DMA_CH10_WRITE_ADDR_LSB _u(0)
+#define DMA_CH10_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_TRANS_COUNT
+// Description : DMA Channel 10 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288)
+#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH10_TRANS_COUNT_MSB _u(31)
+#define DMA_CH10_TRANS_COUNT_LSB _u(0)
+#define DMA_CH10_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_CTRL_TRIG
+// Description : DMA Channel 10 Control and Status
+#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c)
+#define DMA_CH10_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH10_CTRL_TRIG_RESET _u(0x00005000)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (10).
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0xa)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH10_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL1_CTRL
+// Description : Alias for channel 10 CTRL register
+#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290)
+#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH10_AL1_CTRL_RESET "-"
+#define DMA_CH10_AL1_CTRL_MSB _u(31)
+#define DMA_CH10_AL1_CTRL_LSB _u(0)
+#define DMA_CH10_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL1_READ_ADDR
+// Description : Alias for channel 10 READ_ADDR register
+#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294)
+#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_AL1_READ_ADDR_RESET "-"
+#define DMA_CH10_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH10_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL1_WRITE_ADDR
+// Description : Alias for channel 10 WRITE_ADDR register
+#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298)
+#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 10 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL2_CTRL
+// Description : Alias for channel 10 CTRL register
+#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0)
+#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH10_AL2_CTRL_RESET "-"
+#define DMA_CH10_AL2_CTRL_MSB _u(31)
+#define DMA_CH10_AL2_CTRL_LSB _u(0)
+#define DMA_CH10_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL2_TRANS_COUNT
+// Description : Alias for channel 10 TRANS_COUNT register
+#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4)
+#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH10_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL2_READ_ADDR
+// Description : Alias for channel 10 READ_ADDR register
+#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8)
+#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_AL2_READ_ADDR_RESET "-"
+#define DMA_CH10_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH10_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 10 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL3_CTRL
+// Description : Alias for channel 10 CTRL register
+#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0)
+#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH10_AL3_CTRL_RESET "-"
+#define DMA_CH10_AL3_CTRL_MSB _u(31)
+#define DMA_CH10_AL3_CTRL_LSB _u(0)
+#define DMA_CH10_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL3_WRITE_ADDR
+// Description : Alias for channel 10 WRITE_ADDR register
+#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4)
+#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH10_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL3_TRANS_COUNT
+// Description : Alias for channel 10 TRANS_COUNT register
+#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8)
+#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH10_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH10_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 10 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_READ_ADDR
+// Description : DMA Channel 11 Read Address pointer
+// This register updates automatically each time a read completes.
+// The current value is the next address to be read by this
+// channel.
+#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0)
+#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_READ_ADDR_RESET _u(0x00000000)
+#define DMA_CH11_READ_ADDR_MSB _u(31)
+#define DMA_CH11_READ_ADDR_LSB _u(0)
+#define DMA_CH11_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_WRITE_ADDR
+// Description : DMA Channel 11 Write Address pointer
+// This register updates automatically each time a write
+// completes. The current value is the next address to be written
+// by this channel.
+#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4)
+#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000)
+#define DMA_CH11_WRITE_ADDR_MSB _u(31)
+#define DMA_CH11_WRITE_ADDR_LSB _u(0)
+#define DMA_CH11_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_TRANS_COUNT
+// Description : DMA Channel 11 Transfer Count
+// Program the number of bus transfers a channel will perform
+// before halting. Note that, if transfers are larger than one
+// byte in size, this is not equal to the number of bytes
+// transferred (see CTRL_DATA_SIZE).
+//
+// When the channel is active, reading this register shows the
+// number of transfers remaining, updating automatically each time
+// a write transfer completes.
+//
+// Writing this register sets the RELOAD value for the transfer
+// counter. Each time this channel is triggered, the RELOAD value
+// is copied into the live transfer counter. The channel can be
+// started multiple times, and will perform the same number of
+// transfers each time, as programmed by most recent write.
+//
+// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT
+// is used as a trigger, the written value is used immediately as
+// the length of the new transfer sequence, as well as being
+// written to RELOAD.
+#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8)
+#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000)
+#define DMA_CH11_TRANS_COUNT_MSB _u(31)
+#define DMA_CH11_TRANS_COUNT_LSB _u(0)
+#define DMA_CH11_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_CTRL_TRIG
+// Description : DMA Channel 11 Control and Status
+#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc)
+#define DMA_CH11_CTRL_TRIG_BITS _u(0xe1ffffff)
+#define DMA_CH11_CTRL_TRIG_RESET _u(0x00005800)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_AHB_ERROR
+// Description : Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel
+// halts when it encounters any bus error, and always raises its
+// channel IRQ flag.
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31)
+#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_READ_ERROR
+// Description : If 1, the channel received a read bus error. Write one to
+// clear.
+// READ_ADDR shows the approximate address where the bus error was
+// encountered (will not to be earlier, or more than 3 transfers
+// later)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30)
+#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_WRITE_ERROR
+// Description : If 1, the channel received a write bus error. Write one to
+// clear.
+// WRITE_ADDR shows the approximate address where the bus error
+// was encountered (will not to be earlier, or more than 5
+// transfers later)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29)
+#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_BUSY
+// Description : This flag goes high when the channel starts a new transfer
+// sequence, and low when the last transfer of that sequence
+// completes. Clearing EN while BUSY is high pauses the channel,
+// and BUSY will stay high while paused.
+//
+// To terminate a sequence early (and clear the BUSY flag), see
+// CHAN_ABORT.
+#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x01000000)
+#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(24)
+#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(24)
+#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_SNIFF_EN
+// Description : If 1, this channel's data transfers are visible to the sniff
+// hardware, and each transfer will advance the state of the
+// checksum. This only applies if the sniff hardware is enabled,
+// and has this channel selected.
+//
+// This allows checksum to be enabled or disabled on a
+// per-control- block basis.
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x00800000)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(23)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(23)
+#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_BSWAP
+// Description : Apply byte-swap transformation to DMA data.
+// For byte data, this has no effect. For halfword data, the two
+// bytes of each halfword are swapped. For word data, the four
+// bytes of each word are swapped to reverse order.
+#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x00400000)
+#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(22)
+#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(22)
+#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_IRQ_QUIET
+// Description : In QUIET mode, the channel does not generate IRQs at the end of
+// every transfer block. Instead, an IRQ is raised when NULL is
+// written to a trigger register, indicating the end of a control
+// block chain.
+//
+// This reduces the number of interrupts to be serviced by the CPU
+// when transferring a DMA chain of many small control blocks.
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00200000)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(21)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(21)
+#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_TREQ_SEL
+// Description : Select a Transfer Request signal.
+// The channel uses the transfer request signal to pace its data
+// transfer rate. Sources for TREQ signals are internal (TIMERS)
+// or external (DREQ, a Data Request from the system).
+// 0x0 to 0x3a -> select DREQ n as TREQ
+// 0x3b -> Select Timer 0 as TREQ
+// 0x3c -> Select Timer 1 as TREQ
+// 0x3d -> Select Timer 2 as TREQ (Optional)
+// 0x3e -> Select Timer 3 as TREQ (Optional)
+// 0x3f -> Permanent request, for unpaced transfers.
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x001f8000)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(20)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(15)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW"
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)
+#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_CHAIN_TO
+// Description : When this channel completes, it will trigger the channel
+// indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this
+// channel)_.
+// Reset value is equal to channel number (11).
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0xb)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x00007800)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(14)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(11)
+#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_RING_SEL
+// Description : Select whether RING_SIZE applies to read or write addresses.
+// If 0, read addresses are wrapped on a (1 << RING_SIZE)
+// boundary. If 1, write addresses are wrapped.
+#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00000400)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(10)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(10)
+#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_RING_SIZE
+// Description : Size of address wrap region. If 0, don't wrap. For values n >
+// 0, only the lower n bits of the address will change. This wraps
+// the address on a (1 << n) byte boundary, facilitating access to
+// naturally-aligned ring buffers.
+//
+// Ring sizes between 2 and 32768 bytes are possible. This can
+// apply to either read or write addresses, based on value of
+// RING_SEL.
+// 0x0 -> RING_NONE
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x000003c0)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(9)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(6)
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW"
+#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_INCR_WRITE
+// Description : If 1, the write address increments with each transfer. If 0,
+// each write is directed to the same, initial address.
+//
+// Generally this should be disabled for memory-to-peripheral
+// transfers.
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000020)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(5)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(5)
+#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_INCR_READ
+// Description : If 1, the read address increments with each transfer. If 0,
+// each read is directed to the same, initial address.
+//
+// Generally this should be disabled for peripheral-to-memory
+// transfers.
+#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4)
+#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_DATA_SIZE
+// Description : Set the size of each bus transfer (byte/halfword/word).
+// READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes)
+// with each transfer.
+// 0x0 -> SIZE_BYTE
+// 0x1 -> SIZE_HALFWORD
+// 0x2 -> SIZE_WORD
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW"
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)
+#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_HIGH_PRIORITY
+// Description : HIGH_PRIORITY gives a channel preferential treatment in issue
+// scheduling: in each scheduling round, all high priority
+// channels are considered first, and then only a single low
+// priority channel, before returning to the high priority
+// channels.
+//
+// This only affects the order in which the DMA schedules
+// channels. The DMA's bus priority is not changed. If the DMA is
+// not saturated then a low priority channel will see no loss of
+// throughput.
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)
+#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_CH11_CTRL_TRIG_EN
+// Description : DMA Channel Enable.
+// When 1, the channel will respond to triggering events, which
+// will cause it to become BUSY and start transferring data. When
+// 0, the channel will ignore triggers, stop issuing transfers,
+// and pause the current transfer sequence (i.e. BUSY will remain
+// high if already high)
+#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0)
+#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001)
+#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0)
+#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0)
+#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL1_CTRL
+// Description : Alias for channel 11 CTRL register
+#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0)
+#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff)
+#define DMA_CH11_AL1_CTRL_RESET "-"
+#define DMA_CH11_AL1_CTRL_MSB _u(31)
+#define DMA_CH11_AL1_CTRL_LSB _u(0)
+#define DMA_CH11_AL1_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL1_READ_ADDR
+// Description : Alias for channel 11 READ_ADDR register
+#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4)
+#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_AL1_READ_ADDR_RESET "-"
+#define DMA_CH11_AL1_READ_ADDR_MSB _u(31)
+#define DMA_CH11_AL1_READ_ADDR_LSB _u(0)
+#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL1_WRITE_ADDR
+// Description : Alias for channel 11 WRITE_ADDR register
+#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8)
+#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_AL1_WRITE_ADDR_RESET "-"
+#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31)
+#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0)
+#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL1_TRANS_COUNT_TRIG
+// Description : Alias for channel 11 TRANS_COUNT register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-"
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0)
+#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL2_CTRL
+// Description : Alias for channel 11 CTRL register
+#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0)
+#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff)
+#define DMA_CH11_AL2_CTRL_RESET "-"
+#define DMA_CH11_AL2_CTRL_MSB _u(31)
+#define DMA_CH11_AL2_CTRL_LSB _u(0)
+#define DMA_CH11_AL2_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL2_TRANS_COUNT
+// Description : Alias for channel 11 TRANS_COUNT register
+#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4)
+#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH11_AL2_TRANS_COUNT_RESET "-"
+#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31)
+#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0)
+#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL2_READ_ADDR
+// Description : Alias for channel 11 READ_ADDR register
+#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8)
+#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_AL2_READ_ADDR_RESET "-"
+#define DMA_CH11_AL2_READ_ADDR_MSB _u(31)
+#define DMA_CH11_AL2_READ_ADDR_LSB _u(0)
+#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL2_WRITE_ADDR_TRIG
+// Description : Alias for channel 11 WRITE_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-"
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0)
+#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL3_CTRL
+// Description : Alias for channel 11 CTRL register
+#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0)
+#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff)
+#define DMA_CH11_AL3_CTRL_RESET "-"
+#define DMA_CH11_AL3_CTRL_MSB _u(31)
+#define DMA_CH11_AL3_CTRL_LSB _u(0)
+#define DMA_CH11_AL3_CTRL_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL3_WRITE_ADDR
+// Description : Alias for channel 11 WRITE_ADDR register
+#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4)
+#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff)
+#define DMA_CH11_AL3_WRITE_ADDR_RESET "-"
+#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31)
+#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0)
+#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL3_TRANS_COUNT
+// Description : Alias for channel 11 TRANS_COUNT register
+#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8)
+#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff)
+#define DMA_CH11_AL3_TRANS_COUNT_RESET "-"
+#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31)
+#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0)
+#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW"
+// =============================================================================
+// Register : DMA_CH11_AL3_READ_ADDR_TRIG
+// Description : Alias for channel 11 READ_ADDR register
+// This is a trigger register (0xc). Writing a nonzero value will
+// reload the channel counter and start the channel.
+#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-"
+#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0)
+#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW"
+// =============================================================================
+// Register : DMA_INTR
+// Description : Interrupt Status (raw)
+// Raw interrupt status for DMA Channels 0..15. Bit n corresponds
+// to channel n. Ignores any masking or forcing. Channel
+// interrupts can be cleared by writing a bit mask to INTR, INTS0
+// or INTS1.
+//
+// Channel interrupts can be routed to either of two system-level
+// IRQs based on INTE0 and INTE1.
+//
+// This can be used vector different channel interrupts to
+// different ISRs: this might be done to allow NVIC IRQ preemption
+// for more time-critical channels, or to spread IRQ load across
+// different cores.
+//
+// It is also valid to ignore this behaviour and just use
+// INTE0/INTS0/IRQ 0.
+#define DMA_INTR_OFFSET _u(0x00000400)
+#define DMA_INTR_BITS _u(0x0000ffff)
+#define DMA_INTR_RESET _u(0x00000000)
+#define DMA_INTR_MSB _u(15)
+#define DMA_INTR_LSB _u(0)
+#define DMA_INTR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_INTE0
+// Description : Interrupt Enables for IRQ 0
+// Set bit n to pass interrupts from channel n to DMA IRQ 0.
+#define DMA_INTE0_OFFSET _u(0x00000404)
+#define DMA_INTE0_BITS _u(0x0000ffff)
+#define DMA_INTE0_RESET _u(0x00000000)
+#define DMA_INTE0_MSB _u(15)
+#define DMA_INTE0_LSB _u(0)
+#define DMA_INTE0_ACCESS "RW"
+// =============================================================================
+// Register : DMA_INTF0
+// Description : Force Interrupts
+// Write 1s to force the corresponding bits in INTE0. The
+// interrupt remains asserted until INTF0 is cleared.
+#define DMA_INTF0_OFFSET _u(0x00000408)
+#define DMA_INTF0_BITS _u(0x0000ffff)
+#define DMA_INTF0_RESET _u(0x00000000)
+#define DMA_INTF0_MSB _u(15)
+#define DMA_INTF0_LSB _u(0)
+#define DMA_INTF0_ACCESS "RW"
+// =============================================================================
+// Register : DMA_INTS0
+// Description : Interrupt Status for IRQ 0
+// Indicates active channel interrupt requests which are currently
+// causing IRQ 0 to be asserted.
+// Channel interrupts can be cleared by writing a bit mask here.
+#define DMA_INTS0_OFFSET _u(0x0000040c)
+#define DMA_INTS0_BITS _u(0x0000ffff)
+#define DMA_INTS0_RESET _u(0x00000000)
+#define DMA_INTS0_MSB _u(15)
+#define DMA_INTS0_LSB _u(0)
+#define DMA_INTS0_ACCESS "WC"
+// =============================================================================
+// Register : DMA_INTE1
+// Description : Interrupt Enables for IRQ 1
+// Set bit n to pass interrupts from channel n to DMA IRQ 1.
+#define DMA_INTE1_OFFSET _u(0x00000414)
+#define DMA_INTE1_BITS _u(0x0000ffff)
+#define DMA_INTE1_RESET _u(0x00000000)
+#define DMA_INTE1_MSB _u(15)
+#define DMA_INTE1_LSB _u(0)
+#define DMA_INTE1_ACCESS "RW"
+// =============================================================================
+// Register : DMA_INTF1
+// Description : Force Interrupts for IRQ 1
+// Write 1s to force the corresponding bits in INTE0. The
+// interrupt remains asserted until INTF0 is cleared.
+#define DMA_INTF1_OFFSET _u(0x00000418)
+#define DMA_INTF1_BITS _u(0x0000ffff)
+#define DMA_INTF1_RESET _u(0x00000000)
+#define DMA_INTF1_MSB _u(15)
+#define DMA_INTF1_LSB _u(0)
+#define DMA_INTF1_ACCESS "RW"
+// =============================================================================
+// Register : DMA_INTS1
+// Description : Interrupt Status (masked) for IRQ 1
+// Indicates active channel interrupt requests which are currently
+// causing IRQ 1 to be asserted.
+// Channel interrupts can be cleared by writing a bit mask here.
+#define DMA_INTS1_OFFSET _u(0x0000041c)
+#define DMA_INTS1_BITS _u(0x0000ffff)
+#define DMA_INTS1_RESET _u(0x00000000)
+#define DMA_INTS1_MSB _u(15)
+#define DMA_INTS1_LSB _u(0)
+#define DMA_INTS1_ACCESS "WC"
+// =============================================================================
+// Register : DMA_TIMER0
+// Description : Pacing (X/Y) Fractional Timer
+// The pacing timer produces TREQ assertions at a rate set by
+// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+// cycles and therefore can only generate TREQs at a rate of 1 per
+// sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER0_OFFSET _u(0x00000420)
+#define DMA_TIMER0_BITS _u(0xffffffff)
+#define DMA_TIMER0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER0_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER0_X_RESET _u(0x0000)
+#define DMA_TIMER0_X_BITS _u(0xffff0000)
+#define DMA_TIMER0_X_MSB _u(31)
+#define DMA_TIMER0_X_LSB _u(16)
+#define DMA_TIMER0_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER0_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER0_Y_RESET _u(0x0000)
+#define DMA_TIMER0_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER0_Y_MSB _u(15)
+#define DMA_TIMER0_Y_LSB _u(0)
+#define DMA_TIMER0_Y_ACCESS "RW"
+// =============================================================================
+// Register : DMA_TIMER1
+// Description : Pacing (X/Y) Fractional Timer
+// The pacing timer produces TREQ assertions at a rate set by
+// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+// cycles and therefore can only generate TREQs at a rate of 1 per
+// sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER1_OFFSET _u(0x00000424)
+#define DMA_TIMER1_BITS _u(0xffffffff)
+#define DMA_TIMER1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER1_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER1_X_RESET _u(0x0000)
+#define DMA_TIMER1_X_BITS _u(0xffff0000)
+#define DMA_TIMER1_X_MSB _u(31)
+#define DMA_TIMER1_X_LSB _u(16)
+#define DMA_TIMER1_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER1_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER1_Y_RESET _u(0x0000)
+#define DMA_TIMER1_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER1_Y_MSB _u(15)
+#define DMA_TIMER1_Y_LSB _u(0)
+#define DMA_TIMER1_Y_ACCESS "RW"
+// =============================================================================
+// Register : DMA_TIMER2
+// Description : Pacing (X/Y) Fractional Timer
+// The pacing timer produces TREQ assertions at a rate set by
+// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+// cycles and therefore can only generate TREQs at a rate of 1 per
+// sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER2_OFFSET _u(0x00000428)
+#define DMA_TIMER2_BITS _u(0xffffffff)
+#define DMA_TIMER2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER2_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER2_X_RESET _u(0x0000)
+#define DMA_TIMER2_X_BITS _u(0xffff0000)
+#define DMA_TIMER2_X_MSB _u(31)
+#define DMA_TIMER2_X_LSB _u(16)
+#define DMA_TIMER2_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER2_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER2_Y_RESET _u(0x0000)
+#define DMA_TIMER2_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER2_Y_MSB _u(15)
+#define DMA_TIMER2_Y_LSB _u(0)
+#define DMA_TIMER2_Y_ACCESS "RW"
+// =============================================================================
+// Register : DMA_TIMER3
+// Description : Pacing (X/Y) Fractional Timer
+// The pacing timer produces TREQ assertions at a rate set by
+// ((X/Y) * sys_clk). This equation is evaluated every sys_clk
+// cycles and therefore can only generate TREQs at a rate of 1 per
+// sys_clk (i.e. permanent TREQ) or less.
+#define DMA_TIMER3_OFFSET _u(0x0000042c)
+#define DMA_TIMER3_BITS _u(0xffffffff)
+#define DMA_TIMER3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER3_X
+// Description : Pacing Timer Dividend. Specifies the X value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER3_X_RESET _u(0x0000)
+#define DMA_TIMER3_X_BITS _u(0xffff0000)
+#define DMA_TIMER3_X_MSB _u(31)
+#define DMA_TIMER3_X_LSB _u(16)
+#define DMA_TIMER3_X_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_TIMER3_Y
+// Description : Pacing Timer Divisor. Specifies the Y value for the (X/Y)
+// fractional timer.
+#define DMA_TIMER3_Y_RESET _u(0x0000)
+#define DMA_TIMER3_Y_BITS _u(0x0000ffff)
+#define DMA_TIMER3_Y_MSB _u(15)
+#define DMA_TIMER3_Y_LSB _u(0)
+#define DMA_TIMER3_Y_ACCESS "RW"
+// =============================================================================
+// Register : DMA_MULTI_CHAN_TRIGGER
+// Description : Trigger one or more channels simultaneously
+// Each bit in this register corresponds to a DMA channel. Writing
+// a 1 to the relevant bit is the same as writing to that
+// channel's trigger register; the channel will start if it is
+// currently enabled and not already busy.
+#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000430)
+#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff)
+#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000)
+#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15)
+#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0)
+#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC"
+// =============================================================================
+// Register : DMA_SNIFF_CTRL
+// Description : Sniffer Control
+#define DMA_SNIFF_CTRL_OFFSET _u(0x00000434)
+#define DMA_SNIFF_CTRL_BITS _u(0x00000fff)
+#define DMA_SNIFF_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : DMA_SNIFF_CTRL_OUT_INV
+// Description : If set, the result appears inverted (bitwise complement) when
+// read. This does not affect the way the checksum is calculated;
+// the result is transformed on-the-fly between the result
+// register and the bus.
+#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800)
+#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11)
+#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11)
+#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_SNIFF_CTRL_OUT_REV
+// Description : If set, the result appears bit-reversed when read. This does
+// not affect the way the checksum is calculated; the result is
+// transformed on-the-fly between the result register and the bus.
+#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400)
+#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10)
+#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10)
+#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_SNIFF_CTRL_BSWAP
+// Description : Locally perform a byte reverse on the sniffed data, before
+// feeding into checksum.
+//
+// Note that the sniff hardware is downstream of the DMA channel
+// byteswap performed in the read master: if channel CTRL_BSWAP
+// and SNIFF_CTRL_BSWAP are both enabled, their effects cancel
+// from the sniffer's point of view.
+#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200)
+#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9)
+#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9)
+#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_SNIFF_CTRL_CALC
+// Description : 0x0 -> Calculate a CRC-32 (IEEE802.3 polynomial)
+// 0x1 -> Calculate a CRC-32 (IEEE802.3 polynomial) with bit
+// reversed data
+// 0x2 -> Calculate a CRC-16-CCITT
+// 0x3 -> Calculate a CRC-16-CCITT with bit reversed data
+// 0xe -> XOR reduction over all data. == 1 if the total 1
+// population count is odd.
+// 0xf -> Calculate a simple 32-bit checksum (addition with a 32
+// bit accumulator)
+#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0)
+#define DMA_SNIFF_CTRL_CALC_MSB _u(8)
+#define DMA_SNIFF_CTRL_CALC_LSB _u(5)
+#define DMA_SNIFF_CTRL_CALC_ACCESS "RW"
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2)
+#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3)
+#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe)
+#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf)
+// -----------------------------------------------------------------------------
+// Field : DMA_SNIFF_CTRL_DMACH
+// Description : DMA channel for Sniffer to observe
+#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e)
+#define DMA_SNIFF_CTRL_DMACH_MSB _u(4)
+#define DMA_SNIFF_CTRL_DMACH_LSB _u(1)
+#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : DMA_SNIFF_CTRL_EN
+// Description : Enable sniffer
+#define DMA_SNIFF_CTRL_EN_RESET _u(0x0)
+#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001)
+#define DMA_SNIFF_CTRL_EN_MSB _u(0)
+#define DMA_SNIFF_CTRL_EN_LSB _u(0)
+#define DMA_SNIFF_CTRL_EN_ACCESS "RW"
+// =============================================================================
+// Register : DMA_SNIFF_DATA
+// Description : Data accumulator for sniff hardware
+// Write an initial seed value here before starting a DMA transfer
+// on the channel indicated by SNIFF_CTRL_DMACH. The hardware will
+// update this register each time it observes a read from the
+// indicated channel. Once the channel completes, the final result
+// can be read from this register.
+#define DMA_SNIFF_DATA_OFFSET _u(0x00000438)
+#define DMA_SNIFF_DATA_BITS _u(0xffffffff)
+#define DMA_SNIFF_DATA_RESET _u(0x00000000)
+#define DMA_SNIFF_DATA_MSB _u(31)
+#define DMA_SNIFF_DATA_LSB _u(0)
+#define DMA_SNIFF_DATA_ACCESS "RW"
+// =============================================================================
+// Register : DMA_FIFO_LEVELS
+// Description : Debug RAF, WAF, TDF levels
+#define DMA_FIFO_LEVELS_OFFSET _u(0x00000440)
+#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff)
+#define DMA_FIFO_LEVELS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : DMA_FIFO_LEVELS_RAF_LVL
+// Description : Current Read-Address-FIFO fill level
+#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00)
+#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000)
+#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23)
+#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16)
+#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_FIFO_LEVELS_WAF_LVL
+// Description : Current Write-Address-FIFO fill level
+#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00)
+#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00)
+#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15)
+#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8)
+#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : DMA_FIFO_LEVELS_TDF_LVL
+// Description : Current Transfer-Data-FIFO fill level
+#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00)
+#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff)
+#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7)
+#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0)
+#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CHAN_ABORT
+// Description : Abort an in-progress transfer sequence on one or more channels
+// Each bit corresponds to a channel. Writing a 1 aborts whatever
+// transfer sequence is in progress on that channel. The bit will
+// remain high until any in-flight transfers have been flushed
+// through the address and data FIFOs.
+//
+// After writing, this register must be polled until it returns
+// all-zero. Until this point, it is unsafe to restart the
+// channel.
+#define DMA_CHAN_ABORT_OFFSET _u(0x00000444)
+#define DMA_CHAN_ABORT_BITS _u(0x0000ffff)
+#define DMA_CHAN_ABORT_RESET _u(0x00000000)
+#define DMA_CHAN_ABORT_MSB _u(15)
+#define DMA_CHAN_ABORT_LSB _u(0)
+#define DMA_CHAN_ABORT_ACCESS "SC"
+// =============================================================================
+// Register : DMA_N_CHANNELS
+// Description : The number of channels this DMA instance is equipped with. This
+// DMA supports up to 16 hardware channels, but can be configured
+// with as few as one, to minimise silicon area.
+#define DMA_N_CHANNELS_OFFSET _u(0x00000448)
+#define DMA_N_CHANNELS_BITS _u(0x0000001f)
+#define DMA_N_CHANNELS_RESET "-"
+#define DMA_N_CHANNELS_MSB _u(4)
+#define DMA_N_CHANNELS_LSB _u(0)
+#define DMA_N_CHANNELS_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH0_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800)
+#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH0_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH0_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH0_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH0_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804)
+#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH0_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH0_DBG_TCR_MSB _u(31)
+#define DMA_CH0_DBG_TCR_LSB _u(0)
+#define DMA_CH0_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH1_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840)
+#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH1_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH1_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH1_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH1_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844)
+#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH1_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH1_DBG_TCR_MSB _u(31)
+#define DMA_CH1_DBG_TCR_LSB _u(0)
+#define DMA_CH1_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH2_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880)
+#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH2_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH2_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH2_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH2_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884)
+#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH2_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH2_DBG_TCR_MSB _u(31)
+#define DMA_CH2_DBG_TCR_LSB _u(0)
+#define DMA_CH2_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH3_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0)
+#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH3_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH3_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH3_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH3_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4)
+#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH3_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH3_DBG_TCR_MSB _u(31)
+#define DMA_CH3_DBG_TCR_LSB _u(0)
+#define DMA_CH3_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH4_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900)
+#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH4_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH4_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH4_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH4_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904)
+#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH4_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH4_DBG_TCR_MSB _u(31)
+#define DMA_CH4_DBG_TCR_LSB _u(0)
+#define DMA_CH4_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH5_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940)
+#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH5_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH5_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH5_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH5_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944)
+#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH5_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH5_DBG_TCR_MSB _u(31)
+#define DMA_CH5_DBG_TCR_LSB _u(0)
+#define DMA_CH5_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH6_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980)
+#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH6_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH6_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH6_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH6_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984)
+#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH6_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH6_DBG_TCR_MSB _u(31)
+#define DMA_CH6_DBG_TCR_LSB _u(0)
+#define DMA_CH6_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH7_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0)
+#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH7_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH7_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH7_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH7_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4)
+#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH7_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH7_DBG_TCR_MSB _u(31)
+#define DMA_CH7_DBG_TCR_LSB _u(0)
+#define DMA_CH7_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH8_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00)
+#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH8_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH8_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH8_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH8_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04)
+#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH8_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH8_DBG_TCR_MSB _u(31)
+#define DMA_CH8_DBG_TCR_LSB _u(0)
+#define DMA_CH8_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH9_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40)
+#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH9_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH9_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH9_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH9_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44)
+#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH9_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH9_DBG_TCR_MSB _u(31)
+#define DMA_CH9_DBG_TCR_LSB _u(0)
+#define DMA_CH9_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH10_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80)
+#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH10_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH10_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH10_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH10_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84)
+#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH10_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH10_DBG_TCR_MSB _u(31)
+#define DMA_CH10_DBG_TCR_LSB _u(0)
+#define DMA_CH10_DBG_TCR_ACCESS "RO"
+// =============================================================================
+// Register : DMA_CH11_DBG_CTDREQ
+// Description : Read: get channel DREQ counter (i.e. how many accesses the DMA
+// expects it can perform on the peripheral without
+// overflow/underflow. Write any value: clears the counter, and
+// cause channel to re-initiate DREQ handshake.
+#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0)
+#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f)
+#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000)
+#define DMA_CH11_DBG_CTDREQ_MSB _u(5)
+#define DMA_CH11_DBG_CTDREQ_LSB _u(0)
+#define DMA_CH11_DBG_CTDREQ_ACCESS "WC"
+// =============================================================================
+// Register : DMA_CH11_DBG_TCR
+// Description : Read to get channel TRANS_COUNT reload value, i.e. the length
+// of the next transfer
+#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4)
+#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff)
+#define DMA_CH11_DBG_TCR_RESET _u(0x00000000)
+#define DMA_CH11_DBG_TCR_MSB _u(31)
+#define DMA_CH11_DBG_TCR_LSB _u(0)
+#define DMA_CH11_DBG_TCR_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_DMA_DEFINED
diff --git a/arkanoid/pico/hardware/regs/dreq.h b/arkanoid/pico/hardware/regs/dreq.h
new file mode 100644
index 0000000..9de9dd5
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/dreq.h
@@ -0,0 +1,50 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _DREQ_H_
+#define _DREQ_H_
+
+#define DREQ_PIO0_TX0 0x0
+#define DREQ_PIO0_TX1 0x1
+#define DREQ_PIO0_TX2 0x2
+#define DREQ_PIO0_TX3 0x3
+#define DREQ_PIO0_RX0 0x4
+#define DREQ_PIO0_RX1 0x5
+#define DREQ_PIO0_RX2 0x6
+#define DREQ_PIO0_RX3 0x7
+#define DREQ_PIO1_TX0 0x8
+#define DREQ_PIO1_TX1 0x9
+#define DREQ_PIO1_TX2 0xa
+#define DREQ_PIO1_TX3 0xb
+#define DREQ_PIO1_RX0 0xc
+#define DREQ_PIO1_RX1 0xd
+#define DREQ_PIO1_RX2 0xe
+#define DREQ_PIO1_RX3 0xf
+#define DREQ_SPI0_TX 0x10
+#define DREQ_SPI0_RX 0x11
+#define DREQ_SPI1_TX 0x12
+#define DREQ_SPI1_RX 0x13
+#define DREQ_UART0_TX 0x14
+#define DREQ_UART0_RX 0x15
+#define DREQ_UART1_TX 0x16
+#define DREQ_UART1_RX 0x17
+#define DREQ_PWM_WRAP0 0x18
+#define DREQ_PWM_WRAP1 0x19
+#define DREQ_PWM_WRAP2 0x1a
+#define DREQ_PWM_WRAP3 0x1b
+#define DREQ_PWM_WRAP4 0x1c
+#define DREQ_PWM_WRAP5 0x1d
+#define DREQ_PWM_WRAP6 0x1e
+#define DREQ_PWM_WRAP7 0x1f
+#define DREQ_I2C0_TX 0x20
+#define DREQ_I2C0_RX 0x21
+#define DREQ_I2C1_TX 0x22
+#define DREQ_I2C1_RX 0x23
+#define DREQ_ADC 0x24
+#define DREQ_XIP_STREAM 0x25
+#define DREQ_XIP_SSITX 0x26
+#define DREQ_XIP_SSIRX 0x27
+
+#endif // _DREQ_H_
diff --git a/arkanoid/pico/hardware/regs/i2c.h b/arkanoid/pico/hardware/regs/i2c.h
new file mode 100644
index 0000000..dcddb06
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/i2c.h
@@ -0,0 +1,2713 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : I2C
+// Version : 1
+// Bus type : apb
+// Description : DW_apb_i2c address block
+//
+// List of configuration constants for the Synopsys I2C
+// hardware (you may see references to these in I2C register
+// header; these are *fixed* values, set at hardware design
+// time):
+//
+// IC_ULTRA_FAST_MODE ................ 0x0
+// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+// IC_UFM_SCL_LOW_COUNT .............. 0x0008
+// IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+// IC_TX_TL .......................... 0x0
+// IC_TX_CMD_BLOCK ................... 0x1
+// IC_HAS_DMA ........................ 0x1
+// IC_HAS_ASYNC_FIFO ................. 0x0
+// IC_SMBUS_ARP ...................... 0x0
+// IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+// IC_INTR_IO ........................ 0x1
+// IC_MASTER_MODE .................... 0x1
+// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+// IC_INTR_POL ....................... 0x1
+// IC_OPTIONAL_SAR ................... 0x0
+// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+// IC_DEFAULT_SLAVE_ADDR ............. 0x055
+// IC_DEFAULT_HS_SPKLEN .............. 0x1
+// IC_FS_SCL_HIGH_COUNT .............. 0x0006
+// IC_HS_SCL_LOW_COUNT ............... 0x0008
+// IC_DEVICE_ID_VALUE ................ 0x0
+// IC_10BITADDR_MASTER ............... 0x0
+// IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+// IC_DEFAULT_FS_SPKLEN .............. 0x7
+// IC_ADD_ENCODED_PARAMS ............. 0x0
+// IC_DEFAULT_SDA_HOLD ............... 0x000001
+// IC_DEFAULT_SDA_SETUP .............. 0x64
+// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+// IC_CLOCK_PERIOD ................... 100
+// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+// IC_RESTART_EN ..................... 0x1
+// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+// IC_BUS_CLEAR_FEATURE .............. 0x0
+// IC_CAP_LOADING .................... 100
+// IC_FS_SCL_LOW_COUNT ............... 0x000d
+// APB_DATA_WIDTH .................... 32
+// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+// IC_SLV_DATA_NACK_ONLY ............. 0x1
+// IC_10BITADDR_SLAVE ................ 0x0
+// IC_CLK_TYPE ....................... 0x0
+// IC_SMBUS_UDID_MSB ................. 0x0
+// IC_SMBUS_SUSPEND_ALERT ............ 0x0
+// IC_HS_SCL_HIGH_COUNT .............. 0x0006
+// IC_SLV_RESTART_DET_EN ............. 0x1
+// IC_SMBUS .......................... 0x0
+// IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+// IC_USE_COUNTS ..................... 0x0
+// IC_RX_BUFFER_DEPTH ................ 16
+// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+// IC_RX_FULL_HLD_BUS_EN ............. 0x1
+// IC_SLAVE_DISABLE .................. 0x1
+// IC_RX_TL .......................... 0x0
+// IC_DEVICE_ID ...................... 0x0
+// IC_HC_COUNT_VALUES ................ 0x0
+// I2C_DYNAMIC_TAR_UPDATE ............ 0
+// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+// IC_HS_MASTER_CODE ................. 0x1
+// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+// IC_SS_SCL_HIGH_COUNT .............. 0x0028
+// IC_SS_SCL_LOW_COUNT ............... 0x002f
+// IC_MAX_SPEED_MODE ................. 0x2
+// IC_STAT_FOR_CLK_STRETCH ........... 0x0
+// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+// IC_DEFAULT_UFM_SPKLEN ............. 0x1
+// IC_TX_BUFFER_DEPTH ................ 16
+// =============================================================================
+#ifndef HARDWARE_REGS_I2C_DEFINED
+#define HARDWARE_REGS_I2C_DEFINED
+// =============================================================================
+// Register : I2C_IC_CON
+// Description : I2C Control Register. This register can be written only when
+// the DW_apb_i2c is disabled, which corresponds to the
+// IC_ENABLE[0] register being set to 0. Writes at other times
+// have no effect.
+//
+// Read/Write Access: - bit 10 is read only. - bit 11 is read only
+// - bit 16 is read only - bit 17 is read only - bits 18 and 19
+// are read only.
+#define I2C_IC_CON_OFFSET _u(0x00000000)
+#define I2C_IC_CON_BITS _u(0x000007ff)
+#define I2C_IC_CON_RESET _u(0x00000065)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE
+// Description : Master issues the STOP_DET interrupt irrespective of whether
+// master is active or not
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_RESET _u(0x0)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_BITS _u(0x00000400)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_MSB _u(10)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_LSB _u(10)
+#define I2C_IC_CON_STOP_DET_IF_MASTER_ACTIVE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL
+// Description : This bit controls whether DW_apb_i2c should hold the bus when
+// the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as
+// described in the IC_RX_FULL_HLD_BUS_EN parameter.
+//
+// Reset value: 0x0.
+// 0x0 -> Overflow when RX_FIFO is full
+// 0x1 -> Hold bus when RX_FIFO is full
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_RESET _u(0x0)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_BITS _u(0x00000200)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_MSB _u(9)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_LSB _u(9)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_ACCESS "RW"
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_RX_FIFO_FULL_HLD_CTRL_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_TX_EMPTY_CTRL
+// Description : This bit controls the generation of the TX_EMPTY interrupt, as
+// described in the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0.
+// 0x0 -> Default behaviour of TX_EMPTY interrupt
+// 0x1 -> Controlled generation of TX_EMPTY interrupt
+#define I2C_IC_CON_TX_EMPTY_CTRL_RESET _u(0x0)
+#define I2C_IC_CON_TX_EMPTY_CTRL_BITS _u(0x00000100)
+#define I2C_IC_CON_TX_EMPTY_CTRL_MSB _u(8)
+#define I2C_IC_CON_TX_EMPTY_CTRL_LSB _u(8)
+#define I2C_IC_CON_TX_EMPTY_CTRL_ACCESS "RW"
+#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_TX_EMPTY_CTRL_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_STOP_DET_IFADDRESSED
+// Description : In slave mode: - 1'b1: issues the STOP_DET interrupt only when
+// it is addressed. - 1'b0: issues the STOP_DET irrespective of
+// whether it's addressed or not. Reset value: 0x0
+//
+// NOTE: During a general call address, this slave does not issue
+// the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if
+// the slave responds to the general call address by generating
+// ACK. The STOP_DET interrupt is generated only when the
+// transmitted address matches the slave address (SAR).
+// 0x0 -> slave issues STOP_DET intr always
+// 0x1 -> slave issues STOP_DET intr only if addressed
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_RESET _u(0x0)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_BITS _u(0x00000080)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_MSB _u(7)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_LSB _u(7)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_ACCESS "RW"
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_STOP_DET_IFADDRESSED_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_IC_SLAVE_DISABLE
+// Description : This bit controls whether I2C has its slave disabled, which
+// means once the presetn signal is applied, then this bit is set
+// and the slave is disabled.
+//
+// If this bit is set (slave is disabled), DW_apb_i2c functions
+// only as a master and does not perform any action that requires
+// a slave.
+//
+// NOTE: Software should ensure that if this bit is written with
+// 0, then bit 0 should also be written with a 0.
+// 0x0 -> Slave mode is enabled
+// 0x1 -> Slave mode is disabled
+#define I2C_IC_CON_IC_SLAVE_DISABLE_RESET _u(0x1)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_BITS _u(0x00000040)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_MSB _u(6)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_LSB _u(6)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_ACCESS "RW"
+#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_ENABLED _u(0x0)
+#define I2C_IC_CON_IC_SLAVE_DISABLE_VALUE_SLAVE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_IC_RESTART_EN
+// Description : Determines whether RESTART conditions may be sent when acting
+// as a master. Some older slaves do not support handling RESTART
+// conditions; however, RESTART conditions are used in several
+// DW_apb_i2c operations. When RESTART is disabled, the master is
+// prohibited from performing the following functions: - Sending a
+// START BYTE - Performing any high-speed mode operation -
+// High-speed mode operation - Performing direction changes in
+// combined format mode - Performing a read operation with a
+// 10-bit address By replacing RESTART condition followed by a
+// STOP and a subsequent START condition, split operations are
+// broken down into multiple DW_apb_i2c transfers. If the above
+// operations are performed, it will result in setting bit 6
+// (TX_ABRT) of the IC_RAW_INTR_STAT register.
+//
+// Reset value: ENABLED
+// 0x0 -> Master restart disabled
+// 0x1 -> Master restart enabled
+#define I2C_IC_CON_IC_RESTART_EN_RESET _u(0x1)
+#define I2C_IC_CON_IC_RESTART_EN_BITS _u(0x00000020)
+#define I2C_IC_CON_IC_RESTART_EN_MSB _u(5)
+#define I2C_IC_CON_IC_RESTART_EN_LSB _u(5)
+#define I2C_IC_CON_IC_RESTART_EN_ACCESS "RW"
+#define I2C_IC_CON_IC_RESTART_EN_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_IC_RESTART_EN_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_IC_10BITADDR_MASTER
+// Description : Controls whether the DW_apb_i2c starts its transfers in 7- or
+// 10-bit addressing mode when acting as a master. - 0: 7-bit
+// addressing - 1: 10-bit addressing
+// 0x0 -> Master 7Bit addressing mode
+// 0x1 -> Master 10Bit addressing mode
+#define I2C_IC_CON_IC_10BITADDR_MASTER_RESET _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_BITS _u(0x00000010)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_MSB _u(4)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_LSB _u(4)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_ACCESS "RW"
+#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_7BITS _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_MASTER_VALUE_ADDR_10BITS _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_IC_10BITADDR_SLAVE
+// Description : When acting as a slave, this bit controls whether the
+// DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit
+// addressing. The DW_apb_i2c ignores transactions that involve
+// 10-bit addressing; for 7-bit addressing, only the lower 7 bits
+// of the IC_SAR register are compared. - 1: 10-bit addressing.
+// The DW_apb_i2c responds to only 10-bit addressing transfers
+// that match the full 10 bits of the IC_SAR register.
+// 0x0 -> Slave 7Bit addressing
+// 0x1 -> Slave 10Bit addressing
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_RESET _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_BITS _u(0x00000008)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_MSB _u(3)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_LSB _u(3)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_ACCESS "RW"
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_7BITS _u(0x0)
+#define I2C_IC_CON_IC_10BITADDR_SLAVE_VALUE_ADDR_10BITS _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_SPEED
+// Description : These bits control at which speed the DW_apb_i2c operates; its
+// setting is relevant only if one is operating the DW_apb_i2c in
+// master mode. Hardware protects against illegal values being
+// programmed by software. These bits must be programmed
+// appropriately for slave mode also, as it is used to capture
+// correct value of spike filter as per the speed mode.
+//
+// This register should be programmed only with a value in the
+// range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates
+// this register with the value of IC_MAX_SPEED_MODE.
+//
+// 1: standard mode (100 kbit/s)
+//
+// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
+//
+// 3: high speed mode (3.4 Mbit/s)
+//
+// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
+// 0x1 -> Standard Speed mode of operation
+// 0x2 -> Fast or Fast Plus mode of operation
+// 0x3 -> High Speed mode of operation
+#define I2C_IC_CON_SPEED_RESET _u(0x2)
+#define I2C_IC_CON_SPEED_BITS _u(0x00000006)
+#define I2C_IC_CON_SPEED_MSB _u(2)
+#define I2C_IC_CON_SPEED_LSB _u(1)
+#define I2C_IC_CON_SPEED_ACCESS "RW"
+#define I2C_IC_CON_SPEED_VALUE_STANDARD _u(0x1)
+#define I2C_IC_CON_SPEED_VALUE_FAST _u(0x2)
+#define I2C_IC_CON_SPEED_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CON_MASTER_MODE
+// Description : This bit controls whether the DW_apb_i2c master is enabled.
+//
+// NOTE: Software should ensure that if this bit is written with
+// '1' then bit 6 should also be written with a '1'.
+// 0x0 -> Master mode is disabled
+// 0x1 -> Master mode is enabled
+#define I2C_IC_CON_MASTER_MODE_RESET _u(0x1)
+#define I2C_IC_CON_MASTER_MODE_BITS _u(0x00000001)
+#define I2C_IC_CON_MASTER_MODE_MSB _u(0)
+#define I2C_IC_CON_MASTER_MODE_LSB _u(0)
+#define I2C_IC_CON_MASTER_MODE_ACCESS "RW"
+#define I2C_IC_CON_MASTER_MODE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_CON_MASTER_MODE_VALUE_ENABLED _u(0x1)
+// =============================================================================
+// Register : I2C_IC_TAR
+// Description : I2C Target Address Register
+//
+// This register is 12 bits wide, and bits 31:12 are reserved.
+// This register can be written to only when IC_ENABLE[0] is set
+// to 0.
+//
+// Note: If the software or application is aware that the
+// DW_apb_i2c is not using the TAR address for the pending
+// commands in the Tx FIFO, then it is possible to update the TAR
+// address even while the Tx FIFO has entries (IC_STATUS[2]= 0). -
+// It is not necessary to perform any write to this register if
+// DW_apb_i2c is enabled as an I2C slave only.
+#define I2C_IC_TAR_OFFSET _u(0x00000004)
+#define I2C_IC_TAR_BITS _u(0x00000fff)
+#define I2C_IC_TAR_RESET _u(0x00000055)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TAR_SPECIAL
+// Description : This bit indicates whether software performs a Device-ID or
+// General Call or START BYTE command. - 0: ignore bit 10
+// GC_OR_START and use IC_TAR normally - 1: perform special I2C
+// command as specified in Device_ID or GC_OR_START bit Reset
+// value: 0x0
+// 0x0 -> Disables programming of GENERAL_CALL or START_BYTE
+// transmission
+// 0x1 -> Enables programming of GENERAL_CALL or START_BYTE
+// transmission
+#define I2C_IC_TAR_SPECIAL_RESET _u(0x0)
+#define I2C_IC_TAR_SPECIAL_BITS _u(0x00000800)
+#define I2C_IC_TAR_SPECIAL_MSB _u(11)
+#define I2C_IC_TAR_SPECIAL_LSB _u(11)
+#define I2C_IC_TAR_SPECIAL_ACCESS "RW"
+#define I2C_IC_TAR_SPECIAL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_TAR_SPECIAL_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TAR_GC_OR_START
+// Description : If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to
+// 0, then this bit indicates whether a General Call or START byte
+// command is to be performed by the DW_apb_i2c. - 0: General Call
+// Address - after issuing a General Call, only writes may be
+// performed. Attempting to issue a read command results in
+// setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The
+// DW_apb_i2c remains in General Call mode until the SPECIAL bit
+// value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
+// 0x0 -> GENERAL_CALL byte transmission
+// 0x1 -> START byte transmission
+#define I2C_IC_TAR_GC_OR_START_RESET _u(0x0)
+#define I2C_IC_TAR_GC_OR_START_BITS _u(0x00000400)
+#define I2C_IC_TAR_GC_OR_START_MSB _u(10)
+#define I2C_IC_TAR_GC_OR_START_LSB _u(10)
+#define I2C_IC_TAR_GC_OR_START_ACCESS "RW"
+#define I2C_IC_TAR_GC_OR_START_VALUE_GENERAL_CALL _u(0x0)
+#define I2C_IC_TAR_GC_OR_START_VALUE_START_BYTE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TAR_IC_TAR
+// Description : This is the target address for any master transaction. When
+// transmitting a General Call, these bits are ignored. To
+// generate a START BYTE, the CPU needs to write only once into
+// these bits.
+//
+// If the IC_TAR and IC_SAR are the same, loopback exists but the
+// FIFOs are shared between master and slave, so full loopback is
+// not feasible. Only one direction loopback mode is supported
+// (simplex), not duplex. A master cannot transmit to itself; it
+// can transmit to only a slave.
+#define I2C_IC_TAR_IC_TAR_RESET _u(0x055)
+#define I2C_IC_TAR_IC_TAR_BITS _u(0x000003ff)
+#define I2C_IC_TAR_IC_TAR_MSB _u(9)
+#define I2C_IC_TAR_IC_TAR_LSB _u(0)
+#define I2C_IC_TAR_IC_TAR_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_SAR
+// Description : I2C Slave Address Register
+#define I2C_IC_SAR_OFFSET _u(0x00000008)
+#define I2C_IC_SAR_BITS _u(0x000003ff)
+#define I2C_IC_SAR_RESET _u(0x00000055)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_SAR_IC_SAR
+// Description : The IC_SAR holds the slave address when the I2C is operating as
+// a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
+//
+// This register can be written only when the I2C interface is
+// disabled, which corresponds to the IC_ENABLE[0] register being
+// set to 0. Writes at other times have no effect.
+//
+// Note: The default values cannot be any of the reserved address
+// locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct
+// operation of the device is not guaranteed if you program the
+// IC_SAR or IC_TAR to a reserved value. Refer to
+// <<table_I2C_firstbyte_bit_defs>> for a complete list of these
+// reserved values.
+#define I2C_IC_SAR_IC_SAR_RESET _u(0x055)
+#define I2C_IC_SAR_IC_SAR_BITS _u(0x000003ff)
+#define I2C_IC_SAR_IC_SAR_MSB _u(9)
+#define I2C_IC_SAR_IC_SAR_LSB _u(0)
+#define I2C_IC_SAR_IC_SAR_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_DATA_CMD
+// Description : I2C Rx/Tx Data Buffer and Command Register; this is the
+// register the CPU writes to when filling the TX FIFO and the CPU
+// reads from when retrieving bytes from RX FIFO.
+//
+// The size of the register changes as follows:
+//
+// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits
+// when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when
+// IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when
+// IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c
+// to continue acknowledging reads, a read command should be
+// written for every byte that is to be received; otherwise the
+// DW_apb_i2c will stop acknowledging.
+#define I2C_IC_DATA_CMD_OFFSET _u(0x00000010)
+#define I2C_IC_DATA_CMD_BITS _u(0x00000fff)
+#define I2C_IC_DATA_CMD_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DATA_CMD_FIRST_DATA_BYTE
+// Description : Indicates the first data byte received after the address phase
+// for receive transfer in Master receiver or Slave receiver mode.
+//
+// Reset value : 0x0
+//
+// NOTE: In case of APB_DATA_WIDTH=8,
+//
+// 1. The user has to perform two APB Reads to IC_DATA_CMD in
+// order to get status on 11 bit.
+//
+// 2. In order to read the 11 bit, the user has to perform the
+// first data byte read [7:0] (offset 0x10) and then perform the
+// second read [15:8] (offset 0x11) in order to know the status of
+// 11 bit (whether the data received in previous read is a first
+// data byte or not).
+//
+// 3. The 11th bit is an optional read field, user can ignore 2nd
+// byte read [15:8] (offset 0x11) if not interested in
+// FIRST_DATA_BYTE status.
+// 0x0 -> Sequential data byte received
+// 0x1 -> Non sequential data byte received
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_BITS _u(0x00000800)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_MSB _u(11)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_LSB _u(11)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_ACCESS "RO"
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_DATA_CMD_FIRST_DATA_BYTE_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DATA_CMD_RESTART
+// Description : This bit controls whether a RESTART is issued before the byte
+// is sent or received.
+//
+// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data
+// is sent/received (according to the value of CMD), regardless of
+// whether or not the transfer direction is changing from the
+// previous command; if IC_RESTART_EN is 0, a STOP followed by a
+// START is issued instead.
+//
+// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the
+// transfer direction is changing from the previous command; if
+// IC_RESTART_EN is 0, a STOP followed by a START is issued
+// instead.
+//
+// Reset value: 0x0
+// 0x0 -> Don't Issue RESTART before this command
+// 0x1 -> Issue RESTART before this command
+#define I2C_IC_DATA_CMD_RESTART_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_RESTART_BITS _u(0x00000400)
+#define I2C_IC_DATA_CMD_RESTART_MSB _u(10)
+#define I2C_IC_DATA_CMD_RESTART_LSB _u(10)
+#define I2C_IC_DATA_CMD_RESTART_ACCESS "SC"
+#define I2C_IC_DATA_CMD_RESTART_VALUE_DISABLE _u(0x0)
+#define I2C_IC_DATA_CMD_RESTART_VALUE_ENABLE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DATA_CMD_STOP
+// Description : This bit controls whether a STOP is issued after the byte is
+// sent or received.
+//
+// - 1 - STOP is issued after this byte, regardless of whether or
+// not the Tx FIFO is empty. If the Tx FIFO is not empty, the
+// master immediately tries to start a new transfer by issuing a
+// START and arbitrating for the bus. - 0 - STOP is not issued
+// after this byte, regardless of whether or not the Tx FIFO is
+// empty. If the Tx FIFO is not empty, the master continues the
+// current transfer by sending/receiving data bytes according to
+// the value of the CMD bit. If the Tx FIFO is empty, the master
+// holds the SCL line low and stalls the bus until a new command
+// is available in the Tx FIFO. Reset value: 0x0
+// 0x0 -> Don't Issue STOP after this command
+// 0x1 -> Issue STOP after this command
+#define I2C_IC_DATA_CMD_STOP_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_STOP_BITS _u(0x00000200)
+#define I2C_IC_DATA_CMD_STOP_MSB _u(9)
+#define I2C_IC_DATA_CMD_STOP_LSB _u(9)
+#define I2C_IC_DATA_CMD_STOP_ACCESS "SC"
+#define I2C_IC_DATA_CMD_STOP_VALUE_DISABLE _u(0x0)
+#define I2C_IC_DATA_CMD_STOP_VALUE_ENABLE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DATA_CMD_CMD
+// Description : This bit controls whether a read or a write is performed. This
+// bit does not control the direction when the DW_apb_i2con acts
+// as a slave. It controls only the direction when it acts as a
+// master.
+//
+// When a command is entered in the TX FIFO, this bit
+// distinguishes the write and read commands. In slave-receiver
+// mode, this bit is a 'don't care' because writes to this
+// register are not required. In slave-transmitter mode, a '0'
+// indicates that the data in IC_DATA_CMD is to be transmitted.
+//
+// When programming this bit, you should remember the following:
+// attempting to perform a read operation after a General Call
+// command has been sent results in a TX_ABRT interrupt (bit 6 of
+// the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the
+// IC_TAR register has been cleared. If a '1' is written to this
+// bit after receiving a RD_REQ interrupt, then a TX_ABRT
+// interrupt occurs.
+//
+// Reset value: 0x0
+// 0x0 -> Master Write Command
+// 0x1 -> Master Read Command
+#define I2C_IC_DATA_CMD_CMD_RESET _u(0x0)
+#define I2C_IC_DATA_CMD_CMD_BITS _u(0x00000100)
+#define I2C_IC_DATA_CMD_CMD_MSB _u(8)
+#define I2C_IC_DATA_CMD_CMD_LSB _u(8)
+#define I2C_IC_DATA_CMD_CMD_ACCESS "SC"
+#define I2C_IC_DATA_CMD_CMD_VALUE_WRITE _u(0x0)
+#define I2C_IC_DATA_CMD_CMD_VALUE_READ _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DATA_CMD_DAT
+// Description : This register contains the data to be transmitted or received
+// on the I2C bus. If you are writing to this register and want to
+// perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c.
+// However, when you read this register, these bits return the
+// value of data received on the DW_apb_i2c interface.
+//
+// Reset value: 0x0
+#define I2C_IC_DATA_CMD_DAT_RESET _u(0x00)
+#define I2C_IC_DATA_CMD_DAT_BITS _u(0x000000ff)
+#define I2C_IC_DATA_CMD_DAT_MSB _u(7)
+#define I2C_IC_DATA_CMD_DAT_LSB _u(0)
+#define I2C_IC_DATA_CMD_DAT_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_SS_SCL_HCNT
+// Description : Standard Speed I2C Clock SCL High Count Register
+#define I2C_IC_SS_SCL_HCNT_OFFSET _u(0x00000014)
+#define I2C_IC_SS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_HCNT_RESET _u(0x00000028)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT
+// Description : This register must be set before any I2C bus transaction can
+// take place to ensure proper I/O timing. This register sets the
+// SCL clock high-period count for standard speed. For more
+// information, refer to 'IC_CLK Frequency Configuration'.
+//
+// This register can be written only when the I2C interface is
+// disabled which corresponds to the IC_ENABLE[0] register being
+// set to 0. Writes at other times have no effect.
+//
+// The minimum valid value is 6; hardware prevents values less
+// than this being written, and if attempted results in 6 being
+// set. For designs with APB_DATA_WIDTH = 8, the order of
+// programming is important to ensure the correct operation of the
+// DW_apb_i2c. The lower byte must be programmed first. Then the
+// upper byte is programmed.
+//
+// NOTE: This register must not be programmed to a value higher
+// than 65525, because DW_apb_i2c uses a 16-bit counter to flag an
+// I2C bus idle condition when this counter reaches a value of
+// IC_SS_SCL_HCNT + 10.
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_RESET _u(0x0028)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_MSB _u(15)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_LSB _u(0)
+#define I2C_IC_SS_SCL_HCNT_IC_SS_SCL_HCNT_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_SS_SCL_LCNT
+// Description : Standard Speed I2C Clock SCL Low Count Register
+#define I2C_IC_SS_SCL_LCNT_OFFSET _u(0x00000018)
+#define I2C_IC_SS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_LCNT_RESET _u(0x0000002f)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT
+// Description : This register must be set before any I2C bus transaction can
+// take place to ensure proper I/O timing. This register sets the
+// SCL clock low period count for standard speed. For more
+// information, refer to 'IC_CLK Frequency Configuration'
+//
+// This register can be written only when the I2C interface is
+// disabled which corresponds to the IC_ENABLE[0] register being
+// set to 0. Writes at other times have no effect.
+//
+// The minimum valid value is 8; hardware prevents values less
+// than this being written, and if attempted, results in 8 being
+// set. For designs with APB_DATA_WIDTH = 8, the order of
+// programming is important to ensure the correct operation of
+// DW_apb_i2c. The lower byte must be programmed first, and then
+// the upper byte is programmed.
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_RESET _u(0x002f)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_MSB _u(15)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_LSB _u(0)
+#define I2C_IC_SS_SCL_LCNT_IC_SS_SCL_LCNT_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_FS_SCL_HCNT
+// Description : Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
+#define I2C_IC_FS_SCL_HCNT_OFFSET _u(0x0000001c)
+#define I2C_IC_FS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_HCNT_RESET _u(0x00000006)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT
+// Description : This register must be set before any I2C bus transaction can
+// take place to ensure proper I/O timing. This register sets the
+// SCL clock high-period count for fast mode or fast mode plus. It
+// is used in high-speed mode to send the Master Code and START
+// BYTE or General CALL. For more information, refer to 'IC_CLK
+// Frequency Configuration'.
+//
+// This register goes away and becomes read-only returning 0s if
+// IC_MAX_SPEED_MODE = standard. This register can be written only
+// when the I2C interface is disabled, which corresponds to the
+// IC_ENABLE[0] register being set to 0. Writes at other times
+// have no effect.
+//
+// The minimum valid value is 6; hardware prevents values less
+// than this being written, and if attempted results in 6 being
+// set. For designs with APB_DATA_WIDTH == 8 the order of
+// programming is important to ensure the correct operation of the
+// DW_apb_i2c. The lower byte must be programmed first. Then the
+// upper byte is programmed.
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_RESET _u(0x0006)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_MSB _u(15)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_LSB _u(0)
+#define I2C_IC_FS_SCL_HCNT_IC_FS_SCL_HCNT_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_FS_SCL_LCNT
+// Description : Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
+#define I2C_IC_FS_SCL_LCNT_OFFSET _u(0x00000020)
+#define I2C_IC_FS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_LCNT_RESET _u(0x0000000d)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT
+// Description : This register must be set before any I2C bus transaction can
+// take place to ensure proper I/O timing. This register sets the
+// SCL clock low period count for fast speed. It is used in
+// high-speed mode to send the Master Code and START BYTE or
+// General CALL. For more information, refer to 'IC_CLK Frequency
+// Configuration'.
+//
+// This register goes away and becomes read-only returning 0s if
+// IC_MAX_SPEED_MODE = standard.
+//
+// This register can be written only when the I2C interface is
+// disabled, which corresponds to the IC_ENABLE[0] register being
+// set to 0. Writes at other times have no effect.
+//
+// The minimum valid value is 8; hardware prevents values less
+// than this being written, and if attempted results in 8 being
+// set. For designs with APB_DATA_WIDTH = 8 the order of
+// programming is important to ensure the correct operation of the
+// DW_apb_i2c. The lower byte must be programmed first. Then the
+// upper byte is programmed. If the value is less than 8 then the
+// count value gets changed to 8.
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_RESET _u(0x000d)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_BITS _u(0x0000ffff)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_MSB _u(15)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_LSB _u(0)
+#define I2C_IC_FS_SCL_LCNT_IC_FS_SCL_LCNT_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_INTR_STAT
+// Description : I2C Interrupt Status Register
+//
+// Each bit in this register has a corresponding mask bit in the
+// IC_INTR_MASK register. These bits are cleared by reading the
+// matching interrupt clear register. The unmasked raw versions of
+// these bits are available in the IC_RAW_INTR_STAT register.
+#define I2C_IC_INTR_STAT_OFFSET _u(0x0000002c)
+#define I2C_IC_INTR_STAT_BITS _u(0x00001fff)
+#define I2C_IC_INTR_STAT_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_RESTART_DET
+// Description : See IC_RAW_INTR_STAT for a detailed description of
+// R_RESTART_DET bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_RESTART_DET interrupt is inactive
+// 0x1 -> R_RESTART_DET interrupt is active
+#define I2C_IC_INTR_STAT_R_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_BITS _u(0x00001000)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_MSB _u(12)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_LSB _u(12)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RESTART_DET_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_GEN_CALL
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_GEN_CALL interrupt is inactive
+// 0x1 -> R_GEN_CALL interrupt is active
+#define I2C_IC_INTR_STAT_R_GEN_CALL_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_BITS _u(0x00000800)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_MSB _u(11)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_LSB _u(11)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_GEN_CALL_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_START_DET
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_START_DET
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_START_DET interrupt is inactive
+// 0x1 -> R_START_DET interrupt is active
+#define I2C_IC_INTR_STAT_R_START_DET_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_START_DET_BITS _u(0x00000400)
+#define I2C_IC_INTR_STAT_R_START_DET_MSB _u(10)
+#define I2C_IC_INTR_STAT_R_START_DET_LSB _u(10)
+#define I2C_IC_INTR_STAT_R_START_DET_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_START_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_START_DET_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_STOP_DET
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_STOP_DET interrupt is inactive
+// 0x1 -> R_STOP_DET interrupt is active
+#define I2C_IC_INTR_STAT_R_STOP_DET_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_STOP_DET_BITS _u(0x00000200)
+#define I2C_IC_INTR_STAT_R_STOP_DET_MSB _u(9)
+#define I2C_IC_INTR_STAT_R_STOP_DET_LSB _u(9)
+#define I2C_IC_INTR_STAT_R_STOP_DET_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_STOP_DET_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_ACTIVITY
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_ACTIVITY interrupt is inactive
+// 0x1 -> R_ACTIVITY interrupt is active
+#define I2C_IC_INTR_STAT_R_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_BITS _u(0x00000100)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_MSB _u(8)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_LSB _u(8)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_ACTIVITY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_RX_DONE
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_RX_DONE interrupt is inactive
+// 0x1 -> R_RX_DONE interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_DONE_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_DONE_BITS _u(0x00000080)
+#define I2C_IC_INTR_STAT_R_RX_DONE_MSB _u(7)
+#define I2C_IC_INTR_STAT_R_RX_DONE_LSB _u(7)
+#define I2C_IC_INTR_STAT_R_RX_DONE_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_DONE_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_TX_ABRT
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_TX_ABRT interrupt is inactive
+// 0x1 -> R_TX_ABRT interrupt is active
+#define I2C_IC_INTR_STAT_R_TX_ABRT_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_BITS _u(0x00000040)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_MSB _u(6)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_LSB _u(6)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_ABRT_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_RD_REQ
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_RD_REQ interrupt is inactive
+// 0x1 -> R_RD_REQ interrupt is active
+#define I2C_IC_INTR_STAT_R_RD_REQ_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RD_REQ_BITS _u(0x00000020)
+#define I2C_IC_INTR_STAT_R_RD_REQ_MSB _u(5)
+#define I2C_IC_INTR_STAT_R_RD_REQ_LSB _u(5)
+#define I2C_IC_INTR_STAT_R_RD_REQ_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RD_REQ_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_TX_EMPTY
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_TX_EMPTY interrupt is inactive
+// 0x1 -> R_TX_EMPTY interrupt is active
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_BITS _u(0x00000010)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_MSB _u(4)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_LSB _u(4)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_EMPTY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_TX_OVER
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_TX_OVER interrupt is inactive
+// 0x1 -> R_TX_OVER interrupt is active
+#define I2C_IC_INTR_STAT_R_TX_OVER_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_OVER_BITS _u(0x00000008)
+#define I2C_IC_INTR_STAT_R_TX_OVER_MSB _u(3)
+#define I2C_IC_INTR_STAT_R_TX_OVER_LSB _u(3)
+#define I2C_IC_INTR_STAT_R_TX_OVER_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_TX_OVER_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_RX_FULL
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_RX_FULL interrupt is inactive
+// 0x1 -> R_RX_FULL interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_FULL_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_FULL_BITS _u(0x00000004)
+#define I2C_IC_INTR_STAT_R_RX_FULL_MSB _u(2)
+#define I2C_IC_INTR_STAT_R_RX_FULL_LSB _u(2)
+#define I2C_IC_INTR_STAT_R_RX_FULL_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_FULL_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_RX_OVER
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> R_RX_OVER interrupt is inactive
+// 0x1 -> R_RX_OVER interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_OVER_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_OVER_BITS _u(0x00000002)
+#define I2C_IC_INTR_STAT_R_RX_OVER_MSB _u(1)
+#define I2C_IC_INTR_STAT_R_RX_OVER_LSB _u(1)
+#define I2C_IC_INTR_STAT_R_RX_OVER_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_OVER_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_STAT_R_RX_UNDER
+// Description : See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER
+// bit.
+//
+// Reset value: 0x0
+// 0x0 -> RX_UNDER interrupt is inactive
+// 0x1 -> RX_UNDER interrupt is active
+#define I2C_IC_INTR_STAT_R_RX_UNDER_RESET _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_MSB _u(0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_LSB _u(0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_ACCESS "RO"
+#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_INTR_STAT_R_RX_UNDER_VALUE_ACTIVE _u(0x1)
+// =============================================================================
+// Register : I2C_IC_INTR_MASK
+// Description : I2C Interrupt Mask Register.
+//
+// These bits mask their corresponding interrupt status bits. This
+// register is active low; a value of 0 masks the interrupt,
+// whereas a value of 1 unmasks the interrupt.
+#define I2C_IC_INTR_MASK_OFFSET _u(0x00000030)
+#define I2C_IC_INTR_MASK_BITS _u(0x00001fff)
+#define I2C_IC_INTR_MASK_RESET _u(0x000008ff)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_RESTART_DET
+// Description : This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x0
+// 0x0 -> RESTART_DET interrupt is masked
+// 0x1 -> RESTART_DET interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_BITS _u(0x00001000)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_MSB _u(12)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_LSB _u(12)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RESTART_DET_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_GEN_CALL
+// Description : This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> GEN_CALL interrupt is masked
+// 0x1 -> GEN_CALL interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_GEN_CALL_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_BITS _u(0x00000800)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_MSB _u(11)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_LSB _u(11)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_GEN_CALL_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_START_DET
+// Description : This bit masks the R_START_DET interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x0
+// 0x0 -> START_DET interrupt is masked
+// 0x1 -> START_DET interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_START_DET_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_START_DET_BITS _u(0x00000400)
+#define I2C_IC_INTR_MASK_M_START_DET_MSB _u(10)
+#define I2C_IC_INTR_MASK_M_START_DET_LSB _u(10)
+#define I2C_IC_INTR_MASK_M_START_DET_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_START_DET_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_START_DET_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_STOP_DET
+// Description : This bit masks the R_STOP_DET interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x0
+// 0x0 -> STOP_DET interrupt is masked
+// 0x1 -> STOP_DET interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_STOP_DET_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_STOP_DET_BITS _u(0x00000200)
+#define I2C_IC_INTR_MASK_M_STOP_DET_MSB _u(9)
+#define I2C_IC_INTR_MASK_M_STOP_DET_LSB _u(9)
+#define I2C_IC_INTR_MASK_M_STOP_DET_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_STOP_DET_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_ACTIVITY
+// Description : This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x0
+// 0x0 -> ACTIVITY interrupt is masked
+// 0x1 -> ACTIVITY interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_BITS _u(0x00000100)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_MSB _u(8)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_LSB _u(8)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_ACTIVITY_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_RX_DONE
+// Description : This bit masks the R_RX_DONE interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> RX_DONE interrupt is masked
+// 0x1 -> RX_DONE interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_DONE_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_DONE_BITS _u(0x00000080)
+#define I2C_IC_INTR_MASK_M_RX_DONE_MSB _u(7)
+#define I2C_IC_INTR_MASK_M_RX_DONE_LSB _u(7)
+#define I2C_IC_INTR_MASK_M_RX_DONE_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_DONE_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_TX_ABRT
+// Description : This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> TX_ABORT interrupt is masked
+// 0x1 -> TX_ABORT interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_TX_ABRT_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_BITS _u(0x00000040)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_MSB _u(6)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_LSB _u(6)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_ABRT_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_RD_REQ
+// Description : This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
+//
+// Reset value: 0x1
+// 0x0 -> RD_REQ interrupt is masked
+// 0x1 -> RD_REQ interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RD_REQ_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RD_REQ_BITS _u(0x00000020)
+#define I2C_IC_INTR_MASK_M_RD_REQ_MSB _u(5)
+#define I2C_IC_INTR_MASK_M_RD_REQ_LSB _u(5)
+#define I2C_IC_INTR_MASK_M_RD_REQ_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RD_REQ_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_TX_EMPTY
+// Description : This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> TX_EMPTY interrupt is masked
+// 0x1 -> TX_EMPTY interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_BITS _u(0x00000010)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_MSB _u(4)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_LSB _u(4)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_EMPTY_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_TX_OVER
+// Description : This bit masks the R_TX_OVER interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> TX_OVER interrupt is masked
+// 0x1 -> TX_OVER interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_TX_OVER_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_TX_OVER_BITS _u(0x00000008)
+#define I2C_IC_INTR_MASK_M_TX_OVER_MSB _u(3)
+#define I2C_IC_INTR_MASK_M_TX_OVER_LSB _u(3)
+#define I2C_IC_INTR_MASK_M_TX_OVER_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_TX_OVER_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_RX_FULL
+// Description : This bit masks the R_RX_FULL interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> RX_FULL interrupt is masked
+// 0x1 -> RX_FULL interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_FULL_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_FULL_BITS _u(0x00000004)
+#define I2C_IC_INTR_MASK_M_RX_FULL_MSB _u(2)
+#define I2C_IC_INTR_MASK_M_RX_FULL_LSB _u(2)
+#define I2C_IC_INTR_MASK_M_RX_FULL_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_FULL_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_RX_OVER
+// Description : This bit masks the R_RX_OVER interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> RX_OVER interrupt is masked
+// 0x1 -> RX_OVER interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_OVER_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_BITS _u(0x00000002)
+#define I2C_IC_INTR_MASK_M_RX_OVER_MSB _u(1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_LSB _u(1)
+#define I2C_IC_INTR_MASK_M_RX_OVER_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_OVER_VALUE_DISABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_INTR_MASK_M_RX_UNDER
+// Description : This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT
+// register.
+//
+// Reset value: 0x1
+// 0x0 -> RX_UNDER interrupt is masked
+// 0x1 -> RX_UNDER interrupt is unmasked
+#define I2C_IC_INTR_MASK_M_RX_UNDER_RESET _u(0x1)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_MSB _u(0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_LSB _u(0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_ACCESS "RW"
+#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_ENABLED _u(0x0)
+#define I2C_IC_INTR_MASK_M_RX_UNDER_VALUE_DISABLED _u(0x1)
+// =============================================================================
+// Register : I2C_IC_RAW_INTR_STAT
+// Description : I2C Raw Interrupt Status Register
+//
+// Unlike the IC_INTR_STAT register, these bits are not masked so
+// they always show the true status of the DW_apb_i2c.
+#define I2C_IC_RAW_INTR_STAT_OFFSET _u(0x00000034)
+#define I2C_IC_RAW_INTR_STAT_BITS _u(0x00001fff)
+#define I2C_IC_RAW_INTR_STAT_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_RESTART_DET
+// Description : Indicates whether a RESTART condition has occurred on the I2C
+// interface when DW_apb_i2c is operating in Slave mode and the
+// slave is being addressed. Enabled only when
+// IC_SLV_RESTART_DET_EN=1.
+//
+// Note: However, in high-speed mode or during a START BYTE
+// transfer, the RESTART comes before the address field as per the
+// I2C protocol. In this case, the slave is not the addressed
+// slave when the RESTART is issued, therefore DW_apb_i2c does not
+// generate the RESTART_DET interrupt.
+//
+// Reset value: 0x0
+// 0x0 -> RESTART_DET interrupt is inactive
+// 0x1 -> RESTART_DET interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_BITS _u(0x00001000)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_MSB _u(12)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_LSB _u(12)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RESTART_DET_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_GEN_CALL
+// Description : Set only when a General Call address is received and it is
+// acknowledged. It stays set until it is cleared either by
+// disabling DW_apb_i2c or when the CPU reads bit 0 of the
+// IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data
+// in the Rx buffer.
+//
+// Reset value: 0x0
+// 0x0 -> GEN_CALL interrupt is inactive
+// 0x1 -> GEN_CALL interrupt is active
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_BITS _u(0x00000800)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_MSB _u(11)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_LSB _u(11)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_GEN_CALL_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_START_DET
+// Description : Indicates whether a START or RESTART condition has occurred on
+// the I2C interface regardless of whether DW_apb_i2c is operating
+// in slave or master mode.
+//
+// Reset value: 0x0
+// 0x0 -> START_DET interrupt is inactive
+// 0x1 -> START_DET interrupt is active
+#define I2C_IC_RAW_INTR_STAT_START_DET_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_START_DET_BITS _u(0x00000400)
+#define I2C_IC_RAW_INTR_STAT_START_DET_MSB _u(10)
+#define I2C_IC_RAW_INTR_STAT_START_DET_LSB _u(10)
+#define I2C_IC_RAW_INTR_STAT_START_DET_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_START_DET_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_STOP_DET
+// Description : Indicates whether a STOP condition has occurred on the I2C
+// interface regardless of whether DW_apb_i2c is operating in
+// slave or master mode.
+//
+// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the
+// STOP_DET interrupt will be issued only if slave is addressed.
+// Note: During a general call address, this slave does not issue
+// a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the
+// slave responds to the general call address by generating ACK.
+// The STOP_DET interrupt is generated only when the transmitted
+// address matches the slave address (SAR). - If IC_CON[7]=1'b0
+// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued
+// irrespective of whether it is being addressed. In Master Mode:
+// - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET
+// interrupt will be issued only if Master is active. - If
+// IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt
+// will be issued irrespective of whether master is active or not.
+// Reset value: 0x0
+// 0x0 -> STOP_DET interrupt is inactive
+// 0x1 -> STOP_DET interrupt is active
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_BITS _u(0x00000200)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_MSB _u(9)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_LSB _u(9)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_STOP_DET_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_ACTIVITY
+// Description : This bit captures DW_apb_i2c activity and stays set until it is
+// cleared. There are four ways to clear it: - Disabling the
+// DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the
+// IC_CLR_INTR register - System reset Once this bit is set, it
+// stays set unless one of the four methods is used to clear it.
+// Even if the DW_apb_i2c module is idle, this bit remains set
+// until cleared, indicating that there was activity on the bus.
+//
+// Reset value: 0x0
+// 0x0 -> RAW_INTR_ACTIVITY interrupt is inactive
+// 0x1 -> RAW_INTR_ACTIVITY interrupt is active
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_BITS _u(0x00000100)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_MSB _u(8)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_LSB _u(8)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_ACTIVITY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_RX_DONE
+// Description : When the DW_apb_i2c is acting as a slave-transmitter, this bit
+// is set to 1 if the master does not acknowledge a transmitted
+// byte. This occurs on the last byte of the transmission,
+// indicating that the transmission is done.
+//
+// Reset value: 0x0
+// 0x0 -> RX_DONE interrupt is inactive
+// 0x1 -> RX_DONE interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_BITS _u(0x00000080)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_MSB _u(7)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_LSB _u(7)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_DONE_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_TX_ABRT
+// Description : This bit indicates if DW_apb_i2c, as an I2C transmitter, is
+// unable to complete the intended actions on the contents of the
+// transmit FIFO. This situation can occur both as an I2C master
+// or an I2C slave, and is referred to as a 'transmit abort'. When
+// this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates
+// the reason why the transmit abort takes places.
+//
+// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and
+// RX_FIFO whenever there is a transmit abort caused by any of the
+// events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs
+// remains in this flushed state until the register IC_CLR_TX_ABRT
+// is read. Once this read is performed, the Tx FIFO is then ready
+// to accept more data bytes from the APB interface.
+//
+// Reset value: 0x0
+// 0x0 -> TX_ABRT interrupt is inactive
+// 0x1 -> TX_ABRT interrupt is active
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_BITS _u(0x00000040)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_MSB _u(6)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_LSB _u(6)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_ABRT_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_RD_REQ
+// Description : This bit is set to 1 when DW_apb_i2c is acting as a slave and
+// another I2C master is attempting to read data from DW_apb_i2c.
+// The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until
+// this interrupt is serviced, which means that the slave has been
+// addressed by a remote master that is asking for data to be
+// transferred. The processor must respond to this interrupt and
+// then write the requested data to the IC_DATA_CMD register. This
+// bit is set to 0 just after the processor reads the
+// IC_CLR_RD_REQ register.
+//
+// Reset value: 0x0
+// 0x0 -> RD_REQ interrupt is inactive
+// 0x1 -> RD_REQ interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_BITS _u(0x00000020)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_MSB _u(5)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_LSB _u(5)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RD_REQ_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_TX_EMPTY
+// Description : The behavior of the TX_EMPTY interrupt status differs based on
+// the TX_EMPTY_CTRL selection in the IC_CON register. - When
+// TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit
+// buffer is at or below the threshold value set in the IC_TX_TL
+// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when
+// the transmit buffer is at or below the threshold value set in
+// the IC_TX_TL register and the transmission of the address/data
+// from the internal shift register for the most recently popped
+// command is completed. It is automatically cleared by hardware
+// when the buffer level goes above the threshold. When
+// IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in
+// reset. There the TX FIFO looks like it has no data within it,
+// so this bit is set to 1, provided there is activity in the
+// master or slave state machines. When there is no longer any
+// activity, then with ic_en=0, this bit is set to 0.
+//
+// Reset value: 0x0.
+// 0x0 -> TX_EMPTY interrupt is inactive
+// 0x1 -> TX_EMPTY interrupt is active
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_BITS _u(0x00000010)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_MSB _u(4)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_LSB _u(4)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_EMPTY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_TX_OVER
+// Description : Set during transmit if the transmit buffer is filled to
+// IC_TX_BUFFER_DEPTH and the processor attempts to issue another
+// I2C command by writing to the IC_DATA_CMD register. When the
+// module is disabled, this bit keeps its level until the master
+// or slave state machines go into idle, and when ic_en goes to 0,
+// this interrupt is cleared.
+//
+// Reset value: 0x0
+// 0x0 -> TX_OVER interrupt is inactive
+// 0x1 -> TX_OVER interrupt is active
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_BITS _u(0x00000008)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_MSB _u(3)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_LSB _u(3)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_TX_OVER_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_RX_FULL
+// Description : Set when the receive buffer reaches or goes above the RX_TL
+// threshold in the IC_RX_TL register. It is automatically cleared
+// by hardware when buffer level goes below the threshold. If the
+// module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and
+// held in reset; therefore the RX FIFO is not full. So this bit
+// is cleared once the IC_ENABLE bit 0 is programmed with a 0,
+// regardless of the activity that continues.
+//
+// Reset value: 0x0
+// 0x0 -> RX_FULL interrupt is inactive
+// 0x1 -> RX_FULL interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_BITS _u(0x00000004)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_MSB _u(2)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_LSB _u(2)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_FULL_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_RX_OVER
+// Description : Set if the receive buffer is completely filled to
+// IC_RX_BUFFER_DEPTH and an additional byte is received from an
+// external I2C device. The DW_apb_i2c acknowledges this, but any
+// data bytes received after the FIFO is full are lost. If the
+// module is disabled (IC_ENABLE[0]=0), this bit keeps its level
+// until the master or slave state machines go into idle, and when
+// ic_en goes to 0, this interrupt is cleared.
+//
+// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL)
+// is programmed to HIGH, then the RX_OVER interrupt never occurs,
+// because the Rx FIFO never overflows.
+//
+// Reset value: 0x0
+// 0x0 -> RX_OVER interrupt is inactive
+// 0x1 -> RX_OVER interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_BITS _u(0x00000002)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_MSB _u(1)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_LSB _u(1)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_OVER_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RAW_INTR_STAT_RX_UNDER
+// Description : Set if the processor attempts to read the receive buffer when
+// it is empty by reading from the IC_DATA_CMD register. If the
+// module is disabled (IC_ENABLE[0]=0), this bit keeps its level
+// until the master or slave state machines go into idle, and when
+// ic_en goes to 0, this interrupt is cleared.
+//
+// Reset value: 0x0
+// 0x0 -> RX_UNDER interrupt is inactive
+// 0x1 -> RX_UNDER interrupt is active
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_RESET _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_MSB _u(0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_LSB _u(0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_ACCESS "RO"
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_RAW_INTR_STAT_RX_UNDER_VALUE_ACTIVE _u(0x1)
+// =============================================================================
+// Register : I2C_IC_RX_TL
+// Description : I2C Receive FIFO Threshold Register
+#define I2C_IC_RX_TL_OFFSET _u(0x00000038)
+#define I2C_IC_RX_TL_BITS _u(0x000000ff)
+#define I2C_IC_RX_TL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RX_TL_RX_TL
+// Description : Receive FIFO Threshold Level.
+//
+// Controls the level of entries (or above) that triggers the
+// RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The
+// valid range is 0-255, with the additional restriction that
+// hardware does not allow this value to be set to a value larger
+// than the depth of the buffer. If an attempt is made to do that,
+// the actual value set will be the maximum depth of the buffer. A
+// value of 0 sets the threshold for 1 entry, and a value of 255
+// sets the threshold for 256 entries.
+#define I2C_IC_RX_TL_RX_TL_RESET _u(0x00)
+#define I2C_IC_RX_TL_RX_TL_BITS _u(0x000000ff)
+#define I2C_IC_RX_TL_RX_TL_MSB _u(7)
+#define I2C_IC_RX_TL_RX_TL_LSB _u(0)
+#define I2C_IC_RX_TL_RX_TL_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_TX_TL
+// Description : I2C Transmit FIFO Threshold Register
+#define I2C_IC_TX_TL_OFFSET _u(0x0000003c)
+#define I2C_IC_TX_TL_BITS _u(0x000000ff)
+#define I2C_IC_TX_TL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_TL_TX_TL
+// Description : Transmit FIFO Threshold Level.
+//
+// Controls the level of entries (or below) that trigger the
+// TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The
+// valid range is 0-255, with the additional restriction that it
+// may not be set to value larger than the depth of the buffer. If
+// an attempt is made to do that, the actual value set will be the
+// maximum depth of the buffer. A value of 0 sets the threshold
+// for 0 entries, and a value of 255 sets the threshold for 255
+// entries.
+#define I2C_IC_TX_TL_TX_TL_RESET _u(0x00)
+#define I2C_IC_TX_TL_TX_TL_BITS _u(0x000000ff)
+#define I2C_IC_TX_TL_TX_TL_MSB _u(7)
+#define I2C_IC_TX_TL_TX_TL_LSB _u(0)
+#define I2C_IC_TX_TL_TX_TL_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_CLR_INTR
+// Description : Clear Combined and Individual Interrupt Register
+#define I2C_IC_CLR_INTR_OFFSET _u(0x00000040)
+#define I2C_IC_CLR_INTR_BITS _u(0x00000001)
+#define I2C_IC_CLR_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_INTR_CLR_INTR
+// Description : Read this register to clear the combined interrupt, all
+// individual interrupts, and the IC_TX_ABRT_SOURCE register. This
+// bit does not clear hardware clearable interrupts but software
+// clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE
+// register for an exception to clearing IC_TX_ABRT_SOURCE.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_INTR_CLR_INTR_RESET _u(0x0)
+#define I2C_IC_CLR_INTR_CLR_INTR_BITS _u(0x00000001)
+#define I2C_IC_CLR_INTR_CLR_INTR_MSB _u(0)
+#define I2C_IC_CLR_INTR_CLR_INTR_LSB _u(0)
+#define I2C_IC_CLR_INTR_CLR_INTR_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_RX_UNDER
+// Description : Clear RX_UNDER Interrupt Register
+#define I2C_IC_CLR_RX_UNDER_OFFSET _u(0x00000044)
+#define I2C_IC_CLR_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_UNDER_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER
+// Description : Read this register to clear the RX_UNDER interrupt (bit 0) of
+// the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_RESET _u(0x0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_MSB _u(0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_LSB _u(0)
+#define I2C_IC_CLR_RX_UNDER_CLR_RX_UNDER_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_RX_OVER
+// Description : Clear RX_OVER Interrupt Register
+#define I2C_IC_CLR_RX_OVER_OFFSET _u(0x00000048)
+#define I2C_IC_CLR_RX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_OVER_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_RX_OVER_CLR_RX_OVER
+// Description : Read this register to clear the RX_OVER interrupt (bit 1) of
+// the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_RESET _u(0x0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_MSB _u(0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_LSB _u(0)
+#define I2C_IC_CLR_RX_OVER_CLR_RX_OVER_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_TX_OVER
+// Description : Clear TX_OVER Interrupt Register
+#define I2C_IC_CLR_TX_OVER_OFFSET _u(0x0000004c)
+#define I2C_IC_CLR_TX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_OVER_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_TX_OVER_CLR_TX_OVER
+// Description : Read this register to clear the TX_OVER interrupt (bit 3) of
+// the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_RESET _u(0x0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_MSB _u(0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_LSB _u(0)
+#define I2C_IC_CLR_TX_OVER_CLR_TX_OVER_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_RD_REQ
+// Description : Clear RD_REQ Interrupt Register
+#define I2C_IC_CLR_RD_REQ_OFFSET _u(0x00000050)
+#define I2C_IC_CLR_RD_REQ_BITS _u(0x00000001)
+#define I2C_IC_CLR_RD_REQ_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_RD_REQ_CLR_RD_REQ
+// Description : Read this register to clear the RD_REQ interrupt (bit 5) of the
+// IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_RESET _u(0x0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_BITS _u(0x00000001)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_MSB _u(0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_LSB _u(0)
+#define I2C_IC_CLR_RD_REQ_CLR_RD_REQ_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_TX_ABRT
+// Description : Clear TX_ABRT Interrupt Register
+#define I2C_IC_CLR_TX_ABRT_OFFSET _u(0x00000054)
+#define I2C_IC_CLR_TX_ABRT_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_ABRT_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT
+// Description : Read this register to clear the TX_ABRT interrupt (bit 6) of
+// the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE
+// register. This also releases the TX FIFO from the flushed/reset
+// state, allowing more writes to the TX FIFO. Refer to Bit 9 of
+// the IC_TX_ABRT_SOURCE register for an exception to clearing
+// IC_TX_ABRT_SOURCE.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_RESET _u(0x0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_BITS _u(0x00000001)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_MSB _u(0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_LSB _u(0)
+#define I2C_IC_CLR_TX_ABRT_CLR_TX_ABRT_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_RX_DONE
+// Description : Clear RX_DONE Interrupt Register
+#define I2C_IC_CLR_RX_DONE_OFFSET _u(0x00000058)
+#define I2C_IC_CLR_RX_DONE_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_DONE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_RX_DONE_CLR_RX_DONE
+// Description : Read this register to clear the RX_DONE interrupt (bit 7) of
+// the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_RESET _u(0x0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_BITS _u(0x00000001)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_MSB _u(0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_LSB _u(0)
+#define I2C_IC_CLR_RX_DONE_CLR_RX_DONE_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_ACTIVITY
+// Description : Clear ACTIVITY Interrupt Register
+#define I2C_IC_CLR_ACTIVITY_OFFSET _u(0x0000005c)
+#define I2C_IC_CLR_ACTIVITY_BITS _u(0x00000001)
+#define I2C_IC_CLR_ACTIVITY_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY
+// Description : Reading this register clears the ACTIVITY interrupt if the I2C
+// is not active anymore. If the I2C module is still active on the
+// bus, the ACTIVITY interrupt bit continues to be set. It is
+// automatically cleared by hardware if the module is disabled and
+// if there is no further activity on the bus. The value read from
+// this register to get status of the ACTIVITY interrupt (bit 8)
+// of the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_BITS _u(0x00000001)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_MSB _u(0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_LSB _u(0)
+#define I2C_IC_CLR_ACTIVITY_CLR_ACTIVITY_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_STOP_DET
+// Description : Clear STOP_DET Interrupt Register
+#define I2C_IC_CLR_STOP_DET_OFFSET _u(0x00000060)
+#define I2C_IC_CLR_STOP_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_STOP_DET_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_STOP_DET_CLR_STOP_DET
+// Description : Read this register to clear the STOP_DET interrupt (bit 9) of
+// the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_RESET _u(0x0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_MSB _u(0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_LSB _u(0)
+#define I2C_IC_CLR_STOP_DET_CLR_STOP_DET_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_START_DET
+// Description : Clear START_DET Interrupt Register
+#define I2C_IC_CLR_START_DET_OFFSET _u(0x00000064)
+#define I2C_IC_CLR_START_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_START_DET_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_START_DET_CLR_START_DET
+// Description : Read this register to clear the START_DET interrupt (bit 10) of
+// the IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_START_DET_CLR_START_DET_RESET _u(0x0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_MSB _u(0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_LSB _u(0)
+#define I2C_IC_CLR_START_DET_CLR_START_DET_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_CLR_GEN_CALL
+// Description : Clear GEN_CALL Interrupt Register
+#define I2C_IC_CLR_GEN_CALL_OFFSET _u(0x00000068)
+#define I2C_IC_CLR_GEN_CALL_BITS _u(0x00000001)
+#define I2C_IC_CLR_GEN_CALL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL
+// Description : Read this register to clear the GEN_CALL interrupt (bit 11) of
+// IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_RESET _u(0x0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_BITS _u(0x00000001)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_MSB _u(0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_LSB _u(0)
+#define I2C_IC_CLR_GEN_CALL_CLR_GEN_CALL_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_ENABLE
+// Description : I2C Enable Register
+#define I2C_IC_ENABLE_OFFSET _u(0x0000006c)
+#define I2C_IC_ENABLE_BITS _u(0x00000007)
+#define I2C_IC_ENABLE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_ENABLE_TX_CMD_BLOCK
+// Description : In Master mode: - 1'b1: Blocks the transmission of data on I2C
+// bus even if Tx FIFO has data to transmit. - 1'b0: The
+// transmission of data starts on I2C bus automatically, as soon
+// as the first data is available in the Tx FIFO. Note: To block
+// the execution of Master commands, set the TX_CMD_BLOCK bit only
+// when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle
+// state (IC_STATUS[5] == 0). Any further commands put in the Tx
+// FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset
+// value: IC_TX_CMD_BLOCK_DEFAULT
+// 0x0 -> Tx Command execution not blocked
+// 0x1 -> Tx Command execution blocked
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_RESET _u(0x0)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_BITS _u(0x00000004)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_MSB _u(2)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_LSB _u(2)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_ACCESS "RW"
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_NOT_BLOCKED _u(0x0)
+#define I2C_IC_ENABLE_TX_CMD_BLOCK_VALUE_BLOCKED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_ENABLE_ABORT
+// Description : When set, the controller initiates the transfer abort. - 0:
+// ABORT not initiated or ABORT done - 1: ABORT operation in
+// progress The software can abort the I2C transfer in master mode
+// by setting this bit. The software can set this bit only when
+// ENABLE is already set; otherwise, the controller ignores any
+// write to ABORT bit. The software cannot clear the ABORT bit
+// once set. In response to an ABORT, the controller issues a STOP
+// and flushes the Tx FIFO after completing the current transfer,
+// then sets the TX_ABORT interrupt after the abort operation. The
+// ABORT bit is cleared automatically after the abort operation.
+//
+// For a detailed description on how to abort I2C transfers, refer
+// to 'Aborting I2C Transfers'.
+//
+// Reset value: 0x0
+// 0x0 -> ABORT operation not in progress
+// 0x1 -> ABORT operation in progress
+#define I2C_IC_ENABLE_ABORT_RESET _u(0x0)
+#define I2C_IC_ENABLE_ABORT_BITS _u(0x00000002)
+#define I2C_IC_ENABLE_ABORT_MSB _u(1)
+#define I2C_IC_ENABLE_ABORT_LSB _u(1)
+#define I2C_IC_ENABLE_ABORT_ACCESS "RW"
+#define I2C_IC_ENABLE_ABORT_VALUE_DISABLE _u(0x0)
+#define I2C_IC_ENABLE_ABORT_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_ENABLE_ENABLE
+// Description : Controls whether the DW_apb_i2c is enabled. - 0: Disables
+// DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1:
+// Enables DW_apb_i2c Software can disable DW_apb_i2c while it is
+// active. However, it is important that care be taken to ensure
+// that DW_apb_i2c is disabled properly. A recommended procedure
+// is described in 'Disabling DW_apb_i2c'.
+//
+// When DW_apb_i2c is disabled, the following occurs: - The TX
+// FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT
+// register are still active until DW_apb_i2c goes into IDLE
+// state. If the module is transmitting, it stops as well as
+// deletes the contents of the transmit buffer after the current
+// transfer is complete. If the module is receiving, the
+// DW_apb_i2c stops the current transfer at the end of the current
+// byte and does not acknowledge the transfer.
+//
+// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE
+// parameter set to asynchronous (1), there is a two ic_clk delay
+// when enabling or disabling the DW_apb_i2c. For a detailed
+// description on how to disable DW_apb_i2c, refer to 'Disabling
+// DW_apb_i2c'
+//
+// Reset value: 0x0
+// 0x0 -> I2C is disabled
+// 0x1 -> I2C is enabled
+#define I2C_IC_ENABLE_ENABLE_RESET _u(0x0)
+#define I2C_IC_ENABLE_ENABLE_BITS _u(0x00000001)
+#define I2C_IC_ENABLE_ENABLE_MSB _u(0)
+#define I2C_IC_ENABLE_ENABLE_LSB _u(0)
+#define I2C_IC_ENABLE_ENABLE_ACCESS "RW"
+#define I2C_IC_ENABLE_ENABLE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ENABLE_ENABLE_VALUE_ENABLED _u(0x1)
+// =============================================================================
+// Register : I2C_IC_STATUS
+// Description : I2C Status Register
+//
+// This is a read-only register used to indicate the current
+// transfer status and FIFO status. The status register may be
+// read at any time. None of the bits in this register request an
+// interrupt.
+//
+// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE
+// register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set
+// to 0 When the master or slave state machines goes to idle and
+// ic_en=0: - Bits 5 and 6 are set to 0
+#define I2C_IC_STATUS_OFFSET _u(0x00000070)
+#define I2C_IC_STATUS_BITS _u(0x0000007f)
+#define I2C_IC_STATUS_RESET _u(0x00000006)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_STATUS_SLV_ACTIVITY
+// Description : Slave FSM Activity Status. When the Slave Finite State Machine
+// (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM
+// is in IDLE state so the Slave part of DW_apb_i2c is not Active
+// - 1: Slave FSM is not in IDLE state so the Slave part of
+// DW_apb_i2c is Active Reset value: 0x0
+// 0x0 -> Slave is idle
+// 0x1 -> Slave not idle
+#define I2C_IC_STATUS_SLV_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_STATUS_SLV_ACTIVITY_BITS _u(0x00000040)
+#define I2C_IC_STATUS_SLV_ACTIVITY_MSB _u(6)
+#define I2C_IC_STATUS_SLV_ACTIVITY_LSB _u(6)
+#define I2C_IC_STATUS_SLV_ACTIVITY_ACCESS "RO"
+#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_IDLE _u(0x0)
+#define I2C_IC_STATUS_SLV_ACTIVITY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_STATUS_MST_ACTIVITY
+// Description : Master FSM Activity Status. When the Master Finite State
+// Machine (FSM) is not in the IDLE state, this bit is set. - 0:
+// Master FSM is in IDLE state so the Master part of DW_apb_i2c is
+// not Active - 1: Master FSM is not in IDLE state so the Master
+// part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is,
+// ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
+//
+// Reset value: 0x0
+// 0x0 -> Master is idle
+// 0x1 -> Master not idle
+#define I2C_IC_STATUS_MST_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_STATUS_MST_ACTIVITY_BITS _u(0x00000020)
+#define I2C_IC_STATUS_MST_ACTIVITY_MSB _u(5)
+#define I2C_IC_STATUS_MST_ACTIVITY_LSB _u(5)
+#define I2C_IC_STATUS_MST_ACTIVITY_ACCESS "RO"
+#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_IDLE _u(0x0)
+#define I2C_IC_STATUS_MST_ACTIVITY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_STATUS_RFF
+// Description : Receive FIFO Completely Full. When the receive FIFO is
+// completely full, this bit is set. When the receive FIFO
+// contains one or more empty location, this bit is cleared. - 0:
+// Receive FIFO is not full - 1: Receive FIFO is full Reset value:
+// 0x0
+// 0x0 -> Rx FIFO not full
+// 0x1 -> Rx FIFO is full
+#define I2C_IC_STATUS_RFF_RESET _u(0x0)
+#define I2C_IC_STATUS_RFF_BITS _u(0x00000010)
+#define I2C_IC_STATUS_RFF_MSB _u(4)
+#define I2C_IC_STATUS_RFF_LSB _u(4)
+#define I2C_IC_STATUS_RFF_ACCESS "RO"
+#define I2C_IC_STATUS_RFF_VALUE_NOT_FULL _u(0x0)
+#define I2C_IC_STATUS_RFF_VALUE_FULL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_STATUS_RFNE
+// Description : Receive FIFO Not Empty. This bit is set when the receive FIFO
+// contains one or more entries; it is cleared when the receive
+// FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is
+// not empty Reset value: 0x0
+// 0x0 -> Rx FIFO is empty
+// 0x1 -> Rx FIFO not empty
+#define I2C_IC_STATUS_RFNE_RESET _u(0x0)
+#define I2C_IC_STATUS_RFNE_BITS _u(0x00000008)
+#define I2C_IC_STATUS_RFNE_MSB _u(3)
+#define I2C_IC_STATUS_RFNE_LSB _u(3)
+#define I2C_IC_STATUS_RFNE_ACCESS "RO"
+#define I2C_IC_STATUS_RFNE_VALUE_EMPTY _u(0x0)
+#define I2C_IC_STATUS_RFNE_VALUE_NOT_EMPTY _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_STATUS_TFE
+// Description : Transmit FIFO Completely Empty. When the transmit FIFO is
+// completely empty, this bit is set. When it contains one or more
+// valid entries, this bit is cleared. This bit field does not
+// request an interrupt. - 0: Transmit FIFO is not empty - 1:
+// Transmit FIFO is empty Reset value: 0x1
+// 0x0 -> Tx FIFO not empty
+// 0x1 -> Tx FIFO is empty
+#define I2C_IC_STATUS_TFE_RESET _u(0x1)
+#define I2C_IC_STATUS_TFE_BITS _u(0x00000004)
+#define I2C_IC_STATUS_TFE_MSB _u(2)
+#define I2C_IC_STATUS_TFE_LSB _u(2)
+#define I2C_IC_STATUS_TFE_ACCESS "RO"
+#define I2C_IC_STATUS_TFE_VALUE_NON_EMPTY _u(0x0)
+#define I2C_IC_STATUS_TFE_VALUE_EMPTY _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_STATUS_TFNF
+// Description : Transmit FIFO Not Full. Set when the transmit FIFO contains one
+// or more empty locations, and is cleared when the FIFO is full.
+// - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset
+// value: 0x1
+// 0x0 -> Tx FIFO is full
+// 0x1 -> Tx FIFO not full
+#define I2C_IC_STATUS_TFNF_RESET _u(0x1)
+#define I2C_IC_STATUS_TFNF_BITS _u(0x00000002)
+#define I2C_IC_STATUS_TFNF_MSB _u(1)
+#define I2C_IC_STATUS_TFNF_LSB _u(1)
+#define I2C_IC_STATUS_TFNF_ACCESS "RO"
+#define I2C_IC_STATUS_TFNF_VALUE_FULL _u(0x0)
+#define I2C_IC_STATUS_TFNF_VALUE_NOT_FULL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_STATUS_ACTIVITY
+// Description : I2C Activity Status. Reset value: 0x0
+// 0x0 -> I2C is idle
+// 0x1 -> I2C is active
+#define I2C_IC_STATUS_ACTIVITY_RESET _u(0x0)
+#define I2C_IC_STATUS_ACTIVITY_BITS _u(0x00000001)
+#define I2C_IC_STATUS_ACTIVITY_MSB _u(0)
+#define I2C_IC_STATUS_ACTIVITY_LSB _u(0)
+#define I2C_IC_STATUS_ACTIVITY_ACCESS "RO"
+#define I2C_IC_STATUS_ACTIVITY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_STATUS_ACTIVITY_VALUE_ACTIVE _u(0x1)
+// =============================================================================
+// Register : I2C_IC_TXFLR
+// Description : I2C Transmit FIFO Level Register This register contains the
+// number of valid data entries in the transmit FIFO buffer. It is
+// cleared whenever: - The I2C is disabled - There is a transmit
+// abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT
+// register - The slave bulk transmit mode is aborted The register
+// increments whenever data is placed into the transmit FIFO and
+// decrements when data is taken from the transmit FIFO.
+#define I2C_IC_TXFLR_OFFSET _u(0x00000074)
+#define I2C_IC_TXFLR_BITS _u(0x0000001f)
+#define I2C_IC_TXFLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TXFLR_TXFLR
+// Description : Transmit FIFO Level. Contains the number of valid data entries
+// in the transmit FIFO.
+//
+// Reset value: 0x0
+#define I2C_IC_TXFLR_TXFLR_RESET _u(0x00)
+#define I2C_IC_TXFLR_TXFLR_BITS _u(0x0000001f)
+#define I2C_IC_TXFLR_TXFLR_MSB _u(4)
+#define I2C_IC_TXFLR_TXFLR_LSB _u(0)
+#define I2C_IC_TXFLR_TXFLR_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_RXFLR
+// Description : I2C Receive FIFO Level Register This register contains the
+// number of valid data entries in the receive FIFO buffer. It is
+// cleared whenever: - The I2C is disabled - Whenever there is a
+// transmit abort caused by any of the events tracked in
+// IC_TX_ABRT_SOURCE The register increments whenever data is
+// placed into the receive FIFO and decrements when data is taken
+// from the receive FIFO.
+#define I2C_IC_RXFLR_OFFSET _u(0x00000078)
+#define I2C_IC_RXFLR_BITS _u(0x0000001f)
+#define I2C_IC_RXFLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_RXFLR_RXFLR
+// Description : Receive FIFO Level. Contains the number of valid data entries
+// in the receive FIFO.
+//
+// Reset value: 0x0
+#define I2C_IC_RXFLR_RXFLR_RESET _u(0x00)
+#define I2C_IC_RXFLR_RXFLR_BITS _u(0x0000001f)
+#define I2C_IC_RXFLR_RXFLR_MSB _u(4)
+#define I2C_IC_RXFLR_RXFLR_LSB _u(0)
+#define I2C_IC_RXFLR_RXFLR_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_SDA_HOLD
+// Description : I2C SDA Hold Time Length Register
+//
+// The bits [15:0] of this register are used to control the hold
+// time of SDA during transmit in both slave and master mode
+// (after SCL goes from HIGH to LOW).
+//
+// The bits [23:16] of this register are used to extend the SDA
+// transition (if any) whenever SCL is HIGH in the receiver in
+// either master or slave mode.
+//
+// Writes to this register succeed only when IC_ENABLE[0]=0.
+//
+// The values in this register are in units of ic_clk period. The
+// value programmed in IC_SDA_TX_HOLD must be greater than the
+// minimum hold time in each mode (one cycle in master mode, seven
+// cycles in slave mode) for the value to be implemented.
+//
+// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD)
+// cannot exceed at any time the duration of the low part of scl.
+// Therefore the programmed value cannot be larger than
+// N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of
+// the scl period measured in ic_clk cycles.
+#define I2C_IC_SDA_HOLD_OFFSET _u(0x0000007c)
+#define I2C_IC_SDA_HOLD_BITS _u(0x00ffffff)
+#define I2C_IC_SDA_HOLD_RESET _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD
+// Description : Sets the required SDA hold time in units of ic_clk period, when
+// DW_apb_i2c acts as a receiver.
+//
+// Reset value: IC_DEFAULT_SDA_HOLD[23:16].
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_RESET _u(0x00)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_BITS _u(0x00ff0000)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_MSB _u(23)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_LSB _u(16)
+#define I2C_IC_SDA_HOLD_IC_SDA_RX_HOLD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD
+// Description : Sets the required SDA hold time in units of ic_clk period, when
+// DW_apb_i2c acts as a transmitter.
+//
+// Reset value: IC_DEFAULT_SDA_HOLD[15:0].
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_RESET _u(0x0001)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_BITS _u(0x0000ffff)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_MSB _u(15)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_LSB _u(0)
+#define I2C_IC_SDA_HOLD_IC_SDA_TX_HOLD_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_TX_ABRT_SOURCE
+// Description : I2C Transmit Abort Source Register
+//
+// This register has 32 bits that indicate the source of the
+// TX_ABRT bit. Except for Bit 9, this register is cleared
+// whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR
+// register is read. To clear Bit 9, the source of the
+// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled
+// (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or
+// the GC_OR_START bit must be cleared (IC_TAR[10]).
+//
+// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this
+// bit can be cleared in the same manner as other bits in this
+// register. If the source of the ABRT_SBYTE_NORSTRT is not fixed
+// before attempting to clear this bit, Bit 9 clears for one cycle
+// and is then re-asserted.
+#define I2C_IC_TX_ABRT_SOURCE_OFFSET _u(0x00000080)
+#define I2C_IC_TX_ABRT_SOURCE_BITS _u(0xff81ffff)
+#define I2C_IC_TX_ABRT_SOURCE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT
+// Description : This field indicates the number of Tx FIFO Data Commands which
+// are flushed due to TX_ABRT interrupt. It is cleared whenever
+// I2C is disabled.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_RESET _u(0x000)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_BITS _u(0xff800000)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_MSB _u(31)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_LSB _u(23)
+#define I2C_IC_TX_ABRT_SOURCE_TX_FLUSH_CNT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT
+// Description : This is a master-mode-only bit. Master has detected the
+// transfer abort (IC_ENABLE[1])
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter
+// 0x0 -> Transfer abort detected by master- scenario not present
+// 0x1 -> Transfer abort detected by master
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_BITS _u(0x00010000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_MSB _u(16)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_LSB _u(16)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_USER_ABRT_VALUE_ABRT_USER_ABRT_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX
+// Description : 1: When the processor side responds to a slave mode request for
+// data to be transmitted to a remote master and user writes a 1
+// in CMD (bit 8) of IC_DATA_CMD register.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Slave-Transmitter
+// 0x0 -> Slave trying to transmit to remote master in read mode-
+// scenario not present
+// 0x1 -> Slave trying to transmit to remote master in read mode
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_BITS _u(0x00008000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_MSB _u(15)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_LSB _u(15)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVRD_INTX_VALUE_ABRT_SLVRD_INTX_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST
+// Description : This field indicates that a Slave has lost the bus while
+// transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is
+// set at the same time. Note: Even though the slave never 'owns'
+// the bus, something could go wrong on the bus. This is a fail
+// safe check. For instance, during a data transmission at the
+// low-to-high transition of SCL, if what is on the data bus is
+// not what is supposed to be transmitted, then DW_apb_i2c no
+// longer own the bus.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Slave-Transmitter
+// 0x0 -> Slave lost arbitration to remote master- scenario not
+// present
+// 0x1 -> Slave lost arbitration to remote master
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_BITS _u(0x00004000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_MSB _u(14)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_LSB _u(14)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLV_ARBLOST_VALUE_ABRT_SLV_ARBLOST_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO
+// Description : This field specifies that the Slave has received a read command
+// and some data exists in the TX FIFO, so the slave issues a
+// TX_ABRT interrupt to flush old data in TX FIFO.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Slave-Transmitter
+// 0x0 -> Slave flushes existing data in TX-FIFO upon getting read
+// command- scenario not present
+// 0x1 -> Slave flushes existing data in TX-FIFO upon getting read
+// command
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_BITS _u(0x00002000)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_MSB _u(13)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_LSB _u(13)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SLVFLUSH_TXFIFO_VALUE_ABRT_SLVFLUSH_TXFIFO_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ARB_LOST
+// Description : This field specifies that the Master has lost arbitration, or
+// if IC_TX_ABRT_SOURCE[14] is also set, then the slave
+// transmitter has lost arbitration.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
+// 0x0 -> Master or Slave-Transmitter lost arbitration- scenario
+// not present
+// 0x1 -> Master or Slave-Transmitter lost arbitration
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_BITS _u(0x00001000)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_MSB _u(12)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_LSB _u(12)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ARB_LOST_VALUE_ABRT_LOST_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS
+// Description : This field indicates that the User tries to initiate a Master
+// operation with the Master mode disabled.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+// 0x0 -> User initiating master operation when MASTER disabled-
+// scenario not present
+// 0x1 -> User initiating master operation when MASTER disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_BITS _u(0x00000800)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_MSB _u(11)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_LSB _u(11)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_MASTER_DIS_VALUE_ABRT_MASTER_DIS_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT
+// Description : This field indicates that the restart is disabled
+// (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read
+// command in 10-bit addressing mode.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Receiver
+// 0x0 -> Master not trying to read in 10Bit addressing mode when
+// RESTART disabled
+// 0x1 -> Master trying to read in 10Bit addressing mode when
+// RESTART disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_BITS _u(0x00000400)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_MSB _u(10)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_LSB _u(10)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10B_RD_NORSTRT_VALUE_ABRT_10B_RD_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT
+// Description : To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be
+// fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL
+// bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must
+// be cleared (IC_TAR[10]). Once the source of the
+// ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in
+// the same manner as other bits in this register. If the source
+// of the ABRT_SBYTE_NORSTRT is not fixed before attempting to
+// clear this bit, bit 9 clears for one cycle and then gets
+// reasserted. When this field is set to 1, the restart is
+// disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is
+// trying to send a START Byte.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master
+// 0x0 -> User trying to send START byte when RESTART disabled-
+// scenario not present
+// 0x1 -> User trying to send START byte when RESTART disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_BITS _u(0x00000200)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_MSB _u(9)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_LSB _u(9)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_NORSTRT_VALUE_ABRT_SBYTE_NORSTRT_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT
+// Description : This field indicates that the restart is disabled
+// (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to
+// use the master to transfer data in High Speed mode.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+// 0x0 -> User trying to switch Master to HS mode when RESTART
+// disabled- scenario not present
+// 0x1 -> User trying to switch Master to HS mode when RESTART
+// disabled
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_BITS _u(0x00000100)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_MSB _u(8)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_LSB _u(8)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_NORSTRT_VALUE_ABRT_HS_NORSTRT_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET
+// Description : This field indicates that the Master has sent a START Byte and
+// the START Byte was acknowledged (wrong behavior).
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master
+// 0x0 -> ACK detected for START byte- scenario not present
+// 0x1 -> ACK detected for START byte
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_BITS _u(0x00000080)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_MSB _u(7)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_LSB _u(7)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_SBYTE_ACKDET_VALUE_ABRT_SBYTE_ACKDET_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET
+// Description : This field indicates that the Master is in High Speed mode and
+// the High Speed Master code was acknowledged (wrong behavior).
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master
+// 0x0 -> HS Master code ACKed in HS Mode- scenario not present
+// 0x1 -> HS Master code ACKed in HS Mode
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_BITS _u(0x00000040)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_MSB _u(6)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_LSB _u(6)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_HS_ACKDET_VALUE_ABRT_HS_ACK_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ
+// Description : This field indicates that DW_apb_i2c in the master mode has
+// sent a General Call but the user programmed the byte following
+// the General Call to be a read from the bus (IC_DATA_CMD[9] is
+// set to 1).
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter
+// 0x0 -> GCALL is followed by read from bus-scenario not present
+// 0x1 -> GCALL is followed by read from bus
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_BITS _u(0x00000020)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_MSB _u(5)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_LSB _u(5)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_READ_VALUE_ABRT_GCALL_READ_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK
+// Description : This field indicates that DW_apb_i2c in master mode has sent a
+// General Call and no slave on the bus acknowledged the General
+// Call.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter
+// 0x0 -> GCALL not ACKed by any slave-scenario not present
+// 0x1 -> GCALL not ACKed by any slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_BITS _u(0x00000010)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_MSB _u(4)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_LSB _u(4)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_GCALL_NOACK_VALUE_ABRT_GCALL_NOACK_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK
+// Description : This field indicates the master-mode only bit. When the master
+// receives an acknowledgement for the address, but when it sends
+// data byte(s) following the address, it did not receive an
+// acknowledge from the remote slave(s).
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter
+// 0x0 -> Transmitted data non-ACKed by addressed slave-scenario
+// not present
+// 0x1 -> Transmitted data not ACKed by addressed slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_BITS _u(0x00000008)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_MSB _u(3)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_LSB _u(3)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_VOID _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_TXDATA_NOACK_VALUE_ABRT_TXDATA_NOACK_GENERATED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK
+// Description : This field indicates that the Master is in 10-bit address mode
+// and that the second address byte of the 10-bit address was not
+// acknowledged by any slave.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+// 0x0 -> This abort is not generated
+// 0x1 -> Byte 2 of 10Bit Address not ACKed by any slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_BITS _u(0x00000004)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_MSB _u(2)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_LSB _u(2)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR2_NOACK_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK
+// Description : This field indicates that the Master is in 10-bit address mode
+// and the first 10-bit address byte was not acknowledged by any
+// slave.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+// 0x0 -> This abort is not generated
+// 0x1 -> Byte 1 of 10Bit Address not ACKed by any slave
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_BITS _u(0x00000002)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_MSB _u(1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_LSB _u(1)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_10ADDR1_NOACK_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK
+// Description : This field indicates that the Master is in 7-bit addressing
+// mode and the address sent was not acknowledged by any slave.
+//
+// Reset value: 0x0
+//
+// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+// 0x0 -> This abort is not generated
+// 0x1 -> This abort is generated because of NOACK for 7-bit
+// address
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_RESET _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_BITS _u(0x00000001)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_MSB _u(0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_LSB _u(0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_ACCESS "RO"
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_TX_ABRT_SOURCE_ABRT_7B_ADDR_NOACK_VALUE_ACTIVE _u(0x1)
+// =============================================================================
+// Register : I2C_IC_SLV_DATA_NACK_ONLY
+// Description : Generate Slave Data NACK Register
+//
+// The register is used to generate a NACK for the data part of a
+// transfer when DW_apb_i2c is acting as a slave-receiver. This
+// register only exists when the IC_SLV_DATA_NACK_ONLY parameter
+// is set to 1. When this parameter disabled, this register does
+// not exist and writing to the register's address has no effect.
+//
+// A write can occur on this register if both of the following
+// conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0)
+// - Slave part is inactive (IC_STATUS[6] = 0) Note: The
+// IC_STATUS[6] is a register read-back location for the internal
+// slv_activity signal; the user should poll this before writing
+// the ic_slv_data_nack_only bit.
+#define I2C_IC_SLV_DATA_NACK_ONLY_OFFSET _u(0x00000084)
+#define I2C_IC_SLV_DATA_NACK_ONLY_BITS _u(0x00000001)
+#define I2C_IC_SLV_DATA_NACK_ONLY_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_SLV_DATA_NACK_ONLY_NACK
+// Description : Generate NACK. This NACK generation only occurs when DW_apb_i2c
+// is a slave-receiver. If this register is set to a value of 1,
+// it can only generate a NACK after a data byte is received;
+// hence, the data transfer is aborted and the data received is
+// not pushed to the receive buffer.
+//
+// When the register is set to a value of 0, it generates
+// NACK/ACK, depending on normal criteria. - 1: generate NACK
+// after data byte received - 0: generate NACK/ACK normally Reset
+// value: 0x0
+// 0x0 -> Slave receiver generates NACK normally
+// 0x1 -> Slave receiver generates NACK upon data reception only
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_RESET _u(0x0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_BITS _u(0x00000001)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_MSB _u(0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_LSB _u(0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_ACCESS "RW"
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_DISABLED _u(0x0)
+#define I2C_IC_SLV_DATA_NACK_ONLY_NACK_VALUE_ENABLED _u(0x1)
+// =============================================================================
+// Register : I2C_IC_DMA_CR
+// Description : DMA Control Register
+//
+// The register is used to enable the DMA Controller interface
+// operation. There is a separate bit for transmit and receive.
+// This can be programmed regardless of the state of IC_ENABLE.
+#define I2C_IC_DMA_CR_OFFSET _u(0x00000088)
+#define I2C_IC_DMA_CR_BITS _u(0x00000003)
+#define I2C_IC_DMA_CR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DMA_CR_TDMAE
+// Description : Transmit DMA Enable. This bit enables/disables the transmit
+// FIFO DMA channel. Reset value: 0x0
+// 0x0 -> transmit FIFO DMA channel disabled
+// 0x1 -> Transmit FIFO DMA channel enabled
+#define I2C_IC_DMA_CR_TDMAE_RESET _u(0x0)
+#define I2C_IC_DMA_CR_TDMAE_BITS _u(0x00000002)
+#define I2C_IC_DMA_CR_TDMAE_MSB _u(1)
+#define I2C_IC_DMA_CR_TDMAE_LSB _u(1)
+#define I2C_IC_DMA_CR_TDMAE_ACCESS "RW"
+#define I2C_IC_DMA_CR_TDMAE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_DMA_CR_TDMAE_VALUE_ENABLED _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DMA_CR_RDMAE
+// Description : Receive DMA Enable. This bit enables/disables the receive FIFO
+// DMA channel. Reset value: 0x0
+// 0x0 -> Receive FIFO DMA channel disabled
+// 0x1 -> Receive FIFO DMA channel enabled
+#define I2C_IC_DMA_CR_RDMAE_RESET _u(0x0)
+#define I2C_IC_DMA_CR_RDMAE_BITS _u(0x00000001)
+#define I2C_IC_DMA_CR_RDMAE_MSB _u(0)
+#define I2C_IC_DMA_CR_RDMAE_LSB _u(0)
+#define I2C_IC_DMA_CR_RDMAE_ACCESS "RW"
+#define I2C_IC_DMA_CR_RDMAE_VALUE_DISABLED _u(0x0)
+#define I2C_IC_DMA_CR_RDMAE_VALUE_ENABLED _u(0x1)
+// =============================================================================
+// Register : I2C_IC_DMA_TDLR
+// Description : DMA Transmit Data Level Register
+#define I2C_IC_DMA_TDLR_OFFSET _u(0x0000008c)
+#define I2C_IC_DMA_TDLR_BITS _u(0x0000000f)
+#define I2C_IC_DMA_TDLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DMA_TDLR_DMATDL
+// Description : Transmit Data Level. This bit field controls the level at which
+// a DMA request is made by the transmit logic. It is equal to the
+// watermark level; that is, the dma_tx_req signal is generated
+// when the number of valid data entries in the transmit FIFO is
+// equal to or below this field value, and TDMAE = 1.
+//
+// Reset value: 0x0
+#define I2C_IC_DMA_TDLR_DMATDL_RESET _u(0x0)
+#define I2C_IC_DMA_TDLR_DMATDL_BITS _u(0x0000000f)
+#define I2C_IC_DMA_TDLR_DMATDL_MSB _u(3)
+#define I2C_IC_DMA_TDLR_DMATDL_LSB _u(0)
+#define I2C_IC_DMA_TDLR_DMATDL_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_DMA_RDLR
+// Description : I2C Receive Data Level Register
+#define I2C_IC_DMA_RDLR_OFFSET _u(0x00000090)
+#define I2C_IC_DMA_RDLR_BITS _u(0x0000000f)
+#define I2C_IC_DMA_RDLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_DMA_RDLR_DMARDL
+// Description : Receive Data Level. This bit field controls the level at which
+// a DMA request is made by the receive logic. The watermark level
+// = DMARDL+1; that is, dma_rx_req is generated when the number of
+// valid data entries in the receive FIFO is equal to or more than
+// this field value + 1, and RDMAE =1. For instance, when DMARDL
+// is 0, then dma_rx_req is asserted when 1 or more data entries
+// are present in the receive FIFO.
+//
+// Reset value: 0x0
+#define I2C_IC_DMA_RDLR_DMARDL_RESET _u(0x0)
+#define I2C_IC_DMA_RDLR_DMARDL_BITS _u(0x0000000f)
+#define I2C_IC_DMA_RDLR_DMARDL_MSB _u(3)
+#define I2C_IC_DMA_RDLR_DMARDL_LSB _u(0)
+#define I2C_IC_DMA_RDLR_DMARDL_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_SDA_SETUP
+// Description : I2C SDA Setup Register
+//
+// This register controls the amount of time delay (in terms of
+// number of ic_clk clock periods) introduced in the rising edge
+// of SCL - relative to SDA changing - when DW_apb_i2c services a
+// read request in a slave-transmitter operation. The relevant I2C
+// requirement is tSU:DAT (note 4) as detailed in the I2C Bus
+// Specification. This register must be programmed with a value
+// equal to or greater than 2.
+//
+// Writes to this register succeed only when IC_ENABLE[0] = 0.
+//
+// Note: The length of setup time is calculated using
+// [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires
+// 10 ic_clk periods of setup time, they should program a value of
+// 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c
+// when operating as a slave transmitter.
+#define I2C_IC_SDA_SETUP_OFFSET _u(0x00000094)
+#define I2C_IC_SDA_SETUP_BITS _u(0x000000ff)
+#define I2C_IC_SDA_SETUP_RESET _u(0x00000064)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_SDA_SETUP_SDA_SETUP
+// Description : SDA Setup. It is recommended that if the required delay is
+// 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP
+// should be programmed to a value of 11. IC_SDA_SETUP must be
+// programmed with a minimum value of 2.
+#define I2C_IC_SDA_SETUP_SDA_SETUP_RESET _u(0x64)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_BITS _u(0x000000ff)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_MSB _u(7)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_LSB _u(0)
+#define I2C_IC_SDA_SETUP_SDA_SETUP_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_ACK_GENERAL_CALL
+// Description : I2C ACK General Call Register
+//
+// The register controls whether DW_apb_i2c responds with a ACK or
+// NACK when it receives an I2C General Call address.
+//
+// This register is applicable only when the DW_apb_i2c is in
+// slave mode.
+#define I2C_IC_ACK_GENERAL_CALL_OFFSET _u(0x00000098)
+#define I2C_IC_ACK_GENERAL_CALL_BITS _u(0x00000001)
+#define I2C_IC_ACK_GENERAL_CALL_RESET _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL
+// Description : ACK General Call. When set to 1, DW_apb_i2c responds with a ACK
+// (by asserting ic_data_oe) when it receives a General Call.
+// Otherwise, DW_apb_i2c responds with a NACK (by negating
+// ic_data_oe).
+// 0x0 -> Generate NACK for a General Call
+// 0x1 -> Generate ACK for a General Call
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_RESET _u(0x1)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_BITS _u(0x00000001)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_MSB _u(0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_LSB _u(0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_ACCESS "RW"
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ACK_GENERAL_CALL_ACK_GEN_CALL_VALUE_ENABLED _u(0x1)
+// =============================================================================
+// Register : I2C_IC_ENABLE_STATUS
+// Description : I2C Enable Status Register
+//
+// The register is used to report the DW_apb_i2c hardware status
+// when the IC_ENABLE[0] register is set from 1 to 0; that is,
+// when DW_apb_i2c is disabled.
+//
+// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0,
+// and bit 0 is forced to 1.
+//
+// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as
+// soon as bit 0 is read as '0'.
+//
+// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for
+// bit 0 to be read as 0 because disabling the DW_apb_i2c depends
+// on I2C bus activities.
+#define I2C_IC_ENABLE_STATUS_OFFSET _u(0x0000009c)
+#define I2C_IC_ENABLE_STATUS_BITS _u(0x00000007)
+#define I2C_IC_ENABLE_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST
+// Description : Slave Received Data Lost. This bit indicates if a
+// Slave-Receiver operation has been aborted with at least one
+// data byte received from an I2C transfer due to the setting bit
+// 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is
+// deemed to have been actively engaged in an aborted I2C transfer
+// (with matching address) and the data phase of the I2C transfer
+// has been entered, even though a data byte has been responded
+// with a NACK.
+//
+// Note: If the remote I2C master terminates the transfer with a
+// STOP condition before the DW_apb_i2c has a chance to NACK a
+// transfer, and IC_ENABLE[0] has been set to 0, then this bit is
+// also set to 1.
+//
+// When read as 0, DW_apb_i2c is deemed to have been disabled
+// without being actively involved in the data phase of a
+// Slave-Receiver transfer.
+//
+// Note: The CPU can safely read this bit when IC_EN (bit 0) is
+// read as 0.
+//
+// Reset value: 0x0
+// 0x0 -> Slave RX Data is not lost
+// 0x1 -> Slave RX Data is lost
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_RESET _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_BITS _u(0x00000004)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_MSB _u(2)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_LSB _u(2)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_ACCESS "RO"
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_RX_DATA_LOST_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY
+// Description : Slave Disabled While Busy (Transmit, Receive). This bit
+// indicates if a potential or active Slave operation has been
+// aborted due to the setting bit 0 of the IC_ENABLE register from
+// 1 to 0. This bit is set when the CPU writes a 0 to the
+// IC_ENABLE register while:
+//
+// (a) DW_apb_i2c is receiving the address byte of the
+// Slave-Transmitter operation from a remote master;
+//
+// OR,
+//
+// (b) address and data bytes of the Slave-Receiver operation from
+// a remote master.
+//
+// When read as 1, DW_apb_i2c is deemed to have forced a NACK
+// during any part of an I2C transfer, irrespective of whether the
+// I2C address matches the slave address set in DW_apb_i2c (IC_SAR
+// register) OR if the transfer is completed before IC_ENABLE is
+// set to 0 but has not taken effect.
+//
+// Note: If the remote I2C master terminates the transfer with a
+// STOP condition before the DW_apb_i2c has a chance to NACK a
+// transfer, and IC_ENABLE[0] has been set to 0, then this bit
+// will also be set to 1.
+//
+// When read as 0, DW_apb_i2c is deemed to have been disabled when
+// there is master activity, or when the I2C bus is idle.
+//
+// Note: The CPU can safely read this bit when IC_EN (bit 0) is
+// read as 0.
+//
+// Reset value: 0x0
+// 0x0 -> Slave is disabled when it is idle
+// 0x1 -> Slave is disabled when it is active
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_RESET _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_BITS _u(0x00000002)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_MSB _u(1)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_LSB _u(1)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_ACCESS "RO"
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_INACTIVE _u(0x0)
+#define I2C_IC_ENABLE_STATUS_SLV_DISABLED_WHILE_BUSY_VALUE_ACTIVE _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_ENABLE_STATUS_IC_EN
+// Description : ic_en Status. This bit always reflects the value driven on the
+// output port ic_en. - When read as 1, DW_apb_i2c is deemed to be
+// in an enabled state. - When read as 0, DW_apb_i2c is deemed
+// completely inactive. Note: The CPU can safely read this bit
+// anytime. When this bit is read as 0, the CPU can safely read
+// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
+//
+// Reset value: 0x0
+// 0x0 -> I2C disabled
+// 0x1 -> I2C enabled
+#define I2C_IC_ENABLE_STATUS_IC_EN_RESET _u(0x0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_BITS _u(0x00000001)
+#define I2C_IC_ENABLE_STATUS_IC_EN_MSB _u(0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_LSB _u(0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_ACCESS "RO"
+#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_DISABLED _u(0x0)
+#define I2C_IC_ENABLE_STATUS_IC_EN_VALUE_ENABLED _u(0x1)
+// =============================================================================
+// Register : I2C_IC_FS_SPKLEN
+// Description : I2C SS, FS or FM+ spike suppression limit
+//
+// This register is used to store the duration, measured in ic_clk
+// cycles, of the longest spike that is filtered out by the spike
+// suppression logic when the component is operating in SS, FS or
+// FM+ modes. The relevant I2C requirement is tSP (table 4) as
+// detailed in the I2C Bus Specification. This register must be
+// programmed with a minimum value of 1.
+#define I2C_IC_FS_SPKLEN_OFFSET _u(0x000000a0)
+#define I2C_IC_FS_SPKLEN_BITS _u(0x000000ff)
+#define I2C_IC_FS_SPKLEN_RESET _u(0x00000007)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_FS_SPKLEN_IC_FS_SPKLEN
+// Description : This register must be set before any I2C bus transaction can
+// take place to ensure stable operation. This register sets the
+// duration, measured in ic_clk cycles, of the longest spike in
+// the SCL or SDA lines that will be filtered out by the spike
+// suppression logic. This register can be written only when the
+// I2C interface is disabled which corresponds to the IC_ENABLE[0]
+// register being set to 0. Writes at other times have no effect.
+// The minimum valid value is 1; hardware prevents values less
+// than this being written, and if attempted results in 1 being
+// set. or more information, refer to 'Spike Suppression'.
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_RESET _u(0x07)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_BITS _u(0x000000ff)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_MSB _u(7)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_LSB _u(0)
+#define I2C_IC_FS_SPKLEN_IC_FS_SPKLEN_ACCESS "RW"
+// =============================================================================
+// Register : I2C_IC_CLR_RESTART_DET
+// Description : Clear RESTART_DET Interrupt Register
+#define I2C_IC_CLR_RESTART_DET_OFFSET _u(0x000000a8)
+#define I2C_IC_CLR_RESTART_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_RESTART_DET_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET
+// Description : Read this register to clear the RESTART_DET interrupt (bit 12)
+// of IC_RAW_INTR_STAT register.
+//
+// Reset value: 0x0
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_RESET _u(0x0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_BITS _u(0x00000001)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_MSB _u(0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_LSB _u(0)
+#define I2C_IC_CLR_RESTART_DET_CLR_RESTART_DET_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_COMP_PARAM_1
+// Description : Component Parameter Register 1
+//
+// Note This register is not implemented and therefore reads as 0.
+// If it was implemented it would be a constant read-only register
+// that contains encoded information about the component's
+// parameter settings. Fields shown below are the settings for
+// those parameters
+#define I2C_IC_COMP_PARAM_1_OFFSET _u(0x000000f4)
+#define I2C_IC_COMP_PARAM_1_BITS _u(0x00ffffff)
+#define I2C_IC_COMP_PARAM_1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH
+// Description : TX Buffer Depth = 16
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_RESET _u(0x00)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_BITS _u(0x00ff0000)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_MSB _u(23)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_LSB _u(16)
+#define I2C_IC_COMP_PARAM_1_TX_BUFFER_DEPTH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH
+// Description : RX Buffer Depth = 16
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_RESET _u(0x00)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_BITS _u(0x0000ff00)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_MSB _u(15)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_LSB _u(8)
+#define I2C_IC_COMP_PARAM_1_RX_BUFFER_DEPTH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS
+// Description : Encoded parameters not visible
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_BITS _u(0x00000080)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_MSB _u(7)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_LSB _u(7)
+#define I2C_IC_COMP_PARAM_1_ADD_ENCODED_PARAMS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_HAS_DMA
+// Description : DMA handshaking signals are enabled
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_BITS _u(0x00000040)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_MSB _u(6)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_LSB _u(6)
+#define I2C_IC_COMP_PARAM_1_HAS_DMA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_INTR_IO
+// Description : COMBINED Interrupt outputs
+#define I2C_IC_COMP_PARAM_1_INTR_IO_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_BITS _u(0x00000020)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_MSB _u(5)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_LSB _u(5)
+#define I2C_IC_COMP_PARAM_1_INTR_IO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES
+// Description : Programmable count values for each mode.
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_BITS _u(0x00000010)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_MSB _u(4)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_LSB _u(4)
+#define I2C_IC_COMP_PARAM_1_HC_COUNT_VALUES_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE
+// Description : MAX SPEED MODE = FAST MODE
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_BITS _u(0x0000000c)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_MSB _u(3)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_LSB _u(2)
+#define I2C_IC_COMP_PARAM_1_MAX_SPEED_MODE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH
+// Description : APB data bus width is 32 bits
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_RESET _u(0x0)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_BITS _u(0x00000003)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_MSB _u(1)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_LSB _u(0)
+#define I2C_IC_COMP_PARAM_1_APB_DATA_WIDTH_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_COMP_VERSION
+// Description : I2C Component Version Register
+#define I2C_IC_COMP_VERSION_OFFSET _u(0x000000f8)
+#define I2C_IC_COMP_VERSION_BITS _u(0xffffffff)
+#define I2C_IC_COMP_VERSION_RESET _u(0x3230312a)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_VERSION_IC_COMP_VERSION
+// Description : None
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_RESET _u(0x3230312a)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_BITS _u(0xffffffff)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_MSB _u(31)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_LSB _u(0)
+#define I2C_IC_COMP_VERSION_IC_COMP_VERSION_ACCESS "RO"
+// =============================================================================
+// Register : I2C_IC_COMP_TYPE
+// Description : I2C Component Type Register
+#define I2C_IC_COMP_TYPE_OFFSET _u(0x000000fc)
+#define I2C_IC_COMP_TYPE_BITS _u(0xffffffff)
+#define I2C_IC_COMP_TYPE_RESET _u(0x44570140)
+// -----------------------------------------------------------------------------
+// Field : I2C_IC_COMP_TYPE_IC_COMP_TYPE
+// Description : Designware Component Type number = 0x44_57_01_40. This assigned
+// unique hex value is constant and is derived from the two ASCII
+// letters 'DW' followed by a 16-bit unsigned number.
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_RESET _u(0x44570140)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_BITS _u(0xffffffff)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_MSB _u(31)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_LSB _u(0)
+#define I2C_IC_COMP_TYPE_IC_COMP_TYPE_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_I2C_DEFINED
diff --git a/arkanoid/pico/hardware/regs/intctrl.h b/arkanoid/pico/hardware/regs/intctrl.h
new file mode 100644
index 0000000..dec7e36
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/intctrl.h
@@ -0,0 +1,63 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _INTCTRL_H_
+#define _INTCTRL_H_
+
+#define TIMER_IRQ_0 0
+#define TIMER_IRQ_1 1
+#define TIMER_IRQ_2 2
+#define TIMER_IRQ_3 3
+#define PWM_IRQ_WRAP 4
+#define USBCTRL_IRQ 5
+#define XIP_IRQ 6
+#define PIO0_IRQ_0 7
+#define PIO0_IRQ_1 8
+#define PIO1_IRQ_0 9
+#define PIO1_IRQ_1 10
+#define DMA_IRQ_0 11
+#define DMA_IRQ_1 12
+#define IO_IRQ_BANK0 13
+#define IO_IRQ_QSPI 14
+#define SIO_IRQ_PROC0 15
+#define SIO_IRQ_PROC1 16
+#define CLOCKS_IRQ 17
+#define SPI0_IRQ 18
+#define SPI1_IRQ 19
+#define UART0_IRQ 20
+#define UART1_IRQ 21
+#define ADC_IRQ_FIFO 22
+#define I2C0_IRQ 23
+#define I2C1_IRQ 24
+#define RTC_IRQ 25
+
+#define isr_timer_0 isr_irq0
+#define isr_timer_1 isr_irq1
+#define isr_timer_2 isr_irq2
+#define isr_timer_3 isr_irq3
+#define isr_pwm_wrap isr_irq4
+#define isr_usbctrl isr_irq5
+#define isr_xip isr_irq6
+#define isr_pio0_0 isr_irq7
+#define isr_pio0_1 isr_irq8
+#define isr_pio1_0 isr_irq9
+#define isr_pio1_1 isr_irq10
+#define isr_dma_0 isr_irq11
+#define isr_dma_1 isr_irq12
+#define isr_io_bank0 isr_irq13
+#define isr_io_qspi isr_irq14
+#define isr_sio_proc0 isr_irq15
+#define isr_sio_proc1 isr_irq16
+#define isr_clocks isr_irq17
+#define isr_spi0 isr_irq18
+#define isr_spi1 isr_irq19
+#define isr_uart0 isr_irq20
+#define isr_uart1 isr_irq21
+#define isr_adc_fifo isr_irq22
+#define isr_i2c0 isr_irq23
+#define isr_i2c1 isr_irq24
+#define isr_rtc isr_irq25
+
+#endif // _INTCTRL_H_
diff --git a/arkanoid/pico/hardware/regs/io_bank0.h b/arkanoid/pico/hardware/regs/io_bank0.h
new file mode 100644
index 0000000..26f139e
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/io_bank0.h
@@ -0,0 +1,14937 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : IO_BANK0
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_IO_BANK0_DEFINED
+#define HARDWARE_REGS_IO_BANK0_DEFINED
+// =============================================================================
+// Register : IO_BANK0_GPIO0_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO0_STATUS_OFFSET _u(0x00000000)
+#define IO_BANK0_GPIO0_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO0_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO0_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO0_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO0_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO0_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO0_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO0_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO0_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO0_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO0_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO0_CTRL_OFFSET _u(0x00000004)
+#define IO_BANK0_GPIO0_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO0_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO0_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO0_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO0_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO0_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO0_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO0_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO0_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> jtag_tck
+// 0x01 -> spi0_rx
+// 0x02 -> uart0_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_0
+// 0x05 -> sio_0
+// 0x06 -> pio0_0
+// 0x07 -> pio1_0
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_JTAG_TCK _u(0x00)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0 _u(0x05)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0 _u(0x06)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0 _u(0x07)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO1_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO1_STATUS_OFFSET _u(0x00000008)
+#define IO_BANK0_GPIO1_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO1_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO1_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO1_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO1_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO1_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO1_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO1_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO1_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO1_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO1_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO1_CTRL_OFFSET _u(0x0000000c)
+#define IO_BANK0_GPIO1_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO1_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO1_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO1_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO1_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO1_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO1_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO1_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO1_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> jtag_tms
+// 0x01 -> spi0_ss_n
+// 0x02 -> uart0_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_0
+// 0x05 -> sio_1
+// 0x06 -> pio0_1
+// 0x07 -> pio1_1
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_JTAG_TMS _u(0x00)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_SIO_1 _u(0x05)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO0_1 _u(0x06)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_PIO1_1 _u(0x07)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO2_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO2_STATUS_OFFSET _u(0x00000010)
+#define IO_BANK0_GPIO2_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO2_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO2_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO2_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO2_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO2_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO2_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO2_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO2_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO2_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO2_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO2_CTRL_OFFSET _u(0x00000014)
+#define IO_BANK0_GPIO2_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO2_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO2_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO2_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO2_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO2_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO2_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO2_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO2_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> jtag_tdi
+// 0x01 -> spi0_sclk
+// 0x02 -> uart0_cts
+// 0x03 -> i2c1_sda
+// 0x04 -> pwm_a_1
+// 0x05 -> sio_2
+// 0x06 -> pio0_2
+// 0x07 -> pio1_2
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_JTAG_TDI _u(0x00)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_SIO_2 _u(0x05)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO0_2 _u(0x06)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_PIO1_2 _u(0x07)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO3_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO3_STATUS_OFFSET _u(0x00000018)
+#define IO_BANK0_GPIO3_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO3_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO3_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO3_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO3_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO3_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO3_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO3_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO3_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO3_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO3_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO3_CTRL_OFFSET _u(0x0000001c)
+#define IO_BANK0_GPIO3_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO3_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO3_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO3_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO3_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO3_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO3_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO3_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO3_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> jtag_tdo
+// 0x01 -> spi0_tx
+// 0x02 -> uart0_rts
+// 0x03 -> i2c1_scl
+// 0x04 -> pwm_b_1
+// 0x05 -> sio_3
+// 0x06 -> pio0_3
+// 0x07 -> pio1_3
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_JTAG_TDO _u(0x00)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_SIO_3 _u(0x05)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO0_3 _u(0x06)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_PIO1_3 _u(0x07)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO4_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO4_STATUS_OFFSET _u(0x00000020)
+#define IO_BANK0_GPIO4_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO4_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO4_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO4_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO4_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO4_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO4_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO4_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO4_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO4_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO4_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO4_CTRL_OFFSET _u(0x00000024)
+#define IO_BANK0_GPIO4_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO4_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO4_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO4_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO4_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO4_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO4_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO4_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO4_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_rx
+// 0x02 -> uart1_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_2
+// 0x05 -> sio_4
+// 0x06 -> pio0_4
+// 0x07 -> pio1_4
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_SIO_4 _u(0x05)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO0_4 _u(0x06)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_PIO1_4 _u(0x07)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO4_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO5_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO5_STATUS_OFFSET _u(0x00000028)
+#define IO_BANK0_GPIO5_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO5_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO5_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO5_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO5_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO5_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO5_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO5_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO5_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO5_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO5_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO5_CTRL_OFFSET _u(0x0000002c)
+#define IO_BANK0_GPIO5_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO5_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO5_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO5_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO5_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO5_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO5_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO5_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO5_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_ss_n
+// 0x02 -> uart1_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_2
+// 0x05 -> sio_5
+// 0x06 -> pio0_5
+// 0x07 -> pio1_5
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_SIO_5 _u(0x05)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO0_5 _u(0x06)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_PIO1_5 _u(0x07)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO5_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO6_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO6_STATUS_OFFSET _u(0x00000030)
+#define IO_BANK0_GPIO6_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO6_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO6_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO6_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO6_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO6_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO6_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO6_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO6_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO6_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO6_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO6_CTRL_OFFSET _u(0x00000034)
+#define IO_BANK0_GPIO6_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO6_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO6_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO6_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO6_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO6_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO6_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO6_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO6_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_sclk
+// 0x02 -> uart1_cts
+// 0x03 -> i2c1_sda
+// 0x04 -> pwm_a_3
+// 0x05 -> sio_6
+// 0x06 -> pio0_6
+// 0x07 -> pio1_6
+// 0x08 -> usb_muxing_extphy_softcon
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_SIO_6 _u(0x05)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO0_6 _u(0x06)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_PIO1_6 _u(0x07)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SOFTCON _u(0x08)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO6_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO7_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO7_STATUS_OFFSET _u(0x00000038)
+#define IO_BANK0_GPIO7_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO7_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO7_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO7_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO7_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO7_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO7_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO7_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO7_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO7_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO7_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO7_CTRL_OFFSET _u(0x0000003c)
+#define IO_BANK0_GPIO7_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO7_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO7_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO7_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO7_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO7_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO7_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO7_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO7_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_tx
+// 0x02 -> uart1_rts
+// 0x03 -> i2c1_scl
+// 0x04 -> pwm_b_3
+// 0x05 -> sio_7
+// 0x06 -> pio0_7
+// 0x07 -> pio1_7
+// 0x08 -> usb_muxing_extphy_oe_n
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_SIO_7 _u(0x05)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO0_7 _u(0x06)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_PIO1_7 _u(0x07)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_OE_N _u(0x08)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO7_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO8_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO8_STATUS_OFFSET _u(0x00000040)
+#define IO_BANK0_GPIO8_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO8_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO8_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO8_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO8_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO8_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO8_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO8_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO8_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO8_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO8_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO8_CTRL_OFFSET _u(0x00000044)
+#define IO_BANK0_GPIO8_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO8_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO8_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO8_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO8_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO8_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO8_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO8_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO8_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_rx
+// 0x02 -> uart1_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_4
+// 0x05 -> sio_8
+// 0x06 -> pio0_8
+// 0x07 -> pio1_8
+// 0x08 -> usb_muxing_extphy_rcv
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_SIO_8 _u(0x05)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO0_8 _u(0x06)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_PIO1_8 _u(0x07)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_RCV _u(0x08)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO8_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO9_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO9_STATUS_OFFSET _u(0x00000048)
+#define IO_BANK0_GPIO9_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO9_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO9_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO9_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO9_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO9_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO9_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO9_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO9_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO9_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO9_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO9_CTRL_OFFSET _u(0x0000004c)
+#define IO_BANK0_GPIO9_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO9_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO9_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO9_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO9_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO9_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO9_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO9_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO9_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_ss_n
+// 0x02 -> uart1_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_4
+// 0x05 -> sio_9
+// 0x06 -> pio0_9
+// 0x07 -> pio1_9
+// 0x08 -> usb_muxing_extphy_vp
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_SIO_9 _u(0x05)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO0_9 _u(0x06)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_PIO1_9 _u(0x07)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VP _u(0x08)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO9_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO10_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO10_STATUS_OFFSET _u(0x00000050)
+#define IO_BANK0_GPIO10_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO10_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO10_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO10_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO10_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO10_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO10_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO10_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO10_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO10_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO10_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO10_CTRL_OFFSET _u(0x00000054)
+#define IO_BANK0_GPIO10_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO10_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO10_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO10_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO10_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO10_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO10_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO10_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO10_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_sclk
+// 0x02 -> uart1_cts
+// 0x03 -> i2c1_sda
+// 0x04 -> pwm_a_5
+// 0x05 -> sio_10
+// 0x06 -> pio0_10
+// 0x07 -> pio1_10
+// 0x08 -> usb_muxing_extphy_vm
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_SIO_10 _u(0x05)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO0_10 _u(0x06)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_PIO1_10 _u(0x07)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VM _u(0x08)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO10_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO11_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO11_STATUS_OFFSET _u(0x00000058)
+#define IO_BANK0_GPIO11_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO11_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO11_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO11_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO11_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO11_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO11_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO11_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO11_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO11_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO11_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO11_CTRL_OFFSET _u(0x0000005c)
+#define IO_BANK0_GPIO11_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO11_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO11_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO11_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO11_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO11_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO11_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO11_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO11_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_tx
+// 0x02 -> uart1_rts
+// 0x03 -> i2c1_scl
+// 0x04 -> pwm_b_5
+// 0x05 -> sio_11
+// 0x06 -> pio0_11
+// 0x07 -> pio1_11
+// 0x08 -> usb_muxing_extphy_suspnd
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_SIO_11 _u(0x05)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO0_11 _u(0x06)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_PIO1_11 _u(0x07)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SUSPND _u(0x08)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO11_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO12_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO12_STATUS_OFFSET _u(0x00000060)
+#define IO_BANK0_GPIO12_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO12_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO12_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO12_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO12_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO12_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO12_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO12_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO12_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO12_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO12_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO12_CTRL_OFFSET _u(0x00000064)
+#define IO_BANK0_GPIO12_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO12_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO12_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO12_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO12_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO12_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO12_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO12_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO12_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_rx
+// 0x02 -> uart0_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_6
+// 0x05 -> sio_12
+// 0x06 -> pio0_12
+// 0x07 -> pio1_12
+// 0x08 -> usb_muxing_extphy_speed
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_SIO_12 _u(0x05)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO0_12 _u(0x06)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_PIO1_12 _u(0x07)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_SPEED _u(0x08)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO12_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO13_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO13_STATUS_OFFSET _u(0x00000068)
+#define IO_BANK0_GPIO13_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO13_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO13_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO13_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO13_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO13_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO13_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO13_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO13_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO13_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO13_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO13_CTRL_OFFSET _u(0x0000006c)
+#define IO_BANK0_GPIO13_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO13_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO13_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO13_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO13_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO13_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO13_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO13_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO13_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_ss_n
+// 0x02 -> uart0_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_6
+// 0x05 -> sio_13
+// 0x06 -> pio0_13
+// 0x07 -> pio1_13
+// 0x08 -> usb_muxing_extphy_vpo
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_SIO_13 _u(0x05)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO0_13 _u(0x06)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_PIO1_13 _u(0x07)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VPO _u(0x08)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO13_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO14_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO14_STATUS_OFFSET _u(0x00000070)
+#define IO_BANK0_GPIO14_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO14_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO14_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO14_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO14_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO14_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO14_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO14_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO14_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO14_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO14_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO14_CTRL_OFFSET _u(0x00000074)
+#define IO_BANK0_GPIO14_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO14_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO14_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO14_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO14_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO14_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO14_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO14_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO14_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_sclk
+// 0x02 -> uart0_cts
+// 0x03 -> i2c1_sda
+// 0x04 -> pwm_a_7
+// 0x05 -> sio_14
+// 0x06 -> pio0_14
+// 0x07 -> pio1_14
+// 0x08 -> usb_muxing_extphy_vmo
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PWM_A_7 _u(0x04)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_SIO_14 _u(0x05)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO0_14 _u(0x06)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_PIO1_14 _u(0x07)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_EXTPHY_VMO _u(0x08)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO14_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO15_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO15_STATUS_OFFSET _u(0x00000078)
+#define IO_BANK0_GPIO15_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO15_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO15_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO15_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO15_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO15_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO15_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO15_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO15_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO15_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO15_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO15_CTRL_OFFSET _u(0x0000007c)
+#define IO_BANK0_GPIO15_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO15_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO15_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO15_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO15_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO15_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO15_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO15_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO15_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_tx
+// 0x02 -> uart0_rts
+// 0x03 -> i2c1_scl
+// 0x04 -> pwm_b_7
+// 0x05 -> sio_15
+// 0x06 -> pio0_15
+// 0x07 -> pio1_15
+// 0x08 -> usb_muxing_digital_dp
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PWM_B_7 _u(0x04)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_SIO_15 _u(0x05)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO0_15 _u(0x06)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_PIO1_15 _u(0x07)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DP _u(0x08)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO15_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO16_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO16_STATUS_OFFSET _u(0x00000080)
+#define IO_BANK0_GPIO16_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO16_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO16_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO16_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO16_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO16_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO16_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO16_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO16_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO16_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO16_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO16_CTRL_OFFSET _u(0x00000084)
+#define IO_BANK0_GPIO16_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO16_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO16_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO16_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO16_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO16_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO16_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO16_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO16_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_rx
+// 0x02 -> uart0_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_0
+// 0x05 -> sio_16
+// 0x06 -> pio0_16
+// 0x07 -> pio1_16
+// 0x08 -> usb_muxing_digital_dm
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PWM_A_0 _u(0x04)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_SIO_16 _u(0x05)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO0_16 _u(0x06)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_PIO1_16 _u(0x07)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_DIGITAL_DM _u(0x08)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO16_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO17_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO17_STATUS_OFFSET _u(0x00000088)
+#define IO_BANK0_GPIO17_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO17_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO17_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO17_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO17_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO17_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO17_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO17_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO17_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO17_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO17_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO17_CTRL_OFFSET _u(0x0000008c)
+#define IO_BANK0_GPIO17_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO17_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO17_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO17_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO17_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO17_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO17_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO17_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO17_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_ss_n
+// 0x02 -> uart0_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_0
+// 0x05 -> sio_17
+// 0x06 -> pio0_17
+// 0x07 -> pio1_17
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PWM_B_0 _u(0x04)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_SIO_17 _u(0x05)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO0_17 _u(0x06)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_PIO1_17 _u(0x07)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO17_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO18_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO18_STATUS_OFFSET _u(0x00000090)
+#define IO_BANK0_GPIO18_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO18_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO18_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO18_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO18_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO18_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO18_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO18_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO18_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO18_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO18_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO18_CTRL_OFFSET _u(0x00000094)
+#define IO_BANK0_GPIO18_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO18_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO18_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO18_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO18_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO18_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO18_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO18_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO18_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_sclk
+// 0x02 -> uart0_cts
+// 0x03 -> i2c1_sda
+// 0x04 -> pwm_a_1
+// 0x05 -> sio_18
+// 0x06 -> pio0_18
+// 0x07 -> pio1_18
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_UART0_CTS _u(0x02)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PWM_A_1 _u(0x04)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_SIO_18 _u(0x05)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO0_18 _u(0x06)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_PIO1_18 _u(0x07)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO18_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO19_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO19_STATUS_OFFSET _u(0x00000098)
+#define IO_BANK0_GPIO19_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO19_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO19_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO19_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO19_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO19_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO19_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO19_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO19_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO19_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO19_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO19_CTRL_OFFSET _u(0x0000009c)
+#define IO_BANK0_GPIO19_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO19_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO19_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO19_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO19_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO19_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO19_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO19_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO19_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_tx
+// 0x02 -> uart0_rts
+// 0x03 -> i2c1_scl
+// 0x04 -> pwm_b_1
+// 0x05 -> sio_19
+// 0x06 -> pio0_19
+// 0x07 -> pio1_19
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_UART0_RTS _u(0x02)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PWM_B_1 _u(0x04)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_SIO_19 _u(0x05)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO0_19 _u(0x06)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_PIO1_19 _u(0x07)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO19_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO20_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO20_STATUS_OFFSET _u(0x000000a0)
+#define IO_BANK0_GPIO20_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO20_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO20_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO20_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO20_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO20_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO20_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO20_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO20_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO20_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO20_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO20_CTRL_OFFSET _u(0x000000a4)
+#define IO_BANK0_GPIO20_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO20_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO20_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO20_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO20_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO20_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO20_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO20_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO20_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_rx
+// 0x02 -> uart1_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_2
+// 0x05 -> sio_20
+// 0x06 -> pio0_20
+// 0x07 -> pio1_20
+// 0x08 -> clocks_gpin_0
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SPI0_RX _u(0x01)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PWM_A_2 _u(0x04)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_SIO_20 _u(0x05)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO0_20 _u(0x06)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_PIO1_20 _u(0x07)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0 _u(0x08)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO21_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO21_STATUS_OFFSET _u(0x000000a8)
+#define IO_BANK0_GPIO21_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO21_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO21_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO21_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO21_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO21_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO21_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO21_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO21_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO21_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO21_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO21_CTRL_OFFSET _u(0x000000ac)
+#define IO_BANK0_GPIO21_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO21_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO21_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO21_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO21_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO21_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO21_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO21_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO21_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_ss_n
+// 0x02 -> uart1_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_2
+// 0x05 -> sio_21
+// 0x06 -> pio0_21
+// 0x07 -> pio1_21
+// 0x08 -> clocks_gpout_0
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SPI0_SS_N _u(0x01)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PWM_B_2 _u(0x04)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_SIO_21 _u(0x05)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO0_21 _u(0x06)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_PIO1_21 _u(0x07)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0 _u(0x08)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO22_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO22_STATUS_OFFSET _u(0x000000b0)
+#define IO_BANK0_GPIO22_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO22_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO22_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO22_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO22_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO22_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO22_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO22_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO22_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO22_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO22_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO22_CTRL_OFFSET _u(0x000000b4)
+#define IO_BANK0_GPIO22_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO22_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO22_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO22_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO22_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO22_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO22_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO22_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO22_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_sclk
+// 0x02 -> uart1_cts
+// 0x03 -> i2c1_sda
+// 0x04 -> pwm_a_3
+// 0x05 -> sio_22
+// 0x06 -> pio0_22
+// 0x07 -> pio1_22
+// 0x08 -> clocks_gpin_1
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SPI0_SCLK _u(0x01)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PWM_A_3 _u(0x04)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_SIO_22 _u(0x05)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO0_22 _u(0x06)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_PIO1_22 _u(0x07)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_1 _u(0x08)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO22_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO23_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO23_STATUS_OFFSET _u(0x000000b8)
+#define IO_BANK0_GPIO23_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO23_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO23_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO23_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO23_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO23_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO23_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO23_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO23_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO23_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO23_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO23_CTRL_OFFSET _u(0x000000bc)
+#define IO_BANK0_GPIO23_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO23_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO23_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO23_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO23_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO23_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO23_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO23_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO23_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi0_tx
+// 0x02 -> uart1_rts
+// 0x03 -> i2c1_scl
+// 0x04 -> pwm_b_3
+// 0x05 -> sio_23
+// 0x06 -> pio0_23
+// 0x07 -> pio1_23
+// 0x08 -> clocks_gpout_1
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SPI0_TX _u(0x01)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PWM_B_3 _u(0x04)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_SIO_23 _u(0x05)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO0_23 _u(0x06)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_PIO1_23 _u(0x07)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_1 _u(0x08)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO23_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO24_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO24_STATUS_OFFSET _u(0x000000c0)
+#define IO_BANK0_GPIO24_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO24_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO24_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO24_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO24_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO24_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO24_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO24_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO24_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO24_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO24_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO24_CTRL_OFFSET _u(0x000000c4)
+#define IO_BANK0_GPIO24_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO24_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO24_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO24_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO24_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO24_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO24_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO24_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO24_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_rx
+// 0x02 -> uart1_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_4
+// 0x05 -> sio_24
+// 0x06 -> pio0_24
+// 0x07 -> pio1_24
+// 0x08 -> clocks_gpout_2
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_UART1_TX _u(0x02)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PWM_A_4 _u(0x04)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_SIO_24 _u(0x05)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO0_24 _u(0x06)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_PIO1_24 _u(0x07)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_2 _u(0x08)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO24_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO25_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO25_STATUS_OFFSET _u(0x000000c8)
+#define IO_BANK0_GPIO25_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO25_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO25_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO25_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO25_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO25_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO25_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO25_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO25_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO25_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO25_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO25_CTRL_OFFSET _u(0x000000cc)
+#define IO_BANK0_GPIO25_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO25_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO25_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO25_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO25_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO25_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO25_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO25_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO25_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_ss_n
+// 0x02 -> uart1_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_4
+// 0x05 -> sio_25
+// 0x06 -> pio0_25
+// 0x07 -> pio1_25
+// 0x08 -> clocks_gpout_3
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_UART1_RX _u(0x02)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PWM_B_4 _u(0x04)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_SIO_25 _u(0x05)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO0_25 _u(0x06)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_PIO1_25 _u(0x07)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_3 _u(0x08)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO25_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO26_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO26_STATUS_OFFSET _u(0x000000d0)
+#define IO_BANK0_GPIO26_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO26_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO26_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO26_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO26_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO26_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO26_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO26_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO26_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO26_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO26_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO26_CTRL_OFFSET _u(0x000000d4)
+#define IO_BANK0_GPIO26_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO26_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO26_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO26_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO26_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO26_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO26_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO26_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO26_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_sclk
+// 0x02 -> uart1_cts
+// 0x03 -> i2c1_sda
+// 0x04 -> pwm_a_5
+// 0x05 -> sio_26
+// 0x06 -> pio0_26
+// 0x07 -> pio1_26
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SPI1_SCLK _u(0x01)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_UART1_CTS _u(0x02)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_I2C1_SDA _u(0x03)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PWM_A_5 _u(0x04)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_SIO_26 _u(0x05)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO0_26 _u(0x06)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_PIO1_26 _u(0x07)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO26_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO27_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO27_STATUS_OFFSET _u(0x000000d8)
+#define IO_BANK0_GPIO27_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO27_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO27_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO27_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO27_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO27_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO27_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO27_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO27_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO27_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO27_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO27_CTRL_OFFSET _u(0x000000dc)
+#define IO_BANK0_GPIO27_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO27_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO27_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO27_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO27_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO27_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO27_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO27_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO27_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_tx
+// 0x02 -> uart1_rts
+// 0x03 -> i2c1_scl
+// 0x04 -> pwm_b_5
+// 0x05 -> sio_27
+// 0x06 -> pio0_27
+// 0x07 -> pio1_27
+// 0x09 -> usb_muxing_overcurr_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SPI1_TX _u(0x01)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_UART1_RTS _u(0x02)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_I2C1_SCL _u(0x03)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PWM_B_5 _u(0x04)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_SIO_27 _u(0x05)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO0_27 _u(0x06)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_PIO1_27 _u(0x07)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT _u(0x09)
+#define IO_BANK0_GPIO27_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO28_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO28_STATUS_OFFSET _u(0x000000e0)
+#define IO_BANK0_GPIO28_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO28_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO28_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO28_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO28_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO28_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO28_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO28_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO28_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO28_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO28_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO28_CTRL_OFFSET _u(0x000000e4)
+#define IO_BANK0_GPIO28_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO28_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO28_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO28_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO28_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO28_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO28_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO28_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO28_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_rx
+// 0x02 -> uart0_tx
+// 0x03 -> i2c0_sda
+// 0x04 -> pwm_a_6
+// 0x05 -> sio_28
+// 0x06 -> pio0_28
+// 0x07 -> pio1_28
+// 0x09 -> usb_muxing_vbus_detect
+// 0x1f -> null
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SPI1_RX _u(0x01)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_UART0_TX _u(0x02)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_I2C0_SDA _u(0x03)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PWM_A_6 _u(0x04)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_SIO_28 _u(0x05)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO0_28 _u(0x06)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_PIO1_28 _u(0x07)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_DETECT _u(0x09)
+#define IO_BANK0_GPIO28_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_GPIO29_STATUS
+// Description : GPIO status
+#define IO_BANK0_GPIO29_STATUS_OFFSET _u(0x000000e8)
+#define IO_BANK0_GPIO29_STATUS_BITS _u(0x050a3300)
+#define IO_BANK0_GPIO29_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_BANK0_GPIO29_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_BANK0_GPIO29_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_MSB _u(19)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_LSB _u(19)
+#define IO_BANK0_GPIO29_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_MSB _u(17)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_LSB _u(17)
+#define IO_BANK0_GPIO29_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_MSB _u(13)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_LSB _u(13)
+#define IO_BANK0_GPIO29_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_BANK0_GPIO29_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_BANK0_GPIO29_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_BANK0_GPIO29_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_GPIO29_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_BANK0_GPIO29_CTRL_OFFSET _u(0x000000ec)
+#define IO_BANK0_GPIO29_CTRL_BITS _u(0x3003331f)
+#define IO_BANK0_GPIO29_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_MSB _u(29)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_LSB _u(28)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_ACCESS "RW"
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_BANK0_GPIO29_CTRL_INOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_BANK0_GPIO29_CTRL_INOVER_MSB _u(17)
+#define IO_BANK0_GPIO29_CTRL_INOVER_LSB _u(16)
+#define IO_BANK0_GPIO29_CTRL_INOVER_ACCESS "RW"
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_BANK0_GPIO29_CTRL_OEOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_MSB _u(13)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_LSB _u(12)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_ACCESS "RW"
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_MSB _u(9)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_LSB _u(8)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_ACCESS "RW"
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_BANK0_GPIO29_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_GPIO29_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x01 -> spi1_ss_n
+// 0x02 -> uart0_rx
+// 0x03 -> i2c0_scl
+// 0x04 -> pwm_b_6
+// 0x05 -> sio_29
+// 0x06 -> pio0_29
+// 0x07 -> pio1_29
+// 0x09 -> usb_muxing_vbus_en
+// 0x1f -> null
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_MSB _u(4)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_LSB _u(0)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SPI1_SS_N _u(0x01)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_UART0_RX _u(0x02)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_I2C0_SCL _u(0x03)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PWM_B_6 _u(0x04)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_SIO_29 _u(0x05)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO0_29 _u(0x06)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_PIO1_29 _u(0x07)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_USB_MUXING_VBUS_EN _u(0x09)
+#define IO_BANK0_GPIO29_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_BANK0_INTR0
+// Description : Raw Interrupts
+#define IO_BANK0_INTR0_OFFSET _u(0x000000f0)
+#define IO_BANK0_INTR0_BITS _u(0xffffffff)
+#define IO_BANK0_INTR0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_INTR0_GPIO7_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_INTR0_GPIO7_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_INTR0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_INTR0_GPIO6_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_INTR0_GPIO6_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_INTR0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_INTR0_GPIO5_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_INTR0_GPIO5_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_INTR0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_INTR0_GPIO4_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_INTR0_GPIO4_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_INTR0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_INTR0_GPIO3_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_INTR0_GPIO3_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_INTR0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_INTR0_GPIO2_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_INTR0_GPIO2_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_INTR0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_INTR0_GPIO1_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_INTR0_GPIO1_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_INTR0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_INTR0_GPIO0_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_INTR0_GPIO0_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_INTR0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_INTR1
+// Description : Raw Interrupts
+#define IO_BANK0_INTR1_OFFSET _u(0x000000f4)
+#define IO_BANK0_INTR1_BITS _u(0xffffffff)
+#define IO_BANK0_INTR1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_INTR1_GPIO15_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_INTR1_GPIO15_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_INTR1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_INTR1_GPIO14_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_INTR1_GPIO14_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_INTR1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_INTR1_GPIO13_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_INTR1_GPIO13_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_INTR1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_INTR1_GPIO12_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_INTR1_GPIO12_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_INTR1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_INTR1_GPIO11_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_INTR1_GPIO11_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_INTR1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_INTR1_GPIO10_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_INTR1_GPIO10_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_INTR1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_INTR1_GPIO9_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_INTR1_GPIO9_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_INTR1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_INTR1_GPIO8_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_INTR1_GPIO8_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_INTR1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_INTR2
+// Description : Raw Interrupts
+#define IO_BANK0_INTR2_OFFSET _u(0x000000f8)
+#define IO_BANK0_INTR2_BITS _u(0xffffffff)
+#define IO_BANK0_INTR2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_INTR2_GPIO23_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_INTR2_GPIO23_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_INTR2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_INTR2_GPIO22_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_INTR2_GPIO22_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_INTR2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_INTR2_GPIO21_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_INTR2_GPIO21_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_INTR2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_INTR2_GPIO20_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_INTR2_GPIO20_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_INTR2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_INTR2_GPIO19_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_INTR2_GPIO19_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_INTR2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_INTR2_GPIO18_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_INTR2_GPIO18_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_INTR2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_INTR2_GPIO17_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_INTR2_GPIO17_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_INTR2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_INTR2_GPIO16_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_INTR2_GPIO16_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_INTR2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_INTR3
+// Description : Raw Interrupts
+#define IO_BANK0_INTR3_OFFSET _u(0x000000fc)
+#define IO_BANK0_INTR3_BITS _u(0x00ffffff)
+#define IO_BANK0_INTR3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_INTR3_GPIO29_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_INTR3_GPIO29_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_INTR3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_INTR3_GPIO28_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_INTR3_GPIO28_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_INTR3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_INTR3_GPIO27_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_INTR3_GPIO27_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_INTR3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_INTR3_GPIO26_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_INTR3_GPIO26_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_INTR3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_INTR3_GPIO25_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_INTR3_GPIO25_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_INTR3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_INTR3_GPIO24_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_INTR3_GPIO24_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_INTR3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_INTR3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTE0
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE0_OFFSET _u(0x00000100)
+#define IO_BANK0_PROC0_INTE0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTE1
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE1_OFFSET _u(0x00000104)
+#define IO_BANK0_PROC0_INTE1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTE2
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE2_OFFSET _u(0x00000108)
+#define IO_BANK0_PROC0_INTE2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTE2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTE3
+// Description : Interrupt Enable for proc0
+#define IO_BANK0_PROC0_INTE3_OFFSET _u(0x0000010c)
+#define IO_BANK0_PROC0_INTE3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTE3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTF0
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF0_OFFSET _u(0x00000110)
+#define IO_BANK0_PROC0_INTF0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTF1
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF1_OFFSET _u(0x00000114)
+#define IO_BANK0_PROC0_INTF1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTF2
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF2_OFFSET _u(0x00000118)
+#define IO_BANK0_PROC0_INTF2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTF2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTF3
+// Description : Interrupt Force for proc0
+#define IO_BANK0_PROC0_INTF3_OFFSET _u(0x0000011c)
+#define IO_BANK0_PROC0_INTF3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTF3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTS0
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS0_OFFSET _u(0x00000120)
+#define IO_BANK0_PROC0_INTS0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTS1
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS1_OFFSET _u(0x00000124)
+#define IO_BANK0_PROC0_INTS1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTS2
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS2_OFFSET _u(0x00000128)
+#define IO_BANK0_PROC0_INTS2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC0_INTS2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC0_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC0_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC0_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC0_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC0_INTS3
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_BANK0_PROC0_INTS3_OFFSET _u(0x0000012c)
+#define IO_BANK0_PROC0_INTS3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC0_INTS3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC0_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC0_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC0_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC0_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC0_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC0_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC0_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC0_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC0_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC0_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC0_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC0_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTE0
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE0_OFFSET _u(0x00000130)
+#define IO_BANK0_PROC1_INTE0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTE1
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE1_OFFSET _u(0x00000134)
+#define IO_BANK0_PROC1_INTE1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTE2
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE2_OFFSET _u(0x00000138)
+#define IO_BANK0_PROC1_INTE2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTE2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTE3
+// Description : Interrupt Enable for proc1
+#define IO_BANK0_PROC1_INTE3_OFFSET _u(0x0000013c)
+#define IO_BANK0_PROC1_INTE3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTE3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTF0
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF0_OFFSET _u(0x00000140)
+#define IO_BANK0_PROC1_INTF0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTF1
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF1_OFFSET _u(0x00000144)
+#define IO_BANK0_PROC1_INTF1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTF2
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF2_OFFSET _u(0x00000148)
+#define IO_BANK0_PROC1_INTF2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTF2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTF3
+// Description : Interrupt Force for proc1
+#define IO_BANK0_PROC1_INTF3_OFFSET _u(0x0000014c)
+#define IO_BANK0_PROC1_INTF3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTF3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTS0
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS0_OFFSET _u(0x00000150)
+#define IO_BANK0_PROC1_INTS0_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTS1
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS1_OFFSET _u(0x00000154)
+#define IO_BANK0_PROC1_INTS1_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTS2
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS2_OFFSET _u(0x00000158)
+#define IO_BANK0_PROC1_INTS2_BITS _u(0xffffffff)
+#define IO_BANK0_PROC1_INTS2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_PROC1_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_PROC1_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_PROC1_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_PROC1_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_PROC1_INTS3
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_BANK0_PROC1_INTS3_OFFSET _u(0x0000015c)
+#define IO_BANK0_PROC1_INTS3_BITS _u(0x00ffffff)
+#define IO_BANK0_PROC1_INTS3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_PROC1_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_PROC1_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_PROC1_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_PROC1_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_PROC1_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_PROC1_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_PROC1_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_PROC1_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_PROC1_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_PROC1_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_PROC1_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_PROC1_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTE0
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE0_OFFSET _u(0x00000160)
+#define IO_BANK0_DORMANT_WAKE_INTE0_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTE1
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE1_OFFSET _u(0x00000164)
+#define IO_BANK0_DORMANT_WAKE_INTE1_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTE2
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE2_OFFSET _u(0x00000168)
+#define IO_BANK0_DORMANT_WAKE_INTE2_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTE3
+// Description : Interrupt Enable for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTE3_OFFSET _u(0x0000016c)
+#define IO_BANK0_DORMANT_WAKE_INTE3_BITS _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTE3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTE3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTF0
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF0_OFFSET _u(0x00000170)
+#define IO_BANK0_DORMANT_WAKE_INTF0_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO7_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO6_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO5_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO4_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF0_GPIO0_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTF1
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF1_OFFSET _u(0x00000174)
+#define IO_BANK0_DORMANT_WAKE_INTF1_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO15_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO14_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO13_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO12_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO11_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO10_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO9_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF1_GPIO8_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTF2
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF2_OFFSET _u(0x00000178)
+#define IO_BANK0_DORMANT_WAKE_INTF2_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO23_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO22_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO21_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO20_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO19_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO18_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO17_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF2_GPIO16_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTF3
+// Description : Interrupt Force for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTF3_OFFSET _u(0x0000017c)
+#define IO_BANK0_DORMANT_WAKE_INTF3_BITS _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTF3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO29_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO28_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO27_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO26_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO25_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTF3_GPIO24_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTS0
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS0_OFFSET _u(0x00000180)
+#define IO_BANK0_DORMANT_WAKE_INTS0_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO7_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO6_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO5_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO4_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS0_GPIO0_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTS1
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS1_OFFSET _u(0x00000184)
+#define IO_BANK0_DORMANT_WAKE_INTS1_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO15_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO14_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO13_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO12_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO11_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO10_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO9_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS1_GPIO8_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTS2
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS2_OFFSET _u(0x00000188)
+#define IO_BANK0_DORMANT_WAKE_INTS2_BITS _u(0xffffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_BITS _u(0x80000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_MSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_LSB _u(31)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_BITS _u(0x40000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_MSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_LSB _u(30)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_BITS _u(0x20000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_MSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_LSB _u(29)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_BITS _u(0x10000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_MSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_LSB _u(28)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO23_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_BITS _u(0x08000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_MSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_LSB _u(27)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_BITS _u(0x04000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_MSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_LSB _u(26)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_BITS _u(0x02000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_MSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_LSB _u(25)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_BITS _u(0x01000000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_MSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_LSB _u(24)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO22_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO21_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO20_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO19_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO18_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO17_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS2_GPIO16_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_BANK0_DORMANT_WAKE_INTS3
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_BANK0_DORMANT_WAKE_INTS3_OFFSET _u(0x0000018c)
+#define IO_BANK0_DORMANT_WAKE_INTS3_BITS _u(0x00ffffff)
+#define IO_BANK0_DORMANT_WAKE_INTS3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_MSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_LSB _u(23)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_BITS _u(0x00400000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_MSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_LSB _u(22)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_MSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_LSB _u(21)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_MSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_LSB _u(20)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO29_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_MSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_LSB _u(19)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_BITS _u(0x00040000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_MSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_LSB _u(18)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_MSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_LSB _u(17)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_MSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_LSB _u(16)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO28_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_MSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_LSB _u(15)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_BITS _u(0x00004000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_MSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_LSB _u(14)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_MSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_LSB _u(13)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_MSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_LSB _u(12)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO27_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_MSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_LSB _u(11)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_BITS _u(0x00000400)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_MSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_LSB _u(10)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_MSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_LSB _u(9)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_MSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_LSB _u(8)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO26_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_MSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_LSB _u(7)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_BITS _u(0x00000040)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_MSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_LSB _u(6)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_MSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_LSB _u(5)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_MSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_LSB _u(4)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO25_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_MSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_LSB _u(3)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_BITS _u(0x00000004)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_MSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_LSB _u(2)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_MSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_LSB _u(1)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW
+// Description : None
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_RESET _u(0x0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_MSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_LSB _u(0)
+#define IO_BANK0_DORMANT_WAKE_INTS3_GPIO24_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_IO_BANK0_DEFINED
diff --git a/arkanoid/pico/hardware/regs/io_qspi.h b/arkanoid/pico/hardware/regs/io_qspi.h
new file mode 100644
index 0000000..7c381b7
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/io_qspi.h
@@ -0,0 +1,2931 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : IO_QSPI
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_IO_QSPI_DEFINED
+#define HARDWARE_REGS_IO_QSPI_DEFINED
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SCLK_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET _u(0x00000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_LSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_LSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_LSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SCLK_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET _u(0x00000004)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_LSB _u(28)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_LSB _u(16)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> xip_sclk
+// 0x05 -> sio_30
+// 0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_LSB _u(0)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_XIP_SCLK _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_SIO_30 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SCLK_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SS_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OFFSET _u(0x00000008)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_LSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_LSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_LSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SS_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SS_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OFFSET _u(0x0000000c)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_LSB _u(28)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_LSB _u(16)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> xip_ss_n
+// 0x05 -> sio_31
+// 0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_LSB _u(0)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_XIP_SS_N _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_SIO_31 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SS_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD0_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OFFSET _u(0x00000010)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_LSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_LSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_LSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD0_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD0_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OFFSET _u(0x00000014)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_LSB _u(28)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_LSB _u(16)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> xip_sd0
+// 0x05 -> sio_32
+// 0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_LSB _u(0)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_XIP_SD0 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_SIO_32 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD0_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD1_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OFFSET _u(0x00000018)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_LSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_LSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_LSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD1_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD1_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OFFSET _u(0x0000001c)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_LSB _u(28)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_LSB _u(16)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> xip_sd1
+// 0x05 -> sio_33
+// 0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_LSB _u(0)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_XIP_SD1 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_SIO_33 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD1_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD2_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OFFSET _u(0x00000020)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_LSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_LSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_LSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD2_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD2_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OFFSET _u(0x00000024)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_LSB _u(28)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_LSB _u(16)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> xip_sd2
+// 0x05 -> sio_34
+// 0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_LSB _u(0)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_XIP_SD2 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_SIO_34 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD2_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD3_STATUS
+// Description : GPIO status
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OFFSET _u(0x00000028)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_BITS _u(0x050a3300)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC
+// Description : interrupt to processors, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_BITS _u(0x04000000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_MSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_LSB _u(26)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQTOPROC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD
+// Description : interrupt from pad before override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_BITS _u(0x01000000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_MSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_LSB _u(24)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_IRQFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI
+// Description : input signal to peripheral, after override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_BITS _u(0x00080000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_MSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_LSB _u(19)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INTOPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD
+// Description : input signal from pad, before override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_BITS _u(0x00020000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_LSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_INFROMPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD
+// Description : output enable to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_BITS _u(0x00002000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_LSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OETOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI
+// Description : output enable from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_BITS _u(0x00001000)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_MSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OEFROMPERI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD
+// Description : output signal to pad after register override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_BITS _u(0x00000200)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_LSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTTOPAD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI
+// Description : output signal from selected peripheral, before register
+// override is applied
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_BITS _u(0x00000100)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_MSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD3_STATUS_OUTFROMPERI_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_GPIO_QSPI_SD3_CTRL
+// Description : GPIO control including function select and overrides.
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OFFSET _u(0x0000002c)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_BITS _u(0x3003331f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_RESET _u(0x0000001f)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER
+// Description : 0x0 -> don't invert the interrupt
+// 0x1 -> invert the interrupt
+// 0x2 -> drive interrupt low
+// 0x3 -> drive interrupt high
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_BITS _u(0x30000000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_MSB _u(29)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_LSB _u(28)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_IRQOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER
+// Description : 0x0 -> don't invert the peri input
+// 0x1 -> invert the peri input
+// 0x2 -> drive peri input low
+// 0x3 -> drive peri input high
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_BITS _u(0x00030000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_MSB _u(17)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_LSB _u(16)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_INOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER
+// Description : 0x0 -> drive output enable from peripheral signal selected by
+// funcsel
+// 0x1 -> drive output enable from inverse of peripheral signal
+// selected by funcsel
+// 0x2 -> disable output
+// 0x3 -> enable output
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_BITS _u(0x00003000)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_MSB _u(13)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_LSB _u(12)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_DISABLE _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OEOVER_VALUE_ENABLE _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER
+// Description : 0x0 -> drive output from peripheral signal selected by funcsel
+// 0x1 -> drive output from inverse of peripheral signal selected
+// by funcsel
+// 0x2 -> drive output low
+// 0x3 -> drive output high
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_RESET _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_BITS _u(0x00000300)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_MSB _u(9)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_LSB _u(8)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_NORMAL _u(0x0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_INVERT _u(0x1)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_LOW _u(0x2)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_OUTOVER_VALUE_HIGH _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL
+// Description : 0-31 -> selects pin function according to the gpio table
+// 31 == NULL
+// 0x00 -> xip_sd3
+// 0x05 -> sio_35
+// 0x1f -> null
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_RESET _u(0x1f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_BITS _u(0x0000001f)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_MSB _u(4)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_LSB _u(0)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_ACCESS "RW"
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_XIP_SD3 _u(0x00)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_SIO_35 _u(0x05)
+#define IO_QSPI_GPIO_QSPI_SD3_CTRL_FUNCSEL_VALUE_NULL _u(0x1f)
+// =============================================================================
+// Register : IO_QSPI_INTR
+// Description : Raw Interrupts
+#define IO_QSPI_INTR_OFFSET _u(0x00000030)
+#define IO_QSPI_INTR_BITS _u(0x00ffffff)
+#define IO_QSPI_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_INTR_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_INTR_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_INTR_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_INTR_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_INTR_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_INTR_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_PROC0_INTE
+// Description : Interrupt Enable for proc0
+#define IO_QSPI_PROC0_INTE_OFFSET _u(0x00000034)
+#define IO_QSPI_PROC0_INTE_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_PROC0_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_QSPI_PROC0_INTF
+// Description : Interrupt Force for proc0
+#define IO_QSPI_PROC0_INTF_OFFSET _u(0x00000038)
+#define IO_QSPI_PROC0_INTF_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_PROC0_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_QSPI_PROC0_INTS
+// Description : Interrupt status after masking & forcing for proc0
+#define IO_QSPI_PROC0_INTS_OFFSET _u(0x0000003c)
+#define IO_QSPI_PROC0_INTS_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC0_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_PROC0_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_PROC1_INTE
+// Description : Interrupt Enable for proc1
+#define IO_QSPI_PROC1_INTE_OFFSET _u(0x00000040)
+#define IO_QSPI_PROC1_INTE_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_PROC1_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_QSPI_PROC1_INTF
+// Description : Interrupt Force for proc1
+#define IO_QSPI_PROC1_INTF_OFFSET _u(0x00000044)
+#define IO_QSPI_PROC1_INTF_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_PROC1_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_QSPI_PROC1_INTS
+// Description : Interrupt status after masking & forcing for proc1
+#define IO_QSPI_PROC1_INTS_OFFSET _u(0x00000048)
+#define IO_QSPI_PROC1_INTS_BITS _u(0x00ffffff)
+#define IO_QSPI_PROC1_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_PROC1_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+// Register : IO_QSPI_DORMANT_WAKE_INTE
+// Description : Interrupt Enable for dormant_wake
+#define IO_QSPI_DORMANT_WAKE_INTE_OFFSET _u(0x0000004c)
+#define IO_QSPI_DORMANT_WAKE_INTE_BITS _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTE_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_QSPI_DORMANT_WAKE_INTF
+// Description : Interrupt Force for dormant_wake
+#define IO_QSPI_DORMANT_WAKE_INTF_OFFSET _u(0x00000050)
+#define IO_QSPI_DORMANT_WAKE_INTF_BITS _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTF_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RW"
+// =============================================================================
+// Register : IO_QSPI_DORMANT_WAKE_INTS
+// Description : Interrupt status after masking & forcing for dormant_wake
+#define IO_QSPI_DORMANT_WAKE_INTS_OFFSET _u(0x00000054)
+#define IO_QSPI_DORMANT_WAKE_INTS_BITS _u(0x00ffffff)
+#define IO_QSPI_DORMANT_WAKE_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_BITS _u(0x00800000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_MSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_LSB _u(23)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_BITS _u(0x00400000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_MSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_LSB _u(22)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_BITS _u(0x00200000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_MSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_LSB _u(21)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_BITS _u(0x00100000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_MSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_LSB _u(20)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD3_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_BITS _u(0x00080000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_MSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_LSB _u(19)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_BITS _u(0x00040000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_MSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_LSB _u(18)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_BITS _u(0x00020000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_MSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_LSB _u(17)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_BITS _u(0x00010000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_MSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_LSB _u(16)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD2_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_BITS _u(0x00008000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_MSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_LSB _u(15)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_BITS _u(0x00004000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_MSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_LSB _u(14)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_BITS _u(0x00002000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_MSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_LSB _u(13)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_BITS _u(0x00001000)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_MSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_LSB _u(12)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD1_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_BITS _u(0x00000800)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_MSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_LSB _u(11)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_BITS _u(0x00000400)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_MSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_LSB _u(10)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_BITS _u(0x00000200)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_MSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_LSB _u(9)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_BITS _u(0x00000100)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_MSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_LSB _u(8)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SD0_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_BITS _u(0x00000080)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_MSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_LSB _u(7)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_BITS _u(0x00000040)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_MSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_LSB _u(6)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_BITS _u(0x00000020)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_MSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_LSB _u(5)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_BITS _u(0x00000010)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_MSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_LSB _u(4)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SS_LEVEL_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_BITS _u(0x00000008)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_MSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_LSB _u(3)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_BITS _u(0x00000004)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_MSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_LSB _u(2)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_EDGE_LOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_BITS _u(0x00000002)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_MSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_LSB _u(1)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_HIGH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW
+// Description : None
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_RESET _u(0x0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_BITS _u(0x00000001)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_MSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_LSB _u(0)
+#define IO_QSPI_DORMANT_WAKE_INTS_GPIO_QSPI_SCLK_LEVEL_LOW_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_IO_QSPI_DEFINED
diff --git a/arkanoid/pico/hardware/regs/m0plus.h b/arkanoid/pico/hardware/regs/m0plus.h
new file mode 100644
index 0000000..cef5ab0
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/m0plus.h
@@ -0,0 +1,1149 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : M0PLUS
+// Version : 1
+// Bus type : ahbl
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_M0PLUS_DEFINED
+#define HARDWARE_REGS_M0PLUS_DEFINED
+// =============================================================================
+// Register : M0PLUS_SYST_CSR
+// Description : Use the SysTick Control and Status Register to enable the
+// SysTick features.
+#define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010)
+#define M0PLUS_SYST_CSR_BITS _u(0x00010007)
+#define M0PLUS_SYST_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CSR_COUNTFLAG
+// Description : Returns 1 if timer counted to 0 since last time this was read.
+// Clears on read by application or debugger.
+#define M0PLUS_SYST_CSR_COUNTFLAG_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_COUNTFLAG_BITS _u(0x00010000)
+#define M0PLUS_SYST_CSR_COUNTFLAG_MSB _u(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_LSB _u(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CSR_CLKSOURCE
+// Description : SysTick clock source. Always reads as one if SYST_CALIB reports
+// NOREF.
+// Selects the SysTick timer clock source:
+// 0 = External reference clock.
+// 1 = Processor clock.
+#define M0PLUS_SYST_CSR_CLKSOURCE_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_CLKSOURCE_BITS _u(0x00000004)
+#define M0PLUS_SYST_CSR_CLKSOURCE_MSB _u(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_LSB _u(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CSR_TICKINT
+// Description : Enables SysTick exception request:
+// 0 = Counting down to zero does not assert the SysTick exception
+// request.
+// 1 = Counting down to zero to asserts the SysTick exception
+// request.
+#define M0PLUS_SYST_CSR_TICKINT_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_TICKINT_BITS _u(0x00000002)
+#define M0PLUS_SYST_CSR_TICKINT_MSB _u(1)
+#define M0PLUS_SYST_CSR_TICKINT_LSB _u(1)
+#define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CSR_ENABLE
+// Description : Enable SysTick counter:
+// 0 = Counter disabled.
+// 1 = Counter enabled.
+#define M0PLUS_SYST_CSR_ENABLE_RESET _u(0x0)
+#define M0PLUS_SYST_CSR_ENABLE_BITS _u(0x00000001)
+#define M0PLUS_SYST_CSR_ENABLE_MSB _u(0)
+#define M0PLUS_SYST_CSR_ENABLE_LSB _u(0)
+#define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_SYST_RVR
+// Description : Use the SysTick Reload Value Register to specify the start
+// value to load into the current value register when the counter
+// reaches 0. It can be any value between 0 and 0x00FFFFFF. A
+// start value of 0 is possible, but has no effect because the
+// SysTick interrupt and COUNTFLAG are activated when counting
+// from 1 to 0. The reset value of this register is UNKNOWN.
+// To generate a multi-shot timer with a period of N processor
+// clock cycles, use a RELOAD value of N-1. For example, if the
+// SysTick interrupt is required every 100 clock pulses, set
+// RELOAD to 99.
+#define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014)
+#define M0PLUS_SYST_RVR_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_RVR_RELOAD
+// Description : Value to load into the SysTick Current Value Register when the
+// counter reaches 0.
+#define M0PLUS_SYST_RVR_RELOAD_RESET _u(0x000000)
+#define M0PLUS_SYST_RVR_RELOAD_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RELOAD_MSB _u(23)
+#define M0PLUS_SYST_RVR_RELOAD_LSB _u(0)
+#define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_SYST_CVR
+// Description : Use the SysTick Current Value Register to find the current
+// value in the register. The reset value of this register is
+// UNKNOWN.
+#define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018)
+#define M0PLUS_SYST_CVR_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CVR_CURRENT
+// Description : Reads return the current value of the SysTick counter. This
+// register is write-clear. Writing to it with any value clears
+// the register to 0. Clearing this register also clears the
+// COUNTFLAG bit of the SysTick Control and Status Register.
+#define M0PLUS_SYST_CVR_CURRENT_RESET _u(0x000000)
+#define M0PLUS_SYST_CVR_CURRENT_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_CURRENT_MSB _u(23)
+#define M0PLUS_SYST_CVR_CURRENT_LSB _u(0)
+#define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_SYST_CALIB
+// Description : Use the SysTick Calibration Value Register to enable software
+// to scale to any required speed using divide and multiply.
+#define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c)
+#define M0PLUS_SYST_CALIB_BITS _u(0xc0ffffff)
+#define M0PLUS_SYST_CALIB_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CALIB_NOREF
+// Description : If reads as 1, the Reference clock is not provided - the
+// CLKSOURCE bit of the SysTick Control and Status register will
+// be forced to 1 and cannot be cleared to 0.
+#define M0PLUS_SYST_CALIB_NOREF_RESET _u(0x0)
+#define M0PLUS_SYST_CALIB_NOREF_BITS _u(0x80000000)
+#define M0PLUS_SYST_CALIB_NOREF_MSB _u(31)
+#define M0PLUS_SYST_CALIB_NOREF_LSB _u(31)
+#define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CALIB_SKEW
+// Description : If reads as 1, the calibration value for 10ms is inexact (due
+// to clock frequency).
+#define M0PLUS_SYST_CALIB_SKEW_RESET _u(0x0)
+#define M0PLUS_SYST_CALIB_SKEW_BITS _u(0x40000000)
+#define M0PLUS_SYST_CALIB_SKEW_MSB _u(30)
+#define M0PLUS_SYST_CALIB_SKEW_LSB _u(30)
+#define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SYST_CALIB_TENMS
+// Description : An optional Reload value to be used for 10ms (100Hz) timing,
+// subject to system clock skew errors. If the value reads as 0,
+// the calibration value is not known.
+#define M0PLUS_SYST_CALIB_TENMS_RESET _u(0x000000)
+#define M0PLUS_SYST_CALIB_TENMS_BITS _u(0x00ffffff)
+#define M0PLUS_SYST_CALIB_TENMS_MSB _u(23)
+#define M0PLUS_SYST_CALIB_TENMS_LSB _u(0)
+#define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO"
+// =============================================================================
+// Register : M0PLUS_NVIC_ISER
+// Description : Use the Interrupt Set-Enable Register to enable interrupts and
+// determine which interrupts are currently enabled.
+// If a pending interrupt is enabled, the NVIC activates the
+// interrupt based on its priority. If an interrupt is not
+// enabled, asserting its interrupt signal changes the interrupt
+// state to pending, but the NVIC never activates the interrupt,
+// regardless of its priority.
+#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100)
+#define M0PLUS_NVIC_ISER_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_ISER_SETENA
+// Description : Interrupt set-enable bits.
+// Write:
+// 0 = No effect.
+// 1 = Enable interrupt.
+// Read:
+// 0 = Interrupt disabled.
+// 1 = Interrupt enabled.
+#define M0PLUS_NVIC_ISER_SETENA_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ISER_SETENA_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_SETENA_MSB _u(31)
+#define M0PLUS_NVIC_ISER_SETENA_LSB _u(0)
+#define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_ICER
+// Description : Use the Interrupt Clear-Enable Registers to disable interrupts
+// and determine which interrupts are currently enabled.
+#define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180)
+#define M0PLUS_NVIC_ICER_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_ICER_CLRENA
+// Description : Interrupt clear-enable bits.
+// Write:
+// 0 = No effect.
+// 1 = Disable interrupt.
+// Read:
+// 0 = Interrupt disabled.
+// 1 = Interrupt enabled.
+#define M0PLUS_NVIC_ICER_CLRENA_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ICER_CLRENA_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_CLRENA_MSB _u(31)
+#define M0PLUS_NVIC_ICER_CLRENA_LSB _u(0)
+#define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_ISPR
+// Description : The NVIC_ISPR forces interrupts into the pending state, and
+// shows which interrupts are pending.
+#define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200)
+#define M0PLUS_NVIC_ISPR_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_ISPR_SETPEND
+// Description : Interrupt set-pending bits.
+// Write:
+// 0 = No effect.
+// 1 = Changes interrupt state to pending.
+// Read:
+// 0 = Interrupt is not pending.
+// 1 = Interrupt is pending.
+// Note: Writing 1 to the NVIC_ISPR bit corresponding to:
+// An interrupt that is pending has no effect.
+// A disabled interrupt sets the state of that interrupt to
+// pending.
+#define M0PLUS_NVIC_ISPR_SETPEND_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ISPR_SETPEND_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_SETPEND_MSB _u(31)
+#define M0PLUS_NVIC_ISPR_SETPEND_LSB _u(0)
+#define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_ICPR
+// Description : Use the Interrupt Clear-Pending Register to clear pending
+// interrupts and determine which interrupts are currently
+// pending.
+#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280)
+#define M0PLUS_NVIC_ICPR_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_ICPR_CLRPEND
+// Description : Interrupt clear-pending bits.
+// Write:
+// 0 = No effect.
+// 1 = Removes pending state and interrupt.
+// Read:
+// 0 = Interrupt is not pending.
+// 1 = Interrupt is pending.
+#define M0PLUS_NVIC_ICPR_CLRPEND_RESET _u(0x00000000)
+#define M0PLUS_NVIC_ICPR_CLRPEND_BITS _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_CLRPEND_MSB _u(31)
+#define M0PLUS_NVIC_ICPR_CLRPEND_LSB _u(0)
+#define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR0
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+// Note: Writing 1 to an NVIC_ICPR bit does not affect the active
+// state of the corresponding interrupt.
+// These registers are only word-accessible
+#define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400)
+#define M0PLUS_NVIC_IPR0_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR0_IP_3
+// Description : Priority of interrupt 3
+#define M0PLUS_NVIC_IPR0_IP_3_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_3_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR0_IP_3_MSB _u(31)
+#define M0PLUS_NVIC_IPR0_IP_3_LSB _u(30)
+#define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR0_IP_2
+// Description : Priority of interrupt 2
+#define M0PLUS_NVIC_IPR0_IP_2_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_2_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR0_IP_2_MSB _u(23)
+#define M0PLUS_NVIC_IPR0_IP_2_LSB _u(22)
+#define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR0_IP_1
+// Description : Priority of interrupt 1
+#define M0PLUS_NVIC_IPR0_IP_1_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_1_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR0_IP_1_MSB _u(15)
+#define M0PLUS_NVIC_IPR0_IP_1_LSB _u(14)
+#define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR0_IP_0
+// Description : Priority of interrupt 0
+#define M0PLUS_NVIC_IPR0_IP_0_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_0_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR0_IP_0_MSB _u(7)
+#define M0PLUS_NVIC_IPR0_IP_0_LSB _u(6)
+#define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR1
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404)
+#define M0PLUS_NVIC_IPR1_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR1_IP_7
+// Description : Priority of interrupt 7
+#define M0PLUS_NVIC_IPR1_IP_7_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_7_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR1_IP_7_MSB _u(31)
+#define M0PLUS_NVIC_IPR1_IP_7_LSB _u(30)
+#define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR1_IP_6
+// Description : Priority of interrupt 6
+#define M0PLUS_NVIC_IPR1_IP_6_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_6_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR1_IP_6_MSB _u(23)
+#define M0PLUS_NVIC_IPR1_IP_6_LSB _u(22)
+#define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR1_IP_5
+// Description : Priority of interrupt 5
+#define M0PLUS_NVIC_IPR1_IP_5_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_5_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR1_IP_5_MSB _u(15)
+#define M0PLUS_NVIC_IPR1_IP_5_LSB _u(14)
+#define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR1_IP_4
+// Description : Priority of interrupt 4
+#define M0PLUS_NVIC_IPR1_IP_4_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_4_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR1_IP_4_MSB _u(7)
+#define M0PLUS_NVIC_IPR1_IP_4_LSB _u(6)
+#define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR2
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408)
+#define M0PLUS_NVIC_IPR2_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR2_IP_11
+// Description : Priority of interrupt 11
+#define M0PLUS_NVIC_IPR2_IP_11_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_11_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR2_IP_11_MSB _u(31)
+#define M0PLUS_NVIC_IPR2_IP_11_LSB _u(30)
+#define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR2_IP_10
+// Description : Priority of interrupt 10
+#define M0PLUS_NVIC_IPR2_IP_10_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_10_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR2_IP_10_MSB _u(23)
+#define M0PLUS_NVIC_IPR2_IP_10_LSB _u(22)
+#define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR2_IP_9
+// Description : Priority of interrupt 9
+#define M0PLUS_NVIC_IPR2_IP_9_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_9_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR2_IP_9_MSB _u(15)
+#define M0PLUS_NVIC_IPR2_IP_9_LSB _u(14)
+#define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR2_IP_8
+// Description : Priority of interrupt 8
+#define M0PLUS_NVIC_IPR2_IP_8_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_8_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR2_IP_8_MSB _u(7)
+#define M0PLUS_NVIC_IPR2_IP_8_LSB _u(6)
+#define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR3
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c)
+#define M0PLUS_NVIC_IPR3_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR3_IP_15
+// Description : Priority of interrupt 15
+#define M0PLUS_NVIC_IPR3_IP_15_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_15_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR3_IP_15_MSB _u(31)
+#define M0PLUS_NVIC_IPR3_IP_15_LSB _u(30)
+#define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR3_IP_14
+// Description : Priority of interrupt 14
+#define M0PLUS_NVIC_IPR3_IP_14_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_14_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR3_IP_14_MSB _u(23)
+#define M0PLUS_NVIC_IPR3_IP_14_LSB _u(22)
+#define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR3_IP_13
+// Description : Priority of interrupt 13
+#define M0PLUS_NVIC_IPR3_IP_13_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_13_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR3_IP_13_MSB _u(15)
+#define M0PLUS_NVIC_IPR3_IP_13_LSB _u(14)
+#define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR3_IP_12
+// Description : Priority of interrupt 12
+#define M0PLUS_NVIC_IPR3_IP_12_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_12_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR3_IP_12_MSB _u(7)
+#define M0PLUS_NVIC_IPR3_IP_12_LSB _u(6)
+#define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR4
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410)
+#define M0PLUS_NVIC_IPR4_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR4_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR4_IP_19
+// Description : Priority of interrupt 19
+#define M0PLUS_NVIC_IPR4_IP_19_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_19_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR4_IP_19_MSB _u(31)
+#define M0PLUS_NVIC_IPR4_IP_19_LSB _u(30)
+#define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR4_IP_18
+// Description : Priority of interrupt 18
+#define M0PLUS_NVIC_IPR4_IP_18_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_18_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR4_IP_18_MSB _u(23)
+#define M0PLUS_NVIC_IPR4_IP_18_LSB _u(22)
+#define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR4_IP_17
+// Description : Priority of interrupt 17
+#define M0PLUS_NVIC_IPR4_IP_17_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_17_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR4_IP_17_MSB _u(15)
+#define M0PLUS_NVIC_IPR4_IP_17_LSB _u(14)
+#define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR4_IP_16
+// Description : Priority of interrupt 16
+#define M0PLUS_NVIC_IPR4_IP_16_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_16_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR4_IP_16_MSB _u(7)
+#define M0PLUS_NVIC_IPR4_IP_16_LSB _u(6)
+#define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR5
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414)
+#define M0PLUS_NVIC_IPR5_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR5_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR5_IP_23
+// Description : Priority of interrupt 23
+#define M0PLUS_NVIC_IPR5_IP_23_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_23_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR5_IP_23_MSB _u(31)
+#define M0PLUS_NVIC_IPR5_IP_23_LSB _u(30)
+#define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR5_IP_22
+// Description : Priority of interrupt 22
+#define M0PLUS_NVIC_IPR5_IP_22_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_22_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR5_IP_22_MSB _u(23)
+#define M0PLUS_NVIC_IPR5_IP_22_LSB _u(22)
+#define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR5_IP_21
+// Description : Priority of interrupt 21
+#define M0PLUS_NVIC_IPR5_IP_21_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_21_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR5_IP_21_MSB _u(15)
+#define M0PLUS_NVIC_IPR5_IP_21_LSB _u(14)
+#define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR5_IP_20
+// Description : Priority of interrupt 20
+#define M0PLUS_NVIC_IPR5_IP_20_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_20_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR5_IP_20_MSB _u(7)
+#define M0PLUS_NVIC_IPR5_IP_20_LSB _u(6)
+#define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR6
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418)
+#define M0PLUS_NVIC_IPR6_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR6_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR6_IP_27
+// Description : Priority of interrupt 27
+#define M0PLUS_NVIC_IPR6_IP_27_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_27_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR6_IP_27_MSB _u(31)
+#define M0PLUS_NVIC_IPR6_IP_27_LSB _u(30)
+#define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR6_IP_26
+// Description : Priority of interrupt 26
+#define M0PLUS_NVIC_IPR6_IP_26_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_26_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR6_IP_26_MSB _u(23)
+#define M0PLUS_NVIC_IPR6_IP_26_LSB _u(22)
+#define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR6_IP_25
+// Description : Priority of interrupt 25
+#define M0PLUS_NVIC_IPR6_IP_25_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_25_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR6_IP_25_MSB _u(15)
+#define M0PLUS_NVIC_IPR6_IP_25_LSB _u(14)
+#define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR6_IP_24
+// Description : Priority of interrupt 24
+#define M0PLUS_NVIC_IPR6_IP_24_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_24_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR6_IP_24_MSB _u(7)
+#define M0PLUS_NVIC_IPR6_IP_24_LSB _u(6)
+#define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_NVIC_IPR7
+// Description : Use the Interrupt Priority Registers to assign a priority from
+// 0 to 3 to each of the available interrupts. 0 is the highest
+// priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c)
+#define M0PLUS_NVIC_IPR7_BITS _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR7_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR7_IP_31
+// Description : Priority of interrupt 31
+#define M0PLUS_NVIC_IPR7_IP_31_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_31_BITS _u(0xc0000000)
+#define M0PLUS_NVIC_IPR7_IP_31_MSB _u(31)
+#define M0PLUS_NVIC_IPR7_IP_31_LSB _u(30)
+#define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR7_IP_30
+// Description : Priority of interrupt 30
+#define M0PLUS_NVIC_IPR7_IP_30_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_30_BITS _u(0x00c00000)
+#define M0PLUS_NVIC_IPR7_IP_30_MSB _u(23)
+#define M0PLUS_NVIC_IPR7_IP_30_LSB _u(22)
+#define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR7_IP_29
+// Description : Priority of interrupt 29
+#define M0PLUS_NVIC_IPR7_IP_29_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_29_BITS _u(0x0000c000)
+#define M0PLUS_NVIC_IPR7_IP_29_MSB _u(15)
+#define M0PLUS_NVIC_IPR7_IP_29_LSB _u(14)
+#define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_NVIC_IPR7_IP_28
+// Description : Priority of interrupt 28
+#define M0PLUS_NVIC_IPR7_IP_28_RESET _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_28_BITS _u(0x000000c0)
+#define M0PLUS_NVIC_IPR7_IP_28_MSB _u(7)
+#define M0PLUS_NVIC_IPR7_IP_28_LSB _u(6)
+#define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_CPUID
+// Description : Read the CPU ID Base Register to determine: the ID number of
+// the processor core, the version number of the processor core,
+// the implementation details of the processor core.
+#define M0PLUS_CPUID_OFFSET _u(0x0000ed00)
+#define M0PLUS_CPUID_BITS _u(0xffffffff)
+#define M0PLUS_CPUID_RESET _u(0x410cc601)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_CPUID_IMPLEMENTER
+// Description : Implementor code: 0x41 = ARM
+#define M0PLUS_CPUID_IMPLEMENTER_RESET _u(0x41)
+#define M0PLUS_CPUID_IMPLEMENTER_BITS _u(0xff000000)
+#define M0PLUS_CPUID_IMPLEMENTER_MSB _u(31)
+#define M0PLUS_CPUID_IMPLEMENTER_LSB _u(24)
+#define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_CPUID_VARIANT
+// Description : Major revision number n in the rnpm revision status:
+// 0x0 = Revision 0.
+#define M0PLUS_CPUID_VARIANT_RESET _u(0x0)
+#define M0PLUS_CPUID_VARIANT_BITS _u(0x00f00000)
+#define M0PLUS_CPUID_VARIANT_MSB _u(23)
+#define M0PLUS_CPUID_VARIANT_LSB _u(20)
+#define M0PLUS_CPUID_VARIANT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_CPUID_ARCHITECTURE
+// Description : Constant that defines the architecture of the processor:
+// 0xC = ARMv6-M architecture.
+#define M0PLUS_CPUID_ARCHITECTURE_RESET _u(0xc)
+#define M0PLUS_CPUID_ARCHITECTURE_BITS _u(0x000f0000)
+#define M0PLUS_CPUID_ARCHITECTURE_MSB _u(19)
+#define M0PLUS_CPUID_ARCHITECTURE_LSB _u(16)
+#define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_CPUID_PARTNO
+// Description : Number of processor within family: 0xC60 = Cortex-M0+
+#define M0PLUS_CPUID_PARTNO_RESET _u(0xc60)
+#define M0PLUS_CPUID_PARTNO_BITS _u(0x0000fff0)
+#define M0PLUS_CPUID_PARTNO_MSB _u(15)
+#define M0PLUS_CPUID_PARTNO_LSB _u(4)
+#define M0PLUS_CPUID_PARTNO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_CPUID_REVISION
+// Description : Minor revision number m in the rnpm revision status:
+// 0x1 = Patch 1.
+#define M0PLUS_CPUID_REVISION_RESET _u(0x1)
+#define M0PLUS_CPUID_REVISION_BITS _u(0x0000000f)
+#define M0PLUS_CPUID_REVISION_MSB _u(3)
+#define M0PLUS_CPUID_REVISION_LSB _u(0)
+#define M0PLUS_CPUID_REVISION_ACCESS "RO"
+// =============================================================================
+// Register : M0PLUS_ICSR
+// Description : Use the Interrupt Control State Register to set a pending
+// Non-Maskable Interrupt (NMI), set or clear a pending PendSV,
+// set or clear a pending SysTick, check for pending exceptions,
+// check the vector number of the highest priority pended
+// exception, check the vector number of the active exception.
+#define M0PLUS_ICSR_OFFSET _u(0x0000ed04)
+#define M0PLUS_ICSR_BITS _u(0x9edff1ff)
+#define M0PLUS_ICSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_NMIPENDSET
+// Description : Setting this bit will activate an NMI. Since NMI is the highest
+// priority exception, it will activate as soon as it is
+// registered.
+// NMI set-pending bit.
+// Write:
+// 0 = No effect.
+// 1 = Changes NMI exception state to pending.
+// Read:
+// 0 = NMI exception is not pending.
+// 1 = NMI exception is pending.
+// Because NMI is the highest-priority exception, normally the
+// processor enters the NMI
+// exception handler as soon as it detects a write of 1 to this
+// bit. Entering the handler then clears
+// this bit to 0. This means a read of this bit by the NMI
+// exception handler returns 1 only if the
+// NMI signal is reasserted while the processor is executing that
+// handler.
+#define M0PLUS_ICSR_NMIPENDSET_RESET _u(0x0)
+#define M0PLUS_ICSR_NMIPENDSET_BITS _u(0x80000000)
+#define M0PLUS_ICSR_NMIPENDSET_MSB _u(31)
+#define M0PLUS_ICSR_NMIPENDSET_LSB _u(31)
+#define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_PENDSVSET
+// Description : PendSV set-pending bit.
+// Write:
+// 0 = No effect.
+// 1 = Changes PendSV exception state to pending.
+// Read:
+// 0 = PendSV exception is not pending.
+// 1 = PendSV exception is pending.
+// Writing 1 to this bit is the only way to set the PendSV
+// exception state to pending.
+#define M0PLUS_ICSR_PENDSVSET_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSVSET_BITS _u(0x10000000)
+#define M0PLUS_ICSR_PENDSVSET_MSB _u(28)
+#define M0PLUS_ICSR_PENDSVSET_LSB _u(28)
+#define M0PLUS_ICSR_PENDSVSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_PENDSVCLR
+// Description : PendSV clear-pending bit.
+// Write:
+// 0 = No effect.
+// 1 = Removes the pending state from the PendSV exception.
+#define M0PLUS_ICSR_PENDSVCLR_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSVCLR_BITS _u(0x08000000)
+#define M0PLUS_ICSR_PENDSVCLR_MSB _u(27)
+#define M0PLUS_ICSR_PENDSVCLR_LSB _u(27)
+#define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_PENDSTSET
+// Description : SysTick exception set-pending bit.
+// Write:
+// 0 = No effect.
+// 1 = Changes SysTick exception state to pending.
+// Read:
+// 0 = SysTick exception is not pending.
+// 1 = SysTick exception is pending.
+#define M0PLUS_ICSR_PENDSTSET_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSTSET_BITS _u(0x04000000)
+#define M0PLUS_ICSR_PENDSTSET_MSB _u(26)
+#define M0PLUS_ICSR_PENDSTSET_LSB _u(26)
+#define M0PLUS_ICSR_PENDSTSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_PENDSTCLR
+// Description : SysTick exception clear-pending bit.
+// Write:
+// 0 = No effect.
+// 1 = Removes the pending state from the SysTick exception.
+// This bit is WO. On a register read its value is Unknown.
+#define M0PLUS_ICSR_PENDSTCLR_RESET _u(0x0)
+#define M0PLUS_ICSR_PENDSTCLR_BITS _u(0x02000000)
+#define M0PLUS_ICSR_PENDSTCLR_MSB _u(25)
+#define M0PLUS_ICSR_PENDSTCLR_LSB _u(25)
+#define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_ISRPREEMPT
+// Description : The system can only access this bit when the core is halted. It
+// indicates that a pending interrupt is to be taken in the next
+// running cycle. If C_MASKINTS is clear in the Debug Halting
+// Control and Status Register, the interrupt is serviced.
+#define M0PLUS_ICSR_ISRPREEMPT_RESET _u(0x0)
+#define M0PLUS_ICSR_ISRPREEMPT_BITS _u(0x00800000)
+#define M0PLUS_ICSR_ISRPREEMPT_MSB _u(23)
+#define M0PLUS_ICSR_ISRPREEMPT_LSB _u(23)
+#define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_ISRPENDING
+// Description : External interrupt pending flag
+#define M0PLUS_ICSR_ISRPENDING_RESET _u(0x0)
+#define M0PLUS_ICSR_ISRPENDING_BITS _u(0x00400000)
+#define M0PLUS_ICSR_ISRPENDING_MSB _u(22)
+#define M0PLUS_ICSR_ISRPENDING_LSB _u(22)
+#define M0PLUS_ICSR_ISRPENDING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_VECTPENDING
+// Description : Indicates the exception number for the highest priority pending
+// exception: 0 = no pending exceptions. Non zero = The pending
+// state includes the effect of memory-mapped enable and mask
+// registers. It does not include the PRIMASK special-purpose
+// register qualifier.
+#define M0PLUS_ICSR_VECTPENDING_RESET _u(0x000)
+#define M0PLUS_ICSR_VECTPENDING_BITS _u(0x001ff000)
+#define M0PLUS_ICSR_VECTPENDING_MSB _u(20)
+#define M0PLUS_ICSR_VECTPENDING_LSB _u(12)
+#define M0PLUS_ICSR_VECTPENDING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_ICSR_VECTACTIVE
+// Description : Active exception number field. Reset clears the VECTACTIVE
+// field.
+#define M0PLUS_ICSR_VECTACTIVE_RESET _u(0x000)
+#define M0PLUS_ICSR_VECTACTIVE_BITS _u(0x000001ff)
+#define M0PLUS_ICSR_VECTACTIVE_MSB _u(8)
+#define M0PLUS_ICSR_VECTACTIVE_LSB _u(0)
+#define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO"
+// =============================================================================
+// Register : M0PLUS_VTOR
+// Description : The VTOR holds the vector table offset address.
+#define M0PLUS_VTOR_OFFSET _u(0x0000ed08)
+#define M0PLUS_VTOR_BITS _u(0xffffff00)
+#define M0PLUS_VTOR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_VTOR_TBLOFF
+// Description : Bits [31:8] of the indicate the vector table offset address.
+#define M0PLUS_VTOR_TBLOFF_RESET _u(0x000000)
+#define M0PLUS_VTOR_TBLOFF_BITS _u(0xffffff00)
+#define M0PLUS_VTOR_TBLOFF_MSB _u(31)
+#define M0PLUS_VTOR_TBLOFF_LSB _u(8)
+#define M0PLUS_VTOR_TBLOFF_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_AIRCR
+// Description : Use the Application Interrupt and Reset Control Register to:
+// determine data endianness, clear all active state information
+// from debug halt mode, request a system reset.
+#define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c)
+#define M0PLUS_AIRCR_BITS _u(0xffff8006)
+#define M0PLUS_AIRCR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_AIRCR_VECTKEY
+// Description : Register key:
+// Reads as Unknown
+// On writes, write 0x05FA to VECTKEY, otherwise the write is
+// ignored.
+#define M0PLUS_AIRCR_VECTKEY_RESET _u(0x0000)
+#define M0PLUS_AIRCR_VECTKEY_BITS _u(0xffff0000)
+#define M0PLUS_AIRCR_VECTKEY_MSB _u(31)
+#define M0PLUS_AIRCR_VECTKEY_LSB _u(16)
+#define M0PLUS_AIRCR_VECTKEY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_AIRCR_ENDIANESS
+// Description : Data endianness implemented:
+// 0 = Little-endian.
+#define M0PLUS_AIRCR_ENDIANESS_RESET _u(0x0)
+#define M0PLUS_AIRCR_ENDIANESS_BITS _u(0x00008000)
+#define M0PLUS_AIRCR_ENDIANESS_MSB _u(15)
+#define M0PLUS_AIRCR_ENDIANESS_LSB _u(15)
+#define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_AIRCR_SYSRESETREQ
+// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the
+// outer system to be asserted to request a reset. The intention
+// is to force a large system reset of all major components except
+// for debug. The C_HALT bit in the DHCSR is cleared as a result
+// of the system reset requested. The debugger does not lose
+// contact with the device.
+#define M0PLUS_AIRCR_SYSRESETREQ_RESET _u(0x0)
+#define M0PLUS_AIRCR_SYSRESETREQ_BITS _u(0x00000004)
+#define M0PLUS_AIRCR_SYSRESETREQ_MSB _u(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_LSB _u(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_AIRCR_VECTCLRACTIVE
+// Description : Clears all active state information for fixed and configurable
+// exceptions. This bit: is self-clearing, can only be set by the
+// DAP when the core is halted. When set: clears all active
+// exception status of the processor, forces a return to Thread
+// mode, forces an IPSR of 0. A debugger must re-initialize the
+// stack.
+#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET _u(0x0)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS _u(0x00000002)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB _u(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB _u(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_SCR
+// Description : System Control Register. Use the System Control Register for
+// power-management functions: signal to the system when the
+// processor can enter a low power state, control how the
+// processor enters and exits low power states.
+#define M0PLUS_SCR_OFFSET _u(0x0000ed10)
+#define M0PLUS_SCR_BITS _u(0x00000016)
+#define M0PLUS_SCR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SCR_SEVONPEND
+// Description : Send Event on Pending bit:
+// 0 = Only enabled interrupts or events can wakeup the processor,
+// disabled interrupts are excluded.
+// 1 = Enabled events and all interrupts, including disabled
+// interrupts, can wakeup the processor.
+// When an event or interrupt becomes pending, the event signal
+// wakes up the processor from WFE. If the
+// processor is not waiting for an event, the event is registered
+// and affects the next WFE.
+// The processor also wakes up on execution of an SEV instruction
+// or an external event.
+#define M0PLUS_SCR_SEVONPEND_RESET _u(0x0)
+#define M0PLUS_SCR_SEVONPEND_BITS _u(0x00000010)
+#define M0PLUS_SCR_SEVONPEND_MSB _u(4)
+#define M0PLUS_SCR_SEVONPEND_LSB _u(4)
+#define M0PLUS_SCR_SEVONPEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SCR_SLEEPDEEP
+// Description : Controls whether the processor uses sleep or deep sleep as its
+// low power mode:
+// 0 = Sleep.
+// 1 = Deep sleep.
+#define M0PLUS_SCR_SLEEPDEEP_RESET _u(0x0)
+#define M0PLUS_SCR_SLEEPDEEP_BITS _u(0x00000004)
+#define M0PLUS_SCR_SLEEPDEEP_MSB _u(2)
+#define M0PLUS_SCR_SLEEPDEEP_LSB _u(2)
+#define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SCR_SLEEPONEXIT
+// Description : Indicates sleep-on-exit when returning from Handler mode to
+// Thread mode:
+// 0 = Do not sleep when returning to Thread mode.
+// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread
+// mode.
+// Setting this bit to 1 enables an interrupt driven application
+// to avoid returning to an empty main application.
+#define M0PLUS_SCR_SLEEPONEXIT_RESET _u(0x0)
+#define M0PLUS_SCR_SLEEPONEXIT_BITS _u(0x00000002)
+#define M0PLUS_SCR_SLEEPONEXIT_MSB _u(1)
+#define M0PLUS_SCR_SLEEPONEXIT_LSB _u(1)
+#define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_CCR
+// Description : The Configuration and Control Register permanently enables
+// stack alignment and causes unaligned accesses to result in a
+// Hard Fault.
+#define M0PLUS_CCR_OFFSET _u(0x0000ed14)
+#define M0PLUS_CCR_BITS _u(0x00000208)
+#define M0PLUS_CCR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_CCR_STKALIGN
+// Description : Always reads as one, indicates 8-byte stack alignment on
+// exception entry. On exception entry, the processor uses bit[9]
+// of the stacked PSR to indicate the stack alignment. On return
+// from the exception it uses this stacked bit to restore the
+// correct stack alignment.
+#define M0PLUS_CCR_STKALIGN_RESET _u(0x0)
+#define M0PLUS_CCR_STKALIGN_BITS _u(0x00000200)
+#define M0PLUS_CCR_STKALIGN_MSB _u(9)
+#define M0PLUS_CCR_STKALIGN_LSB _u(9)
+#define M0PLUS_CCR_STKALIGN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_CCR_UNALIGN_TRP
+// Description : Always reads as one, indicates that all unaligned accesses
+// generate a HardFault.
+#define M0PLUS_CCR_UNALIGN_TRP_RESET _u(0x0)
+#define M0PLUS_CCR_UNALIGN_TRP_BITS _u(0x00000008)
+#define M0PLUS_CCR_UNALIGN_TRP_MSB _u(3)
+#define M0PLUS_CCR_UNALIGN_TRP_LSB _u(3)
+#define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO"
+// =============================================================================
+// Register : M0PLUS_SHPR2
+// Description : System handlers are a special class of exception handler that
+// can have their priority set to any of the priority levels. Use
+// the System Handler Priority Register 2 to set the priority of
+// SVCall.
+#define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c)
+#define M0PLUS_SHPR2_BITS _u(0xc0000000)
+#define M0PLUS_SHPR2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SHPR2_PRI_11
+// Description : Priority of system handler 11, SVCall
+#define M0PLUS_SHPR2_PRI_11_RESET _u(0x0)
+#define M0PLUS_SHPR2_PRI_11_BITS _u(0xc0000000)
+#define M0PLUS_SHPR2_PRI_11_MSB _u(31)
+#define M0PLUS_SHPR2_PRI_11_LSB _u(30)
+#define M0PLUS_SHPR2_PRI_11_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_SHPR3
+// Description : System handlers are a special class of exception handler that
+// can have their priority set to any of the priority levels. Use
+// the System Handler Priority Register 3 to set the priority of
+// PendSV and SysTick.
+#define M0PLUS_SHPR3_OFFSET _u(0x0000ed20)
+#define M0PLUS_SHPR3_BITS _u(0xc0c00000)
+#define M0PLUS_SHPR3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SHPR3_PRI_15
+// Description : Priority of system handler 15, SysTick
+#define M0PLUS_SHPR3_PRI_15_RESET _u(0x0)
+#define M0PLUS_SHPR3_PRI_15_BITS _u(0xc0000000)
+#define M0PLUS_SHPR3_PRI_15_MSB _u(31)
+#define M0PLUS_SHPR3_PRI_15_LSB _u(30)
+#define M0PLUS_SHPR3_PRI_15_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SHPR3_PRI_14
+// Description : Priority of system handler 14, PendSV
+#define M0PLUS_SHPR3_PRI_14_RESET _u(0x0)
+#define M0PLUS_SHPR3_PRI_14_BITS _u(0x00c00000)
+#define M0PLUS_SHPR3_PRI_14_MSB _u(23)
+#define M0PLUS_SHPR3_PRI_14_LSB _u(22)
+#define M0PLUS_SHPR3_PRI_14_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_SHCSR
+// Description : Use the System Handler Control and State Register to determine
+// or clear the pending status of SVCall.
+#define M0PLUS_SHCSR_OFFSET _u(0x0000ed24)
+#define M0PLUS_SHCSR_BITS _u(0x00008000)
+#define M0PLUS_SHCSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_SHCSR_SVCALLPENDED
+// Description : Reads as 1 if SVCall is Pending. Write 1 to set pending
+// SVCall, write 0 to clear pending SVCall.
+#define M0PLUS_SHCSR_SVCALLPENDED_RESET _u(0x0)
+#define M0PLUS_SHCSR_SVCALLPENDED_BITS _u(0x00008000)
+#define M0PLUS_SHCSR_SVCALLPENDED_MSB _u(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_LSB _u(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_MPU_TYPE
+// Description : Read the MPU Type Register to determine if the processor
+// implements an MPU, and how many regions the MPU supports.
+#define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90)
+#define M0PLUS_MPU_TYPE_BITS _u(0x00ffff01)
+#define M0PLUS_MPU_TYPE_RESET _u(0x00000800)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_TYPE_IREGION
+// Description : Instruction region. Reads as zero as ARMv6-M only supports a
+// unified MPU.
+#define M0PLUS_MPU_TYPE_IREGION_RESET _u(0x00)
+#define M0PLUS_MPU_TYPE_IREGION_BITS _u(0x00ff0000)
+#define M0PLUS_MPU_TYPE_IREGION_MSB _u(23)
+#define M0PLUS_MPU_TYPE_IREGION_LSB _u(16)
+#define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_TYPE_DREGION
+// Description : Number of regions supported by the MPU.
+#define M0PLUS_MPU_TYPE_DREGION_RESET _u(0x08)
+#define M0PLUS_MPU_TYPE_DREGION_BITS _u(0x0000ff00)
+#define M0PLUS_MPU_TYPE_DREGION_MSB _u(15)
+#define M0PLUS_MPU_TYPE_DREGION_LSB _u(8)
+#define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_TYPE_SEPARATE
+// Description : Indicates support for separate instruction and data address
+// maps. Reads as 0 as ARMv6-M only supports a unified MPU.
+#define M0PLUS_MPU_TYPE_SEPARATE_RESET _u(0x0)
+#define M0PLUS_MPU_TYPE_SEPARATE_BITS _u(0x00000001)
+#define M0PLUS_MPU_TYPE_SEPARATE_MSB _u(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_LSB _u(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO"
+// =============================================================================
+// Register : M0PLUS_MPU_CTRL
+// Description : Use the MPU Control Register to enable and disable the MPU, and
+// to control whether the default memory map is enabled as a
+// background region for privileged accesses, and whether the MPU
+// is enabled for HardFaults and NMIs.
+#define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94)
+#define M0PLUS_MPU_CTRL_BITS _u(0x00000007)
+#define M0PLUS_MPU_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_CTRL_PRIVDEFENA
+// Description : Controls whether the default memory map is enabled as a
+// background region for privileged accesses. This bit is ignored
+// when ENABLE is clear.
+// 0 = If the MPU is enabled, disables use of the default memory
+// map. Any memory access to a location not
+// covered by any enabled region causes a fault.
+// 1 = If the MPU is enabled, enables use of the default memory
+// map as a background region for privileged software accesses.
+// When enabled, the background region acts as if it is region
+// number -1. Any region that is defined and enabled has priority
+// over this default map.
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET _u(0x0)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS _u(0x00000004)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB _u(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB _u(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_CTRL_HFNMIENA
+// Description : Controls the use of the MPU for HardFaults and NMIs. Setting
+// this bit when ENABLE is clear results in UNPREDICTABLE
+// behaviour.
+// When the MPU is enabled:
+// 0 = MPU is disabled during HardFault and NMI handlers,
+// regardless of the value of the ENABLE bit.
+// 1 = the MPU is enabled during HardFault and NMI handlers.
+#define M0PLUS_MPU_CTRL_HFNMIENA_RESET _u(0x0)
+#define M0PLUS_MPU_CTRL_HFNMIENA_BITS _u(0x00000002)
+#define M0PLUS_MPU_CTRL_HFNMIENA_MSB _u(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_LSB _u(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_CTRL_ENABLE
+// Description : Enables the MPU. If the MPU is disabled, privileged and
+// unprivileged accesses use the default memory map.
+// 0 = MPU disabled.
+// 1 = MPU enabled.
+#define M0PLUS_MPU_CTRL_ENABLE_RESET _u(0x0)
+#define M0PLUS_MPU_CTRL_ENABLE_BITS _u(0x00000001)
+#define M0PLUS_MPU_CTRL_ENABLE_MSB _u(0)
+#define M0PLUS_MPU_CTRL_ENABLE_LSB _u(0)
+#define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_MPU_RNR
+// Description : Use the MPU Region Number Register to select the region
+// currently accessed by MPU_RBAR and MPU_RASR.
+#define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98)
+#define M0PLUS_MPU_RNR_BITS _u(0x0000000f)
+#define M0PLUS_MPU_RNR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RNR_REGION
+// Description : Indicates the MPU region referenced by the MPU_RBAR and
+// MPU_RASR registers.
+// The MPU supports 8 memory regions, so the permitted values of
+// this field are 0-7.
+#define M0PLUS_MPU_RNR_REGION_RESET _u(0x0)
+#define M0PLUS_MPU_RNR_REGION_BITS _u(0x0000000f)
+#define M0PLUS_MPU_RNR_REGION_MSB _u(3)
+#define M0PLUS_MPU_RNR_REGION_LSB _u(0)
+#define M0PLUS_MPU_RNR_REGION_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_MPU_RBAR
+// Description : Read the MPU Region Base Address Register to determine the base
+// address of the region identified by MPU_RNR. Write to update
+// the base address of said region or that of a specified region,
+// with whose number MPU_RNR will also be updated.
+#define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c)
+#define M0PLUS_MPU_RBAR_BITS _u(0xffffff1f)
+#define M0PLUS_MPU_RBAR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RBAR_ADDR
+// Description : Base address of the region.
+#define M0PLUS_MPU_RBAR_ADDR_RESET _u(0x000000)
+#define M0PLUS_MPU_RBAR_ADDR_BITS _u(0xffffff00)
+#define M0PLUS_MPU_RBAR_ADDR_MSB _u(31)
+#define M0PLUS_MPU_RBAR_ADDR_LSB _u(8)
+#define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RBAR_VALID
+// Description : On writes, indicates whether the write must update the base
+// address of the region identified by the REGION field, updating
+// the MPU_RNR to indicate this new region.
+// Write:
+// 0 = MPU_RNR not changed, and the processor:
+// Updates the base address for the region specified in the
+// MPU_RNR.
+// Ignores the value of the REGION field.
+// 1 = The processor:
+// Updates the value of the MPU_RNR to the value of the REGION
+// field.
+// Updates the base address for the region specified in the REGION
+// field.
+// Always reads as zero.
+#define M0PLUS_MPU_RBAR_VALID_RESET _u(0x0)
+#define M0PLUS_MPU_RBAR_VALID_BITS _u(0x00000010)
+#define M0PLUS_MPU_RBAR_VALID_MSB _u(4)
+#define M0PLUS_MPU_RBAR_VALID_LSB _u(4)
+#define M0PLUS_MPU_RBAR_VALID_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RBAR_REGION
+// Description : On writes, specifies the number of the region whose base
+// address to update provided VALID is set written as 1. On reads,
+// returns bits [3:0] of MPU_RNR.
+#define M0PLUS_MPU_RBAR_REGION_RESET _u(0x0)
+#define M0PLUS_MPU_RBAR_REGION_BITS _u(0x0000000f)
+#define M0PLUS_MPU_RBAR_REGION_MSB _u(3)
+#define M0PLUS_MPU_RBAR_REGION_LSB _u(0)
+#define M0PLUS_MPU_RBAR_REGION_ACCESS "RW"
+// =============================================================================
+// Register : M0PLUS_MPU_RASR
+// Description : Use the MPU Region Attribute and Size Register to define the
+// size, access behaviour and memory type of the region identified
+// by MPU_RNR, and enable that region.
+#define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0)
+#define M0PLUS_MPU_RASR_BITS _u(0xffffff3f)
+#define M0PLUS_MPU_RASR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RASR_ATTRS
+// Description : The MPU Region Attribute field. Use to define the region
+// attribute control.
+// 28 = XN: Instruction access disable bit:
+// 0 = Instruction fetches enabled.
+// 1 = Instruction fetches disabled.
+// 26:24 = AP: Access permission field
+// 18 = S: Shareable bit
+// 17 = C: Cacheable bit
+// 16 = B: Bufferable bit
+#define M0PLUS_MPU_RASR_ATTRS_RESET _u(0x0000)
+#define M0PLUS_MPU_RASR_ATTRS_BITS _u(0xffff0000)
+#define M0PLUS_MPU_RASR_ATTRS_MSB _u(31)
+#define M0PLUS_MPU_RASR_ATTRS_LSB _u(16)
+#define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RASR_SRD
+// Description : Subregion Disable. For regions of 256 bytes or larger, each bit
+// of this field controls whether one of the eight equal
+// subregions is enabled.
+#define M0PLUS_MPU_RASR_SRD_RESET _u(0x00)
+#define M0PLUS_MPU_RASR_SRD_BITS _u(0x0000ff00)
+#define M0PLUS_MPU_RASR_SRD_MSB _u(15)
+#define M0PLUS_MPU_RASR_SRD_LSB _u(8)
+#define M0PLUS_MPU_RASR_SRD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RASR_SIZE
+// Description : Indicates the region size. Region size in bytes = 2^(SIZE+1).
+// The minimum permitted value is 7 (b00111) = 256Bytes
+#define M0PLUS_MPU_RASR_SIZE_RESET _u(0x00)
+#define M0PLUS_MPU_RASR_SIZE_BITS _u(0x0000003e)
+#define M0PLUS_MPU_RASR_SIZE_MSB _u(5)
+#define M0PLUS_MPU_RASR_SIZE_LSB _u(1)
+#define M0PLUS_MPU_RASR_SIZE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : M0PLUS_MPU_RASR_ENABLE
+// Description : Enables the region.
+#define M0PLUS_MPU_RASR_ENABLE_RESET _u(0x0)
+#define M0PLUS_MPU_RASR_ENABLE_BITS _u(0x00000001)
+#define M0PLUS_MPU_RASR_ENABLE_MSB _u(0)
+#define M0PLUS_MPU_RASR_ENABLE_LSB _u(0)
+#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_M0PLUS_DEFINED
diff --git a/arkanoid/pico/hardware/regs/pads_bank0.h b/arkanoid/pico/hardware/regs/pads_bank0.h
new file mode 100644
index 0000000..06102ac
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/pads_bank0.h
@@ -0,0 +1,2300 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PADS_BANK0
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PADS_BANK0_DEFINED
+#define HARDWARE_REGS_PADS_BANK0_DEFINED
+// =============================================================================
+// Register : PADS_BANK0_VOLTAGE_SELECT
+// Description : Voltage select. Per bank control
+// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
+// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
+#define PADS_BANK0_VOLTAGE_SELECT_OFFSET _u(0x00000000)
+#define PADS_BANK0_VOLTAGE_SELECT_BITS _u(0x00000001)
+#define PADS_BANK0_VOLTAGE_SELECT_RESET _u(0x00000000)
+#define PADS_BANK0_VOLTAGE_SELECT_MSB _u(0)
+#define PADS_BANK0_VOLTAGE_SELECT_LSB _u(0)
+#define PADS_BANK0_VOLTAGE_SELECT_ACCESS "RW"
+#define PADS_BANK0_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
+#define PADS_BANK0_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
+// =============================================================================
+// Register : PADS_BANK0_GPIO0
+// Description : Pad control register
+#define PADS_BANK0_GPIO0_OFFSET _u(0x00000004)
+#define PADS_BANK0_GPIO0_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO0_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO0_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO0_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO0_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO0_OD_MSB _u(7)
+#define PADS_BANK0_GPIO0_OD_LSB _u(7)
+#define PADS_BANK0_GPIO0_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO0_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO0_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO0_IE_MSB _u(6)
+#define PADS_BANK0_GPIO0_IE_LSB _u(6)
+#define PADS_BANK0_GPIO0_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO0_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO0_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO0_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO0_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO0_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO0_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO0_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO0_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO0_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO0_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO0_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO0_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO0_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO0_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO0_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO0_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO0_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO0_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO0_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO0_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO0_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO0_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO0_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO0_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO0_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO0_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO0_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO0_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO0_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO1
+// Description : Pad control register
+#define PADS_BANK0_GPIO1_OFFSET _u(0x00000008)
+#define PADS_BANK0_GPIO1_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO1_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO1_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO1_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO1_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO1_OD_MSB _u(7)
+#define PADS_BANK0_GPIO1_OD_LSB _u(7)
+#define PADS_BANK0_GPIO1_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO1_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO1_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO1_IE_MSB _u(6)
+#define PADS_BANK0_GPIO1_IE_LSB _u(6)
+#define PADS_BANK0_GPIO1_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO1_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO1_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO1_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO1_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO1_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO1_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO1_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO1_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO1_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO1_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO1_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO1_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO1_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO1_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO1_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO1_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO1_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO1_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO1_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO1_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO1_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO1_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO1_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO1_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO1_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO1_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO1_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO1_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO1_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO2
+// Description : Pad control register
+#define PADS_BANK0_GPIO2_OFFSET _u(0x0000000c)
+#define PADS_BANK0_GPIO2_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO2_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO2_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO2_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO2_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO2_OD_MSB _u(7)
+#define PADS_BANK0_GPIO2_OD_LSB _u(7)
+#define PADS_BANK0_GPIO2_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO2_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO2_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO2_IE_MSB _u(6)
+#define PADS_BANK0_GPIO2_IE_LSB _u(6)
+#define PADS_BANK0_GPIO2_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO2_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO2_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO2_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO2_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO2_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO2_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO2_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO2_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO2_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO2_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO2_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO2_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO2_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO2_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO2_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO2_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO2_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO2_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO2_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO2_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO2_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO2_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO2_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO2_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO2_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO2_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO2_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO2_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO2_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO3
+// Description : Pad control register
+#define PADS_BANK0_GPIO3_OFFSET _u(0x00000010)
+#define PADS_BANK0_GPIO3_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO3_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO3_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO3_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO3_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO3_OD_MSB _u(7)
+#define PADS_BANK0_GPIO3_OD_LSB _u(7)
+#define PADS_BANK0_GPIO3_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO3_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO3_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO3_IE_MSB _u(6)
+#define PADS_BANK0_GPIO3_IE_LSB _u(6)
+#define PADS_BANK0_GPIO3_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO3_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO3_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO3_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO3_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO3_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO3_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO3_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO3_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO3_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO3_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO3_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO3_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO3_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO3_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO3_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO3_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO3_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO3_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO3_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO3_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO3_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO3_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO3_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO3_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO3_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO3_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO3_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO3_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO3_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO4
+// Description : Pad control register
+#define PADS_BANK0_GPIO4_OFFSET _u(0x00000014)
+#define PADS_BANK0_GPIO4_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO4_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO4_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO4_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO4_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO4_OD_MSB _u(7)
+#define PADS_BANK0_GPIO4_OD_LSB _u(7)
+#define PADS_BANK0_GPIO4_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO4_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO4_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO4_IE_MSB _u(6)
+#define PADS_BANK0_GPIO4_IE_LSB _u(6)
+#define PADS_BANK0_GPIO4_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO4_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO4_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO4_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO4_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO4_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO4_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO4_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO4_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO4_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO4_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO4_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO4_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO4_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO4_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO4_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO4_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO4_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO4_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO4_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO4_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO4_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO4_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO4_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO4_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO4_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO4_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO4_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO4_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO4_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO5
+// Description : Pad control register
+#define PADS_BANK0_GPIO5_OFFSET _u(0x00000018)
+#define PADS_BANK0_GPIO5_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO5_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO5_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO5_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO5_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO5_OD_MSB _u(7)
+#define PADS_BANK0_GPIO5_OD_LSB _u(7)
+#define PADS_BANK0_GPIO5_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO5_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO5_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO5_IE_MSB _u(6)
+#define PADS_BANK0_GPIO5_IE_LSB _u(6)
+#define PADS_BANK0_GPIO5_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO5_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO5_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO5_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO5_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO5_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO5_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO5_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO5_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO5_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO5_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO5_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO5_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO5_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO5_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO5_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO5_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO5_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO5_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO5_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO5_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO5_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO5_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO5_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO5_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO5_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO5_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO5_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO5_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO5_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO6
+// Description : Pad control register
+#define PADS_BANK0_GPIO6_OFFSET _u(0x0000001c)
+#define PADS_BANK0_GPIO6_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO6_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO6_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO6_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO6_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO6_OD_MSB _u(7)
+#define PADS_BANK0_GPIO6_OD_LSB _u(7)
+#define PADS_BANK0_GPIO6_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO6_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO6_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO6_IE_MSB _u(6)
+#define PADS_BANK0_GPIO6_IE_LSB _u(6)
+#define PADS_BANK0_GPIO6_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO6_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO6_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO6_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO6_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO6_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO6_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO6_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO6_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO6_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO6_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO6_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO6_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO6_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO6_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO6_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO6_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO6_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO6_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO6_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO6_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO6_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO6_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO6_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO6_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO6_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO6_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO6_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO6_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO6_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO7
+// Description : Pad control register
+#define PADS_BANK0_GPIO7_OFFSET _u(0x00000020)
+#define PADS_BANK0_GPIO7_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO7_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO7_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO7_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO7_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO7_OD_MSB _u(7)
+#define PADS_BANK0_GPIO7_OD_LSB _u(7)
+#define PADS_BANK0_GPIO7_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO7_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO7_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO7_IE_MSB _u(6)
+#define PADS_BANK0_GPIO7_IE_LSB _u(6)
+#define PADS_BANK0_GPIO7_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO7_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO7_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO7_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO7_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO7_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO7_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO7_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO7_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO7_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO7_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO7_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO7_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO7_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO7_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO7_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO7_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO7_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO7_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO7_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO7_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO7_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO7_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO7_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO7_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO7_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO7_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO7_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO7_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO7_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO8
+// Description : Pad control register
+#define PADS_BANK0_GPIO8_OFFSET _u(0x00000024)
+#define PADS_BANK0_GPIO8_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO8_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO8_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO8_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO8_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO8_OD_MSB _u(7)
+#define PADS_BANK0_GPIO8_OD_LSB _u(7)
+#define PADS_BANK0_GPIO8_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO8_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO8_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO8_IE_MSB _u(6)
+#define PADS_BANK0_GPIO8_IE_LSB _u(6)
+#define PADS_BANK0_GPIO8_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO8_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO8_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO8_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO8_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO8_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO8_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO8_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO8_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO8_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO8_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO8_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO8_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO8_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO8_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO8_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO8_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO8_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO8_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO8_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO8_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO8_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO8_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO8_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO8_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO8_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO8_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO8_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO8_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO8_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO9
+// Description : Pad control register
+#define PADS_BANK0_GPIO9_OFFSET _u(0x00000028)
+#define PADS_BANK0_GPIO9_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO9_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO9_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO9_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO9_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO9_OD_MSB _u(7)
+#define PADS_BANK0_GPIO9_OD_LSB _u(7)
+#define PADS_BANK0_GPIO9_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO9_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO9_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO9_IE_MSB _u(6)
+#define PADS_BANK0_GPIO9_IE_LSB _u(6)
+#define PADS_BANK0_GPIO9_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO9_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO9_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO9_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO9_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO9_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO9_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO9_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO9_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO9_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO9_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO9_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO9_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO9_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO9_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO9_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO9_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO9_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO9_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO9_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO9_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO9_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO9_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO9_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO9_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO9_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO9_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO9_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO9_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO9_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO10
+// Description : Pad control register
+#define PADS_BANK0_GPIO10_OFFSET _u(0x0000002c)
+#define PADS_BANK0_GPIO10_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO10_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO10_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO10_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO10_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO10_OD_MSB _u(7)
+#define PADS_BANK0_GPIO10_OD_LSB _u(7)
+#define PADS_BANK0_GPIO10_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO10_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO10_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO10_IE_MSB _u(6)
+#define PADS_BANK0_GPIO10_IE_LSB _u(6)
+#define PADS_BANK0_GPIO10_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO10_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO10_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO10_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO10_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO10_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO10_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO10_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO10_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO10_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO10_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO10_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO10_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO10_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO10_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO10_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO10_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO10_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO10_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO10_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO10_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO10_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO10_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO10_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO10_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO10_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO10_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO10_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO10_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO10_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO11
+// Description : Pad control register
+#define PADS_BANK0_GPIO11_OFFSET _u(0x00000030)
+#define PADS_BANK0_GPIO11_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO11_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO11_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO11_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO11_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO11_OD_MSB _u(7)
+#define PADS_BANK0_GPIO11_OD_LSB _u(7)
+#define PADS_BANK0_GPIO11_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO11_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO11_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO11_IE_MSB _u(6)
+#define PADS_BANK0_GPIO11_IE_LSB _u(6)
+#define PADS_BANK0_GPIO11_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO11_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO11_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO11_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO11_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO11_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO11_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO11_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO11_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO11_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO11_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO11_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO11_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO11_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO11_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO11_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO11_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO11_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO11_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO11_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO11_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO11_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO11_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO11_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO11_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO11_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO11_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO11_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO11_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO11_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO12
+// Description : Pad control register
+#define PADS_BANK0_GPIO12_OFFSET _u(0x00000034)
+#define PADS_BANK0_GPIO12_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO12_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO12_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO12_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO12_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO12_OD_MSB _u(7)
+#define PADS_BANK0_GPIO12_OD_LSB _u(7)
+#define PADS_BANK0_GPIO12_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO12_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO12_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO12_IE_MSB _u(6)
+#define PADS_BANK0_GPIO12_IE_LSB _u(6)
+#define PADS_BANK0_GPIO12_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO12_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO12_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO12_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO12_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO12_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO12_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO12_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO12_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO12_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO12_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO12_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO12_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO12_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO12_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO12_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO12_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO12_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO12_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO12_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO12_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO12_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO12_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO12_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO12_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO12_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO12_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO12_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO12_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO12_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO13
+// Description : Pad control register
+#define PADS_BANK0_GPIO13_OFFSET _u(0x00000038)
+#define PADS_BANK0_GPIO13_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO13_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO13_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO13_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO13_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO13_OD_MSB _u(7)
+#define PADS_BANK0_GPIO13_OD_LSB _u(7)
+#define PADS_BANK0_GPIO13_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO13_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO13_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO13_IE_MSB _u(6)
+#define PADS_BANK0_GPIO13_IE_LSB _u(6)
+#define PADS_BANK0_GPIO13_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO13_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO13_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO13_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO13_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO13_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO13_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO13_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO13_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO13_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO13_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO13_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO13_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO13_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO13_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO13_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO13_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO13_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO13_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO13_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO13_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO13_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO13_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO13_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO13_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO13_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO13_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO13_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO13_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO13_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO14
+// Description : Pad control register
+#define PADS_BANK0_GPIO14_OFFSET _u(0x0000003c)
+#define PADS_BANK0_GPIO14_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO14_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO14_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO14_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO14_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO14_OD_MSB _u(7)
+#define PADS_BANK0_GPIO14_OD_LSB _u(7)
+#define PADS_BANK0_GPIO14_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO14_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO14_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO14_IE_MSB _u(6)
+#define PADS_BANK0_GPIO14_IE_LSB _u(6)
+#define PADS_BANK0_GPIO14_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO14_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO14_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO14_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO14_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO14_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO14_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO14_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO14_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO14_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO14_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO14_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO14_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO14_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO14_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO14_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO14_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO14_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO14_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO14_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO14_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO14_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO14_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO14_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO14_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO14_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO14_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO14_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO14_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO14_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO15
+// Description : Pad control register
+#define PADS_BANK0_GPIO15_OFFSET _u(0x00000040)
+#define PADS_BANK0_GPIO15_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO15_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO15_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO15_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO15_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO15_OD_MSB _u(7)
+#define PADS_BANK0_GPIO15_OD_LSB _u(7)
+#define PADS_BANK0_GPIO15_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO15_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO15_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO15_IE_MSB _u(6)
+#define PADS_BANK0_GPIO15_IE_LSB _u(6)
+#define PADS_BANK0_GPIO15_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO15_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO15_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO15_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO15_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO15_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO15_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO15_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO15_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO15_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO15_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO15_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO15_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO15_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO15_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO15_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO15_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO15_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO15_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO15_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO15_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO15_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO15_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO15_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO15_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO15_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO15_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO15_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO15_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO15_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO16
+// Description : Pad control register
+#define PADS_BANK0_GPIO16_OFFSET _u(0x00000044)
+#define PADS_BANK0_GPIO16_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO16_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO16_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO16_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO16_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO16_OD_MSB _u(7)
+#define PADS_BANK0_GPIO16_OD_LSB _u(7)
+#define PADS_BANK0_GPIO16_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO16_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO16_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO16_IE_MSB _u(6)
+#define PADS_BANK0_GPIO16_IE_LSB _u(6)
+#define PADS_BANK0_GPIO16_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO16_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO16_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO16_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO16_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO16_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO16_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO16_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO16_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO16_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO16_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO16_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO16_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO16_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO16_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO16_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO16_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO16_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO16_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO16_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO16_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO16_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO16_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO16_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO16_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO16_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO16_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO16_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO16_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO16_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO17
+// Description : Pad control register
+#define PADS_BANK0_GPIO17_OFFSET _u(0x00000048)
+#define PADS_BANK0_GPIO17_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO17_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO17_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO17_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO17_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO17_OD_MSB _u(7)
+#define PADS_BANK0_GPIO17_OD_LSB _u(7)
+#define PADS_BANK0_GPIO17_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO17_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO17_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO17_IE_MSB _u(6)
+#define PADS_BANK0_GPIO17_IE_LSB _u(6)
+#define PADS_BANK0_GPIO17_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO17_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO17_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO17_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO17_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO17_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO17_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO17_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO17_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO17_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO17_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO17_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO17_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO17_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO17_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO17_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO17_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO17_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO17_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO17_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO17_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO17_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO17_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO17_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO17_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO17_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO17_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO17_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO17_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO17_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO18
+// Description : Pad control register
+#define PADS_BANK0_GPIO18_OFFSET _u(0x0000004c)
+#define PADS_BANK0_GPIO18_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO18_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO18_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO18_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO18_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO18_OD_MSB _u(7)
+#define PADS_BANK0_GPIO18_OD_LSB _u(7)
+#define PADS_BANK0_GPIO18_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO18_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO18_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO18_IE_MSB _u(6)
+#define PADS_BANK0_GPIO18_IE_LSB _u(6)
+#define PADS_BANK0_GPIO18_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO18_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO18_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO18_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO18_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO18_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO18_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO18_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO18_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO18_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO18_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO18_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO18_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO18_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO18_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO18_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO18_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO18_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO18_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO18_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO18_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO18_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO18_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO18_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO18_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO18_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO18_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO18_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO18_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO18_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO19
+// Description : Pad control register
+#define PADS_BANK0_GPIO19_OFFSET _u(0x00000050)
+#define PADS_BANK0_GPIO19_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO19_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO19_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO19_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO19_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO19_OD_MSB _u(7)
+#define PADS_BANK0_GPIO19_OD_LSB _u(7)
+#define PADS_BANK0_GPIO19_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO19_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO19_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO19_IE_MSB _u(6)
+#define PADS_BANK0_GPIO19_IE_LSB _u(6)
+#define PADS_BANK0_GPIO19_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO19_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO19_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO19_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO19_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO19_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO19_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO19_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO19_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO19_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO19_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO19_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO19_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO19_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO19_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO19_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO19_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO19_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO19_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO19_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO19_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO19_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO19_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO19_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO19_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO19_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO19_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO19_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO19_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO19_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO20
+// Description : Pad control register
+#define PADS_BANK0_GPIO20_OFFSET _u(0x00000054)
+#define PADS_BANK0_GPIO20_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO20_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO20_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO20_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO20_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO20_OD_MSB _u(7)
+#define PADS_BANK0_GPIO20_OD_LSB _u(7)
+#define PADS_BANK0_GPIO20_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO20_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO20_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO20_IE_MSB _u(6)
+#define PADS_BANK0_GPIO20_IE_LSB _u(6)
+#define PADS_BANK0_GPIO20_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO20_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO20_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO20_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO20_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO20_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO20_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO20_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO20_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO20_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO20_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO20_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO20_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO20_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO20_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO20_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO20_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO20_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO20_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO20_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO20_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO20_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO20_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO20_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO20_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO20_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO20_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO20_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO20_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO20_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO21
+// Description : Pad control register
+#define PADS_BANK0_GPIO21_OFFSET _u(0x00000058)
+#define PADS_BANK0_GPIO21_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO21_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO21_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO21_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO21_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO21_OD_MSB _u(7)
+#define PADS_BANK0_GPIO21_OD_LSB _u(7)
+#define PADS_BANK0_GPIO21_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO21_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO21_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO21_IE_MSB _u(6)
+#define PADS_BANK0_GPIO21_IE_LSB _u(6)
+#define PADS_BANK0_GPIO21_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO21_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO21_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO21_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO21_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO21_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO21_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO21_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO21_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO21_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO21_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO21_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO21_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO21_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO21_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO21_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO21_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO21_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO21_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO21_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO21_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO21_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO21_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO21_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO21_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO21_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO21_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO21_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO21_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO21_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO22
+// Description : Pad control register
+#define PADS_BANK0_GPIO22_OFFSET _u(0x0000005c)
+#define PADS_BANK0_GPIO22_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO22_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO22_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO22_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO22_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO22_OD_MSB _u(7)
+#define PADS_BANK0_GPIO22_OD_LSB _u(7)
+#define PADS_BANK0_GPIO22_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO22_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO22_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO22_IE_MSB _u(6)
+#define PADS_BANK0_GPIO22_IE_LSB _u(6)
+#define PADS_BANK0_GPIO22_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO22_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO22_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO22_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO22_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO22_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO22_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO22_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO22_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO22_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO22_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO22_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO22_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO22_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO22_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO22_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO22_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO22_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO22_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO22_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO22_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO22_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO22_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO22_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO22_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO22_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO22_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO22_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO22_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO22_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO23
+// Description : Pad control register
+#define PADS_BANK0_GPIO23_OFFSET _u(0x00000060)
+#define PADS_BANK0_GPIO23_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO23_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO23_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO23_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO23_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO23_OD_MSB _u(7)
+#define PADS_BANK0_GPIO23_OD_LSB _u(7)
+#define PADS_BANK0_GPIO23_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO23_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO23_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO23_IE_MSB _u(6)
+#define PADS_BANK0_GPIO23_IE_LSB _u(6)
+#define PADS_BANK0_GPIO23_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO23_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO23_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO23_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO23_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO23_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO23_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO23_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO23_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO23_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO23_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO23_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO23_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO23_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO23_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO23_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO23_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO23_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO23_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO23_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO23_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO23_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO23_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO23_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO23_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO23_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO23_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO23_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO23_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO23_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO24
+// Description : Pad control register
+#define PADS_BANK0_GPIO24_OFFSET _u(0x00000064)
+#define PADS_BANK0_GPIO24_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO24_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO24_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO24_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO24_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO24_OD_MSB _u(7)
+#define PADS_BANK0_GPIO24_OD_LSB _u(7)
+#define PADS_BANK0_GPIO24_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO24_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO24_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO24_IE_MSB _u(6)
+#define PADS_BANK0_GPIO24_IE_LSB _u(6)
+#define PADS_BANK0_GPIO24_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO24_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO24_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO24_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO24_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO24_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO24_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO24_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO24_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO24_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO24_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO24_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO24_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO24_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO24_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO24_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO24_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO24_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO24_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO24_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO24_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO24_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO24_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO24_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO24_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO24_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO24_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO24_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO24_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO24_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO25
+// Description : Pad control register
+#define PADS_BANK0_GPIO25_OFFSET _u(0x00000068)
+#define PADS_BANK0_GPIO25_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO25_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO25_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO25_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO25_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO25_OD_MSB _u(7)
+#define PADS_BANK0_GPIO25_OD_LSB _u(7)
+#define PADS_BANK0_GPIO25_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO25_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO25_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO25_IE_MSB _u(6)
+#define PADS_BANK0_GPIO25_IE_LSB _u(6)
+#define PADS_BANK0_GPIO25_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO25_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO25_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO25_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO25_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO25_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO25_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO25_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO25_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO25_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO25_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO25_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO25_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO25_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO25_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO25_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO25_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO25_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO25_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO25_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO25_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO25_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO25_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO25_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO25_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO25_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO25_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO25_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO25_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO25_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO26
+// Description : Pad control register
+#define PADS_BANK0_GPIO26_OFFSET _u(0x0000006c)
+#define PADS_BANK0_GPIO26_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO26_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO26_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO26_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO26_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO26_OD_MSB _u(7)
+#define PADS_BANK0_GPIO26_OD_LSB _u(7)
+#define PADS_BANK0_GPIO26_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO26_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO26_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO26_IE_MSB _u(6)
+#define PADS_BANK0_GPIO26_IE_LSB _u(6)
+#define PADS_BANK0_GPIO26_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO26_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO26_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO26_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO26_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO26_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO26_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO26_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO26_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO26_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO26_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO26_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO26_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO26_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO26_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO26_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO26_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO26_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO26_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO26_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO26_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO26_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO26_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO26_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO26_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO26_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO26_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO26_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO26_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO26_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO27
+// Description : Pad control register
+#define PADS_BANK0_GPIO27_OFFSET _u(0x00000070)
+#define PADS_BANK0_GPIO27_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO27_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO27_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO27_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO27_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO27_OD_MSB _u(7)
+#define PADS_BANK0_GPIO27_OD_LSB _u(7)
+#define PADS_BANK0_GPIO27_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO27_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO27_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO27_IE_MSB _u(6)
+#define PADS_BANK0_GPIO27_IE_LSB _u(6)
+#define PADS_BANK0_GPIO27_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO27_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO27_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO27_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO27_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO27_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO27_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO27_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO27_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO27_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO27_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO27_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO27_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO27_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO27_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO27_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO27_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO27_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO27_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO27_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO27_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO27_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO27_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO27_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO27_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO27_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO27_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO27_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO27_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO27_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO28
+// Description : Pad control register
+#define PADS_BANK0_GPIO28_OFFSET _u(0x00000074)
+#define PADS_BANK0_GPIO28_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO28_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO28_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO28_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO28_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO28_OD_MSB _u(7)
+#define PADS_BANK0_GPIO28_OD_LSB _u(7)
+#define PADS_BANK0_GPIO28_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO28_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO28_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO28_IE_MSB _u(6)
+#define PADS_BANK0_GPIO28_IE_LSB _u(6)
+#define PADS_BANK0_GPIO28_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO28_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO28_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO28_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO28_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO28_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO28_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO28_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO28_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO28_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO28_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO28_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO28_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO28_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO28_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO28_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO28_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO28_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO28_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO28_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO28_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO28_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO28_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO28_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO28_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO28_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO28_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO28_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO28_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO28_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_GPIO29
+// Description : Pad control register
+#define PADS_BANK0_GPIO29_OFFSET _u(0x00000078)
+#define PADS_BANK0_GPIO29_BITS _u(0x000000ff)
+#define PADS_BANK0_GPIO29_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO29_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_GPIO29_OD_RESET _u(0x0)
+#define PADS_BANK0_GPIO29_OD_BITS _u(0x00000080)
+#define PADS_BANK0_GPIO29_OD_MSB _u(7)
+#define PADS_BANK0_GPIO29_OD_LSB _u(7)
+#define PADS_BANK0_GPIO29_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO29_IE
+// Description : Input enable
+#define PADS_BANK0_GPIO29_IE_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_IE_BITS _u(0x00000040)
+#define PADS_BANK0_GPIO29_IE_MSB _u(6)
+#define PADS_BANK0_GPIO29_IE_LSB _u(6)
+#define PADS_BANK0_GPIO29_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO29_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_GPIO29_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_GPIO29_DRIVE_MSB _u(5)
+#define PADS_BANK0_GPIO29_DRIVE_LSB _u(4)
+#define PADS_BANK0_GPIO29_DRIVE_ACCESS "RW"
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_GPIO29_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO29_PUE
+// Description : Pull up enable
+#define PADS_BANK0_GPIO29_PUE_RESET _u(0x0)
+#define PADS_BANK0_GPIO29_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_GPIO29_PUE_MSB _u(3)
+#define PADS_BANK0_GPIO29_PUE_LSB _u(3)
+#define PADS_BANK0_GPIO29_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO29_PDE
+// Description : Pull down enable
+#define PADS_BANK0_GPIO29_PDE_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_GPIO29_PDE_MSB _u(2)
+#define PADS_BANK0_GPIO29_PDE_LSB _u(2)
+#define PADS_BANK0_GPIO29_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO29_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_GPIO29_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_GPIO29_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_GPIO29_SCHMITT_MSB _u(1)
+#define PADS_BANK0_GPIO29_SCHMITT_LSB _u(1)
+#define PADS_BANK0_GPIO29_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_GPIO29_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_GPIO29_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_GPIO29_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_GPIO29_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_GPIO29_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_GPIO29_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_SWCLK
+// Description : Pad control register
+#define PADS_BANK0_SWCLK_OFFSET _u(0x0000007c)
+#define PADS_BANK0_SWCLK_BITS _u(0x000000ff)
+#define PADS_BANK0_SWCLK_RESET _u(0x000000da)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWCLK_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_SWCLK_OD_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_OD_BITS _u(0x00000080)
+#define PADS_BANK0_SWCLK_OD_MSB _u(7)
+#define PADS_BANK0_SWCLK_OD_LSB _u(7)
+#define PADS_BANK0_SWCLK_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWCLK_IE
+// Description : Input enable
+#define PADS_BANK0_SWCLK_IE_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_IE_BITS _u(0x00000040)
+#define PADS_BANK0_SWCLK_IE_MSB _u(6)
+#define PADS_BANK0_SWCLK_IE_LSB _u(6)
+#define PADS_BANK0_SWCLK_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWCLK_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_SWCLK_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_SWCLK_DRIVE_MSB _u(5)
+#define PADS_BANK0_SWCLK_DRIVE_LSB _u(4)
+#define PADS_BANK0_SWCLK_DRIVE_ACCESS "RW"
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_SWCLK_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWCLK_PUE
+// Description : Pull up enable
+#define PADS_BANK0_SWCLK_PUE_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_SWCLK_PUE_MSB _u(3)
+#define PADS_BANK0_SWCLK_PUE_LSB _u(3)
+#define PADS_BANK0_SWCLK_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWCLK_PDE
+// Description : Pull down enable
+#define PADS_BANK0_SWCLK_PDE_RESET _u(0x0)
+#define PADS_BANK0_SWCLK_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_SWCLK_PDE_MSB _u(2)
+#define PADS_BANK0_SWCLK_PDE_LSB _u(2)
+#define PADS_BANK0_SWCLK_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWCLK_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_SWCLK_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_SWCLK_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_SWCLK_SCHMITT_MSB _u(1)
+#define PADS_BANK0_SWCLK_SCHMITT_LSB _u(1)
+#define PADS_BANK0_SWCLK_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWCLK_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_SWCLK_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_SWCLK_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_SWCLK_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_SWCLK_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_SWCLK_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_BANK0_SWD
+// Description : Pad control register
+#define PADS_BANK0_SWD_OFFSET _u(0x00000080)
+#define PADS_BANK0_SWD_BITS _u(0x000000ff)
+#define PADS_BANK0_SWD_RESET _u(0x0000005a)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWD_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_BANK0_SWD_OD_RESET _u(0x0)
+#define PADS_BANK0_SWD_OD_BITS _u(0x00000080)
+#define PADS_BANK0_SWD_OD_MSB _u(7)
+#define PADS_BANK0_SWD_OD_LSB _u(7)
+#define PADS_BANK0_SWD_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWD_IE
+// Description : Input enable
+#define PADS_BANK0_SWD_IE_RESET _u(0x1)
+#define PADS_BANK0_SWD_IE_BITS _u(0x00000040)
+#define PADS_BANK0_SWD_IE_MSB _u(6)
+#define PADS_BANK0_SWD_IE_LSB _u(6)
+#define PADS_BANK0_SWD_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWD_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_BANK0_SWD_DRIVE_RESET _u(0x1)
+#define PADS_BANK0_SWD_DRIVE_BITS _u(0x00000030)
+#define PADS_BANK0_SWD_DRIVE_MSB _u(5)
+#define PADS_BANK0_SWD_DRIVE_LSB _u(4)
+#define PADS_BANK0_SWD_DRIVE_ACCESS "RW"
+#define PADS_BANK0_SWD_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_BANK0_SWD_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_BANK0_SWD_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_BANK0_SWD_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWD_PUE
+// Description : Pull up enable
+#define PADS_BANK0_SWD_PUE_RESET _u(0x1)
+#define PADS_BANK0_SWD_PUE_BITS _u(0x00000008)
+#define PADS_BANK0_SWD_PUE_MSB _u(3)
+#define PADS_BANK0_SWD_PUE_LSB _u(3)
+#define PADS_BANK0_SWD_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWD_PDE
+// Description : Pull down enable
+#define PADS_BANK0_SWD_PDE_RESET _u(0x0)
+#define PADS_BANK0_SWD_PDE_BITS _u(0x00000004)
+#define PADS_BANK0_SWD_PDE_MSB _u(2)
+#define PADS_BANK0_SWD_PDE_LSB _u(2)
+#define PADS_BANK0_SWD_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWD_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_BANK0_SWD_SCHMITT_RESET _u(0x1)
+#define PADS_BANK0_SWD_SCHMITT_BITS _u(0x00000002)
+#define PADS_BANK0_SWD_SCHMITT_MSB _u(1)
+#define PADS_BANK0_SWD_SCHMITT_LSB _u(1)
+#define PADS_BANK0_SWD_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_BANK0_SWD_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_BANK0_SWD_SLEWFAST_RESET _u(0x0)
+#define PADS_BANK0_SWD_SLEWFAST_BITS _u(0x00000001)
+#define PADS_BANK0_SWD_SLEWFAST_MSB _u(0)
+#define PADS_BANK0_SWD_SLEWFAST_LSB _u(0)
+#define PADS_BANK0_SWD_SLEWFAST_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_PADS_BANK0_DEFINED
diff --git a/arkanoid/pico/hardware/regs/pads_qspi.h b/arkanoid/pico/hardware/regs/pads_qspi.h
new file mode 100644
index 0000000..b3a09e9
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/pads_qspi.h
@@ -0,0 +1,454 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PADS_QSPI
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED
+#define HARDWARE_REGS_PADS_QSPI_DEFINED
+// =============================================================================
+// Register : PADS_QSPI_VOLTAGE_SELECT
+// Description : Voltage select. Per bank control
+// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
+// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
+#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
+#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
+#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
+#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
+// =============================================================================
+// Register : PADS_QSPI_GPIO_QSPI_SCLK
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_QSPI_GPIO_QSPI_SD0
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_QSPI_GPIO_QSPI_SD1
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
+#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_QSPI_GPIO_QSPI_SD2
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
+#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_QSPI_GPIO_QSPI_SD3
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
+#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register : PADS_QSPI_GPIO_QSPI_SS
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
+#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000005a)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SS_OD
+// Description : Output disable. Has priority over output enable from
+// peripherals
+#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SS_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
+// Description : Drive strength.
+// 0x0 -> 2mA
+// 0x1 -> 4mA
+// 0x2 -> 8mA
+// 0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_PADS_QSPI_DEFINED
diff --git a/arkanoid/pico/hardware/regs/pio.h b/arkanoid/pico/hardware/regs/pio.h
new file mode 100644
index 0000000..b231882
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/pio.h
@@ -0,0 +1,2764 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PIO
+// Version : 1
+// Bus type : ahbl
+// Description : Programmable IO block
+// =============================================================================
+#ifndef HARDWARE_REGS_PIO_DEFINED
+#define HARDWARE_REGS_PIO_DEFINED
+// =============================================================================
+// Register : PIO_CTRL
+// Description : PIO control register
+#define PIO_CTRL_OFFSET _u(0x00000000)
+#define PIO_CTRL_BITS _u(0x00000fff)
+#define PIO_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_CTRL_CLKDIV_RESTART
+// Description : Restart a state machine's clock divider from an initial phase
+// of 0. Clock dividers are free-running, so once started, their
+// output (including fractional jitter) is completely determined
+// by the integer/fractional divisor configured in SMx_CLKDIV.
+// This means that, if multiple clock dividers with the same
+// divisor are restarted simultaneously, by writing multiple 1
+// bits to this field, the execution clocks of those state
+// machines will run in precise lockstep.
+//
+// Note that setting/clearing SM_ENABLE does not stop the clock
+// divider from running, so once multiple state machines' clocks
+// are synchronised, it is safe to disable/reenable a state
+// machine, whilst keeping the clock dividers in sync.
+//
+// Note also that CLKDIV_RESTART can be written to whilst the
+// state machine is running, and this is useful to resynchronise
+// clock dividers after the divisors (SMx_CLKDIV) have been
+// changed on-the-fly.
+#define PIO_CTRL_CLKDIV_RESTART_RESET _u(0x0)
+#define PIO_CTRL_CLKDIV_RESTART_BITS _u(0x00000f00)
+#define PIO_CTRL_CLKDIV_RESTART_MSB _u(11)
+#define PIO_CTRL_CLKDIV_RESTART_LSB _u(8)
+#define PIO_CTRL_CLKDIV_RESTART_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PIO_CTRL_SM_RESTART
+// Description : Write 1 to instantly clear internal SM state which may be
+// otherwise difficult to access and will affect future execution.
+//
+// Specifically, the following are cleared: input and output shift
+// counters; the contents of the input shift register; the delay
+// counter; the waiting-on-IRQ state; any stalled instruction
+// written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left
+// asserted due to OUT_STICKY.
+#define PIO_CTRL_SM_RESTART_RESET _u(0x0)
+#define PIO_CTRL_SM_RESTART_BITS _u(0x000000f0)
+#define PIO_CTRL_SM_RESTART_MSB _u(7)
+#define PIO_CTRL_SM_RESTART_LSB _u(4)
+#define PIO_CTRL_SM_RESTART_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PIO_CTRL_SM_ENABLE
+// Description : Enable/disable each of the four state machines by writing 1/0
+// to each of these four bits. When disabled, a state machine will
+// cease executing instructions, except those written directly to
+// SMx_INSTR by the system. Multiple bits can be set/cleared at
+// once to run/halt multiple state machines simultaneously.
+#define PIO_CTRL_SM_ENABLE_RESET _u(0x0)
+#define PIO_CTRL_SM_ENABLE_BITS _u(0x0000000f)
+#define PIO_CTRL_SM_ENABLE_MSB _u(3)
+#define PIO_CTRL_SM_ENABLE_LSB _u(0)
+#define PIO_CTRL_SM_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register : PIO_FSTAT
+// Description : FIFO status register
+#define PIO_FSTAT_OFFSET _u(0x00000004)
+#define PIO_FSTAT_BITS _u(0x0f0f0f0f)
+#define PIO_FSTAT_RESET _u(0x0f000f00)
+// -----------------------------------------------------------------------------
+// Field : PIO_FSTAT_TXEMPTY
+// Description : State machine TX FIFO is empty
+#define PIO_FSTAT_TXEMPTY_RESET _u(0xf)
+#define PIO_FSTAT_TXEMPTY_BITS _u(0x0f000000)
+#define PIO_FSTAT_TXEMPTY_MSB _u(27)
+#define PIO_FSTAT_TXEMPTY_LSB _u(24)
+#define PIO_FSTAT_TXEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FSTAT_TXFULL
+// Description : State machine TX FIFO is full
+#define PIO_FSTAT_TXFULL_RESET _u(0x0)
+#define PIO_FSTAT_TXFULL_BITS _u(0x000f0000)
+#define PIO_FSTAT_TXFULL_MSB _u(19)
+#define PIO_FSTAT_TXFULL_LSB _u(16)
+#define PIO_FSTAT_TXFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FSTAT_RXEMPTY
+// Description : State machine RX FIFO is empty
+#define PIO_FSTAT_RXEMPTY_RESET _u(0xf)
+#define PIO_FSTAT_RXEMPTY_BITS _u(0x00000f00)
+#define PIO_FSTAT_RXEMPTY_MSB _u(11)
+#define PIO_FSTAT_RXEMPTY_LSB _u(8)
+#define PIO_FSTAT_RXEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FSTAT_RXFULL
+// Description : State machine RX FIFO is full
+#define PIO_FSTAT_RXFULL_RESET _u(0x0)
+#define PIO_FSTAT_RXFULL_BITS _u(0x0000000f)
+#define PIO_FSTAT_RXFULL_MSB _u(3)
+#define PIO_FSTAT_RXFULL_LSB _u(0)
+#define PIO_FSTAT_RXFULL_ACCESS "RO"
+// =============================================================================
+// Register : PIO_FDEBUG
+// Description : FIFO debug register
+#define PIO_FDEBUG_OFFSET _u(0x00000008)
+#define PIO_FDEBUG_BITS _u(0x0f0f0f0f)
+#define PIO_FDEBUG_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_FDEBUG_TXSTALL
+// Description : State machine has stalled on empty TX FIFO during a blocking
+// PULL, or an OUT with autopull enabled. Write 1 to clear.
+#define PIO_FDEBUG_TXSTALL_RESET _u(0x0)
+#define PIO_FDEBUG_TXSTALL_BITS _u(0x0f000000)
+#define PIO_FDEBUG_TXSTALL_MSB _u(27)
+#define PIO_FDEBUG_TXSTALL_LSB _u(24)
+#define PIO_FDEBUG_TXSTALL_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PIO_FDEBUG_TXOVER
+// Description : TX FIFO overflow (i.e. write-on-full by the system) has
+// occurred. Write 1 to clear. Note that write-on-full does not
+// alter the state or contents of the FIFO in any way, but the
+// data that the system attempted to write is dropped, so if this
+// flag is set, your software has quite likely dropped some data
+// on the floor.
+#define PIO_FDEBUG_TXOVER_RESET _u(0x0)
+#define PIO_FDEBUG_TXOVER_BITS _u(0x000f0000)
+#define PIO_FDEBUG_TXOVER_MSB _u(19)
+#define PIO_FDEBUG_TXOVER_LSB _u(16)
+#define PIO_FDEBUG_TXOVER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PIO_FDEBUG_RXUNDER
+// Description : RX FIFO underflow (i.e. read-on-empty by the system) has
+// occurred. Write 1 to clear. Note that read-on-empty does not
+// perturb the state of the FIFO in any way, but the data returned
+// by reading from an empty FIFO is undefined, so this flag
+// generally only becomes set due to some kind of software error.
+#define PIO_FDEBUG_RXUNDER_RESET _u(0x0)
+#define PIO_FDEBUG_RXUNDER_BITS _u(0x00000f00)
+#define PIO_FDEBUG_RXUNDER_MSB _u(11)
+#define PIO_FDEBUG_RXUNDER_LSB _u(8)
+#define PIO_FDEBUG_RXUNDER_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PIO_FDEBUG_RXSTALL
+// Description : State machine has stalled on full RX FIFO during a blocking
+// PUSH, or an IN with autopush enabled. This flag is also set
+// when a nonblocking PUSH to a full FIFO took place, in which
+// case the state machine has dropped data. Write 1 to clear.
+#define PIO_FDEBUG_RXSTALL_RESET _u(0x0)
+#define PIO_FDEBUG_RXSTALL_BITS _u(0x0000000f)
+#define PIO_FDEBUG_RXSTALL_MSB _u(3)
+#define PIO_FDEBUG_RXSTALL_LSB _u(0)
+#define PIO_FDEBUG_RXSTALL_ACCESS "WC"
+// =============================================================================
+// Register : PIO_FLEVEL
+// Description : FIFO levels
+#define PIO_FLEVEL_OFFSET _u(0x0000000c)
+#define PIO_FLEVEL_BITS _u(0xffffffff)
+#define PIO_FLEVEL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_RX3
+// Description : None
+#define PIO_FLEVEL_RX3_RESET _u(0x0)
+#define PIO_FLEVEL_RX3_BITS _u(0xf0000000)
+#define PIO_FLEVEL_RX3_MSB _u(31)
+#define PIO_FLEVEL_RX3_LSB _u(28)
+#define PIO_FLEVEL_RX3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_TX3
+// Description : None
+#define PIO_FLEVEL_TX3_RESET _u(0x0)
+#define PIO_FLEVEL_TX3_BITS _u(0x0f000000)
+#define PIO_FLEVEL_TX3_MSB _u(27)
+#define PIO_FLEVEL_TX3_LSB _u(24)
+#define PIO_FLEVEL_TX3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_RX2
+// Description : None
+#define PIO_FLEVEL_RX2_RESET _u(0x0)
+#define PIO_FLEVEL_RX2_BITS _u(0x00f00000)
+#define PIO_FLEVEL_RX2_MSB _u(23)
+#define PIO_FLEVEL_RX2_LSB _u(20)
+#define PIO_FLEVEL_RX2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_TX2
+// Description : None
+#define PIO_FLEVEL_TX2_RESET _u(0x0)
+#define PIO_FLEVEL_TX2_BITS _u(0x000f0000)
+#define PIO_FLEVEL_TX2_MSB _u(19)
+#define PIO_FLEVEL_TX2_LSB _u(16)
+#define PIO_FLEVEL_TX2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_RX1
+// Description : None
+#define PIO_FLEVEL_RX1_RESET _u(0x0)
+#define PIO_FLEVEL_RX1_BITS _u(0x0000f000)
+#define PIO_FLEVEL_RX1_MSB _u(15)
+#define PIO_FLEVEL_RX1_LSB _u(12)
+#define PIO_FLEVEL_RX1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_TX1
+// Description : None
+#define PIO_FLEVEL_TX1_RESET _u(0x0)
+#define PIO_FLEVEL_TX1_BITS _u(0x00000f00)
+#define PIO_FLEVEL_TX1_MSB _u(11)
+#define PIO_FLEVEL_TX1_LSB _u(8)
+#define PIO_FLEVEL_TX1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_RX0
+// Description : None
+#define PIO_FLEVEL_RX0_RESET _u(0x0)
+#define PIO_FLEVEL_RX0_BITS _u(0x000000f0)
+#define PIO_FLEVEL_RX0_MSB _u(7)
+#define PIO_FLEVEL_RX0_LSB _u(4)
+#define PIO_FLEVEL_RX0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_FLEVEL_TX0
+// Description : None
+#define PIO_FLEVEL_TX0_RESET _u(0x0)
+#define PIO_FLEVEL_TX0_BITS _u(0x0000000f)
+#define PIO_FLEVEL_TX0_MSB _u(3)
+#define PIO_FLEVEL_TX0_LSB _u(0)
+#define PIO_FLEVEL_TX0_ACCESS "RO"
+// =============================================================================
+// Register : PIO_TXF0
+// Description : Direct write access to the TX FIFO for this state machine. Each
+// write pushes one word to the FIFO. Attempting to write to a
+// full FIFO has no effect on the FIFO state or contents, and sets
+// the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF0_OFFSET _u(0x00000010)
+#define PIO_TXF0_BITS _u(0xffffffff)
+#define PIO_TXF0_RESET _u(0x00000000)
+#define PIO_TXF0_MSB _u(31)
+#define PIO_TXF0_LSB _u(0)
+#define PIO_TXF0_ACCESS "WF"
+// =============================================================================
+// Register : PIO_TXF1
+// Description : Direct write access to the TX FIFO for this state machine. Each
+// write pushes one word to the FIFO. Attempting to write to a
+// full FIFO has no effect on the FIFO state or contents, and sets
+// the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF1_OFFSET _u(0x00000014)
+#define PIO_TXF1_BITS _u(0xffffffff)
+#define PIO_TXF1_RESET _u(0x00000000)
+#define PIO_TXF1_MSB _u(31)
+#define PIO_TXF1_LSB _u(0)
+#define PIO_TXF1_ACCESS "WF"
+// =============================================================================
+// Register : PIO_TXF2
+// Description : Direct write access to the TX FIFO for this state machine. Each
+// write pushes one word to the FIFO. Attempting to write to a
+// full FIFO has no effect on the FIFO state or contents, and sets
+// the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF2_OFFSET _u(0x00000018)
+#define PIO_TXF2_BITS _u(0xffffffff)
+#define PIO_TXF2_RESET _u(0x00000000)
+#define PIO_TXF2_MSB _u(31)
+#define PIO_TXF2_LSB _u(0)
+#define PIO_TXF2_ACCESS "WF"
+// =============================================================================
+// Register : PIO_TXF3
+// Description : Direct write access to the TX FIFO for this state machine. Each
+// write pushes one word to the FIFO. Attempting to write to a
+// full FIFO has no effect on the FIFO state or contents, and sets
+// the sticky FDEBUG_TXOVER error flag for this FIFO.
+#define PIO_TXF3_OFFSET _u(0x0000001c)
+#define PIO_TXF3_BITS _u(0xffffffff)
+#define PIO_TXF3_RESET _u(0x00000000)
+#define PIO_TXF3_MSB _u(31)
+#define PIO_TXF3_LSB _u(0)
+#define PIO_TXF3_ACCESS "WF"
+// =============================================================================
+// Register : PIO_RXF0
+// Description : Direct read access to the RX FIFO for this state machine. Each
+// read pops one word from the FIFO. Attempting to read from an
+// empty FIFO has no effect on the FIFO state, and sets the sticky
+// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+// the system on a read from an empty FIFO is undefined.
+#define PIO_RXF0_OFFSET _u(0x00000020)
+#define PIO_RXF0_BITS _u(0xffffffff)
+#define PIO_RXF0_RESET "-"
+#define PIO_RXF0_MSB _u(31)
+#define PIO_RXF0_LSB _u(0)
+#define PIO_RXF0_ACCESS "RF"
+// =============================================================================
+// Register : PIO_RXF1
+// Description : Direct read access to the RX FIFO for this state machine. Each
+// read pops one word from the FIFO. Attempting to read from an
+// empty FIFO has no effect on the FIFO state, and sets the sticky
+// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+// the system on a read from an empty FIFO is undefined.
+#define PIO_RXF1_OFFSET _u(0x00000024)
+#define PIO_RXF1_BITS _u(0xffffffff)
+#define PIO_RXF1_RESET "-"
+#define PIO_RXF1_MSB _u(31)
+#define PIO_RXF1_LSB _u(0)
+#define PIO_RXF1_ACCESS "RF"
+// =============================================================================
+// Register : PIO_RXF2
+// Description : Direct read access to the RX FIFO for this state machine. Each
+// read pops one word from the FIFO. Attempting to read from an
+// empty FIFO has no effect on the FIFO state, and sets the sticky
+// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+// the system on a read from an empty FIFO is undefined.
+#define PIO_RXF2_OFFSET _u(0x00000028)
+#define PIO_RXF2_BITS _u(0xffffffff)
+#define PIO_RXF2_RESET "-"
+#define PIO_RXF2_MSB _u(31)
+#define PIO_RXF2_LSB _u(0)
+#define PIO_RXF2_ACCESS "RF"
+// =============================================================================
+// Register : PIO_RXF3
+// Description : Direct read access to the RX FIFO for this state machine. Each
+// read pops one word from the FIFO. Attempting to read from an
+// empty FIFO has no effect on the FIFO state, and sets the sticky
+// FDEBUG_RXUNDER error flag for this FIFO. The data returned to
+// the system on a read from an empty FIFO is undefined.
+#define PIO_RXF3_OFFSET _u(0x0000002c)
+#define PIO_RXF3_BITS _u(0xffffffff)
+#define PIO_RXF3_RESET "-"
+#define PIO_RXF3_MSB _u(31)
+#define PIO_RXF3_LSB _u(0)
+#define PIO_RXF3_ACCESS "RF"
+// =============================================================================
+// Register : PIO_IRQ
+// Description : State machine IRQ flags register. Write 1 to clear. There are 8
+// state machine IRQ flags, which can be set, cleared, and waited
+// on by the state machines. There's no fixed association between
+// flags and state machines -- any state machine can use any flag.
+//
+// Any of the 8 flags can be used for timing synchronisation
+// between state machines, using IRQ and WAIT instructions. The
+// lower four of these flags are also routed out to system-level
+// interrupt requests, alongside FIFO status interrupts -- see
+// e.g. IRQ0_INTE.
+#define PIO_IRQ_OFFSET _u(0x00000030)
+#define PIO_IRQ_BITS _u(0x000000ff)
+#define PIO_IRQ_RESET _u(0x00000000)
+#define PIO_IRQ_MSB _u(7)
+#define PIO_IRQ_LSB _u(0)
+#define PIO_IRQ_ACCESS "WC"
+// =============================================================================
+// Register : PIO_IRQ_FORCE
+// Description : Writing a 1 to each of these bits will forcibly assert the
+// corresponding IRQ. Note this is different to the INTF register:
+// writing here affects PIO internal state. INTF just asserts the
+// processor-facing IRQ signal for testing ISRs, and is not
+// visible to the state machines.
+#define PIO_IRQ_FORCE_OFFSET _u(0x00000034)
+#define PIO_IRQ_FORCE_BITS _u(0x000000ff)
+#define PIO_IRQ_FORCE_RESET _u(0x00000000)
+#define PIO_IRQ_FORCE_MSB _u(7)
+#define PIO_IRQ_FORCE_LSB _u(0)
+#define PIO_IRQ_FORCE_ACCESS "WF"
+// =============================================================================
+// Register : PIO_INPUT_SYNC_BYPASS
+// Description : There is a 2-flipflop synchronizer on each GPIO input, which
+// protects PIO logic from metastabilities. This increases input
+// delay, and for fast synchronous IO (e.g. SPI) these
+// synchronizers may need to be bypassed. Each bit in this
+// register corresponds to one GPIO.
+// 0 -> input is synchronized (default)
+// 1 -> synchronizer is bypassed
+// If in doubt, leave this register as all zeroes.
+#define PIO_INPUT_SYNC_BYPASS_OFFSET _u(0x00000038)
+#define PIO_INPUT_SYNC_BYPASS_BITS _u(0xffffffff)
+#define PIO_INPUT_SYNC_BYPASS_RESET _u(0x00000000)
+#define PIO_INPUT_SYNC_BYPASS_MSB _u(31)
+#define PIO_INPUT_SYNC_BYPASS_LSB _u(0)
+#define PIO_INPUT_SYNC_BYPASS_ACCESS "RW"
+// =============================================================================
+// Register : PIO_DBG_PADOUT
+// Description : Read to sample the pad output values PIO is currently driving
+// to the GPIOs. On RP2040 there are 30 GPIOs, so the two most
+// significant bits are hardwired to 0.
+#define PIO_DBG_PADOUT_OFFSET _u(0x0000003c)
+#define PIO_DBG_PADOUT_BITS _u(0xffffffff)
+#define PIO_DBG_PADOUT_RESET _u(0x00000000)
+#define PIO_DBG_PADOUT_MSB _u(31)
+#define PIO_DBG_PADOUT_LSB _u(0)
+#define PIO_DBG_PADOUT_ACCESS "RO"
+// =============================================================================
+// Register : PIO_DBG_PADOE
+// Description : Read to sample the pad output enables (direction) PIO is
+// currently driving to the GPIOs. On RP2040 there are 30 GPIOs,
+// so the two most significant bits are hardwired to 0.
+#define PIO_DBG_PADOE_OFFSET _u(0x00000040)
+#define PIO_DBG_PADOE_BITS _u(0xffffffff)
+#define PIO_DBG_PADOE_RESET _u(0x00000000)
+#define PIO_DBG_PADOE_MSB _u(31)
+#define PIO_DBG_PADOE_LSB _u(0)
+#define PIO_DBG_PADOE_ACCESS "RO"
+// =============================================================================
+// Register : PIO_DBG_CFGINFO
+// Description : The PIO hardware has some free parameters that may vary between
+// chip products.
+// These should be provided in the chip datasheet, but are also
+// exposed here.
+#define PIO_DBG_CFGINFO_OFFSET _u(0x00000044)
+#define PIO_DBG_CFGINFO_BITS _u(0x003f0f3f)
+#define PIO_DBG_CFGINFO_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_DBG_CFGINFO_IMEM_SIZE
+// Description : The size of the instruction memory, measured in units of one
+// instruction
+#define PIO_DBG_CFGINFO_IMEM_SIZE_RESET "-"
+#define PIO_DBG_CFGINFO_IMEM_SIZE_BITS _u(0x003f0000)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_MSB _u(21)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_LSB _u(16)
+#define PIO_DBG_CFGINFO_IMEM_SIZE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_DBG_CFGINFO_SM_COUNT
+// Description : The number of state machines this PIO instance is equipped
+// with.
+#define PIO_DBG_CFGINFO_SM_COUNT_RESET "-"
+#define PIO_DBG_CFGINFO_SM_COUNT_BITS _u(0x00000f00)
+#define PIO_DBG_CFGINFO_SM_COUNT_MSB _u(11)
+#define PIO_DBG_CFGINFO_SM_COUNT_LSB _u(8)
+#define PIO_DBG_CFGINFO_SM_COUNT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_DBG_CFGINFO_FIFO_DEPTH
+// Description : The depth of the state machine TX/RX FIFOs, measured in words.
+// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double
+// this depth.
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_RESET "-"
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_BITS _u(0x0000003f)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_MSB _u(5)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_LSB _u(0)
+#define PIO_DBG_CFGINFO_FIFO_DEPTH_ACCESS "RO"
+// =============================================================================
+// Register : PIO_INSTR_MEM0
+// Description : Write-only access to instruction memory location 0
+#define PIO_INSTR_MEM0_OFFSET _u(0x00000048)
+#define PIO_INSTR_MEM0_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM0_RESET _u(0x00000000)
+#define PIO_INSTR_MEM0_MSB _u(15)
+#define PIO_INSTR_MEM0_LSB _u(0)
+#define PIO_INSTR_MEM0_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM1
+// Description : Write-only access to instruction memory location 1
+#define PIO_INSTR_MEM1_OFFSET _u(0x0000004c)
+#define PIO_INSTR_MEM1_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM1_RESET _u(0x00000000)
+#define PIO_INSTR_MEM1_MSB _u(15)
+#define PIO_INSTR_MEM1_LSB _u(0)
+#define PIO_INSTR_MEM1_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM2
+// Description : Write-only access to instruction memory location 2
+#define PIO_INSTR_MEM2_OFFSET _u(0x00000050)
+#define PIO_INSTR_MEM2_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM2_RESET _u(0x00000000)
+#define PIO_INSTR_MEM2_MSB _u(15)
+#define PIO_INSTR_MEM2_LSB _u(0)
+#define PIO_INSTR_MEM2_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM3
+// Description : Write-only access to instruction memory location 3
+#define PIO_INSTR_MEM3_OFFSET _u(0x00000054)
+#define PIO_INSTR_MEM3_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM3_RESET _u(0x00000000)
+#define PIO_INSTR_MEM3_MSB _u(15)
+#define PIO_INSTR_MEM3_LSB _u(0)
+#define PIO_INSTR_MEM3_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM4
+// Description : Write-only access to instruction memory location 4
+#define PIO_INSTR_MEM4_OFFSET _u(0x00000058)
+#define PIO_INSTR_MEM4_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM4_RESET _u(0x00000000)
+#define PIO_INSTR_MEM4_MSB _u(15)
+#define PIO_INSTR_MEM4_LSB _u(0)
+#define PIO_INSTR_MEM4_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM5
+// Description : Write-only access to instruction memory location 5
+#define PIO_INSTR_MEM5_OFFSET _u(0x0000005c)
+#define PIO_INSTR_MEM5_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM5_RESET _u(0x00000000)
+#define PIO_INSTR_MEM5_MSB _u(15)
+#define PIO_INSTR_MEM5_LSB _u(0)
+#define PIO_INSTR_MEM5_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM6
+// Description : Write-only access to instruction memory location 6
+#define PIO_INSTR_MEM6_OFFSET _u(0x00000060)
+#define PIO_INSTR_MEM6_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM6_RESET _u(0x00000000)
+#define PIO_INSTR_MEM6_MSB _u(15)
+#define PIO_INSTR_MEM6_LSB _u(0)
+#define PIO_INSTR_MEM6_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM7
+// Description : Write-only access to instruction memory location 7
+#define PIO_INSTR_MEM7_OFFSET _u(0x00000064)
+#define PIO_INSTR_MEM7_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM7_RESET _u(0x00000000)
+#define PIO_INSTR_MEM7_MSB _u(15)
+#define PIO_INSTR_MEM7_LSB _u(0)
+#define PIO_INSTR_MEM7_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM8
+// Description : Write-only access to instruction memory location 8
+#define PIO_INSTR_MEM8_OFFSET _u(0x00000068)
+#define PIO_INSTR_MEM8_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM8_RESET _u(0x00000000)
+#define PIO_INSTR_MEM8_MSB _u(15)
+#define PIO_INSTR_MEM8_LSB _u(0)
+#define PIO_INSTR_MEM8_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM9
+// Description : Write-only access to instruction memory location 9
+#define PIO_INSTR_MEM9_OFFSET _u(0x0000006c)
+#define PIO_INSTR_MEM9_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM9_RESET _u(0x00000000)
+#define PIO_INSTR_MEM9_MSB _u(15)
+#define PIO_INSTR_MEM9_LSB _u(0)
+#define PIO_INSTR_MEM9_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM10
+// Description : Write-only access to instruction memory location 10
+#define PIO_INSTR_MEM10_OFFSET _u(0x00000070)
+#define PIO_INSTR_MEM10_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM10_RESET _u(0x00000000)
+#define PIO_INSTR_MEM10_MSB _u(15)
+#define PIO_INSTR_MEM10_LSB _u(0)
+#define PIO_INSTR_MEM10_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM11
+// Description : Write-only access to instruction memory location 11
+#define PIO_INSTR_MEM11_OFFSET _u(0x00000074)
+#define PIO_INSTR_MEM11_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM11_RESET _u(0x00000000)
+#define PIO_INSTR_MEM11_MSB _u(15)
+#define PIO_INSTR_MEM11_LSB _u(0)
+#define PIO_INSTR_MEM11_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM12
+// Description : Write-only access to instruction memory location 12
+#define PIO_INSTR_MEM12_OFFSET _u(0x00000078)
+#define PIO_INSTR_MEM12_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM12_RESET _u(0x00000000)
+#define PIO_INSTR_MEM12_MSB _u(15)
+#define PIO_INSTR_MEM12_LSB _u(0)
+#define PIO_INSTR_MEM12_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM13
+// Description : Write-only access to instruction memory location 13
+#define PIO_INSTR_MEM13_OFFSET _u(0x0000007c)
+#define PIO_INSTR_MEM13_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM13_RESET _u(0x00000000)
+#define PIO_INSTR_MEM13_MSB _u(15)
+#define PIO_INSTR_MEM13_LSB _u(0)
+#define PIO_INSTR_MEM13_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM14
+// Description : Write-only access to instruction memory location 14
+#define PIO_INSTR_MEM14_OFFSET _u(0x00000080)
+#define PIO_INSTR_MEM14_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM14_RESET _u(0x00000000)
+#define PIO_INSTR_MEM14_MSB _u(15)
+#define PIO_INSTR_MEM14_LSB _u(0)
+#define PIO_INSTR_MEM14_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM15
+// Description : Write-only access to instruction memory location 15
+#define PIO_INSTR_MEM15_OFFSET _u(0x00000084)
+#define PIO_INSTR_MEM15_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM15_RESET _u(0x00000000)
+#define PIO_INSTR_MEM15_MSB _u(15)
+#define PIO_INSTR_MEM15_LSB _u(0)
+#define PIO_INSTR_MEM15_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM16
+// Description : Write-only access to instruction memory location 16
+#define PIO_INSTR_MEM16_OFFSET _u(0x00000088)
+#define PIO_INSTR_MEM16_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM16_RESET _u(0x00000000)
+#define PIO_INSTR_MEM16_MSB _u(15)
+#define PIO_INSTR_MEM16_LSB _u(0)
+#define PIO_INSTR_MEM16_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM17
+// Description : Write-only access to instruction memory location 17
+#define PIO_INSTR_MEM17_OFFSET _u(0x0000008c)
+#define PIO_INSTR_MEM17_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM17_RESET _u(0x00000000)
+#define PIO_INSTR_MEM17_MSB _u(15)
+#define PIO_INSTR_MEM17_LSB _u(0)
+#define PIO_INSTR_MEM17_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM18
+// Description : Write-only access to instruction memory location 18
+#define PIO_INSTR_MEM18_OFFSET _u(0x00000090)
+#define PIO_INSTR_MEM18_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM18_RESET _u(0x00000000)
+#define PIO_INSTR_MEM18_MSB _u(15)
+#define PIO_INSTR_MEM18_LSB _u(0)
+#define PIO_INSTR_MEM18_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM19
+// Description : Write-only access to instruction memory location 19
+#define PIO_INSTR_MEM19_OFFSET _u(0x00000094)
+#define PIO_INSTR_MEM19_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM19_RESET _u(0x00000000)
+#define PIO_INSTR_MEM19_MSB _u(15)
+#define PIO_INSTR_MEM19_LSB _u(0)
+#define PIO_INSTR_MEM19_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM20
+// Description : Write-only access to instruction memory location 20
+#define PIO_INSTR_MEM20_OFFSET _u(0x00000098)
+#define PIO_INSTR_MEM20_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM20_RESET _u(0x00000000)
+#define PIO_INSTR_MEM20_MSB _u(15)
+#define PIO_INSTR_MEM20_LSB _u(0)
+#define PIO_INSTR_MEM20_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM21
+// Description : Write-only access to instruction memory location 21
+#define PIO_INSTR_MEM21_OFFSET _u(0x0000009c)
+#define PIO_INSTR_MEM21_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM21_RESET _u(0x00000000)
+#define PIO_INSTR_MEM21_MSB _u(15)
+#define PIO_INSTR_MEM21_LSB _u(0)
+#define PIO_INSTR_MEM21_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM22
+// Description : Write-only access to instruction memory location 22
+#define PIO_INSTR_MEM22_OFFSET _u(0x000000a0)
+#define PIO_INSTR_MEM22_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM22_RESET _u(0x00000000)
+#define PIO_INSTR_MEM22_MSB _u(15)
+#define PIO_INSTR_MEM22_LSB _u(0)
+#define PIO_INSTR_MEM22_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM23
+// Description : Write-only access to instruction memory location 23
+#define PIO_INSTR_MEM23_OFFSET _u(0x000000a4)
+#define PIO_INSTR_MEM23_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM23_RESET _u(0x00000000)
+#define PIO_INSTR_MEM23_MSB _u(15)
+#define PIO_INSTR_MEM23_LSB _u(0)
+#define PIO_INSTR_MEM23_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM24
+// Description : Write-only access to instruction memory location 24
+#define PIO_INSTR_MEM24_OFFSET _u(0x000000a8)
+#define PIO_INSTR_MEM24_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM24_RESET _u(0x00000000)
+#define PIO_INSTR_MEM24_MSB _u(15)
+#define PIO_INSTR_MEM24_LSB _u(0)
+#define PIO_INSTR_MEM24_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM25
+// Description : Write-only access to instruction memory location 25
+#define PIO_INSTR_MEM25_OFFSET _u(0x000000ac)
+#define PIO_INSTR_MEM25_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM25_RESET _u(0x00000000)
+#define PIO_INSTR_MEM25_MSB _u(15)
+#define PIO_INSTR_MEM25_LSB _u(0)
+#define PIO_INSTR_MEM25_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM26
+// Description : Write-only access to instruction memory location 26
+#define PIO_INSTR_MEM26_OFFSET _u(0x000000b0)
+#define PIO_INSTR_MEM26_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM26_RESET _u(0x00000000)
+#define PIO_INSTR_MEM26_MSB _u(15)
+#define PIO_INSTR_MEM26_LSB _u(0)
+#define PIO_INSTR_MEM26_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM27
+// Description : Write-only access to instruction memory location 27
+#define PIO_INSTR_MEM27_OFFSET _u(0x000000b4)
+#define PIO_INSTR_MEM27_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM27_RESET _u(0x00000000)
+#define PIO_INSTR_MEM27_MSB _u(15)
+#define PIO_INSTR_MEM27_LSB _u(0)
+#define PIO_INSTR_MEM27_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM28
+// Description : Write-only access to instruction memory location 28
+#define PIO_INSTR_MEM28_OFFSET _u(0x000000b8)
+#define PIO_INSTR_MEM28_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM28_RESET _u(0x00000000)
+#define PIO_INSTR_MEM28_MSB _u(15)
+#define PIO_INSTR_MEM28_LSB _u(0)
+#define PIO_INSTR_MEM28_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM29
+// Description : Write-only access to instruction memory location 29
+#define PIO_INSTR_MEM29_OFFSET _u(0x000000bc)
+#define PIO_INSTR_MEM29_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM29_RESET _u(0x00000000)
+#define PIO_INSTR_MEM29_MSB _u(15)
+#define PIO_INSTR_MEM29_LSB _u(0)
+#define PIO_INSTR_MEM29_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM30
+// Description : Write-only access to instruction memory location 30
+#define PIO_INSTR_MEM30_OFFSET _u(0x000000c0)
+#define PIO_INSTR_MEM30_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM30_RESET _u(0x00000000)
+#define PIO_INSTR_MEM30_MSB _u(15)
+#define PIO_INSTR_MEM30_LSB _u(0)
+#define PIO_INSTR_MEM30_ACCESS "WO"
+// =============================================================================
+// Register : PIO_INSTR_MEM31
+// Description : Write-only access to instruction memory location 31
+#define PIO_INSTR_MEM31_OFFSET _u(0x000000c4)
+#define PIO_INSTR_MEM31_BITS _u(0x0000ffff)
+#define PIO_INSTR_MEM31_RESET _u(0x00000000)
+#define PIO_INSTR_MEM31_MSB _u(15)
+#define PIO_INSTR_MEM31_LSB _u(0)
+#define PIO_INSTR_MEM31_ACCESS "WO"
+// =============================================================================
+// Register : PIO_SM0_CLKDIV
+// Description : Clock divisor register for state machine 0
+// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM0_CLKDIV_OFFSET _u(0x000000c8)
+#define PIO_SM0_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM0_CLKDIV_RESET _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+// be 0.
+#define PIO_SM0_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM0_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM0_CLKDIV_INT_MSB _u(31)
+#define PIO_SM0_CLKDIV_INT_LSB _u(16)
+#define PIO_SM0_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM0_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM0_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM0_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM0_CLKDIV_FRAC_LSB _u(8)
+#define PIO_SM0_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM0_EXECCTRL
+// Description : Execution/behavioural settings for state machine 0
+#define PIO_SM0_EXECCTRL_OFFSET _u(0x000000cc)
+#define PIO_SM0_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM0_EXECCTRL_RESET _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+// latched by the state machine. Will clear to 0 once this
+// instruction completes.
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_LSB _u(31)
+#define PIO_SM0_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+// as side-set enable, rather than a side-set data bit. This
+// allows instructions to perform side-set optionally, rather than
+// on every instruction, but the maximum possible side-set width
+// is reduced from 5 to 4. Note that the value of
+// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM0_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM0_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM0_EXECCTRL_SIDE_EN_LSB _u(30)
+#define PIO_SM0_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+// pin values
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_LSB _u(29)
+#define PIO_SM0_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+// input mapping.
+#define PIO_SM0_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM0_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM0_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM0_EXECCTRL_JMP_PIN_LSB _u(24)
+#define PIO_SM0_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_LSB _u(19)
+#define PIO_SM0_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+// When used in conjunction with OUT_STICKY, writes with an enable
+// of 0 will
+// deassert the latest pin write. This can create useful
+// masking/override behaviour
+// due to the priority ordering of state machine pin writes (SM0 <
+// SM1 < ...)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
+#define PIO_SM0_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM0_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_LSB _u(17)
+#define PIO_SM0_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+// wrap_bottom.
+// If the instruction is a jump, and the jump condition is true,
+// the jump takes priority.
+#define PIO_SM0_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_LSB _u(12)
+#define PIO_SM0_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
+#define PIO_SM0_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM0_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_LSB _u(4)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_ACCESS "RW"
+#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM0_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM0_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM0_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM0_EXECCTRL_STATUS_N_LSB _u(0)
+#define PIO_SM0_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM0_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+// machine 0
+#define PIO_SM0_SHIFTCTRL_OFFSET _u(0x000000d0)
+#define PIO_SM0_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM0_SHIFTCTRL_RESET _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+// as deep.
+// TX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_LSB _u(31)
+#define PIO_SM0_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+// as deep.
+// RX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_LSB _u(30)
+#define PIO_SM0_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+// conditional pull (PULL IFEMPTY), will take place.
+// Write 0 for value of 32.
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_LSB _u(25)
+#define PIO_SM0_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+// push (PUSH IFFULL), will take place.
+// Write 0 for value of 32.
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
+#define PIO_SM0_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
+#define PIO_SM0_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+// left). 0 = to left.
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
+#define PIO_SM0_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+// i.e. on or following an OUT instruction which causes the output
+// shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_LSB _u(17)
+#define PIO_SM0_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+// i.e. on an IN instruction which causes the input shift counter
+// to reach or exceed PUSH_THRESH.
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_LSB _u(16)
+#define PIO_SM0_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM0_ADDR
+// Description : Current instruction address of state machine 0
+#define PIO_SM0_ADDR_OFFSET _u(0x000000d4)
+#define PIO_SM0_ADDR_BITS _u(0x0000001f)
+#define PIO_SM0_ADDR_RESET _u(0x00000000)
+#define PIO_SM0_ADDR_MSB _u(4)
+#define PIO_SM0_ADDR_LSB _u(0)
+#define PIO_SM0_ADDR_ACCESS "RO"
+// =============================================================================
+// Register : PIO_SM0_INSTR
+// Description : Read to see the instruction currently addressed by state
+// machine 0's program counter
+// Write to execute an instruction immediately (including jumps)
+// and then resume execution.
+#define PIO_SM0_INSTR_OFFSET _u(0x000000d8)
+#define PIO_SM0_INSTR_BITS _u(0x0000ffff)
+#define PIO_SM0_INSTR_RESET "-"
+#define PIO_SM0_INSTR_MSB _u(15)
+#define PIO_SM0_INSTR_LSB _u(0)
+#define PIO_SM0_INSTR_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM0_PINCTRL
+// Description : State machine pin control
+#define PIO_SM0_PINCTRL_OFFSET _u(0x000000dc)
+#define PIO_SM0_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM0_PINCTRL_RESET _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+// which are used for side-set. Inclusive of the enable bit, if
+// present. Minimum of 0 (all delay bits, no side-set) and maximum
+// of 5 (all side-set, no delay).
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_LSB _u(29)
+#define PIO_SM0_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+// inclusive.
+#define PIO_SM0_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM0_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM0_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM0_PINCTRL_SET_COUNT_LSB _u(26)
+#define PIO_SM0_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+// PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM0_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM0_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM0_PINCTRL_OUT_COUNT_LSB _u(20)
+#define PIO_SM0_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+// machine's IN data bus. Higher-numbered pins are mapped to
+// consecutively more-significant data bits, with a modulo of 32
+// applied to pin number.
+#define PIO_SM0_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM0_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM0_PINCTRL_IN_BASE_LSB _u(15)
+#define PIO_SM0_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+// operation. The MSBs of an instruction's side-set/delay field
+// (up to 5, determined by SIDESET_COUNT) are used for side-set
+// data, with the remaining LSBs used for delay. The
+// least-significant bit of the side-set portion is the bit
+// written to this pin, with more-significant bits written to
+// higher-numbered pins.
+#define PIO_SM0_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_LSB _u(10)
+#define PIO_SM0_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+// SET PINDIRS instruction. The data written to this pin is the
+// least-significant bit of the SET data.
+#define PIO_SM0_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM0_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM0_PINCTRL_SET_BASE_LSB _u(5)
+#define PIO_SM0_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM0_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+// OUT PINDIRS or MOV PINS instruction. The data written to this
+// pin will always be the least-significant bit of the OUT or MOV
+// data.
+#define PIO_SM0_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM0_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM0_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM0_PINCTRL_OUT_BASE_LSB _u(0)
+#define PIO_SM0_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM1_CLKDIV
+// Description : Clock divisor register for state machine 1
+// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM1_CLKDIV_OFFSET _u(0x000000e0)
+#define PIO_SM1_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM1_CLKDIV_RESET _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+// be 0.
+#define PIO_SM1_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM1_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM1_CLKDIV_INT_MSB _u(31)
+#define PIO_SM1_CLKDIV_INT_LSB _u(16)
+#define PIO_SM1_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM1_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM1_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM1_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM1_CLKDIV_FRAC_LSB _u(8)
+#define PIO_SM1_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM1_EXECCTRL
+// Description : Execution/behavioural settings for state machine 1
+#define PIO_SM1_EXECCTRL_OFFSET _u(0x000000e4)
+#define PIO_SM1_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM1_EXECCTRL_RESET _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+// latched by the state machine. Will clear to 0 once this
+// instruction completes.
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_LSB _u(31)
+#define PIO_SM1_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+// as side-set enable, rather than a side-set data bit. This
+// allows instructions to perform side-set optionally, rather than
+// on every instruction, but the maximum possible side-set width
+// is reduced from 5 to 4. Note that the value of
+// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM1_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM1_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM1_EXECCTRL_SIDE_EN_LSB _u(30)
+#define PIO_SM1_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+// pin values
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_LSB _u(29)
+#define PIO_SM1_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+// input mapping.
+#define PIO_SM1_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM1_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM1_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM1_EXECCTRL_JMP_PIN_LSB _u(24)
+#define PIO_SM1_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_LSB _u(19)
+#define PIO_SM1_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+// When used in conjunction with OUT_STICKY, writes with an enable
+// of 0 will
+// deassert the latest pin write. This can create useful
+// masking/override behaviour
+// due to the priority ordering of state machine pin writes (SM0 <
+// SM1 < ...)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
+#define PIO_SM1_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM1_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_LSB _u(17)
+#define PIO_SM1_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+// wrap_bottom.
+// If the instruction is a jump, and the jump condition is true,
+// the jump takes priority.
+#define PIO_SM1_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_LSB _u(12)
+#define PIO_SM1_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
+#define PIO_SM1_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM1_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_LSB _u(4)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_ACCESS "RW"
+#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM1_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM1_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM1_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM1_EXECCTRL_STATUS_N_LSB _u(0)
+#define PIO_SM1_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM1_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+// machine 1
+#define PIO_SM1_SHIFTCTRL_OFFSET _u(0x000000e8)
+#define PIO_SM1_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM1_SHIFTCTRL_RESET _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+// as deep.
+// TX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_LSB _u(31)
+#define PIO_SM1_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+// as deep.
+// RX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_LSB _u(30)
+#define PIO_SM1_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+// conditional pull (PULL IFEMPTY), will take place.
+// Write 0 for value of 32.
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_LSB _u(25)
+#define PIO_SM1_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+// push (PUSH IFFULL), will take place.
+// Write 0 for value of 32.
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
+#define PIO_SM1_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
+#define PIO_SM1_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+// left). 0 = to left.
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
+#define PIO_SM1_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+// i.e. on or following an OUT instruction which causes the output
+// shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_LSB _u(17)
+#define PIO_SM1_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+// i.e. on an IN instruction which causes the input shift counter
+// to reach or exceed PUSH_THRESH.
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_LSB _u(16)
+#define PIO_SM1_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM1_ADDR
+// Description : Current instruction address of state machine 1
+#define PIO_SM1_ADDR_OFFSET _u(0x000000ec)
+#define PIO_SM1_ADDR_BITS _u(0x0000001f)
+#define PIO_SM1_ADDR_RESET _u(0x00000000)
+#define PIO_SM1_ADDR_MSB _u(4)
+#define PIO_SM1_ADDR_LSB _u(0)
+#define PIO_SM1_ADDR_ACCESS "RO"
+// =============================================================================
+// Register : PIO_SM1_INSTR
+// Description : Read to see the instruction currently addressed by state
+// machine 1's program counter
+// Write to execute an instruction immediately (including jumps)
+// and then resume execution.
+#define PIO_SM1_INSTR_OFFSET _u(0x000000f0)
+#define PIO_SM1_INSTR_BITS _u(0x0000ffff)
+#define PIO_SM1_INSTR_RESET "-"
+#define PIO_SM1_INSTR_MSB _u(15)
+#define PIO_SM1_INSTR_LSB _u(0)
+#define PIO_SM1_INSTR_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM1_PINCTRL
+// Description : State machine pin control
+#define PIO_SM1_PINCTRL_OFFSET _u(0x000000f4)
+#define PIO_SM1_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM1_PINCTRL_RESET _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+// which are used for side-set. Inclusive of the enable bit, if
+// present. Minimum of 0 (all delay bits, no side-set) and maximum
+// of 5 (all side-set, no delay).
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_LSB _u(29)
+#define PIO_SM1_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+// inclusive.
+#define PIO_SM1_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM1_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM1_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM1_PINCTRL_SET_COUNT_LSB _u(26)
+#define PIO_SM1_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+// PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM1_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM1_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM1_PINCTRL_OUT_COUNT_LSB _u(20)
+#define PIO_SM1_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+// machine's IN data bus. Higher-numbered pins are mapped to
+// consecutively more-significant data bits, with a modulo of 32
+// applied to pin number.
+#define PIO_SM1_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM1_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM1_PINCTRL_IN_BASE_LSB _u(15)
+#define PIO_SM1_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+// operation. The MSBs of an instruction's side-set/delay field
+// (up to 5, determined by SIDESET_COUNT) are used for side-set
+// data, with the remaining LSBs used for delay. The
+// least-significant bit of the side-set portion is the bit
+// written to this pin, with more-significant bits written to
+// higher-numbered pins.
+#define PIO_SM1_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_LSB _u(10)
+#define PIO_SM1_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+// SET PINDIRS instruction. The data written to this pin is the
+// least-significant bit of the SET data.
+#define PIO_SM1_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM1_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM1_PINCTRL_SET_BASE_LSB _u(5)
+#define PIO_SM1_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM1_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+// OUT PINDIRS or MOV PINS instruction. The data written to this
+// pin will always be the least-significant bit of the OUT or MOV
+// data.
+#define PIO_SM1_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM1_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM1_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM1_PINCTRL_OUT_BASE_LSB _u(0)
+#define PIO_SM1_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM2_CLKDIV
+// Description : Clock divisor register for state machine 2
+// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM2_CLKDIV_OFFSET _u(0x000000f8)
+#define PIO_SM2_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM2_CLKDIV_RESET _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+// be 0.
+#define PIO_SM2_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM2_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM2_CLKDIV_INT_MSB _u(31)
+#define PIO_SM2_CLKDIV_INT_LSB _u(16)
+#define PIO_SM2_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM2_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM2_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM2_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM2_CLKDIV_FRAC_LSB _u(8)
+#define PIO_SM2_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM2_EXECCTRL
+// Description : Execution/behavioural settings for state machine 2
+#define PIO_SM2_EXECCTRL_OFFSET _u(0x000000fc)
+#define PIO_SM2_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM2_EXECCTRL_RESET _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+// latched by the state machine. Will clear to 0 once this
+// instruction completes.
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_LSB _u(31)
+#define PIO_SM2_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+// as side-set enable, rather than a side-set data bit. This
+// allows instructions to perform side-set optionally, rather than
+// on every instruction, but the maximum possible side-set width
+// is reduced from 5 to 4. Note that the value of
+// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM2_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM2_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM2_EXECCTRL_SIDE_EN_LSB _u(30)
+#define PIO_SM2_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+// pin values
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_LSB _u(29)
+#define PIO_SM2_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+// input mapping.
+#define PIO_SM2_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM2_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM2_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM2_EXECCTRL_JMP_PIN_LSB _u(24)
+#define PIO_SM2_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_LSB _u(19)
+#define PIO_SM2_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+// When used in conjunction with OUT_STICKY, writes with an enable
+// of 0 will
+// deassert the latest pin write. This can create useful
+// masking/override behaviour
+// due to the priority ordering of state machine pin writes (SM0 <
+// SM1 < ...)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
+#define PIO_SM2_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM2_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_LSB _u(17)
+#define PIO_SM2_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+// wrap_bottom.
+// If the instruction is a jump, and the jump condition is true,
+// the jump takes priority.
+#define PIO_SM2_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_LSB _u(12)
+#define PIO_SM2_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
+#define PIO_SM2_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM2_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_LSB _u(4)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_ACCESS "RW"
+#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM2_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM2_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM2_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM2_EXECCTRL_STATUS_N_LSB _u(0)
+#define PIO_SM2_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM2_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+// machine 2
+#define PIO_SM2_SHIFTCTRL_OFFSET _u(0x00000100)
+#define PIO_SM2_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM2_SHIFTCTRL_RESET _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+// as deep.
+// TX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_LSB _u(31)
+#define PIO_SM2_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+// as deep.
+// RX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_LSB _u(30)
+#define PIO_SM2_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+// conditional pull (PULL IFEMPTY), will take place.
+// Write 0 for value of 32.
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_LSB _u(25)
+#define PIO_SM2_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+// push (PUSH IFFULL), will take place.
+// Write 0 for value of 32.
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
+#define PIO_SM2_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
+#define PIO_SM2_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+// left). 0 = to left.
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
+#define PIO_SM2_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+// i.e. on or following an OUT instruction which causes the output
+// shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_LSB _u(17)
+#define PIO_SM2_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+// i.e. on an IN instruction which causes the input shift counter
+// to reach or exceed PUSH_THRESH.
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_LSB _u(16)
+#define PIO_SM2_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM2_ADDR
+// Description : Current instruction address of state machine 2
+#define PIO_SM2_ADDR_OFFSET _u(0x00000104)
+#define PIO_SM2_ADDR_BITS _u(0x0000001f)
+#define PIO_SM2_ADDR_RESET _u(0x00000000)
+#define PIO_SM2_ADDR_MSB _u(4)
+#define PIO_SM2_ADDR_LSB _u(0)
+#define PIO_SM2_ADDR_ACCESS "RO"
+// =============================================================================
+// Register : PIO_SM2_INSTR
+// Description : Read to see the instruction currently addressed by state
+// machine 2's program counter
+// Write to execute an instruction immediately (including jumps)
+// and then resume execution.
+#define PIO_SM2_INSTR_OFFSET _u(0x00000108)
+#define PIO_SM2_INSTR_BITS _u(0x0000ffff)
+#define PIO_SM2_INSTR_RESET "-"
+#define PIO_SM2_INSTR_MSB _u(15)
+#define PIO_SM2_INSTR_LSB _u(0)
+#define PIO_SM2_INSTR_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM2_PINCTRL
+// Description : State machine pin control
+#define PIO_SM2_PINCTRL_OFFSET _u(0x0000010c)
+#define PIO_SM2_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM2_PINCTRL_RESET _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+// which are used for side-set. Inclusive of the enable bit, if
+// present. Minimum of 0 (all delay bits, no side-set) and maximum
+// of 5 (all side-set, no delay).
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_LSB _u(29)
+#define PIO_SM2_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+// inclusive.
+#define PIO_SM2_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM2_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM2_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM2_PINCTRL_SET_COUNT_LSB _u(26)
+#define PIO_SM2_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+// PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM2_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM2_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM2_PINCTRL_OUT_COUNT_LSB _u(20)
+#define PIO_SM2_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+// machine's IN data bus. Higher-numbered pins are mapped to
+// consecutively more-significant data bits, with a modulo of 32
+// applied to pin number.
+#define PIO_SM2_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM2_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM2_PINCTRL_IN_BASE_LSB _u(15)
+#define PIO_SM2_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+// operation. The MSBs of an instruction's side-set/delay field
+// (up to 5, determined by SIDESET_COUNT) are used for side-set
+// data, with the remaining LSBs used for delay. The
+// least-significant bit of the side-set portion is the bit
+// written to this pin, with more-significant bits written to
+// higher-numbered pins.
+#define PIO_SM2_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_LSB _u(10)
+#define PIO_SM2_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+// SET PINDIRS instruction. The data written to this pin is the
+// least-significant bit of the SET data.
+#define PIO_SM2_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM2_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM2_PINCTRL_SET_BASE_LSB _u(5)
+#define PIO_SM2_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM2_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+// OUT PINDIRS or MOV PINS instruction. The data written to this
+// pin will always be the least-significant bit of the OUT or MOV
+// data.
+#define PIO_SM2_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM2_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM2_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM2_PINCTRL_OUT_BASE_LSB _u(0)
+#define PIO_SM2_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM3_CLKDIV
+// Description : Clock divisor register for state machine 3
+// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+#define PIO_SM3_CLKDIV_OFFSET _u(0x00000110)
+#define PIO_SM3_CLKDIV_BITS _u(0xffffff00)
+#define PIO_SM3_CLKDIV_RESET _u(0x00010000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_CLKDIV_INT
+// Description : Effective frequency is sysclk/(int + frac/256).
+// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also
+// be 0.
+#define PIO_SM3_CLKDIV_INT_RESET _u(0x0001)
+#define PIO_SM3_CLKDIV_INT_BITS _u(0xffff0000)
+#define PIO_SM3_CLKDIV_INT_MSB _u(31)
+#define PIO_SM3_CLKDIV_INT_LSB _u(16)
+#define PIO_SM3_CLKDIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_CLKDIV_FRAC
+// Description : Fractional part of clock divisor
+#define PIO_SM3_CLKDIV_FRAC_RESET _u(0x00)
+#define PIO_SM3_CLKDIV_FRAC_BITS _u(0x0000ff00)
+#define PIO_SM3_CLKDIV_FRAC_MSB _u(15)
+#define PIO_SM3_CLKDIV_FRAC_LSB _u(8)
+#define PIO_SM3_CLKDIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM3_EXECCTRL
+// Description : Execution/behavioural settings for state machine 3
+#define PIO_SM3_EXECCTRL_OFFSET _u(0x00000114)
+#define PIO_SM3_EXECCTRL_BITS _u(0xffffff9f)
+#define PIO_SM3_EXECCTRL_RESET _u(0x0001f000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_EXEC_STALLED
+// Description : If 1, an instruction written to SMx_INSTR is stalled, and
+// latched by the state machine. Will clear to 0 once this
+// instruction completes.
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_BITS _u(0x80000000)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_MSB _u(31)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_LSB _u(31)
+#define PIO_SM3_EXECCTRL_EXEC_STALLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_SIDE_EN
+// Description : If 1, the MSB of the Delay/Side-set instruction field is used
+// as side-set enable, rather than a side-set data bit. This
+// allows instructions to perform side-set optionally, rather than
+// on every instruction, but the maximum possible side-set width
+// is reduced from 5 to 4. Note that the value of
+// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+#define PIO_SM3_EXECCTRL_SIDE_EN_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_SIDE_EN_BITS _u(0x40000000)
+#define PIO_SM3_EXECCTRL_SIDE_EN_MSB _u(30)
+#define PIO_SM3_EXECCTRL_SIDE_EN_LSB _u(30)
+#define PIO_SM3_EXECCTRL_SIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_SIDE_PINDIR
+// Description : If 1, side-set data is asserted to pin directions, instead of
+// pin values
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_BITS _u(0x20000000)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_MSB _u(29)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_LSB _u(29)
+#define PIO_SM3_EXECCTRL_SIDE_PINDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_JMP_PIN
+// Description : The GPIO number to use as condition for JMP PIN. Unaffected by
+// input mapping.
+#define PIO_SM3_EXECCTRL_JMP_PIN_RESET _u(0x00)
+#define PIO_SM3_EXECCTRL_JMP_PIN_BITS _u(0x1f000000)
+#define PIO_SM3_EXECCTRL_JMP_PIN_MSB _u(28)
+#define PIO_SM3_EXECCTRL_JMP_PIN_LSB _u(24)
+#define PIO_SM3_EXECCTRL_JMP_PIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_OUT_EN_SEL
+// Description : Which data bit to use for inline OUT enable
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_RESET _u(0x00)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_BITS _u(0x00f80000)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_MSB _u(23)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_LSB _u(19)
+#define PIO_SM3_EXECCTRL_OUT_EN_SEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_INLINE_OUT_EN
+// Description : If 1, use a bit of OUT data as an auxiliary write enable
+// When used in conjunction with OUT_STICKY, writes with an enable
+// of 0 will
+// deassert the latest pin write. This can create useful
+// masking/override behaviour
+// due to the priority ordering of state machine pin writes (SM0 <
+// SM1 < ...)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_BITS _u(0x00040000)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_MSB _u(18)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_LSB _u(18)
+#define PIO_SM3_EXECCTRL_INLINE_OUT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_OUT_STICKY
+// Description : Continuously assert the most recent OUT/SET to the pins
+#define PIO_SM3_EXECCTRL_OUT_STICKY_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_BITS _u(0x00020000)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_MSB _u(17)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_LSB _u(17)
+#define PIO_SM3_EXECCTRL_OUT_STICKY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_WRAP_TOP
+// Description : After reaching this address, execution is wrapped to
+// wrap_bottom.
+// If the instruction is a jump, and the jump condition is true,
+// the jump takes priority.
+#define PIO_SM3_EXECCTRL_WRAP_TOP_RESET _u(0x1f)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_BITS _u(0x0001f000)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_MSB _u(16)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_LSB _u(12)
+#define PIO_SM3_EXECCTRL_WRAP_TOP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_WRAP_BOTTOM
+// Description : After reaching wrap_top, execution is wrapped to this address.
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_RESET _u(0x00)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_BITS _u(0x00000f80)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_MSB _u(11)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_LSB _u(7)
+#define PIO_SM3_EXECCTRL_WRAP_BOTTOM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_STATUS_SEL
+// Description : Comparison used for the MOV x, STATUS instruction.
+// 0x0 -> All-ones if TX FIFO level < N, otherwise all-zeroes
+// 0x1 -> All-ones if RX FIFO level < N, otherwise all-zeroes
+#define PIO_SM3_EXECCTRL_STATUS_SEL_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_BITS _u(0x00000010)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_MSB _u(4)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_LSB _u(4)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_ACCESS "RW"
+#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_TXLEVEL _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_SEL_VALUE_RXLEVEL _u(0x1)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_EXECCTRL_STATUS_N
+// Description : Comparison level for the MOV x, STATUS instruction
+#define PIO_SM3_EXECCTRL_STATUS_N_RESET _u(0x0)
+#define PIO_SM3_EXECCTRL_STATUS_N_BITS _u(0x0000000f)
+#define PIO_SM3_EXECCTRL_STATUS_N_MSB _u(3)
+#define PIO_SM3_EXECCTRL_STATUS_N_LSB _u(0)
+#define PIO_SM3_EXECCTRL_STATUS_N_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM3_SHIFTCTRL
+// Description : Control behaviour of the input/output shift registers for state
+// machine 3
+#define PIO_SM3_SHIFTCTRL_OFFSET _u(0x00000118)
+#define PIO_SM3_SHIFTCTRL_BITS _u(0xffff0000)
+#define PIO_SM3_SHIFTCTRL_RESET _u(0x000c0000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_FJOIN_RX
+// Description : When 1, RX FIFO steals the TX FIFO's storage, and becomes twice
+// as deep.
+// TX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_BITS _u(0x80000000)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_MSB _u(31)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_LSB _u(31)
+#define PIO_SM3_SHIFTCTRL_FJOIN_RX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_FJOIN_TX
+// Description : When 1, TX FIFO steals the RX FIFO's storage, and becomes twice
+// as deep.
+// RX FIFO is disabled as a result (always reads as both full and
+// empty).
+// FIFOs are flushed when this bit is changed.
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_BITS _u(0x40000000)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_MSB _u(30)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_LSB _u(30)
+#define PIO_SM3_SHIFTCTRL_FJOIN_TX_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_PULL_THRESH
+// Description : Number of bits shifted out of OSR before autopull, or
+// conditional pull (PULL IFEMPTY), will take place.
+// Write 0 for value of 32.
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_RESET _u(0x00)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_BITS _u(0x3e000000)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_MSB _u(29)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_LSB _u(25)
+#define PIO_SM3_SHIFTCTRL_PULL_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_PUSH_THRESH
+// Description : Number of bits shifted into ISR before autopush, or conditional
+// push (PUSH IFFULL), will take place.
+// Write 0 for value of 32.
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_RESET _u(0x00)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_BITS _u(0x01f00000)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_MSB _u(24)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_LSB _u(20)
+#define PIO_SM3_SHIFTCTRL_PUSH_THRESH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR
+// Description : 1 = shift out of output shift register to right. 0 = to left.
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_BITS _u(0x00080000)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_MSB _u(19)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_LSB _u(19)
+#define PIO_SM3_SHIFTCTRL_OUT_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_IN_SHIFTDIR
+// Description : 1 = shift input shift register to right (data enters from
+// left). 0 = to left.
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_RESET _u(0x1)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_BITS _u(0x00040000)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_MSB _u(18)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_LSB _u(18)
+#define PIO_SM3_SHIFTCTRL_IN_SHIFTDIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_AUTOPULL
+// Description : Pull automatically when the output shift register is emptied,
+// i.e. on or following an OUT instruction which causes the output
+// shift counter to reach or exceed PULL_THRESH.
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_BITS _u(0x00020000)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_MSB _u(17)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_LSB _u(17)
+#define PIO_SM3_SHIFTCTRL_AUTOPULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_SHIFTCTRL_AUTOPUSH
+// Description : Push automatically when the input shift register is filled,
+// i.e. on an IN instruction which causes the input shift counter
+// to reach or exceed PUSH_THRESH.
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_RESET _u(0x0)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_BITS _u(0x00010000)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_MSB _u(16)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_LSB _u(16)
+#define PIO_SM3_SHIFTCTRL_AUTOPUSH_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM3_ADDR
+// Description : Current instruction address of state machine 3
+#define PIO_SM3_ADDR_OFFSET _u(0x0000011c)
+#define PIO_SM3_ADDR_BITS _u(0x0000001f)
+#define PIO_SM3_ADDR_RESET _u(0x00000000)
+#define PIO_SM3_ADDR_MSB _u(4)
+#define PIO_SM3_ADDR_LSB _u(0)
+#define PIO_SM3_ADDR_ACCESS "RO"
+// =============================================================================
+// Register : PIO_SM3_INSTR
+// Description : Read to see the instruction currently addressed by state
+// machine 3's program counter
+// Write to execute an instruction immediately (including jumps)
+// and then resume execution.
+#define PIO_SM3_INSTR_OFFSET _u(0x00000120)
+#define PIO_SM3_INSTR_BITS _u(0x0000ffff)
+#define PIO_SM3_INSTR_RESET "-"
+#define PIO_SM3_INSTR_MSB _u(15)
+#define PIO_SM3_INSTR_LSB _u(0)
+#define PIO_SM3_INSTR_ACCESS "RW"
+// =============================================================================
+// Register : PIO_SM3_PINCTRL
+// Description : State machine pin control
+#define PIO_SM3_PINCTRL_OFFSET _u(0x00000124)
+#define PIO_SM3_PINCTRL_BITS _u(0xffffffff)
+#define PIO_SM3_PINCTRL_RESET _u(0x14000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_PINCTRL_SIDESET_COUNT
+// Description : The number of MSBs of the Delay/Side-set instruction field
+// which are used for side-set. Inclusive of the enable bit, if
+// present. Minimum of 0 (all delay bits, no side-set) and maximum
+// of 5 (all side-set, no delay).
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_RESET _u(0x0)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_BITS _u(0xe0000000)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_MSB _u(31)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_LSB _u(29)
+#define PIO_SM3_PINCTRL_SIDESET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_PINCTRL_SET_COUNT
+// Description : The number of pins asserted by a SET. In the range 0 to 5
+// inclusive.
+#define PIO_SM3_PINCTRL_SET_COUNT_RESET _u(0x5)
+#define PIO_SM3_PINCTRL_SET_COUNT_BITS _u(0x1c000000)
+#define PIO_SM3_PINCTRL_SET_COUNT_MSB _u(28)
+#define PIO_SM3_PINCTRL_SET_COUNT_LSB _u(26)
+#define PIO_SM3_PINCTRL_SET_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_PINCTRL_OUT_COUNT
+// Description : The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV
+// PINS instruction. In the range 0 to 32 inclusive.
+#define PIO_SM3_PINCTRL_OUT_COUNT_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_OUT_COUNT_BITS _u(0x03f00000)
+#define PIO_SM3_PINCTRL_OUT_COUNT_MSB _u(25)
+#define PIO_SM3_PINCTRL_OUT_COUNT_LSB _u(20)
+#define PIO_SM3_PINCTRL_OUT_COUNT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_PINCTRL_IN_BASE
+// Description : The pin which is mapped to the least-significant bit of a state
+// machine's IN data bus. Higher-numbered pins are mapped to
+// consecutively more-significant data bits, with a modulo of 32
+// applied to pin number.
+#define PIO_SM3_PINCTRL_IN_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_IN_BASE_BITS _u(0x000f8000)
+#define PIO_SM3_PINCTRL_IN_BASE_MSB _u(19)
+#define PIO_SM3_PINCTRL_IN_BASE_LSB _u(15)
+#define PIO_SM3_PINCTRL_IN_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_PINCTRL_SIDESET_BASE
+// Description : The lowest-numbered pin that will be affected by a side-set
+// operation. The MSBs of an instruction's side-set/delay field
+// (up to 5, determined by SIDESET_COUNT) are used for side-set
+// data, with the remaining LSBs used for delay. The
+// least-significant bit of the side-set portion is the bit
+// written to this pin, with more-significant bits written to
+// higher-numbered pins.
+#define PIO_SM3_PINCTRL_SIDESET_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_BITS _u(0x00007c00)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_MSB _u(14)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_LSB _u(10)
+#define PIO_SM3_PINCTRL_SIDESET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_PINCTRL_SET_BASE
+// Description : The lowest-numbered pin that will be affected by a SET PINS or
+// SET PINDIRS instruction. The data written to this pin is the
+// least-significant bit of the SET data.
+#define PIO_SM3_PINCTRL_SET_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_SET_BASE_BITS _u(0x000003e0)
+#define PIO_SM3_PINCTRL_SET_BASE_MSB _u(9)
+#define PIO_SM3_PINCTRL_SET_BASE_LSB _u(5)
+#define PIO_SM3_PINCTRL_SET_BASE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_SM3_PINCTRL_OUT_BASE
+// Description : The lowest-numbered pin that will be affected by an OUT PINS,
+// OUT PINDIRS or MOV PINS instruction. The data written to this
+// pin will always be the least-significant bit of the OUT or MOV
+// data.
+#define PIO_SM3_PINCTRL_OUT_BASE_RESET _u(0x00)
+#define PIO_SM3_PINCTRL_OUT_BASE_BITS _u(0x0000001f)
+#define PIO_SM3_PINCTRL_OUT_BASE_MSB _u(4)
+#define PIO_SM3_PINCTRL_OUT_BASE_LSB _u(0)
+#define PIO_SM3_PINCTRL_OUT_BASE_ACCESS "RW"
+// =============================================================================
+// Register : PIO_INTR
+// Description : Raw Interrupts
+#define PIO_INTR_OFFSET _u(0x00000128)
+#define PIO_INTR_BITS _u(0x00000fff)
+#define PIO_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM3
+// Description : None
+#define PIO_INTR_SM3_RESET _u(0x0)
+#define PIO_INTR_SM3_BITS _u(0x00000800)
+#define PIO_INTR_SM3_MSB _u(11)
+#define PIO_INTR_SM3_LSB _u(11)
+#define PIO_INTR_SM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM2
+// Description : None
+#define PIO_INTR_SM2_RESET _u(0x0)
+#define PIO_INTR_SM2_BITS _u(0x00000400)
+#define PIO_INTR_SM2_MSB _u(10)
+#define PIO_INTR_SM2_LSB _u(10)
+#define PIO_INTR_SM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM1
+// Description : None
+#define PIO_INTR_SM1_RESET _u(0x0)
+#define PIO_INTR_SM1_BITS _u(0x00000200)
+#define PIO_INTR_SM1_MSB _u(9)
+#define PIO_INTR_SM1_LSB _u(9)
+#define PIO_INTR_SM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM0
+// Description : None
+#define PIO_INTR_SM0_RESET _u(0x0)
+#define PIO_INTR_SM0_BITS _u(0x00000100)
+#define PIO_INTR_SM0_MSB _u(8)
+#define PIO_INTR_SM0_LSB _u(8)
+#define PIO_INTR_SM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM3_TXNFULL
+// Description : None
+#define PIO_INTR_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_INTR_SM3_TXNFULL_MSB _u(7)
+#define PIO_INTR_SM3_TXNFULL_LSB _u(7)
+#define PIO_INTR_SM3_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM2_TXNFULL
+// Description : None
+#define PIO_INTR_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_INTR_SM2_TXNFULL_MSB _u(6)
+#define PIO_INTR_SM2_TXNFULL_LSB _u(6)
+#define PIO_INTR_SM2_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM1_TXNFULL
+// Description : None
+#define PIO_INTR_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_INTR_SM1_TXNFULL_MSB _u(5)
+#define PIO_INTR_SM1_TXNFULL_LSB _u(5)
+#define PIO_INTR_SM1_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM0_TXNFULL
+// Description : None
+#define PIO_INTR_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_INTR_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_INTR_SM0_TXNFULL_MSB _u(4)
+#define PIO_INTR_SM0_TXNFULL_LSB _u(4)
+#define PIO_INTR_SM0_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM3_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_INTR_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_INTR_SM3_RXNEMPTY_LSB _u(3)
+#define PIO_INTR_SM3_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM2_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_INTR_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_INTR_SM2_RXNEMPTY_LSB _u(2)
+#define PIO_INTR_SM2_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM1_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_INTR_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_INTR_SM1_RXNEMPTY_LSB _u(1)
+#define PIO_INTR_SM1_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_INTR_SM0_RXNEMPTY
+// Description : None
+#define PIO_INTR_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_INTR_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_INTR_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_INTR_SM0_RXNEMPTY_LSB _u(0)
+#define PIO_INTR_SM0_RXNEMPTY_ACCESS "RO"
+// =============================================================================
+// Register : PIO_IRQ0_INTE
+// Description : Interrupt Enable for irq0
+#define PIO_IRQ0_INTE_OFFSET _u(0x0000012c)
+#define PIO_IRQ0_INTE_BITS _u(0x00000fff)
+#define PIO_IRQ0_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM3
+// Description : None
+#define PIO_IRQ0_INTE_SM3_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM3_BITS _u(0x00000800)
+#define PIO_IRQ0_INTE_SM3_MSB _u(11)
+#define PIO_IRQ0_INTE_SM3_LSB _u(11)
+#define PIO_IRQ0_INTE_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM2
+// Description : None
+#define PIO_IRQ0_INTE_SM2_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM2_BITS _u(0x00000400)
+#define PIO_IRQ0_INTE_SM2_MSB _u(10)
+#define PIO_IRQ0_INTE_SM2_LSB _u(10)
+#define PIO_IRQ0_INTE_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM1
+// Description : None
+#define PIO_IRQ0_INTE_SM1_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM1_BITS _u(0x00000200)
+#define PIO_IRQ0_INTE_SM1_MSB _u(9)
+#define PIO_IRQ0_INTE_SM1_LSB _u(9)
+#define PIO_IRQ0_INTE_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM0
+// Description : None
+#define PIO_IRQ0_INTE_SM0_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM0_BITS _u(0x00000100)
+#define PIO_IRQ0_INTE_SM0_MSB _u(8)
+#define PIO_IRQ0_INTE_SM0_LSB _u(8)
+#define PIO_IRQ0_INTE_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_LSB _u(7)
+#define PIO_IRQ0_INTE_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_LSB _u(6)
+#define PIO_IRQ0_INTE_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_LSB _u(5)
+#define PIO_IRQ0_INTE_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTE_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_LSB _u(4)
+#define PIO_IRQ0_INTE_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_LSB _u(3)
+#define PIO_IRQ0_INTE_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_LSB _u(2)
+#define PIO_IRQ0_INTE_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_LSB _u(1)
+#define PIO_IRQ0_INTE_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTE_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_LSB _u(0)
+#define PIO_IRQ0_INTE_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register : PIO_IRQ0_INTF
+// Description : Interrupt Force for irq0
+#define PIO_IRQ0_INTF_OFFSET _u(0x00000130)
+#define PIO_IRQ0_INTF_BITS _u(0x00000fff)
+#define PIO_IRQ0_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM3
+// Description : None
+#define PIO_IRQ0_INTF_SM3_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM3_BITS _u(0x00000800)
+#define PIO_IRQ0_INTF_SM3_MSB _u(11)
+#define PIO_IRQ0_INTF_SM3_LSB _u(11)
+#define PIO_IRQ0_INTF_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM2
+// Description : None
+#define PIO_IRQ0_INTF_SM2_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM2_BITS _u(0x00000400)
+#define PIO_IRQ0_INTF_SM2_MSB _u(10)
+#define PIO_IRQ0_INTF_SM2_LSB _u(10)
+#define PIO_IRQ0_INTF_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM1
+// Description : None
+#define PIO_IRQ0_INTF_SM1_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM1_BITS _u(0x00000200)
+#define PIO_IRQ0_INTF_SM1_MSB _u(9)
+#define PIO_IRQ0_INTF_SM1_LSB _u(9)
+#define PIO_IRQ0_INTF_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM0
+// Description : None
+#define PIO_IRQ0_INTF_SM0_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM0_BITS _u(0x00000100)
+#define PIO_IRQ0_INTF_SM0_MSB _u(8)
+#define PIO_IRQ0_INTF_SM0_LSB _u(8)
+#define PIO_IRQ0_INTF_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_LSB _u(7)
+#define PIO_IRQ0_INTF_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_LSB _u(6)
+#define PIO_IRQ0_INTF_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_LSB _u(5)
+#define PIO_IRQ0_INTF_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTF_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_LSB _u(4)
+#define PIO_IRQ0_INTF_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_LSB _u(3)
+#define PIO_IRQ0_INTF_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_LSB _u(2)
+#define PIO_IRQ0_INTF_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_LSB _u(1)
+#define PIO_IRQ0_INTF_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTF_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_LSB _u(0)
+#define PIO_IRQ0_INTF_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register : PIO_IRQ0_INTS
+// Description : Interrupt status after masking & forcing for irq0
+#define PIO_IRQ0_INTS_OFFSET _u(0x00000134)
+#define PIO_IRQ0_INTS_BITS _u(0x00000fff)
+#define PIO_IRQ0_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM3
+// Description : None
+#define PIO_IRQ0_INTS_SM3_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM3_BITS _u(0x00000800)
+#define PIO_IRQ0_INTS_SM3_MSB _u(11)
+#define PIO_IRQ0_INTS_SM3_LSB _u(11)
+#define PIO_IRQ0_INTS_SM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM2
+// Description : None
+#define PIO_IRQ0_INTS_SM2_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM2_BITS _u(0x00000400)
+#define PIO_IRQ0_INTS_SM2_MSB _u(10)
+#define PIO_IRQ0_INTS_SM2_LSB _u(10)
+#define PIO_IRQ0_INTS_SM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM1
+// Description : None
+#define PIO_IRQ0_INTS_SM1_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM1_BITS _u(0x00000200)
+#define PIO_IRQ0_INTS_SM1_MSB _u(9)
+#define PIO_IRQ0_INTS_SM1_LSB _u(9)
+#define PIO_IRQ0_INTS_SM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM0
+// Description : None
+#define PIO_IRQ0_INTS_SM0_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM0_BITS _u(0x00000100)
+#define PIO_IRQ0_INTS_SM0_MSB _u(8)
+#define PIO_IRQ0_INTS_SM0_LSB _u(8)
+#define PIO_IRQ0_INTS_SM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_LSB _u(7)
+#define PIO_IRQ0_INTS_SM3_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_LSB _u(6)
+#define PIO_IRQ0_INTS_SM2_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_LSB _u(5)
+#define PIO_IRQ0_INTS_SM1_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ0_INTS_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_LSB _u(4)
+#define PIO_IRQ0_INTS_SM0_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_LSB _u(3)
+#define PIO_IRQ0_INTS_SM3_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_LSB _u(2)
+#define PIO_IRQ0_INTS_SM2_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_LSB _u(1)
+#define PIO_IRQ0_INTS_SM1_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ0_INTS_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_LSB _u(0)
+#define PIO_IRQ0_INTS_SM0_RXNEMPTY_ACCESS "RO"
+// =============================================================================
+// Register : PIO_IRQ1_INTE
+// Description : Interrupt Enable for irq1
+#define PIO_IRQ1_INTE_OFFSET _u(0x00000138)
+#define PIO_IRQ1_INTE_BITS _u(0x00000fff)
+#define PIO_IRQ1_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM3
+// Description : None
+#define PIO_IRQ1_INTE_SM3_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM3_BITS _u(0x00000800)
+#define PIO_IRQ1_INTE_SM3_MSB _u(11)
+#define PIO_IRQ1_INTE_SM3_LSB _u(11)
+#define PIO_IRQ1_INTE_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM2
+// Description : None
+#define PIO_IRQ1_INTE_SM2_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM2_BITS _u(0x00000400)
+#define PIO_IRQ1_INTE_SM2_MSB _u(10)
+#define PIO_IRQ1_INTE_SM2_LSB _u(10)
+#define PIO_IRQ1_INTE_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM1
+// Description : None
+#define PIO_IRQ1_INTE_SM1_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM1_BITS _u(0x00000200)
+#define PIO_IRQ1_INTE_SM1_MSB _u(9)
+#define PIO_IRQ1_INTE_SM1_LSB _u(9)
+#define PIO_IRQ1_INTE_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM0
+// Description : None
+#define PIO_IRQ1_INTE_SM0_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM0_BITS _u(0x00000100)
+#define PIO_IRQ1_INTE_SM0_MSB _u(8)
+#define PIO_IRQ1_INTE_SM0_LSB _u(8)
+#define PIO_IRQ1_INTE_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_LSB _u(7)
+#define PIO_IRQ1_INTE_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_LSB _u(6)
+#define PIO_IRQ1_INTE_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_LSB _u(5)
+#define PIO_IRQ1_INTE_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTE_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_LSB _u(4)
+#define PIO_IRQ1_INTE_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_LSB _u(3)
+#define PIO_IRQ1_INTE_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_LSB _u(2)
+#define PIO_IRQ1_INTE_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_LSB _u(1)
+#define PIO_IRQ1_INTE_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTE_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_LSB _u(0)
+#define PIO_IRQ1_INTE_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register : PIO_IRQ1_INTF
+// Description : Interrupt Force for irq1
+#define PIO_IRQ1_INTF_OFFSET _u(0x0000013c)
+#define PIO_IRQ1_INTF_BITS _u(0x00000fff)
+#define PIO_IRQ1_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM3
+// Description : None
+#define PIO_IRQ1_INTF_SM3_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM3_BITS _u(0x00000800)
+#define PIO_IRQ1_INTF_SM3_MSB _u(11)
+#define PIO_IRQ1_INTF_SM3_LSB _u(11)
+#define PIO_IRQ1_INTF_SM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM2
+// Description : None
+#define PIO_IRQ1_INTF_SM2_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM2_BITS _u(0x00000400)
+#define PIO_IRQ1_INTF_SM2_MSB _u(10)
+#define PIO_IRQ1_INTF_SM2_LSB _u(10)
+#define PIO_IRQ1_INTF_SM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM1
+// Description : None
+#define PIO_IRQ1_INTF_SM1_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM1_BITS _u(0x00000200)
+#define PIO_IRQ1_INTF_SM1_MSB _u(9)
+#define PIO_IRQ1_INTF_SM1_LSB _u(9)
+#define PIO_IRQ1_INTF_SM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM0
+// Description : None
+#define PIO_IRQ1_INTF_SM0_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM0_BITS _u(0x00000100)
+#define PIO_IRQ1_INTF_SM0_MSB _u(8)
+#define PIO_IRQ1_INTF_SM0_LSB _u(8)
+#define PIO_IRQ1_INTF_SM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_LSB _u(7)
+#define PIO_IRQ1_INTF_SM3_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_LSB _u(6)
+#define PIO_IRQ1_INTF_SM2_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_LSB _u(5)
+#define PIO_IRQ1_INTF_SM1_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTF_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_LSB _u(4)
+#define PIO_IRQ1_INTF_SM0_TXNFULL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_LSB _u(3)
+#define PIO_IRQ1_INTF_SM3_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_LSB _u(2)
+#define PIO_IRQ1_INTF_SM2_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_LSB _u(1)
+#define PIO_IRQ1_INTF_SM1_RXNEMPTY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTF_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_LSB _u(0)
+#define PIO_IRQ1_INTF_SM0_RXNEMPTY_ACCESS "RW"
+// =============================================================================
+// Register : PIO_IRQ1_INTS
+// Description : Interrupt status after masking & forcing for irq1
+#define PIO_IRQ1_INTS_OFFSET _u(0x00000140)
+#define PIO_IRQ1_INTS_BITS _u(0x00000fff)
+#define PIO_IRQ1_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM3
+// Description : None
+#define PIO_IRQ1_INTS_SM3_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM3_BITS _u(0x00000800)
+#define PIO_IRQ1_INTS_SM3_MSB _u(11)
+#define PIO_IRQ1_INTS_SM3_LSB _u(11)
+#define PIO_IRQ1_INTS_SM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM2
+// Description : None
+#define PIO_IRQ1_INTS_SM2_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM2_BITS _u(0x00000400)
+#define PIO_IRQ1_INTS_SM2_MSB _u(10)
+#define PIO_IRQ1_INTS_SM2_LSB _u(10)
+#define PIO_IRQ1_INTS_SM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM1
+// Description : None
+#define PIO_IRQ1_INTS_SM1_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM1_BITS _u(0x00000200)
+#define PIO_IRQ1_INTS_SM1_MSB _u(9)
+#define PIO_IRQ1_INTS_SM1_LSB _u(9)
+#define PIO_IRQ1_INTS_SM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM0
+// Description : None
+#define PIO_IRQ1_INTS_SM0_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM0_BITS _u(0x00000100)
+#define PIO_IRQ1_INTS_SM0_MSB _u(8)
+#define PIO_IRQ1_INTS_SM0_LSB _u(8)
+#define PIO_IRQ1_INTS_SM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM3_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM3_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_BITS _u(0x00000080)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_MSB _u(7)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_LSB _u(7)
+#define PIO_IRQ1_INTS_SM3_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM2_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM2_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_BITS _u(0x00000040)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_MSB _u(6)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_LSB _u(6)
+#define PIO_IRQ1_INTS_SM2_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM1_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM1_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_BITS _u(0x00000020)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_MSB _u(5)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_LSB _u(5)
+#define PIO_IRQ1_INTS_SM1_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM0_TXNFULL
+// Description : None
+#define PIO_IRQ1_INTS_SM0_TXNFULL_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_BITS _u(0x00000010)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_MSB _u(4)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_LSB _u(4)
+#define PIO_IRQ1_INTS_SM0_TXNFULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM3_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_BITS _u(0x00000008)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_MSB _u(3)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_LSB _u(3)
+#define PIO_IRQ1_INTS_SM3_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM2_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_BITS _u(0x00000004)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_MSB _u(2)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_LSB _u(2)
+#define PIO_IRQ1_INTS_SM2_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM1_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_BITS _u(0x00000002)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_MSB _u(1)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_LSB _u(1)
+#define PIO_IRQ1_INTS_SM1_RXNEMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PIO_IRQ1_INTS_SM0_RXNEMPTY
+// Description : None
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_RESET _u(0x0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_BITS _u(0x00000001)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_MSB _u(0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_LSB _u(0)
+#define PIO_IRQ1_INTS_SM0_RXNEMPTY_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_PIO_DEFINED
diff --git a/arkanoid/pico/hardware/regs/pll.h b/arkanoid/pico/hardware/regs/pll.h
new file mode 100644
index 0000000..a0f5ad0
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/pll.h
@@ -0,0 +1,135 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PLL
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PLL_DEFINED
+#define HARDWARE_REGS_PLL_DEFINED
+// =============================================================================
+// Register : PLL_CS
+// Description : Control and Status
+// GENERAL CONSTRAINTS:
+// Reference clock frequency min=5MHz, max=800MHz
+// Feedback divider min=16, max=320
+// VCO frequency min=400MHz, max=1600MHz
+#define PLL_CS_OFFSET _u(0x00000000)
+#define PLL_CS_BITS _u(0x8000013f)
+#define PLL_CS_RESET _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field : PLL_CS_LOCK
+// Description : PLL is locked
+#define PLL_CS_LOCK_RESET _u(0x0)
+#define PLL_CS_LOCK_BITS _u(0x80000000)
+#define PLL_CS_LOCK_MSB _u(31)
+#define PLL_CS_LOCK_LSB _u(31)
+#define PLL_CS_LOCK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PLL_CS_BYPASS
+// Description : Passes the reference clock to the output instead of the divided
+// VCO. The VCO continues to run so the user can switch between
+// the reference clock and the divided VCO but the output will
+// glitch when doing so.
+#define PLL_CS_BYPASS_RESET _u(0x0)
+#define PLL_CS_BYPASS_BITS _u(0x00000100)
+#define PLL_CS_BYPASS_MSB _u(8)
+#define PLL_CS_BYPASS_LSB _u(8)
+#define PLL_CS_BYPASS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PLL_CS_REFDIV
+// Description : Divides the PLL input reference clock.
+// Behaviour is undefined for div=0.
+// PLL output will be unpredictable during refdiv changes, wait
+// for lock=1 before using it.
+#define PLL_CS_REFDIV_RESET _u(0x01)
+#define PLL_CS_REFDIV_BITS _u(0x0000003f)
+#define PLL_CS_REFDIV_MSB _u(5)
+#define PLL_CS_REFDIV_LSB _u(0)
+#define PLL_CS_REFDIV_ACCESS "RW"
+// =============================================================================
+// Register : PLL_PWR
+// Description : Controls the PLL power modes.
+#define PLL_PWR_OFFSET _u(0x00000004)
+#define PLL_PWR_BITS _u(0x0000002d)
+#define PLL_PWR_RESET _u(0x0000002d)
+// -----------------------------------------------------------------------------
+// Field : PLL_PWR_VCOPD
+// Description : PLL VCO powerdown
+// To save power set high when PLL output not required or
+// bypass=1.
+#define PLL_PWR_VCOPD_RESET _u(0x1)
+#define PLL_PWR_VCOPD_BITS _u(0x00000020)
+#define PLL_PWR_VCOPD_MSB _u(5)
+#define PLL_PWR_VCOPD_LSB _u(5)
+#define PLL_PWR_VCOPD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PLL_PWR_POSTDIVPD
+// Description : PLL post divider powerdown
+// To save power set high when PLL output not required or
+// bypass=1.
+#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
+#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
+#define PLL_PWR_POSTDIVPD_MSB _u(3)
+#define PLL_PWR_POSTDIVPD_LSB _u(3)
+#define PLL_PWR_POSTDIVPD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PLL_PWR_DSMPD
+// Description : PLL DSM powerdown
+// Nothing is achieved by setting this low.
+#define PLL_PWR_DSMPD_RESET _u(0x1)
+#define PLL_PWR_DSMPD_BITS _u(0x00000004)
+#define PLL_PWR_DSMPD_MSB _u(2)
+#define PLL_PWR_DSMPD_LSB _u(2)
+#define PLL_PWR_DSMPD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PLL_PWR_PD
+// Description : PLL powerdown
+// To save power set high when PLL output not required.
+#define PLL_PWR_PD_RESET _u(0x1)
+#define PLL_PWR_PD_BITS _u(0x00000001)
+#define PLL_PWR_PD_MSB _u(0)
+#define PLL_PWR_PD_LSB _u(0)
+#define PLL_PWR_PD_ACCESS "RW"
+// =============================================================================
+// Register : PLL_FBDIV_INT
+// Description : Feedback divisor
+// (note: this PLL does not support fractional division)
+// see ctrl reg description for constraints
+#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
+#define PLL_FBDIV_INT_BITS _u(0x00000fff)
+#define PLL_FBDIV_INT_RESET _u(0x00000000)
+#define PLL_FBDIV_INT_MSB _u(11)
+#define PLL_FBDIV_INT_LSB _u(0)
+#define PLL_FBDIV_INT_ACCESS "RW"
+// =============================================================================
+// Register : PLL_PRIM
+// Description : Controls the PLL post dividers for the primary output
+// (note: this PLL does not have a secondary output)
+// the primary output is driven from VCO divided by
+// postdiv1*postdiv2
+#define PLL_PRIM_OFFSET _u(0x0000000c)
+#define PLL_PRIM_BITS _u(0x00077000)
+#define PLL_PRIM_RESET _u(0x00077000)
+// -----------------------------------------------------------------------------
+// Field : PLL_PRIM_POSTDIV1
+// Description : divide by 1-7
+#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
+#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
+#define PLL_PRIM_POSTDIV1_MSB _u(18)
+#define PLL_PRIM_POSTDIV1_LSB _u(16)
+#define PLL_PRIM_POSTDIV1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PLL_PRIM_POSTDIV2
+// Description : divide by 1-7
+#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
+#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
+#define PLL_PRIM_POSTDIV2_MSB _u(14)
+#define PLL_PRIM_POSTDIV2_LSB _u(12)
+#define PLL_PRIM_POSTDIV2_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_PLL_DEFINED
diff --git a/arkanoid/pico/hardware/regs/psm.h b/arkanoid/pico/hardware/regs/psm.h
new file mode 100644
index 0000000..8810ae8
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/psm.h
@@ -0,0 +1,584 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PSM
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PSM_DEFINED
+#define HARDWARE_REGS_PSM_DEFINED
+// =============================================================================
+// Register : PSM_FRCE_ON
+// Description : Force block out of reset (i.e. power it on)
+#define PSM_FRCE_ON_OFFSET _u(0x00000000)
+#define PSM_FRCE_ON_BITS _u(0x0001ffff)
+#define PSM_FRCE_ON_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_PROC1
+// Description : None
+#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
+#define PSM_FRCE_ON_PROC1_BITS _u(0x00010000)
+#define PSM_FRCE_ON_PROC1_MSB _u(16)
+#define PSM_FRCE_ON_PROC1_LSB _u(16)
+#define PSM_FRCE_ON_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_PROC0
+// Description : None
+#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
+#define PSM_FRCE_ON_PROC0_BITS _u(0x00008000)
+#define PSM_FRCE_ON_PROC0_MSB _u(15)
+#define PSM_FRCE_ON_PROC0_LSB _u(15)
+#define PSM_FRCE_ON_PROC0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_SIO
+// Description : None
+#define PSM_FRCE_ON_SIO_RESET _u(0x0)
+#define PSM_FRCE_ON_SIO_BITS _u(0x00004000)
+#define PSM_FRCE_ON_SIO_MSB _u(14)
+#define PSM_FRCE_ON_SIO_LSB _u(14)
+#define PSM_FRCE_ON_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_LSB _u(13)
+#define PSM_FRCE_ON_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_XIP
+// Description : None
+#define PSM_FRCE_ON_XIP_RESET _u(0x0)
+#define PSM_FRCE_ON_XIP_BITS _u(0x00001000)
+#define PSM_FRCE_ON_XIP_MSB _u(12)
+#define PSM_FRCE_ON_XIP_LSB _u(12)
+#define PSM_FRCE_ON_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_SRAM5
+// Description : None
+#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM5_BITS _u(0x00000800)
+#define PSM_FRCE_ON_SRAM5_MSB _u(11)
+#define PSM_FRCE_ON_SRAM5_LSB _u(11)
+#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_SRAM4
+// Description : None
+#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM4_BITS _u(0x00000400)
+#define PSM_FRCE_ON_SRAM4_MSB _u(10)
+#define PSM_FRCE_ON_SRAM4_LSB _u(10)
+#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_SRAM3
+// Description : None
+#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM3_BITS _u(0x00000200)
+#define PSM_FRCE_ON_SRAM3_MSB _u(9)
+#define PSM_FRCE_ON_SRAM3_LSB _u(9)
+#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_SRAM2
+// Description : None
+#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM2_BITS _u(0x00000100)
+#define PSM_FRCE_ON_SRAM2_MSB _u(8)
+#define PSM_FRCE_ON_SRAM2_LSB _u(8)
+#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_SRAM1
+// Description : None
+#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000080)
+#define PSM_FRCE_ON_SRAM1_MSB _u(7)
+#define PSM_FRCE_ON_SRAM1_LSB _u(7)
+#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_SRAM0
+// Description : None
+#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
+#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000040)
+#define PSM_FRCE_ON_SRAM0_MSB _u(6)
+#define PSM_FRCE_ON_SRAM0_LSB _u(6)
+#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_ROM
+// Description : None
+#define PSM_FRCE_ON_ROM_RESET _u(0x0)
+#define PSM_FRCE_ON_ROM_BITS _u(0x00000020)
+#define PSM_FRCE_ON_ROM_MSB _u(5)
+#define PSM_FRCE_ON_ROM_LSB _u(5)
+#define PSM_FRCE_ON_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_BUSFABRIC
+// Description : None
+#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
+#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_FRCE_ON_BUSFABRIC_MSB _u(4)
+#define PSM_FRCE_ON_BUSFABRIC_LSB _u(4)
+#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_RESETS
+// Description : None
+#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
+#define PSM_FRCE_ON_RESETS_BITS _u(0x00000008)
+#define PSM_FRCE_ON_RESETS_MSB _u(3)
+#define PSM_FRCE_ON_RESETS_LSB _u(3)
+#define PSM_FRCE_ON_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_CLOCKS
+// Description : None
+#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
+#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000004)
+#define PSM_FRCE_ON_CLOCKS_MSB _u(2)
+#define PSM_FRCE_ON_CLOCKS_LSB _u(2)
+#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_XOSC
+// Description : None
+#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
+#define PSM_FRCE_ON_XOSC_BITS _u(0x00000002)
+#define PSM_FRCE_ON_XOSC_MSB _u(1)
+#define PSM_FRCE_ON_XOSC_LSB _u(1)
+#define PSM_FRCE_ON_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_ON_ROSC
+// Description : None
+#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
+#define PSM_FRCE_ON_ROSC_BITS _u(0x00000001)
+#define PSM_FRCE_ON_ROSC_MSB _u(0)
+#define PSM_FRCE_ON_ROSC_LSB _u(0)
+#define PSM_FRCE_ON_ROSC_ACCESS "RW"
+// =============================================================================
+// Register : PSM_FRCE_OFF
+// Description : Force into reset (i.e. power it off)
+#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
+#define PSM_FRCE_OFF_BITS _u(0x0001ffff)
+#define PSM_FRCE_OFF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_PROC1
+// Description : None
+#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
+#define PSM_FRCE_OFF_PROC1_BITS _u(0x00010000)
+#define PSM_FRCE_OFF_PROC1_MSB _u(16)
+#define PSM_FRCE_OFF_PROC1_LSB _u(16)
+#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_PROC0
+// Description : None
+#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
+#define PSM_FRCE_OFF_PROC0_BITS _u(0x00008000)
+#define PSM_FRCE_OFF_PROC0_MSB _u(15)
+#define PSM_FRCE_OFF_PROC0_LSB _u(15)
+#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_SIO
+// Description : None
+#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
+#define PSM_FRCE_OFF_SIO_BITS _u(0x00004000)
+#define PSM_FRCE_OFF_SIO_MSB _u(14)
+#define PSM_FRCE_OFF_SIO_LSB _u(14)
+#define PSM_FRCE_OFF_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_LSB _u(13)
+#define PSM_FRCE_OFF_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_XIP
+// Description : None
+#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
+#define PSM_FRCE_OFF_XIP_BITS _u(0x00001000)
+#define PSM_FRCE_OFF_XIP_MSB _u(12)
+#define PSM_FRCE_OFF_XIP_LSB _u(12)
+#define PSM_FRCE_OFF_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_SRAM5
+// Description : None
+#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00000800)
+#define PSM_FRCE_OFF_SRAM5_MSB _u(11)
+#define PSM_FRCE_OFF_SRAM5_LSB _u(11)
+#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_SRAM4
+// Description : None
+#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00000400)
+#define PSM_FRCE_OFF_SRAM4_MSB _u(10)
+#define PSM_FRCE_OFF_SRAM4_LSB _u(10)
+#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_SRAM3
+// Description : None
+#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00000200)
+#define PSM_FRCE_OFF_SRAM3_MSB _u(9)
+#define PSM_FRCE_OFF_SRAM3_LSB _u(9)
+#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_SRAM2
+// Description : None
+#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00000100)
+#define PSM_FRCE_OFF_SRAM2_MSB _u(8)
+#define PSM_FRCE_OFF_SRAM2_LSB _u(8)
+#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_SRAM1
+// Description : None
+#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000080)
+#define PSM_FRCE_OFF_SRAM1_MSB _u(7)
+#define PSM_FRCE_OFF_SRAM1_LSB _u(7)
+#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_SRAM0
+// Description : None
+#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
+#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000040)
+#define PSM_FRCE_OFF_SRAM0_MSB _u(6)
+#define PSM_FRCE_OFF_SRAM0_LSB _u(6)
+#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_ROM
+// Description : None
+#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
+#define PSM_FRCE_OFF_ROM_BITS _u(0x00000020)
+#define PSM_FRCE_OFF_ROM_MSB _u(5)
+#define PSM_FRCE_OFF_ROM_LSB _u(5)
+#define PSM_FRCE_OFF_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_BUSFABRIC
+// Description : None
+#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
+#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(4)
+#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(4)
+#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_RESETS
+// Description : None
+#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
+#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000008)
+#define PSM_FRCE_OFF_RESETS_MSB _u(3)
+#define PSM_FRCE_OFF_RESETS_LSB _u(3)
+#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_CLOCKS
+// Description : None
+#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
+#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000004)
+#define PSM_FRCE_OFF_CLOCKS_MSB _u(2)
+#define PSM_FRCE_OFF_CLOCKS_LSB _u(2)
+#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_XOSC
+// Description : None
+#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
+#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000002)
+#define PSM_FRCE_OFF_XOSC_MSB _u(1)
+#define PSM_FRCE_OFF_XOSC_LSB _u(1)
+#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_FRCE_OFF_ROSC
+// Description : None
+#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
+#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000001)
+#define PSM_FRCE_OFF_ROSC_MSB _u(0)
+#define PSM_FRCE_OFF_ROSC_LSB _u(0)
+#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
+// =============================================================================
+// Register : PSM_WDSEL
+// Description : Set to 1 if this peripheral should be reset when the watchdog
+// fires.
+#define PSM_WDSEL_OFFSET _u(0x00000008)
+#define PSM_WDSEL_BITS _u(0x0001ffff)
+#define PSM_WDSEL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_PROC1
+// Description : None
+#define PSM_WDSEL_PROC1_RESET _u(0x0)
+#define PSM_WDSEL_PROC1_BITS _u(0x00010000)
+#define PSM_WDSEL_PROC1_MSB _u(16)
+#define PSM_WDSEL_PROC1_LSB _u(16)
+#define PSM_WDSEL_PROC1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_PROC0
+// Description : None
+#define PSM_WDSEL_PROC0_RESET _u(0x0)
+#define PSM_WDSEL_PROC0_BITS _u(0x00008000)
+#define PSM_WDSEL_PROC0_MSB _u(15)
+#define PSM_WDSEL_PROC0_LSB _u(15)
+#define PSM_WDSEL_PROC0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_SIO
+// Description : None
+#define PSM_WDSEL_SIO_RESET _u(0x0)
+#define PSM_WDSEL_SIO_BITS _u(0x00004000)
+#define PSM_WDSEL_SIO_MSB _u(14)
+#define PSM_WDSEL_SIO_LSB _u(14)
+#define PSM_WDSEL_SIO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_LSB _u(13)
+#define PSM_WDSEL_VREG_AND_CHIP_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_XIP
+// Description : None
+#define PSM_WDSEL_XIP_RESET _u(0x0)
+#define PSM_WDSEL_XIP_BITS _u(0x00001000)
+#define PSM_WDSEL_XIP_MSB _u(12)
+#define PSM_WDSEL_XIP_LSB _u(12)
+#define PSM_WDSEL_XIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_SRAM5
+// Description : None
+#define PSM_WDSEL_SRAM5_RESET _u(0x0)
+#define PSM_WDSEL_SRAM5_BITS _u(0x00000800)
+#define PSM_WDSEL_SRAM5_MSB _u(11)
+#define PSM_WDSEL_SRAM5_LSB _u(11)
+#define PSM_WDSEL_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_SRAM4
+// Description : None
+#define PSM_WDSEL_SRAM4_RESET _u(0x0)
+#define PSM_WDSEL_SRAM4_BITS _u(0x00000400)
+#define PSM_WDSEL_SRAM4_MSB _u(10)
+#define PSM_WDSEL_SRAM4_LSB _u(10)
+#define PSM_WDSEL_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_SRAM3
+// Description : None
+#define PSM_WDSEL_SRAM3_RESET _u(0x0)
+#define PSM_WDSEL_SRAM3_BITS _u(0x00000200)
+#define PSM_WDSEL_SRAM3_MSB _u(9)
+#define PSM_WDSEL_SRAM3_LSB _u(9)
+#define PSM_WDSEL_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_SRAM2
+// Description : None
+#define PSM_WDSEL_SRAM2_RESET _u(0x0)
+#define PSM_WDSEL_SRAM2_BITS _u(0x00000100)
+#define PSM_WDSEL_SRAM2_MSB _u(8)
+#define PSM_WDSEL_SRAM2_LSB _u(8)
+#define PSM_WDSEL_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_SRAM1
+// Description : None
+#define PSM_WDSEL_SRAM1_RESET _u(0x0)
+#define PSM_WDSEL_SRAM1_BITS _u(0x00000080)
+#define PSM_WDSEL_SRAM1_MSB _u(7)
+#define PSM_WDSEL_SRAM1_LSB _u(7)
+#define PSM_WDSEL_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_SRAM0
+// Description : None
+#define PSM_WDSEL_SRAM0_RESET _u(0x0)
+#define PSM_WDSEL_SRAM0_BITS _u(0x00000040)
+#define PSM_WDSEL_SRAM0_MSB _u(6)
+#define PSM_WDSEL_SRAM0_LSB _u(6)
+#define PSM_WDSEL_SRAM0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_ROM
+// Description : None
+#define PSM_WDSEL_ROM_RESET _u(0x0)
+#define PSM_WDSEL_ROM_BITS _u(0x00000020)
+#define PSM_WDSEL_ROM_MSB _u(5)
+#define PSM_WDSEL_ROM_LSB _u(5)
+#define PSM_WDSEL_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_BUSFABRIC
+// Description : None
+#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
+#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_WDSEL_BUSFABRIC_MSB _u(4)
+#define PSM_WDSEL_BUSFABRIC_LSB _u(4)
+#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_RESETS
+// Description : None
+#define PSM_WDSEL_RESETS_RESET _u(0x0)
+#define PSM_WDSEL_RESETS_BITS _u(0x00000008)
+#define PSM_WDSEL_RESETS_MSB _u(3)
+#define PSM_WDSEL_RESETS_LSB _u(3)
+#define PSM_WDSEL_RESETS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_CLOCKS
+// Description : None
+#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
+#define PSM_WDSEL_CLOCKS_BITS _u(0x00000004)
+#define PSM_WDSEL_CLOCKS_MSB _u(2)
+#define PSM_WDSEL_CLOCKS_LSB _u(2)
+#define PSM_WDSEL_CLOCKS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_XOSC
+// Description : None
+#define PSM_WDSEL_XOSC_RESET _u(0x0)
+#define PSM_WDSEL_XOSC_BITS _u(0x00000002)
+#define PSM_WDSEL_XOSC_MSB _u(1)
+#define PSM_WDSEL_XOSC_LSB _u(1)
+#define PSM_WDSEL_XOSC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PSM_WDSEL_ROSC
+// Description : None
+#define PSM_WDSEL_ROSC_RESET _u(0x0)
+#define PSM_WDSEL_ROSC_BITS _u(0x00000001)
+#define PSM_WDSEL_ROSC_MSB _u(0)
+#define PSM_WDSEL_ROSC_LSB _u(0)
+#define PSM_WDSEL_ROSC_ACCESS "RW"
+// =============================================================================
+// Register : PSM_DONE
+// Description : Indicates the peripheral's registers are ready to access.
+#define PSM_DONE_OFFSET _u(0x0000000c)
+#define PSM_DONE_BITS _u(0x0001ffff)
+#define PSM_DONE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_PROC1
+// Description : None
+#define PSM_DONE_PROC1_RESET _u(0x0)
+#define PSM_DONE_PROC1_BITS _u(0x00010000)
+#define PSM_DONE_PROC1_MSB _u(16)
+#define PSM_DONE_PROC1_LSB _u(16)
+#define PSM_DONE_PROC1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_PROC0
+// Description : None
+#define PSM_DONE_PROC0_RESET _u(0x0)
+#define PSM_DONE_PROC0_BITS _u(0x00008000)
+#define PSM_DONE_PROC0_MSB _u(15)
+#define PSM_DONE_PROC0_LSB _u(15)
+#define PSM_DONE_PROC0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_SIO
+// Description : None
+#define PSM_DONE_SIO_RESET _u(0x0)
+#define PSM_DONE_SIO_BITS _u(0x00004000)
+#define PSM_DONE_SIO_MSB _u(14)
+#define PSM_DONE_SIO_LSB _u(14)
+#define PSM_DONE_SIO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_VREG_AND_CHIP_RESET
+// Description : None
+#define PSM_DONE_VREG_AND_CHIP_RESET_RESET _u(0x0)
+#define PSM_DONE_VREG_AND_CHIP_RESET_BITS _u(0x00002000)
+#define PSM_DONE_VREG_AND_CHIP_RESET_MSB _u(13)
+#define PSM_DONE_VREG_AND_CHIP_RESET_LSB _u(13)
+#define PSM_DONE_VREG_AND_CHIP_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_XIP
+// Description : None
+#define PSM_DONE_XIP_RESET _u(0x0)
+#define PSM_DONE_XIP_BITS _u(0x00001000)
+#define PSM_DONE_XIP_MSB _u(12)
+#define PSM_DONE_XIP_LSB _u(12)
+#define PSM_DONE_XIP_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_SRAM5
+// Description : None
+#define PSM_DONE_SRAM5_RESET _u(0x0)
+#define PSM_DONE_SRAM5_BITS _u(0x00000800)
+#define PSM_DONE_SRAM5_MSB _u(11)
+#define PSM_DONE_SRAM5_LSB _u(11)
+#define PSM_DONE_SRAM5_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_SRAM4
+// Description : None
+#define PSM_DONE_SRAM4_RESET _u(0x0)
+#define PSM_DONE_SRAM4_BITS _u(0x00000400)
+#define PSM_DONE_SRAM4_MSB _u(10)
+#define PSM_DONE_SRAM4_LSB _u(10)
+#define PSM_DONE_SRAM4_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_SRAM3
+// Description : None
+#define PSM_DONE_SRAM3_RESET _u(0x0)
+#define PSM_DONE_SRAM3_BITS _u(0x00000200)
+#define PSM_DONE_SRAM3_MSB _u(9)
+#define PSM_DONE_SRAM3_LSB _u(9)
+#define PSM_DONE_SRAM3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_SRAM2
+// Description : None
+#define PSM_DONE_SRAM2_RESET _u(0x0)
+#define PSM_DONE_SRAM2_BITS _u(0x00000100)
+#define PSM_DONE_SRAM2_MSB _u(8)
+#define PSM_DONE_SRAM2_LSB _u(8)
+#define PSM_DONE_SRAM2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_SRAM1
+// Description : None
+#define PSM_DONE_SRAM1_RESET _u(0x0)
+#define PSM_DONE_SRAM1_BITS _u(0x00000080)
+#define PSM_DONE_SRAM1_MSB _u(7)
+#define PSM_DONE_SRAM1_LSB _u(7)
+#define PSM_DONE_SRAM1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_SRAM0
+// Description : None
+#define PSM_DONE_SRAM0_RESET _u(0x0)
+#define PSM_DONE_SRAM0_BITS _u(0x00000040)
+#define PSM_DONE_SRAM0_MSB _u(6)
+#define PSM_DONE_SRAM0_LSB _u(6)
+#define PSM_DONE_SRAM0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_ROM
+// Description : None
+#define PSM_DONE_ROM_RESET _u(0x0)
+#define PSM_DONE_ROM_BITS _u(0x00000020)
+#define PSM_DONE_ROM_MSB _u(5)
+#define PSM_DONE_ROM_LSB _u(5)
+#define PSM_DONE_ROM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_BUSFABRIC
+// Description : None
+#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
+#define PSM_DONE_BUSFABRIC_BITS _u(0x00000010)
+#define PSM_DONE_BUSFABRIC_MSB _u(4)
+#define PSM_DONE_BUSFABRIC_LSB _u(4)
+#define PSM_DONE_BUSFABRIC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_RESETS
+// Description : None
+#define PSM_DONE_RESETS_RESET _u(0x0)
+#define PSM_DONE_RESETS_BITS _u(0x00000008)
+#define PSM_DONE_RESETS_MSB _u(3)
+#define PSM_DONE_RESETS_LSB _u(3)
+#define PSM_DONE_RESETS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_CLOCKS
+// Description : None
+#define PSM_DONE_CLOCKS_RESET _u(0x0)
+#define PSM_DONE_CLOCKS_BITS _u(0x00000004)
+#define PSM_DONE_CLOCKS_MSB _u(2)
+#define PSM_DONE_CLOCKS_LSB _u(2)
+#define PSM_DONE_CLOCKS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_XOSC
+// Description : None
+#define PSM_DONE_XOSC_RESET _u(0x0)
+#define PSM_DONE_XOSC_BITS _u(0x00000002)
+#define PSM_DONE_XOSC_MSB _u(1)
+#define PSM_DONE_XOSC_LSB _u(1)
+#define PSM_DONE_XOSC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PSM_DONE_ROSC
+// Description : None
+#define PSM_DONE_ROSC_RESET _u(0x0)
+#define PSM_DONE_ROSC_BITS _u(0x00000001)
+#define PSM_DONE_ROSC_MSB _u(0)
+#define PSM_DONE_ROSC_LSB _u(0)
+#define PSM_DONE_ROSC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_PSM_DEFINED
diff --git a/arkanoid/pico/hardware/regs/pwm.h b/arkanoid/pico/hardware/regs/pwm.h
new file mode 100644
index 0000000..a853597
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/pwm.h
@@ -0,0 +1,1505 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PWM
+// Version : 1
+// Bus type : apb
+// Description : Simple PWM
+// =============================================================================
+#ifndef HARDWARE_REGS_PWM_DEFINED
+#define HARDWARE_REGS_PWM_DEFINED
+// =============================================================================
+// Register : PWM_CH0_CSR
+// Description : Control and status register
+#define PWM_CH0_CSR_OFFSET _u(0x00000000)
+#define PWM_CH0_CSR_BITS _u(0x000000ff)
+#define PWM_CH0_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH0_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH0_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH0_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH0_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH0_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH0_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH0_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH0_CSR_PH_RET_MSB _u(6)
+#define PWM_CH0_CSR_PH_RET_LSB _u(6)
+#define PWM_CH0_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH0_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH0_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH0_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH0_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH0_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH0_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH0_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH0_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH0_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH0_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH0_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH0_CSR_B_INV_MSB _u(3)
+#define PWM_CH0_CSR_B_INV_LSB _u(3)
+#define PWM_CH0_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH0_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH0_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH0_CSR_A_INV_MSB _u(2)
+#define PWM_CH0_CSR_A_INV_LSB _u(2)
+#define PWM_CH0_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH0_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH0_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH0_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH0_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH0_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH0_CSR_EN_RESET _u(0x0)
+#define PWM_CH0_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH0_CSR_EN_MSB _u(0)
+#define PWM_CH0_CSR_EN_LSB _u(0)
+#define PWM_CH0_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH0_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH0_DIV_OFFSET _u(0x00000004)
+#define PWM_CH0_DIV_BITS _u(0x00000fff)
+#define PWM_CH0_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_DIV_INT
+// Description : None
+#define PWM_CH0_DIV_INT_RESET _u(0x01)
+#define PWM_CH0_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH0_DIV_INT_MSB _u(11)
+#define PWM_CH0_DIV_INT_LSB _u(4)
+#define PWM_CH0_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_DIV_FRAC
+// Description : None
+#define PWM_CH0_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH0_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH0_DIV_FRAC_MSB _u(3)
+#define PWM_CH0_DIV_FRAC_LSB _u(0)
+#define PWM_CH0_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH0_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH0_CTR_OFFSET _u(0x00000008)
+#define PWM_CH0_CTR_BITS _u(0x0000ffff)
+#define PWM_CH0_CTR_RESET _u(0x00000000)
+#define PWM_CH0_CTR_MSB _u(15)
+#define PWM_CH0_CTR_LSB _u(0)
+#define PWM_CH0_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH0_CC
+// Description : Counter compare values
+#define PWM_CH0_CC_OFFSET _u(0x0000000c)
+#define PWM_CH0_CC_BITS _u(0xffffffff)
+#define PWM_CH0_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CC_B
+// Description : None
+#define PWM_CH0_CC_B_RESET _u(0x0000)
+#define PWM_CH0_CC_B_BITS _u(0xffff0000)
+#define PWM_CH0_CC_B_MSB _u(31)
+#define PWM_CH0_CC_B_LSB _u(16)
+#define PWM_CH0_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH0_CC_A
+// Description : None
+#define PWM_CH0_CC_A_RESET _u(0x0000)
+#define PWM_CH0_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH0_CC_A_MSB _u(15)
+#define PWM_CH0_CC_A_LSB _u(0)
+#define PWM_CH0_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH0_TOP
+// Description : Counter wrap value
+#define PWM_CH0_TOP_OFFSET _u(0x00000010)
+#define PWM_CH0_TOP_BITS _u(0x0000ffff)
+#define PWM_CH0_TOP_RESET _u(0x0000ffff)
+#define PWM_CH0_TOP_MSB _u(15)
+#define PWM_CH0_TOP_LSB _u(0)
+#define PWM_CH0_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH1_CSR
+// Description : Control and status register
+#define PWM_CH1_CSR_OFFSET _u(0x00000014)
+#define PWM_CH1_CSR_BITS _u(0x000000ff)
+#define PWM_CH1_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH1_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH1_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH1_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH1_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH1_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH1_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH1_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH1_CSR_PH_RET_MSB _u(6)
+#define PWM_CH1_CSR_PH_RET_LSB _u(6)
+#define PWM_CH1_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH1_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH1_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH1_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH1_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH1_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH1_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH1_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH1_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH1_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH1_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH1_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH1_CSR_B_INV_MSB _u(3)
+#define PWM_CH1_CSR_B_INV_LSB _u(3)
+#define PWM_CH1_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH1_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH1_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH1_CSR_A_INV_MSB _u(2)
+#define PWM_CH1_CSR_A_INV_LSB _u(2)
+#define PWM_CH1_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH1_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH1_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH1_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH1_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH1_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH1_CSR_EN_RESET _u(0x0)
+#define PWM_CH1_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH1_CSR_EN_MSB _u(0)
+#define PWM_CH1_CSR_EN_LSB _u(0)
+#define PWM_CH1_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH1_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH1_DIV_OFFSET _u(0x00000018)
+#define PWM_CH1_DIV_BITS _u(0x00000fff)
+#define PWM_CH1_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_DIV_INT
+// Description : None
+#define PWM_CH1_DIV_INT_RESET _u(0x01)
+#define PWM_CH1_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH1_DIV_INT_MSB _u(11)
+#define PWM_CH1_DIV_INT_LSB _u(4)
+#define PWM_CH1_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_DIV_FRAC
+// Description : None
+#define PWM_CH1_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH1_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH1_DIV_FRAC_MSB _u(3)
+#define PWM_CH1_DIV_FRAC_LSB _u(0)
+#define PWM_CH1_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH1_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH1_CTR_OFFSET _u(0x0000001c)
+#define PWM_CH1_CTR_BITS _u(0x0000ffff)
+#define PWM_CH1_CTR_RESET _u(0x00000000)
+#define PWM_CH1_CTR_MSB _u(15)
+#define PWM_CH1_CTR_LSB _u(0)
+#define PWM_CH1_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH1_CC
+// Description : Counter compare values
+#define PWM_CH1_CC_OFFSET _u(0x00000020)
+#define PWM_CH1_CC_BITS _u(0xffffffff)
+#define PWM_CH1_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CC_B
+// Description : None
+#define PWM_CH1_CC_B_RESET _u(0x0000)
+#define PWM_CH1_CC_B_BITS _u(0xffff0000)
+#define PWM_CH1_CC_B_MSB _u(31)
+#define PWM_CH1_CC_B_LSB _u(16)
+#define PWM_CH1_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH1_CC_A
+// Description : None
+#define PWM_CH1_CC_A_RESET _u(0x0000)
+#define PWM_CH1_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH1_CC_A_MSB _u(15)
+#define PWM_CH1_CC_A_LSB _u(0)
+#define PWM_CH1_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH1_TOP
+// Description : Counter wrap value
+#define PWM_CH1_TOP_OFFSET _u(0x00000024)
+#define PWM_CH1_TOP_BITS _u(0x0000ffff)
+#define PWM_CH1_TOP_RESET _u(0x0000ffff)
+#define PWM_CH1_TOP_MSB _u(15)
+#define PWM_CH1_TOP_LSB _u(0)
+#define PWM_CH1_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH2_CSR
+// Description : Control and status register
+#define PWM_CH2_CSR_OFFSET _u(0x00000028)
+#define PWM_CH2_CSR_BITS _u(0x000000ff)
+#define PWM_CH2_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH2_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH2_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH2_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH2_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH2_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH2_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH2_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH2_CSR_PH_RET_MSB _u(6)
+#define PWM_CH2_CSR_PH_RET_LSB _u(6)
+#define PWM_CH2_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH2_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH2_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH2_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH2_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH2_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH2_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH2_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH2_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH2_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH2_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH2_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH2_CSR_B_INV_MSB _u(3)
+#define PWM_CH2_CSR_B_INV_LSB _u(3)
+#define PWM_CH2_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH2_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH2_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH2_CSR_A_INV_MSB _u(2)
+#define PWM_CH2_CSR_A_INV_LSB _u(2)
+#define PWM_CH2_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH2_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH2_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH2_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH2_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH2_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH2_CSR_EN_RESET _u(0x0)
+#define PWM_CH2_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH2_CSR_EN_MSB _u(0)
+#define PWM_CH2_CSR_EN_LSB _u(0)
+#define PWM_CH2_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH2_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH2_DIV_OFFSET _u(0x0000002c)
+#define PWM_CH2_DIV_BITS _u(0x00000fff)
+#define PWM_CH2_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_DIV_INT
+// Description : None
+#define PWM_CH2_DIV_INT_RESET _u(0x01)
+#define PWM_CH2_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH2_DIV_INT_MSB _u(11)
+#define PWM_CH2_DIV_INT_LSB _u(4)
+#define PWM_CH2_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_DIV_FRAC
+// Description : None
+#define PWM_CH2_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH2_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH2_DIV_FRAC_MSB _u(3)
+#define PWM_CH2_DIV_FRAC_LSB _u(0)
+#define PWM_CH2_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH2_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH2_CTR_OFFSET _u(0x00000030)
+#define PWM_CH2_CTR_BITS _u(0x0000ffff)
+#define PWM_CH2_CTR_RESET _u(0x00000000)
+#define PWM_CH2_CTR_MSB _u(15)
+#define PWM_CH2_CTR_LSB _u(0)
+#define PWM_CH2_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH2_CC
+// Description : Counter compare values
+#define PWM_CH2_CC_OFFSET _u(0x00000034)
+#define PWM_CH2_CC_BITS _u(0xffffffff)
+#define PWM_CH2_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CC_B
+// Description : None
+#define PWM_CH2_CC_B_RESET _u(0x0000)
+#define PWM_CH2_CC_B_BITS _u(0xffff0000)
+#define PWM_CH2_CC_B_MSB _u(31)
+#define PWM_CH2_CC_B_LSB _u(16)
+#define PWM_CH2_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH2_CC_A
+// Description : None
+#define PWM_CH2_CC_A_RESET _u(0x0000)
+#define PWM_CH2_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH2_CC_A_MSB _u(15)
+#define PWM_CH2_CC_A_LSB _u(0)
+#define PWM_CH2_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH2_TOP
+// Description : Counter wrap value
+#define PWM_CH2_TOP_OFFSET _u(0x00000038)
+#define PWM_CH2_TOP_BITS _u(0x0000ffff)
+#define PWM_CH2_TOP_RESET _u(0x0000ffff)
+#define PWM_CH2_TOP_MSB _u(15)
+#define PWM_CH2_TOP_LSB _u(0)
+#define PWM_CH2_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH3_CSR
+// Description : Control and status register
+#define PWM_CH3_CSR_OFFSET _u(0x0000003c)
+#define PWM_CH3_CSR_BITS _u(0x000000ff)
+#define PWM_CH3_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH3_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH3_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH3_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH3_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH3_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH3_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH3_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH3_CSR_PH_RET_MSB _u(6)
+#define PWM_CH3_CSR_PH_RET_LSB _u(6)
+#define PWM_CH3_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH3_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH3_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH3_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH3_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH3_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH3_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH3_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH3_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH3_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH3_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH3_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH3_CSR_B_INV_MSB _u(3)
+#define PWM_CH3_CSR_B_INV_LSB _u(3)
+#define PWM_CH3_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH3_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH3_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH3_CSR_A_INV_MSB _u(2)
+#define PWM_CH3_CSR_A_INV_LSB _u(2)
+#define PWM_CH3_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH3_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH3_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH3_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH3_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH3_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH3_CSR_EN_RESET _u(0x0)
+#define PWM_CH3_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH3_CSR_EN_MSB _u(0)
+#define PWM_CH3_CSR_EN_LSB _u(0)
+#define PWM_CH3_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH3_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH3_DIV_OFFSET _u(0x00000040)
+#define PWM_CH3_DIV_BITS _u(0x00000fff)
+#define PWM_CH3_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_DIV_INT
+// Description : None
+#define PWM_CH3_DIV_INT_RESET _u(0x01)
+#define PWM_CH3_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH3_DIV_INT_MSB _u(11)
+#define PWM_CH3_DIV_INT_LSB _u(4)
+#define PWM_CH3_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_DIV_FRAC
+// Description : None
+#define PWM_CH3_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH3_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH3_DIV_FRAC_MSB _u(3)
+#define PWM_CH3_DIV_FRAC_LSB _u(0)
+#define PWM_CH3_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH3_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH3_CTR_OFFSET _u(0x00000044)
+#define PWM_CH3_CTR_BITS _u(0x0000ffff)
+#define PWM_CH3_CTR_RESET _u(0x00000000)
+#define PWM_CH3_CTR_MSB _u(15)
+#define PWM_CH3_CTR_LSB _u(0)
+#define PWM_CH3_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH3_CC
+// Description : Counter compare values
+#define PWM_CH3_CC_OFFSET _u(0x00000048)
+#define PWM_CH3_CC_BITS _u(0xffffffff)
+#define PWM_CH3_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CC_B
+// Description : None
+#define PWM_CH3_CC_B_RESET _u(0x0000)
+#define PWM_CH3_CC_B_BITS _u(0xffff0000)
+#define PWM_CH3_CC_B_MSB _u(31)
+#define PWM_CH3_CC_B_LSB _u(16)
+#define PWM_CH3_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH3_CC_A
+// Description : None
+#define PWM_CH3_CC_A_RESET _u(0x0000)
+#define PWM_CH3_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH3_CC_A_MSB _u(15)
+#define PWM_CH3_CC_A_LSB _u(0)
+#define PWM_CH3_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH3_TOP
+// Description : Counter wrap value
+#define PWM_CH3_TOP_OFFSET _u(0x0000004c)
+#define PWM_CH3_TOP_BITS _u(0x0000ffff)
+#define PWM_CH3_TOP_RESET _u(0x0000ffff)
+#define PWM_CH3_TOP_MSB _u(15)
+#define PWM_CH3_TOP_LSB _u(0)
+#define PWM_CH3_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH4_CSR
+// Description : Control and status register
+#define PWM_CH4_CSR_OFFSET _u(0x00000050)
+#define PWM_CH4_CSR_BITS _u(0x000000ff)
+#define PWM_CH4_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH4_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH4_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH4_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH4_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH4_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH4_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH4_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH4_CSR_PH_RET_MSB _u(6)
+#define PWM_CH4_CSR_PH_RET_LSB _u(6)
+#define PWM_CH4_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH4_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH4_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH4_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH4_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH4_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH4_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH4_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH4_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH4_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH4_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH4_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH4_CSR_B_INV_MSB _u(3)
+#define PWM_CH4_CSR_B_INV_LSB _u(3)
+#define PWM_CH4_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH4_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH4_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH4_CSR_A_INV_MSB _u(2)
+#define PWM_CH4_CSR_A_INV_LSB _u(2)
+#define PWM_CH4_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH4_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH4_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH4_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH4_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH4_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH4_CSR_EN_RESET _u(0x0)
+#define PWM_CH4_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH4_CSR_EN_MSB _u(0)
+#define PWM_CH4_CSR_EN_LSB _u(0)
+#define PWM_CH4_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH4_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH4_DIV_OFFSET _u(0x00000054)
+#define PWM_CH4_DIV_BITS _u(0x00000fff)
+#define PWM_CH4_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_DIV_INT
+// Description : None
+#define PWM_CH4_DIV_INT_RESET _u(0x01)
+#define PWM_CH4_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH4_DIV_INT_MSB _u(11)
+#define PWM_CH4_DIV_INT_LSB _u(4)
+#define PWM_CH4_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_DIV_FRAC
+// Description : None
+#define PWM_CH4_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH4_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH4_DIV_FRAC_MSB _u(3)
+#define PWM_CH4_DIV_FRAC_LSB _u(0)
+#define PWM_CH4_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH4_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH4_CTR_OFFSET _u(0x00000058)
+#define PWM_CH4_CTR_BITS _u(0x0000ffff)
+#define PWM_CH4_CTR_RESET _u(0x00000000)
+#define PWM_CH4_CTR_MSB _u(15)
+#define PWM_CH4_CTR_LSB _u(0)
+#define PWM_CH4_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH4_CC
+// Description : Counter compare values
+#define PWM_CH4_CC_OFFSET _u(0x0000005c)
+#define PWM_CH4_CC_BITS _u(0xffffffff)
+#define PWM_CH4_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CC_B
+// Description : None
+#define PWM_CH4_CC_B_RESET _u(0x0000)
+#define PWM_CH4_CC_B_BITS _u(0xffff0000)
+#define PWM_CH4_CC_B_MSB _u(31)
+#define PWM_CH4_CC_B_LSB _u(16)
+#define PWM_CH4_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH4_CC_A
+// Description : None
+#define PWM_CH4_CC_A_RESET _u(0x0000)
+#define PWM_CH4_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH4_CC_A_MSB _u(15)
+#define PWM_CH4_CC_A_LSB _u(0)
+#define PWM_CH4_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH4_TOP
+// Description : Counter wrap value
+#define PWM_CH4_TOP_OFFSET _u(0x00000060)
+#define PWM_CH4_TOP_BITS _u(0x0000ffff)
+#define PWM_CH4_TOP_RESET _u(0x0000ffff)
+#define PWM_CH4_TOP_MSB _u(15)
+#define PWM_CH4_TOP_LSB _u(0)
+#define PWM_CH4_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH5_CSR
+// Description : Control and status register
+#define PWM_CH5_CSR_OFFSET _u(0x00000064)
+#define PWM_CH5_CSR_BITS _u(0x000000ff)
+#define PWM_CH5_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH5_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH5_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH5_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH5_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH5_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH5_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH5_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH5_CSR_PH_RET_MSB _u(6)
+#define PWM_CH5_CSR_PH_RET_LSB _u(6)
+#define PWM_CH5_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH5_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH5_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH5_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH5_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH5_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH5_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH5_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH5_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH5_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH5_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH5_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH5_CSR_B_INV_MSB _u(3)
+#define PWM_CH5_CSR_B_INV_LSB _u(3)
+#define PWM_CH5_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH5_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH5_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH5_CSR_A_INV_MSB _u(2)
+#define PWM_CH5_CSR_A_INV_LSB _u(2)
+#define PWM_CH5_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH5_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH5_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH5_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH5_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH5_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH5_CSR_EN_RESET _u(0x0)
+#define PWM_CH5_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH5_CSR_EN_MSB _u(0)
+#define PWM_CH5_CSR_EN_LSB _u(0)
+#define PWM_CH5_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH5_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH5_DIV_OFFSET _u(0x00000068)
+#define PWM_CH5_DIV_BITS _u(0x00000fff)
+#define PWM_CH5_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_DIV_INT
+// Description : None
+#define PWM_CH5_DIV_INT_RESET _u(0x01)
+#define PWM_CH5_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH5_DIV_INT_MSB _u(11)
+#define PWM_CH5_DIV_INT_LSB _u(4)
+#define PWM_CH5_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_DIV_FRAC
+// Description : None
+#define PWM_CH5_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH5_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH5_DIV_FRAC_MSB _u(3)
+#define PWM_CH5_DIV_FRAC_LSB _u(0)
+#define PWM_CH5_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH5_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH5_CTR_OFFSET _u(0x0000006c)
+#define PWM_CH5_CTR_BITS _u(0x0000ffff)
+#define PWM_CH5_CTR_RESET _u(0x00000000)
+#define PWM_CH5_CTR_MSB _u(15)
+#define PWM_CH5_CTR_LSB _u(0)
+#define PWM_CH5_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH5_CC
+// Description : Counter compare values
+#define PWM_CH5_CC_OFFSET _u(0x00000070)
+#define PWM_CH5_CC_BITS _u(0xffffffff)
+#define PWM_CH5_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CC_B
+// Description : None
+#define PWM_CH5_CC_B_RESET _u(0x0000)
+#define PWM_CH5_CC_B_BITS _u(0xffff0000)
+#define PWM_CH5_CC_B_MSB _u(31)
+#define PWM_CH5_CC_B_LSB _u(16)
+#define PWM_CH5_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH5_CC_A
+// Description : None
+#define PWM_CH5_CC_A_RESET _u(0x0000)
+#define PWM_CH5_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH5_CC_A_MSB _u(15)
+#define PWM_CH5_CC_A_LSB _u(0)
+#define PWM_CH5_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH5_TOP
+// Description : Counter wrap value
+#define PWM_CH5_TOP_OFFSET _u(0x00000074)
+#define PWM_CH5_TOP_BITS _u(0x0000ffff)
+#define PWM_CH5_TOP_RESET _u(0x0000ffff)
+#define PWM_CH5_TOP_MSB _u(15)
+#define PWM_CH5_TOP_LSB _u(0)
+#define PWM_CH5_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH6_CSR
+// Description : Control and status register
+#define PWM_CH6_CSR_OFFSET _u(0x00000078)
+#define PWM_CH6_CSR_BITS _u(0x000000ff)
+#define PWM_CH6_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH6_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH6_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH6_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH6_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH6_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH6_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH6_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH6_CSR_PH_RET_MSB _u(6)
+#define PWM_CH6_CSR_PH_RET_LSB _u(6)
+#define PWM_CH6_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH6_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH6_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH6_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH6_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH6_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH6_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH6_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH6_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH6_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH6_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH6_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH6_CSR_B_INV_MSB _u(3)
+#define PWM_CH6_CSR_B_INV_LSB _u(3)
+#define PWM_CH6_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH6_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH6_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH6_CSR_A_INV_MSB _u(2)
+#define PWM_CH6_CSR_A_INV_LSB _u(2)
+#define PWM_CH6_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH6_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH6_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH6_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH6_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH6_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH6_CSR_EN_RESET _u(0x0)
+#define PWM_CH6_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH6_CSR_EN_MSB _u(0)
+#define PWM_CH6_CSR_EN_LSB _u(0)
+#define PWM_CH6_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH6_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH6_DIV_OFFSET _u(0x0000007c)
+#define PWM_CH6_DIV_BITS _u(0x00000fff)
+#define PWM_CH6_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_DIV_INT
+// Description : None
+#define PWM_CH6_DIV_INT_RESET _u(0x01)
+#define PWM_CH6_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH6_DIV_INT_MSB _u(11)
+#define PWM_CH6_DIV_INT_LSB _u(4)
+#define PWM_CH6_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_DIV_FRAC
+// Description : None
+#define PWM_CH6_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH6_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH6_DIV_FRAC_MSB _u(3)
+#define PWM_CH6_DIV_FRAC_LSB _u(0)
+#define PWM_CH6_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH6_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH6_CTR_OFFSET _u(0x00000080)
+#define PWM_CH6_CTR_BITS _u(0x0000ffff)
+#define PWM_CH6_CTR_RESET _u(0x00000000)
+#define PWM_CH6_CTR_MSB _u(15)
+#define PWM_CH6_CTR_LSB _u(0)
+#define PWM_CH6_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH6_CC
+// Description : Counter compare values
+#define PWM_CH6_CC_OFFSET _u(0x00000084)
+#define PWM_CH6_CC_BITS _u(0xffffffff)
+#define PWM_CH6_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CC_B
+// Description : None
+#define PWM_CH6_CC_B_RESET _u(0x0000)
+#define PWM_CH6_CC_B_BITS _u(0xffff0000)
+#define PWM_CH6_CC_B_MSB _u(31)
+#define PWM_CH6_CC_B_LSB _u(16)
+#define PWM_CH6_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH6_CC_A
+// Description : None
+#define PWM_CH6_CC_A_RESET _u(0x0000)
+#define PWM_CH6_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH6_CC_A_MSB _u(15)
+#define PWM_CH6_CC_A_LSB _u(0)
+#define PWM_CH6_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH6_TOP
+// Description : Counter wrap value
+#define PWM_CH6_TOP_OFFSET _u(0x00000088)
+#define PWM_CH6_TOP_BITS _u(0x0000ffff)
+#define PWM_CH6_TOP_RESET _u(0x0000ffff)
+#define PWM_CH6_TOP_MSB _u(15)
+#define PWM_CH6_TOP_LSB _u(0)
+#define PWM_CH6_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH7_CSR
+// Description : Control and status register
+#define PWM_CH7_CSR_OFFSET _u(0x0000008c)
+#define PWM_CH7_CSR_BITS _u(0x000000ff)
+#define PWM_CH7_CSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CSR_PH_ADV
+// Description : Advance the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running
+// at less than full speed (div_int + div_frac / 16 > 1)
+#define PWM_CH7_CSR_PH_ADV_RESET _u(0x0)
+#define PWM_CH7_CSR_PH_ADV_BITS _u(0x00000080)
+#define PWM_CH7_CSR_PH_ADV_MSB _u(7)
+#define PWM_CH7_CSR_PH_ADV_LSB _u(7)
+#define PWM_CH7_CSR_PH_ADV_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CSR_PH_RET
+// Description : Retard the phase of the counter by 1 count, while it is
+// running.
+// Self-clearing. Write a 1, and poll until low. Counter must be
+// running.
+#define PWM_CH7_CSR_PH_RET_RESET _u(0x0)
+#define PWM_CH7_CSR_PH_RET_BITS _u(0x00000040)
+#define PWM_CH7_CSR_PH_RET_MSB _u(6)
+#define PWM_CH7_CSR_PH_RET_LSB _u(6)
+#define PWM_CH7_CSR_PH_RET_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CSR_DIVMODE
+// Description : 0x0 -> Free-running counting at rate dictated by fractional
+// divider
+// 0x1 -> Fractional divider operation is gated by the PWM B pin.
+// 0x2 -> Counter advances with each rising edge of the PWM B pin.
+// 0x3 -> Counter advances with each falling edge of the PWM B
+// pin.
+#define PWM_CH7_CSR_DIVMODE_RESET _u(0x0)
+#define PWM_CH7_CSR_DIVMODE_BITS _u(0x00000030)
+#define PWM_CH7_CSR_DIVMODE_MSB _u(5)
+#define PWM_CH7_CSR_DIVMODE_LSB _u(4)
+#define PWM_CH7_CSR_DIVMODE_ACCESS "RW"
+#define PWM_CH7_CSR_DIVMODE_VALUE_DIV _u(0x0)
+#define PWM_CH7_CSR_DIVMODE_VALUE_LEVEL _u(0x1)
+#define PWM_CH7_CSR_DIVMODE_VALUE_RISE _u(0x2)
+#define PWM_CH7_CSR_DIVMODE_VALUE_FALL _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CSR_B_INV
+// Description : Invert output B
+#define PWM_CH7_CSR_B_INV_RESET _u(0x0)
+#define PWM_CH7_CSR_B_INV_BITS _u(0x00000008)
+#define PWM_CH7_CSR_B_INV_MSB _u(3)
+#define PWM_CH7_CSR_B_INV_LSB _u(3)
+#define PWM_CH7_CSR_B_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CSR_A_INV
+// Description : Invert output A
+#define PWM_CH7_CSR_A_INV_RESET _u(0x0)
+#define PWM_CH7_CSR_A_INV_BITS _u(0x00000004)
+#define PWM_CH7_CSR_A_INV_MSB _u(2)
+#define PWM_CH7_CSR_A_INV_LSB _u(2)
+#define PWM_CH7_CSR_A_INV_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CSR_PH_CORRECT
+// Description : 1: Enable phase-correct modulation. 0: Trailing-edge
+#define PWM_CH7_CSR_PH_CORRECT_RESET _u(0x0)
+#define PWM_CH7_CSR_PH_CORRECT_BITS _u(0x00000002)
+#define PWM_CH7_CSR_PH_CORRECT_MSB _u(1)
+#define PWM_CH7_CSR_PH_CORRECT_LSB _u(1)
+#define PWM_CH7_CSR_PH_CORRECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CSR_EN
+// Description : Enable the PWM channel.
+#define PWM_CH7_CSR_EN_RESET _u(0x0)
+#define PWM_CH7_CSR_EN_BITS _u(0x00000001)
+#define PWM_CH7_CSR_EN_MSB _u(0)
+#define PWM_CH7_CSR_EN_LSB _u(0)
+#define PWM_CH7_CSR_EN_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH7_DIV
+// Description : INT and FRAC form a fixed-point fractional number.
+// Counting rate is system clock frequency divided by this number.
+// Fractional division uses simple 1st-order sigma-delta.
+#define PWM_CH7_DIV_OFFSET _u(0x00000090)
+#define PWM_CH7_DIV_BITS _u(0x00000fff)
+#define PWM_CH7_DIV_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_DIV_INT
+// Description : None
+#define PWM_CH7_DIV_INT_RESET _u(0x01)
+#define PWM_CH7_DIV_INT_BITS _u(0x00000ff0)
+#define PWM_CH7_DIV_INT_MSB _u(11)
+#define PWM_CH7_DIV_INT_LSB _u(4)
+#define PWM_CH7_DIV_INT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_DIV_FRAC
+// Description : None
+#define PWM_CH7_DIV_FRAC_RESET _u(0x0)
+#define PWM_CH7_DIV_FRAC_BITS _u(0x0000000f)
+#define PWM_CH7_DIV_FRAC_MSB _u(3)
+#define PWM_CH7_DIV_FRAC_LSB _u(0)
+#define PWM_CH7_DIV_FRAC_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH7_CTR
+// Description : Direct access to the PWM counter
+#define PWM_CH7_CTR_OFFSET _u(0x00000094)
+#define PWM_CH7_CTR_BITS _u(0x0000ffff)
+#define PWM_CH7_CTR_RESET _u(0x00000000)
+#define PWM_CH7_CTR_MSB _u(15)
+#define PWM_CH7_CTR_LSB _u(0)
+#define PWM_CH7_CTR_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH7_CC
+// Description : Counter compare values
+#define PWM_CH7_CC_OFFSET _u(0x00000098)
+#define PWM_CH7_CC_BITS _u(0xffffffff)
+#define PWM_CH7_CC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CC_B
+// Description : None
+#define PWM_CH7_CC_B_RESET _u(0x0000)
+#define PWM_CH7_CC_B_BITS _u(0xffff0000)
+#define PWM_CH7_CC_B_MSB _u(31)
+#define PWM_CH7_CC_B_LSB _u(16)
+#define PWM_CH7_CC_B_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_CH7_CC_A
+// Description : None
+#define PWM_CH7_CC_A_RESET _u(0x0000)
+#define PWM_CH7_CC_A_BITS _u(0x0000ffff)
+#define PWM_CH7_CC_A_MSB _u(15)
+#define PWM_CH7_CC_A_LSB _u(0)
+#define PWM_CH7_CC_A_ACCESS "RW"
+// =============================================================================
+// Register : PWM_CH7_TOP
+// Description : Counter wrap value
+#define PWM_CH7_TOP_OFFSET _u(0x0000009c)
+#define PWM_CH7_TOP_BITS _u(0x0000ffff)
+#define PWM_CH7_TOP_RESET _u(0x0000ffff)
+#define PWM_CH7_TOP_MSB _u(15)
+#define PWM_CH7_TOP_LSB _u(0)
+#define PWM_CH7_TOP_ACCESS "RW"
+// =============================================================================
+// Register : PWM_EN
+// Description : This register aliases the CSR_EN bits for all channels.
+// Writing to this register allows multiple channels to be enabled
+// or disabled simultaneously, so they can run in perfect sync.
+// For each channel, there is only one physical EN register bit,
+// which can be accessed through here or CHx_CSR.
+#define PWM_EN_OFFSET _u(0x000000a0)
+#define PWM_EN_BITS _u(0x000000ff)
+#define PWM_EN_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH7
+// Description : None
+#define PWM_EN_CH7_RESET _u(0x0)
+#define PWM_EN_CH7_BITS _u(0x00000080)
+#define PWM_EN_CH7_MSB _u(7)
+#define PWM_EN_CH7_LSB _u(7)
+#define PWM_EN_CH7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH6
+// Description : None
+#define PWM_EN_CH6_RESET _u(0x0)
+#define PWM_EN_CH6_BITS _u(0x00000040)
+#define PWM_EN_CH6_MSB _u(6)
+#define PWM_EN_CH6_LSB _u(6)
+#define PWM_EN_CH6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH5
+// Description : None
+#define PWM_EN_CH5_RESET _u(0x0)
+#define PWM_EN_CH5_BITS _u(0x00000020)
+#define PWM_EN_CH5_MSB _u(5)
+#define PWM_EN_CH5_LSB _u(5)
+#define PWM_EN_CH5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH4
+// Description : None
+#define PWM_EN_CH4_RESET _u(0x0)
+#define PWM_EN_CH4_BITS _u(0x00000010)
+#define PWM_EN_CH4_MSB _u(4)
+#define PWM_EN_CH4_LSB _u(4)
+#define PWM_EN_CH4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH3
+// Description : None
+#define PWM_EN_CH3_RESET _u(0x0)
+#define PWM_EN_CH3_BITS _u(0x00000008)
+#define PWM_EN_CH3_MSB _u(3)
+#define PWM_EN_CH3_LSB _u(3)
+#define PWM_EN_CH3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH2
+// Description : None
+#define PWM_EN_CH2_RESET _u(0x0)
+#define PWM_EN_CH2_BITS _u(0x00000004)
+#define PWM_EN_CH2_MSB _u(2)
+#define PWM_EN_CH2_LSB _u(2)
+#define PWM_EN_CH2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH1
+// Description : None
+#define PWM_EN_CH1_RESET _u(0x0)
+#define PWM_EN_CH1_BITS _u(0x00000002)
+#define PWM_EN_CH1_MSB _u(1)
+#define PWM_EN_CH1_LSB _u(1)
+#define PWM_EN_CH1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_EN_CH0
+// Description : None
+#define PWM_EN_CH0_RESET _u(0x0)
+#define PWM_EN_CH0_BITS _u(0x00000001)
+#define PWM_EN_CH0_MSB _u(0)
+#define PWM_EN_CH0_LSB _u(0)
+#define PWM_EN_CH0_ACCESS "RW"
+// =============================================================================
+// Register : PWM_INTR
+// Description : Raw Interrupts
+#define PWM_INTR_OFFSET _u(0x000000a4)
+#define PWM_INTR_BITS _u(0x000000ff)
+#define PWM_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH7
+// Description : None
+#define PWM_INTR_CH7_RESET _u(0x0)
+#define PWM_INTR_CH7_BITS _u(0x00000080)
+#define PWM_INTR_CH7_MSB _u(7)
+#define PWM_INTR_CH7_LSB _u(7)
+#define PWM_INTR_CH7_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH6
+// Description : None
+#define PWM_INTR_CH6_RESET _u(0x0)
+#define PWM_INTR_CH6_BITS _u(0x00000040)
+#define PWM_INTR_CH6_MSB _u(6)
+#define PWM_INTR_CH6_LSB _u(6)
+#define PWM_INTR_CH6_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH5
+// Description : None
+#define PWM_INTR_CH5_RESET _u(0x0)
+#define PWM_INTR_CH5_BITS _u(0x00000020)
+#define PWM_INTR_CH5_MSB _u(5)
+#define PWM_INTR_CH5_LSB _u(5)
+#define PWM_INTR_CH5_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH4
+// Description : None
+#define PWM_INTR_CH4_RESET _u(0x0)
+#define PWM_INTR_CH4_BITS _u(0x00000010)
+#define PWM_INTR_CH4_MSB _u(4)
+#define PWM_INTR_CH4_LSB _u(4)
+#define PWM_INTR_CH4_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH3
+// Description : None
+#define PWM_INTR_CH3_RESET _u(0x0)
+#define PWM_INTR_CH3_BITS _u(0x00000008)
+#define PWM_INTR_CH3_MSB _u(3)
+#define PWM_INTR_CH3_LSB _u(3)
+#define PWM_INTR_CH3_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH2
+// Description : None
+#define PWM_INTR_CH2_RESET _u(0x0)
+#define PWM_INTR_CH2_BITS _u(0x00000004)
+#define PWM_INTR_CH2_MSB _u(2)
+#define PWM_INTR_CH2_LSB _u(2)
+#define PWM_INTR_CH2_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH1
+// Description : None
+#define PWM_INTR_CH1_RESET _u(0x0)
+#define PWM_INTR_CH1_BITS _u(0x00000002)
+#define PWM_INTR_CH1_MSB _u(1)
+#define PWM_INTR_CH1_LSB _u(1)
+#define PWM_INTR_CH1_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTR_CH0
+// Description : None
+#define PWM_INTR_CH0_RESET _u(0x0)
+#define PWM_INTR_CH0_BITS _u(0x00000001)
+#define PWM_INTR_CH0_MSB _u(0)
+#define PWM_INTR_CH0_LSB _u(0)
+#define PWM_INTR_CH0_ACCESS "WC"
+// =============================================================================
+// Register : PWM_INTE
+// Description : Interrupt Enable
+#define PWM_INTE_OFFSET _u(0x000000a8)
+#define PWM_INTE_BITS _u(0x000000ff)
+#define PWM_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH7
+// Description : None
+#define PWM_INTE_CH7_RESET _u(0x0)
+#define PWM_INTE_CH7_BITS _u(0x00000080)
+#define PWM_INTE_CH7_MSB _u(7)
+#define PWM_INTE_CH7_LSB _u(7)
+#define PWM_INTE_CH7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH6
+// Description : None
+#define PWM_INTE_CH6_RESET _u(0x0)
+#define PWM_INTE_CH6_BITS _u(0x00000040)
+#define PWM_INTE_CH6_MSB _u(6)
+#define PWM_INTE_CH6_LSB _u(6)
+#define PWM_INTE_CH6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH5
+// Description : None
+#define PWM_INTE_CH5_RESET _u(0x0)
+#define PWM_INTE_CH5_BITS _u(0x00000020)
+#define PWM_INTE_CH5_MSB _u(5)
+#define PWM_INTE_CH5_LSB _u(5)
+#define PWM_INTE_CH5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH4
+// Description : None
+#define PWM_INTE_CH4_RESET _u(0x0)
+#define PWM_INTE_CH4_BITS _u(0x00000010)
+#define PWM_INTE_CH4_MSB _u(4)
+#define PWM_INTE_CH4_LSB _u(4)
+#define PWM_INTE_CH4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH3
+// Description : None
+#define PWM_INTE_CH3_RESET _u(0x0)
+#define PWM_INTE_CH3_BITS _u(0x00000008)
+#define PWM_INTE_CH3_MSB _u(3)
+#define PWM_INTE_CH3_LSB _u(3)
+#define PWM_INTE_CH3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH2
+// Description : None
+#define PWM_INTE_CH2_RESET _u(0x0)
+#define PWM_INTE_CH2_BITS _u(0x00000004)
+#define PWM_INTE_CH2_MSB _u(2)
+#define PWM_INTE_CH2_LSB _u(2)
+#define PWM_INTE_CH2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH1
+// Description : None
+#define PWM_INTE_CH1_RESET _u(0x0)
+#define PWM_INTE_CH1_BITS _u(0x00000002)
+#define PWM_INTE_CH1_MSB _u(1)
+#define PWM_INTE_CH1_LSB _u(1)
+#define PWM_INTE_CH1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTE_CH0
+// Description : None
+#define PWM_INTE_CH0_RESET _u(0x0)
+#define PWM_INTE_CH0_BITS _u(0x00000001)
+#define PWM_INTE_CH0_MSB _u(0)
+#define PWM_INTE_CH0_LSB _u(0)
+#define PWM_INTE_CH0_ACCESS "RW"
+// =============================================================================
+// Register : PWM_INTF
+// Description : Interrupt Force
+#define PWM_INTF_OFFSET _u(0x000000ac)
+#define PWM_INTF_BITS _u(0x000000ff)
+#define PWM_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH7
+// Description : None
+#define PWM_INTF_CH7_RESET _u(0x0)
+#define PWM_INTF_CH7_BITS _u(0x00000080)
+#define PWM_INTF_CH7_MSB _u(7)
+#define PWM_INTF_CH7_LSB _u(7)
+#define PWM_INTF_CH7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH6
+// Description : None
+#define PWM_INTF_CH6_RESET _u(0x0)
+#define PWM_INTF_CH6_BITS _u(0x00000040)
+#define PWM_INTF_CH6_MSB _u(6)
+#define PWM_INTF_CH6_LSB _u(6)
+#define PWM_INTF_CH6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH5
+// Description : None
+#define PWM_INTF_CH5_RESET _u(0x0)
+#define PWM_INTF_CH5_BITS _u(0x00000020)
+#define PWM_INTF_CH5_MSB _u(5)
+#define PWM_INTF_CH5_LSB _u(5)
+#define PWM_INTF_CH5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH4
+// Description : None
+#define PWM_INTF_CH4_RESET _u(0x0)
+#define PWM_INTF_CH4_BITS _u(0x00000010)
+#define PWM_INTF_CH4_MSB _u(4)
+#define PWM_INTF_CH4_LSB _u(4)
+#define PWM_INTF_CH4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH3
+// Description : None
+#define PWM_INTF_CH3_RESET _u(0x0)
+#define PWM_INTF_CH3_BITS _u(0x00000008)
+#define PWM_INTF_CH3_MSB _u(3)
+#define PWM_INTF_CH3_LSB _u(3)
+#define PWM_INTF_CH3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH2
+// Description : None
+#define PWM_INTF_CH2_RESET _u(0x0)
+#define PWM_INTF_CH2_BITS _u(0x00000004)
+#define PWM_INTF_CH2_MSB _u(2)
+#define PWM_INTF_CH2_LSB _u(2)
+#define PWM_INTF_CH2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH1
+// Description : None
+#define PWM_INTF_CH1_RESET _u(0x0)
+#define PWM_INTF_CH1_BITS _u(0x00000002)
+#define PWM_INTF_CH1_MSB _u(1)
+#define PWM_INTF_CH1_LSB _u(1)
+#define PWM_INTF_CH1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTF_CH0
+// Description : None
+#define PWM_INTF_CH0_RESET _u(0x0)
+#define PWM_INTF_CH0_BITS _u(0x00000001)
+#define PWM_INTF_CH0_MSB _u(0)
+#define PWM_INTF_CH0_LSB _u(0)
+#define PWM_INTF_CH0_ACCESS "RW"
+// =============================================================================
+// Register : PWM_INTS
+// Description : Interrupt status after masking & forcing
+#define PWM_INTS_OFFSET _u(0x000000b0)
+#define PWM_INTS_BITS _u(0x000000ff)
+#define PWM_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH7
+// Description : None
+#define PWM_INTS_CH7_RESET _u(0x0)
+#define PWM_INTS_CH7_BITS _u(0x00000080)
+#define PWM_INTS_CH7_MSB _u(7)
+#define PWM_INTS_CH7_LSB _u(7)
+#define PWM_INTS_CH7_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH6
+// Description : None
+#define PWM_INTS_CH6_RESET _u(0x0)
+#define PWM_INTS_CH6_BITS _u(0x00000040)
+#define PWM_INTS_CH6_MSB _u(6)
+#define PWM_INTS_CH6_LSB _u(6)
+#define PWM_INTS_CH6_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH5
+// Description : None
+#define PWM_INTS_CH5_RESET _u(0x0)
+#define PWM_INTS_CH5_BITS _u(0x00000020)
+#define PWM_INTS_CH5_MSB _u(5)
+#define PWM_INTS_CH5_LSB _u(5)
+#define PWM_INTS_CH5_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH4
+// Description : None
+#define PWM_INTS_CH4_RESET _u(0x0)
+#define PWM_INTS_CH4_BITS _u(0x00000010)
+#define PWM_INTS_CH4_MSB _u(4)
+#define PWM_INTS_CH4_LSB _u(4)
+#define PWM_INTS_CH4_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH3
+// Description : None
+#define PWM_INTS_CH3_RESET _u(0x0)
+#define PWM_INTS_CH3_BITS _u(0x00000008)
+#define PWM_INTS_CH3_MSB _u(3)
+#define PWM_INTS_CH3_LSB _u(3)
+#define PWM_INTS_CH3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH2
+// Description : None
+#define PWM_INTS_CH2_RESET _u(0x0)
+#define PWM_INTS_CH2_BITS _u(0x00000004)
+#define PWM_INTS_CH2_MSB _u(2)
+#define PWM_INTS_CH2_LSB _u(2)
+#define PWM_INTS_CH2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH1
+// Description : None
+#define PWM_INTS_CH1_RESET _u(0x0)
+#define PWM_INTS_CH1_BITS _u(0x00000002)
+#define PWM_INTS_CH1_MSB _u(1)
+#define PWM_INTS_CH1_LSB _u(1)
+#define PWM_INTS_CH1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : PWM_INTS_CH0
+// Description : None
+#define PWM_INTS_CH0_RESET _u(0x0)
+#define PWM_INTS_CH0_BITS _u(0x00000001)
+#define PWM_INTS_CH0_MSB _u(0)
+#define PWM_INTS_CH0_LSB _u(0)
+#define PWM_INTS_CH0_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_PWM_DEFINED
diff --git a/arkanoid/pico/hardware/regs/resets.h b/arkanoid/pico/hardware/regs/resets.h
new file mode 100644
index 0000000..689a358
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/resets.h
@@ -0,0 +1,637 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : RESETS
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_RESETS_DEFINED
+#define HARDWARE_REGS_RESETS_DEFINED
+// =============================================================================
+// Register : RESETS_RESET
+// Description : Reset control. If a bit is set it means the peripheral is in
+// reset. 0 means the peripheral's reset is deasserted.
+#define RESETS_RESET_OFFSET _u(0x00000000)
+#define RESETS_RESET_BITS _u(0x01ffffff)
+#define RESETS_RESET_RESET _u(0x01ffffff)
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_USBCTRL
+// Description : None
+#define RESETS_RESET_USBCTRL_RESET _u(0x1)
+#define RESETS_RESET_USBCTRL_BITS _u(0x01000000)
+#define RESETS_RESET_USBCTRL_MSB _u(24)
+#define RESETS_RESET_USBCTRL_LSB _u(24)
+#define RESETS_RESET_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_UART1
+// Description : None
+#define RESETS_RESET_UART1_RESET _u(0x1)
+#define RESETS_RESET_UART1_BITS _u(0x00800000)
+#define RESETS_RESET_UART1_MSB _u(23)
+#define RESETS_RESET_UART1_LSB _u(23)
+#define RESETS_RESET_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_UART0
+// Description : None
+#define RESETS_RESET_UART0_RESET _u(0x1)
+#define RESETS_RESET_UART0_BITS _u(0x00400000)
+#define RESETS_RESET_UART0_MSB _u(22)
+#define RESETS_RESET_UART0_LSB _u(22)
+#define RESETS_RESET_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_TIMER
+// Description : None
+#define RESETS_RESET_TIMER_RESET _u(0x1)
+#define RESETS_RESET_TIMER_BITS _u(0x00200000)
+#define RESETS_RESET_TIMER_MSB _u(21)
+#define RESETS_RESET_TIMER_LSB _u(21)
+#define RESETS_RESET_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_TBMAN
+// Description : None
+#define RESETS_RESET_TBMAN_RESET _u(0x1)
+#define RESETS_RESET_TBMAN_BITS _u(0x00100000)
+#define RESETS_RESET_TBMAN_MSB _u(20)
+#define RESETS_RESET_TBMAN_LSB _u(20)
+#define RESETS_RESET_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_SYSINFO
+// Description : None
+#define RESETS_RESET_SYSINFO_RESET _u(0x1)
+#define RESETS_RESET_SYSINFO_BITS _u(0x00080000)
+#define RESETS_RESET_SYSINFO_MSB _u(19)
+#define RESETS_RESET_SYSINFO_LSB _u(19)
+#define RESETS_RESET_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_SYSCFG
+// Description : None
+#define RESETS_RESET_SYSCFG_RESET _u(0x1)
+#define RESETS_RESET_SYSCFG_BITS _u(0x00040000)
+#define RESETS_RESET_SYSCFG_MSB _u(18)
+#define RESETS_RESET_SYSCFG_LSB _u(18)
+#define RESETS_RESET_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_SPI1
+// Description : None
+#define RESETS_RESET_SPI1_RESET _u(0x1)
+#define RESETS_RESET_SPI1_BITS _u(0x00020000)
+#define RESETS_RESET_SPI1_MSB _u(17)
+#define RESETS_RESET_SPI1_LSB _u(17)
+#define RESETS_RESET_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_SPI0
+// Description : None
+#define RESETS_RESET_SPI0_RESET _u(0x1)
+#define RESETS_RESET_SPI0_BITS _u(0x00010000)
+#define RESETS_RESET_SPI0_MSB _u(16)
+#define RESETS_RESET_SPI0_LSB _u(16)
+#define RESETS_RESET_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_RTC
+// Description : None
+#define RESETS_RESET_RTC_RESET _u(0x1)
+#define RESETS_RESET_RTC_BITS _u(0x00008000)
+#define RESETS_RESET_RTC_MSB _u(15)
+#define RESETS_RESET_RTC_LSB _u(15)
+#define RESETS_RESET_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_PWM
+// Description : None
+#define RESETS_RESET_PWM_RESET _u(0x1)
+#define RESETS_RESET_PWM_BITS _u(0x00004000)
+#define RESETS_RESET_PWM_MSB _u(14)
+#define RESETS_RESET_PWM_LSB _u(14)
+#define RESETS_RESET_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_PLL_USB
+// Description : None
+#define RESETS_RESET_PLL_USB_RESET _u(0x1)
+#define RESETS_RESET_PLL_USB_BITS _u(0x00002000)
+#define RESETS_RESET_PLL_USB_MSB _u(13)
+#define RESETS_RESET_PLL_USB_LSB _u(13)
+#define RESETS_RESET_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_PLL_SYS
+// Description : None
+#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
+#define RESETS_RESET_PLL_SYS_BITS _u(0x00001000)
+#define RESETS_RESET_PLL_SYS_MSB _u(12)
+#define RESETS_RESET_PLL_SYS_LSB _u(12)
+#define RESETS_RESET_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_PIO1
+// Description : None
+#define RESETS_RESET_PIO1_RESET _u(0x1)
+#define RESETS_RESET_PIO1_BITS _u(0x00000800)
+#define RESETS_RESET_PIO1_MSB _u(11)
+#define RESETS_RESET_PIO1_LSB _u(11)
+#define RESETS_RESET_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_PIO0
+// Description : None
+#define RESETS_RESET_PIO0_RESET _u(0x1)
+#define RESETS_RESET_PIO0_BITS _u(0x00000400)
+#define RESETS_RESET_PIO0_MSB _u(10)
+#define RESETS_RESET_PIO0_LSB _u(10)
+#define RESETS_RESET_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_PADS_QSPI
+// Description : None
+#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
+#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000200)
+#define RESETS_RESET_PADS_QSPI_MSB _u(9)
+#define RESETS_RESET_PADS_QSPI_LSB _u(9)
+#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_PADS_BANK0
+// Description : None
+#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
+#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000100)
+#define RESETS_RESET_PADS_BANK0_MSB _u(8)
+#define RESETS_RESET_PADS_BANK0_LSB _u(8)
+#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_JTAG
+// Description : None
+#define RESETS_RESET_JTAG_RESET _u(0x1)
+#define RESETS_RESET_JTAG_BITS _u(0x00000080)
+#define RESETS_RESET_JTAG_MSB _u(7)
+#define RESETS_RESET_JTAG_LSB _u(7)
+#define RESETS_RESET_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_IO_QSPI
+// Description : None
+#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
+#define RESETS_RESET_IO_QSPI_BITS _u(0x00000040)
+#define RESETS_RESET_IO_QSPI_MSB _u(6)
+#define RESETS_RESET_IO_QSPI_LSB _u(6)
+#define RESETS_RESET_IO_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_IO_BANK0
+// Description : None
+#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
+#define RESETS_RESET_IO_BANK0_BITS _u(0x00000020)
+#define RESETS_RESET_IO_BANK0_MSB _u(5)
+#define RESETS_RESET_IO_BANK0_LSB _u(5)
+#define RESETS_RESET_IO_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_I2C1
+// Description : None
+#define RESETS_RESET_I2C1_RESET _u(0x1)
+#define RESETS_RESET_I2C1_BITS _u(0x00000010)
+#define RESETS_RESET_I2C1_MSB _u(4)
+#define RESETS_RESET_I2C1_LSB _u(4)
+#define RESETS_RESET_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_I2C0
+// Description : None
+#define RESETS_RESET_I2C0_RESET _u(0x1)
+#define RESETS_RESET_I2C0_BITS _u(0x00000008)
+#define RESETS_RESET_I2C0_MSB _u(3)
+#define RESETS_RESET_I2C0_LSB _u(3)
+#define RESETS_RESET_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DMA
+// Description : None
+#define RESETS_RESET_DMA_RESET _u(0x1)
+#define RESETS_RESET_DMA_BITS _u(0x00000004)
+#define RESETS_RESET_DMA_MSB _u(2)
+#define RESETS_RESET_DMA_LSB _u(2)
+#define RESETS_RESET_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_BUSCTRL
+// Description : None
+#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
+#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
+#define RESETS_RESET_BUSCTRL_MSB _u(1)
+#define RESETS_RESET_BUSCTRL_LSB _u(1)
+#define RESETS_RESET_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_ADC
+// Description : None
+#define RESETS_RESET_ADC_RESET _u(0x1)
+#define RESETS_RESET_ADC_BITS _u(0x00000001)
+#define RESETS_RESET_ADC_MSB _u(0)
+#define RESETS_RESET_ADC_LSB _u(0)
+#define RESETS_RESET_ADC_ACCESS "RW"
+// =============================================================================
+// Register : RESETS_WDSEL
+// Description : Watchdog select. If a bit is set then the watchdog will reset
+// this peripheral when the watchdog fires.
+#define RESETS_WDSEL_OFFSET _u(0x00000004)
+#define RESETS_WDSEL_BITS _u(0x01ffffff)
+#define RESETS_WDSEL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_USBCTRL
+// Description : None
+#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
+#define RESETS_WDSEL_USBCTRL_BITS _u(0x01000000)
+#define RESETS_WDSEL_USBCTRL_MSB _u(24)
+#define RESETS_WDSEL_USBCTRL_LSB _u(24)
+#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_UART1
+// Description : None
+#define RESETS_WDSEL_UART1_RESET _u(0x0)
+#define RESETS_WDSEL_UART1_BITS _u(0x00800000)
+#define RESETS_WDSEL_UART1_MSB _u(23)
+#define RESETS_WDSEL_UART1_LSB _u(23)
+#define RESETS_WDSEL_UART1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_UART0
+// Description : None
+#define RESETS_WDSEL_UART0_RESET _u(0x0)
+#define RESETS_WDSEL_UART0_BITS _u(0x00400000)
+#define RESETS_WDSEL_UART0_MSB _u(22)
+#define RESETS_WDSEL_UART0_LSB _u(22)
+#define RESETS_WDSEL_UART0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_TIMER
+// Description : None
+#define RESETS_WDSEL_TIMER_RESET _u(0x0)
+#define RESETS_WDSEL_TIMER_BITS _u(0x00200000)
+#define RESETS_WDSEL_TIMER_MSB _u(21)
+#define RESETS_WDSEL_TIMER_LSB _u(21)
+#define RESETS_WDSEL_TIMER_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_TBMAN
+// Description : None
+#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
+#define RESETS_WDSEL_TBMAN_BITS _u(0x00100000)
+#define RESETS_WDSEL_TBMAN_MSB _u(20)
+#define RESETS_WDSEL_TBMAN_LSB _u(20)
+#define RESETS_WDSEL_TBMAN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_SYSINFO
+// Description : None
+#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
+#define RESETS_WDSEL_SYSINFO_BITS _u(0x00080000)
+#define RESETS_WDSEL_SYSINFO_MSB _u(19)
+#define RESETS_WDSEL_SYSINFO_LSB _u(19)
+#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_SYSCFG
+// Description : None
+#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
+#define RESETS_WDSEL_SYSCFG_BITS _u(0x00040000)
+#define RESETS_WDSEL_SYSCFG_MSB _u(18)
+#define RESETS_WDSEL_SYSCFG_LSB _u(18)
+#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_SPI1
+// Description : None
+#define RESETS_WDSEL_SPI1_RESET _u(0x0)
+#define RESETS_WDSEL_SPI1_BITS _u(0x00020000)
+#define RESETS_WDSEL_SPI1_MSB _u(17)
+#define RESETS_WDSEL_SPI1_LSB _u(17)
+#define RESETS_WDSEL_SPI1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_SPI0
+// Description : None
+#define RESETS_WDSEL_SPI0_RESET _u(0x0)
+#define RESETS_WDSEL_SPI0_BITS _u(0x00010000)
+#define RESETS_WDSEL_SPI0_MSB _u(16)
+#define RESETS_WDSEL_SPI0_LSB _u(16)
+#define RESETS_WDSEL_SPI0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_RTC
+// Description : None
+#define RESETS_WDSEL_RTC_RESET _u(0x0)
+#define RESETS_WDSEL_RTC_BITS _u(0x00008000)
+#define RESETS_WDSEL_RTC_MSB _u(15)
+#define RESETS_WDSEL_RTC_LSB _u(15)
+#define RESETS_WDSEL_RTC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_PWM
+// Description : None
+#define RESETS_WDSEL_PWM_RESET _u(0x0)
+#define RESETS_WDSEL_PWM_BITS _u(0x00004000)
+#define RESETS_WDSEL_PWM_MSB _u(14)
+#define RESETS_WDSEL_PWM_LSB _u(14)
+#define RESETS_WDSEL_PWM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_PLL_USB
+// Description : None
+#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
+#define RESETS_WDSEL_PLL_USB_BITS _u(0x00002000)
+#define RESETS_WDSEL_PLL_USB_MSB _u(13)
+#define RESETS_WDSEL_PLL_USB_LSB _u(13)
+#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_PLL_SYS
+// Description : None
+#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
+#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00001000)
+#define RESETS_WDSEL_PLL_SYS_MSB _u(12)
+#define RESETS_WDSEL_PLL_SYS_LSB _u(12)
+#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_PIO1
+// Description : None
+#define RESETS_WDSEL_PIO1_RESET _u(0x0)
+#define RESETS_WDSEL_PIO1_BITS _u(0x00000800)
+#define RESETS_WDSEL_PIO1_MSB _u(11)
+#define RESETS_WDSEL_PIO1_LSB _u(11)
+#define RESETS_WDSEL_PIO1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_PIO0
+// Description : None
+#define RESETS_WDSEL_PIO0_RESET _u(0x0)
+#define RESETS_WDSEL_PIO0_BITS _u(0x00000400)
+#define RESETS_WDSEL_PIO0_MSB _u(10)
+#define RESETS_WDSEL_PIO0_LSB _u(10)
+#define RESETS_WDSEL_PIO0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_PADS_QSPI
+// Description : None
+#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
+#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000200)
+#define RESETS_WDSEL_PADS_QSPI_MSB _u(9)
+#define RESETS_WDSEL_PADS_QSPI_LSB _u(9)
+#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_PADS_BANK0
+// Description : None
+#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
+#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000100)
+#define RESETS_WDSEL_PADS_BANK0_MSB _u(8)
+#define RESETS_WDSEL_PADS_BANK0_LSB _u(8)
+#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_JTAG
+// Description : None
+#define RESETS_WDSEL_JTAG_RESET _u(0x0)
+#define RESETS_WDSEL_JTAG_BITS _u(0x00000080)
+#define RESETS_WDSEL_JTAG_MSB _u(7)
+#define RESETS_WDSEL_JTAG_LSB _u(7)
+#define RESETS_WDSEL_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_IO_QSPI
+// Description : None
+#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
+#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000040)
+#define RESETS_WDSEL_IO_QSPI_MSB _u(6)
+#define RESETS_WDSEL_IO_QSPI_LSB _u(6)
+#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_IO_BANK0
+// Description : None
+#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
+#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000020)
+#define RESETS_WDSEL_IO_BANK0_MSB _u(5)
+#define RESETS_WDSEL_IO_BANK0_LSB _u(5)
+#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_I2C1
+// Description : None
+#define RESETS_WDSEL_I2C1_RESET _u(0x0)
+#define RESETS_WDSEL_I2C1_BITS _u(0x00000010)
+#define RESETS_WDSEL_I2C1_MSB _u(4)
+#define RESETS_WDSEL_I2C1_LSB _u(4)
+#define RESETS_WDSEL_I2C1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_I2C0
+// Description : None
+#define RESETS_WDSEL_I2C0_RESET _u(0x0)
+#define RESETS_WDSEL_I2C0_BITS _u(0x00000008)
+#define RESETS_WDSEL_I2C0_MSB _u(3)
+#define RESETS_WDSEL_I2C0_LSB _u(3)
+#define RESETS_WDSEL_I2C0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_DMA
+// Description : None
+#define RESETS_WDSEL_DMA_RESET _u(0x0)
+#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
+#define RESETS_WDSEL_DMA_MSB _u(2)
+#define RESETS_WDSEL_DMA_LSB _u(2)
+#define RESETS_WDSEL_DMA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_BUSCTRL
+// Description : None
+#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
+#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
+#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
+#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
+#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RESETS_WDSEL_ADC
+// Description : None
+#define RESETS_WDSEL_ADC_RESET _u(0x0)
+#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
+#define RESETS_WDSEL_ADC_MSB _u(0)
+#define RESETS_WDSEL_ADC_LSB _u(0)
+#define RESETS_WDSEL_ADC_ACCESS "RW"
+// =============================================================================
+// Register : RESETS_RESET_DONE
+// Description : Reset done. If a bit is set then a reset done signal has been
+// returned by the peripheral. This indicates that the
+// peripheral's registers are ready to be accessed.
+#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
+#define RESETS_RESET_DONE_BITS _u(0x01ffffff)
+#define RESETS_RESET_DONE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_USBCTRL
+// Description : None
+#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
+#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x01000000)
+#define RESETS_RESET_DONE_USBCTRL_MSB _u(24)
+#define RESETS_RESET_DONE_USBCTRL_LSB _u(24)
+#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_UART1
+// Description : None
+#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
+#define RESETS_RESET_DONE_UART1_BITS _u(0x00800000)
+#define RESETS_RESET_DONE_UART1_MSB _u(23)
+#define RESETS_RESET_DONE_UART1_LSB _u(23)
+#define RESETS_RESET_DONE_UART1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_UART0
+// Description : None
+#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
+#define RESETS_RESET_DONE_UART0_BITS _u(0x00400000)
+#define RESETS_RESET_DONE_UART0_MSB _u(22)
+#define RESETS_RESET_DONE_UART0_LSB _u(22)
+#define RESETS_RESET_DONE_UART0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_TIMER
+// Description : None
+#define RESETS_RESET_DONE_TIMER_RESET _u(0x0)
+#define RESETS_RESET_DONE_TIMER_BITS _u(0x00200000)
+#define RESETS_RESET_DONE_TIMER_MSB _u(21)
+#define RESETS_RESET_DONE_TIMER_LSB _u(21)
+#define RESETS_RESET_DONE_TIMER_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_TBMAN
+// Description : None
+#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
+#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00100000)
+#define RESETS_RESET_DONE_TBMAN_MSB _u(20)
+#define RESETS_RESET_DONE_TBMAN_LSB _u(20)
+#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_SYSINFO
+// Description : None
+#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
+#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00080000)
+#define RESETS_RESET_DONE_SYSINFO_MSB _u(19)
+#define RESETS_RESET_DONE_SYSINFO_LSB _u(19)
+#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_SYSCFG
+// Description : None
+#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
+#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00040000)
+#define RESETS_RESET_DONE_SYSCFG_MSB _u(18)
+#define RESETS_RESET_DONE_SYSCFG_LSB _u(18)
+#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_SPI1
+// Description : None
+#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
+#define RESETS_RESET_DONE_SPI1_BITS _u(0x00020000)
+#define RESETS_RESET_DONE_SPI1_MSB _u(17)
+#define RESETS_RESET_DONE_SPI1_LSB _u(17)
+#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_SPI0
+// Description : None
+#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
+#define RESETS_RESET_DONE_SPI0_BITS _u(0x00010000)
+#define RESETS_RESET_DONE_SPI0_MSB _u(16)
+#define RESETS_RESET_DONE_SPI0_LSB _u(16)
+#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_RTC
+// Description : None
+#define RESETS_RESET_DONE_RTC_RESET _u(0x0)
+#define RESETS_RESET_DONE_RTC_BITS _u(0x00008000)
+#define RESETS_RESET_DONE_RTC_MSB _u(15)
+#define RESETS_RESET_DONE_RTC_LSB _u(15)
+#define RESETS_RESET_DONE_RTC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_PWM
+// Description : None
+#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
+#define RESETS_RESET_DONE_PWM_BITS _u(0x00004000)
+#define RESETS_RESET_DONE_PWM_MSB _u(14)
+#define RESETS_RESET_DONE_PWM_LSB _u(14)
+#define RESETS_RESET_DONE_PWM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_PLL_USB
+// Description : None
+#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
+#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00002000)
+#define RESETS_RESET_DONE_PLL_USB_MSB _u(13)
+#define RESETS_RESET_DONE_PLL_USB_LSB _u(13)
+#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_PLL_SYS
+// Description : None
+#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
+#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00001000)
+#define RESETS_RESET_DONE_PLL_SYS_MSB _u(12)
+#define RESETS_RESET_DONE_PLL_SYS_LSB _u(12)
+#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_PIO1
+// Description : None
+#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
+#define RESETS_RESET_DONE_PIO1_BITS _u(0x00000800)
+#define RESETS_RESET_DONE_PIO1_MSB _u(11)
+#define RESETS_RESET_DONE_PIO1_LSB _u(11)
+#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_PIO0
+// Description : None
+#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
+#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000400)
+#define RESETS_RESET_DONE_PIO0_MSB _u(10)
+#define RESETS_RESET_DONE_PIO0_LSB _u(10)
+#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_PADS_QSPI
+// Description : None
+#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
+#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000200)
+#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(9)
+#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(9)
+#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_PADS_BANK0
+// Description : None
+#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
+#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000100)
+#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(8)
+#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(8)
+#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_JTAG
+// Description : None
+#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
+#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000080)
+#define RESETS_RESET_DONE_JTAG_MSB _u(7)
+#define RESETS_RESET_DONE_JTAG_LSB _u(7)
+#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_IO_QSPI
+// Description : None
+#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
+#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000040)
+#define RESETS_RESET_DONE_IO_QSPI_MSB _u(6)
+#define RESETS_RESET_DONE_IO_QSPI_LSB _u(6)
+#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_IO_BANK0
+// Description : None
+#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
+#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000020)
+#define RESETS_RESET_DONE_IO_BANK0_MSB _u(5)
+#define RESETS_RESET_DONE_IO_BANK0_LSB _u(5)
+#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_I2C1
+// Description : None
+#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
+#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000010)
+#define RESETS_RESET_DONE_I2C1_MSB _u(4)
+#define RESETS_RESET_DONE_I2C1_LSB _u(4)
+#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_I2C0
+// Description : None
+#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
+#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000008)
+#define RESETS_RESET_DONE_I2C0_MSB _u(3)
+#define RESETS_RESET_DONE_I2C0_LSB _u(3)
+#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_DMA
+// Description : None
+#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
+#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
+#define RESETS_RESET_DONE_DMA_MSB _u(2)
+#define RESETS_RESET_DONE_DMA_LSB _u(2)
+#define RESETS_RESET_DONE_DMA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_BUSCTRL
+// Description : None
+#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
+#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
+#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
+#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
+#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RESETS_RESET_DONE_ADC
+// Description : None
+#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
+#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
+#define RESETS_RESET_DONE_ADC_MSB _u(0)
+#define RESETS_RESET_DONE_ADC_LSB _u(0)
+#define RESETS_RESET_DONE_ADC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_RESETS_DEFINED
diff --git a/arkanoid/pico/hardware/regs/rosc.h b/arkanoid/pico/hardware/regs/rosc.h
new file mode 100644
index 0000000..5501e7e
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/rosc.h
@@ -0,0 +1,312 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : ROSC
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_ROSC_DEFINED
+#define HARDWARE_REGS_ROSC_DEFINED
+// =============================================================================
+// Register : ROSC_CTRL
+// Description : Ring Oscillator control
+#define ROSC_CTRL_OFFSET _u(0x00000000)
+#define ROSC_CTRL_BITS _u(0x00ffffff)
+#define ROSC_CTRL_RESET _u(0x00000aa0)
+// -----------------------------------------------------------------------------
+// Field : ROSC_CTRL_ENABLE
+// Description : On power-up this field is initialised to ENABLE
+// The system clock must be switched to another source before
+// setting this field to DISABLE otherwise the chip will lock up
+// The 12-bit code is intended to give some protection against
+// accidental writes. An invalid setting will enable the
+// oscillator.
+// 0xd1e -> DISABLE
+// 0xfab -> ENABLE
+#define ROSC_CTRL_ENABLE_RESET "-"
+#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
+#define ROSC_CTRL_ENABLE_MSB _u(23)
+#define ROSC_CTRL_ENABLE_LSB _u(12)
+#define ROSC_CTRL_ENABLE_ACCESS "RW"
+#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
+#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
+// -----------------------------------------------------------------------------
+// Field : ROSC_CTRL_FREQ_RANGE
+// Description : Controls the number of delay stages in the ROSC ring
+// LOW uses stages 0 to 7
+// MEDIUM uses stages 0 to 5
+// HIGH uses stages 0 to 3
+// TOOHIGH uses stages 0 to 1 and should not be used because its
+// frequency exceeds design specifications
+// The clock output will not glitch when changing the range up one
+// step at a time
+// The clock output will glitch when changing the range down
+// Note: the values here are gray coded which is why HIGH comes
+// before TOOHIGH
+// 0xfa4 -> LOW
+// 0xfa5 -> MEDIUM
+// 0xfa7 -> HIGH
+// 0xfa6 -> TOOHIGH
+#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
+#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
+#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
+#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
+#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
+#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
+#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
+// =============================================================================
+// Register : ROSC_FREQA
+// Description : The FREQA & FREQB registers control the frequency by
+// controlling the drive strength of each stage
+// The drive strength has 4 levels determined by the number of
+// bits set
+// Increasing the number of bits set increases the drive strength
+// and increases the oscillation frequency
+// 0 bits set is the default drive strength
+// 1 bit set doubles the drive strength
+// 2 bits set triples drive strength
+// 3 bits set quadruples drive strength
+#define ROSC_FREQA_OFFSET _u(0x00000004)
+#define ROSC_FREQA_BITS _u(0xffff7777)
+#define ROSC_FREQA_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQA_PASSWD
+// Description : Set to 0x9696 to apply the settings
+// Any other value in this field will set all drive strengths to 0
+// 0x9696 -> PASS
+#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
+#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
+#define ROSC_FREQA_PASSWD_MSB _u(31)
+#define ROSC_FREQA_PASSWD_LSB _u(16)
+#define ROSC_FREQA_PASSWD_ACCESS "RW"
+#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQA_DS3
+// Description : Stage 3 drive strength
+#define ROSC_FREQA_DS3_RESET _u(0x0)
+#define ROSC_FREQA_DS3_BITS _u(0x00007000)
+#define ROSC_FREQA_DS3_MSB _u(14)
+#define ROSC_FREQA_DS3_LSB _u(12)
+#define ROSC_FREQA_DS3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQA_DS2
+// Description : Stage 2 drive strength
+#define ROSC_FREQA_DS2_RESET _u(0x0)
+#define ROSC_FREQA_DS2_BITS _u(0x00000700)
+#define ROSC_FREQA_DS2_MSB _u(10)
+#define ROSC_FREQA_DS2_LSB _u(8)
+#define ROSC_FREQA_DS2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQA_DS1
+// Description : Stage 1 drive strength
+#define ROSC_FREQA_DS1_RESET _u(0x0)
+#define ROSC_FREQA_DS1_BITS _u(0x00000070)
+#define ROSC_FREQA_DS1_MSB _u(6)
+#define ROSC_FREQA_DS1_LSB _u(4)
+#define ROSC_FREQA_DS1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQA_DS0
+// Description : Stage 0 drive strength
+#define ROSC_FREQA_DS0_RESET _u(0x0)
+#define ROSC_FREQA_DS0_BITS _u(0x00000007)
+#define ROSC_FREQA_DS0_MSB _u(2)
+#define ROSC_FREQA_DS0_LSB _u(0)
+#define ROSC_FREQA_DS0_ACCESS "RW"
+// =============================================================================
+// Register : ROSC_FREQB
+// Description : For a detailed description see freqa register
+#define ROSC_FREQB_OFFSET _u(0x00000008)
+#define ROSC_FREQB_BITS _u(0xffff7777)
+#define ROSC_FREQB_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQB_PASSWD
+// Description : Set to 0x9696 to apply the settings
+// Any other value in this field will set all drive strengths to 0
+// 0x9696 -> PASS
+#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
+#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
+#define ROSC_FREQB_PASSWD_MSB _u(31)
+#define ROSC_FREQB_PASSWD_LSB _u(16)
+#define ROSC_FREQB_PASSWD_ACCESS "RW"
+#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQB_DS7
+// Description : Stage 7 drive strength
+#define ROSC_FREQB_DS7_RESET _u(0x0)
+#define ROSC_FREQB_DS7_BITS _u(0x00007000)
+#define ROSC_FREQB_DS7_MSB _u(14)
+#define ROSC_FREQB_DS7_LSB _u(12)
+#define ROSC_FREQB_DS7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQB_DS6
+// Description : Stage 6 drive strength
+#define ROSC_FREQB_DS6_RESET _u(0x0)
+#define ROSC_FREQB_DS6_BITS _u(0x00000700)
+#define ROSC_FREQB_DS6_MSB _u(10)
+#define ROSC_FREQB_DS6_LSB _u(8)
+#define ROSC_FREQB_DS6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQB_DS5
+// Description : Stage 5 drive strength
+#define ROSC_FREQB_DS5_RESET _u(0x0)
+#define ROSC_FREQB_DS5_BITS _u(0x00000070)
+#define ROSC_FREQB_DS5_MSB _u(6)
+#define ROSC_FREQB_DS5_LSB _u(4)
+#define ROSC_FREQB_DS5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_FREQB_DS4
+// Description : Stage 4 drive strength
+#define ROSC_FREQB_DS4_RESET _u(0x0)
+#define ROSC_FREQB_DS4_BITS _u(0x00000007)
+#define ROSC_FREQB_DS4_MSB _u(2)
+#define ROSC_FREQB_DS4_LSB _u(0)
+#define ROSC_FREQB_DS4_ACCESS "RW"
+// =============================================================================
+// Register : ROSC_DORMANT
+// Description : Ring Oscillator pause control
+// This is used to save power by pausing the ROSC
+// On power-up this field is initialised to WAKE
+// An invalid write will also select WAKE
+// Warning: setup the irq before selecting dormant mode
+// 0x636f6d61 -> DORMANT
+// 0x77616b65 -> WAKE
+#define ROSC_DORMANT_OFFSET _u(0x0000000c)
+#define ROSC_DORMANT_BITS _u(0xffffffff)
+#define ROSC_DORMANT_RESET "-"
+#define ROSC_DORMANT_MSB _u(31)
+#define ROSC_DORMANT_LSB _u(0)
+#define ROSC_DORMANT_ACCESS "RW"
+#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
+#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
+// =============================================================================
+// Register : ROSC_DIV
+// Description : Controls the output divider
+// set to 0xaa0 + div where
+// div = 0 divides by 32
+// div = 1-31 divides by div
+// any other value sets div=31
+// this register resets to div=16
+// 0xaa0 -> PASS
+#define ROSC_DIV_OFFSET _u(0x00000010)
+#define ROSC_DIV_BITS _u(0x00000fff)
+#define ROSC_DIV_RESET "-"
+#define ROSC_DIV_MSB _u(11)
+#define ROSC_DIV_LSB _u(0)
+#define ROSC_DIV_ACCESS "RW"
+#define ROSC_DIV_VALUE_PASS _u(0xaa0)
+// =============================================================================
+// Register : ROSC_PHASE
+// Description : Controls the phase shifted output
+#define ROSC_PHASE_OFFSET _u(0x00000014)
+#define ROSC_PHASE_BITS _u(0x00000fff)
+#define ROSC_PHASE_RESET _u(0x00000008)
+// -----------------------------------------------------------------------------
+// Field : ROSC_PHASE_PASSWD
+// Description : set to 0xaa
+// any other value enables the output with shift=0
+#define ROSC_PHASE_PASSWD_RESET _u(0x00)
+#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
+#define ROSC_PHASE_PASSWD_MSB _u(11)
+#define ROSC_PHASE_PASSWD_LSB _u(4)
+#define ROSC_PHASE_PASSWD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_PHASE_ENABLE
+// Description : enable the phase-shifted output
+// this can be changed on-the-fly
+#define ROSC_PHASE_ENABLE_RESET _u(0x1)
+#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
+#define ROSC_PHASE_ENABLE_MSB _u(3)
+#define ROSC_PHASE_ENABLE_LSB _u(3)
+#define ROSC_PHASE_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_PHASE_FLIP
+// Description : invert the phase-shifted output
+// this is ignored when div=1
+#define ROSC_PHASE_FLIP_RESET _u(0x0)
+#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
+#define ROSC_PHASE_FLIP_MSB _u(2)
+#define ROSC_PHASE_FLIP_LSB _u(2)
+#define ROSC_PHASE_FLIP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : ROSC_PHASE_SHIFT
+// Description : phase shift the phase-shifted output by SHIFT input clocks
+// this can be changed on-the-fly
+// must be set to 0 before setting div=1
+#define ROSC_PHASE_SHIFT_RESET _u(0x0)
+#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
+#define ROSC_PHASE_SHIFT_MSB _u(1)
+#define ROSC_PHASE_SHIFT_LSB _u(0)
+#define ROSC_PHASE_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register : ROSC_STATUS
+// Description : Ring Oscillator Status
+#define ROSC_STATUS_OFFSET _u(0x00000018)
+#define ROSC_STATUS_BITS _u(0x81011000)
+#define ROSC_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : ROSC_STATUS_STABLE
+// Description : Oscillator is running and stable
+#define ROSC_STATUS_STABLE_RESET _u(0x0)
+#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
+#define ROSC_STATUS_STABLE_MSB _u(31)
+#define ROSC_STATUS_STABLE_LSB _u(31)
+#define ROSC_STATUS_STABLE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : ROSC_STATUS_BADWRITE
+// Description : An invalid value has been written to CTRL_ENABLE or
+// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
+#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
+#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
+#define ROSC_STATUS_BADWRITE_MSB _u(24)
+#define ROSC_STATUS_BADWRITE_LSB _u(24)
+#define ROSC_STATUS_BADWRITE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : ROSC_STATUS_DIV_RUNNING
+// Description : post-divider is running
+// this resets to 0 but transitions to 1 during chip startup
+#define ROSC_STATUS_DIV_RUNNING_RESET "-"
+#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
+#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
+#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
+#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : ROSC_STATUS_ENABLED
+// Description : Oscillator is enabled but not necessarily running and stable
+// this resets to 0 but transitions to 1 during chip startup
+#define ROSC_STATUS_ENABLED_RESET "-"
+#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
+#define ROSC_STATUS_ENABLED_MSB _u(12)
+#define ROSC_STATUS_ENABLED_LSB _u(12)
+#define ROSC_STATUS_ENABLED_ACCESS "RO"
+// =============================================================================
+// Register : ROSC_RANDOMBIT
+// Description : This just reads the state of the oscillator output so
+// randomness is compromised if the ring oscillator is stopped or
+// run at a harmonic of the bus frequency
+#define ROSC_RANDOMBIT_OFFSET _u(0x0000001c)
+#define ROSC_RANDOMBIT_BITS _u(0x00000001)
+#define ROSC_RANDOMBIT_RESET _u(0x00000001)
+#define ROSC_RANDOMBIT_MSB _u(0)
+#define ROSC_RANDOMBIT_LSB _u(0)
+#define ROSC_RANDOMBIT_ACCESS "RO"
+// =============================================================================
+// Register : ROSC_COUNT
+// Description : A down counter running at the ROSC frequency which counts to
+// zero and stops.
+// To start the counter write a non-zero value.
+// Can be used for short software pauses when setting up time
+// sensitive hardware.
+#define ROSC_COUNT_OFFSET _u(0x00000020)
+#define ROSC_COUNT_BITS _u(0x000000ff)
+#define ROSC_COUNT_RESET _u(0x00000000)
+#define ROSC_COUNT_MSB _u(7)
+#define ROSC_COUNT_LSB _u(0)
+#define ROSC_COUNT_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_ROSC_DEFINED
diff --git a/arkanoid/pico/hardware/regs/rtc.h b/arkanoid/pico/hardware/regs/rtc.h
new file mode 100644
index 0000000..7d62c9d
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/rtc.h
@@ -0,0 +1,398 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : RTC
+// Version : 1
+// Bus type : apb
+// Description : Register block to control RTC
+// =============================================================================
+#ifndef HARDWARE_REGS_RTC_DEFINED
+#define HARDWARE_REGS_RTC_DEFINED
+// =============================================================================
+// Register : RTC_CLKDIV_M1
+// Description : Divider minus 1 for the 1 second counter. Safe to change the
+// value when RTC is not enabled.
+#define RTC_CLKDIV_M1_OFFSET _u(0x00000000)
+#define RTC_CLKDIV_M1_BITS _u(0x0000ffff)
+#define RTC_CLKDIV_M1_RESET _u(0x00000000)
+#define RTC_CLKDIV_M1_MSB _u(15)
+#define RTC_CLKDIV_M1_LSB _u(0)
+#define RTC_CLKDIV_M1_ACCESS "RW"
+// =============================================================================
+// Register : RTC_SETUP_0
+// Description : RTC setup register 0
+#define RTC_SETUP_0_OFFSET _u(0x00000004)
+#define RTC_SETUP_0_BITS _u(0x00ffff1f)
+#define RTC_SETUP_0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_SETUP_0_YEAR
+// Description : Year
+#define RTC_SETUP_0_YEAR_RESET _u(0x000)
+#define RTC_SETUP_0_YEAR_BITS _u(0x00fff000)
+#define RTC_SETUP_0_YEAR_MSB _u(23)
+#define RTC_SETUP_0_YEAR_LSB _u(12)
+#define RTC_SETUP_0_YEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_SETUP_0_MONTH
+// Description : Month (1..12)
+#define RTC_SETUP_0_MONTH_RESET _u(0x0)
+#define RTC_SETUP_0_MONTH_BITS _u(0x00000f00)
+#define RTC_SETUP_0_MONTH_MSB _u(11)
+#define RTC_SETUP_0_MONTH_LSB _u(8)
+#define RTC_SETUP_0_MONTH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_SETUP_0_DAY
+// Description : Day of the month (1..31)
+#define RTC_SETUP_0_DAY_RESET _u(0x00)
+#define RTC_SETUP_0_DAY_BITS _u(0x0000001f)
+#define RTC_SETUP_0_DAY_MSB _u(4)
+#define RTC_SETUP_0_DAY_LSB _u(0)
+#define RTC_SETUP_0_DAY_ACCESS "RW"
+// =============================================================================
+// Register : RTC_SETUP_1
+// Description : RTC setup register 1
+#define RTC_SETUP_1_OFFSET _u(0x00000008)
+#define RTC_SETUP_1_BITS _u(0x071f3f3f)
+#define RTC_SETUP_1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_SETUP_1_DOTW
+// Description : Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
+#define RTC_SETUP_1_DOTW_RESET _u(0x0)
+#define RTC_SETUP_1_DOTW_BITS _u(0x07000000)
+#define RTC_SETUP_1_DOTW_MSB _u(26)
+#define RTC_SETUP_1_DOTW_LSB _u(24)
+#define RTC_SETUP_1_DOTW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_SETUP_1_HOUR
+// Description : Hours
+#define RTC_SETUP_1_HOUR_RESET _u(0x00)
+#define RTC_SETUP_1_HOUR_BITS _u(0x001f0000)
+#define RTC_SETUP_1_HOUR_MSB _u(20)
+#define RTC_SETUP_1_HOUR_LSB _u(16)
+#define RTC_SETUP_1_HOUR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_SETUP_1_MIN
+// Description : Minutes
+#define RTC_SETUP_1_MIN_RESET _u(0x00)
+#define RTC_SETUP_1_MIN_BITS _u(0x00003f00)
+#define RTC_SETUP_1_MIN_MSB _u(13)
+#define RTC_SETUP_1_MIN_LSB _u(8)
+#define RTC_SETUP_1_MIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_SETUP_1_SEC
+// Description : Seconds
+#define RTC_SETUP_1_SEC_RESET _u(0x00)
+#define RTC_SETUP_1_SEC_BITS _u(0x0000003f)
+#define RTC_SETUP_1_SEC_MSB _u(5)
+#define RTC_SETUP_1_SEC_LSB _u(0)
+#define RTC_SETUP_1_SEC_ACCESS "RW"
+// =============================================================================
+// Register : RTC_CTRL
+// Description : RTC Control and status
+#define RTC_CTRL_OFFSET _u(0x0000000c)
+#define RTC_CTRL_BITS _u(0x00000113)
+#define RTC_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_CTRL_FORCE_NOTLEAPYEAR
+// Description : If set, leapyear is forced off.
+// Useful for years divisible by 100 but not by 400
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_RESET _u(0x0)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_BITS _u(0x00000100)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_MSB _u(8)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_LSB _u(8)
+#define RTC_CTRL_FORCE_NOTLEAPYEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_CTRL_LOAD
+// Description : Load RTC
+#define RTC_CTRL_LOAD_RESET _u(0x0)
+#define RTC_CTRL_LOAD_BITS _u(0x00000010)
+#define RTC_CTRL_LOAD_MSB _u(4)
+#define RTC_CTRL_LOAD_LSB _u(4)
+#define RTC_CTRL_LOAD_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : RTC_CTRL_RTC_ACTIVE
+// Description : RTC enabled (running)
+#define RTC_CTRL_RTC_ACTIVE_RESET "-"
+#define RTC_CTRL_RTC_ACTIVE_BITS _u(0x00000002)
+#define RTC_CTRL_RTC_ACTIVE_MSB _u(1)
+#define RTC_CTRL_RTC_ACTIVE_LSB _u(1)
+#define RTC_CTRL_RTC_ACTIVE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RTC_CTRL_RTC_ENABLE
+// Description : Enable RTC
+#define RTC_CTRL_RTC_ENABLE_RESET _u(0x0)
+#define RTC_CTRL_RTC_ENABLE_BITS _u(0x00000001)
+#define RTC_CTRL_RTC_ENABLE_MSB _u(0)
+#define RTC_CTRL_RTC_ENABLE_LSB _u(0)
+#define RTC_CTRL_RTC_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register : RTC_IRQ_SETUP_0
+// Description : Interrupt setup register 0
+#define RTC_IRQ_SETUP_0_OFFSET _u(0x00000010)
+#define RTC_IRQ_SETUP_0_BITS _u(0x37ffff1f)
+#define RTC_IRQ_SETUP_0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_MATCH_ACTIVE
+// Description : None
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_RESET "-"
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS _u(0x20000000)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_MSB _u(29)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_LSB _u(29)
+#define RTC_IRQ_SETUP_0_MATCH_ACTIVE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_MATCH_ENA
+// Description : Global match enable. Don't change any other value while this
+// one is enabled
+#define RTC_IRQ_SETUP_0_MATCH_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_BITS _u(0x10000000)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_MSB _u(28)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_LSB _u(28)
+#define RTC_IRQ_SETUP_0_MATCH_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_YEAR_ENA
+// Description : Enable year matching
+#define RTC_IRQ_SETUP_0_YEAR_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_BITS _u(0x04000000)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_MSB _u(26)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_LSB _u(26)
+#define RTC_IRQ_SETUP_0_YEAR_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_MONTH_ENA
+// Description : Enable month matching
+#define RTC_IRQ_SETUP_0_MONTH_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_BITS _u(0x02000000)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_MSB _u(25)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_LSB _u(25)
+#define RTC_IRQ_SETUP_0_MONTH_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_DAY_ENA
+// Description : Enable day matching
+#define RTC_IRQ_SETUP_0_DAY_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_DAY_ENA_BITS _u(0x01000000)
+#define RTC_IRQ_SETUP_0_DAY_ENA_MSB _u(24)
+#define RTC_IRQ_SETUP_0_DAY_ENA_LSB _u(24)
+#define RTC_IRQ_SETUP_0_DAY_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_YEAR
+// Description : Year
+#define RTC_IRQ_SETUP_0_YEAR_RESET _u(0x000)
+#define RTC_IRQ_SETUP_0_YEAR_BITS _u(0x00fff000)
+#define RTC_IRQ_SETUP_0_YEAR_MSB _u(23)
+#define RTC_IRQ_SETUP_0_YEAR_LSB _u(12)
+#define RTC_IRQ_SETUP_0_YEAR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_MONTH
+// Description : Month (1..12)
+#define RTC_IRQ_SETUP_0_MONTH_RESET _u(0x0)
+#define RTC_IRQ_SETUP_0_MONTH_BITS _u(0x00000f00)
+#define RTC_IRQ_SETUP_0_MONTH_MSB _u(11)
+#define RTC_IRQ_SETUP_0_MONTH_LSB _u(8)
+#define RTC_IRQ_SETUP_0_MONTH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_0_DAY
+// Description : Day of the month (1..31)
+#define RTC_IRQ_SETUP_0_DAY_RESET _u(0x00)
+#define RTC_IRQ_SETUP_0_DAY_BITS _u(0x0000001f)
+#define RTC_IRQ_SETUP_0_DAY_MSB _u(4)
+#define RTC_IRQ_SETUP_0_DAY_LSB _u(0)
+#define RTC_IRQ_SETUP_0_DAY_ACCESS "RW"
+// =============================================================================
+// Register : RTC_IRQ_SETUP_1
+// Description : Interrupt setup register 1
+#define RTC_IRQ_SETUP_1_OFFSET _u(0x00000014)
+#define RTC_IRQ_SETUP_1_BITS _u(0xf71f3f3f)
+#define RTC_IRQ_SETUP_1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_DOTW_ENA
+// Description : Enable day of the week matching
+#define RTC_IRQ_SETUP_1_DOTW_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_BITS _u(0x80000000)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_MSB _u(31)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_LSB _u(31)
+#define RTC_IRQ_SETUP_1_DOTW_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_HOUR_ENA
+// Description : Enable hour matching
+#define RTC_IRQ_SETUP_1_HOUR_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_BITS _u(0x40000000)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_MSB _u(30)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_LSB _u(30)
+#define RTC_IRQ_SETUP_1_HOUR_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_MIN_ENA
+// Description : Enable minute matching
+#define RTC_IRQ_SETUP_1_MIN_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_MIN_ENA_BITS _u(0x20000000)
+#define RTC_IRQ_SETUP_1_MIN_ENA_MSB _u(29)
+#define RTC_IRQ_SETUP_1_MIN_ENA_LSB _u(29)
+#define RTC_IRQ_SETUP_1_MIN_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_SEC_ENA
+// Description : Enable second matching
+#define RTC_IRQ_SETUP_1_SEC_ENA_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_SEC_ENA_BITS _u(0x10000000)
+#define RTC_IRQ_SETUP_1_SEC_ENA_MSB _u(28)
+#define RTC_IRQ_SETUP_1_SEC_ENA_LSB _u(28)
+#define RTC_IRQ_SETUP_1_SEC_ENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_DOTW
+// Description : Day of the week
+#define RTC_IRQ_SETUP_1_DOTW_RESET _u(0x0)
+#define RTC_IRQ_SETUP_1_DOTW_BITS _u(0x07000000)
+#define RTC_IRQ_SETUP_1_DOTW_MSB _u(26)
+#define RTC_IRQ_SETUP_1_DOTW_LSB _u(24)
+#define RTC_IRQ_SETUP_1_DOTW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_HOUR
+// Description : Hours
+#define RTC_IRQ_SETUP_1_HOUR_RESET _u(0x00)
+#define RTC_IRQ_SETUP_1_HOUR_BITS _u(0x001f0000)
+#define RTC_IRQ_SETUP_1_HOUR_MSB _u(20)
+#define RTC_IRQ_SETUP_1_HOUR_LSB _u(16)
+#define RTC_IRQ_SETUP_1_HOUR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_MIN
+// Description : Minutes
+#define RTC_IRQ_SETUP_1_MIN_RESET _u(0x00)
+#define RTC_IRQ_SETUP_1_MIN_BITS _u(0x00003f00)
+#define RTC_IRQ_SETUP_1_MIN_MSB _u(13)
+#define RTC_IRQ_SETUP_1_MIN_LSB _u(8)
+#define RTC_IRQ_SETUP_1_MIN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : RTC_IRQ_SETUP_1_SEC
+// Description : Seconds
+#define RTC_IRQ_SETUP_1_SEC_RESET _u(0x00)
+#define RTC_IRQ_SETUP_1_SEC_BITS _u(0x0000003f)
+#define RTC_IRQ_SETUP_1_SEC_MSB _u(5)
+#define RTC_IRQ_SETUP_1_SEC_LSB _u(0)
+#define RTC_IRQ_SETUP_1_SEC_ACCESS "RW"
+// =============================================================================
+// Register : RTC_RTC_1
+// Description : RTC register 1.
+#define RTC_RTC_1_OFFSET _u(0x00000018)
+#define RTC_RTC_1_BITS _u(0x00ffff1f)
+#define RTC_RTC_1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_RTC_1_YEAR
+// Description : Year
+#define RTC_RTC_1_YEAR_RESET "-"
+#define RTC_RTC_1_YEAR_BITS _u(0x00fff000)
+#define RTC_RTC_1_YEAR_MSB _u(23)
+#define RTC_RTC_1_YEAR_LSB _u(12)
+#define RTC_RTC_1_YEAR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RTC_RTC_1_MONTH
+// Description : Month (1..12)
+#define RTC_RTC_1_MONTH_RESET "-"
+#define RTC_RTC_1_MONTH_BITS _u(0x00000f00)
+#define RTC_RTC_1_MONTH_MSB _u(11)
+#define RTC_RTC_1_MONTH_LSB _u(8)
+#define RTC_RTC_1_MONTH_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : RTC_RTC_1_DAY
+// Description : Day of the month (1..31)
+#define RTC_RTC_1_DAY_RESET "-"
+#define RTC_RTC_1_DAY_BITS _u(0x0000001f)
+#define RTC_RTC_1_DAY_MSB _u(4)
+#define RTC_RTC_1_DAY_LSB _u(0)
+#define RTC_RTC_1_DAY_ACCESS "RO"
+// =============================================================================
+// Register : RTC_RTC_0
+// Description : RTC register 0
+// Read this before RTC 1!
+#define RTC_RTC_0_OFFSET _u(0x0000001c)
+#define RTC_RTC_0_BITS _u(0x071f3f3f)
+#define RTC_RTC_0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_RTC_0_DOTW
+// Description : Day of the week
+#define RTC_RTC_0_DOTW_RESET "-"
+#define RTC_RTC_0_DOTW_BITS _u(0x07000000)
+#define RTC_RTC_0_DOTW_MSB _u(26)
+#define RTC_RTC_0_DOTW_LSB _u(24)
+#define RTC_RTC_0_DOTW_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field : RTC_RTC_0_HOUR
+// Description : Hours
+#define RTC_RTC_0_HOUR_RESET "-"
+#define RTC_RTC_0_HOUR_BITS _u(0x001f0000)
+#define RTC_RTC_0_HOUR_MSB _u(20)
+#define RTC_RTC_0_HOUR_LSB _u(16)
+#define RTC_RTC_0_HOUR_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field : RTC_RTC_0_MIN
+// Description : Minutes
+#define RTC_RTC_0_MIN_RESET "-"
+#define RTC_RTC_0_MIN_BITS _u(0x00003f00)
+#define RTC_RTC_0_MIN_MSB _u(13)
+#define RTC_RTC_0_MIN_LSB _u(8)
+#define RTC_RTC_0_MIN_ACCESS "RF"
+// -----------------------------------------------------------------------------
+// Field : RTC_RTC_0_SEC
+// Description : Seconds
+#define RTC_RTC_0_SEC_RESET "-"
+#define RTC_RTC_0_SEC_BITS _u(0x0000003f)
+#define RTC_RTC_0_SEC_MSB _u(5)
+#define RTC_RTC_0_SEC_LSB _u(0)
+#define RTC_RTC_0_SEC_ACCESS "RF"
+// =============================================================================
+// Register : RTC_INTR
+// Description : Raw Interrupts
+#define RTC_INTR_OFFSET _u(0x00000020)
+#define RTC_INTR_BITS _u(0x00000001)
+#define RTC_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_INTR_RTC
+// Description : None
+#define RTC_INTR_RTC_RESET _u(0x0)
+#define RTC_INTR_RTC_BITS _u(0x00000001)
+#define RTC_INTR_RTC_MSB _u(0)
+#define RTC_INTR_RTC_LSB _u(0)
+#define RTC_INTR_RTC_ACCESS "RO"
+// =============================================================================
+// Register : RTC_INTE
+// Description : Interrupt Enable
+#define RTC_INTE_OFFSET _u(0x00000024)
+#define RTC_INTE_BITS _u(0x00000001)
+#define RTC_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_INTE_RTC
+// Description : None
+#define RTC_INTE_RTC_RESET _u(0x0)
+#define RTC_INTE_RTC_BITS _u(0x00000001)
+#define RTC_INTE_RTC_MSB _u(0)
+#define RTC_INTE_RTC_LSB _u(0)
+#define RTC_INTE_RTC_ACCESS "RW"
+// =============================================================================
+// Register : RTC_INTF
+// Description : Interrupt Force
+#define RTC_INTF_OFFSET _u(0x00000028)
+#define RTC_INTF_BITS _u(0x00000001)
+#define RTC_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_INTF_RTC
+// Description : None
+#define RTC_INTF_RTC_RESET _u(0x0)
+#define RTC_INTF_RTC_BITS _u(0x00000001)
+#define RTC_INTF_RTC_MSB _u(0)
+#define RTC_INTF_RTC_LSB _u(0)
+#define RTC_INTF_RTC_ACCESS "RW"
+// =============================================================================
+// Register : RTC_INTS
+// Description : Interrupt status after masking & forcing
+#define RTC_INTS_OFFSET _u(0x0000002c)
+#define RTC_INTS_BITS _u(0x00000001)
+#define RTC_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : RTC_INTS_RTC
+// Description : None
+#define RTC_INTS_RTC_RESET _u(0x0)
+#define RTC_INTS_RTC_BITS _u(0x00000001)
+#define RTC_INTS_RTC_MSB _u(0)
+#define RTC_INTS_RTC_LSB _u(0)
+#define RTC_INTS_RTC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_RTC_DEFINED
diff --git a/arkanoid/pico/hardware/regs/sio.h b/arkanoid/pico/hardware/regs/sio.h
new file mode 100644
index 0000000..f641533
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/sio.h
@@ -0,0 +1,1656 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SIO
+// Version : 1
+// Bus type : apb
+// Description : Single-cycle IO block
+// Provides core-local and inter-core hardware for the two
+// processors, with single-cycle access.
+// =============================================================================
+#ifndef HARDWARE_REGS_SIO_DEFINED
+#define HARDWARE_REGS_SIO_DEFINED
+// =============================================================================
+// Register : SIO_CPUID
+// Description : Processor core identifier
+// Value is 0 when read from processor core 0, and 1 when read
+// from processor core 1.
+#define SIO_CPUID_OFFSET _u(0x00000000)
+#define SIO_CPUID_BITS _u(0xffffffff)
+#define SIO_CPUID_RESET "-"
+#define SIO_CPUID_MSB _u(31)
+#define SIO_CPUID_LSB _u(0)
+#define SIO_CPUID_ACCESS "RO"
+// =============================================================================
+// Register : SIO_GPIO_IN
+// Description : Input value for GPIO pins
+// Input value for GPIO0...29
+#define SIO_GPIO_IN_OFFSET _u(0x00000004)
+#define SIO_GPIO_IN_BITS _u(0x3fffffff)
+#define SIO_GPIO_IN_RESET _u(0x00000000)
+#define SIO_GPIO_IN_MSB _u(29)
+#define SIO_GPIO_IN_LSB _u(0)
+#define SIO_GPIO_IN_ACCESS "RO"
+// =============================================================================
+// Register : SIO_GPIO_HI_IN
+// Description : Input value for QSPI pins
+// Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2,
+// SD3
+#define SIO_GPIO_HI_IN_OFFSET _u(0x00000008)
+#define SIO_GPIO_HI_IN_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_IN_RESET _u(0x00000000)
+#define SIO_GPIO_HI_IN_MSB _u(5)
+#define SIO_GPIO_HI_IN_LSB _u(0)
+#define SIO_GPIO_HI_IN_ACCESS "RO"
+// =============================================================================
+// Register : SIO_GPIO_OUT
+// Description : GPIO output value
+// Set output level (1/0 -> high/low) for GPIO0...29.
+// Reading back gives the last value written, NOT the input value
+// from the pins.
+// If core 0 and core 1 both write to GPIO_OUT simultaneously (or
+// to a SET/CLR/XOR alias),
+// the result is as though the write from core 0 took place first,
+// and the write from core 1 was then applied to that intermediate
+// result.
+#define SIO_GPIO_OUT_OFFSET _u(0x00000010)
+#define SIO_GPIO_OUT_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_MSB _u(29)
+#define SIO_GPIO_OUT_LSB _u(0)
+#define SIO_GPIO_OUT_ACCESS "RW"
+// =============================================================================
+// Register : SIO_GPIO_OUT_SET
+// Description : GPIO output value set
+// Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
+#define SIO_GPIO_OUT_SET_OFFSET _u(0x00000014)
+#define SIO_GPIO_OUT_SET_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_SET_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_SET_MSB _u(29)
+#define SIO_GPIO_OUT_SET_LSB _u(0)
+#define SIO_GPIO_OUT_SET_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_OUT_CLR
+// Description : GPIO output value clear
+// Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &=
+// ~wdata`
+#define SIO_GPIO_OUT_CLR_OFFSET _u(0x00000018)
+#define SIO_GPIO_OUT_CLR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_CLR_MSB _u(29)
+#define SIO_GPIO_OUT_CLR_LSB _u(0)
+#define SIO_GPIO_OUT_CLR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_OUT_XOR
+// Description : GPIO output value XOR
+// Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^=
+// wdata`
+#define SIO_GPIO_OUT_XOR_OFFSET _u(0x0000001c)
+#define SIO_GPIO_OUT_XOR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OUT_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_OUT_XOR_MSB _u(29)
+#define SIO_GPIO_OUT_XOR_LSB _u(0)
+#define SIO_GPIO_OUT_XOR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_OE
+// Description : GPIO output enable
+// Set output enable (1/0 -> output/input) for GPIO0...29.
+// Reading back gives the last value written.
+// If core 0 and core 1 both write to GPIO_OE simultaneously (or
+// to a SET/CLR/XOR alias),
+// the result is as though the write from core 0 took place first,
+// and the write from core 1 was then applied to that intermediate
+// result.
+#define SIO_GPIO_OE_OFFSET _u(0x00000020)
+#define SIO_GPIO_OE_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_RESET _u(0x00000000)
+#define SIO_GPIO_OE_MSB _u(29)
+#define SIO_GPIO_OE_LSB _u(0)
+#define SIO_GPIO_OE_ACCESS "RW"
+// =============================================================================
+// Register : SIO_GPIO_OE_SET
+// Description : GPIO output enable set
+// Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
+#define SIO_GPIO_OE_SET_OFFSET _u(0x00000024)
+#define SIO_GPIO_OE_SET_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_SET_RESET _u(0x00000000)
+#define SIO_GPIO_OE_SET_MSB _u(29)
+#define SIO_GPIO_OE_SET_LSB _u(0)
+#define SIO_GPIO_OE_SET_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_OE_CLR
+// Description : GPIO output enable clear
+// Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &=
+// ~wdata`
+#define SIO_GPIO_OE_CLR_OFFSET _u(0x00000028)
+#define SIO_GPIO_OE_CLR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_OE_CLR_MSB _u(29)
+#define SIO_GPIO_OE_CLR_LSB _u(0)
+#define SIO_GPIO_OE_CLR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_OE_XOR
+// Description : GPIO output enable XOR
+// Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^=
+// wdata`
+#define SIO_GPIO_OE_XOR_OFFSET _u(0x0000002c)
+#define SIO_GPIO_OE_XOR_BITS _u(0x3fffffff)
+#define SIO_GPIO_OE_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_OE_XOR_MSB _u(29)
+#define SIO_GPIO_OE_XOR_LSB _u(0)
+#define SIO_GPIO_OE_XOR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_HI_OUT
+// Description : QSPI output value
+// Set output level (1/0 -> high/low) for QSPI IO0...5.
+// Reading back gives the last value written, NOT the input value
+// from the pins.
+// If core 0 and core 1 both write to GPIO_HI_OUT simultaneously
+// (or to a SET/CLR/XOR alias),
+// the result is as though the write from core 0 took place first,
+// and the write from core 1 was then applied to that intermediate
+// result.
+#define SIO_GPIO_HI_OUT_OFFSET _u(0x00000030)
+#define SIO_GPIO_HI_OUT_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_MSB _u(5)
+#define SIO_GPIO_HI_OUT_LSB _u(0)
+#define SIO_GPIO_HI_OUT_ACCESS "RW"
+// =============================================================================
+// Register : SIO_GPIO_HI_OUT_SET
+// Description : QSPI output value set
+// Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |=
+// wdata`
+#define SIO_GPIO_HI_OUT_SET_OFFSET _u(0x00000034)
+#define SIO_GPIO_HI_OUT_SET_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_SET_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_SET_MSB _u(5)
+#define SIO_GPIO_HI_OUT_SET_LSB _u(0)
+#define SIO_GPIO_HI_OUT_SET_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_HI_OUT_CLR
+// Description : QSPI output value clear
+// Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT
+// &= ~wdata`
+#define SIO_GPIO_HI_OUT_CLR_OFFSET _u(0x00000038)
+#define SIO_GPIO_HI_OUT_CLR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_CLR_MSB _u(5)
+#define SIO_GPIO_HI_OUT_CLR_LSB _u(0)
+#define SIO_GPIO_HI_OUT_CLR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_HI_OUT_XOR
+// Description : QSPI output value XOR
+// Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT
+// ^= wdata`
+#define SIO_GPIO_HI_OUT_XOR_OFFSET _u(0x0000003c)
+#define SIO_GPIO_HI_OUT_XOR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OUT_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OUT_XOR_MSB _u(5)
+#define SIO_GPIO_HI_OUT_XOR_LSB _u(0)
+#define SIO_GPIO_HI_OUT_XOR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_HI_OE
+// Description : QSPI output enable
+// Set output enable (1/0 -> output/input) for QSPI IO0...5.
+// Reading back gives the last value written.
+// If core 0 and core 1 both write to GPIO_HI_OE simultaneously
+// (or to a SET/CLR/XOR alias),
+// the result is as though the write from core 0 took place first,
+// and the write from core 1 was then applied to that intermediate
+// result.
+#define SIO_GPIO_HI_OE_OFFSET _u(0x00000040)
+#define SIO_GPIO_HI_OE_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_MSB _u(5)
+#define SIO_GPIO_HI_OE_LSB _u(0)
+#define SIO_GPIO_HI_OE_ACCESS "RW"
+// =============================================================================
+// Register : SIO_GPIO_HI_OE_SET
+// Description : QSPI output enable set
+// Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |=
+// wdata`
+#define SIO_GPIO_HI_OE_SET_OFFSET _u(0x00000044)
+#define SIO_GPIO_HI_OE_SET_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_SET_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_SET_MSB _u(5)
+#define SIO_GPIO_HI_OE_SET_LSB _u(0)
+#define SIO_GPIO_HI_OE_SET_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_HI_OE_CLR
+// Description : QSPI output enable clear
+// Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &=
+// ~wdata`
+#define SIO_GPIO_HI_OE_CLR_OFFSET _u(0x00000048)
+#define SIO_GPIO_HI_OE_CLR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_CLR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_CLR_MSB _u(5)
+#define SIO_GPIO_HI_OE_CLR_LSB _u(0)
+#define SIO_GPIO_HI_OE_CLR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_GPIO_HI_OE_XOR
+// Description : QSPI output enable XOR
+// Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE
+// ^= wdata`
+#define SIO_GPIO_HI_OE_XOR_OFFSET _u(0x0000004c)
+#define SIO_GPIO_HI_OE_XOR_BITS _u(0x0000003f)
+#define SIO_GPIO_HI_OE_XOR_RESET _u(0x00000000)
+#define SIO_GPIO_HI_OE_XOR_MSB _u(5)
+#define SIO_GPIO_HI_OE_XOR_LSB _u(0)
+#define SIO_GPIO_HI_OE_XOR_ACCESS "WO"
+// =============================================================================
+// Register : SIO_FIFO_ST
+// Description : Status register for inter-core FIFOs (mailboxes).
+// There is one FIFO in the core 0 -> core 1 direction, and one
+// core 1 -> core 0. Both are 32 bits wide and 8 words deep.
+// Core 0 can see the read side of the 1->0 FIFO (RX), and the
+// write side of 0->1 FIFO (TX).
+// Core 1 can see the read side of the 0->1 FIFO (RX), and the
+// write side of 1->0 FIFO (TX).
+// The SIO IRQ for each core is the logical OR of the VLD, WOF and
+// ROE fields of its FIFO_ST register.
+#define SIO_FIFO_ST_OFFSET _u(0x00000050)
+#define SIO_FIFO_ST_BITS _u(0x0000000f)
+#define SIO_FIFO_ST_RESET _u(0x00000002)
+// -----------------------------------------------------------------------------
+// Field : SIO_FIFO_ST_ROE
+// Description : Sticky flag indicating the RX FIFO was read when empty. This
+// read was ignored by the FIFO.
+#define SIO_FIFO_ST_ROE_RESET _u(0x0)
+#define SIO_FIFO_ST_ROE_BITS _u(0x00000008)
+#define SIO_FIFO_ST_ROE_MSB _u(3)
+#define SIO_FIFO_ST_ROE_LSB _u(3)
+#define SIO_FIFO_ST_ROE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : SIO_FIFO_ST_WOF
+// Description : Sticky flag indicating the TX FIFO was written when full. This
+// write was ignored by the FIFO.
+#define SIO_FIFO_ST_WOF_RESET _u(0x0)
+#define SIO_FIFO_ST_WOF_BITS _u(0x00000004)
+#define SIO_FIFO_ST_WOF_MSB _u(2)
+#define SIO_FIFO_ST_WOF_LSB _u(2)
+#define SIO_FIFO_ST_WOF_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : SIO_FIFO_ST_RDY
+// Description : Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR
+// is ready for more data)
+#define SIO_FIFO_ST_RDY_RESET _u(0x1)
+#define SIO_FIFO_ST_RDY_BITS _u(0x00000002)
+#define SIO_FIFO_ST_RDY_MSB _u(1)
+#define SIO_FIFO_ST_RDY_LSB _u(1)
+#define SIO_FIFO_ST_RDY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_FIFO_ST_VLD
+// Description : Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD
+// is valid)
+#define SIO_FIFO_ST_VLD_RESET _u(0x0)
+#define SIO_FIFO_ST_VLD_BITS _u(0x00000001)
+#define SIO_FIFO_ST_VLD_MSB _u(0)
+#define SIO_FIFO_ST_VLD_LSB _u(0)
+#define SIO_FIFO_ST_VLD_ACCESS "RO"
+// =============================================================================
+// Register : SIO_FIFO_WR
+// Description : Write access to this core's TX FIFO
+#define SIO_FIFO_WR_OFFSET _u(0x00000054)
+#define SIO_FIFO_WR_BITS _u(0xffffffff)
+#define SIO_FIFO_WR_RESET _u(0x00000000)
+#define SIO_FIFO_WR_MSB _u(31)
+#define SIO_FIFO_WR_LSB _u(0)
+#define SIO_FIFO_WR_ACCESS "WF"
+// =============================================================================
+// Register : SIO_FIFO_RD
+// Description : Read access to this core's RX FIFO
+#define SIO_FIFO_RD_OFFSET _u(0x00000058)
+#define SIO_FIFO_RD_BITS _u(0xffffffff)
+#define SIO_FIFO_RD_RESET "-"
+#define SIO_FIFO_RD_MSB _u(31)
+#define SIO_FIFO_RD_LSB _u(0)
+#define SIO_FIFO_RD_ACCESS "RF"
+// =============================================================================
+// Register : SIO_SPINLOCK_ST
+// Description : Spinlock state
+// A bitmap containing the state of all 32 spinlocks (1=locked).
+// Mainly intended for debugging.
+#define SIO_SPINLOCK_ST_OFFSET _u(0x0000005c)
+#define SIO_SPINLOCK_ST_BITS _u(0xffffffff)
+#define SIO_SPINLOCK_ST_RESET _u(0x00000000)
+#define SIO_SPINLOCK_ST_MSB _u(31)
+#define SIO_SPINLOCK_ST_LSB _u(0)
+#define SIO_SPINLOCK_ST_ACCESS "RO"
+// =============================================================================
+// Register : SIO_DIV_UDIVIDEND
+// Description : Divider unsigned dividend
+// Write to the DIVIDEND operand of the divider, i.e. the p in `p
+// / q`.
+// Any operand write starts a new calculation. The results appear
+// in QUOTIENT, REMAINDER.
+// UDIVIDEND/SDIVIDEND are aliases of the same internal register.
+// The U alias starts an
+// unsigned calculation, and the S alias starts a signed
+// calculation.
+#define SIO_DIV_UDIVIDEND_OFFSET _u(0x00000060)
+#define SIO_DIV_UDIVIDEND_BITS _u(0xffffffff)
+#define SIO_DIV_UDIVIDEND_RESET _u(0x00000000)
+#define SIO_DIV_UDIVIDEND_MSB _u(31)
+#define SIO_DIV_UDIVIDEND_LSB _u(0)
+#define SIO_DIV_UDIVIDEND_ACCESS "RW"
+// =============================================================================
+// Register : SIO_DIV_UDIVISOR
+// Description : Divider unsigned divisor
+// Write to the DIVISOR operand of the divider, i.e. the q in `p /
+// q`.
+// Any operand write starts a new calculation. The results appear
+// in QUOTIENT, REMAINDER.
+// UDIVIDEND/SDIVIDEND are aliases of the same internal register.
+// The U alias starts an
+// unsigned calculation, and the S alias starts a signed
+// calculation.
+#define SIO_DIV_UDIVISOR_OFFSET _u(0x00000064)
+#define SIO_DIV_UDIVISOR_BITS _u(0xffffffff)
+#define SIO_DIV_UDIVISOR_RESET _u(0x00000000)
+#define SIO_DIV_UDIVISOR_MSB _u(31)
+#define SIO_DIV_UDIVISOR_LSB _u(0)
+#define SIO_DIV_UDIVISOR_ACCESS "RW"
+// =============================================================================
+// Register : SIO_DIV_SDIVIDEND
+// Description : Divider signed dividend
+// The same as UDIVIDEND, but starts a signed calculation, rather
+// than unsigned.
+#define SIO_DIV_SDIVIDEND_OFFSET _u(0x00000068)
+#define SIO_DIV_SDIVIDEND_BITS _u(0xffffffff)
+#define SIO_DIV_SDIVIDEND_RESET _u(0x00000000)
+#define SIO_DIV_SDIVIDEND_MSB _u(31)
+#define SIO_DIV_SDIVIDEND_LSB _u(0)
+#define SIO_DIV_SDIVIDEND_ACCESS "RW"
+// =============================================================================
+// Register : SIO_DIV_SDIVISOR
+// Description : Divider signed divisor
+// The same as UDIVISOR, but starts a signed calculation, rather
+// than unsigned.
+#define SIO_DIV_SDIVISOR_OFFSET _u(0x0000006c)
+#define SIO_DIV_SDIVISOR_BITS _u(0xffffffff)
+#define SIO_DIV_SDIVISOR_RESET _u(0x00000000)
+#define SIO_DIV_SDIVISOR_MSB _u(31)
+#define SIO_DIV_SDIVISOR_LSB _u(0)
+#define SIO_DIV_SDIVISOR_ACCESS "RW"
+// =============================================================================
+// Register : SIO_DIV_QUOTIENT
+// Description : Divider result quotient
+// The result of `DIVIDEND / DIVISOR` (division). Contents
+// undefined while CSR_READY is low.
+// For signed calculations, QUOTIENT is negative when the signs of
+// DIVIDEND and DIVISOR differ.
+// This register can be written to directly, for context
+// save/restore purposes. This halts any
+// in-progress calculation and sets the CSR_READY and CSR_DIRTY
+// flags.
+// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read
+// results in the order
+// REMAINDER, QUOTIENT if CSR_DIRTY is used.
+#define SIO_DIV_QUOTIENT_OFFSET _u(0x00000070)
+#define SIO_DIV_QUOTIENT_BITS _u(0xffffffff)
+#define SIO_DIV_QUOTIENT_RESET _u(0x00000000)
+#define SIO_DIV_QUOTIENT_MSB _u(31)
+#define SIO_DIV_QUOTIENT_LSB _u(0)
+#define SIO_DIV_QUOTIENT_ACCESS "RW"
+// =============================================================================
+// Register : SIO_DIV_REMAINDER
+// Description : Divider result remainder
+// The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined
+// while CSR_READY is low.
+// For signed calculations, REMAINDER is negative only when
+// DIVIDEND is negative.
+// This register can be written to directly, for context
+// save/restore purposes. This halts any
+// in-progress calculation and sets the CSR_READY and CSR_DIRTY
+// flags.
+#define SIO_DIV_REMAINDER_OFFSET _u(0x00000074)
+#define SIO_DIV_REMAINDER_BITS _u(0xffffffff)
+#define SIO_DIV_REMAINDER_RESET _u(0x00000000)
+#define SIO_DIV_REMAINDER_MSB _u(31)
+#define SIO_DIV_REMAINDER_LSB _u(0)
+#define SIO_DIV_REMAINDER_ACCESS "RW"
+// =============================================================================
+// Register : SIO_DIV_CSR
+// Description : Control and status register for divider.
+#define SIO_DIV_CSR_OFFSET _u(0x00000078)
+#define SIO_DIV_CSR_BITS _u(0x00000003)
+#define SIO_DIV_CSR_RESET _u(0x00000001)
+// -----------------------------------------------------------------------------
+// Field : SIO_DIV_CSR_DIRTY
+// Description : Changes to 1 when any register is written, and back to 0 when
+// QUOTIENT is read.
+// Software can use this flag to make save/restore more efficient
+// (skip if not DIRTY).
+// If the flag is used in this way, it's recommended to either
+// read QUOTIENT only,
+// or REMAINDER and then QUOTIENT, to prevent data loss on context
+// switch.
+#define SIO_DIV_CSR_DIRTY_RESET _u(0x0)
+#define SIO_DIV_CSR_DIRTY_BITS _u(0x00000002)
+#define SIO_DIV_CSR_DIRTY_MSB _u(1)
+#define SIO_DIV_CSR_DIRTY_LSB _u(1)
+#define SIO_DIV_CSR_DIRTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_DIV_CSR_READY
+// Description : Reads as 0 when a calculation is in progress, 1 otherwise.
+// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start
+// a new calculation, no
+// matter if one is already in progress.
+// Writing to a result register will immediately terminate any
+// in-progress calculation
+// and set the READY and DIRTY flags.
+#define SIO_DIV_CSR_READY_RESET _u(0x1)
+#define SIO_DIV_CSR_READY_BITS _u(0x00000001)
+#define SIO_DIV_CSR_READY_MSB _u(0)
+#define SIO_DIV_CSR_READY_LSB _u(0)
+#define SIO_DIV_CSR_READY_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP0_ACCUM0
+// Description : Read/write access to accumulator 0
+#define SIO_INTERP0_ACCUM0_OFFSET _u(0x00000080)
+#define SIO_INTERP0_ACCUM0_BITS _u(0xffffffff)
+#define SIO_INTERP0_ACCUM0_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM0_MSB _u(31)
+#define SIO_INTERP0_ACCUM0_LSB _u(0)
+#define SIO_INTERP0_ACCUM0_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_ACCUM1
+// Description : Read/write access to accumulator 1
+#define SIO_INTERP0_ACCUM1_OFFSET _u(0x00000084)
+#define SIO_INTERP0_ACCUM1_BITS _u(0xffffffff)
+#define SIO_INTERP0_ACCUM1_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM1_MSB _u(31)
+#define SIO_INTERP0_ACCUM1_LSB _u(0)
+#define SIO_INTERP0_ACCUM1_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_BASE0
+// Description : Read/write access to BASE0 register.
+#define SIO_INTERP0_BASE0_OFFSET _u(0x00000088)
+#define SIO_INTERP0_BASE0_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE0_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE0_MSB _u(31)
+#define SIO_INTERP0_BASE0_LSB _u(0)
+#define SIO_INTERP0_BASE0_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_BASE1
+// Description : Read/write access to BASE1 register.
+#define SIO_INTERP0_BASE1_OFFSET _u(0x0000008c)
+#define SIO_INTERP0_BASE1_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE1_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE1_MSB _u(31)
+#define SIO_INTERP0_BASE1_LSB _u(0)
+#define SIO_INTERP0_BASE1_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_BASE2
+// Description : Read/write access to BASE2 register.
+#define SIO_INTERP0_BASE2_OFFSET _u(0x00000090)
+#define SIO_INTERP0_BASE2_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE2_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE2_MSB _u(31)
+#define SIO_INTERP0_BASE2_LSB _u(0)
+#define SIO_INTERP0_BASE2_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_POP_LANE0
+// Description : Read LANE0 result, and simultaneously write lane results to
+// both accumulators (POP).
+#define SIO_INTERP0_POP_LANE0_OFFSET _u(0x00000094)
+#define SIO_INTERP0_POP_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP0_POP_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP0_POP_LANE0_MSB _u(31)
+#define SIO_INTERP0_POP_LANE0_LSB _u(0)
+#define SIO_INTERP0_POP_LANE0_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP0_POP_LANE1
+// Description : Read LANE1 result, and simultaneously write lane results to
+// both accumulators (POP).
+#define SIO_INTERP0_POP_LANE1_OFFSET _u(0x00000098)
+#define SIO_INTERP0_POP_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP0_POP_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP0_POP_LANE1_MSB _u(31)
+#define SIO_INTERP0_POP_LANE1_LSB _u(0)
+#define SIO_INTERP0_POP_LANE1_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP0_POP_FULL
+// Description : Read FULL result, and simultaneously write lane results to both
+// accumulators (POP).
+#define SIO_INTERP0_POP_FULL_OFFSET _u(0x0000009c)
+#define SIO_INTERP0_POP_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP0_POP_FULL_RESET _u(0x00000000)
+#define SIO_INTERP0_POP_FULL_MSB _u(31)
+#define SIO_INTERP0_POP_FULL_LSB _u(0)
+#define SIO_INTERP0_POP_FULL_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP0_PEEK_LANE0
+// Description : Read LANE0 result, without altering any internal state (PEEK).
+#define SIO_INTERP0_PEEK_LANE0_OFFSET _u(0x000000a0)
+#define SIO_INTERP0_PEEK_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP0_PEEK_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP0_PEEK_LANE0_MSB _u(31)
+#define SIO_INTERP0_PEEK_LANE0_LSB _u(0)
+#define SIO_INTERP0_PEEK_LANE0_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP0_PEEK_LANE1
+// Description : Read LANE1 result, without altering any internal state (PEEK).
+#define SIO_INTERP0_PEEK_LANE1_OFFSET _u(0x000000a4)
+#define SIO_INTERP0_PEEK_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP0_PEEK_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP0_PEEK_LANE1_MSB _u(31)
+#define SIO_INTERP0_PEEK_LANE1_LSB _u(0)
+#define SIO_INTERP0_PEEK_LANE1_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP0_PEEK_FULL
+// Description : Read FULL result, without altering any internal state (PEEK).
+#define SIO_INTERP0_PEEK_FULL_OFFSET _u(0x000000a8)
+#define SIO_INTERP0_PEEK_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP0_PEEK_FULL_RESET _u(0x00000000)
+#define SIO_INTERP0_PEEK_FULL_MSB _u(31)
+#define SIO_INTERP0_PEEK_FULL_LSB _u(0)
+#define SIO_INTERP0_PEEK_FULL_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP0_CTRL_LANE0
+// Description : Control register for lane 0
+#define SIO_INTERP0_CTRL_LANE0_OFFSET _u(0x000000ac)
+#define SIO_INTERP0_CTRL_LANE0_BITS _u(0x03bfffff)
+#define SIO_INTERP0_CTRL_LANE0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_OVERF
+// Description : Set if either OVERF0 or OVERF1 is set.
+#define SIO_INTERP0_CTRL_LANE0_OVERF_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_BITS _u(0x02000000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_MSB _u(25)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_LSB _u(25)
+#define SIO_INTERP0_CTRL_LANE0_OVERF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_OVERF1
+// Description : Indicates if any masked-off MSBs in ACCUM1 are set.
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_BITS _u(0x01000000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_MSB _u(24)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_LSB _u(24)
+#define SIO_INTERP0_CTRL_LANE0_OVERF1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_OVERF0
+// Description : Indicates if any masked-off MSBs in ACCUM0 are set.
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_BITS _u(0x00800000)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_MSB _u(23)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_LSB _u(23)
+#define SIO_INTERP0_CTRL_LANE0_OVERF0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_BLEND
+// Description : Only present on INTERP0 on each core. If BLEND mode is enabled:
+// - LANE1 result is a linear interpolation between BASE0 and
+// BASE1, controlled
+// by the 8 LSBs of lane 1 shift and mask value (a fractional
+// number between
+// 0 and 255/256ths)
+// - LANE0 result does not have BASE0 added (yields only the 8
+// LSBs of lane 1 shift+mask value)
+// - FULL result does not have lane 1 shift+mask value added
+// (BASE2 + lane 0 shift+mask)
+// LANE1 SIGNED flag controls whether the interpolation is signed
+// or unsigned.
+#define SIO_INTERP0_CTRL_LANE0_BLEND_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_BITS _u(0x00200000)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_MSB _u(21)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_LSB _u(21)
+#define SIO_INTERP0_CTRL_LANE0_BLEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+// processor on the bus.
+// No effect on the internal 32-bit datapath. Handy for using a
+// lane to generate sequence
+// of pointers into flash or SRAM.
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_LSB _u(19)
+#define SIO_INTERP0_CTRL_LANE0_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE0 result. This does not
+// affect FULL result.
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_MSB _u(18)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_LSB _u(18)
+#define SIO_INTERP0_CTRL_LANE0_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+// accumulator on POP.
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_LSB _u(17)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+// shift + mask hardware.
+// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+// before the shift+mask bypass)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_LSB _u(16)
+#define SIO_INTERP0_CTRL_LANE0_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+// sign-extended to 32 bits
+// before adding to BASE0, and LANE0 PEEK/POP appear extended to
+// 32 bits when read by processor.
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_MSB _u(15)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_LSB _u(15)
+#define SIO_INTERP0_CTRL_LANE0_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+// (inclusive)
+// Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_MSB _u(14)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_LSB _u(10)
+#define SIO_INTERP0_CTRL_LANE0_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+// (inclusive)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_MSB _u(9)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_LSB _u(5)
+#define SIO_INTERP0_CTRL_LANE0_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE0_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_MSB _u(4)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_LSB _u(0)
+#define SIO_INTERP0_CTRL_LANE0_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_CTRL_LANE1
+// Description : Control register for lane 1
+#define SIO_INTERP0_CTRL_LANE1_OFFSET _u(0x000000b0)
+#define SIO_INTERP0_CTRL_LANE1_BITS _u(0x001fffff)
+#define SIO_INTERP0_CTRL_LANE1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+// processor on the bus.
+// No effect on the internal 32-bit datapath. Handy for using a
+// lane to generate sequence
+// of pointers into flash or SRAM.
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_LSB _u(19)
+#define SIO_INTERP0_CTRL_LANE1_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE1 result. This does not
+// affect FULL result.
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_MSB _u(18)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_LSB _u(18)
+#define SIO_INTERP0_CTRL_LANE1_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+// accumulator on POP.
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_LSB _u(17)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+// shift + mask hardware.
+// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+// before the shift+mask bypass)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_LSB _u(16)
+#define SIO_INTERP0_CTRL_LANE1_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+// sign-extended to 32 bits
+// before adding to BASE1, and LANE1 PEEK/POP appear extended to
+// 32 bits when read by processor.
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_RESET _u(0x0)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_MSB _u(15)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_LSB _u(15)
+#define SIO_INTERP0_CTRL_LANE1_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+// (inclusive)
+// Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_MSB _u(14)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_LSB _u(10)
+#define SIO_INTERP0_CTRL_LANE1_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+// (inclusive)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_MSB _u(9)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_LSB _u(5)
+#define SIO_INTERP0_CTRL_LANE1_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP0_CTRL_LANE1_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_RESET _u(0x00)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_MSB _u(4)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_LSB _u(0)
+#define SIO_INTERP0_CTRL_LANE1_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_ACCUM0_ADD
+// Description : Values written here are atomically added to ACCUM0
+// Reading yields lane 0's raw shift and mask value (BASE0 not
+// added).
+#define SIO_INTERP0_ACCUM0_ADD_OFFSET _u(0x000000b4)
+#define SIO_INTERP0_ACCUM0_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP0_ACCUM0_ADD_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM0_ADD_MSB _u(23)
+#define SIO_INTERP0_ACCUM0_ADD_LSB _u(0)
+#define SIO_INTERP0_ACCUM0_ADD_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_ACCUM1_ADD
+// Description : Values written here are atomically added to ACCUM1
+// Reading yields lane 1's raw shift and mask value (BASE1 not
+// added).
+#define SIO_INTERP0_ACCUM1_ADD_OFFSET _u(0x000000b8)
+#define SIO_INTERP0_ACCUM1_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP0_ACCUM1_ADD_RESET _u(0x00000000)
+#define SIO_INTERP0_ACCUM1_ADD_MSB _u(23)
+#define SIO_INTERP0_ACCUM1_ADD_LSB _u(0)
+#define SIO_INTERP0_ACCUM1_ADD_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP0_BASE_1AND0
+// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1
+// simultaneously.
+// Each half is sign-extended to 32 bits if that lane's SIGNED
+// flag is set.
+#define SIO_INTERP0_BASE_1AND0_OFFSET _u(0x000000bc)
+#define SIO_INTERP0_BASE_1AND0_BITS _u(0xffffffff)
+#define SIO_INTERP0_BASE_1AND0_RESET _u(0x00000000)
+#define SIO_INTERP0_BASE_1AND0_MSB _u(31)
+#define SIO_INTERP0_BASE_1AND0_LSB _u(0)
+#define SIO_INTERP0_BASE_1AND0_ACCESS "WO"
+// =============================================================================
+// Register : SIO_INTERP1_ACCUM0
+// Description : Read/write access to accumulator 0
+#define SIO_INTERP1_ACCUM0_OFFSET _u(0x000000c0)
+#define SIO_INTERP1_ACCUM0_BITS _u(0xffffffff)
+#define SIO_INTERP1_ACCUM0_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM0_MSB _u(31)
+#define SIO_INTERP1_ACCUM0_LSB _u(0)
+#define SIO_INTERP1_ACCUM0_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_ACCUM1
+// Description : Read/write access to accumulator 1
+#define SIO_INTERP1_ACCUM1_OFFSET _u(0x000000c4)
+#define SIO_INTERP1_ACCUM1_BITS _u(0xffffffff)
+#define SIO_INTERP1_ACCUM1_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM1_MSB _u(31)
+#define SIO_INTERP1_ACCUM1_LSB _u(0)
+#define SIO_INTERP1_ACCUM1_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_BASE0
+// Description : Read/write access to BASE0 register.
+#define SIO_INTERP1_BASE0_OFFSET _u(0x000000c8)
+#define SIO_INTERP1_BASE0_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE0_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE0_MSB _u(31)
+#define SIO_INTERP1_BASE0_LSB _u(0)
+#define SIO_INTERP1_BASE0_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_BASE1
+// Description : Read/write access to BASE1 register.
+#define SIO_INTERP1_BASE1_OFFSET _u(0x000000cc)
+#define SIO_INTERP1_BASE1_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE1_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE1_MSB _u(31)
+#define SIO_INTERP1_BASE1_LSB _u(0)
+#define SIO_INTERP1_BASE1_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_BASE2
+// Description : Read/write access to BASE2 register.
+#define SIO_INTERP1_BASE2_OFFSET _u(0x000000d0)
+#define SIO_INTERP1_BASE2_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE2_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE2_MSB _u(31)
+#define SIO_INTERP1_BASE2_LSB _u(0)
+#define SIO_INTERP1_BASE2_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_POP_LANE0
+// Description : Read LANE0 result, and simultaneously write lane results to
+// both accumulators (POP).
+#define SIO_INTERP1_POP_LANE0_OFFSET _u(0x000000d4)
+#define SIO_INTERP1_POP_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP1_POP_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP1_POP_LANE0_MSB _u(31)
+#define SIO_INTERP1_POP_LANE0_LSB _u(0)
+#define SIO_INTERP1_POP_LANE0_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP1_POP_LANE1
+// Description : Read LANE1 result, and simultaneously write lane results to
+// both accumulators (POP).
+#define SIO_INTERP1_POP_LANE1_OFFSET _u(0x000000d8)
+#define SIO_INTERP1_POP_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP1_POP_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP1_POP_LANE1_MSB _u(31)
+#define SIO_INTERP1_POP_LANE1_LSB _u(0)
+#define SIO_INTERP1_POP_LANE1_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP1_POP_FULL
+// Description : Read FULL result, and simultaneously write lane results to both
+// accumulators (POP).
+#define SIO_INTERP1_POP_FULL_OFFSET _u(0x000000dc)
+#define SIO_INTERP1_POP_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP1_POP_FULL_RESET _u(0x00000000)
+#define SIO_INTERP1_POP_FULL_MSB _u(31)
+#define SIO_INTERP1_POP_FULL_LSB _u(0)
+#define SIO_INTERP1_POP_FULL_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP1_PEEK_LANE0
+// Description : Read LANE0 result, without altering any internal state (PEEK).
+#define SIO_INTERP1_PEEK_LANE0_OFFSET _u(0x000000e0)
+#define SIO_INTERP1_PEEK_LANE0_BITS _u(0xffffffff)
+#define SIO_INTERP1_PEEK_LANE0_RESET _u(0x00000000)
+#define SIO_INTERP1_PEEK_LANE0_MSB _u(31)
+#define SIO_INTERP1_PEEK_LANE0_LSB _u(0)
+#define SIO_INTERP1_PEEK_LANE0_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP1_PEEK_LANE1
+// Description : Read LANE1 result, without altering any internal state (PEEK).
+#define SIO_INTERP1_PEEK_LANE1_OFFSET _u(0x000000e4)
+#define SIO_INTERP1_PEEK_LANE1_BITS _u(0xffffffff)
+#define SIO_INTERP1_PEEK_LANE1_RESET _u(0x00000000)
+#define SIO_INTERP1_PEEK_LANE1_MSB _u(31)
+#define SIO_INTERP1_PEEK_LANE1_LSB _u(0)
+#define SIO_INTERP1_PEEK_LANE1_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP1_PEEK_FULL
+// Description : Read FULL result, without altering any internal state (PEEK).
+#define SIO_INTERP1_PEEK_FULL_OFFSET _u(0x000000e8)
+#define SIO_INTERP1_PEEK_FULL_BITS _u(0xffffffff)
+#define SIO_INTERP1_PEEK_FULL_RESET _u(0x00000000)
+#define SIO_INTERP1_PEEK_FULL_MSB _u(31)
+#define SIO_INTERP1_PEEK_FULL_LSB _u(0)
+#define SIO_INTERP1_PEEK_FULL_ACCESS "RO"
+// =============================================================================
+// Register : SIO_INTERP1_CTRL_LANE0
+// Description : Control register for lane 0
+#define SIO_INTERP1_CTRL_LANE0_OFFSET _u(0x000000ec)
+#define SIO_INTERP1_CTRL_LANE0_BITS _u(0x03dfffff)
+#define SIO_INTERP1_CTRL_LANE0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_OVERF
+// Description : Set if either OVERF0 or OVERF1 is set.
+#define SIO_INTERP1_CTRL_LANE0_OVERF_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_BITS _u(0x02000000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_MSB _u(25)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_LSB _u(25)
+#define SIO_INTERP1_CTRL_LANE0_OVERF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_OVERF1
+// Description : Indicates if any masked-off MSBs in ACCUM1 are set.
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_BITS _u(0x01000000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_MSB _u(24)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_LSB _u(24)
+#define SIO_INTERP1_CTRL_LANE0_OVERF1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_OVERF0
+// Description : Indicates if any masked-off MSBs in ACCUM0 are set.
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_BITS _u(0x00800000)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_MSB _u(23)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_LSB _u(23)
+#define SIO_INTERP1_CTRL_LANE0_OVERF0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_CLAMP
+// Description : Only present on INTERP1 on each core. If CLAMP mode is enabled:
+// - LANE0 result is shifted and masked ACCUM0, clamped by a lower
+// bound of
+// BASE0 and an upper bound of BASE1.
+// - Signedness of these comparisons is determined by
+// LANE0_CTRL_SIGNED
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_BITS _u(0x00400000)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_MSB _u(22)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_LSB _u(22)
+#define SIO_INTERP1_CTRL_LANE0_CLAMP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+// processor on the bus.
+// No effect on the internal 32-bit datapath. Handy for using a
+// lane to generate sequence
+// of pointers into flash or SRAM.
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_LSB _u(19)
+#define SIO_INTERP1_CTRL_LANE0_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE0 result. This does not
+// affect FULL result.
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_MSB _u(18)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_LSB _u(18)
+#define SIO_INTERP1_CTRL_LANE0_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+// accumulator on POP.
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_LSB _u(17)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+// shift + mask hardware.
+// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+// before the shift+mask bypass)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_LSB _u(16)
+#define SIO_INTERP1_CTRL_LANE0_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+// sign-extended to 32 bits
+// before adding to BASE0, and LANE0 PEEK/POP appear extended to
+// 32 bits when read by processor.
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_MSB _u(15)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_LSB _u(15)
+#define SIO_INTERP1_CTRL_LANE0_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+// (inclusive)
+// Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_MSB _u(14)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_LSB _u(10)
+#define SIO_INTERP1_CTRL_LANE0_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+// (inclusive)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_MSB _u(9)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_LSB _u(5)
+#define SIO_INTERP1_CTRL_LANE0_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE0_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_MSB _u(4)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_LSB _u(0)
+#define SIO_INTERP1_CTRL_LANE0_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_CTRL_LANE1
+// Description : Control register for lane 1
+#define SIO_INTERP1_CTRL_LANE1_OFFSET _u(0x000000f0)
+#define SIO_INTERP1_CTRL_LANE1_BITS _u(0x001fffff)
+#define SIO_INTERP1_CTRL_LANE1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_FORCE_MSB
+// Description : ORed into bits 29:28 of the lane result presented to the
+// processor on the bus.
+// No effect on the internal 32-bit datapath. Handy for using a
+// lane to generate sequence
+// of pointers into flash or SRAM.
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_BITS _u(0x00180000)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_MSB _u(20)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_LSB _u(19)
+#define SIO_INTERP1_CTRL_LANE1_FORCE_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_ADD_RAW
+// Description : If 1, mask + shift is bypassed for LANE1 result. This does not
+// affect FULL result.
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_BITS _u(0x00040000)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_MSB _u(18)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_LSB _u(18)
+#define SIO_INTERP1_CTRL_LANE1_ADD_RAW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_CROSS_RESULT
+// Description : If 1, feed the opposite lane's result into this lane's
+// accumulator on POP.
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_BITS _u(0x00020000)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_MSB _u(17)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_LSB _u(17)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_RESULT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_CROSS_INPUT
+// Description : If 1, feed the opposite lane's accumulator into this lane's
+// shift + mask hardware.
+// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is
+// before the shift+mask bypass)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_BITS _u(0x00010000)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_MSB _u(16)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_LSB _u(16)
+#define SIO_INTERP1_CTRL_LANE1_CROSS_INPUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_SIGNED
+// Description : If SIGNED is set, the shifted and masked accumulator value is
+// sign-extended to 32 bits
+// before adding to BASE1, and LANE1 PEEK/POP appear extended to
+// 32 bits when read by processor.
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_RESET _u(0x0)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_BITS _u(0x00008000)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_MSB _u(15)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_LSB _u(15)
+#define SIO_INTERP1_CTRL_LANE1_SIGNED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_MASK_MSB
+// Description : The most-significant bit allowed to pass by the mask
+// (inclusive)
+// Setting MSB < LSB may cause chip to turn inside-out
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_BITS _u(0x00007c00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_MSB _u(14)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_LSB _u(10)
+#define SIO_INTERP1_CTRL_LANE1_MASK_MSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_MASK_LSB
+// Description : The least-significant bit allowed to pass by the mask
+// (inclusive)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_BITS _u(0x000003e0)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_MSB _u(9)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_LSB _u(5)
+#define SIO_INTERP1_CTRL_LANE1_MASK_LSB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SIO_INTERP1_CTRL_LANE1_SHIFT
+// Description : Logical right-shift applied to accumulator before masking
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_RESET _u(0x00)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_BITS _u(0x0000001f)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_MSB _u(4)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_LSB _u(0)
+#define SIO_INTERP1_CTRL_LANE1_SHIFT_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_ACCUM0_ADD
+// Description : Values written here are atomically added to ACCUM0
+// Reading yields lane 0's raw shift and mask value (BASE0 not
+// added).
+#define SIO_INTERP1_ACCUM0_ADD_OFFSET _u(0x000000f4)
+#define SIO_INTERP1_ACCUM0_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP1_ACCUM0_ADD_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM0_ADD_MSB _u(23)
+#define SIO_INTERP1_ACCUM0_ADD_LSB _u(0)
+#define SIO_INTERP1_ACCUM0_ADD_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_ACCUM1_ADD
+// Description : Values written here are atomically added to ACCUM1
+// Reading yields lane 1's raw shift and mask value (BASE1 not
+// added).
+#define SIO_INTERP1_ACCUM1_ADD_OFFSET _u(0x000000f8)
+#define SIO_INTERP1_ACCUM1_ADD_BITS _u(0x00ffffff)
+#define SIO_INTERP1_ACCUM1_ADD_RESET _u(0x00000000)
+#define SIO_INTERP1_ACCUM1_ADD_MSB _u(23)
+#define SIO_INTERP1_ACCUM1_ADD_LSB _u(0)
+#define SIO_INTERP1_ACCUM1_ADD_ACCESS "RW"
+// =============================================================================
+// Register : SIO_INTERP1_BASE_1AND0
+// Description : On write, the lower 16 bits go to BASE0, upper bits to BASE1
+// simultaneously.
+// Each half is sign-extended to 32 bits if that lane's SIGNED
+// flag is set.
+#define SIO_INTERP1_BASE_1AND0_OFFSET _u(0x000000fc)
+#define SIO_INTERP1_BASE_1AND0_BITS _u(0xffffffff)
+#define SIO_INTERP1_BASE_1AND0_RESET _u(0x00000000)
+#define SIO_INTERP1_BASE_1AND0_MSB _u(31)
+#define SIO_INTERP1_BASE_1AND0_LSB _u(0)
+#define SIO_INTERP1_BASE_1AND0_ACCESS "WO"
+// =============================================================================
+// Register : SIO_SPINLOCK0
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK0_OFFSET _u(0x00000100)
+#define SIO_SPINLOCK0_BITS _u(0xffffffff)
+#define SIO_SPINLOCK0_RESET _u(0x00000000)
+#define SIO_SPINLOCK0_MSB _u(31)
+#define SIO_SPINLOCK0_LSB _u(0)
+#define SIO_SPINLOCK0_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK1
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK1_OFFSET _u(0x00000104)
+#define SIO_SPINLOCK1_BITS _u(0xffffffff)
+#define SIO_SPINLOCK1_RESET _u(0x00000000)
+#define SIO_SPINLOCK1_MSB _u(31)
+#define SIO_SPINLOCK1_LSB _u(0)
+#define SIO_SPINLOCK1_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK2
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK2_OFFSET _u(0x00000108)
+#define SIO_SPINLOCK2_BITS _u(0xffffffff)
+#define SIO_SPINLOCK2_RESET _u(0x00000000)
+#define SIO_SPINLOCK2_MSB _u(31)
+#define SIO_SPINLOCK2_LSB _u(0)
+#define SIO_SPINLOCK2_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK3
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK3_OFFSET _u(0x0000010c)
+#define SIO_SPINLOCK3_BITS _u(0xffffffff)
+#define SIO_SPINLOCK3_RESET _u(0x00000000)
+#define SIO_SPINLOCK3_MSB _u(31)
+#define SIO_SPINLOCK3_LSB _u(0)
+#define SIO_SPINLOCK3_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK4
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK4_OFFSET _u(0x00000110)
+#define SIO_SPINLOCK4_BITS _u(0xffffffff)
+#define SIO_SPINLOCK4_RESET _u(0x00000000)
+#define SIO_SPINLOCK4_MSB _u(31)
+#define SIO_SPINLOCK4_LSB _u(0)
+#define SIO_SPINLOCK4_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK5
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK5_OFFSET _u(0x00000114)
+#define SIO_SPINLOCK5_BITS _u(0xffffffff)
+#define SIO_SPINLOCK5_RESET _u(0x00000000)
+#define SIO_SPINLOCK5_MSB _u(31)
+#define SIO_SPINLOCK5_LSB _u(0)
+#define SIO_SPINLOCK5_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK6
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK6_OFFSET _u(0x00000118)
+#define SIO_SPINLOCK6_BITS _u(0xffffffff)
+#define SIO_SPINLOCK6_RESET _u(0x00000000)
+#define SIO_SPINLOCK6_MSB _u(31)
+#define SIO_SPINLOCK6_LSB _u(0)
+#define SIO_SPINLOCK6_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK7
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK7_OFFSET _u(0x0000011c)
+#define SIO_SPINLOCK7_BITS _u(0xffffffff)
+#define SIO_SPINLOCK7_RESET _u(0x00000000)
+#define SIO_SPINLOCK7_MSB _u(31)
+#define SIO_SPINLOCK7_LSB _u(0)
+#define SIO_SPINLOCK7_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK8
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK8_OFFSET _u(0x00000120)
+#define SIO_SPINLOCK8_BITS _u(0xffffffff)
+#define SIO_SPINLOCK8_RESET _u(0x00000000)
+#define SIO_SPINLOCK8_MSB _u(31)
+#define SIO_SPINLOCK8_LSB _u(0)
+#define SIO_SPINLOCK8_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK9
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK9_OFFSET _u(0x00000124)
+#define SIO_SPINLOCK9_BITS _u(0xffffffff)
+#define SIO_SPINLOCK9_RESET _u(0x00000000)
+#define SIO_SPINLOCK9_MSB _u(31)
+#define SIO_SPINLOCK9_LSB _u(0)
+#define SIO_SPINLOCK9_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK10
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK10_OFFSET _u(0x00000128)
+#define SIO_SPINLOCK10_BITS _u(0xffffffff)
+#define SIO_SPINLOCK10_RESET _u(0x00000000)
+#define SIO_SPINLOCK10_MSB _u(31)
+#define SIO_SPINLOCK10_LSB _u(0)
+#define SIO_SPINLOCK10_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK11
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK11_OFFSET _u(0x0000012c)
+#define SIO_SPINLOCK11_BITS _u(0xffffffff)
+#define SIO_SPINLOCK11_RESET _u(0x00000000)
+#define SIO_SPINLOCK11_MSB _u(31)
+#define SIO_SPINLOCK11_LSB _u(0)
+#define SIO_SPINLOCK11_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK12
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK12_OFFSET _u(0x00000130)
+#define SIO_SPINLOCK12_BITS _u(0xffffffff)
+#define SIO_SPINLOCK12_RESET _u(0x00000000)
+#define SIO_SPINLOCK12_MSB _u(31)
+#define SIO_SPINLOCK12_LSB _u(0)
+#define SIO_SPINLOCK12_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK13
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK13_OFFSET _u(0x00000134)
+#define SIO_SPINLOCK13_BITS _u(0xffffffff)
+#define SIO_SPINLOCK13_RESET _u(0x00000000)
+#define SIO_SPINLOCK13_MSB _u(31)
+#define SIO_SPINLOCK13_LSB _u(0)
+#define SIO_SPINLOCK13_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK14
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK14_OFFSET _u(0x00000138)
+#define SIO_SPINLOCK14_BITS _u(0xffffffff)
+#define SIO_SPINLOCK14_RESET _u(0x00000000)
+#define SIO_SPINLOCK14_MSB _u(31)
+#define SIO_SPINLOCK14_LSB _u(0)
+#define SIO_SPINLOCK14_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK15
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK15_OFFSET _u(0x0000013c)
+#define SIO_SPINLOCK15_BITS _u(0xffffffff)
+#define SIO_SPINLOCK15_RESET _u(0x00000000)
+#define SIO_SPINLOCK15_MSB _u(31)
+#define SIO_SPINLOCK15_LSB _u(0)
+#define SIO_SPINLOCK15_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK16
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK16_OFFSET _u(0x00000140)
+#define SIO_SPINLOCK16_BITS _u(0xffffffff)
+#define SIO_SPINLOCK16_RESET _u(0x00000000)
+#define SIO_SPINLOCK16_MSB _u(31)
+#define SIO_SPINLOCK16_LSB _u(0)
+#define SIO_SPINLOCK16_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK17
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK17_OFFSET _u(0x00000144)
+#define SIO_SPINLOCK17_BITS _u(0xffffffff)
+#define SIO_SPINLOCK17_RESET _u(0x00000000)
+#define SIO_SPINLOCK17_MSB _u(31)
+#define SIO_SPINLOCK17_LSB _u(0)
+#define SIO_SPINLOCK17_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK18
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK18_OFFSET _u(0x00000148)
+#define SIO_SPINLOCK18_BITS _u(0xffffffff)
+#define SIO_SPINLOCK18_RESET _u(0x00000000)
+#define SIO_SPINLOCK18_MSB _u(31)
+#define SIO_SPINLOCK18_LSB _u(0)
+#define SIO_SPINLOCK18_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK19
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK19_OFFSET _u(0x0000014c)
+#define SIO_SPINLOCK19_BITS _u(0xffffffff)
+#define SIO_SPINLOCK19_RESET _u(0x00000000)
+#define SIO_SPINLOCK19_MSB _u(31)
+#define SIO_SPINLOCK19_LSB _u(0)
+#define SIO_SPINLOCK19_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK20
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK20_OFFSET _u(0x00000150)
+#define SIO_SPINLOCK20_BITS _u(0xffffffff)
+#define SIO_SPINLOCK20_RESET _u(0x00000000)
+#define SIO_SPINLOCK20_MSB _u(31)
+#define SIO_SPINLOCK20_LSB _u(0)
+#define SIO_SPINLOCK20_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK21
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK21_OFFSET _u(0x00000154)
+#define SIO_SPINLOCK21_BITS _u(0xffffffff)
+#define SIO_SPINLOCK21_RESET _u(0x00000000)
+#define SIO_SPINLOCK21_MSB _u(31)
+#define SIO_SPINLOCK21_LSB _u(0)
+#define SIO_SPINLOCK21_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK22
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK22_OFFSET _u(0x00000158)
+#define SIO_SPINLOCK22_BITS _u(0xffffffff)
+#define SIO_SPINLOCK22_RESET _u(0x00000000)
+#define SIO_SPINLOCK22_MSB _u(31)
+#define SIO_SPINLOCK22_LSB _u(0)
+#define SIO_SPINLOCK22_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK23
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK23_OFFSET _u(0x0000015c)
+#define SIO_SPINLOCK23_BITS _u(0xffffffff)
+#define SIO_SPINLOCK23_RESET _u(0x00000000)
+#define SIO_SPINLOCK23_MSB _u(31)
+#define SIO_SPINLOCK23_LSB _u(0)
+#define SIO_SPINLOCK23_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK24
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK24_OFFSET _u(0x00000160)
+#define SIO_SPINLOCK24_BITS _u(0xffffffff)
+#define SIO_SPINLOCK24_RESET _u(0x00000000)
+#define SIO_SPINLOCK24_MSB _u(31)
+#define SIO_SPINLOCK24_LSB _u(0)
+#define SIO_SPINLOCK24_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK25
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK25_OFFSET _u(0x00000164)
+#define SIO_SPINLOCK25_BITS _u(0xffffffff)
+#define SIO_SPINLOCK25_RESET _u(0x00000000)
+#define SIO_SPINLOCK25_MSB _u(31)
+#define SIO_SPINLOCK25_LSB _u(0)
+#define SIO_SPINLOCK25_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK26
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK26_OFFSET _u(0x00000168)
+#define SIO_SPINLOCK26_BITS _u(0xffffffff)
+#define SIO_SPINLOCK26_RESET _u(0x00000000)
+#define SIO_SPINLOCK26_MSB _u(31)
+#define SIO_SPINLOCK26_LSB _u(0)
+#define SIO_SPINLOCK26_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK27
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK27_OFFSET _u(0x0000016c)
+#define SIO_SPINLOCK27_BITS _u(0xffffffff)
+#define SIO_SPINLOCK27_RESET _u(0x00000000)
+#define SIO_SPINLOCK27_MSB _u(31)
+#define SIO_SPINLOCK27_LSB _u(0)
+#define SIO_SPINLOCK27_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK28
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK28_OFFSET _u(0x00000170)
+#define SIO_SPINLOCK28_BITS _u(0xffffffff)
+#define SIO_SPINLOCK28_RESET _u(0x00000000)
+#define SIO_SPINLOCK28_MSB _u(31)
+#define SIO_SPINLOCK28_LSB _u(0)
+#define SIO_SPINLOCK28_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK29
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK29_OFFSET _u(0x00000174)
+#define SIO_SPINLOCK29_BITS _u(0xffffffff)
+#define SIO_SPINLOCK29_RESET _u(0x00000000)
+#define SIO_SPINLOCK29_MSB _u(31)
+#define SIO_SPINLOCK29_LSB _u(0)
+#define SIO_SPINLOCK29_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK30
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK30_OFFSET _u(0x00000178)
+#define SIO_SPINLOCK30_BITS _u(0xffffffff)
+#define SIO_SPINLOCK30_RESET _u(0x00000000)
+#define SIO_SPINLOCK30_MSB _u(31)
+#define SIO_SPINLOCK30_LSB _u(0)
+#define SIO_SPINLOCK30_ACCESS "RW"
+// =============================================================================
+// Register : SIO_SPINLOCK31
+// Description : Reading from a spinlock address will:
+// - Return 0 if lock is already locked
+// - Otherwise return nonzero, and simultaneously claim the lock
+//
+// Writing (any value) releases the lock.
+// If core 0 and core 1 attempt to claim the same lock
+// simultaneously, core 0 wins.
+// The value returned on success is 0x1 << lock number.
+#define SIO_SPINLOCK31_OFFSET _u(0x0000017c)
+#define SIO_SPINLOCK31_BITS _u(0xffffffff)
+#define SIO_SPINLOCK31_RESET _u(0x00000000)
+#define SIO_SPINLOCK31_MSB _u(31)
+#define SIO_SPINLOCK31_LSB _u(0)
+#define SIO_SPINLOCK31_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_SIO_DEFINED
diff --git a/arkanoid/pico/hardware/regs/spi.h b/arkanoid/pico/hardware/regs/spi.h
new file mode 100644
index 0000000..816e150
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/spi.h
@@ -0,0 +1,521 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SPI
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_SPI_DEFINED
+#define HARDWARE_REGS_SPI_DEFINED
+// =============================================================================
+// Register : SPI_SSPCR0
+// Description : Control register 0, SSPCR0 on page 3-4
+#define SPI_SSPCR0_OFFSET _u(0x00000000)
+#define SPI_SSPCR0_BITS _u(0x0000ffff)
+#define SPI_SSPCR0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR0_SCR
+// Description : Serial clock rate. The value SCR is used to generate the
+// transmit and receive bit rate of the PrimeCell SSP. The bit
+// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
+// value from 2-254, programmed through the SSPCPSR register and
+// SCR is a value from 0-255.
+#define SPI_SSPCR0_SCR_RESET _u(0x00)
+#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
+#define SPI_SSPCR0_SCR_MSB _u(15)
+#define SPI_SSPCR0_SCR_LSB _u(8)
+#define SPI_SSPCR0_SCR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR0_SPH
+// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
+// See Motorola SPI frame format on page 2-10.
+#define SPI_SSPCR0_SPH_RESET _u(0x0)
+#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
+#define SPI_SSPCR0_SPH_MSB _u(7)
+#define SPI_SSPCR0_SPH_LSB _u(7)
+#define SPI_SSPCR0_SPH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR0_SPO
+// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
+// only. See Motorola SPI frame format on page 2-10.
+#define SPI_SSPCR0_SPO_RESET _u(0x0)
+#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
+#define SPI_SSPCR0_SPO_MSB _u(6)
+#define SPI_SSPCR0_SPO_LSB _u(6)
+#define SPI_SSPCR0_SPO_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR0_FRF
+// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
+// serial frame format. 10 National Microwire frame format. 11
+// Reserved, undefined operation.
+#define SPI_SSPCR0_FRF_RESET _u(0x0)
+#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
+#define SPI_SSPCR0_FRF_MSB _u(5)
+#define SPI_SSPCR0_FRF_LSB _u(4)
+#define SPI_SSPCR0_FRF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR0_DSS
+// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
+// Reserved, undefined operation. 0010 Reserved, undefined
+// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
+// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
+// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
+// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
+#define SPI_SSPCR0_DSS_RESET _u(0x0)
+#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
+#define SPI_SSPCR0_DSS_MSB _u(3)
+#define SPI_SSPCR0_DSS_LSB _u(0)
+#define SPI_SSPCR0_DSS_ACCESS "RW"
+// =============================================================================
+// Register : SPI_SSPCR1
+// Description : Control register 1, SSPCR1 on page 3-5
+#define SPI_SSPCR1_OFFSET _u(0x00000004)
+#define SPI_SSPCR1_BITS _u(0x0000000f)
+#define SPI_SSPCR1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR1_SOD
+// Description : Slave-mode output disable. This bit is relevant only in the
+// slave mode, MS=1. In multiple-slave systems, it is possible for
+// an PrimeCell SSP master to broadcast a message to all slaves in
+// the system while ensuring that only one slave drives data onto
+// its serial output line. In such systems the RXD lines from
+// multiple slaves could be tied together. To operate in such
+// systems, the SOD bit can be set if the PrimeCell SSP slave is
+// not supposed to drive the SSPTXD line: 0 SSP can drive the
+// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
+// output in slave mode.
+#define SPI_SSPCR1_SOD_RESET _u(0x0)
+#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
+#define SPI_SSPCR1_SOD_MSB _u(3)
+#define SPI_SSPCR1_SOD_LSB _u(3)
+#define SPI_SSPCR1_SOD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR1_MS
+// Description : Master or slave mode select. This bit can be modified only when
+// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
+// master, default. 1 Device configured as slave.
+#define SPI_SSPCR1_MS_RESET _u(0x0)
+#define SPI_SSPCR1_MS_BITS _u(0x00000004)
+#define SPI_SSPCR1_MS_MSB _u(2)
+#define SPI_SSPCR1_MS_LSB _u(2)
+#define SPI_SSPCR1_MS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR1_SSE
+// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
+// operation enabled.
+#define SPI_SSPCR1_SSE_RESET _u(0x0)
+#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
+#define SPI_SSPCR1_SSE_MSB _u(1)
+#define SPI_SSPCR1_SSE_LSB _u(1)
+#define SPI_SSPCR1_SSE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCR1_LBM
+// Description : Loop back mode: 0 Normal serial port operation enabled. 1
+// Output of transmit serial shifter is connected to input of
+// receive serial shifter internally.
+#define SPI_SSPCR1_LBM_RESET _u(0x0)
+#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
+#define SPI_SSPCR1_LBM_MSB _u(0)
+#define SPI_SSPCR1_LBM_LSB _u(0)
+#define SPI_SSPCR1_LBM_ACCESS "RW"
+// =============================================================================
+// Register : SPI_SSPDR
+// Description : Data register, SSPDR on page 3-6
+#define SPI_SSPDR_OFFSET _u(0x00000008)
+#define SPI_SSPDR_BITS _u(0x0000ffff)
+#define SPI_SSPDR_RESET "-"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPDR_DATA
+// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
+// You must right-justify data when the PrimeCell SSP is
+// programmed for a data size that is less than 16 bits. Unused
+// bits at the top are ignored by transmit logic. The receive
+// logic automatically right-justifies.
+#define SPI_SSPDR_DATA_RESET "-"
+#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
+#define SPI_SSPDR_DATA_MSB _u(15)
+#define SPI_SSPDR_DATA_LSB _u(0)
+#define SPI_SSPDR_DATA_ACCESS "RWF"
+// =============================================================================
+// Register : SPI_SSPSR
+// Description : Status register, SSPSR on page 3-7
+#define SPI_SSPSR_OFFSET _u(0x0000000c)
+#define SPI_SSPSR_BITS _u(0x0000001f)
+#define SPI_SSPSR_RESET _u(0x00000003)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPSR_BSY
+// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
+// transmitting and/or receiving a frame or the transmit FIFO is
+// not empty.
+#define SPI_SSPSR_BSY_RESET _u(0x0)
+#define SPI_SSPSR_BSY_BITS _u(0x00000010)
+#define SPI_SSPSR_BSY_MSB _u(4)
+#define SPI_SSPSR_BSY_LSB _u(4)
+#define SPI_SSPSR_BSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPSR_RFF
+// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
+// FIFO is full.
+#define SPI_SSPSR_RFF_RESET _u(0x0)
+#define SPI_SSPSR_RFF_BITS _u(0x00000008)
+#define SPI_SSPSR_RFF_MSB _u(3)
+#define SPI_SSPSR_RFF_LSB _u(3)
+#define SPI_SSPSR_RFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPSR_RNE
+// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
+// FIFO is not empty.
+#define SPI_SSPSR_RNE_RESET _u(0x0)
+#define SPI_SSPSR_RNE_BITS _u(0x00000004)
+#define SPI_SSPSR_RNE_MSB _u(2)
+#define SPI_SSPSR_RNE_LSB _u(2)
+#define SPI_SSPSR_RNE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPSR_TNF
+// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
+// FIFO is not full.
+#define SPI_SSPSR_TNF_RESET _u(0x1)
+#define SPI_SSPSR_TNF_BITS _u(0x00000002)
+#define SPI_SSPSR_TNF_MSB _u(1)
+#define SPI_SSPSR_TNF_LSB _u(1)
+#define SPI_SSPSR_TNF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPSR_TFE
+// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
+// Transmit FIFO is empty.
+#define SPI_SSPSR_TFE_RESET _u(0x1)
+#define SPI_SSPSR_TFE_BITS _u(0x00000001)
+#define SPI_SSPSR_TFE_MSB _u(0)
+#define SPI_SSPSR_TFE_LSB _u(0)
+#define SPI_SSPSR_TFE_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPCPSR
+// Description : Clock prescale register, SSPCPSR on page 3-8
+#define SPI_SSPCPSR_OFFSET _u(0x00000010)
+#define SPI_SSPCPSR_BITS _u(0x000000ff)
+#define SPI_SSPCPSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPCPSR_CPSDVSR
+// Description : Clock prescale divisor. Must be an even number from 2-254,
+// depending on the frequency of SSPCLK. The least significant bit
+// always returns zero on reads.
+#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
+#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
+#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
+#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
+#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
+// =============================================================================
+// Register : SPI_SSPIMSC
+// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
+#define SPI_SSPIMSC_OFFSET _u(0x00000014)
+#define SPI_SSPIMSC_BITS _u(0x0000000f)
+#define SPI_SSPIMSC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPIMSC_TXIM
+// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
+// less condition interrupt is masked. 1 Transmit FIFO half empty
+// or less condition interrupt is not masked.
+#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
+#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
+#define SPI_SSPIMSC_TXIM_MSB _u(3)
+#define SPI_SSPIMSC_TXIM_LSB _u(3)
+#define SPI_SSPIMSC_TXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPIMSC_RXIM
+// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
+// condition interrupt is masked. 1 Receive FIFO half full or less
+// condition interrupt is not masked.
+#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
+#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
+#define SPI_SSPIMSC_RXIM_MSB _u(2)
+#define SPI_SSPIMSC_RXIM_LSB _u(2)
+#define SPI_SSPIMSC_RXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPIMSC_RTIM
+// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
+// read prior to timeout period interrupt is masked. 1 Receive
+// FIFO not empty and no read prior to timeout period interrupt is
+// not masked.
+#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
+#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
+#define SPI_SSPIMSC_RTIM_MSB _u(1)
+#define SPI_SSPIMSC_RTIM_LSB _u(1)
+#define SPI_SSPIMSC_RTIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPIMSC_RORIM
+// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
+// full condition interrupt is masked. 1 Receive FIFO written to
+// while full condition interrupt is not masked.
+#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
+#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
+#define SPI_SSPIMSC_RORIM_MSB _u(0)
+#define SPI_SSPIMSC_RORIM_LSB _u(0)
+#define SPI_SSPIMSC_RORIM_ACCESS "RW"
+// =============================================================================
+// Register : SPI_SSPRIS
+// Description : Raw interrupt status register, SSPRIS on page 3-10
+#define SPI_SSPRIS_OFFSET _u(0x00000018)
+#define SPI_SSPRIS_BITS _u(0x0000000f)
+#define SPI_SSPRIS_RESET _u(0x00000008)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPRIS_TXRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+// SSPTXINTR interrupt
+#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
+#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
+#define SPI_SSPRIS_TXRIS_MSB _u(3)
+#define SPI_SSPRIS_TXRIS_LSB _u(3)
+#define SPI_SSPRIS_TXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPRIS_RXRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+// SSPRXINTR interrupt
+#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
+#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
+#define SPI_SSPRIS_RXRIS_MSB _u(2)
+#define SPI_SSPRIS_RXRIS_LSB _u(2)
+#define SPI_SSPRIS_RXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPRIS_RTRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+// SSPRTINTR interrupt
+#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
+#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
+#define SPI_SSPRIS_RTRIS_MSB _u(1)
+#define SPI_SSPRIS_RTRIS_LSB _u(1)
+#define SPI_SSPRIS_RTRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPRIS_RORRIS
+// Description : Gives the raw interrupt state, prior to masking, of the
+// SSPRORINTR interrupt
+#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
+#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
+#define SPI_SSPRIS_RORRIS_MSB _u(0)
+#define SPI_SSPRIS_RORRIS_LSB _u(0)
+#define SPI_SSPRIS_RORRIS_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPMIS
+// Description : Masked interrupt status register, SSPMIS on page 3-11
+#define SPI_SSPMIS_OFFSET _u(0x0000001c)
+#define SPI_SSPMIS_BITS _u(0x0000000f)
+#define SPI_SSPMIS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPMIS_TXMIS
+// Description : Gives the transmit FIFO masked interrupt state, after masking,
+// of the SSPTXINTR interrupt
+#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
+#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
+#define SPI_SSPMIS_TXMIS_MSB _u(3)
+#define SPI_SSPMIS_TXMIS_LSB _u(3)
+#define SPI_SSPMIS_TXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPMIS_RXMIS
+// Description : Gives the receive FIFO masked interrupt state, after masking,
+// of the SSPRXINTR interrupt
+#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
+#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
+#define SPI_SSPMIS_RXMIS_MSB _u(2)
+#define SPI_SSPMIS_RXMIS_LSB _u(2)
+#define SPI_SSPMIS_RXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPMIS_RTMIS
+// Description : Gives the receive timeout masked interrupt state, after
+// masking, of the SSPRTINTR interrupt
+#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
+#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
+#define SPI_SSPMIS_RTMIS_MSB _u(1)
+#define SPI_SSPMIS_RTMIS_LSB _u(1)
+#define SPI_SSPMIS_RTMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPMIS_RORMIS
+// Description : Gives the receive over run masked interrupt status, after
+// masking, of the SSPRORINTR interrupt
+#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
+#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
+#define SPI_SSPMIS_RORMIS_MSB _u(0)
+#define SPI_SSPMIS_RORMIS_LSB _u(0)
+#define SPI_SSPMIS_RORMIS_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPICR
+// Description : Interrupt clear register, SSPICR on page 3-11
+#define SPI_SSPICR_OFFSET _u(0x00000020)
+#define SPI_SSPICR_BITS _u(0x00000003)
+#define SPI_SSPICR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPICR_RTIC
+// Description : Clears the SSPRTINTR interrupt
+#define SPI_SSPICR_RTIC_RESET _u(0x0)
+#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
+#define SPI_SSPICR_RTIC_MSB _u(1)
+#define SPI_SSPICR_RTIC_LSB _u(1)
+#define SPI_SSPICR_RTIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPICR_RORIC
+// Description : Clears the SSPRORINTR interrupt
+#define SPI_SSPICR_RORIC_RESET _u(0x0)
+#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
+#define SPI_SSPICR_RORIC_MSB _u(0)
+#define SPI_SSPICR_RORIC_LSB _u(0)
+#define SPI_SSPICR_RORIC_ACCESS "WC"
+// =============================================================================
+// Register : SPI_SSPDMACR
+// Description : DMA control register, SSPDMACR on page 3-12
+#define SPI_SSPDMACR_OFFSET _u(0x00000024)
+#define SPI_SSPDMACR_BITS _u(0x00000003)
+#define SPI_SSPDMACR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPDMACR_TXDMAE
+// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
+// transmit FIFO is enabled.
+#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
+#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
+#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
+#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
+#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPDMACR_RXDMAE
+// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
+// receive FIFO is enabled.
+#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
+#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
+#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
+#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
+#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
+// =============================================================================
+// Register : SPI_SSPPERIPHID0
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+// 3-13
+#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
+#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPERIPHID0_PARTNUMBER0
+// Description : These bits read back as 0x22
+#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
+#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPPERIPHID1
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+// 3-13
+#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
+#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPERIPHID1_DESIGNER0
+// Description : These bits read back as 0x1
+#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
+#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
+#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
+#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
+#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPERIPHID1_PARTNUMBER1
+// Description : These bits read back as 0x0
+#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
+#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPPERIPHID2
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+// 3-13
+#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
+#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPERIPHID2_REVISION
+// Description : These bits return the peripheral revision
+#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
+#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
+#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
+#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
+#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPERIPHID2_DESIGNER1
+// Description : These bits read back as 0x4
+#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
+#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
+#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
+#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
+#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPPERIPHID3
+// Description : Peripheral identification registers, SSPPeriphID0-3 on page
+// 3-13
+#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
+#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPERIPHID3_CONFIGURATION
+// Description : These bits read back as 0x00
+#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
+#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
+#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
+#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
+#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPPCELLID0
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
+#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPCELLID0_SSPPCELLID0
+// Description : These bits read back as 0x0D
+#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
+#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
+#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
+#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPPCELLID1
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
+#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPCELLID1_SSPPCELLID1
+// Description : These bits read back as 0xF0
+#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
+#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
+#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
+#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPPCELLID2
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
+#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID2_RESET _u(0x00000005)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPCELLID2_SSPPCELLID2
+// Description : These bits read back as 0x05
+#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
+#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
+#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
+#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
+// =============================================================================
+// Register : SPI_SSPPCELLID3
+// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
+#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
+// -----------------------------------------------------------------------------
+// Field : SPI_SSPPCELLID3_SSPPCELLID3
+// Description : These bits read back as 0xB1
+#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
+#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
+#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
+#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
+#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_SPI_DEFINED
diff --git a/arkanoid/pico/hardware/regs/ssi.h b/arkanoid/pico/hardware/regs/ssi.h
new file mode 100644
index 0000000..67fddc0
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/ssi.h
@@ -0,0 +1,809 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SSI
+// Version : 1
+// Bus type : apb
+// Description : DW_apb_ssi has the following features:
+// * APB interface – Allows for easy integration into a
+// DesignWare Synthesizable Components for AMBA 2
+// implementation.
+// * APB3 and APB4 protocol support.
+// * Scalable APB data bus width – Supports APB data bus widths
+// of 8, 16, and 32 bits.
+// * Serial-master or serial-slave operation – Enables serial
+// communication with serial-master or serial-slave peripheral
+// devices.
+// * Programmable Dual/Quad/Octal SPI support in Master Mode.
+// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support -
+// Enables the DW_apb_ssi master to perform operations with the
+// device in DDR and RDS modes when working in Dual/Quad/Octal
+// mode of operation.
+// * Data Mask Support - Enables the DW_apb_ssi to selectively
+// update the bytes in the device. This feature is applicable
+// only in enhanced SPI modes.
+// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi
+// master to behave as a memory mapped I/O and fetches the data
+// from the device based on the APB read request. This feature
+// is applicable only in enhanced SPI modes.
+// * DMA Controller Interface – Enables the DW_apb_ssi to
+// interface to a DMA controller over the bus using a
+// handshaking interface for transfer requests.
+// * Independent masking of interrupts – Master collision,
+// transmit FIFO overflow, transmit FIFO empty, receive FIFO
+// full, receive FIFO underflow, and receive FIFO overflow
+// interrupts can all be masked independently.
+// * Multi-master contention detection – Informs the processor
+// of multiple serial-master accesses on the serial bus.
+// * Bypass of meta-stability flip-flops for synchronous clocks
+// – When the APB clock (pclk) and the DW_apb_ssi serial clock
+// (ssi_clk) are synchronous, meta-stable flip-flops are not
+// used when transferring control signals across these clock
+// domains.
+// * Programmable delay on the sample time of the received
+// serial data bit (rxd); enables programmable control of
+// routing delays resulting in higher serial data-bit rates.
+// * Programmable features:
+// - Serial interface operation – Choice of Motorola SPI, Texas
+// Instruments Synchronous Serial Protocol or National
+// Semiconductor Microwire.
+// - Clock bit-rate – Dynamic control of the serial bit rate of
+// the data transfer; used in only serial-master mode of
+// operation.
+// - Data Item size (4 to 32 bits) – Item size of each data
+// transfer under the control of the programmer.
+// * Configured features:
+// - FIFO depth – 16 words deep. The FIFO width is fixed at 32
+// bits.
+// - 1 slave select output.
+// - Hardware slave-select – Dedicated hardware slave-select
+// line.
+// - Combined interrupt line - one combined interrupt line from
+// the DW_apb_ssi to the interrupt controller.
+// - Interrupt polarity – active high interrupt lines.
+// - Serial clock polarity – low serial-clock polarity directly
+// after reset.
+// - Serial clock phase – capture on first edge of serial-clock
+// directly after reset.
+// =============================================================================
+#ifndef HARDWARE_REGS_SSI_DEFINED
+#define HARDWARE_REGS_SSI_DEFINED
+// =============================================================================
+// Register : SSI_CTRLR0
+// Description : Control register 0
+#define SSI_CTRLR0_OFFSET _u(0x00000000)
+#define SSI_CTRLR0_BITS _u(0x017fffff)
+#define SSI_CTRLR0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_SSTE
+// Description : Slave select toggle enable
+#define SSI_CTRLR0_SSTE_RESET _u(0x0)
+#define SSI_CTRLR0_SSTE_BITS _u(0x01000000)
+#define SSI_CTRLR0_SSTE_MSB _u(24)
+#define SSI_CTRLR0_SSTE_LSB _u(24)
+#define SSI_CTRLR0_SSTE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_SPI_FRF
+// Description : SPI frame format
+// 0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK,
+// full-duplex
+// 0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex
+// 0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex
+#define SSI_CTRLR0_SPI_FRF_RESET _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_BITS _u(0x00600000)
+#define SSI_CTRLR0_SPI_FRF_MSB _u(22)
+#define SSI_CTRLR0_SPI_FRF_LSB _u(21)
+#define SSI_CTRLR0_SPI_FRF_ACCESS "RW"
+#define SSI_CTRLR0_SPI_FRF_VALUE_STD _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1)
+#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_DFS_32
+// Description : Data frame size in 32b transfer mode
+// Value of n -> n+1 clocks per frame.
+#define SSI_CTRLR0_DFS_32_RESET _u(0x00)
+#define SSI_CTRLR0_DFS_32_BITS _u(0x001f0000)
+#define SSI_CTRLR0_DFS_32_MSB _u(20)
+#define SSI_CTRLR0_DFS_32_LSB _u(16)
+#define SSI_CTRLR0_DFS_32_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_CFS
+// Description : Control frame size
+// Value of n -> n+1 clocks per frame.
+#define SSI_CTRLR0_CFS_RESET _u(0x0)
+#define SSI_CTRLR0_CFS_BITS _u(0x0000f000)
+#define SSI_CTRLR0_CFS_MSB _u(15)
+#define SSI_CTRLR0_CFS_LSB _u(12)
+#define SSI_CTRLR0_CFS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_SRL
+// Description : Shift register loop (test mode)
+#define SSI_CTRLR0_SRL_RESET _u(0x0)
+#define SSI_CTRLR0_SRL_BITS _u(0x00000800)
+#define SSI_CTRLR0_SRL_MSB _u(11)
+#define SSI_CTRLR0_SRL_LSB _u(11)
+#define SSI_CTRLR0_SRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_SLV_OE
+// Description : Slave output enable
+#define SSI_CTRLR0_SLV_OE_RESET _u(0x0)
+#define SSI_CTRLR0_SLV_OE_BITS _u(0x00000400)
+#define SSI_CTRLR0_SLV_OE_MSB _u(10)
+#define SSI_CTRLR0_SLV_OE_LSB _u(10)
+#define SSI_CTRLR0_SLV_OE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_TMOD
+// Description : Transfer mode
+// 0x0 -> Both transmit and receive
+// 0x1 -> Transmit only (not for FRF == 0, standard SPI mode)
+// 0x2 -> Receive only (not for FRF == 0, standard SPI mode)
+// 0x3 -> EEPROM read mode (TX then RX; RX starts after control
+// data TX'd)
+#define SSI_CTRLR0_TMOD_RESET _u(0x0)
+#define SSI_CTRLR0_TMOD_BITS _u(0x00000300)
+#define SSI_CTRLR0_TMOD_MSB _u(9)
+#define SSI_CTRLR0_TMOD_LSB _u(8)
+#define SSI_CTRLR0_TMOD_ACCESS "RW"
+#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX _u(0x0)
+#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY _u(0x1)
+#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY _u(0x2)
+#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_SCPOL
+// Description : Serial clock polarity
+#define SSI_CTRLR0_SCPOL_RESET _u(0x0)
+#define SSI_CTRLR0_SCPOL_BITS _u(0x00000080)
+#define SSI_CTRLR0_SCPOL_MSB _u(7)
+#define SSI_CTRLR0_SCPOL_LSB _u(7)
+#define SSI_CTRLR0_SCPOL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_SCPH
+// Description : Serial clock phase
+#define SSI_CTRLR0_SCPH_RESET _u(0x0)
+#define SSI_CTRLR0_SCPH_BITS _u(0x00000040)
+#define SSI_CTRLR0_SCPH_MSB _u(6)
+#define SSI_CTRLR0_SCPH_LSB _u(6)
+#define SSI_CTRLR0_SCPH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_FRF
+// Description : Frame format
+#define SSI_CTRLR0_FRF_RESET _u(0x0)
+#define SSI_CTRLR0_FRF_BITS _u(0x00000030)
+#define SSI_CTRLR0_FRF_MSB _u(5)
+#define SSI_CTRLR0_FRF_LSB _u(4)
+#define SSI_CTRLR0_FRF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR0_DFS
+// Description : Data frame size
+#define SSI_CTRLR0_DFS_RESET _u(0x0)
+#define SSI_CTRLR0_DFS_BITS _u(0x0000000f)
+#define SSI_CTRLR0_DFS_MSB _u(3)
+#define SSI_CTRLR0_DFS_LSB _u(0)
+#define SSI_CTRLR0_DFS_ACCESS "RW"
+// =============================================================================
+// Register : SSI_CTRLR1
+// Description : Master Control register 1
+#define SSI_CTRLR1_OFFSET _u(0x00000004)
+#define SSI_CTRLR1_BITS _u(0x0000ffff)
+#define SSI_CTRLR1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_CTRLR1_NDF
+// Description : Number of data frames
+#define SSI_CTRLR1_NDF_RESET _u(0x0000)
+#define SSI_CTRLR1_NDF_BITS _u(0x0000ffff)
+#define SSI_CTRLR1_NDF_MSB _u(15)
+#define SSI_CTRLR1_NDF_LSB _u(0)
+#define SSI_CTRLR1_NDF_ACCESS "RW"
+// =============================================================================
+// Register : SSI_SSIENR
+// Description : SSI Enable
+#define SSI_SSIENR_OFFSET _u(0x00000008)
+#define SSI_SSIENR_BITS _u(0x00000001)
+#define SSI_SSIENR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_SSIENR_SSI_EN
+// Description : SSI enable
+#define SSI_SSIENR_SSI_EN_RESET _u(0x0)
+#define SSI_SSIENR_SSI_EN_BITS _u(0x00000001)
+#define SSI_SSIENR_SSI_EN_MSB _u(0)
+#define SSI_SSIENR_SSI_EN_LSB _u(0)
+#define SSI_SSIENR_SSI_EN_ACCESS "RW"
+// =============================================================================
+// Register : SSI_MWCR
+// Description : Microwire Control
+#define SSI_MWCR_OFFSET _u(0x0000000c)
+#define SSI_MWCR_BITS _u(0x00000007)
+#define SSI_MWCR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_MWCR_MHS
+// Description : Microwire handshaking
+#define SSI_MWCR_MHS_RESET _u(0x0)
+#define SSI_MWCR_MHS_BITS _u(0x00000004)
+#define SSI_MWCR_MHS_MSB _u(2)
+#define SSI_MWCR_MHS_LSB _u(2)
+#define SSI_MWCR_MHS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_MWCR_MDD
+// Description : Microwire control
+#define SSI_MWCR_MDD_RESET _u(0x0)
+#define SSI_MWCR_MDD_BITS _u(0x00000002)
+#define SSI_MWCR_MDD_MSB _u(1)
+#define SSI_MWCR_MDD_LSB _u(1)
+#define SSI_MWCR_MDD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_MWCR_MWMOD
+// Description : Microwire transfer mode
+#define SSI_MWCR_MWMOD_RESET _u(0x0)
+#define SSI_MWCR_MWMOD_BITS _u(0x00000001)
+#define SSI_MWCR_MWMOD_MSB _u(0)
+#define SSI_MWCR_MWMOD_LSB _u(0)
+#define SSI_MWCR_MWMOD_ACCESS "RW"
+// =============================================================================
+// Register : SSI_SER
+// Description : Slave enable
+// For each bit:
+// 0 -> slave not selected
+// 1 -> slave selected
+#define SSI_SER_OFFSET _u(0x00000010)
+#define SSI_SER_BITS _u(0x00000001)
+#define SSI_SER_RESET _u(0x00000000)
+#define SSI_SER_MSB _u(0)
+#define SSI_SER_LSB _u(0)
+#define SSI_SER_ACCESS "RW"
+// =============================================================================
+// Register : SSI_BAUDR
+// Description : Baud rate
+#define SSI_BAUDR_OFFSET _u(0x00000014)
+#define SSI_BAUDR_BITS _u(0x0000ffff)
+#define SSI_BAUDR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_BAUDR_SCKDV
+// Description : SSI clock divider
+#define SSI_BAUDR_SCKDV_RESET _u(0x0000)
+#define SSI_BAUDR_SCKDV_BITS _u(0x0000ffff)
+#define SSI_BAUDR_SCKDV_MSB _u(15)
+#define SSI_BAUDR_SCKDV_LSB _u(0)
+#define SSI_BAUDR_SCKDV_ACCESS "RW"
+// =============================================================================
+// Register : SSI_TXFTLR
+// Description : TX FIFO threshold level
+#define SSI_TXFTLR_OFFSET _u(0x00000018)
+#define SSI_TXFTLR_BITS _u(0x000000ff)
+#define SSI_TXFTLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_TXFTLR_TFT
+// Description : Transmit FIFO threshold
+#define SSI_TXFTLR_TFT_RESET _u(0x00)
+#define SSI_TXFTLR_TFT_BITS _u(0x000000ff)
+#define SSI_TXFTLR_TFT_MSB _u(7)
+#define SSI_TXFTLR_TFT_LSB _u(0)
+#define SSI_TXFTLR_TFT_ACCESS "RW"
+// =============================================================================
+// Register : SSI_RXFTLR
+// Description : RX FIFO threshold level
+#define SSI_RXFTLR_OFFSET _u(0x0000001c)
+#define SSI_RXFTLR_BITS _u(0x000000ff)
+#define SSI_RXFTLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_RXFTLR_RFT
+// Description : Receive FIFO threshold
+#define SSI_RXFTLR_RFT_RESET _u(0x00)
+#define SSI_RXFTLR_RFT_BITS _u(0x000000ff)
+#define SSI_RXFTLR_RFT_MSB _u(7)
+#define SSI_RXFTLR_RFT_LSB _u(0)
+#define SSI_RXFTLR_RFT_ACCESS "RW"
+// =============================================================================
+// Register : SSI_TXFLR
+// Description : TX FIFO level
+#define SSI_TXFLR_OFFSET _u(0x00000020)
+#define SSI_TXFLR_BITS _u(0x000000ff)
+#define SSI_TXFLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_TXFLR_TFTFL
+// Description : Transmit FIFO level
+#define SSI_TXFLR_TFTFL_RESET _u(0x00)
+#define SSI_TXFLR_TFTFL_BITS _u(0x000000ff)
+#define SSI_TXFLR_TFTFL_MSB _u(7)
+#define SSI_TXFLR_TFTFL_LSB _u(0)
+#define SSI_TXFLR_TFTFL_ACCESS "RO"
+// =============================================================================
+// Register : SSI_RXFLR
+// Description : RX FIFO level
+#define SSI_RXFLR_OFFSET _u(0x00000024)
+#define SSI_RXFLR_BITS _u(0x000000ff)
+#define SSI_RXFLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_RXFLR_RXTFL
+// Description : Receive FIFO level
+#define SSI_RXFLR_RXTFL_RESET _u(0x00)
+#define SSI_RXFLR_RXTFL_BITS _u(0x000000ff)
+#define SSI_RXFLR_RXTFL_MSB _u(7)
+#define SSI_RXFLR_RXTFL_LSB _u(0)
+#define SSI_RXFLR_RXTFL_ACCESS "RO"
+// =============================================================================
+// Register : SSI_SR
+// Description : Status register
+#define SSI_SR_OFFSET _u(0x00000028)
+#define SSI_SR_BITS _u(0x0000007f)
+#define SSI_SR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_SR_DCOL
+// Description : Data collision error
+#define SSI_SR_DCOL_RESET _u(0x0)
+#define SSI_SR_DCOL_BITS _u(0x00000040)
+#define SSI_SR_DCOL_MSB _u(6)
+#define SSI_SR_DCOL_LSB _u(6)
+#define SSI_SR_DCOL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_SR_TXE
+// Description : Transmission error
+#define SSI_SR_TXE_RESET _u(0x0)
+#define SSI_SR_TXE_BITS _u(0x00000020)
+#define SSI_SR_TXE_MSB _u(5)
+#define SSI_SR_TXE_LSB _u(5)
+#define SSI_SR_TXE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_SR_RFF
+// Description : Receive FIFO full
+#define SSI_SR_RFF_RESET _u(0x0)
+#define SSI_SR_RFF_BITS _u(0x00000010)
+#define SSI_SR_RFF_MSB _u(4)
+#define SSI_SR_RFF_LSB _u(4)
+#define SSI_SR_RFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_SR_RFNE
+// Description : Receive FIFO not empty
+#define SSI_SR_RFNE_RESET _u(0x0)
+#define SSI_SR_RFNE_BITS _u(0x00000008)
+#define SSI_SR_RFNE_MSB _u(3)
+#define SSI_SR_RFNE_LSB _u(3)
+#define SSI_SR_RFNE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_SR_TFE
+// Description : Transmit FIFO empty
+#define SSI_SR_TFE_RESET _u(0x0)
+#define SSI_SR_TFE_BITS _u(0x00000004)
+#define SSI_SR_TFE_MSB _u(2)
+#define SSI_SR_TFE_LSB _u(2)
+#define SSI_SR_TFE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_SR_TFNF
+// Description : Transmit FIFO not full
+#define SSI_SR_TFNF_RESET _u(0x0)
+#define SSI_SR_TFNF_BITS _u(0x00000002)
+#define SSI_SR_TFNF_MSB _u(1)
+#define SSI_SR_TFNF_LSB _u(1)
+#define SSI_SR_TFNF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_SR_BUSY
+// Description : SSI busy flag
+#define SSI_SR_BUSY_RESET _u(0x0)
+#define SSI_SR_BUSY_BITS _u(0x00000001)
+#define SSI_SR_BUSY_MSB _u(0)
+#define SSI_SR_BUSY_LSB _u(0)
+#define SSI_SR_BUSY_ACCESS "RO"
+// =============================================================================
+// Register : SSI_IMR
+// Description : Interrupt mask
+#define SSI_IMR_OFFSET _u(0x0000002c)
+#define SSI_IMR_BITS _u(0x0000003f)
+#define SSI_IMR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_IMR_MSTIM
+// Description : Multi-master contention interrupt mask
+#define SSI_IMR_MSTIM_RESET _u(0x0)
+#define SSI_IMR_MSTIM_BITS _u(0x00000020)
+#define SSI_IMR_MSTIM_MSB _u(5)
+#define SSI_IMR_MSTIM_LSB _u(5)
+#define SSI_IMR_MSTIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_IMR_RXFIM
+// Description : Receive FIFO full interrupt mask
+#define SSI_IMR_RXFIM_RESET _u(0x0)
+#define SSI_IMR_RXFIM_BITS _u(0x00000010)
+#define SSI_IMR_RXFIM_MSB _u(4)
+#define SSI_IMR_RXFIM_LSB _u(4)
+#define SSI_IMR_RXFIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_IMR_RXOIM
+// Description : Receive FIFO overflow interrupt mask
+#define SSI_IMR_RXOIM_RESET _u(0x0)
+#define SSI_IMR_RXOIM_BITS _u(0x00000008)
+#define SSI_IMR_RXOIM_MSB _u(3)
+#define SSI_IMR_RXOIM_LSB _u(3)
+#define SSI_IMR_RXOIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_IMR_RXUIM
+// Description : Receive FIFO underflow interrupt mask
+#define SSI_IMR_RXUIM_RESET _u(0x0)
+#define SSI_IMR_RXUIM_BITS _u(0x00000004)
+#define SSI_IMR_RXUIM_MSB _u(2)
+#define SSI_IMR_RXUIM_LSB _u(2)
+#define SSI_IMR_RXUIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_IMR_TXOIM
+// Description : Transmit FIFO overflow interrupt mask
+#define SSI_IMR_TXOIM_RESET _u(0x0)
+#define SSI_IMR_TXOIM_BITS _u(0x00000002)
+#define SSI_IMR_TXOIM_MSB _u(1)
+#define SSI_IMR_TXOIM_LSB _u(1)
+#define SSI_IMR_TXOIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_IMR_TXEIM
+// Description : Transmit FIFO empty interrupt mask
+#define SSI_IMR_TXEIM_RESET _u(0x0)
+#define SSI_IMR_TXEIM_BITS _u(0x00000001)
+#define SSI_IMR_TXEIM_MSB _u(0)
+#define SSI_IMR_TXEIM_LSB _u(0)
+#define SSI_IMR_TXEIM_ACCESS "RW"
+// =============================================================================
+// Register : SSI_ISR
+// Description : Interrupt status
+#define SSI_ISR_OFFSET _u(0x00000030)
+#define SSI_ISR_BITS _u(0x0000003f)
+#define SSI_ISR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_ISR_MSTIS
+// Description : Multi-master contention interrupt status
+#define SSI_ISR_MSTIS_RESET _u(0x0)
+#define SSI_ISR_MSTIS_BITS _u(0x00000020)
+#define SSI_ISR_MSTIS_MSB _u(5)
+#define SSI_ISR_MSTIS_LSB _u(5)
+#define SSI_ISR_MSTIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_ISR_RXFIS
+// Description : Receive FIFO full interrupt status
+#define SSI_ISR_RXFIS_RESET _u(0x0)
+#define SSI_ISR_RXFIS_BITS _u(0x00000010)
+#define SSI_ISR_RXFIS_MSB _u(4)
+#define SSI_ISR_RXFIS_LSB _u(4)
+#define SSI_ISR_RXFIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_ISR_RXOIS
+// Description : Receive FIFO overflow interrupt status
+#define SSI_ISR_RXOIS_RESET _u(0x0)
+#define SSI_ISR_RXOIS_BITS _u(0x00000008)
+#define SSI_ISR_RXOIS_MSB _u(3)
+#define SSI_ISR_RXOIS_LSB _u(3)
+#define SSI_ISR_RXOIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_ISR_RXUIS
+// Description : Receive FIFO underflow interrupt status
+#define SSI_ISR_RXUIS_RESET _u(0x0)
+#define SSI_ISR_RXUIS_BITS _u(0x00000004)
+#define SSI_ISR_RXUIS_MSB _u(2)
+#define SSI_ISR_RXUIS_LSB _u(2)
+#define SSI_ISR_RXUIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_ISR_TXOIS
+// Description : Transmit FIFO overflow interrupt status
+#define SSI_ISR_TXOIS_RESET _u(0x0)
+#define SSI_ISR_TXOIS_BITS _u(0x00000002)
+#define SSI_ISR_TXOIS_MSB _u(1)
+#define SSI_ISR_TXOIS_LSB _u(1)
+#define SSI_ISR_TXOIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_ISR_TXEIS
+// Description : Transmit FIFO empty interrupt status
+#define SSI_ISR_TXEIS_RESET _u(0x0)
+#define SSI_ISR_TXEIS_BITS _u(0x00000001)
+#define SSI_ISR_TXEIS_MSB _u(0)
+#define SSI_ISR_TXEIS_LSB _u(0)
+#define SSI_ISR_TXEIS_ACCESS "RO"
+// =============================================================================
+// Register : SSI_RISR
+// Description : Raw interrupt status
+#define SSI_RISR_OFFSET _u(0x00000034)
+#define SSI_RISR_BITS _u(0x0000003f)
+#define SSI_RISR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_RISR_MSTIR
+// Description : Multi-master contention raw interrupt status
+#define SSI_RISR_MSTIR_RESET _u(0x0)
+#define SSI_RISR_MSTIR_BITS _u(0x00000020)
+#define SSI_RISR_MSTIR_MSB _u(5)
+#define SSI_RISR_MSTIR_LSB _u(5)
+#define SSI_RISR_MSTIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_RISR_RXFIR
+// Description : Receive FIFO full raw interrupt status
+#define SSI_RISR_RXFIR_RESET _u(0x0)
+#define SSI_RISR_RXFIR_BITS _u(0x00000010)
+#define SSI_RISR_RXFIR_MSB _u(4)
+#define SSI_RISR_RXFIR_LSB _u(4)
+#define SSI_RISR_RXFIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_RISR_RXOIR
+// Description : Receive FIFO overflow raw interrupt status
+#define SSI_RISR_RXOIR_RESET _u(0x0)
+#define SSI_RISR_RXOIR_BITS _u(0x00000008)
+#define SSI_RISR_RXOIR_MSB _u(3)
+#define SSI_RISR_RXOIR_LSB _u(3)
+#define SSI_RISR_RXOIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_RISR_RXUIR
+// Description : Receive FIFO underflow raw interrupt status
+#define SSI_RISR_RXUIR_RESET _u(0x0)
+#define SSI_RISR_RXUIR_BITS _u(0x00000004)
+#define SSI_RISR_RXUIR_MSB _u(2)
+#define SSI_RISR_RXUIR_LSB _u(2)
+#define SSI_RISR_RXUIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_RISR_TXOIR
+// Description : Transmit FIFO overflow raw interrupt status
+#define SSI_RISR_TXOIR_RESET _u(0x0)
+#define SSI_RISR_TXOIR_BITS _u(0x00000002)
+#define SSI_RISR_TXOIR_MSB _u(1)
+#define SSI_RISR_TXOIR_LSB _u(1)
+#define SSI_RISR_TXOIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SSI_RISR_TXEIR
+// Description : Transmit FIFO empty raw interrupt status
+#define SSI_RISR_TXEIR_RESET _u(0x0)
+#define SSI_RISR_TXEIR_BITS _u(0x00000001)
+#define SSI_RISR_TXEIR_MSB _u(0)
+#define SSI_RISR_TXEIR_LSB _u(0)
+#define SSI_RISR_TXEIR_ACCESS "RO"
+// =============================================================================
+// Register : SSI_TXOICR
+// Description : TX FIFO overflow interrupt clear
+// Clear-on-read transmit FIFO overflow interrupt
+#define SSI_TXOICR_OFFSET _u(0x00000038)
+#define SSI_TXOICR_BITS _u(0x00000001)
+#define SSI_TXOICR_RESET _u(0x00000000)
+#define SSI_TXOICR_MSB _u(0)
+#define SSI_TXOICR_LSB _u(0)
+#define SSI_TXOICR_ACCESS "RO"
+// =============================================================================
+// Register : SSI_RXOICR
+// Description : RX FIFO overflow interrupt clear
+// Clear-on-read receive FIFO overflow interrupt
+#define SSI_RXOICR_OFFSET _u(0x0000003c)
+#define SSI_RXOICR_BITS _u(0x00000001)
+#define SSI_RXOICR_RESET _u(0x00000000)
+#define SSI_RXOICR_MSB _u(0)
+#define SSI_RXOICR_LSB _u(0)
+#define SSI_RXOICR_ACCESS "RO"
+// =============================================================================
+// Register : SSI_RXUICR
+// Description : RX FIFO underflow interrupt clear
+// Clear-on-read receive FIFO underflow interrupt
+#define SSI_RXUICR_OFFSET _u(0x00000040)
+#define SSI_RXUICR_BITS _u(0x00000001)
+#define SSI_RXUICR_RESET _u(0x00000000)
+#define SSI_RXUICR_MSB _u(0)
+#define SSI_RXUICR_LSB _u(0)
+#define SSI_RXUICR_ACCESS "RO"
+// =============================================================================
+// Register : SSI_MSTICR
+// Description : Multi-master interrupt clear
+// Clear-on-read multi-master contention interrupt
+#define SSI_MSTICR_OFFSET _u(0x00000044)
+#define SSI_MSTICR_BITS _u(0x00000001)
+#define SSI_MSTICR_RESET _u(0x00000000)
+#define SSI_MSTICR_MSB _u(0)
+#define SSI_MSTICR_LSB _u(0)
+#define SSI_MSTICR_ACCESS "RO"
+// =============================================================================
+// Register : SSI_ICR
+// Description : Interrupt clear
+// Clear-on-read all active interrupts
+#define SSI_ICR_OFFSET _u(0x00000048)
+#define SSI_ICR_BITS _u(0x00000001)
+#define SSI_ICR_RESET _u(0x00000000)
+#define SSI_ICR_MSB _u(0)
+#define SSI_ICR_LSB _u(0)
+#define SSI_ICR_ACCESS "RO"
+// =============================================================================
+// Register : SSI_DMACR
+// Description : DMA control
+#define SSI_DMACR_OFFSET _u(0x0000004c)
+#define SSI_DMACR_BITS _u(0x00000003)
+#define SSI_DMACR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_DMACR_TDMAE
+// Description : Transmit DMA enable
+#define SSI_DMACR_TDMAE_RESET _u(0x0)
+#define SSI_DMACR_TDMAE_BITS _u(0x00000002)
+#define SSI_DMACR_TDMAE_MSB _u(1)
+#define SSI_DMACR_TDMAE_LSB _u(1)
+#define SSI_DMACR_TDMAE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_DMACR_RDMAE
+// Description : Receive DMA enable
+#define SSI_DMACR_RDMAE_RESET _u(0x0)
+#define SSI_DMACR_RDMAE_BITS _u(0x00000001)
+#define SSI_DMACR_RDMAE_MSB _u(0)
+#define SSI_DMACR_RDMAE_LSB _u(0)
+#define SSI_DMACR_RDMAE_ACCESS "RW"
+// =============================================================================
+// Register : SSI_DMATDLR
+// Description : DMA TX data level
+#define SSI_DMATDLR_OFFSET _u(0x00000050)
+#define SSI_DMATDLR_BITS _u(0x000000ff)
+#define SSI_DMATDLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_DMATDLR_DMATDL
+// Description : Transmit data watermark level
+#define SSI_DMATDLR_DMATDL_RESET _u(0x00)
+#define SSI_DMATDLR_DMATDL_BITS _u(0x000000ff)
+#define SSI_DMATDLR_DMATDL_MSB _u(7)
+#define SSI_DMATDLR_DMATDL_LSB _u(0)
+#define SSI_DMATDLR_DMATDL_ACCESS "RW"
+// =============================================================================
+// Register : SSI_DMARDLR
+// Description : DMA RX data level
+#define SSI_DMARDLR_OFFSET _u(0x00000054)
+#define SSI_DMARDLR_BITS _u(0x000000ff)
+#define SSI_DMARDLR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_DMARDLR_DMARDL
+// Description : Receive data watermark level (DMARDLR+1)
+#define SSI_DMARDLR_DMARDL_RESET _u(0x00)
+#define SSI_DMARDLR_DMARDL_BITS _u(0x000000ff)
+#define SSI_DMARDLR_DMARDL_MSB _u(7)
+#define SSI_DMARDLR_DMARDL_LSB _u(0)
+#define SSI_DMARDLR_DMARDL_ACCESS "RW"
+// =============================================================================
+// Register : SSI_IDR
+// Description : Identification register
+#define SSI_IDR_OFFSET _u(0x00000058)
+#define SSI_IDR_BITS _u(0xffffffff)
+#define SSI_IDR_RESET _u(0x51535049)
+// -----------------------------------------------------------------------------
+// Field : SSI_IDR_IDCODE
+// Description : Peripheral dentification code
+#define SSI_IDR_IDCODE_RESET _u(0x51535049)
+#define SSI_IDR_IDCODE_BITS _u(0xffffffff)
+#define SSI_IDR_IDCODE_MSB _u(31)
+#define SSI_IDR_IDCODE_LSB _u(0)
+#define SSI_IDR_IDCODE_ACCESS "RO"
+// =============================================================================
+// Register : SSI_SSI_VERSION_ID
+// Description : Version ID
+#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c)
+#define SSI_SSI_VERSION_ID_BITS _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_RESET _u(0x3430312a)
+// -----------------------------------------------------------------------------
+// Field : SSI_SSI_VERSION_ID_SSI_COMP_VERSION
+// Description : SNPS component version (format X.YY)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET _u(0x3430312a)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB _u(31)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB _u(0)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO"
+// =============================================================================
+// Register : SSI_DR0
+// Description : Data Register 0 (of 36)
+#define SSI_DR0_OFFSET _u(0x00000060)
+#define SSI_DR0_BITS _u(0xffffffff)
+#define SSI_DR0_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_DR0_DR
+// Description : First data register of 36
+#define SSI_DR0_DR_RESET _u(0x00000000)
+#define SSI_DR0_DR_BITS _u(0xffffffff)
+#define SSI_DR0_DR_MSB _u(31)
+#define SSI_DR0_DR_LSB _u(0)
+#define SSI_DR0_DR_ACCESS "RW"
+// =============================================================================
+// Register : SSI_RX_SAMPLE_DLY
+// Description : RX sample delay
+#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0)
+#define SSI_RX_SAMPLE_DLY_BITS _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_RX_SAMPLE_DLY_RSD
+// Description : RXD sample delay (in SCLK cycles)
+#define SSI_RX_SAMPLE_DLY_RSD_RESET _u(0x00)
+#define SSI_RX_SAMPLE_DLY_RSD_BITS _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RSD_MSB _u(7)
+#define SSI_RX_SAMPLE_DLY_RSD_LSB _u(0)
+#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW"
+// =============================================================================
+// Register : SSI_SPI_CTRLR0
+// Description : SPI control
+#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4)
+#define SSI_SPI_CTRLR0_BITS _u(0xff07fb3f)
+#define SSI_SPI_CTRLR0_RESET _u(0x03000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_XIP_CMD
+// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append
+// to Address (INST_L = 0-bit)
+#define SSI_SPI_CTRLR0_XIP_CMD_RESET _u(0x03)
+#define SSI_SPI_CTRLR0_XIP_CMD_BITS _u(0xff000000)
+#define SSI_SPI_CTRLR0_XIP_CMD_MSB _u(31)
+#define SSI_SPI_CTRLR0_XIP_CMD_LSB _u(24)
+#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_SPI_RXDS_EN
+// Description : Read data strobe enable
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS _u(0x00040000)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB _u(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB _u(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_INST_DDR_EN
+// Description : Instruction DDR transfer enable
+#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS _u(0x00020000)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB _u(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB _u(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_SPI_DDR_EN
+// Description : SPI DDR transfer enable
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS _u(0x00010000)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB _u(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB _u(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_WAIT_CYCLES
+// Description : Wait cycles between control frame transmit and data reception
+// (in SCLK cycles)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET _u(0x00)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS _u(0x0000f800)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB _u(15)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB _u(11)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_INST_L
+// Description : Instruction length (0/4/8/16b)
+// 0x0 -> No instruction
+// 0x1 -> 4-bit instruction
+// 0x2 -> 8-bit instruction
+// 0x3 -> 16-bit instruction
+#define SSI_SPI_CTRLR0_INST_L_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_BITS _u(0x00000300)
+#define SSI_SPI_CTRLR0_INST_L_MSB _u(9)
+#define SSI_SPI_CTRLR0_INST_L_LSB _u(8)
+#define SSI_SPI_CTRLR0_INST_L_ACCESS "RW"
+#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_4B _u(0x1)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_8B _u(0x2)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_16B _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_ADDR_L
+// Description : Address length (0b-60b in 4b increments)
+#define SSI_SPI_CTRLR0_ADDR_L_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_ADDR_L_BITS _u(0x0000003c)
+#define SSI_SPI_CTRLR0_ADDR_L_MSB _u(5)
+#define SSI_SPI_CTRLR0_ADDR_L_LSB _u(2)
+#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SSI_SPI_CTRLR0_TRANS_TYPE
+// Description : Address and instruction transfer format
+// 0x0 -> Command and address both in standard SPI frame format
+// 0x1 -> Command in standard SPI format, address in format
+// specified by FRF
+// 0x2 -> Command and address both in format specified by FRF
+// (e.g. Dual-SPI)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS _u(0x00000003)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB _u(1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB _u(0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS "RW"
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2)
+// =============================================================================
+// Register : SSI_TXD_DRIVE_EDGE
+// Description : TX drive edge
+#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8)
+#define SSI_TXD_DRIVE_EDGE_BITS _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SSI_TXD_DRIVE_EDGE_TDE
+// Description : TXD drive edge
+#define SSI_TXD_DRIVE_EDGE_TDE_RESET _u(0x00)
+#define SSI_TXD_DRIVE_EDGE_TDE_BITS _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_TDE_MSB _u(7)
+#define SSI_TXD_DRIVE_EDGE_TDE_LSB _u(0)
+#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_SSI_DEFINED
diff --git a/arkanoid/pico/hardware/regs/syscfg.h b/arkanoid/pico/hardware/regs/syscfg.h
new file mode 100644
index 0000000..2bf09e2
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/syscfg.h
@@ -0,0 +1,257 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SYSCFG
+// Version : 1
+// Bus type : apb
+// Description : Register block for various chip control signals
+// =============================================================================
+#ifndef HARDWARE_REGS_SYSCFG_DEFINED
+#define HARDWARE_REGS_SYSCFG_DEFINED
+// =============================================================================
+// Register : SYSCFG_PROC0_NMI_MASK
+// Description : Processor core 0 NMI source mask
+// Set a bit high to enable NMI from that IRQ
+#define SYSCFG_PROC0_NMI_MASK_OFFSET _u(0x00000000)
+#define SYSCFG_PROC0_NMI_MASK_BITS _u(0xffffffff)
+#define SYSCFG_PROC0_NMI_MASK_RESET _u(0x00000000)
+#define SYSCFG_PROC0_NMI_MASK_MSB _u(31)
+#define SYSCFG_PROC0_NMI_MASK_LSB _u(0)
+#define SYSCFG_PROC0_NMI_MASK_ACCESS "RW"
+// =============================================================================
+// Register : SYSCFG_PROC1_NMI_MASK
+// Description : Processor core 1 NMI source mask
+// Set a bit high to enable NMI from that IRQ
+#define SYSCFG_PROC1_NMI_MASK_OFFSET _u(0x00000004)
+#define SYSCFG_PROC1_NMI_MASK_BITS _u(0xffffffff)
+#define SYSCFG_PROC1_NMI_MASK_RESET _u(0x00000000)
+#define SYSCFG_PROC1_NMI_MASK_MSB _u(31)
+#define SYSCFG_PROC1_NMI_MASK_LSB _u(0)
+#define SYSCFG_PROC1_NMI_MASK_ACCESS "RW"
+// =============================================================================
+// Register : SYSCFG_PROC_CONFIG
+// Description : Configuration for processors
+#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000008)
+#define SYSCFG_PROC_CONFIG_BITS _u(0xff000003)
+#define SYSCFG_PROC_CONFIG_RESET _u(0x10000000)
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID
+// Description : Configure proc1 DAP instance ID.
+// Recommend that this is NOT changed until you require debug
+// access in multi-chip environment
+// WARNING: do not set to 15 as this is reserved for RescueDP
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_RESET _u(0x1)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_BITS _u(0xf0000000)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_MSB _u(31)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_LSB _u(28)
+#define SYSCFG_PROC_CONFIG_PROC1_DAP_INSTID_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID
+// Description : Configure proc0 DAP instance ID.
+// Recommend that this is NOT changed until you require debug
+// access in multi-chip environment
+// WARNING: do not set to 15 as this is reserved for RescueDP
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_RESET _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_BITS _u(0x0f000000)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_MSB _u(27)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_LSB _u(24)
+#define SYSCFG_PROC_CONFIG_PROC0_DAP_INSTID_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
+// Description : Indication that proc1 has halted
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
+#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
+// Description : Indication that proc0 has halted
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
+#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
+// =============================================================================
+// Register : SYSCFG_PROC_IN_SYNC_BYPASS
+// Description : For each bit, if 1, bypass the input synchronizer between that
+// GPIO
+// and the GPIO input register in the SIO. The input synchronizers
+// should
+// generally be unbypassed, to avoid injecting metastabilities
+// into processors.
+// If you're feeling brave, you can bypass to save two cycles of
+// input
+// latency. This register applies to GPIO 0...29.
+#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x0000000c)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0x3fffffff)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_MSB _u(29)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_LSB _u(0)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_ACCESS "RW"
+// =============================================================================
+// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
+// Description : For each bit, if 1, bypass the input synchronizer between that
+// GPIO
+// and the GPIO input register in the SIO. The input synchronizers
+// should
+// generally be unbypassed, to avoid injecting metastabilities
+// into processors.
+// If you're feeling brave, you can bypass to save two cycles of
+// input
+// latency. This register applies to GPIO 30...35 (the QSPI IOs).
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000010)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0x0000003f)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_MSB _u(5)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_LSB _u(0)
+#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_ACCESS "RW"
+// =============================================================================
+// Register : SYSCFG_DBGFORCE
+// Description : Directly control the SWD debug port of either processor
+#define SYSCFG_DBGFORCE_OFFSET _u(0x00000014)
+#define SYSCFG_DBGFORCE_BITS _u(0x000000ff)
+#define SYSCFG_DBGFORCE_RESET _u(0x00000066)
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC1_ATTACH
+// Description : Attach processor 1 debug port to syscfg controls, and
+// disconnect it from external SWD pads.
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_RESET _u(0x0)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_BITS _u(0x00000080)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_MSB _u(7)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_LSB _u(7)
+#define SYSCFG_DBGFORCE_PROC1_ATTACH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC1_SWCLK
+// Description : Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_BITS _u(0x00000040)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_MSB _u(6)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_LSB _u(6)
+#define SYSCFG_DBGFORCE_PROC1_SWCLK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC1_SWDI
+// Description : Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC1_SWDI_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_BITS _u(0x00000020)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_MSB _u(5)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_LSB _u(5)
+#define SYSCFG_DBGFORCE_PROC1_SWDI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC1_SWDO
+// Description : Observe the value of processor 1 SWDIO output.
+#define SYSCFG_DBGFORCE_PROC1_SWDO_RESET "-"
+#define SYSCFG_DBGFORCE_PROC1_SWDO_BITS _u(0x00000010)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_MSB _u(4)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_LSB _u(4)
+#define SYSCFG_DBGFORCE_PROC1_SWDO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC0_ATTACH
+// Description : Attach processor 0 debug port to syscfg controls, and
+// disconnect it from external SWD pads.
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_RESET _u(0x0)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_BITS _u(0x00000008)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_MSB _u(3)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_LSB _u(3)
+#define SYSCFG_DBGFORCE_PROC0_ATTACH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC0_SWCLK
+// Description : Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_BITS _u(0x00000004)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_MSB _u(2)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_LSB _u(2)
+#define SYSCFG_DBGFORCE_PROC0_SWCLK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC0_SWDI
+// Description : Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
+#define SYSCFG_DBGFORCE_PROC0_SWDI_RESET _u(0x1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_BITS _u(0x00000002)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_MSB _u(1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_LSB _u(1)
+#define SYSCFG_DBGFORCE_PROC0_SWDI_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_DBGFORCE_PROC0_SWDO
+// Description : Observe the value of processor 0 SWDIO output.
+#define SYSCFG_DBGFORCE_PROC0_SWDO_RESET "-"
+#define SYSCFG_DBGFORCE_PROC0_SWDO_BITS _u(0x00000001)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_MSB _u(0)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_LSB _u(0)
+#define SYSCFG_DBGFORCE_PROC0_SWDO_ACCESS "RO"
+// =============================================================================
+// Register : SYSCFG_MEMPOWERDOWN
+// Description : Control power downs to memories. Set high to power down
+// memories.
+// Use with extreme caution
+#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000018)
+#define SYSCFG_MEMPOWERDOWN_BITS _u(0x000000ff)
+#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_ROM
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000080)
+#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(7)
+#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(7)
+#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_USB
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000040)
+#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(6)
+#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(6)
+#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_SRAM5
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
+#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_SRAM4
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
+#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_SRAM3
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
+#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_SRAM2
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
+#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_SRAM1
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
+#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : SYSCFG_MEMPOWERDOWN_SRAM0
+// Description : None
+#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
+#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_SYSCFG_DEFINED
diff --git a/arkanoid/pico/hardware/regs/sysinfo.h b/arkanoid/pico/hardware/regs/sysinfo.h
new file mode 100644
index 0000000..2a46658
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/sysinfo.h
@@ -0,0 +1,77 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SYSINFO
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_SYSINFO_DEFINED
+#define HARDWARE_REGS_SYSINFO_DEFINED
+// =============================================================================
+// Register : SYSINFO_CHIP_ID
+// Description : JEDEC JEP-106 compliant chip identifier.
+#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
+#define SYSINFO_CHIP_ID_BITS _u(0xffffffff)
+#define SYSINFO_CHIP_ID_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SYSINFO_CHIP_ID_REVISION
+// Description : None
+#define SYSINFO_CHIP_ID_REVISION_RESET "-"
+#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
+#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
+#define SYSINFO_CHIP_ID_REVISION_LSB _u(28)
+#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SYSINFO_CHIP_ID_PART
+// Description : None
+#define SYSINFO_CHIP_ID_PART_RESET "-"
+#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
+#define SYSINFO_CHIP_ID_PART_MSB _u(27)
+#define SYSINFO_CHIP_ID_PART_LSB _u(12)
+#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SYSINFO_CHIP_ID_MANUFACTURER
+// Description : None
+#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
+#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000fff)
+#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
+#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(0)
+#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
+// =============================================================================
+// Register : SYSINFO_PLATFORM
+// Description : Platform register. Allows software to know what environment it
+// is running in.
+#define SYSINFO_PLATFORM_OFFSET _u(0x00000004)
+#define SYSINFO_PLATFORM_BITS _u(0x00000003)
+#define SYSINFO_PLATFORM_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : SYSINFO_PLATFORM_ASIC
+// Description : None
+#define SYSINFO_PLATFORM_ASIC_RESET _u(0x0)
+#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
+#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
+#define SYSINFO_PLATFORM_ASIC_LSB _u(1)
+#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : SYSINFO_PLATFORM_FPGA
+// Description : None
+#define SYSINFO_PLATFORM_FPGA_RESET _u(0x0)
+#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
+#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
+#define SYSINFO_PLATFORM_FPGA_LSB _u(0)
+#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
+// =============================================================================
+// Register : SYSINFO_GITREF_RP2040
+// Description : Git hash of the chip source. Used to identify chip version.
+#define SYSINFO_GITREF_RP2040_OFFSET _u(0x00000040)
+#define SYSINFO_GITREF_RP2040_BITS _u(0xffffffff)
+#define SYSINFO_GITREF_RP2040_RESET "-"
+#define SYSINFO_GITREF_RP2040_MSB _u(31)
+#define SYSINFO_GITREF_RP2040_LSB _u(0)
+#define SYSINFO_GITREF_RP2040_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_SYSINFO_DEFINED
diff --git a/arkanoid/pico/hardware/regs/tbman.h b/arkanoid/pico/hardware/regs/tbman.h
new file mode 100644
index 0000000..4f8f641
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/tbman.h
@@ -0,0 +1,38 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : TBMAN
+// Version : 1
+// Bus type : apb
+// Description : Testbench manager. Allows the programmer to know what
+// platform their software is running on.
+// =============================================================================
+#ifndef HARDWARE_REGS_TBMAN_DEFINED
+#define HARDWARE_REGS_TBMAN_DEFINED
+// =============================================================================
+// Register : TBMAN_PLATFORM
+// Description : Indicates the type of platform in use
+#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
+#define TBMAN_PLATFORM_BITS _u(0x00000003)
+#define TBMAN_PLATFORM_RESET _u(0x00000005)
+// -----------------------------------------------------------------------------
+// Field : TBMAN_PLATFORM_FPGA
+// Description : Indicates the platform is an FPGA
+#define TBMAN_PLATFORM_FPGA_RESET _u(0x0)
+#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002)
+#define TBMAN_PLATFORM_FPGA_MSB _u(1)
+#define TBMAN_PLATFORM_FPGA_LSB _u(1)
+#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : TBMAN_PLATFORM_ASIC
+// Description : Indicates the platform is an ASIC
+#define TBMAN_PLATFORM_ASIC_RESET _u(0x1)
+#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001)
+#define TBMAN_PLATFORM_ASIC_MSB _u(0)
+#define TBMAN_PLATFORM_ASIC_LSB _u(0)
+#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_TBMAN_DEFINED
diff --git a/arkanoid/pico/hardware/regs/timer.h b/arkanoid/pico/hardware/regs/timer.h
new file mode 100644
index 0000000..c3ef0c5
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/timer.h
@@ -0,0 +1,332 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : TIMER
+// Version : 1
+// Bus type : apb
+// Description : Controls time and alarms
+// time is a 64 bit value indicating the time in usec since
+// power-on
+// timeh is the top 32 bits of time & timel is the bottom 32
+// bits
+// to change time write to timelw before timehw
+// to read time read from timelr before timehr
+// An alarm is set by setting alarm_enable and writing to the
+// corresponding alarm register
+// When an alarm is pending, the corresponding alarm_running
+// signal will be high
+// An alarm can be cancelled before it has finished by clearing
+// the alarm_enable
+// When an alarm fires, the corresponding alarm_irq is set and
+// alarm_running is cleared
+// To clear the interrupt write a 1 to the corresponding
+// alarm_irq
+// =============================================================================
+#ifndef HARDWARE_REGS_TIMER_DEFINED
+#define HARDWARE_REGS_TIMER_DEFINED
+// =============================================================================
+// Register : TIMER_TIMEHW
+// Description : Write to bits 63:32 of time
+// always write timelw before timehw
+#define TIMER_TIMEHW_OFFSET _u(0x00000000)
+#define TIMER_TIMEHW_BITS _u(0xffffffff)
+#define TIMER_TIMEHW_RESET _u(0x00000000)
+#define TIMER_TIMEHW_MSB _u(31)
+#define TIMER_TIMEHW_LSB _u(0)
+#define TIMER_TIMEHW_ACCESS "WF"
+// =============================================================================
+// Register : TIMER_TIMELW
+// Description : Write to bits 31:0 of time
+// writes do not get copied to time until timehw is written
+#define TIMER_TIMELW_OFFSET _u(0x00000004)
+#define TIMER_TIMELW_BITS _u(0xffffffff)
+#define TIMER_TIMELW_RESET _u(0x00000000)
+#define TIMER_TIMELW_MSB _u(31)
+#define TIMER_TIMELW_LSB _u(0)
+#define TIMER_TIMELW_ACCESS "WF"
+// =============================================================================
+// Register : TIMER_TIMEHR
+// Description : Read from bits 63:32 of time
+// always read timelr before timehr
+#define TIMER_TIMEHR_OFFSET _u(0x00000008)
+#define TIMER_TIMEHR_BITS _u(0xffffffff)
+#define TIMER_TIMEHR_RESET _u(0x00000000)
+#define TIMER_TIMEHR_MSB _u(31)
+#define TIMER_TIMEHR_LSB _u(0)
+#define TIMER_TIMEHR_ACCESS "RO"
+// =============================================================================
+// Register : TIMER_TIMELR
+// Description : Read from bits 31:0 of time
+#define TIMER_TIMELR_OFFSET _u(0x0000000c)
+#define TIMER_TIMELR_BITS _u(0xffffffff)
+#define TIMER_TIMELR_RESET _u(0x00000000)
+#define TIMER_TIMELR_MSB _u(31)
+#define TIMER_TIMELR_LSB _u(0)
+#define TIMER_TIMELR_ACCESS "RO"
+// =============================================================================
+// Register : TIMER_ALARM0
+// Description : Arm alarm 0, and configure the time it will fire.
+// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
+// The alarm will disarm itself once it fires, and can
+// be disarmed early using the ARMED status register.
+#define TIMER_ALARM0_OFFSET _u(0x00000010)
+#define TIMER_ALARM0_BITS _u(0xffffffff)
+#define TIMER_ALARM0_RESET _u(0x00000000)
+#define TIMER_ALARM0_MSB _u(31)
+#define TIMER_ALARM0_LSB _u(0)
+#define TIMER_ALARM0_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_ALARM1
+// Description : Arm alarm 1, and configure the time it will fire.
+// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
+// The alarm will disarm itself once it fires, and can
+// be disarmed early using the ARMED status register.
+#define TIMER_ALARM1_OFFSET _u(0x00000014)
+#define TIMER_ALARM1_BITS _u(0xffffffff)
+#define TIMER_ALARM1_RESET _u(0x00000000)
+#define TIMER_ALARM1_MSB _u(31)
+#define TIMER_ALARM1_LSB _u(0)
+#define TIMER_ALARM1_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_ALARM2
+// Description : Arm alarm 2, and configure the time it will fire.
+// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
+// The alarm will disarm itself once it fires, and can
+// be disarmed early using the ARMED status register.
+#define TIMER_ALARM2_OFFSET _u(0x00000018)
+#define TIMER_ALARM2_BITS _u(0xffffffff)
+#define TIMER_ALARM2_RESET _u(0x00000000)
+#define TIMER_ALARM2_MSB _u(31)
+#define TIMER_ALARM2_LSB _u(0)
+#define TIMER_ALARM2_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_ALARM3
+// Description : Arm alarm 3, and configure the time it will fire.
+// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
+// The alarm will disarm itself once it fires, and can
+// be disarmed early using the ARMED status register.
+#define TIMER_ALARM3_OFFSET _u(0x0000001c)
+#define TIMER_ALARM3_BITS _u(0xffffffff)
+#define TIMER_ALARM3_RESET _u(0x00000000)
+#define TIMER_ALARM3_MSB _u(31)
+#define TIMER_ALARM3_LSB _u(0)
+#define TIMER_ALARM3_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_ARMED
+// Description : Indicates the armed/disarmed status of each alarm.
+// A write to the corresponding ALARMx register arms the alarm.
+// Alarms automatically disarm upon firing, but writing ones here
+// will disarm immediately without waiting to fire.
+#define TIMER_ARMED_OFFSET _u(0x00000020)
+#define TIMER_ARMED_BITS _u(0x0000000f)
+#define TIMER_ARMED_RESET _u(0x00000000)
+#define TIMER_ARMED_MSB _u(3)
+#define TIMER_ARMED_LSB _u(0)
+#define TIMER_ARMED_ACCESS "WC"
+// =============================================================================
+// Register : TIMER_TIMERAWH
+// Description : Raw read from bits 63:32 of time (no side effects)
+#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
+#define TIMER_TIMERAWH_BITS _u(0xffffffff)
+#define TIMER_TIMERAWH_RESET _u(0x00000000)
+#define TIMER_TIMERAWH_MSB _u(31)
+#define TIMER_TIMERAWH_LSB _u(0)
+#define TIMER_TIMERAWH_ACCESS "RO"
+// =============================================================================
+// Register : TIMER_TIMERAWL
+// Description : Raw read from bits 31:0 of time (no side effects)
+#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
+#define TIMER_TIMERAWL_BITS _u(0xffffffff)
+#define TIMER_TIMERAWL_RESET _u(0x00000000)
+#define TIMER_TIMERAWL_MSB _u(31)
+#define TIMER_TIMERAWL_LSB _u(0)
+#define TIMER_TIMERAWL_ACCESS "RO"
+// =============================================================================
+// Register : TIMER_DBGPAUSE
+// Description : Set bits high to enable pause when the corresponding debug
+// ports are active
+#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
+#define TIMER_DBGPAUSE_BITS _u(0x00000006)
+#define TIMER_DBGPAUSE_RESET _u(0x00000007)
+// -----------------------------------------------------------------------------
+// Field : TIMER_DBGPAUSE_DBG1
+// Description : Pause when processor 1 is in debug mode
+#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
+#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
+#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
+#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
+#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : TIMER_DBGPAUSE_DBG0
+// Description : Pause when processor 0 is in debug mode
+#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
+#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
+#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
+#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
+#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_PAUSE
+// Description : Set high to pause the timer
+#define TIMER_PAUSE_OFFSET _u(0x00000030)
+#define TIMER_PAUSE_BITS _u(0x00000001)
+#define TIMER_PAUSE_RESET _u(0x00000000)
+#define TIMER_PAUSE_MSB _u(0)
+#define TIMER_PAUSE_LSB _u(0)
+#define TIMER_PAUSE_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_INTR
+// Description : Raw Interrupts
+#define TIMER_INTR_OFFSET _u(0x00000034)
+#define TIMER_INTR_BITS _u(0x0000000f)
+#define TIMER_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTR_ALARM_3
+// Description : None
+#define TIMER_INTR_ALARM_3_RESET _u(0x0)
+#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTR_ALARM_3_MSB _u(3)
+#define TIMER_INTR_ALARM_3_LSB _u(3)
+#define TIMER_INTR_ALARM_3_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTR_ALARM_2
+// Description : None
+#define TIMER_INTR_ALARM_2_RESET _u(0x0)
+#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTR_ALARM_2_MSB _u(2)
+#define TIMER_INTR_ALARM_2_LSB _u(2)
+#define TIMER_INTR_ALARM_2_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTR_ALARM_1
+// Description : None
+#define TIMER_INTR_ALARM_1_RESET _u(0x0)
+#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTR_ALARM_1_MSB _u(1)
+#define TIMER_INTR_ALARM_1_LSB _u(1)
+#define TIMER_INTR_ALARM_1_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTR_ALARM_0
+// Description : None
+#define TIMER_INTR_ALARM_0_RESET _u(0x0)
+#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTR_ALARM_0_MSB _u(0)
+#define TIMER_INTR_ALARM_0_LSB _u(0)
+#define TIMER_INTR_ALARM_0_ACCESS "WC"
+// =============================================================================
+// Register : TIMER_INTE
+// Description : Interrupt Enable
+#define TIMER_INTE_OFFSET _u(0x00000038)
+#define TIMER_INTE_BITS _u(0x0000000f)
+#define TIMER_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTE_ALARM_3
+// Description : None
+#define TIMER_INTE_ALARM_3_RESET _u(0x0)
+#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTE_ALARM_3_MSB _u(3)
+#define TIMER_INTE_ALARM_3_LSB _u(3)
+#define TIMER_INTE_ALARM_3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTE_ALARM_2
+// Description : None
+#define TIMER_INTE_ALARM_2_RESET _u(0x0)
+#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTE_ALARM_2_MSB _u(2)
+#define TIMER_INTE_ALARM_2_LSB _u(2)
+#define TIMER_INTE_ALARM_2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTE_ALARM_1
+// Description : None
+#define TIMER_INTE_ALARM_1_RESET _u(0x0)
+#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTE_ALARM_1_MSB _u(1)
+#define TIMER_INTE_ALARM_1_LSB _u(1)
+#define TIMER_INTE_ALARM_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTE_ALARM_0
+// Description : None
+#define TIMER_INTE_ALARM_0_RESET _u(0x0)
+#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTE_ALARM_0_MSB _u(0)
+#define TIMER_INTE_ALARM_0_LSB _u(0)
+#define TIMER_INTE_ALARM_0_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_INTF
+// Description : Interrupt Force
+#define TIMER_INTF_OFFSET _u(0x0000003c)
+#define TIMER_INTF_BITS _u(0x0000000f)
+#define TIMER_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTF_ALARM_3
+// Description : None
+#define TIMER_INTF_ALARM_3_RESET _u(0x0)
+#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTF_ALARM_3_MSB _u(3)
+#define TIMER_INTF_ALARM_3_LSB _u(3)
+#define TIMER_INTF_ALARM_3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTF_ALARM_2
+// Description : None
+#define TIMER_INTF_ALARM_2_RESET _u(0x0)
+#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTF_ALARM_2_MSB _u(2)
+#define TIMER_INTF_ALARM_2_LSB _u(2)
+#define TIMER_INTF_ALARM_2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTF_ALARM_1
+// Description : None
+#define TIMER_INTF_ALARM_1_RESET _u(0x0)
+#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTF_ALARM_1_MSB _u(1)
+#define TIMER_INTF_ALARM_1_LSB _u(1)
+#define TIMER_INTF_ALARM_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTF_ALARM_0
+// Description : None
+#define TIMER_INTF_ALARM_0_RESET _u(0x0)
+#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTF_ALARM_0_MSB _u(0)
+#define TIMER_INTF_ALARM_0_LSB _u(0)
+#define TIMER_INTF_ALARM_0_ACCESS "RW"
+// =============================================================================
+// Register : TIMER_INTS
+// Description : Interrupt status after masking & forcing
+#define TIMER_INTS_OFFSET _u(0x00000040)
+#define TIMER_INTS_BITS _u(0x0000000f)
+#define TIMER_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTS_ALARM_3
+// Description : None
+#define TIMER_INTS_ALARM_3_RESET _u(0x0)
+#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
+#define TIMER_INTS_ALARM_3_MSB _u(3)
+#define TIMER_INTS_ALARM_3_LSB _u(3)
+#define TIMER_INTS_ALARM_3_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTS_ALARM_2
+// Description : None
+#define TIMER_INTS_ALARM_2_RESET _u(0x0)
+#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
+#define TIMER_INTS_ALARM_2_MSB _u(2)
+#define TIMER_INTS_ALARM_2_LSB _u(2)
+#define TIMER_INTS_ALARM_2_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTS_ALARM_1
+// Description : None
+#define TIMER_INTS_ALARM_1_RESET _u(0x0)
+#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
+#define TIMER_INTS_ALARM_1_MSB _u(1)
+#define TIMER_INTS_ALARM_1_LSB _u(1)
+#define TIMER_INTS_ALARM_1_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : TIMER_INTS_ALARM_0
+// Description : None
+#define TIMER_INTS_ALARM_0_RESET _u(0x0)
+#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
+#define TIMER_INTS_ALARM_0_MSB _u(0)
+#define TIMER_INTS_ALARM_0_LSB _u(0)
+#define TIMER_INTS_ALARM_0_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_TIMER_DEFINED
diff --git a/arkanoid/pico/hardware/regs/uart.h b/arkanoid/pico/hardware/regs/uart.h
new file mode 100644
index 0000000..409f598
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/uart.h
@@ -0,0 +1,1148 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : UART
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_UART_DEFINED
+#define HARDWARE_REGS_UART_DEFINED
+// =============================================================================
+// Register : UART_UARTDR
+// Description : Data Register, UARTDR
+#define UART_UARTDR_OFFSET _u(0x00000000)
+#define UART_UARTDR_BITS _u(0x00000fff)
+#define UART_UARTDR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDR_OE
+// Description : Overrun error. This bit is set to 1 if data is received and the
+// receive FIFO is already full. This is cleared to 0 once there
+// is an empty space in the FIFO and a new character can be
+// written to it.
+#define UART_UARTDR_OE_RESET "-"
+#define UART_UARTDR_OE_BITS _u(0x00000800)
+#define UART_UARTDR_OE_MSB _u(11)
+#define UART_UARTDR_OE_LSB _u(11)
+#define UART_UARTDR_OE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDR_BE
+// Description : Break error. This bit is set to 1 if a break condition was
+// detected, indicating that the received data input was held LOW
+// for longer than a full-word transmission time (defined as
+// start, data, parity and stop bits). In FIFO mode, this error is
+// associated with the character at the top of the FIFO. When a
+// break occurs, only one 0 character is loaded into the FIFO. The
+// next character is only enabled after the receive data input
+// goes to a 1 (marking state), and the next valid start bit is
+// received.
+#define UART_UARTDR_BE_RESET "-"
+#define UART_UARTDR_BE_BITS _u(0x00000400)
+#define UART_UARTDR_BE_MSB _u(10)
+#define UART_UARTDR_BE_LSB _u(10)
+#define UART_UARTDR_BE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDR_PE
+// Description : Parity error. When set to 1, it indicates that the parity of
+// the received data character does not match the parity that the
+// EPS and SPS bits in the Line Control Register, UARTLCR_H. In
+// FIFO mode, this error is associated with the character at the
+// top of the FIFO.
+#define UART_UARTDR_PE_RESET "-"
+#define UART_UARTDR_PE_BITS _u(0x00000200)
+#define UART_UARTDR_PE_MSB _u(9)
+#define UART_UARTDR_PE_LSB _u(9)
+#define UART_UARTDR_PE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDR_FE
+// Description : Framing error. When set to 1, it indicates that the received
+// character did not have a valid stop bit (a valid stop bit is
+// 1). In FIFO mode, this error is associated with the character
+// at the top of the FIFO.
+#define UART_UARTDR_FE_RESET "-"
+#define UART_UARTDR_FE_BITS _u(0x00000100)
+#define UART_UARTDR_FE_MSB _u(8)
+#define UART_UARTDR_FE_LSB _u(8)
+#define UART_UARTDR_FE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDR_DATA
+// Description : Receive (read) data character. Transmit (write) data character.
+#define UART_UARTDR_DATA_RESET "-"
+#define UART_UARTDR_DATA_BITS _u(0x000000ff)
+#define UART_UARTDR_DATA_MSB _u(7)
+#define UART_UARTDR_DATA_LSB _u(0)
+#define UART_UARTDR_DATA_ACCESS "RWF"
+// =============================================================================
+// Register : UART_UARTRSR
+// Description : Receive Status Register/Error Clear Register, UARTRSR/UARTECR
+#define UART_UARTRSR_OFFSET _u(0x00000004)
+#define UART_UARTRSR_BITS _u(0x0000000f)
+#define UART_UARTRSR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRSR_OE
+// Description : Overrun error. This bit is set to 1 if data is received and the
+// FIFO is already full. This bit is cleared to 0 by a write to
+// UARTECR. The FIFO contents remain valid because no more data is
+// written when the FIFO is full, only the contents of the shift
+// register are overwritten. The CPU must now read the data, to
+// empty the FIFO.
+#define UART_UARTRSR_OE_RESET _u(0x0)
+#define UART_UARTRSR_OE_BITS _u(0x00000008)
+#define UART_UARTRSR_OE_MSB _u(3)
+#define UART_UARTRSR_OE_LSB _u(3)
+#define UART_UARTRSR_OE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRSR_BE
+// Description : Break error. This bit is set to 1 if a break condition was
+// detected, indicating that the received data input was held LOW
+// for longer than a full-word transmission time (defined as
+// start, data, parity, and stop bits). This bit is cleared to 0
+// after a write to UARTECR. In FIFO mode, this error is
+// associated with the character at the top of the FIFO. When a
+// break occurs, only one 0 character is loaded into the FIFO. The
+// next character is only enabled after the receive data input
+// goes to a 1 (marking state) and the next valid start bit is
+// received.
+#define UART_UARTRSR_BE_RESET _u(0x0)
+#define UART_UARTRSR_BE_BITS _u(0x00000004)
+#define UART_UARTRSR_BE_MSB _u(2)
+#define UART_UARTRSR_BE_LSB _u(2)
+#define UART_UARTRSR_BE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRSR_PE
+// Description : Parity error. When set to 1, it indicates that the parity of
+// the received data character does not match the parity that the
+// EPS and SPS bits in the Line Control Register, UARTLCR_H. This
+// bit is cleared to 0 by a write to UARTECR. In FIFO mode, this
+// error is associated with the character at the top of the FIFO.
+#define UART_UARTRSR_PE_RESET _u(0x0)
+#define UART_UARTRSR_PE_BITS _u(0x00000002)
+#define UART_UARTRSR_PE_MSB _u(1)
+#define UART_UARTRSR_PE_LSB _u(1)
+#define UART_UARTRSR_PE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRSR_FE
+// Description : Framing error. When set to 1, it indicates that the received
+// character did not have a valid stop bit (a valid stop bit is
+// 1). This bit is cleared to 0 by a write to UARTECR. In FIFO
+// mode, this error is associated with the character at the top of
+// the FIFO.
+#define UART_UARTRSR_FE_RESET _u(0x0)
+#define UART_UARTRSR_FE_BITS _u(0x00000001)
+#define UART_UARTRSR_FE_MSB _u(0)
+#define UART_UARTRSR_FE_LSB _u(0)
+#define UART_UARTRSR_FE_ACCESS "WC"
+// =============================================================================
+// Register : UART_UARTFR
+// Description : Flag Register, UARTFR
+#define UART_UARTFR_OFFSET _u(0x00000018)
+#define UART_UARTFR_BITS _u(0x000001ff)
+#define UART_UARTFR_RESET _u(0x00000090)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_RI
+// Description : Ring indicator. This bit is the complement of the UART ring
+// indicator, nUARTRI, modem status input. That is, the bit is 1
+// when nUARTRI is LOW.
+#define UART_UARTFR_RI_RESET "-"
+#define UART_UARTFR_RI_BITS _u(0x00000100)
+#define UART_UARTFR_RI_MSB _u(8)
+#define UART_UARTFR_RI_LSB _u(8)
+#define UART_UARTFR_RI_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_TXFE
+// Description : Transmit FIFO empty. The meaning of this bit depends on the
+// state of the FEN bit in the Line Control Register, UARTLCR_H.
+// If the FIFO is disabled, this bit is set when the transmit
+// holding register is empty. If the FIFO is enabled, the TXFE bit
+// is set when the transmit FIFO is empty. This bit does not
+// indicate if there is data in the transmit shift register.
+#define UART_UARTFR_TXFE_RESET _u(0x1)
+#define UART_UARTFR_TXFE_BITS _u(0x00000080)
+#define UART_UARTFR_TXFE_MSB _u(7)
+#define UART_UARTFR_TXFE_LSB _u(7)
+#define UART_UARTFR_TXFE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_RXFF
+// Description : Receive FIFO full. The meaning of this bit depends on the state
+// of the FEN bit in the UARTLCR_H Register. If the FIFO is
+// disabled, this bit is set when the receive holding register is
+// full. If the FIFO is enabled, the RXFF bit is set when the
+// receive FIFO is full.
+#define UART_UARTFR_RXFF_RESET _u(0x0)
+#define UART_UARTFR_RXFF_BITS _u(0x00000040)
+#define UART_UARTFR_RXFF_MSB _u(6)
+#define UART_UARTFR_RXFF_LSB _u(6)
+#define UART_UARTFR_RXFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_TXFF
+// Description : Transmit FIFO full. The meaning of this bit depends on the
+// state of the FEN bit in the UARTLCR_H Register. If the FIFO is
+// disabled, this bit is set when the transmit holding register is
+// full. If the FIFO is enabled, the TXFF bit is set when the
+// transmit FIFO is full.
+#define UART_UARTFR_TXFF_RESET _u(0x0)
+#define UART_UARTFR_TXFF_BITS _u(0x00000020)
+#define UART_UARTFR_TXFF_MSB _u(5)
+#define UART_UARTFR_TXFF_LSB _u(5)
+#define UART_UARTFR_TXFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_RXFE
+// Description : Receive FIFO empty. The meaning of this bit depends on the
+// state of the FEN bit in the UARTLCR_H Register. If the FIFO is
+// disabled, this bit is set when the receive holding register is
+// empty. If the FIFO is enabled, the RXFE bit is set when the
+// receive FIFO is empty.
+#define UART_UARTFR_RXFE_RESET _u(0x1)
+#define UART_UARTFR_RXFE_BITS _u(0x00000010)
+#define UART_UARTFR_RXFE_MSB _u(4)
+#define UART_UARTFR_RXFE_LSB _u(4)
+#define UART_UARTFR_RXFE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_BUSY
+// Description : UART busy. If this bit is set to 1, the UART is busy
+// transmitting data. This bit remains set until the complete
+// byte, including all the stop bits, has been sent from the shift
+// register. This bit is set as soon as the transmit FIFO becomes
+// non-empty, regardless of whether the UART is enabled or not.
+#define UART_UARTFR_BUSY_RESET _u(0x0)
+#define UART_UARTFR_BUSY_BITS _u(0x00000008)
+#define UART_UARTFR_BUSY_MSB _u(3)
+#define UART_UARTFR_BUSY_LSB _u(3)
+#define UART_UARTFR_BUSY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_DCD
+// Description : Data carrier detect. This bit is the complement of the UART
+// data carrier detect, nUARTDCD, modem status input. That is, the
+// bit is 1 when nUARTDCD is LOW.
+#define UART_UARTFR_DCD_RESET "-"
+#define UART_UARTFR_DCD_BITS _u(0x00000004)
+#define UART_UARTFR_DCD_MSB _u(2)
+#define UART_UARTFR_DCD_LSB _u(2)
+#define UART_UARTFR_DCD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_DSR
+// Description : Data set ready. This bit is the complement of the UART data set
+// ready, nUARTDSR, modem status input. That is, the bit is 1 when
+// nUARTDSR is LOW.
+#define UART_UARTFR_DSR_RESET "-"
+#define UART_UARTFR_DSR_BITS _u(0x00000002)
+#define UART_UARTFR_DSR_MSB _u(1)
+#define UART_UARTFR_DSR_LSB _u(1)
+#define UART_UARTFR_DSR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFR_CTS
+// Description : Clear to send. This bit is the complement of the UART clear to
+// send, nUARTCTS, modem status input. That is, the bit is 1 when
+// nUARTCTS is LOW.
+#define UART_UARTFR_CTS_RESET "-"
+#define UART_UARTFR_CTS_BITS _u(0x00000001)
+#define UART_UARTFR_CTS_MSB _u(0)
+#define UART_UARTFR_CTS_LSB _u(0)
+#define UART_UARTFR_CTS_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTILPR
+// Description : IrDA Low-Power Counter Register, UARTILPR
+#define UART_UARTILPR_OFFSET _u(0x00000020)
+#define UART_UARTILPR_BITS _u(0x000000ff)
+#define UART_UARTILPR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTILPR_ILPDVSR
+// Description : 8-bit low-power divisor value. These bits are cleared to 0 at
+// reset.
+#define UART_UARTILPR_ILPDVSR_RESET _u(0x00)
+#define UART_UARTILPR_ILPDVSR_BITS _u(0x000000ff)
+#define UART_UARTILPR_ILPDVSR_MSB _u(7)
+#define UART_UARTILPR_ILPDVSR_LSB _u(0)
+#define UART_UARTILPR_ILPDVSR_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTIBRD
+// Description : Integer Baud Rate Register, UARTIBRD
+#define UART_UARTIBRD_OFFSET _u(0x00000024)
+#define UART_UARTIBRD_BITS _u(0x0000ffff)
+#define UART_UARTIBRD_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIBRD_BAUD_DIVINT
+// Description : The integer baud rate divisor. These bits are cleared to 0 on
+// reset.
+#define UART_UARTIBRD_BAUD_DIVINT_RESET _u(0x0000)
+#define UART_UARTIBRD_BAUD_DIVINT_BITS _u(0x0000ffff)
+#define UART_UARTIBRD_BAUD_DIVINT_MSB _u(15)
+#define UART_UARTIBRD_BAUD_DIVINT_LSB _u(0)
+#define UART_UARTIBRD_BAUD_DIVINT_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTFBRD
+// Description : Fractional Baud Rate Register, UARTFBRD
+#define UART_UARTFBRD_OFFSET _u(0x00000028)
+#define UART_UARTFBRD_BITS _u(0x0000003f)
+#define UART_UARTFBRD_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTFBRD_BAUD_DIVFRAC
+// Description : The fractional baud rate divisor. These bits are cleared to 0
+// on reset.
+#define UART_UARTFBRD_BAUD_DIVFRAC_RESET _u(0x00)
+#define UART_UARTFBRD_BAUD_DIVFRAC_BITS _u(0x0000003f)
+#define UART_UARTFBRD_BAUD_DIVFRAC_MSB _u(5)
+#define UART_UARTFBRD_BAUD_DIVFRAC_LSB _u(0)
+#define UART_UARTFBRD_BAUD_DIVFRAC_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTLCR_H
+// Description : Line Control Register, UARTLCR_H
+#define UART_UARTLCR_H_OFFSET _u(0x0000002c)
+#define UART_UARTLCR_H_BITS _u(0x000000ff)
+#define UART_UARTLCR_H_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTLCR_H_SPS
+// Description : Stick parity select. 0 = stick parity is disabled 1 = either: *
+// if the EPS bit is 0 then the parity bit is transmitted and
+// checked as a 1 * if the EPS bit is 1 then the parity bit is
+// transmitted and checked as a 0. This bit has no effect when the
+// PEN bit disables parity checking and generation.
+#define UART_UARTLCR_H_SPS_RESET _u(0x0)
+#define UART_UARTLCR_H_SPS_BITS _u(0x00000080)
+#define UART_UARTLCR_H_SPS_MSB _u(7)
+#define UART_UARTLCR_H_SPS_LSB _u(7)
+#define UART_UARTLCR_H_SPS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTLCR_H_WLEN
+// Description : Word length. These bits indicate the number of data bits
+// transmitted or received in a frame as follows: b11 = 8 bits b10
+// = 7 bits b01 = 6 bits b00 = 5 bits.
+#define UART_UARTLCR_H_WLEN_RESET _u(0x0)
+#define UART_UARTLCR_H_WLEN_BITS _u(0x00000060)
+#define UART_UARTLCR_H_WLEN_MSB _u(6)
+#define UART_UARTLCR_H_WLEN_LSB _u(5)
+#define UART_UARTLCR_H_WLEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTLCR_H_FEN
+// Description : Enable FIFOs: 0 = FIFOs are disabled (character mode) that is,
+// the FIFOs become 1-byte-deep holding registers 1 = transmit and
+// receive FIFO buffers are enabled (FIFO mode).
+#define UART_UARTLCR_H_FEN_RESET _u(0x0)
+#define UART_UARTLCR_H_FEN_BITS _u(0x00000010)
+#define UART_UARTLCR_H_FEN_MSB _u(4)
+#define UART_UARTLCR_H_FEN_LSB _u(4)
+#define UART_UARTLCR_H_FEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTLCR_H_STP2
+// Description : Two stop bits select. If this bit is set to 1, two stop bits
+// are transmitted at the end of the frame. The receive logic does
+// not check for two stop bits being received.
+#define UART_UARTLCR_H_STP2_RESET _u(0x0)
+#define UART_UARTLCR_H_STP2_BITS _u(0x00000008)
+#define UART_UARTLCR_H_STP2_MSB _u(3)
+#define UART_UARTLCR_H_STP2_LSB _u(3)
+#define UART_UARTLCR_H_STP2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTLCR_H_EPS
+// Description : Even parity select. Controls the type of parity the UART uses
+// during transmission and reception: 0 = odd parity. The UART
+// generates or checks for an odd number of 1s in the data and
+// parity bits. 1 = even parity. The UART generates or checks for
+// an even number of 1s in the data and parity bits. This bit has
+// no effect when the PEN bit disables parity checking and
+// generation.
+#define UART_UARTLCR_H_EPS_RESET _u(0x0)
+#define UART_UARTLCR_H_EPS_BITS _u(0x00000004)
+#define UART_UARTLCR_H_EPS_MSB _u(2)
+#define UART_UARTLCR_H_EPS_LSB _u(2)
+#define UART_UARTLCR_H_EPS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTLCR_H_PEN
+// Description : Parity enable: 0 = parity is disabled and no parity bit added
+// to the data frame 1 = parity checking and generation is
+// enabled.
+#define UART_UARTLCR_H_PEN_RESET _u(0x0)
+#define UART_UARTLCR_H_PEN_BITS _u(0x00000002)
+#define UART_UARTLCR_H_PEN_MSB _u(1)
+#define UART_UARTLCR_H_PEN_LSB _u(1)
+#define UART_UARTLCR_H_PEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTLCR_H_BRK
+// Description : Send break. If this bit is set to 1, a low-level is continually
+// output on the UARTTXD output, after completing transmission of
+// the current character. For the proper execution of the break
+// command, the software must set this bit for at least two
+// complete frames. For normal use, this bit must be cleared to 0.
+#define UART_UARTLCR_H_BRK_RESET _u(0x0)
+#define UART_UARTLCR_H_BRK_BITS _u(0x00000001)
+#define UART_UARTLCR_H_BRK_MSB _u(0)
+#define UART_UARTLCR_H_BRK_LSB _u(0)
+#define UART_UARTLCR_H_BRK_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTCR
+// Description : Control Register, UARTCR
+#define UART_UARTCR_OFFSET _u(0x00000030)
+#define UART_UARTCR_BITS _u(0x0000ff87)
+#define UART_UARTCR_RESET _u(0x00000300)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_CTSEN
+// Description : CTS hardware flow control enable. If this bit is set to 1, CTS
+// hardware flow control is enabled. Data is only transmitted when
+// the nUARTCTS signal is asserted.
+#define UART_UARTCR_CTSEN_RESET _u(0x0)
+#define UART_UARTCR_CTSEN_BITS _u(0x00008000)
+#define UART_UARTCR_CTSEN_MSB _u(15)
+#define UART_UARTCR_CTSEN_LSB _u(15)
+#define UART_UARTCR_CTSEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_RTSEN
+// Description : RTS hardware flow control enable. If this bit is set to 1, RTS
+// hardware flow control is enabled. Data is only requested when
+// there is space in the receive FIFO for it to be received.
+#define UART_UARTCR_RTSEN_RESET _u(0x0)
+#define UART_UARTCR_RTSEN_BITS _u(0x00004000)
+#define UART_UARTCR_RTSEN_MSB _u(14)
+#define UART_UARTCR_RTSEN_LSB _u(14)
+#define UART_UARTCR_RTSEN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_OUT2
+// Description : This bit is the complement of the UART Out2 (nUARTOut2) modem
+// status output. That is, when the bit is programmed to a 1, the
+// output is 0. For DTE this can be used as Ring Indicator (RI).
+#define UART_UARTCR_OUT2_RESET _u(0x0)
+#define UART_UARTCR_OUT2_BITS _u(0x00002000)
+#define UART_UARTCR_OUT2_MSB _u(13)
+#define UART_UARTCR_OUT2_LSB _u(13)
+#define UART_UARTCR_OUT2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_OUT1
+// Description : This bit is the complement of the UART Out1 (nUARTOut1) modem
+// status output. That is, when the bit is programmed to a 1 the
+// output is 0. For DTE this can be used as Data Carrier Detect
+// (DCD).
+#define UART_UARTCR_OUT1_RESET _u(0x0)
+#define UART_UARTCR_OUT1_BITS _u(0x00001000)
+#define UART_UARTCR_OUT1_MSB _u(12)
+#define UART_UARTCR_OUT1_LSB _u(12)
+#define UART_UARTCR_OUT1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_RTS
+// Description : Request to send. This bit is the complement of the UART request
+// to send, nUARTRTS, modem status output. That is, when the bit
+// is programmed to a 1 then nUARTRTS is LOW.
+#define UART_UARTCR_RTS_RESET _u(0x0)
+#define UART_UARTCR_RTS_BITS _u(0x00000800)
+#define UART_UARTCR_RTS_MSB _u(11)
+#define UART_UARTCR_RTS_LSB _u(11)
+#define UART_UARTCR_RTS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_DTR
+// Description : Data transmit ready. This bit is the complement of the UART
+// data transmit ready, nUARTDTR, modem status output. That is,
+// when the bit is programmed to a 1 then nUARTDTR is LOW.
+#define UART_UARTCR_DTR_RESET _u(0x0)
+#define UART_UARTCR_DTR_BITS _u(0x00000400)
+#define UART_UARTCR_DTR_MSB _u(10)
+#define UART_UARTCR_DTR_LSB _u(10)
+#define UART_UARTCR_DTR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_RXE
+// Description : Receive enable. If this bit is set to 1, the receive section of
+// the UART is enabled. Data reception occurs for either UART
+// signals or SIR signals depending on the setting of the SIREN
+// bit. When the UART is disabled in the middle of reception, it
+// completes the current character before stopping.
+#define UART_UARTCR_RXE_RESET _u(0x1)
+#define UART_UARTCR_RXE_BITS _u(0x00000200)
+#define UART_UARTCR_RXE_MSB _u(9)
+#define UART_UARTCR_RXE_LSB _u(9)
+#define UART_UARTCR_RXE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_TXE
+// Description : Transmit enable. If this bit is set to 1, the transmit section
+// of the UART is enabled. Data transmission occurs for either
+// UART signals, or SIR signals depending on the setting of the
+// SIREN bit. When the UART is disabled in the middle of
+// transmission, it completes the current character before
+// stopping.
+#define UART_UARTCR_TXE_RESET _u(0x1)
+#define UART_UARTCR_TXE_BITS _u(0x00000100)
+#define UART_UARTCR_TXE_MSB _u(8)
+#define UART_UARTCR_TXE_LSB _u(8)
+#define UART_UARTCR_TXE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_LBE
+// Description : Loopback enable. If this bit is set to 1 and the SIREN bit is
+// set to 1 and the SIRTEST bit in the Test Control Register,
+// UARTTCR is set to 1, then the nSIROUT path is inverted, and fed
+// through to the SIRIN path. The SIRTEST bit in the test register
+// must be set to 1 to override the normal half-duplex SIR
+// operation. This must be the requirement for accessing the test
+// registers during normal operation, and SIRTEST must be cleared
+// to 0 when loopback testing is finished. This feature reduces
+// the amount of external coupling required during system test. If
+// this bit is set to 1, and the SIRTEST bit is set to 0, the
+// UARTTXD path is fed through to the UARTRXD path. In either SIR
+// mode or UART mode, when this bit is set, the modem outputs are
+// also fed through to the modem inputs. This bit is cleared to 0
+// on reset, to disable loopback.
+#define UART_UARTCR_LBE_RESET _u(0x0)
+#define UART_UARTCR_LBE_BITS _u(0x00000080)
+#define UART_UARTCR_LBE_MSB _u(7)
+#define UART_UARTCR_LBE_LSB _u(7)
+#define UART_UARTCR_LBE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_SIRLP
+// Description : SIR low-power IrDA mode. This bit selects the IrDA encoding
+// mode. If this bit is cleared to 0, low-level bits are
+// transmitted as an active high pulse with a width of 3 / 16th of
+// the bit period. If this bit is set to 1, low-level bits are
+// transmitted with a pulse width that is 3 times the period of
+// the IrLPBaud16 input signal, regardless of the selected bit
+// rate. Setting this bit uses less power, but might reduce
+// transmission distances.
+#define UART_UARTCR_SIRLP_RESET _u(0x0)
+#define UART_UARTCR_SIRLP_BITS _u(0x00000004)
+#define UART_UARTCR_SIRLP_MSB _u(2)
+#define UART_UARTCR_SIRLP_LSB _u(2)
+#define UART_UARTCR_SIRLP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_SIREN
+// Description : SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW
+// (no light pulse generated), and signal transitions on SIRIN
+// have no effect. 1 = IrDA SIR ENDEC is enabled. Data is
+// transmitted and received on nSIROUT and SIRIN. UARTTXD remains
+// HIGH, in the marking state. Signal transitions on UARTRXD or
+// modem status inputs have no effect. This bit has no effect if
+// the UARTEN bit disables the UART.
+#define UART_UARTCR_SIREN_RESET _u(0x0)
+#define UART_UARTCR_SIREN_BITS _u(0x00000002)
+#define UART_UARTCR_SIREN_MSB _u(1)
+#define UART_UARTCR_SIREN_LSB _u(1)
+#define UART_UARTCR_SIREN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTCR_UARTEN
+// Description : UART enable: 0 = UART is disabled. If the UART is disabled in
+// the middle of transmission or reception, it completes the
+// current character before stopping. 1 = the UART is enabled.
+// Data transmission and reception occurs for either UART signals
+// or SIR signals depending on the setting of the SIREN bit.
+#define UART_UARTCR_UARTEN_RESET _u(0x0)
+#define UART_UARTCR_UARTEN_BITS _u(0x00000001)
+#define UART_UARTCR_UARTEN_MSB _u(0)
+#define UART_UARTCR_UARTEN_LSB _u(0)
+#define UART_UARTCR_UARTEN_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTIFLS
+// Description : Interrupt FIFO Level Select Register, UARTIFLS
+#define UART_UARTIFLS_OFFSET _u(0x00000034)
+#define UART_UARTIFLS_BITS _u(0x0000003f)
+#define UART_UARTIFLS_RESET _u(0x00000012)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIFLS_RXIFLSEL
+// Description : Receive interrupt FIFO level select. The trigger points for the
+// receive interrupt are as follows: b000 = Receive FIFO becomes
+// >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 =
+// Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes
+// >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full
+// b101-b111 = reserved.
+#define UART_UARTIFLS_RXIFLSEL_RESET _u(0x2)
+#define UART_UARTIFLS_RXIFLSEL_BITS _u(0x00000038)
+#define UART_UARTIFLS_RXIFLSEL_MSB _u(5)
+#define UART_UARTIFLS_RXIFLSEL_LSB _u(3)
+#define UART_UARTIFLS_RXIFLSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIFLS_TXIFLSEL
+// Description : Transmit interrupt FIFO level select. The trigger points for
+// the transmit interrupt are as follows: b000 = Transmit FIFO
+// becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4
+// full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit
+// FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 /
+// 8 full b101-b111 = reserved.
+#define UART_UARTIFLS_TXIFLSEL_RESET _u(0x2)
+#define UART_UARTIFLS_TXIFLSEL_BITS _u(0x00000007)
+#define UART_UARTIFLS_TXIFLSEL_MSB _u(2)
+#define UART_UARTIFLS_TXIFLSEL_LSB _u(0)
+#define UART_UARTIFLS_TXIFLSEL_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTIMSC
+// Description : Interrupt Mask Set/Clear Register, UARTIMSC
+#define UART_UARTIMSC_OFFSET _u(0x00000038)
+#define UART_UARTIMSC_BITS _u(0x000007ff)
+#define UART_UARTIMSC_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_OEIM
+// Description : Overrun error interrupt mask. A read returns the current mask
+// for the UARTOEINTR interrupt. On a write of 1, the mask of the
+// UARTOEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_OEIM_RESET _u(0x0)
+#define UART_UARTIMSC_OEIM_BITS _u(0x00000400)
+#define UART_UARTIMSC_OEIM_MSB _u(10)
+#define UART_UARTIMSC_OEIM_LSB _u(10)
+#define UART_UARTIMSC_OEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_BEIM
+// Description : Break error interrupt mask. A read returns the current mask for
+// the UARTBEINTR interrupt. On a write of 1, the mask of the
+// UARTBEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_BEIM_RESET _u(0x0)
+#define UART_UARTIMSC_BEIM_BITS _u(0x00000200)
+#define UART_UARTIMSC_BEIM_MSB _u(9)
+#define UART_UARTIMSC_BEIM_LSB _u(9)
+#define UART_UARTIMSC_BEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_PEIM
+// Description : Parity error interrupt mask. A read returns the current mask
+// for the UARTPEINTR interrupt. On a write of 1, the mask of the
+// UARTPEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_PEIM_RESET _u(0x0)
+#define UART_UARTIMSC_PEIM_BITS _u(0x00000100)
+#define UART_UARTIMSC_PEIM_MSB _u(8)
+#define UART_UARTIMSC_PEIM_LSB _u(8)
+#define UART_UARTIMSC_PEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_FEIM
+// Description : Framing error interrupt mask. A read returns the current mask
+// for the UARTFEINTR interrupt. On a write of 1, the mask of the
+// UARTFEINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_FEIM_RESET _u(0x0)
+#define UART_UARTIMSC_FEIM_BITS _u(0x00000080)
+#define UART_UARTIMSC_FEIM_MSB _u(7)
+#define UART_UARTIMSC_FEIM_LSB _u(7)
+#define UART_UARTIMSC_FEIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_RTIM
+// Description : Receive timeout interrupt mask. A read returns the current mask
+// for the UARTRTINTR interrupt. On a write of 1, the mask of the
+// UARTRTINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_RTIM_RESET _u(0x0)
+#define UART_UARTIMSC_RTIM_BITS _u(0x00000040)
+#define UART_UARTIMSC_RTIM_MSB _u(6)
+#define UART_UARTIMSC_RTIM_LSB _u(6)
+#define UART_UARTIMSC_RTIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_TXIM
+// Description : Transmit interrupt mask. A read returns the current mask for
+// the UARTTXINTR interrupt. On a write of 1, the mask of the
+// UARTTXINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_TXIM_RESET _u(0x0)
+#define UART_UARTIMSC_TXIM_BITS _u(0x00000020)
+#define UART_UARTIMSC_TXIM_MSB _u(5)
+#define UART_UARTIMSC_TXIM_LSB _u(5)
+#define UART_UARTIMSC_TXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_RXIM
+// Description : Receive interrupt mask. A read returns the current mask for the
+// UARTRXINTR interrupt. On a write of 1, the mask of the
+// UARTRXINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_RXIM_RESET _u(0x0)
+#define UART_UARTIMSC_RXIM_BITS _u(0x00000010)
+#define UART_UARTIMSC_RXIM_MSB _u(4)
+#define UART_UARTIMSC_RXIM_LSB _u(4)
+#define UART_UARTIMSC_RXIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_DSRMIM
+// Description : nUARTDSR modem interrupt mask. A read returns the current mask
+// for the UARTDSRINTR interrupt. On a write of 1, the mask of the
+// UARTDSRINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_DSRMIM_RESET _u(0x0)
+#define UART_UARTIMSC_DSRMIM_BITS _u(0x00000008)
+#define UART_UARTIMSC_DSRMIM_MSB _u(3)
+#define UART_UARTIMSC_DSRMIM_LSB _u(3)
+#define UART_UARTIMSC_DSRMIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_DCDMIM
+// Description : nUARTDCD modem interrupt mask. A read returns the current mask
+// for the UARTDCDINTR interrupt. On a write of 1, the mask of the
+// UARTDCDINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_DCDMIM_RESET _u(0x0)
+#define UART_UARTIMSC_DCDMIM_BITS _u(0x00000004)
+#define UART_UARTIMSC_DCDMIM_MSB _u(2)
+#define UART_UARTIMSC_DCDMIM_LSB _u(2)
+#define UART_UARTIMSC_DCDMIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_CTSMIM
+// Description : nUARTCTS modem interrupt mask. A read returns the current mask
+// for the UARTCTSINTR interrupt. On a write of 1, the mask of the
+// UARTCTSINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_CTSMIM_RESET _u(0x0)
+#define UART_UARTIMSC_CTSMIM_BITS _u(0x00000002)
+#define UART_UARTIMSC_CTSMIM_MSB _u(1)
+#define UART_UARTIMSC_CTSMIM_LSB _u(1)
+#define UART_UARTIMSC_CTSMIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTIMSC_RIMIM
+// Description : nUARTRI modem interrupt mask. A read returns the current mask
+// for the UARTRIINTR interrupt. On a write of 1, the mask of the
+// UARTRIINTR interrupt is set. A write of 0 clears the mask.
+#define UART_UARTIMSC_RIMIM_RESET _u(0x0)
+#define UART_UARTIMSC_RIMIM_BITS _u(0x00000001)
+#define UART_UARTIMSC_RIMIM_MSB _u(0)
+#define UART_UARTIMSC_RIMIM_LSB _u(0)
+#define UART_UARTIMSC_RIMIM_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTRIS
+// Description : Raw Interrupt Status Register, UARTRIS
+#define UART_UARTRIS_OFFSET _u(0x0000003c)
+#define UART_UARTRIS_BITS _u(0x000007ff)
+#define UART_UARTRIS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_OERIS
+// Description : Overrun error interrupt status. Returns the raw interrupt state
+// of the UARTOEINTR interrupt.
+#define UART_UARTRIS_OERIS_RESET _u(0x0)
+#define UART_UARTRIS_OERIS_BITS _u(0x00000400)
+#define UART_UARTRIS_OERIS_MSB _u(10)
+#define UART_UARTRIS_OERIS_LSB _u(10)
+#define UART_UARTRIS_OERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_BERIS
+// Description : Break error interrupt status. Returns the raw interrupt state
+// of the UARTBEINTR interrupt.
+#define UART_UARTRIS_BERIS_RESET _u(0x0)
+#define UART_UARTRIS_BERIS_BITS _u(0x00000200)
+#define UART_UARTRIS_BERIS_MSB _u(9)
+#define UART_UARTRIS_BERIS_LSB _u(9)
+#define UART_UARTRIS_BERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_PERIS
+// Description : Parity error interrupt status. Returns the raw interrupt state
+// of the UARTPEINTR interrupt.
+#define UART_UARTRIS_PERIS_RESET _u(0x0)
+#define UART_UARTRIS_PERIS_BITS _u(0x00000100)
+#define UART_UARTRIS_PERIS_MSB _u(8)
+#define UART_UARTRIS_PERIS_LSB _u(8)
+#define UART_UARTRIS_PERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_FERIS
+// Description : Framing error interrupt status. Returns the raw interrupt state
+// of the UARTFEINTR interrupt.
+#define UART_UARTRIS_FERIS_RESET _u(0x0)
+#define UART_UARTRIS_FERIS_BITS _u(0x00000080)
+#define UART_UARTRIS_FERIS_MSB _u(7)
+#define UART_UARTRIS_FERIS_LSB _u(7)
+#define UART_UARTRIS_FERIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_RTRIS
+// Description : Receive timeout interrupt status. Returns the raw interrupt
+// state of the UARTRTINTR interrupt. a
+#define UART_UARTRIS_RTRIS_RESET _u(0x0)
+#define UART_UARTRIS_RTRIS_BITS _u(0x00000040)
+#define UART_UARTRIS_RTRIS_MSB _u(6)
+#define UART_UARTRIS_RTRIS_LSB _u(6)
+#define UART_UARTRIS_RTRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_TXRIS
+// Description : Transmit interrupt status. Returns the raw interrupt state of
+// the UARTTXINTR interrupt.
+#define UART_UARTRIS_TXRIS_RESET _u(0x0)
+#define UART_UARTRIS_TXRIS_BITS _u(0x00000020)
+#define UART_UARTRIS_TXRIS_MSB _u(5)
+#define UART_UARTRIS_TXRIS_LSB _u(5)
+#define UART_UARTRIS_TXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_RXRIS
+// Description : Receive interrupt status. Returns the raw interrupt state of
+// the UARTRXINTR interrupt.
+#define UART_UARTRIS_RXRIS_RESET _u(0x0)
+#define UART_UARTRIS_RXRIS_BITS _u(0x00000010)
+#define UART_UARTRIS_RXRIS_MSB _u(4)
+#define UART_UARTRIS_RXRIS_LSB _u(4)
+#define UART_UARTRIS_RXRIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_DSRRMIS
+// Description : nUARTDSR modem interrupt status. Returns the raw interrupt
+// state of the UARTDSRINTR interrupt.
+#define UART_UARTRIS_DSRRMIS_RESET "-"
+#define UART_UARTRIS_DSRRMIS_BITS _u(0x00000008)
+#define UART_UARTRIS_DSRRMIS_MSB _u(3)
+#define UART_UARTRIS_DSRRMIS_LSB _u(3)
+#define UART_UARTRIS_DSRRMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_DCDRMIS
+// Description : nUARTDCD modem interrupt status. Returns the raw interrupt
+// state of the UARTDCDINTR interrupt.
+#define UART_UARTRIS_DCDRMIS_RESET "-"
+#define UART_UARTRIS_DCDRMIS_BITS _u(0x00000004)
+#define UART_UARTRIS_DCDRMIS_MSB _u(2)
+#define UART_UARTRIS_DCDRMIS_LSB _u(2)
+#define UART_UARTRIS_DCDRMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_CTSRMIS
+// Description : nUARTCTS modem interrupt status. Returns the raw interrupt
+// state of the UARTCTSINTR interrupt.
+#define UART_UARTRIS_CTSRMIS_RESET "-"
+#define UART_UARTRIS_CTSRMIS_BITS _u(0x00000002)
+#define UART_UARTRIS_CTSRMIS_MSB _u(1)
+#define UART_UARTRIS_CTSRMIS_LSB _u(1)
+#define UART_UARTRIS_CTSRMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTRIS_RIRMIS
+// Description : nUARTRI modem interrupt status. Returns the raw interrupt state
+// of the UARTRIINTR interrupt.
+#define UART_UARTRIS_RIRMIS_RESET "-"
+#define UART_UARTRIS_RIRMIS_BITS _u(0x00000001)
+#define UART_UARTRIS_RIRMIS_MSB _u(0)
+#define UART_UARTRIS_RIRMIS_LSB _u(0)
+#define UART_UARTRIS_RIRMIS_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTMIS
+// Description : Masked Interrupt Status Register, UARTMIS
+#define UART_UARTMIS_OFFSET _u(0x00000040)
+#define UART_UARTMIS_BITS _u(0x000007ff)
+#define UART_UARTMIS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_OEMIS
+// Description : Overrun error masked interrupt status. Returns the masked
+// interrupt state of the UARTOEINTR interrupt.
+#define UART_UARTMIS_OEMIS_RESET _u(0x0)
+#define UART_UARTMIS_OEMIS_BITS _u(0x00000400)
+#define UART_UARTMIS_OEMIS_MSB _u(10)
+#define UART_UARTMIS_OEMIS_LSB _u(10)
+#define UART_UARTMIS_OEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_BEMIS
+// Description : Break error masked interrupt status. Returns the masked
+// interrupt state of the UARTBEINTR interrupt.
+#define UART_UARTMIS_BEMIS_RESET _u(0x0)
+#define UART_UARTMIS_BEMIS_BITS _u(0x00000200)
+#define UART_UARTMIS_BEMIS_MSB _u(9)
+#define UART_UARTMIS_BEMIS_LSB _u(9)
+#define UART_UARTMIS_BEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_PEMIS
+// Description : Parity error masked interrupt status. Returns the masked
+// interrupt state of the UARTPEINTR interrupt.
+#define UART_UARTMIS_PEMIS_RESET _u(0x0)
+#define UART_UARTMIS_PEMIS_BITS _u(0x00000100)
+#define UART_UARTMIS_PEMIS_MSB _u(8)
+#define UART_UARTMIS_PEMIS_LSB _u(8)
+#define UART_UARTMIS_PEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_FEMIS
+// Description : Framing error masked interrupt status. Returns the masked
+// interrupt state of the UARTFEINTR interrupt.
+#define UART_UARTMIS_FEMIS_RESET _u(0x0)
+#define UART_UARTMIS_FEMIS_BITS _u(0x00000080)
+#define UART_UARTMIS_FEMIS_MSB _u(7)
+#define UART_UARTMIS_FEMIS_LSB _u(7)
+#define UART_UARTMIS_FEMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_RTMIS
+// Description : Receive timeout masked interrupt status. Returns the masked
+// interrupt state of the UARTRTINTR interrupt.
+#define UART_UARTMIS_RTMIS_RESET _u(0x0)
+#define UART_UARTMIS_RTMIS_BITS _u(0x00000040)
+#define UART_UARTMIS_RTMIS_MSB _u(6)
+#define UART_UARTMIS_RTMIS_LSB _u(6)
+#define UART_UARTMIS_RTMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_TXMIS
+// Description : Transmit masked interrupt status. Returns the masked interrupt
+// state of the UARTTXINTR interrupt.
+#define UART_UARTMIS_TXMIS_RESET _u(0x0)
+#define UART_UARTMIS_TXMIS_BITS _u(0x00000020)
+#define UART_UARTMIS_TXMIS_MSB _u(5)
+#define UART_UARTMIS_TXMIS_LSB _u(5)
+#define UART_UARTMIS_TXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_RXMIS
+// Description : Receive masked interrupt status. Returns the masked interrupt
+// state of the UARTRXINTR interrupt.
+#define UART_UARTMIS_RXMIS_RESET _u(0x0)
+#define UART_UARTMIS_RXMIS_BITS _u(0x00000010)
+#define UART_UARTMIS_RXMIS_MSB _u(4)
+#define UART_UARTMIS_RXMIS_LSB _u(4)
+#define UART_UARTMIS_RXMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_DSRMMIS
+// Description : nUARTDSR modem masked interrupt status. Returns the masked
+// interrupt state of the UARTDSRINTR interrupt.
+#define UART_UARTMIS_DSRMMIS_RESET "-"
+#define UART_UARTMIS_DSRMMIS_BITS _u(0x00000008)
+#define UART_UARTMIS_DSRMMIS_MSB _u(3)
+#define UART_UARTMIS_DSRMMIS_LSB _u(3)
+#define UART_UARTMIS_DSRMMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_DCDMMIS
+// Description : nUARTDCD modem masked interrupt status. Returns the masked
+// interrupt state of the UARTDCDINTR interrupt.
+#define UART_UARTMIS_DCDMMIS_RESET "-"
+#define UART_UARTMIS_DCDMMIS_BITS _u(0x00000004)
+#define UART_UARTMIS_DCDMMIS_MSB _u(2)
+#define UART_UARTMIS_DCDMMIS_LSB _u(2)
+#define UART_UARTMIS_DCDMMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_CTSMMIS
+// Description : nUARTCTS modem masked interrupt status. Returns the masked
+// interrupt state of the UARTCTSINTR interrupt.
+#define UART_UARTMIS_CTSMMIS_RESET "-"
+#define UART_UARTMIS_CTSMMIS_BITS _u(0x00000002)
+#define UART_UARTMIS_CTSMMIS_MSB _u(1)
+#define UART_UARTMIS_CTSMMIS_LSB _u(1)
+#define UART_UARTMIS_CTSMMIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTMIS_RIMMIS
+// Description : nUARTRI modem masked interrupt status. Returns the masked
+// interrupt state of the UARTRIINTR interrupt.
+#define UART_UARTMIS_RIMMIS_RESET "-"
+#define UART_UARTMIS_RIMMIS_BITS _u(0x00000001)
+#define UART_UARTMIS_RIMMIS_MSB _u(0)
+#define UART_UARTMIS_RIMMIS_LSB _u(0)
+#define UART_UARTMIS_RIMMIS_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTICR
+// Description : Interrupt Clear Register, UARTICR
+#define UART_UARTICR_OFFSET _u(0x00000044)
+#define UART_UARTICR_BITS _u(0x000007ff)
+#define UART_UARTICR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_OEIC
+// Description : Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
+#define UART_UARTICR_OEIC_RESET "-"
+#define UART_UARTICR_OEIC_BITS _u(0x00000400)
+#define UART_UARTICR_OEIC_MSB _u(10)
+#define UART_UARTICR_OEIC_LSB _u(10)
+#define UART_UARTICR_OEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_BEIC
+// Description : Break error interrupt clear. Clears the UARTBEINTR interrupt.
+#define UART_UARTICR_BEIC_RESET "-"
+#define UART_UARTICR_BEIC_BITS _u(0x00000200)
+#define UART_UARTICR_BEIC_MSB _u(9)
+#define UART_UARTICR_BEIC_LSB _u(9)
+#define UART_UARTICR_BEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_PEIC
+// Description : Parity error interrupt clear. Clears the UARTPEINTR interrupt.
+#define UART_UARTICR_PEIC_RESET "-"
+#define UART_UARTICR_PEIC_BITS _u(0x00000100)
+#define UART_UARTICR_PEIC_MSB _u(8)
+#define UART_UARTICR_PEIC_LSB _u(8)
+#define UART_UARTICR_PEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_FEIC
+// Description : Framing error interrupt clear. Clears the UARTFEINTR interrupt.
+#define UART_UARTICR_FEIC_RESET "-"
+#define UART_UARTICR_FEIC_BITS _u(0x00000080)
+#define UART_UARTICR_FEIC_MSB _u(7)
+#define UART_UARTICR_FEIC_LSB _u(7)
+#define UART_UARTICR_FEIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_RTIC
+// Description : Receive timeout interrupt clear. Clears the UARTRTINTR
+// interrupt.
+#define UART_UARTICR_RTIC_RESET "-"
+#define UART_UARTICR_RTIC_BITS _u(0x00000040)
+#define UART_UARTICR_RTIC_MSB _u(6)
+#define UART_UARTICR_RTIC_LSB _u(6)
+#define UART_UARTICR_RTIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_TXIC
+// Description : Transmit interrupt clear. Clears the UARTTXINTR interrupt.
+#define UART_UARTICR_TXIC_RESET "-"
+#define UART_UARTICR_TXIC_BITS _u(0x00000020)
+#define UART_UARTICR_TXIC_MSB _u(5)
+#define UART_UARTICR_TXIC_LSB _u(5)
+#define UART_UARTICR_TXIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_RXIC
+// Description : Receive interrupt clear. Clears the UARTRXINTR interrupt.
+#define UART_UARTICR_RXIC_RESET "-"
+#define UART_UARTICR_RXIC_BITS _u(0x00000010)
+#define UART_UARTICR_RXIC_MSB _u(4)
+#define UART_UARTICR_RXIC_LSB _u(4)
+#define UART_UARTICR_RXIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_DSRMIC
+// Description : nUARTDSR modem interrupt clear. Clears the UARTDSRINTR
+// interrupt.
+#define UART_UARTICR_DSRMIC_RESET "-"
+#define UART_UARTICR_DSRMIC_BITS _u(0x00000008)
+#define UART_UARTICR_DSRMIC_MSB _u(3)
+#define UART_UARTICR_DSRMIC_LSB _u(3)
+#define UART_UARTICR_DSRMIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_DCDMIC
+// Description : nUARTDCD modem interrupt clear. Clears the UARTDCDINTR
+// interrupt.
+#define UART_UARTICR_DCDMIC_RESET "-"
+#define UART_UARTICR_DCDMIC_BITS _u(0x00000004)
+#define UART_UARTICR_DCDMIC_MSB _u(2)
+#define UART_UARTICR_DCDMIC_LSB _u(2)
+#define UART_UARTICR_DCDMIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_CTSMIC
+// Description : nUARTCTS modem interrupt clear. Clears the UARTCTSINTR
+// interrupt.
+#define UART_UARTICR_CTSMIC_RESET "-"
+#define UART_UARTICR_CTSMIC_BITS _u(0x00000002)
+#define UART_UARTICR_CTSMIC_MSB _u(1)
+#define UART_UARTICR_CTSMIC_LSB _u(1)
+#define UART_UARTICR_CTSMIC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTICR_RIMIC
+// Description : nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
+#define UART_UARTICR_RIMIC_RESET "-"
+#define UART_UARTICR_RIMIC_BITS _u(0x00000001)
+#define UART_UARTICR_RIMIC_MSB _u(0)
+#define UART_UARTICR_RIMIC_LSB _u(0)
+#define UART_UARTICR_RIMIC_ACCESS "WC"
+// =============================================================================
+// Register : UART_UARTDMACR
+// Description : DMA Control Register, UARTDMACR
+#define UART_UARTDMACR_OFFSET _u(0x00000048)
+#define UART_UARTDMACR_BITS _u(0x00000007)
+#define UART_UARTDMACR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDMACR_DMAONERR
+// Description : DMA on error. If this bit is set to 1, the DMA receive request
+// outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the
+// UART error interrupt is asserted.
+#define UART_UARTDMACR_DMAONERR_RESET _u(0x0)
+#define UART_UARTDMACR_DMAONERR_BITS _u(0x00000004)
+#define UART_UARTDMACR_DMAONERR_MSB _u(2)
+#define UART_UARTDMACR_DMAONERR_LSB _u(2)
+#define UART_UARTDMACR_DMAONERR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDMACR_TXDMAE
+// Description : Transmit DMA enable. If this bit is set to 1, DMA for the
+// transmit FIFO is enabled.
+#define UART_UARTDMACR_TXDMAE_RESET _u(0x0)
+#define UART_UARTDMACR_TXDMAE_BITS _u(0x00000002)
+#define UART_UARTDMACR_TXDMAE_MSB _u(1)
+#define UART_UARTDMACR_TXDMAE_LSB _u(1)
+#define UART_UARTDMACR_TXDMAE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTDMACR_RXDMAE
+// Description : Receive DMA enable. If this bit is set to 1, DMA for the
+// receive FIFO is enabled.
+#define UART_UARTDMACR_RXDMAE_RESET _u(0x0)
+#define UART_UARTDMACR_RXDMAE_BITS _u(0x00000001)
+#define UART_UARTDMACR_RXDMAE_MSB _u(0)
+#define UART_UARTDMACR_RXDMAE_LSB _u(0)
+#define UART_UARTDMACR_RXDMAE_ACCESS "RW"
+// =============================================================================
+// Register : UART_UARTPERIPHID0
+// Description : UARTPeriphID0 Register
+#define UART_UARTPERIPHID0_OFFSET _u(0x00000fe0)
+#define UART_UARTPERIPHID0_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID0_RESET _u(0x00000011)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPERIPHID0_PARTNUMBER0
+// Description : These bits read back as 0x11
+#define UART_UARTPERIPHID0_PARTNUMBER0_RESET _u(0x11)
+#define UART_UARTPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID0_PARTNUMBER0_MSB _u(7)
+#define UART_UARTPERIPHID0_PARTNUMBER0_LSB _u(0)
+#define UART_UARTPERIPHID0_PARTNUMBER0_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTPERIPHID1
+// Description : UARTPeriphID1 Register
+#define UART_UARTPERIPHID1_OFFSET _u(0x00000fe4)
+#define UART_UARTPERIPHID1_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID1_RESET _u(0x00000010)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPERIPHID1_DESIGNER0
+// Description : These bits read back as 0x1
+#define UART_UARTPERIPHID1_DESIGNER0_RESET _u(0x1)
+#define UART_UARTPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
+#define UART_UARTPERIPHID1_DESIGNER0_MSB _u(7)
+#define UART_UARTPERIPHID1_DESIGNER0_LSB _u(4)
+#define UART_UARTPERIPHID1_DESIGNER0_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPERIPHID1_PARTNUMBER1
+// Description : These bits read back as 0x0
+#define UART_UARTPERIPHID1_PARTNUMBER1_RESET _u(0x0)
+#define UART_UARTPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
+#define UART_UARTPERIPHID1_PARTNUMBER1_MSB _u(3)
+#define UART_UARTPERIPHID1_PARTNUMBER1_LSB _u(0)
+#define UART_UARTPERIPHID1_PARTNUMBER1_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTPERIPHID2
+// Description : UARTPeriphID2 Register
+#define UART_UARTPERIPHID2_OFFSET _u(0x00000fe8)
+#define UART_UARTPERIPHID2_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID2_RESET _u(0x00000034)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPERIPHID2_REVISION
+// Description : This field depends on the revision of the UART: r1p0 0x0 r1p1
+// 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
+#define UART_UARTPERIPHID2_REVISION_RESET _u(0x3)
+#define UART_UARTPERIPHID2_REVISION_BITS _u(0x000000f0)
+#define UART_UARTPERIPHID2_REVISION_MSB _u(7)
+#define UART_UARTPERIPHID2_REVISION_LSB _u(4)
+#define UART_UARTPERIPHID2_REVISION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPERIPHID2_DESIGNER1
+// Description : These bits read back as 0x4
+#define UART_UARTPERIPHID2_DESIGNER1_RESET _u(0x4)
+#define UART_UARTPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
+#define UART_UARTPERIPHID2_DESIGNER1_MSB _u(3)
+#define UART_UARTPERIPHID2_DESIGNER1_LSB _u(0)
+#define UART_UARTPERIPHID2_DESIGNER1_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTPERIPHID3
+// Description : UARTPeriphID3 Register
+#define UART_UARTPERIPHID3_OFFSET _u(0x00000fec)
+#define UART_UARTPERIPHID3_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPERIPHID3_CONFIGURATION
+// Description : These bits read back as 0x00
+#define UART_UARTPERIPHID3_CONFIGURATION_RESET _u(0x00)
+#define UART_UARTPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
+#define UART_UARTPERIPHID3_CONFIGURATION_MSB _u(7)
+#define UART_UARTPERIPHID3_CONFIGURATION_LSB _u(0)
+#define UART_UARTPERIPHID3_CONFIGURATION_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTPCELLID0
+// Description : UARTPCellID0 Register
+#define UART_UARTPCELLID0_OFFSET _u(0x00000ff0)
+#define UART_UARTPCELLID0_BITS _u(0x000000ff)
+#define UART_UARTPCELLID0_RESET _u(0x0000000d)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPCELLID0_UARTPCELLID0
+// Description : These bits read back as 0x0D
+#define UART_UARTPCELLID0_UARTPCELLID0_RESET _u(0x0d)
+#define UART_UARTPCELLID0_UARTPCELLID0_BITS _u(0x000000ff)
+#define UART_UARTPCELLID0_UARTPCELLID0_MSB _u(7)
+#define UART_UARTPCELLID0_UARTPCELLID0_LSB _u(0)
+#define UART_UARTPCELLID0_UARTPCELLID0_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTPCELLID1
+// Description : UARTPCellID1 Register
+#define UART_UARTPCELLID1_OFFSET _u(0x00000ff4)
+#define UART_UARTPCELLID1_BITS _u(0x000000ff)
+#define UART_UARTPCELLID1_RESET _u(0x000000f0)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPCELLID1_UARTPCELLID1
+// Description : These bits read back as 0xF0
+#define UART_UARTPCELLID1_UARTPCELLID1_RESET _u(0xf0)
+#define UART_UARTPCELLID1_UARTPCELLID1_BITS _u(0x000000ff)
+#define UART_UARTPCELLID1_UARTPCELLID1_MSB _u(7)
+#define UART_UARTPCELLID1_UARTPCELLID1_LSB _u(0)
+#define UART_UARTPCELLID1_UARTPCELLID1_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTPCELLID2
+// Description : UARTPCellID2 Register
+#define UART_UARTPCELLID2_OFFSET _u(0x00000ff8)
+#define UART_UARTPCELLID2_BITS _u(0x000000ff)
+#define UART_UARTPCELLID2_RESET _u(0x00000005)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPCELLID2_UARTPCELLID2
+// Description : These bits read back as 0x05
+#define UART_UARTPCELLID2_UARTPCELLID2_RESET _u(0x05)
+#define UART_UARTPCELLID2_UARTPCELLID2_BITS _u(0x000000ff)
+#define UART_UARTPCELLID2_UARTPCELLID2_MSB _u(7)
+#define UART_UARTPCELLID2_UARTPCELLID2_LSB _u(0)
+#define UART_UARTPCELLID2_UARTPCELLID2_ACCESS "RO"
+// =============================================================================
+// Register : UART_UARTPCELLID3
+// Description : UARTPCellID3 Register
+#define UART_UARTPCELLID3_OFFSET _u(0x00000ffc)
+#define UART_UARTPCELLID3_BITS _u(0x000000ff)
+#define UART_UARTPCELLID3_RESET _u(0x000000b1)
+// -----------------------------------------------------------------------------
+// Field : UART_UARTPCELLID3_UARTPCELLID3
+// Description : These bits read back as 0xB1
+#define UART_UARTPCELLID3_UARTPCELLID3_RESET _u(0xb1)
+#define UART_UARTPCELLID3_UARTPCELLID3_BITS _u(0x000000ff)
+#define UART_UARTPCELLID3_UARTPCELLID3_MSB _u(7)
+#define UART_UARTPCELLID3_UARTPCELLID3_LSB _u(0)
+#define UART_UARTPCELLID3_UARTPCELLID3_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_UART_DEFINED
diff --git a/arkanoid/pico/hardware/regs/usb.h b/arkanoid/pico/hardware/regs/usb.h
new file mode 100644
index 0000000..552cd11
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/usb.h
@@ -0,0 +1,3603 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : USB
+// Version : 1
+// Bus type : ahbl
+// Description : USB FS/LS controller device registers
+// =============================================================================
+#ifndef HARDWARE_REGS_USB_DEFINED
+#define HARDWARE_REGS_USB_DEFINED
+// =============================================================================
+// Register : USB_ADDR_ENDP
+// Description : Device address and endpoint control
+#define USB_ADDR_ENDP_OFFSET _u(0x00000000)
+#define USB_ADDR_ENDP_BITS _u(0x000f007f)
+#define USB_ADDR_ENDP_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP_ENDPOINT
+// Description : Device endpoint to send data to. Only valid for HOST mode.
+#define USB_ADDR_ENDP_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP_ADDRESS
+// Description : In device mode, the address that the device should respond to.
+// Set in response to a SET_ADDR setup packet from the host. In
+// host mode set to the address of the device to communicate with.
+#define USB_ADDR_ENDP_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP1
+// Description : Interrupt endpoint 1. Only valid for HOST mode.
+#define USB_ADDR_ENDP1_OFFSET _u(0x00000004)
+#define USB_ADDR_ENDP1_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP1_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP1_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP1_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP1_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP1_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP1_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP1_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP1_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP1_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP1_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP1_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP1_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP1_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP1_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP1_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP1_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP1_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP1_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP1_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP1_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP1_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP2
+// Description : Interrupt endpoint 2. Only valid for HOST mode.
+#define USB_ADDR_ENDP2_OFFSET _u(0x00000008)
+#define USB_ADDR_ENDP2_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP2_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP2_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP2_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP2_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP2_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP2_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP2_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP2_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP2_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP2_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP2_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP2_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP2_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP2_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP2_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP2_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP2_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP2_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP2_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP2_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP2_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP3
+// Description : Interrupt endpoint 3. Only valid for HOST mode.
+#define USB_ADDR_ENDP3_OFFSET _u(0x0000000c)
+#define USB_ADDR_ENDP3_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP3_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP3_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP3_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP3_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP3_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP3_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP3_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP3_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP3_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP3_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP3_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP3_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP3_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP3_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP3_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP3_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP3_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP3_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP3_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP3_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP3_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP4
+// Description : Interrupt endpoint 4. Only valid for HOST mode.
+#define USB_ADDR_ENDP4_OFFSET _u(0x00000010)
+#define USB_ADDR_ENDP4_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP4_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP4_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP4_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP4_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP4_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP4_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP4_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP4_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP4_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP4_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP4_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP4_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP4_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP4_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP4_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP4_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP4_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP4_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP4_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP4_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP4_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP5
+// Description : Interrupt endpoint 5. Only valid for HOST mode.
+#define USB_ADDR_ENDP5_OFFSET _u(0x00000014)
+#define USB_ADDR_ENDP5_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP5_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP5_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP5_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP5_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP5_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP5_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP5_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP5_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP5_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP5_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP5_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP5_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP5_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP5_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP5_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP5_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP5_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP5_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP5_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP5_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP5_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP6
+// Description : Interrupt endpoint 6. Only valid for HOST mode.
+#define USB_ADDR_ENDP6_OFFSET _u(0x00000018)
+#define USB_ADDR_ENDP6_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP6_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP6_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP6_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP6_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP6_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP6_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP6_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP6_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP6_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP6_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP6_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP6_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP6_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP6_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP6_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP6_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP6_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP6_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP6_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP6_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP6_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP7
+// Description : Interrupt endpoint 7. Only valid for HOST mode.
+#define USB_ADDR_ENDP7_OFFSET _u(0x0000001c)
+#define USB_ADDR_ENDP7_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP7_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP7_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP7_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP7_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP7_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP7_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP7_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP7_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP7_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP7_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP7_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP7_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP7_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP7_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP7_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP7_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP7_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP7_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP7_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP7_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP7_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP8
+// Description : Interrupt endpoint 8. Only valid for HOST mode.
+#define USB_ADDR_ENDP8_OFFSET _u(0x00000020)
+#define USB_ADDR_ENDP8_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP8_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP8_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP8_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP8_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP8_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP8_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP8_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP8_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP8_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP8_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP8_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP8_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP8_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP8_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP8_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP8_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP8_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP8_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP8_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP8_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP8_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP9
+// Description : Interrupt endpoint 9. Only valid for HOST mode.
+#define USB_ADDR_ENDP9_OFFSET _u(0x00000024)
+#define USB_ADDR_ENDP9_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP9_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP9_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP9_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP9_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP9_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP9_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP9_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP9_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP9_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP9_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP9_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP9_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP9_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP9_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP9_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP9_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP9_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP9_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP9_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP9_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP9_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP10
+// Description : Interrupt endpoint 10. Only valid for HOST mode.
+#define USB_ADDR_ENDP10_OFFSET _u(0x00000028)
+#define USB_ADDR_ENDP10_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP10_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP10_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP10_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP10_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP10_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP10_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP10_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP10_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP10_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP10_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP10_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP10_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP10_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP10_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP10_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP10_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP10_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP10_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP10_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP10_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP10_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP11
+// Description : Interrupt endpoint 11. Only valid for HOST mode.
+#define USB_ADDR_ENDP11_OFFSET _u(0x0000002c)
+#define USB_ADDR_ENDP11_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP11_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP11_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP11_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP11_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP11_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP11_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP11_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP11_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP11_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP11_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP11_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP11_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP11_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP11_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP11_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP11_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP11_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP11_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP11_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP11_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP11_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP12
+// Description : Interrupt endpoint 12. Only valid for HOST mode.
+#define USB_ADDR_ENDP12_OFFSET _u(0x00000030)
+#define USB_ADDR_ENDP12_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP12_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP12_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP12_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP12_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP12_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP12_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP12_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP12_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP12_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP12_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP12_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP12_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP12_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP12_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP12_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP12_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP12_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP12_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP12_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP12_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP12_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP13
+// Description : Interrupt endpoint 13. Only valid for HOST mode.
+#define USB_ADDR_ENDP13_OFFSET _u(0x00000034)
+#define USB_ADDR_ENDP13_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP13_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP13_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP13_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP13_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP13_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP13_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP13_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP13_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP13_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP13_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP13_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP13_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP13_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP13_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP13_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP13_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP13_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP13_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP13_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP13_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP13_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP14
+// Description : Interrupt endpoint 14. Only valid for HOST mode.
+#define USB_ADDR_ENDP14_OFFSET _u(0x00000038)
+#define USB_ADDR_ENDP14_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP14_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP14_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP14_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP14_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP14_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP14_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP14_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP14_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP14_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP14_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP14_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP14_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP14_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP14_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP14_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP14_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP14_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP14_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP14_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP14_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP14_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_ADDR_ENDP15
+// Description : Interrupt endpoint 15. Only valid for HOST mode.
+#define USB_ADDR_ENDP15_OFFSET _u(0x0000003c)
+#define USB_ADDR_ENDP15_BITS _u(0x060f007f)
+#define USB_ADDR_ENDP15_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP15_INTEP_PREAMBLE
+// Description : Interrupt EP requires preamble (is a low speed device on a full
+// speed hub)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_RESET _u(0x0)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_BITS _u(0x04000000)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_MSB _u(26)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_LSB _u(26)
+#define USB_ADDR_ENDP15_INTEP_PREAMBLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP15_INTEP_DIR
+// Description : Direction of the interrupt endpoint. In=0, Out=1
+#define USB_ADDR_ENDP15_INTEP_DIR_RESET _u(0x0)
+#define USB_ADDR_ENDP15_INTEP_DIR_BITS _u(0x02000000)
+#define USB_ADDR_ENDP15_INTEP_DIR_MSB _u(25)
+#define USB_ADDR_ENDP15_INTEP_DIR_LSB _u(25)
+#define USB_ADDR_ENDP15_INTEP_DIR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP15_ENDPOINT
+// Description : Endpoint number of the interrupt endpoint
+#define USB_ADDR_ENDP15_ENDPOINT_RESET _u(0x0)
+#define USB_ADDR_ENDP15_ENDPOINT_BITS _u(0x000f0000)
+#define USB_ADDR_ENDP15_ENDPOINT_MSB _u(19)
+#define USB_ADDR_ENDP15_ENDPOINT_LSB _u(16)
+#define USB_ADDR_ENDP15_ENDPOINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_ADDR_ENDP15_ADDRESS
+// Description : Device address
+#define USB_ADDR_ENDP15_ADDRESS_RESET _u(0x00)
+#define USB_ADDR_ENDP15_ADDRESS_BITS _u(0x0000007f)
+#define USB_ADDR_ENDP15_ADDRESS_MSB _u(6)
+#define USB_ADDR_ENDP15_ADDRESS_LSB _u(0)
+#define USB_ADDR_ENDP15_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_MAIN_CTRL
+// Description : Main control register
+#define USB_MAIN_CTRL_OFFSET _u(0x00000040)
+#define USB_MAIN_CTRL_BITS _u(0x80000003)
+#define USB_MAIN_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_MAIN_CTRL_SIM_TIMING
+// Description : Reduced timings for simulation
+#define USB_MAIN_CTRL_SIM_TIMING_RESET _u(0x0)
+#define USB_MAIN_CTRL_SIM_TIMING_BITS _u(0x80000000)
+#define USB_MAIN_CTRL_SIM_TIMING_MSB _u(31)
+#define USB_MAIN_CTRL_SIM_TIMING_LSB _u(31)
+#define USB_MAIN_CTRL_SIM_TIMING_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_MAIN_CTRL_HOST_NDEVICE
+// Description : Device mode = 0, Host mode = 1
+#define USB_MAIN_CTRL_HOST_NDEVICE_RESET _u(0x0)
+#define USB_MAIN_CTRL_HOST_NDEVICE_BITS _u(0x00000002)
+#define USB_MAIN_CTRL_HOST_NDEVICE_MSB _u(1)
+#define USB_MAIN_CTRL_HOST_NDEVICE_LSB _u(1)
+#define USB_MAIN_CTRL_HOST_NDEVICE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_MAIN_CTRL_CONTROLLER_EN
+// Description : Enable controller
+#define USB_MAIN_CTRL_CONTROLLER_EN_RESET _u(0x0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_BITS _u(0x00000001)
+#define USB_MAIN_CTRL_CONTROLLER_EN_MSB _u(0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_LSB _u(0)
+#define USB_MAIN_CTRL_CONTROLLER_EN_ACCESS "RW"
+// =============================================================================
+// Register : USB_SOF_WR
+// Description : Set the SOF (Start of Frame) frame number in the host
+// controller. The SOF packet is sent every 1ms and the host will
+// increment the frame number by 1 each time.
+#define USB_SOF_WR_OFFSET _u(0x00000044)
+#define USB_SOF_WR_BITS _u(0x000007ff)
+#define USB_SOF_WR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_SOF_WR_COUNT
+// Description : None
+#define USB_SOF_WR_COUNT_RESET _u(0x000)
+#define USB_SOF_WR_COUNT_BITS _u(0x000007ff)
+#define USB_SOF_WR_COUNT_MSB _u(10)
+#define USB_SOF_WR_COUNT_LSB _u(0)
+#define USB_SOF_WR_COUNT_ACCESS "WF"
+// =============================================================================
+// Register : USB_SOF_RD
+// Description : Read the last SOF (Start of Frame) frame number seen. In device
+// mode the last SOF received from the host. In host mode the last
+// SOF sent by the host.
+#define USB_SOF_RD_OFFSET _u(0x00000048)
+#define USB_SOF_RD_BITS _u(0x000007ff)
+#define USB_SOF_RD_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_SOF_RD_COUNT
+// Description : None
+#define USB_SOF_RD_COUNT_RESET _u(0x000)
+#define USB_SOF_RD_COUNT_BITS _u(0x000007ff)
+#define USB_SOF_RD_COUNT_MSB _u(10)
+#define USB_SOF_RD_COUNT_LSB _u(0)
+#define USB_SOF_RD_COUNT_ACCESS "RO"
+// =============================================================================
+// Register : USB_SIE_CTRL
+// Description : SIE control register
+#define USB_SIE_CTRL_OFFSET _u(0x0000004c)
+#define USB_SIE_CTRL_BITS _u(0xff07bf5f)
+#define USB_SIE_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_EP0_INT_STALL
+// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
+#define USB_SIE_CTRL_EP0_INT_STALL_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_STALL_BITS _u(0x80000000)
+#define USB_SIE_CTRL_EP0_INT_STALL_MSB _u(31)
+#define USB_SIE_CTRL_EP0_INT_STALL_LSB _u(31)
+#define USB_SIE_CTRL_EP0_INT_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_EP0_DOUBLE_BUF
+// Description : Device: EP0 single buffered = 0, double buffered = 1
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_BITS _u(0x40000000)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_MSB _u(30)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_LSB _u(30)
+#define USB_SIE_CTRL_EP0_DOUBLE_BUF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_EP0_INT_1BUF
+// Description : Device: Set bit in BUFF_STATUS for every buffer completed on
+// EP0
+#define USB_SIE_CTRL_EP0_INT_1BUF_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_1BUF_BITS _u(0x20000000)
+#define USB_SIE_CTRL_EP0_INT_1BUF_MSB _u(29)
+#define USB_SIE_CTRL_EP0_INT_1BUF_LSB _u(29)
+#define USB_SIE_CTRL_EP0_INT_1BUF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_EP0_INT_2BUF
+// Description : Device: Set bit in BUFF_STATUS for every 2 buffers completed on
+// EP0
+#define USB_SIE_CTRL_EP0_INT_2BUF_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_2BUF_BITS _u(0x10000000)
+#define USB_SIE_CTRL_EP0_INT_2BUF_MSB _u(28)
+#define USB_SIE_CTRL_EP0_INT_2BUF_LSB _u(28)
+#define USB_SIE_CTRL_EP0_INT_2BUF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_EP0_INT_NAK
+// Description : Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
+#define USB_SIE_CTRL_EP0_INT_NAK_RESET _u(0x0)
+#define USB_SIE_CTRL_EP0_INT_NAK_BITS _u(0x08000000)
+#define USB_SIE_CTRL_EP0_INT_NAK_MSB _u(27)
+#define USB_SIE_CTRL_EP0_INT_NAK_LSB _u(27)
+#define USB_SIE_CTRL_EP0_INT_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_DIRECT_EN
+// Description : Direct bus drive enable
+#define USB_SIE_CTRL_DIRECT_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_DIRECT_EN_BITS _u(0x04000000)
+#define USB_SIE_CTRL_DIRECT_EN_MSB _u(26)
+#define USB_SIE_CTRL_DIRECT_EN_LSB _u(26)
+#define USB_SIE_CTRL_DIRECT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_DIRECT_DP
+// Description : Direct control of DP
+#define USB_SIE_CTRL_DIRECT_DP_RESET _u(0x0)
+#define USB_SIE_CTRL_DIRECT_DP_BITS _u(0x02000000)
+#define USB_SIE_CTRL_DIRECT_DP_MSB _u(25)
+#define USB_SIE_CTRL_DIRECT_DP_LSB _u(25)
+#define USB_SIE_CTRL_DIRECT_DP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_DIRECT_DM
+// Description : Direct control of DM
+#define USB_SIE_CTRL_DIRECT_DM_RESET _u(0x0)
+#define USB_SIE_CTRL_DIRECT_DM_BITS _u(0x01000000)
+#define USB_SIE_CTRL_DIRECT_DM_MSB _u(24)
+#define USB_SIE_CTRL_DIRECT_DM_LSB _u(24)
+#define USB_SIE_CTRL_DIRECT_DM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_TRANSCEIVER_PD
+// Description : Power down bus transceiver
+#define USB_SIE_CTRL_TRANSCEIVER_PD_RESET _u(0x0)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_BITS _u(0x00040000)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_MSB _u(18)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_LSB _u(18)
+#define USB_SIE_CTRL_TRANSCEIVER_PD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_RPU_OPT
+// Description : Device: Pull-up strength (0=1K2, 1=2k3)
+#define USB_SIE_CTRL_RPU_OPT_RESET _u(0x0)
+#define USB_SIE_CTRL_RPU_OPT_BITS _u(0x00020000)
+#define USB_SIE_CTRL_RPU_OPT_MSB _u(17)
+#define USB_SIE_CTRL_RPU_OPT_LSB _u(17)
+#define USB_SIE_CTRL_RPU_OPT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_PULLUP_EN
+// Description : Device: Enable pull up resistor
+#define USB_SIE_CTRL_PULLUP_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_PULLUP_EN_BITS _u(0x00010000)
+#define USB_SIE_CTRL_PULLUP_EN_MSB _u(16)
+#define USB_SIE_CTRL_PULLUP_EN_LSB _u(16)
+#define USB_SIE_CTRL_PULLUP_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_PULLDOWN_EN
+// Description : Host: Enable pull down resistors
+#define USB_SIE_CTRL_PULLDOWN_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_PULLDOWN_EN_BITS _u(0x00008000)
+#define USB_SIE_CTRL_PULLDOWN_EN_MSB _u(15)
+#define USB_SIE_CTRL_PULLDOWN_EN_LSB _u(15)
+#define USB_SIE_CTRL_PULLDOWN_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_RESET_BUS
+// Description : Host: Reset bus
+#define USB_SIE_CTRL_RESET_BUS_RESET _u(0x0)
+#define USB_SIE_CTRL_RESET_BUS_BITS _u(0x00002000)
+#define USB_SIE_CTRL_RESET_BUS_MSB _u(13)
+#define USB_SIE_CTRL_RESET_BUS_LSB _u(13)
+#define USB_SIE_CTRL_RESET_BUS_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_RESUME
+// Description : Device: Remote wakeup. Device can initiate its own resume after
+// suspend.
+#define USB_SIE_CTRL_RESUME_RESET _u(0x0)
+#define USB_SIE_CTRL_RESUME_BITS _u(0x00001000)
+#define USB_SIE_CTRL_RESUME_MSB _u(12)
+#define USB_SIE_CTRL_RESUME_LSB _u(12)
+#define USB_SIE_CTRL_RESUME_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_VBUS_EN
+// Description : Host: Enable VBUS
+#define USB_SIE_CTRL_VBUS_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_VBUS_EN_BITS _u(0x00000800)
+#define USB_SIE_CTRL_VBUS_EN_MSB _u(11)
+#define USB_SIE_CTRL_VBUS_EN_LSB _u(11)
+#define USB_SIE_CTRL_VBUS_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_KEEP_ALIVE_EN
+// Description : Host: Enable keep alive packet (for low speed bus)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_BITS _u(0x00000400)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_MSB _u(10)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_LSB _u(10)
+#define USB_SIE_CTRL_KEEP_ALIVE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_SOF_EN
+// Description : Host: Enable SOF generation (for full speed bus)
+#define USB_SIE_CTRL_SOF_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_SOF_EN_BITS _u(0x00000200)
+#define USB_SIE_CTRL_SOF_EN_MSB _u(9)
+#define USB_SIE_CTRL_SOF_EN_LSB _u(9)
+#define USB_SIE_CTRL_SOF_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_SOF_SYNC
+// Description : Host: Delay packet(s) until after SOF
+#define USB_SIE_CTRL_SOF_SYNC_RESET _u(0x0)
+#define USB_SIE_CTRL_SOF_SYNC_BITS _u(0x00000100)
+#define USB_SIE_CTRL_SOF_SYNC_MSB _u(8)
+#define USB_SIE_CTRL_SOF_SYNC_LSB _u(8)
+#define USB_SIE_CTRL_SOF_SYNC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_PREAMBLE_EN
+// Description : Host: Preable enable for LS device on FS hub
+#define USB_SIE_CTRL_PREAMBLE_EN_RESET _u(0x0)
+#define USB_SIE_CTRL_PREAMBLE_EN_BITS _u(0x00000040)
+#define USB_SIE_CTRL_PREAMBLE_EN_MSB _u(6)
+#define USB_SIE_CTRL_PREAMBLE_EN_LSB _u(6)
+#define USB_SIE_CTRL_PREAMBLE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_STOP_TRANS
+// Description : Host: Stop transaction
+#define USB_SIE_CTRL_STOP_TRANS_RESET _u(0x0)
+#define USB_SIE_CTRL_STOP_TRANS_BITS _u(0x00000010)
+#define USB_SIE_CTRL_STOP_TRANS_MSB _u(4)
+#define USB_SIE_CTRL_STOP_TRANS_LSB _u(4)
+#define USB_SIE_CTRL_STOP_TRANS_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_RECEIVE_DATA
+// Description : Host: Receive transaction (IN to host)
+#define USB_SIE_CTRL_RECEIVE_DATA_RESET _u(0x0)
+#define USB_SIE_CTRL_RECEIVE_DATA_BITS _u(0x00000008)
+#define USB_SIE_CTRL_RECEIVE_DATA_MSB _u(3)
+#define USB_SIE_CTRL_RECEIVE_DATA_LSB _u(3)
+#define USB_SIE_CTRL_RECEIVE_DATA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_SEND_DATA
+// Description : Host: Send transaction (OUT from host)
+#define USB_SIE_CTRL_SEND_DATA_RESET _u(0x0)
+#define USB_SIE_CTRL_SEND_DATA_BITS _u(0x00000004)
+#define USB_SIE_CTRL_SEND_DATA_MSB _u(2)
+#define USB_SIE_CTRL_SEND_DATA_LSB _u(2)
+#define USB_SIE_CTRL_SEND_DATA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_SEND_SETUP
+// Description : Host: Send Setup packet
+#define USB_SIE_CTRL_SEND_SETUP_RESET _u(0x0)
+#define USB_SIE_CTRL_SEND_SETUP_BITS _u(0x00000002)
+#define USB_SIE_CTRL_SEND_SETUP_MSB _u(1)
+#define USB_SIE_CTRL_SEND_SETUP_LSB _u(1)
+#define USB_SIE_CTRL_SEND_SETUP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_CTRL_START_TRANS
+// Description : Host: Start transaction
+#define USB_SIE_CTRL_START_TRANS_RESET _u(0x0)
+#define USB_SIE_CTRL_START_TRANS_BITS _u(0x00000001)
+#define USB_SIE_CTRL_START_TRANS_MSB _u(0)
+#define USB_SIE_CTRL_START_TRANS_LSB _u(0)
+#define USB_SIE_CTRL_START_TRANS_ACCESS "SC"
+// =============================================================================
+// Register : USB_SIE_STATUS
+// Description : SIE status register
+#define USB_SIE_STATUS_OFFSET _u(0x00000050)
+#define USB_SIE_STATUS_BITS _u(0xff0f0f1d)
+#define USB_SIE_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_DATA_SEQ_ERROR
+// Description : Data Sequence Error.
+//
+// The device can raise a sequence error in the following
+// conditions:
+//
+// * A SETUP packet is received followed by a DATA1 packet (data
+// phase should always be DATA0) * An OUT packet is received from
+// the host but doesn't match the data pid in the buffer control
+// register read from DPSRAM
+//
+// The host can raise a data sequence error in the following
+// conditions:
+//
+// * An IN packet from the device has the wrong data PID
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_RESET _u(0x0)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_BITS _u(0x80000000)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_MSB _u(31)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_LSB _u(31)
+#define USB_SIE_STATUS_DATA_SEQ_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_ACK_REC
+// Description : ACK received. Raised by both host and device.
+#define USB_SIE_STATUS_ACK_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_ACK_REC_BITS _u(0x40000000)
+#define USB_SIE_STATUS_ACK_REC_MSB _u(30)
+#define USB_SIE_STATUS_ACK_REC_LSB _u(30)
+#define USB_SIE_STATUS_ACK_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_STALL_REC
+// Description : Host: STALL received
+#define USB_SIE_STATUS_STALL_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_STALL_REC_BITS _u(0x20000000)
+#define USB_SIE_STATUS_STALL_REC_MSB _u(29)
+#define USB_SIE_STATUS_STALL_REC_LSB _u(29)
+#define USB_SIE_STATUS_STALL_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_NAK_REC
+// Description : Host: NAK received
+#define USB_SIE_STATUS_NAK_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_NAK_REC_BITS _u(0x10000000)
+#define USB_SIE_STATUS_NAK_REC_MSB _u(28)
+#define USB_SIE_STATUS_NAK_REC_LSB _u(28)
+#define USB_SIE_STATUS_NAK_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_RX_TIMEOUT
+// Description : RX timeout is raised by both the host and device if an ACK is
+// not received in the maximum time specified by the USB spec.
+#define USB_SIE_STATUS_RX_TIMEOUT_RESET _u(0x0)
+#define USB_SIE_STATUS_RX_TIMEOUT_BITS _u(0x08000000)
+#define USB_SIE_STATUS_RX_TIMEOUT_MSB _u(27)
+#define USB_SIE_STATUS_RX_TIMEOUT_LSB _u(27)
+#define USB_SIE_STATUS_RX_TIMEOUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_RX_OVERFLOW
+// Description : RX overflow is raised by the Serial RX engine if the incoming
+// data is too fast.
+#define USB_SIE_STATUS_RX_OVERFLOW_RESET _u(0x0)
+#define USB_SIE_STATUS_RX_OVERFLOW_BITS _u(0x04000000)
+#define USB_SIE_STATUS_RX_OVERFLOW_MSB _u(26)
+#define USB_SIE_STATUS_RX_OVERFLOW_LSB _u(26)
+#define USB_SIE_STATUS_RX_OVERFLOW_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_BIT_STUFF_ERROR
+// Description : Bit Stuff Error. Raised by the Serial RX engine.
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_RESET _u(0x0)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_BITS _u(0x02000000)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_MSB _u(25)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_LSB _u(25)
+#define USB_SIE_STATUS_BIT_STUFF_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_CRC_ERROR
+// Description : CRC Error. Raised by the Serial RX engine.
+#define USB_SIE_STATUS_CRC_ERROR_RESET _u(0x0)
+#define USB_SIE_STATUS_CRC_ERROR_BITS _u(0x01000000)
+#define USB_SIE_STATUS_CRC_ERROR_MSB _u(24)
+#define USB_SIE_STATUS_CRC_ERROR_LSB _u(24)
+#define USB_SIE_STATUS_CRC_ERROR_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_BUS_RESET
+// Description : Device: bus reset received
+#define USB_SIE_STATUS_BUS_RESET_RESET _u(0x0)
+#define USB_SIE_STATUS_BUS_RESET_BITS _u(0x00080000)
+#define USB_SIE_STATUS_BUS_RESET_MSB _u(19)
+#define USB_SIE_STATUS_BUS_RESET_LSB _u(19)
+#define USB_SIE_STATUS_BUS_RESET_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_TRANS_COMPLETE
+// Description : Transaction complete.
+//
+// Raised by device if:
+//
+// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in
+// the buffer control register
+//
+// Raised by host if:
+//
+// * A setup packet is sent when no data in or data out
+// transaction follows * An IN packet is received and the
+// `LAST_BUFF` bit is set in the buffer control register * An IN
+// packet is received with zero length * An OUT packet is sent and
+// the `LAST_BUFF` bit is set
+#define USB_SIE_STATUS_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_SIE_STATUS_TRANS_COMPLETE_BITS _u(0x00040000)
+#define USB_SIE_STATUS_TRANS_COMPLETE_MSB _u(18)
+#define USB_SIE_STATUS_TRANS_COMPLETE_LSB _u(18)
+#define USB_SIE_STATUS_TRANS_COMPLETE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_SETUP_REC
+// Description : Device: Setup packet received
+#define USB_SIE_STATUS_SETUP_REC_RESET _u(0x0)
+#define USB_SIE_STATUS_SETUP_REC_BITS _u(0x00020000)
+#define USB_SIE_STATUS_SETUP_REC_MSB _u(17)
+#define USB_SIE_STATUS_SETUP_REC_LSB _u(17)
+#define USB_SIE_STATUS_SETUP_REC_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_CONNECTED
+// Description : Device: connected
+#define USB_SIE_STATUS_CONNECTED_RESET _u(0x0)
+#define USB_SIE_STATUS_CONNECTED_BITS _u(0x00010000)
+#define USB_SIE_STATUS_CONNECTED_MSB _u(16)
+#define USB_SIE_STATUS_CONNECTED_LSB _u(16)
+#define USB_SIE_STATUS_CONNECTED_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_RESUME
+// Description : Host: Device has initiated a remote resume. Device: host has
+// initiated a resume.
+#define USB_SIE_STATUS_RESUME_RESET _u(0x0)
+#define USB_SIE_STATUS_RESUME_BITS _u(0x00000800)
+#define USB_SIE_STATUS_RESUME_MSB _u(11)
+#define USB_SIE_STATUS_RESUME_LSB _u(11)
+#define USB_SIE_STATUS_RESUME_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_VBUS_OVER_CURR
+// Description : VBUS over current detected
+#define USB_SIE_STATUS_VBUS_OVER_CURR_RESET _u(0x0)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_BITS _u(0x00000400)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_MSB _u(10)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_LSB _u(10)
+#define USB_SIE_STATUS_VBUS_OVER_CURR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_SPEED
+// Description : Host: device speed. Disconnected = 00, LS = 01, FS = 10
+#define USB_SIE_STATUS_SPEED_RESET _u(0x0)
+#define USB_SIE_STATUS_SPEED_BITS _u(0x00000300)
+#define USB_SIE_STATUS_SPEED_MSB _u(9)
+#define USB_SIE_STATUS_SPEED_LSB _u(8)
+#define USB_SIE_STATUS_SPEED_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_SUSPENDED
+// Description : Bus in suspended state. Valid for device and host. Host and
+// device will go into suspend if neither Keep Alive / SOF frames
+// are enabled.
+#define USB_SIE_STATUS_SUSPENDED_RESET _u(0x0)
+#define USB_SIE_STATUS_SUSPENDED_BITS _u(0x00000010)
+#define USB_SIE_STATUS_SUSPENDED_MSB _u(4)
+#define USB_SIE_STATUS_SUSPENDED_LSB _u(4)
+#define USB_SIE_STATUS_SUSPENDED_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_LINE_STATE
+// Description : USB bus line state
+#define USB_SIE_STATUS_LINE_STATE_RESET _u(0x0)
+#define USB_SIE_STATUS_LINE_STATE_BITS _u(0x0000000c)
+#define USB_SIE_STATUS_LINE_STATE_MSB _u(3)
+#define USB_SIE_STATUS_LINE_STATE_LSB _u(2)
+#define USB_SIE_STATUS_LINE_STATE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_SIE_STATUS_VBUS_DETECTED
+// Description : Device: VBUS Detected
+#define USB_SIE_STATUS_VBUS_DETECTED_RESET _u(0x0)
+#define USB_SIE_STATUS_VBUS_DETECTED_BITS _u(0x00000001)
+#define USB_SIE_STATUS_VBUS_DETECTED_MSB _u(0)
+#define USB_SIE_STATUS_VBUS_DETECTED_LSB _u(0)
+#define USB_SIE_STATUS_VBUS_DETECTED_ACCESS "RO"
+// =============================================================================
+// Register : USB_INT_EP_CTRL
+// Description : interrupt endpoint control register
+#define USB_INT_EP_CTRL_OFFSET _u(0x00000054)
+#define USB_INT_EP_CTRL_BITS _u(0x0000fffe)
+#define USB_INT_EP_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_INT_EP_CTRL_INT_EP_ACTIVE
+// Description : Host: Enable interrupt endpoint 1 -> 15
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_RESET _u(0x0000)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_BITS _u(0x0000fffe)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_MSB _u(15)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_LSB _u(1)
+#define USB_INT_EP_CTRL_INT_EP_ACTIVE_ACCESS "RW"
+// =============================================================================
+// Register : USB_BUFF_STATUS
+// Description : Buffer status register. A bit set here indicates that a buffer
+// has completed on the endpoint (if the buffer interrupt is
+// enabled). It is possible for 2 buffers to be completed, so
+// clearing the buffer status bit may instantly re set it on the
+// next clock cycle.
+#define USB_BUFF_STATUS_OFFSET _u(0x00000058)
+#define USB_BUFF_STATUS_BITS _u(0xffffffff)
+#define USB_BUFF_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP15_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP15_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP15_OUT_BITS _u(0x80000000)
+#define USB_BUFF_STATUS_EP15_OUT_MSB _u(31)
+#define USB_BUFF_STATUS_EP15_OUT_LSB _u(31)
+#define USB_BUFF_STATUS_EP15_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP15_IN
+// Description : None
+#define USB_BUFF_STATUS_EP15_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP15_IN_BITS _u(0x40000000)
+#define USB_BUFF_STATUS_EP15_IN_MSB _u(30)
+#define USB_BUFF_STATUS_EP15_IN_LSB _u(30)
+#define USB_BUFF_STATUS_EP15_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP14_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP14_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP14_OUT_BITS _u(0x20000000)
+#define USB_BUFF_STATUS_EP14_OUT_MSB _u(29)
+#define USB_BUFF_STATUS_EP14_OUT_LSB _u(29)
+#define USB_BUFF_STATUS_EP14_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP14_IN
+// Description : None
+#define USB_BUFF_STATUS_EP14_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP14_IN_BITS _u(0x10000000)
+#define USB_BUFF_STATUS_EP14_IN_MSB _u(28)
+#define USB_BUFF_STATUS_EP14_IN_LSB _u(28)
+#define USB_BUFF_STATUS_EP14_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP13_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP13_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP13_OUT_BITS _u(0x08000000)
+#define USB_BUFF_STATUS_EP13_OUT_MSB _u(27)
+#define USB_BUFF_STATUS_EP13_OUT_LSB _u(27)
+#define USB_BUFF_STATUS_EP13_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP13_IN
+// Description : None
+#define USB_BUFF_STATUS_EP13_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP13_IN_BITS _u(0x04000000)
+#define USB_BUFF_STATUS_EP13_IN_MSB _u(26)
+#define USB_BUFF_STATUS_EP13_IN_LSB _u(26)
+#define USB_BUFF_STATUS_EP13_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP12_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP12_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP12_OUT_BITS _u(0x02000000)
+#define USB_BUFF_STATUS_EP12_OUT_MSB _u(25)
+#define USB_BUFF_STATUS_EP12_OUT_LSB _u(25)
+#define USB_BUFF_STATUS_EP12_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP12_IN
+// Description : None
+#define USB_BUFF_STATUS_EP12_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP12_IN_BITS _u(0x01000000)
+#define USB_BUFF_STATUS_EP12_IN_MSB _u(24)
+#define USB_BUFF_STATUS_EP12_IN_LSB _u(24)
+#define USB_BUFF_STATUS_EP12_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP11_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP11_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP11_OUT_BITS _u(0x00800000)
+#define USB_BUFF_STATUS_EP11_OUT_MSB _u(23)
+#define USB_BUFF_STATUS_EP11_OUT_LSB _u(23)
+#define USB_BUFF_STATUS_EP11_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP11_IN
+// Description : None
+#define USB_BUFF_STATUS_EP11_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP11_IN_BITS _u(0x00400000)
+#define USB_BUFF_STATUS_EP11_IN_MSB _u(22)
+#define USB_BUFF_STATUS_EP11_IN_LSB _u(22)
+#define USB_BUFF_STATUS_EP11_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP10_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP10_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP10_OUT_BITS _u(0x00200000)
+#define USB_BUFF_STATUS_EP10_OUT_MSB _u(21)
+#define USB_BUFF_STATUS_EP10_OUT_LSB _u(21)
+#define USB_BUFF_STATUS_EP10_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP10_IN
+// Description : None
+#define USB_BUFF_STATUS_EP10_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP10_IN_BITS _u(0x00100000)
+#define USB_BUFF_STATUS_EP10_IN_MSB _u(20)
+#define USB_BUFF_STATUS_EP10_IN_LSB _u(20)
+#define USB_BUFF_STATUS_EP10_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP9_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP9_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP9_OUT_BITS _u(0x00080000)
+#define USB_BUFF_STATUS_EP9_OUT_MSB _u(19)
+#define USB_BUFF_STATUS_EP9_OUT_LSB _u(19)
+#define USB_BUFF_STATUS_EP9_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP9_IN
+// Description : None
+#define USB_BUFF_STATUS_EP9_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP9_IN_BITS _u(0x00040000)
+#define USB_BUFF_STATUS_EP9_IN_MSB _u(18)
+#define USB_BUFF_STATUS_EP9_IN_LSB _u(18)
+#define USB_BUFF_STATUS_EP9_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP8_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP8_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP8_OUT_BITS _u(0x00020000)
+#define USB_BUFF_STATUS_EP8_OUT_MSB _u(17)
+#define USB_BUFF_STATUS_EP8_OUT_LSB _u(17)
+#define USB_BUFF_STATUS_EP8_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP8_IN
+// Description : None
+#define USB_BUFF_STATUS_EP8_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP8_IN_BITS _u(0x00010000)
+#define USB_BUFF_STATUS_EP8_IN_MSB _u(16)
+#define USB_BUFF_STATUS_EP8_IN_LSB _u(16)
+#define USB_BUFF_STATUS_EP8_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP7_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP7_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP7_OUT_BITS _u(0x00008000)
+#define USB_BUFF_STATUS_EP7_OUT_MSB _u(15)
+#define USB_BUFF_STATUS_EP7_OUT_LSB _u(15)
+#define USB_BUFF_STATUS_EP7_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP7_IN
+// Description : None
+#define USB_BUFF_STATUS_EP7_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP7_IN_BITS _u(0x00004000)
+#define USB_BUFF_STATUS_EP7_IN_MSB _u(14)
+#define USB_BUFF_STATUS_EP7_IN_LSB _u(14)
+#define USB_BUFF_STATUS_EP7_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP6_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP6_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP6_OUT_BITS _u(0x00002000)
+#define USB_BUFF_STATUS_EP6_OUT_MSB _u(13)
+#define USB_BUFF_STATUS_EP6_OUT_LSB _u(13)
+#define USB_BUFF_STATUS_EP6_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP6_IN
+// Description : None
+#define USB_BUFF_STATUS_EP6_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP6_IN_BITS _u(0x00001000)
+#define USB_BUFF_STATUS_EP6_IN_MSB _u(12)
+#define USB_BUFF_STATUS_EP6_IN_LSB _u(12)
+#define USB_BUFF_STATUS_EP6_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP5_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP5_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP5_OUT_BITS _u(0x00000800)
+#define USB_BUFF_STATUS_EP5_OUT_MSB _u(11)
+#define USB_BUFF_STATUS_EP5_OUT_LSB _u(11)
+#define USB_BUFF_STATUS_EP5_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP5_IN
+// Description : None
+#define USB_BUFF_STATUS_EP5_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP5_IN_BITS _u(0x00000400)
+#define USB_BUFF_STATUS_EP5_IN_MSB _u(10)
+#define USB_BUFF_STATUS_EP5_IN_LSB _u(10)
+#define USB_BUFF_STATUS_EP5_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP4_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP4_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP4_OUT_BITS _u(0x00000200)
+#define USB_BUFF_STATUS_EP4_OUT_MSB _u(9)
+#define USB_BUFF_STATUS_EP4_OUT_LSB _u(9)
+#define USB_BUFF_STATUS_EP4_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP4_IN
+// Description : None
+#define USB_BUFF_STATUS_EP4_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP4_IN_BITS _u(0x00000100)
+#define USB_BUFF_STATUS_EP4_IN_MSB _u(8)
+#define USB_BUFF_STATUS_EP4_IN_LSB _u(8)
+#define USB_BUFF_STATUS_EP4_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP3_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP3_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP3_OUT_BITS _u(0x00000080)
+#define USB_BUFF_STATUS_EP3_OUT_MSB _u(7)
+#define USB_BUFF_STATUS_EP3_OUT_LSB _u(7)
+#define USB_BUFF_STATUS_EP3_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP3_IN
+// Description : None
+#define USB_BUFF_STATUS_EP3_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP3_IN_BITS _u(0x00000040)
+#define USB_BUFF_STATUS_EP3_IN_MSB _u(6)
+#define USB_BUFF_STATUS_EP3_IN_LSB _u(6)
+#define USB_BUFF_STATUS_EP3_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP2_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP2_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP2_OUT_BITS _u(0x00000020)
+#define USB_BUFF_STATUS_EP2_OUT_MSB _u(5)
+#define USB_BUFF_STATUS_EP2_OUT_LSB _u(5)
+#define USB_BUFF_STATUS_EP2_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP2_IN
+// Description : None
+#define USB_BUFF_STATUS_EP2_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP2_IN_BITS _u(0x00000010)
+#define USB_BUFF_STATUS_EP2_IN_MSB _u(4)
+#define USB_BUFF_STATUS_EP2_IN_LSB _u(4)
+#define USB_BUFF_STATUS_EP2_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP1_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP1_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP1_OUT_BITS _u(0x00000008)
+#define USB_BUFF_STATUS_EP1_OUT_MSB _u(3)
+#define USB_BUFF_STATUS_EP1_OUT_LSB _u(3)
+#define USB_BUFF_STATUS_EP1_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP1_IN
+// Description : None
+#define USB_BUFF_STATUS_EP1_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP1_IN_BITS _u(0x00000004)
+#define USB_BUFF_STATUS_EP1_IN_MSB _u(2)
+#define USB_BUFF_STATUS_EP1_IN_LSB _u(2)
+#define USB_BUFF_STATUS_EP1_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP0_OUT
+// Description : None
+#define USB_BUFF_STATUS_EP0_OUT_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP0_OUT_BITS _u(0x00000002)
+#define USB_BUFF_STATUS_EP0_OUT_MSB _u(1)
+#define USB_BUFF_STATUS_EP0_OUT_LSB _u(1)
+#define USB_BUFF_STATUS_EP0_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_STATUS_EP0_IN
+// Description : None
+#define USB_BUFF_STATUS_EP0_IN_RESET _u(0x0)
+#define USB_BUFF_STATUS_EP0_IN_BITS _u(0x00000001)
+#define USB_BUFF_STATUS_EP0_IN_MSB _u(0)
+#define USB_BUFF_STATUS_EP0_IN_LSB _u(0)
+#define USB_BUFF_STATUS_EP0_IN_ACCESS "WC"
+// =============================================================================
+// Register : USB_BUFF_CPU_SHOULD_HANDLE
+// Description : Which of the double buffers should be handled. Only valid if
+// using an interrupt per buffer (i.e. not per 2 buffers). Not
+// valid for host interrupt endpoint polling because they are only
+// single buffered.
+#define USB_BUFF_CPU_SHOULD_HANDLE_OFFSET _u(0x0000005c)
+#define USB_BUFF_CPU_SHOULD_HANDLE_BITS _u(0xffffffff)
+#define USB_BUFF_CPU_SHOULD_HANDLE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_BITS _u(0x80000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_MSB _u(31)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_LSB _u(31)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_BITS _u(0x40000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_MSB _u(30)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_LSB _u(30)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP15_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_BITS _u(0x20000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_MSB _u(29)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_LSB _u(29)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_BITS _u(0x10000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_MSB _u(28)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_LSB _u(28)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP14_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_BITS _u(0x08000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_MSB _u(27)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_LSB _u(27)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_BITS _u(0x04000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_MSB _u(26)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_LSB _u(26)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP13_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_BITS _u(0x02000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_MSB _u(25)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_LSB _u(25)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_BITS _u(0x01000000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_MSB _u(24)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_LSB _u(24)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP12_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_BITS _u(0x00800000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_MSB _u(23)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_LSB _u(23)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_BITS _u(0x00400000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_MSB _u(22)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_LSB _u(22)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP11_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_BITS _u(0x00200000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_MSB _u(21)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_LSB _u(21)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_BITS _u(0x00100000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_MSB _u(20)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_LSB _u(20)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP10_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_BITS _u(0x00080000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_MSB _u(19)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_LSB _u(19)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_BITS _u(0x00040000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_MSB _u(18)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_LSB _u(18)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP9_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_BITS _u(0x00020000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_MSB _u(17)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_LSB _u(17)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_BITS _u(0x00010000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_MSB _u(16)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_LSB _u(16)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP8_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_BITS _u(0x00008000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_MSB _u(15)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_LSB _u(15)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_BITS _u(0x00004000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_MSB _u(14)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_LSB _u(14)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP7_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_BITS _u(0x00002000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_MSB _u(13)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_LSB _u(13)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_BITS _u(0x00001000)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_MSB _u(12)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_LSB _u(12)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP6_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_BITS _u(0x00000800)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_MSB _u(11)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_LSB _u(11)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_BITS _u(0x00000400)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_MSB _u(10)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_LSB _u(10)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP5_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_BITS _u(0x00000200)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_MSB _u(9)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_LSB _u(9)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_BITS _u(0x00000100)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_MSB _u(8)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_LSB _u(8)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP4_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_BITS _u(0x00000080)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_MSB _u(7)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_LSB _u(7)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_BITS _u(0x00000040)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_MSB _u(6)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_LSB _u(6)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP3_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_BITS _u(0x00000020)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_MSB _u(5)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_LSB _u(5)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_BITS _u(0x00000010)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_MSB _u(4)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_LSB _u(4)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP2_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_BITS _u(0x00000008)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_MSB _u(3)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_LSB _u(3)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_BITS _u(0x00000004)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_MSB _u(2)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_LSB _u(2)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP1_IN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_BITS _u(0x00000002)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_MSB _u(1)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_LSB _u(1)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_OUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN
+// Description : None
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_RESET _u(0x0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_BITS _u(0x00000001)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_MSB _u(0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_LSB _u(0)
+#define USB_BUFF_CPU_SHOULD_HANDLE_EP0_IN_ACCESS "RO"
+// =============================================================================
+// Register : USB_EP_ABORT
+// Description : Device only: Can be set to ignore the buffer control register
+// for this endpoint in case you would like to revoke a buffer. A
+// NAK will be sent for every access to the endpoint until this
+// bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set
+// when it is safe to modify the buffer control register.
+#define USB_EP_ABORT_OFFSET _u(0x00000060)
+#define USB_EP_ABORT_BITS _u(0xffffffff)
+#define USB_EP_ABORT_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP15_OUT
+// Description : None
+#define USB_EP_ABORT_EP15_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP15_OUT_BITS _u(0x80000000)
+#define USB_EP_ABORT_EP15_OUT_MSB _u(31)
+#define USB_EP_ABORT_EP15_OUT_LSB _u(31)
+#define USB_EP_ABORT_EP15_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP15_IN
+// Description : None
+#define USB_EP_ABORT_EP15_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP15_IN_BITS _u(0x40000000)
+#define USB_EP_ABORT_EP15_IN_MSB _u(30)
+#define USB_EP_ABORT_EP15_IN_LSB _u(30)
+#define USB_EP_ABORT_EP15_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP14_OUT
+// Description : None
+#define USB_EP_ABORT_EP14_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP14_OUT_BITS _u(0x20000000)
+#define USB_EP_ABORT_EP14_OUT_MSB _u(29)
+#define USB_EP_ABORT_EP14_OUT_LSB _u(29)
+#define USB_EP_ABORT_EP14_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP14_IN
+// Description : None
+#define USB_EP_ABORT_EP14_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP14_IN_BITS _u(0x10000000)
+#define USB_EP_ABORT_EP14_IN_MSB _u(28)
+#define USB_EP_ABORT_EP14_IN_LSB _u(28)
+#define USB_EP_ABORT_EP14_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP13_OUT
+// Description : None
+#define USB_EP_ABORT_EP13_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP13_OUT_BITS _u(0x08000000)
+#define USB_EP_ABORT_EP13_OUT_MSB _u(27)
+#define USB_EP_ABORT_EP13_OUT_LSB _u(27)
+#define USB_EP_ABORT_EP13_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP13_IN
+// Description : None
+#define USB_EP_ABORT_EP13_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP13_IN_BITS _u(0x04000000)
+#define USB_EP_ABORT_EP13_IN_MSB _u(26)
+#define USB_EP_ABORT_EP13_IN_LSB _u(26)
+#define USB_EP_ABORT_EP13_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP12_OUT
+// Description : None
+#define USB_EP_ABORT_EP12_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP12_OUT_BITS _u(0x02000000)
+#define USB_EP_ABORT_EP12_OUT_MSB _u(25)
+#define USB_EP_ABORT_EP12_OUT_LSB _u(25)
+#define USB_EP_ABORT_EP12_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP12_IN
+// Description : None
+#define USB_EP_ABORT_EP12_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP12_IN_BITS _u(0x01000000)
+#define USB_EP_ABORT_EP12_IN_MSB _u(24)
+#define USB_EP_ABORT_EP12_IN_LSB _u(24)
+#define USB_EP_ABORT_EP12_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP11_OUT
+// Description : None
+#define USB_EP_ABORT_EP11_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP11_OUT_BITS _u(0x00800000)
+#define USB_EP_ABORT_EP11_OUT_MSB _u(23)
+#define USB_EP_ABORT_EP11_OUT_LSB _u(23)
+#define USB_EP_ABORT_EP11_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP11_IN
+// Description : None
+#define USB_EP_ABORT_EP11_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP11_IN_BITS _u(0x00400000)
+#define USB_EP_ABORT_EP11_IN_MSB _u(22)
+#define USB_EP_ABORT_EP11_IN_LSB _u(22)
+#define USB_EP_ABORT_EP11_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP10_OUT
+// Description : None
+#define USB_EP_ABORT_EP10_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP10_OUT_BITS _u(0x00200000)
+#define USB_EP_ABORT_EP10_OUT_MSB _u(21)
+#define USB_EP_ABORT_EP10_OUT_LSB _u(21)
+#define USB_EP_ABORT_EP10_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP10_IN
+// Description : None
+#define USB_EP_ABORT_EP10_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP10_IN_BITS _u(0x00100000)
+#define USB_EP_ABORT_EP10_IN_MSB _u(20)
+#define USB_EP_ABORT_EP10_IN_LSB _u(20)
+#define USB_EP_ABORT_EP10_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP9_OUT
+// Description : None
+#define USB_EP_ABORT_EP9_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP9_OUT_BITS _u(0x00080000)
+#define USB_EP_ABORT_EP9_OUT_MSB _u(19)
+#define USB_EP_ABORT_EP9_OUT_LSB _u(19)
+#define USB_EP_ABORT_EP9_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP9_IN
+// Description : None
+#define USB_EP_ABORT_EP9_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP9_IN_BITS _u(0x00040000)
+#define USB_EP_ABORT_EP9_IN_MSB _u(18)
+#define USB_EP_ABORT_EP9_IN_LSB _u(18)
+#define USB_EP_ABORT_EP9_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP8_OUT
+// Description : None
+#define USB_EP_ABORT_EP8_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP8_OUT_BITS _u(0x00020000)
+#define USB_EP_ABORT_EP8_OUT_MSB _u(17)
+#define USB_EP_ABORT_EP8_OUT_LSB _u(17)
+#define USB_EP_ABORT_EP8_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP8_IN
+// Description : None
+#define USB_EP_ABORT_EP8_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP8_IN_BITS _u(0x00010000)
+#define USB_EP_ABORT_EP8_IN_MSB _u(16)
+#define USB_EP_ABORT_EP8_IN_LSB _u(16)
+#define USB_EP_ABORT_EP8_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP7_OUT
+// Description : None
+#define USB_EP_ABORT_EP7_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP7_OUT_BITS _u(0x00008000)
+#define USB_EP_ABORT_EP7_OUT_MSB _u(15)
+#define USB_EP_ABORT_EP7_OUT_LSB _u(15)
+#define USB_EP_ABORT_EP7_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP7_IN
+// Description : None
+#define USB_EP_ABORT_EP7_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP7_IN_BITS _u(0x00004000)
+#define USB_EP_ABORT_EP7_IN_MSB _u(14)
+#define USB_EP_ABORT_EP7_IN_LSB _u(14)
+#define USB_EP_ABORT_EP7_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP6_OUT
+// Description : None
+#define USB_EP_ABORT_EP6_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP6_OUT_BITS _u(0x00002000)
+#define USB_EP_ABORT_EP6_OUT_MSB _u(13)
+#define USB_EP_ABORT_EP6_OUT_LSB _u(13)
+#define USB_EP_ABORT_EP6_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP6_IN
+// Description : None
+#define USB_EP_ABORT_EP6_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP6_IN_BITS _u(0x00001000)
+#define USB_EP_ABORT_EP6_IN_MSB _u(12)
+#define USB_EP_ABORT_EP6_IN_LSB _u(12)
+#define USB_EP_ABORT_EP6_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP5_OUT
+// Description : None
+#define USB_EP_ABORT_EP5_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP5_OUT_BITS _u(0x00000800)
+#define USB_EP_ABORT_EP5_OUT_MSB _u(11)
+#define USB_EP_ABORT_EP5_OUT_LSB _u(11)
+#define USB_EP_ABORT_EP5_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP5_IN
+// Description : None
+#define USB_EP_ABORT_EP5_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP5_IN_BITS _u(0x00000400)
+#define USB_EP_ABORT_EP5_IN_MSB _u(10)
+#define USB_EP_ABORT_EP5_IN_LSB _u(10)
+#define USB_EP_ABORT_EP5_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP4_OUT
+// Description : None
+#define USB_EP_ABORT_EP4_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP4_OUT_BITS _u(0x00000200)
+#define USB_EP_ABORT_EP4_OUT_MSB _u(9)
+#define USB_EP_ABORT_EP4_OUT_LSB _u(9)
+#define USB_EP_ABORT_EP4_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP4_IN
+// Description : None
+#define USB_EP_ABORT_EP4_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP4_IN_BITS _u(0x00000100)
+#define USB_EP_ABORT_EP4_IN_MSB _u(8)
+#define USB_EP_ABORT_EP4_IN_LSB _u(8)
+#define USB_EP_ABORT_EP4_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP3_OUT
+// Description : None
+#define USB_EP_ABORT_EP3_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP3_OUT_BITS _u(0x00000080)
+#define USB_EP_ABORT_EP3_OUT_MSB _u(7)
+#define USB_EP_ABORT_EP3_OUT_LSB _u(7)
+#define USB_EP_ABORT_EP3_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP3_IN
+// Description : None
+#define USB_EP_ABORT_EP3_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP3_IN_BITS _u(0x00000040)
+#define USB_EP_ABORT_EP3_IN_MSB _u(6)
+#define USB_EP_ABORT_EP3_IN_LSB _u(6)
+#define USB_EP_ABORT_EP3_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP2_OUT
+// Description : None
+#define USB_EP_ABORT_EP2_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP2_OUT_BITS _u(0x00000020)
+#define USB_EP_ABORT_EP2_OUT_MSB _u(5)
+#define USB_EP_ABORT_EP2_OUT_LSB _u(5)
+#define USB_EP_ABORT_EP2_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP2_IN
+// Description : None
+#define USB_EP_ABORT_EP2_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP2_IN_BITS _u(0x00000010)
+#define USB_EP_ABORT_EP2_IN_MSB _u(4)
+#define USB_EP_ABORT_EP2_IN_LSB _u(4)
+#define USB_EP_ABORT_EP2_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP1_OUT
+// Description : None
+#define USB_EP_ABORT_EP1_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP1_OUT_BITS _u(0x00000008)
+#define USB_EP_ABORT_EP1_OUT_MSB _u(3)
+#define USB_EP_ABORT_EP1_OUT_LSB _u(3)
+#define USB_EP_ABORT_EP1_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP1_IN
+// Description : None
+#define USB_EP_ABORT_EP1_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP1_IN_BITS _u(0x00000004)
+#define USB_EP_ABORT_EP1_IN_MSB _u(2)
+#define USB_EP_ABORT_EP1_IN_LSB _u(2)
+#define USB_EP_ABORT_EP1_IN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP0_OUT
+// Description : None
+#define USB_EP_ABORT_EP0_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_ABORT_EP0_OUT_MSB _u(1)
+#define USB_EP_ABORT_EP0_OUT_LSB _u(1)
+#define USB_EP_ABORT_EP0_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_EP0_IN
+// Description : None
+#define USB_EP_ABORT_EP0_IN_RESET _u(0x0)
+#define USB_EP_ABORT_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_ABORT_EP0_IN_MSB _u(0)
+#define USB_EP_ABORT_EP0_IN_LSB _u(0)
+#define USB_EP_ABORT_EP0_IN_ACCESS "RW"
+// =============================================================================
+// Register : USB_EP_ABORT_DONE
+// Description : Device only: Used in conjunction with `EP_ABORT`. Set once an
+// endpoint is idle so the programmer knows it is safe to modify
+// the buffer control register.
+#define USB_EP_ABORT_DONE_OFFSET _u(0x00000064)
+#define USB_EP_ABORT_DONE_BITS _u(0xffffffff)
+#define USB_EP_ABORT_DONE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP15_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP15_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP15_OUT_BITS _u(0x80000000)
+#define USB_EP_ABORT_DONE_EP15_OUT_MSB _u(31)
+#define USB_EP_ABORT_DONE_EP15_OUT_LSB _u(31)
+#define USB_EP_ABORT_DONE_EP15_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP15_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP15_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP15_IN_BITS _u(0x40000000)
+#define USB_EP_ABORT_DONE_EP15_IN_MSB _u(30)
+#define USB_EP_ABORT_DONE_EP15_IN_LSB _u(30)
+#define USB_EP_ABORT_DONE_EP15_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP14_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP14_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP14_OUT_BITS _u(0x20000000)
+#define USB_EP_ABORT_DONE_EP14_OUT_MSB _u(29)
+#define USB_EP_ABORT_DONE_EP14_OUT_LSB _u(29)
+#define USB_EP_ABORT_DONE_EP14_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP14_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP14_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP14_IN_BITS _u(0x10000000)
+#define USB_EP_ABORT_DONE_EP14_IN_MSB _u(28)
+#define USB_EP_ABORT_DONE_EP14_IN_LSB _u(28)
+#define USB_EP_ABORT_DONE_EP14_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP13_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP13_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP13_OUT_BITS _u(0x08000000)
+#define USB_EP_ABORT_DONE_EP13_OUT_MSB _u(27)
+#define USB_EP_ABORT_DONE_EP13_OUT_LSB _u(27)
+#define USB_EP_ABORT_DONE_EP13_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP13_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP13_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP13_IN_BITS _u(0x04000000)
+#define USB_EP_ABORT_DONE_EP13_IN_MSB _u(26)
+#define USB_EP_ABORT_DONE_EP13_IN_LSB _u(26)
+#define USB_EP_ABORT_DONE_EP13_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP12_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP12_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP12_OUT_BITS _u(0x02000000)
+#define USB_EP_ABORT_DONE_EP12_OUT_MSB _u(25)
+#define USB_EP_ABORT_DONE_EP12_OUT_LSB _u(25)
+#define USB_EP_ABORT_DONE_EP12_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP12_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP12_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP12_IN_BITS _u(0x01000000)
+#define USB_EP_ABORT_DONE_EP12_IN_MSB _u(24)
+#define USB_EP_ABORT_DONE_EP12_IN_LSB _u(24)
+#define USB_EP_ABORT_DONE_EP12_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP11_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP11_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP11_OUT_BITS _u(0x00800000)
+#define USB_EP_ABORT_DONE_EP11_OUT_MSB _u(23)
+#define USB_EP_ABORT_DONE_EP11_OUT_LSB _u(23)
+#define USB_EP_ABORT_DONE_EP11_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP11_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP11_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP11_IN_BITS _u(0x00400000)
+#define USB_EP_ABORT_DONE_EP11_IN_MSB _u(22)
+#define USB_EP_ABORT_DONE_EP11_IN_LSB _u(22)
+#define USB_EP_ABORT_DONE_EP11_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP10_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP10_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP10_OUT_BITS _u(0x00200000)
+#define USB_EP_ABORT_DONE_EP10_OUT_MSB _u(21)
+#define USB_EP_ABORT_DONE_EP10_OUT_LSB _u(21)
+#define USB_EP_ABORT_DONE_EP10_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP10_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP10_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP10_IN_BITS _u(0x00100000)
+#define USB_EP_ABORT_DONE_EP10_IN_MSB _u(20)
+#define USB_EP_ABORT_DONE_EP10_IN_LSB _u(20)
+#define USB_EP_ABORT_DONE_EP10_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP9_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP9_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP9_OUT_BITS _u(0x00080000)
+#define USB_EP_ABORT_DONE_EP9_OUT_MSB _u(19)
+#define USB_EP_ABORT_DONE_EP9_OUT_LSB _u(19)
+#define USB_EP_ABORT_DONE_EP9_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP9_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP9_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP9_IN_BITS _u(0x00040000)
+#define USB_EP_ABORT_DONE_EP9_IN_MSB _u(18)
+#define USB_EP_ABORT_DONE_EP9_IN_LSB _u(18)
+#define USB_EP_ABORT_DONE_EP9_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP8_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP8_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP8_OUT_BITS _u(0x00020000)
+#define USB_EP_ABORT_DONE_EP8_OUT_MSB _u(17)
+#define USB_EP_ABORT_DONE_EP8_OUT_LSB _u(17)
+#define USB_EP_ABORT_DONE_EP8_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP8_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP8_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP8_IN_BITS _u(0x00010000)
+#define USB_EP_ABORT_DONE_EP8_IN_MSB _u(16)
+#define USB_EP_ABORT_DONE_EP8_IN_LSB _u(16)
+#define USB_EP_ABORT_DONE_EP8_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP7_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP7_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP7_OUT_BITS _u(0x00008000)
+#define USB_EP_ABORT_DONE_EP7_OUT_MSB _u(15)
+#define USB_EP_ABORT_DONE_EP7_OUT_LSB _u(15)
+#define USB_EP_ABORT_DONE_EP7_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP7_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP7_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP7_IN_BITS _u(0x00004000)
+#define USB_EP_ABORT_DONE_EP7_IN_MSB _u(14)
+#define USB_EP_ABORT_DONE_EP7_IN_LSB _u(14)
+#define USB_EP_ABORT_DONE_EP7_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP6_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP6_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP6_OUT_BITS _u(0x00002000)
+#define USB_EP_ABORT_DONE_EP6_OUT_MSB _u(13)
+#define USB_EP_ABORT_DONE_EP6_OUT_LSB _u(13)
+#define USB_EP_ABORT_DONE_EP6_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP6_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP6_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP6_IN_BITS _u(0x00001000)
+#define USB_EP_ABORT_DONE_EP6_IN_MSB _u(12)
+#define USB_EP_ABORT_DONE_EP6_IN_LSB _u(12)
+#define USB_EP_ABORT_DONE_EP6_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP5_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP5_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP5_OUT_BITS _u(0x00000800)
+#define USB_EP_ABORT_DONE_EP5_OUT_MSB _u(11)
+#define USB_EP_ABORT_DONE_EP5_OUT_LSB _u(11)
+#define USB_EP_ABORT_DONE_EP5_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP5_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP5_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP5_IN_BITS _u(0x00000400)
+#define USB_EP_ABORT_DONE_EP5_IN_MSB _u(10)
+#define USB_EP_ABORT_DONE_EP5_IN_LSB _u(10)
+#define USB_EP_ABORT_DONE_EP5_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP4_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP4_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP4_OUT_BITS _u(0x00000200)
+#define USB_EP_ABORT_DONE_EP4_OUT_MSB _u(9)
+#define USB_EP_ABORT_DONE_EP4_OUT_LSB _u(9)
+#define USB_EP_ABORT_DONE_EP4_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP4_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP4_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP4_IN_BITS _u(0x00000100)
+#define USB_EP_ABORT_DONE_EP4_IN_MSB _u(8)
+#define USB_EP_ABORT_DONE_EP4_IN_LSB _u(8)
+#define USB_EP_ABORT_DONE_EP4_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP3_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP3_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP3_OUT_BITS _u(0x00000080)
+#define USB_EP_ABORT_DONE_EP3_OUT_MSB _u(7)
+#define USB_EP_ABORT_DONE_EP3_OUT_LSB _u(7)
+#define USB_EP_ABORT_DONE_EP3_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP3_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP3_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP3_IN_BITS _u(0x00000040)
+#define USB_EP_ABORT_DONE_EP3_IN_MSB _u(6)
+#define USB_EP_ABORT_DONE_EP3_IN_LSB _u(6)
+#define USB_EP_ABORT_DONE_EP3_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP2_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP2_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP2_OUT_BITS _u(0x00000020)
+#define USB_EP_ABORT_DONE_EP2_OUT_MSB _u(5)
+#define USB_EP_ABORT_DONE_EP2_OUT_LSB _u(5)
+#define USB_EP_ABORT_DONE_EP2_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP2_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP2_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP2_IN_BITS _u(0x00000010)
+#define USB_EP_ABORT_DONE_EP2_IN_MSB _u(4)
+#define USB_EP_ABORT_DONE_EP2_IN_LSB _u(4)
+#define USB_EP_ABORT_DONE_EP2_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP1_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP1_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP1_OUT_BITS _u(0x00000008)
+#define USB_EP_ABORT_DONE_EP1_OUT_MSB _u(3)
+#define USB_EP_ABORT_DONE_EP1_OUT_LSB _u(3)
+#define USB_EP_ABORT_DONE_EP1_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP1_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP1_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP1_IN_BITS _u(0x00000004)
+#define USB_EP_ABORT_DONE_EP1_IN_MSB _u(2)
+#define USB_EP_ABORT_DONE_EP1_IN_LSB _u(2)
+#define USB_EP_ABORT_DONE_EP1_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP0_OUT
+// Description : None
+#define USB_EP_ABORT_DONE_EP0_OUT_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_ABORT_DONE_EP0_OUT_MSB _u(1)
+#define USB_EP_ABORT_DONE_EP0_OUT_LSB _u(1)
+#define USB_EP_ABORT_DONE_EP0_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_ABORT_DONE_EP0_IN
+// Description : None
+#define USB_EP_ABORT_DONE_EP0_IN_RESET _u(0x0)
+#define USB_EP_ABORT_DONE_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_ABORT_DONE_EP0_IN_MSB _u(0)
+#define USB_EP_ABORT_DONE_EP0_IN_LSB _u(0)
+#define USB_EP_ABORT_DONE_EP0_IN_ACCESS "WC"
+// =============================================================================
+// Register : USB_EP_STALL_ARM
+// Description : Device: this bit must be set in conjunction with the `STALL`
+// bit in the buffer control register to send a STALL on EP0. The
+// device controller clears these bits when a SETUP packet is
+// received because the USB spec requires that a STALL condition
+// is cleared when a SETUP packet is received.
+#define USB_EP_STALL_ARM_OFFSET _u(0x00000068)
+#define USB_EP_STALL_ARM_BITS _u(0x00000003)
+#define USB_EP_STALL_ARM_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STALL_ARM_EP0_OUT
+// Description : None
+#define USB_EP_STALL_ARM_EP0_OUT_RESET _u(0x0)
+#define USB_EP_STALL_ARM_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_STALL_ARM_EP0_OUT_MSB _u(1)
+#define USB_EP_STALL_ARM_EP0_OUT_LSB _u(1)
+#define USB_EP_STALL_ARM_EP0_OUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STALL_ARM_EP0_IN
+// Description : None
+#define USB_EP_STALL_ARM_EP0_IN_RESET _u(0x0)
+#define USB_EP_STALL_ARM_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_STALL_ARM_EP0_IN_MSB _u(0)
+#define USB_EP_STALL_ARM_EP0_IN_LSB _u(0)
+#define USB_EP_STALL_ARM_EP0_IN_ACCESS "RW"
+// =============================================================================
+// Register : USB_NAK_POLL
+// Description : Used by the host controller. Sets the wait time in microseconds
+// before trying again if the device replies with a NAK.
+#define USB_NAK_POLL_OFFSET _u(0x0000006c)
+#define USB_NAK_POLL_BITS _u(0x03ff03ff)
+#define USB_NAK_POLL_RESET _u(0x00100010)
+// -----------------------------------------------------------------------------
+// Field : USB_NAK_POLL_DELAY_FS
+// Description : NAK polling interval for a full speed device
+#define USB_NAK_POLL_DELAY_FS_RESET _u(0x010)
+#define USB_NAK_POLL_DELAY_FS_BITS _u(0x03ff0000)
+#define USB_NAK_POLL_DELAY_FS_MSB _u(25)
+#define USB_NAK_POLL_DELAY_FS_LSB _u(16)
+#define USB_NAK_POLL_DELAY_FS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_NAK_POLL_DELAY_LS
+// Description : NAK polling interval for a low speed device
+#define USB_NAK_POLL_DELAY_LS_RESET _u(0x010)
+#define USB_NAK_POLL_DELAY_LS_BITS _u(0x000003ff)
+#define USB_NAK_POLL_DELAY_LS_MSB _u(9)
+#define USB_NAK_POLL_DELAY_LS_LSB _u(0)
+#define USB_NAK_POLL_DELAY_LS_ACCESS "RW"
+// =============================================================================
+// Register : USB_EP_STATUS_STALL_NAK
+// Description : Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL`
+// bits are set. For EP0 this comes from `SIE_CTRL`. For all other
+// endpoints it comes from the endpoint control register.
+#define USB_EP_STATUS_STALL_NAK_OFFSET _u(0x00000070)
+#define USB_EP_STATUS_STALL_NAK_BITS _u(0xffffffff)
+#define USB_EP_STATUS_STALL_NAK_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP15_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_BITS _u(0x80000000)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_MSB _u(31)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_LSB _u(31)
+#define USB_EP_STATUS_STALL_NAK_EP15_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP15_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_BITS _u(0x40000000)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_MSB _u(30)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_LSB _u(30)
+#define USB_EP_STATUS_STALL_NAK_EP15_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP14_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_BITS _u(0x20000000)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_MSB _u(29)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_LSB _u(29)
+#define USB_EP_STATUS_STALL_NAK_EP14_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP14_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_BITS _u(0x10000000)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_MSB _u(28)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_LSB _u(28)
+#define USB_EP_STATUS_STALL_NAK_EP14_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP13_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_BITS _u(0x08000000)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_MSB _u(27)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_LSB _u(27)
+#define USB_EP_STATUS_STALL_NAK_EP13_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP13_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_BITS _u(0x04000000)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_MSB _u(26)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_LSB _u(26)
+#define USB_EP_STATUS_STALL_NAK_EP13_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP12_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_BITS _u(0x02000000)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_MSB _u(25)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_LSB _u(25)
+#define USB_EP_STATUS_STALL_NAK_EP12_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP12_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_BITS _u(0x01000000)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_MSB _u(24)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_LSB _u(24)
+#define USB_EP_STATUS_STALL_NAK_EP12_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP11_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_BITS _u(0x00800000)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_MSB _u(23)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_LSB _u(23)
+#define USB_EP_STATUS_STALL_NAK_EP11_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP11_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_BITS _u(0x00400000)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_MSB _u(22)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_LSB _u(22)
+#define USB_EP_STATUS_STALL_NAK_EP11_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP10_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_BITS _u(0x00200000)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_MSB _u(21)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_LSB _u(21)
+#define USB_EP_STATUS_STALL_NAK_EP10_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP10_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_BITS _u(0x00100000)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_MSB _u(20)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_LSB _u(20)
+#define USB_EP_STATUS_STALL_NAK_EP10_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP9_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_BITS _u(0x00080000)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_MSB _u(19)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_LSB _u(19)
+#define USB_EP_STATUS_STALL_NAK_EP9_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP9_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_BITS _u(0x00040000)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_MSB _u(18)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_LSB _u(18)
+#define USB_EP_STATUS_STALL_NAK_EP9_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP8_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_BITS _u(0x00020000)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_MSB _u(17)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_LSB _u(17)
+#define USB_EP_STATUS_STALL_NAK_EP8_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP8_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_BITS _u(0x00010000)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_MSB _u(16)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_LSB _u(16)
+#define USB_EP_STATUS_STALL_NAK_EP8_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP7_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_BITS _u(0x00008000)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_MSB _u(15)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_LSB _u(15)
+#define USB_EP_STATUS_STALL_NAK_EP7_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP7_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_BITS _u(0x00004000)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_MSB _u(14)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_LSB _u(14)
+#define USB_EP_STATUS_STALL_NAK_EP7_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP6_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_BITS _u(0x00002000)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_MSB _u(13)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_LSB _u(13)
+#define USB_EP_STATUS_STALL_NAK_EP6_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP6_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_BITS _u(0x00001000)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_MSB _u(12)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_LSB _u(12)
+#define USB_EP_STATUS_STALL_NAK_EP6_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP5_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_BITS _u(0x00000800)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_MSB _u(11)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_LSB _u(11)
+#define USB_EP_STATUS_STALL_NAK_EP5_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP5_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_BITS _u(0x00000400)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_MSB _u(10)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_LSB _u(10)
+#define USB_EP_STATUS_STALL_NAK_EP5_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP4_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_BITS _u(0x00000200)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_MSB _u(9)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_LSB _u(9)
+#define USB_EP_STATUS_STALL_NAK_EP4_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP4_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_BITS _u(0x00000100)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_MSB _u(8)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_LSB _u(8)
+#define USB_EP_STATUS_STALL_NAK_EP4_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP3_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_BITS _u(0x00000080)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_MSB _u(7)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_LSB _u(7)
+#define USB_EP_STATUS_STALL_NAK_EP3_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP3_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_BITS _u(0x00000040)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_MSB _u(6)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_LSB _u(6)
+#define USB_EP_STATUS_STALL_NAK_EP3_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP2_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_BITS _u(0x00000020)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_MSB _u(5)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_LSB _u(5)
+#define USB_EP_STATUS_STALL_NAK_EP2_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP2_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_BITS _u(0x00000010)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_MSB _u(4)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_LSB _u(4)
+#define USB_EP_STATUS_STALL_NAK_EP2_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP1_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_BITS _u(0x00000008)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_MSB _u(3)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_LSB _u(3)
+#define USB_EP_STATUS_STALL_NAK_EP1_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP1_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_BITS _u(0x00000004)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_MSB _u(2)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_LSB _u(2)
+#define USB_EP_STATUS_STALL_NAK_EP1_IN_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP0_OUT
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_BITS _u(0x00000002)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_MSB _u(1)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_LSB _u(1)
+#define USB_EP_STATUS_STALL_NAK_EP0_OUT_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : USB_EP_STATUS_STALL_NAK_EP0_IN
+// Description : None
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_RESET _u(0x0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_BITS _u(0x00000001)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_MSB _u(0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_LSB _u(0)
+#define USB_EP_STATUS_STALL_NAK_EP0_IN_ACCESS "WC"
+// =============================================================================
+// Register : USB_USB_MUXING
+// Description : Where to connect the USB controller. Should be to_phy by
+// default.
+#define USB_USB_MUXING_OFFSET _u(0x00000074)
+#define USB_USB_MUXING_BITS _u(0x0000000f)
+#define USB_USB_MUXING_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_USB_MUXING_SOFTCON
+// Description : None
+#define USB_USB_MUXING_SOFTCON_RESET _u(0x0)
+#define USB_USB_MUXING_SOFTCON_BITS _u(0x00000008)
+#define USB_USB_MUXING_SOFTCON_MSB _u(3)
+#define USB_USB_MUXING_SOFTCON_LSB _u(3)
+#define USB_USB_MUXING_SOFTCON_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_MUXING_TO_DIGITAL_PAD
+// Description : None
+#define USB_USB_MUXING_TO_DIGITAL_PAD_RESET _u(0x0)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_BITS _u(0x00000004)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_MSB _u(2)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_LSB _u(2)
+#define USB_USB_MUXING_TO_DIGITAL_PAD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_MUXING_TO_EXTPHY
+// Description : None
+#define USB_USB_MUXING_TO_EXTPHY_RESET _u(0x0)
+#define USB_USB_MUXING_TO_EXTPHY_BITS _u(0x00000002)
+#define USB_USB_MUXING_TO_EXTPHY_MSB _u(1)
+#define USB_USB_MUXING_TO_EXTPHY_LSB _u(1)
+#define USB_USB_MUXING_TO_EXTPHY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_MUXING_TO_PHY
+// Description : None
+#define USB_USB_MUXING_TO_PHY_RESET _u(0x0)
+#define USB_USB_MUXING_TO_PHY_BITS _u(0x00000001)
+#define USB_USB_MUXING_TO_PHY_MSB _u(0)
+#define USB_USB_MUXING_TO_PHY_LSB _u(0)
+#define USB_USB_MUXING_TO_PHY_ACCESS "RW"
+// =============================================================================
+// Register : USB_USB_PWR
+// Description : Overrides for the power signals in the event that the VBUS
+// signals are not hooked up to GPIO. Set the value of the
+// override and then the override enable to switch over to the
+// override value.
+#define USB_USB_PWR_OFFSET _u(0x00000078)
+#define USB_USB_PWR_BITS _u(0x0000003f)
+#define USB_USB_PWR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_USB_PWR_OVERCURR_DETECT_EN
+// Description : None
+#define USB_USB_PWR_OVERCURR_DETECT_EN_RESET _u(0x0)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_BITS _u(0x00000020)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_MSB _u(5)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_LSB _u(5)
+#define USB_USB_PWR_OVERCURR_DETECT_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_PWR_OVERCURR_DETECT
+// Description : None
+#define USB_USB_PWR_OVERCURR_DETECT_RESET _u(0x0)
+#define USB_USB_PWR_OVERCURR_DETECT_BITS _u(0x00000010)
+#define USB_USB_PWR_OVERCURR_DETECT_MSB _u(4)
+#define USB_USB_PWR_OVERCURR_DETECT_LSB _u(4)
+#define USB_USB_PWR_OVERCURR_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN
+// Description : None
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS _u(0x00000008)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_MSB _u(3)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_LSB _u(3)
+#define USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_PWR_VBUS_DETECT
+// Description : None
+#define USB_USB_PWR_VBUS_DETECT_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_DETECT_BITS _u(0x00000004)
+#define USB_USB_PWR_VBUS_DETECT_MSB _u(2)
+#define USB_USB_PWR_VBUS_DETECT_LSB _u(2)
+#define USB_USB_PWR_VBUS_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_PWR_VBUS_EN_OVERRIDE_EN
+// Description : None
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_BITS _u(0x00000002)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_MSB _u(1)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_LSB _u(1)
+#define USB_USB_PWR_VBUS_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USB_PWR_VBUS_EN
+// Description : None
+#define USB_USB_PWR_VBUS_EN_RESET _u(0x0)
+#define USB_USB_PWR_VBUS_EN_BITS _u(0x00000001)
+#define USB_USB_PWR_VBUS_EN_MSB _u(0)
+#define USB_USB_PWR_VBUS_EN_LSB _u(0)
+#define USB_USB_PWR_VBUS_EN_ACCESS "RW"
+// =============================================================================
+// Register : USB_USBPHY_DIRECT
+// Description : This register allows for direct control of the USB phy. Use in
+// conjunction with usbphy_direct_override register to enable each
+// override bit.
+#define USB_USBPHY_DIRECT_OFFSET _u(0x0000007c)
+#define USB_USBPHY_DIRECT_BITS _u(0x007fff77)
+#define USB_USBPHY_DIRECT_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DM_OVV
+// Description : DM over voltage
+#define USB_USBPHY_DIRECT_DM_OVV_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_OVV_BITS _u(0x00400000)
+#define USB_USBPHY_DIRECT_DM_OVV_MSB _u(22)
+#define USB_USBPHY_DIRECT_DM_OVV_LSB _u(22)
+#define USB_USBPHY_DIRECT_DM_OVV_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DP_OVV
+// Description : DP over voltage
+#define USB_USBPHY_DIRECT_DP_OVV_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_OVV_BITS _u(0x00200000)
+#define USB_USBPHY_DIRECT_DP_OVV_MSB _u(21)
+#define USB_USBPHY_DIRECT_DP_OVV_LSB _u(21)
+#define USB_USBPHY_DIRECT_DP_OVV_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DM_OVCN
+// Description : DM overcurrent
+#define USB_USBPHY_DIRECT_DM_OVCN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_OVCN_BITS _u(0x00100000)
+#define USB_USBPHY_DIRECT_DM_OVCN_MSB _u(20)
+#define USB_USBPHY_DIRECT_DM_OVCN_LSB _u(20)
+#define USB_USBPHY_DIRECT_DM_OVCN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DP_OVCN
+// Description : DP overcurrent
+#define USB_USBPHY_DIRECT_DP_OVCN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_OVCN_BITS _u(0x00080000)
+#define USB_USBPHY_DIRECT_DP_OVCN_MSB _u(19)
+#define USB_USBPHY_DIRECT_DP_OVCN_LSB _u(19)
+#define USB_USBPHY_DIRECT_DP_OVCN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_RX_DM
+// Description : DPM pin state
+#define USB_USBPHY_DIRECT_RX_DM_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DM_BITS _u(0x00040000)
+#define USB_USBPHY_DIRECT_RX_DM_MSB _u(18)
+#define USB_USBPHY_DIRECT_RX_DM_LSB _u(18)
+#define USB_USBPHY_DIRECT_RX_DM_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_RX_DP
+// Description : DPP pin state
+#define USB_USBPHY_DIRECT_RX_DP_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DP_BITS _u(0x00020000)
+#define USB_USBPHY_DIRECT_RX_DP_MSB _u(17)
+#define USB_USBPHY_DIRECT_RX_DP_LSB _u(17)
+#define USB_USBPHY_DIRECT_RX_DP_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_RX_DD
+// Description : Differential RX
+#define USB_USBPHY_DIRECT_RX_DD_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_DD_BITS _u(0x00010000)
+#define USB_USBPHY_DIRECT_RX_DD_MSB _u(16)
+#define USB_USBPHY_DIRECT_RX_DD_LSB _u(16)
+#define USB_USBPHY_DIRECT_RX_DD_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_TX_DIFFMODE
+// Description : TX_DIFFMODE=0: Single ended mode
+// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE
+// ignored)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_BITS _u(0x00008000)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_MSB _u(15)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_LSB _u(15)
+#define USB_USBPHY_DIRECT_TX_DIFFMODE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_TX_FSSLEW
+// Description : TX_FSSLEW=0: Low speed slew rate
+// TX_FSSLEW=1: Full speed slew rate
+#define USB_USBPHY_DIRECT_TX_FSSLEW_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_BITS _u(0x00004000)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_MSB _u(14)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_LSB _u(14)
+#define USB_USBPHY_DIRECT_TX_FSSLEW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_TX_PD
+// Description : TX power down override (if override enable is set). 1 = powered
+// down.
+#define USB_USBPHY_DIRECT_TX_PD_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_PD_BITS _u(0x00002000)
+#define USB_USBPHY_DIRECT_TX_PD_MSB _u(13)
+#define USB_USBPHY_DIRECT_TX_PD_LSB _u(13)
+#define USB_USBPHY_DIRECT_TX_PD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_RX_PD
+// Description : RX power down override (if override enable is set). 1 = powered
+// down.
+#define USB_USBPHY_DIRECT_RX_PD_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_RX_PD_BITS _u(0x00001000)
+#define USB_USBPHY_DIRECT_RX_PD_MSB _u(12)
+#define USB_USBPHY_DIRECT_RX_PD_LSB _u(12)
+#define USB_USBPHY_DIRECT_RX_PD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_TX_DM
+// Description : Output data. TX_DIFFMODE=1, Ignored
+// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive.
+// DPM=TX_DM
+#define USB_USBPHY_DIRECT_TX_DM_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DM_BITS _u(0x00000800)
+#define USB_USBPHY_DIRECT_TX_DM_MSB _u(11)
+#define USB_USBPHY_DIRECT_TX_DM_LSB _u(11)
+#define USB_USBPHY_DIRECT_TX_DM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_TX_DP
+// Description : Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair.
+// TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
+// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive.
+// DPP=TX_DP
+#define USB_USBPHY_DIRECT_TX_DP_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DP_BITS _u(0x00000400)
+#define USB_USBPHY_DIRECT_TX_DP_MSB _u(10)
+#define USB_USBPHY_DIRECT_TX_DP_LSB _u(10)
+#define USB_USBPHY_DIRECT_TX_DP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_TX_DM_OE
+// Description : Output enable. If TX_DIFFMODE=1, Ignored.
+// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 -
+// DPM driving
+#define USB_USBPHY_DIRECT_TX_DM_OE_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DM_OE_BITS _u(0x00000200)
+#define USB_USBPHY_DIRECT_TX_DM_OE_MSB _u(9)
+#define USB_USBPHY_DIRECT_TX_DM_OE_LSB _u(9)
+#define USB_USBPHY_DIRECT_TX_DM_OE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_TX_DP_OE
+// Description : Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 -
+// DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
+// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 -
+// DPP driving
+#define USB_USBPHY_DIRECT_TX_DP_OE_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_TX_DP_OE_BITS _u(0x00000100)
+#define USB_USBPHY_DIRECT_TX_DP_OE_MSB _u(8)
+#define USB_USBPHY_DIRECT_TX_DP_OE_LSB _u(8)
+#define USB_USBPHY_DIRECT_TX_DP_OE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DM_PULLDN_EN
+// Description : DM pull down enable
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_BITS _u(0x00000040)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_MSB _u(6)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_LSB _u(6)
+#define USB_USBPHY_DIRECT_DM_PULLDN_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DM_PULLUP_EN
+// Description : DM pull up enable
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_BITS _u(0x00000020)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_MSB _u(5)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_LSB _u(5)
+#define USB_USBPHY_DIRECT_DM_PULLUP_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DM_PULLUP_HISEL
+// Description : Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 -
+// Pull = Rpu1 + Rpu2
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_BITS _u(0x00000010)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_MSB _u(4)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_LSB _u(4)
+#define USB_USBPHY_DIRECT_DM_PULLUP_HISEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DP_PULLDN_EN
+// Description : DP pull down enable
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_BITS _u(0x00000004)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_MSB _u(2)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_LSB _u(2)
+#define USB_USBPHY_DIRECT_DP_PULLDN_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DP_PULLUP_EN
+// Description : DP pull up enable
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_BITS _u(0x00000002)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_MSB _u(1)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_LSB _u(1)
+#define USB_USBPHY_DIRECT_DP_PULLUP_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_DP_PULLUP_HISEL
+// Description : Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 -
+// Pull = Rpu1 + Rpu2
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_BITS _u(0x00000001)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_MSB _u(0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_LSB _u(0)
+#define USB_USBPHY_DIRECT_DP_PULLUP_HISEL_ACCESS "RW"
+// =============================================================================
+// Register : USB_USBPHY_DIRECT_OVERRIDE
+// Description : Override enable for each control in usbphy_direct
+#define USB_USBPHY_DIRECT_OVERRIDE_OFFSET _u(0x00000080)
+#define USB_USBPHY_DIRECT_OVERRIDE_BITS _u(0x00009fff)
+#define USB_USBPHY_DIRECT_OVERRIDE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_BITS _u(0x00008000)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_MSB _u(15)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_LSB _u(15)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DIFFMODE_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_BITS _u(0x00001000)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_MSB _u(12)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_LSB _u(12)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_BITS _u(0x00000800)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_MSB _u(11)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_LSB _u(11)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_FSSLEW_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_BITS _u(0x00000400)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_MSB _u(10)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_LSB _u(10)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_PD_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_BITS _u(0x00000200)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_MSB _u(9)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_LSB _u(9)
+#define USB_USBPHY_DIRECT_OVERRIDE_RX_PD_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_BITS _u(0x00000100)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_MSB _u(8)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_LSB _u(8)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_BITS _u(0x00000080)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_MSB _u(7)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_LSB _u(7)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_BITS _u(0x00000040)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_MSB _u(6)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_LSB _u(6)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DM_OE_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_BITS _u(0x00000020)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_MSB _u(5)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_LSB _u(5)
+#define USB_USBPHY_DIRECT_OVERRIDE_TX_DP_OE_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000010)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_MSB _u(4)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_LSB _u(4)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_BITS _u(0x00000008)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_MSB _u(3)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_LSB _u(3)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLDN_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_BITS _u(0x00000004)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_MSB _u(2)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_LSB _u(2)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_EN_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000002)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_MSB _u(1)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_LSB _u(1)
+#define USB_USBPHY_DIRECT_OVERRIDE_DM_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN
+// Description : None
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_RESET _u(0x0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_BITS _u(0x00000001)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_MSB _u(0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_LSB _u(0)
+#define USB_USBPHY_DIRECT_OVERRIDE_DP_PULLUP_HISEL_OVERRIDE_EN_ACCESS "RW"
+// =============================================================================
+// Register : USB_USBPHY_TRIM
+// Description : Used to adjust trim values of USB phy pull down resistors.
+#define USB_USBPHY_TRIM_OFFSET _u(0x00000084)
+#define USB_USBPHY_TRIM_BITS _u(0x00001f1f)
+#define USB_USBPHY_TRIM_RESET _u(0x00001f1f)
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_TRIM_DM_PULLDN_TRIM
+// Description : Value to drive to USB PHY
+// DM pulldown resistor trim control
+// Experimental data suggests that the reset value will work, but
+// this register allows adjustment if required
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_RESET _u(0x1f)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_BITS _u(0x00001f00)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_MSB _u(12)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_LSB _u(8)
+#define USB_USBPHY_TRIM_DM_PULLDN_TRIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_USBPHY_TRIM_DP_PULLDN_TRIM
+// Description : Value to drive to USB PHY
+// DP pulldown resistor trim control
+// Experimental data suggests that the reset value will work, but
+// this register allows adjustment if required
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_RESET _u(0x1f)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_BITS _u(0x0000001f)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_MSB _u(4)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_LSB _u(0)
+#define USB_USBPHY_TRIM_DP_PULLDN_TRIM_ACCESS "RW"
+// =============================================================================
+// Register : USB_INTR
+// Description : Raw Interrupts
+#define USB_INTR_OFFSET _u(0x0000008c)
+#define USB_INTR_BITS _u(0x000fffff)
+#define USB_INTR_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+// clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTR_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTR_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTR_EP_STALL_NAK_MSB _u(19)
+#define USB_INTR_EP_STALL_NAK_LSB _u(19)
+#define USB_INTR_EP_STALL_NAK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+// bits in ABORT_DONE.
+#define USB_INTR_ABORT_DONE_RESET _u(0x0)
+#define USB_INTR_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTR_ABORT_DONE_MSB _u(18)
+#define USB_INTR_ABORT_DONE_LSB _u(18)
+#define USB_INTR_ABORT_DONE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+// packet. Cleared by reading SOF_RD
+#define USB_INTR_DEV_SOF_RESET _u(0x0)
+#define USB_INTR_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTR_DEV_SOF_MSB _u(17)
+#define USB_INTR_DEV_SOF_LSB _u(17)
+#define USB_INTR_DEV_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTR_SETUP_REQ_RESET _u(0x0)
+#define USB_INTR_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTR_SETUP_REQ_MSB _u(16)
+#define USB_INTR_SETUP_REQ_LSB _u(16)
+#define USB_INTR_SETUP_REQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTR_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTR_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTR_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTR_DEV_RESUME_FROM_HOST_LSB _u(15)
+#define USB_INTR_DEV_RESUME_FROM_HOST_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+// to SIE_STATUS.SUSPENDED
+#define USB_INTR_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTR_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTR_DEV_SUSPEND_MSB _u(14)
+#define USB_INTR_DEV_SUSPEND_LSB _u(14)
+#define USB_INTR_DEV_SUSPEND_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+// writing to SIE_STATUS.CONNECTED
+#define USB_INTR_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTR_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTR_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTR_DEV_CONN_DIS_LSB _u(13)
+#define USB_INTR_DEV_CONN_DIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTR_BUS_RESET_RESET _u(0x0)
+#define USB_INTR_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTR_BUS_RESET_MSB _u(12)
+#define USB_INTR_BUS_RESET_LSB _u(12)
+#define USB_INTR_BUS_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTR_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTR_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTR_VBUS_DETECT_MSB _u(11)
+#define USB_INTR_VBUS_DETECT_LSB _u(11)
+#define USB_INTR_VBUS_DETECT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTR_STALL_RESET _u(0x0)
+#define USB_INTR_STALL_BITS _u(0x00000400)
+#define USB_INTR_STALL_MSB _u(10)
+#define USB_INTR_STALL_LSB _u(10)
+#define USB_INTR_STALL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTR_ERROR_CRC_RESET _u(0x0)
+#define USB_INTR_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTR_ERROR_CRC_MSB _u(9)
+#define USB_INTR_ERROR_CRC_LSB _u(9)
+#define USB_INTR_ERROR_CRC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTR_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTR_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTR_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTR_ERROR_BIT_STUFF_LSB _u(8)
+#define USB_INTR_ERROR_BIT_STUFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTR_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTR_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTR_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTR_ERROR_RX_OVERFLOW_LSB _u(7)
+#define USB_INTR_ERROR_RX_OVERFLOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTR_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTR_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTR_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTR_ERROR_RX_TIMEOUT_LSB _u(6)
+#define USB_INTR_ERROR_RX_TIMEOUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTR_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTR_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTR_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTR_ERROR_DATA_SEQ_LSB _u(5)
+#define USB_INTR_ERROR_DATA_SEQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+// all bits in BUFF_STATUS.
+#define USB_INTR_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTR_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTR_BUFF_STATUS_MSB _u(4)
+#define USB_INTR_BUFF_STATUS_LSB _u(4)
+#define USB_INTR_BUFF_STATUS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+// writing to this bit.
+#define USB_INTR_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTR_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTR_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTR_TRANS_COMPLETE_LSB _u(3)
+#define USB_INTR_TRANS_COMPLETE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+// Cleared by reading SOF_RD
+#define USB_INTR_HOST_SOF_RESET _u(0x0)
+#define USB_INTR_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTR_HOST_SOF_MSB _u(2)
+#define USB_INTR_HOST_SOF_LSB _u(2)
+#define USB_INTR_HOST_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTR_HOST_RESUME_RESET _u(0x0)
+#define USB_INTR_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTR_HOST_RESUME_MSB _u(1)
+#define USB_INTR_HOST_RESUME_LSB _u(1)
+#define USB_INTR_HOST_RESUME_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTR_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+// when SIE_STATUS.SPEED changes). Cleared by writing to
+// SIE_STATUS.SPEED
+#define USB_INTR_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTR_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTR_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTR_HOST_CONN_DIS_LSB _u(0)
+#define USB_INTR_HOST_CONN_DIS_ACCESS "RO"
+// =============================================================================
+// Register : USB_INTE
+// Description : Interrupt Enable
+#define USB_INTE_OFFSET _u(0x00000090)
+#define USB_INTE_BITS _u(0x000fffff)
+#define USB_INTE_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+// clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTE_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTE_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTE_EP_STALL_NAK_MSB _u(19)
+#define USB_INTE_EP_STALL_NAK_LSB _u(19)
+#define USB_INTE_EP_STALL_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+// bits in ABORT_DONE.
+#define USB_INTE_ABORT_DONE_RESET _u(0x0)
+#define USB_INTE_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTE_ABORT_DONE_MSB _u(18)
+#define USB_INTE_ABORT_DONE_LSB _u(18)
+#define USB_INTE_ABORT_DONE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+// packet. Cleared by reading SOF_RD
+#define USB_INTE_DEV_SOF_RESET _u(0x0)
+#define USB_INTE_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTE_DEV_SOF_MSB _u(17)
+#define USB_INTE_DEV_SOF_LSB _u(17)
+#define USB_INTE_DEV_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTE_SETUP_REQ_RESET _u(0x0)
+#define USB_INTE_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTE_SETUP_REQ_MSB _u(16)
+#define USB_INTE_SETUP_REQ_LSB _u(16)
+#define USB_INTE_SETUP_REQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTE_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTE_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTE_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTE_DEV_RESUME_FROM_HOST_LSB _u(15)
+#define USB_INTE_DEV_RESUME_FROM_HOST_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+// to SIE_STATUS.SUSPENDED
+#define USB_INTE_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTE_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTE_DEV_SUSPEND_MSB _u(14)
+#define USB_INTE_DEV_SUSPEND_LSB _u(14)
+#define USB_INTE_DEV_SUSPEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+// writing to SIE_STATUS.CONNECTED
+#define USB_INTE_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTE_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTE_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTE_DEV_CONN_DIS_LSB _u(13)
+#define USB_INTE_DEV_CONN_DIS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTE_BUS_RESET_RESET _u(0x0)
+#define USB_INTE_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTE_BUS_RESET_MSB _u(12)
+#define USB_INTE_BUS_RESET_LSB _u(12)
+#define USB_INTE_BUS_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTE_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTE_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTE_VBUS_DETECT_MSB _u(11)
+#define USB_INTE_VBUS_DETECT_LSB _u(11)
+#define USB_INTE_VBUS_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTE_STALL_RESET _u(0x0)
+#define USB_INTE_STALL_BITS _u(0x00000400)
+#define USB_INTE_STALL_MSB _u(10)
+#define USB_INTE_STALL_LSB _u(10)
+#define USB_INTE_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTE_ERROR_CRC_RESET _u(0x0)
+#define USB_INTE_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTE_ERROR_CRC_MSB _u(9)
+#define USB_INTE_ERROR_CRC_LSB _u(9)
+#define USB_INTE_ERROR_CRC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTE_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTE_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTE_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTE_ERROR_BIT_STUFF_LSB _u(8)
+#define USB_INTE_ERROR_BIT_STUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTE_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTE_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTE_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTE_ERROR_RX_OVERFLOW_LSB _u(7)
+#define USB_INTE_ERROR_RX_OVERFLOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTE_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTE_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTE_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTE_ERROR_RX_TIMEOUT_LSB _u(6)
+#define USB_INTE_ERROR_RX_TIMEOUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTE_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTE_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTE_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTE_ERROR_DATA_SEQ_LSB _u(5)
+#define USB_INTE_ERROR_DATA_SEQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+// all bits in BUFF_STATUS.
+#define USB_INTE_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTE_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTE_BUFF_STATUS_MSB _u(4)
+#define USB_INTE_BUFF_STATUS_LSB _u(4)
+#define USB_INTE_BUFF_STATUS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+// writing to this bit.
+#define USB_INTE_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTE_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTE_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTE_TRANS_COMPLETE_LSB _u(3)
+#define USB_INTE_TRANS_COMPLETE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+// Cleared by reading SOF_RD
+#define USB_INTE_HOST_SOF_RESET _u(0x0)
+#define USB_INTE_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTE_HOST_SOF_MSB _u(2)
+#define USB_INTE_HOST_SOF_LSB _u(2)
+#define USB_INTE_HOST_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTE_HOST_RESUME_RESET _u(0x0)
+#define USB_INTE_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTE_HOST_RESUME_MSB _u(1)
+#define USB_INTE_HOST_RESUME_LSB _u(1)
+#define USB_INTE_HOST_RESUME_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTE_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+// when SIE_STATUS.SPEED changes). Cleared by writing to
+// SIE_STATUS.SPEED
+#define USB_INTE_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTE_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTE_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTE_HOST_CONN_DIS_LSB _u(0)
+#define USB_INTE_HOST_CONN_DIS_ACCESS "RW"
+// =============================================================================
+// Register : USB_INTF
+// Description : Interrupt Force
+#define USB_INTF_OFFSET _u(0x00000094)
+#define USB_INTF_BITS _u(0x000fffff)
+#define USB_INTF_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+// clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTF_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTF_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTF_EP_STALL_NAK_MSB _u(19)
+#define USB_INTF_EP_STALL_NAK_LSB _u(19)
+#define USB_INTF_EP_STALL_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+// bits in ABORT_DONE.
+#define USB_INTF_ABORT_DONE_RESET _u(0x0)
+#define USB_INTF_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTF_ABORT_DONE_MSB _u(18)
+#define USB_INTF_ABORT_DONE_LSB _u(18)
+#define USB_INTF_ABORT_DONE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+// packet. Cleared by reading SOF_RD
+#define USB_INTF_DEV_SOF_RESET _u(0x0)
+#define USB_INTF_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTF_DEV_SOF_MSB _u(17)
+#define USB_INTF_DEV_SOF_LSB _u(17)
+#define USB_INTF_DEV_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTF_SETUP_REQ_RESET _u(0x0)
+#define USB_INTF_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTF_SETUP_REQ_MSB _u(16)
+#define USB_INTF_SETUP_REQ_LSB _u(16)
+#define USB_INTF_SETUP_REQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTF_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTF_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTF_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTF_DEV_RESUME_FROM_HOST_LSB _u(15)
+#define USB_INTF_DEV_RESUME_FROM_HOST_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+// to SIE_STATUS.SUSPENDED
+#define USB_INTF_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTF_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTF_DEV_SUSPEND_MSB _u(14)
+#define USB_INTF_DEV_SUSPEND_LSB _u(14)
+#define USB_INTF_DEV_SUSPEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+// writing to SIE_STATUS.CONNECTED
+#define USB_INTF_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTF_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTF_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTF_DEV_CONN_DIS_LSB _u(13)
+#define USB_INTF_DEV_CONN_DIS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTF_BUS_RESET_RESET _u(0x0)
+#define USB_INTF_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTF_BUS_RESET_MSB _u(12)
+#define USB_INTF_BUS_RESET_LSB _u(12)
+#define USB_INTF_BUS_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTF_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTF_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTF_VBUS_DETECT_MSB _u(11)
+#define USB_INTF_VBUS_DETECT_LSB _u(11)
+#define USB_INTF_VBUS_DETECT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTF_STALL_RESET _u(0x0)
+#define USB_INTF_STALL_BITS _u(0x00000400)
+#define USB_INTF_STALL_MSB _u(10)
+#define USB_INTF_STALL_LSB _u(10)
+#define USB_INTF_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTF_ERROR_CRC_RESET _u(0x0)
+#define USB_INTF_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTF_ERROR_CRC_MSB _u(9)
+#define USB_INTF_ERROR_CRC_LSB _u(9)
+#define USB_INTF_ERROR_CRC_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTF_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTF_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTF_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTF_ERROR_BIT_STUFF_LSB _u(8)
+#define USB_INTF_ERROR_BIT_STUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTF_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTF_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTF_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTF_ERROR_RX_OVERFLOW_LSB _u(7)
+#define USB_INTF_ERROR_RX_OVERFLOW_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTF_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTF_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTF_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTF_ERROR_RX_TIMEOUT_LSB _u(6)
+#define USB_INTF_ERROR_RX_TIMEOUT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTF_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTF_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTF_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTF_ERROR_DATA_SEQ_LSB _u(5)
+#define USB_INTF_ERROR_DATA_SEQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+// all bits in BUFF_STATUS.
+#define USB_INTF_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTF_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTF_BUFF_STATUS_MSB _u(4)
+#define USB_INTF_BUFF_STATUS_LSB _u(4)
+#define USB_INTF_BUFF_STATUS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+// writing to this bit.
+#define USB_INTF_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTF_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTF_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTF_TRANS_COMPLETE_LSB _u(3)
+#define USB_INTF_TRANS_COMPLETE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+// Cleared by reading SOF_RD
+#define USB_INTF_HOST_SOF_RESET _u(0x0)
+#define USB_INTF_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTF_HOST_SOF_MSB _u(2)
+#define USB_INTF_HOST_SOF_LSB _u(2)
+#define USB_INTF_HOST_SOF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTF_HOST_RESUME_RESET _u(0x0)
+#define USB_INTF_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTF_HOST_RESUME_MSB _u(1)
+#define USB_INTF_HOST_RESUME_LSB _u(1)
+#define USB_INTF_HOST_RESUME_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_INTF_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+// when SIE_STATUS.SPEED changes). Cleared by writing to
+// SIE_STATUS.SPEED
+#define USB_INTF_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTF_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTF_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTF_HOST_CONN_DIS_LSB _u(0)
+#define USB_INTF_HOST_CONN_DIS_ACCESS "RW"
+// =============================================================================
+// Register : USB_INTS
+// Description : Interrupt status after masking & forcing
+#define USB_INTS_OFFSET _u(0x00000098)
+#define USB_INTS_BITS _u(0x000fffff)
+#define USB_INTS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_EP_STALL_NAK
+// Description : Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by
+// clearing all bits in EP_STATUS_STALL_NAK.
+#define USB_INTS_EP_STALL_NAK_RESET _u(0x0)
+#define USB_INTS_EP_STALL_NAK_BITS _u(0x00080000)
+#define USB_INTS_EP_STALL_NAK_MSB _u(19)
+#define USB_INTS_EP_STALL_NAK_LSB _u(19)
+#define USB_INTS_EP_STALL_NAK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_ABORT_DONE
+// Description : Raised when any bit in ABORT_DONE is set. Clear by clearing all
+// bits in ABORT_DONE.
+#define USB_INTS_ABORT_DONE_RESET _u(0x0)
+#define USB_INTS_ABORT_DONE_BITS _u(0x00040000)
+#define USB_INTS_ABORT_DONE_MSB _u(18)
+#define USB_INTS_ABORT_DONE_LSB _u(18)
+#define USB_INTS_ABORT_DONE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_DEV_SOF
+// Description : Set every time the device receives a SOF (Start of Frame)
+// packet. Cleared by reading SOF_RD
+#define USB_INTS_DEV_SOF_RESET _u(0x0)
+#define USB_INTS_DEV_SOF_BITS _u(0x00020000)
+#define USB_INTS_DEV_SOF_MSB _u(17)
+#define USB_INTS_DEV_SOF_LSB _u(17)
+#define USB_INTS_DEV_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_SETUP_REQ
+// Description : Device. Source: SIE_STATUS.SETUP_REC
+#define USB_INTS_SETUP_REQ_RESET _u(0x0)
+#define USB_INTS_SETUP_REQ_BITS _u(0x00010000)
+#define USB_INTS_SETUP_REQ_MSB _u(16)
+#define USB_INTS_SETUP_REQ_LSB _u(16)
+#define USB_INTS_SETUP_REQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_DEV_RESUME_FROM_HOST
+// Description : Set when the device receives a resume from the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTS_DEV_RESUME_FROM_HOST_RESET _u(0x0)
+#define USB_INTS_DEV_RESUME_FROM_HOST_BITS _u(0x00008000)
+#define USB_INTS_DEV_RESUME_FROM_HOST_MSB _u(15)
+#define USB_INTS_DEV_RESUME_FROM_HOST_LSB _u(15)
+#define USB_INTS_DEV_RESUME_FROM_HOST_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_DEV_SUSPEND
+// Description : Set when the device suspend state changes. Cleared by writing
+// to SIE_STATUS.SUSPENDED
+#define USB_INTS_DEV_SUSPEND_RESET _u(0x0)
+#define USB_INTS_DEV_SUSPEND_BITS _u(0x00004000)
+#define USB_INTS_DEV_SUSPEND_MSB _u(14)
+#define USB_INTS_DEV_SUSPEND_LSB _u(14)
+#define USB_INTS_DEV_SUSPEND_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_DEV_CONN_DIS
+// Description : Set when the device connection state changes. Cleared by
+// writing to SIE_STATUS.CONNECTED
+#define USB_INTS_DEV_CONN_DIS_RESET _u(0x0)
+#define USB_INTS_DEV_CONN_DIS_BITS _u(0x00002000)
+#define USB_INTS_DEV_CONN_DIS_MSB _u(13)
+#define USB_INTS_DEV_CONN_DIS_LSB _u(13)
+#define USB_INTS_DEV_CONN_DIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_BUS_RESET
+// Description : Source: SIE_STATUS.BUS_RESET
+#define USB_INTS_BUS_RESET_RESET _u(0x0)
+#define USB_INTS_BUS_RESET_BITS _u(0x00001000)
+#define USB_INTS_BUS_RESET_MSB _u(12)
+#define USB_INTS_BUS_RESET_LSB _u(12)
+#define USB_INTS_BUS_RESET_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_VBUS_DETECT
+// Description : Source: SIE_STATUS.VBUS_DETECTED
+#define USB_INTS_VBUS_DETECT_RESET _u(0x0)
+#define USB_INTS_VBUS_DETECT_BITS _u(0x00000800)
+#define USB_INTS_VBUS_DETECT_MSB _u(11)
+#define USB_INTS_VBUS_DETECT_LSB _u(11)
+#define USB_INTS_VBUS_DETECT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_STALL
+// Description : Source: SIE_STATUS.STALL_REC
+#define USB_INTS_STALL_RESET _u(0x0)
+#define USB_INTS_STALL_BITS _u(0x00000400)
+#define USB_INTS_STALL_MSB _u(10)
+#define USB_INTS_STALL_LSB _u(10)
+#define USB_INTS_STALL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_ERROR_CRC
+// Description : Source: SIE_STATUS.CRC_ERROR
+#define USB_INTS_ERROR_CRC_RESET _u(0x0)
+#define USB_INTS_ERROR_CRC_BITS _u(0x00000200)
+#define USB_INTS_ERROR_CRC_MSB _u(9)
+#define USB_INTS_ERROR_CRC_LSB _u(9)
+#define USB_INTS_ERROR_CRC_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_ERROR_BIT_STUFF
+// Description : Source: SIE_STATUS.BIT_STUFF_ERROR
+#define USB_INTS_ERROR_BIT_STUFF_RESET _u(0x0)
+#define USB_INTS_ERROR_BIT_STUFF_BITS _u(0x00000100)
+#define USB_INTS_ERROR_BIT_STUFF_MSB _u(8)
+#define USB_INTS_ERROR_BIT_STUFF_LSB _u(8)
+#define USB_INTS_ERROR_BIT_STUFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_ERROR_RX_OVERFLOW
+// Description : Source: SIE_STATUS.RX_OVERFLOW
+#define USB_INTS_ERROR_RX_OVERFLOW_RESET _u(0x0)
+#define USB_INTS_ERROR_RX_OVERFLOW_BITS _u(0x00000080)
+#define USB_INTS_ERROR_RX_OVERFLOW_MSB _u(7)
+#define USB_INTS_ERROR_RX_OVERFLOW_LSB _u(7)
+#define USB_INTS_ERROR_RX_OVERFLOW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_ERROR_RX_TIMEOUT
+// Description : Source: SIE_STATUS.RX_TIMEOUT
+#define USB_INTS_ERROR_RX_TIMEOUT_RESET _u(0x0)
+#define USB_INTS_ERROR_RX_TIMEOUT_BITS _u(0x00000040)
+#define USB_INTS_ERROR_RX_TIMEOUT_MSB _u(6)
+#define USB_INTS_ERROR_RX_TIMEOUT_LSB _u(6)
+#define USB_INTS_ERROR_RX_TIMEOUT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_ERROR_DATA_SEQ
+// Description : Source: SIE_STATUS.DATA_SEQ_ERROR
+#define USB_INTS_ERROR_DATA_SEQ_RESET _u(0x0)
+#define USB_INTS_ERROR_DATA_SEQ_BITS _u(0x00000020)
+#define USB_INTS_ERROR_DATA_SEQ_MSB _u(5)
+#define USB_INTS_ERROR_DATA_SEQ_LSB _u(5)
+#define USB_INTS_ERROR_DATA_SEQ_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_BUFF_STATUS
+// Description : Raised when any bit in BUFF_STATUS is set. Clear by clearing
+// all bits in BUFF_STATUS.
+#define USB_INTS_BUFF_STATUS_RESET _u(0x0)
+#define USB_INTS_BUFF_STATUS_BITS _u(0x00000010)
+#define USB_INTS_BUFF_STATUS_MSB _u(4)
+#define USB_INTS_BUFF_STATUS_LSB _u(4)
+#define USB_INTS_BUFF_STATUS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_TRANS_COMPLETE
+// Description : Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by
+// writing to this bit.
+#define USB_INTS_TRANS_COMPLETE_RESET _u(0x0)
+#define USB_INTS_TRANS_COMPLETE_BITS _u(0x00000008)
+#define USB_INTS_TRANS_COMPLETE_MSB _u(3)
+#define USB_INTS_TRANS_COMPLETE_LSB _u(3)
+#define USB_INTS_TRANS_COMPLETE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_HOST_SOF
+// Description : Host: raised every time the host sends a SOF (Start of Frame).
+// Cleared by reading SOF_RD
+#define USB_INTS_HOST_SOF_RESET _u(0x0)
+#define USB_INTS_HOST_SOF_BITS _u(0x00000004)
+#define USB_INTS_HOST_SOF_MSB _u(2)
+#define USB_INTS_HOST_SOF_LSB _u(2)
+#define USB_INTS_HOST_SOF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_HOST_RESUME
+// Description : Host: raised when a device wakes up the host. Cleared by
+// writing to SIE_STATUS.RESUME
+#define USB_INTS_HOST_RESUME_RESET _u(0x0)
+#define USB_INTS_HOST_RESUME_BITS _u(0x00000002)
+#define USB_INTS_HOST_RESUME_MSB _u(1)
+#define USB_INTS_HOST_RESUME_LSB _u(1)
+#define USB_INTS_HOST_RESUME_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : USB_INTS_HOST_CONN_DIS
+// Description : Host: raised when a device is connected or disconnected (i.e.
+// when SIE_STATUS.SPEED changes). Cleared by writing to
+// SIE_STATUS.SPEED
+#define USB_INTS_HOST_CONN_DIS_RESET _u(0x0)
+#define USB_INTS_HOST_CONN_DIS_BITS _u(0x00000001)
+#define USB_INTS_HOST_CONN_DIS_MSB _u(0)
+#define USB_INTS_HOST_CONN_DIS_LSB _u(0)
+#define USB_INTS_HOST_CONN_DIS_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_USB_DEFINED
diff --git a/arkanoid/pico/hardware/regs/usb_device_dpram.h b/arkanoid/pico/hardware/regs/usb_device_dpram.h
new file mode 100644
index 0000000..fe65ffb
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/usb_device_dpram.h
@@ -0,0 +1,6807 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : USB_DEVICE_DPRAM
+// Version : 1
+// Bus type : ahbl
+// Description : DPRAM layout for USB device.
+// =============================================================================
+#ifndef HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
+#define HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_SETUP_PACKET_LOW
+// Description : Bytes 0-3 of the SETUP packet from the host.
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_OFFSET _u(0x00000000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_BITS _u(0xffff0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_MSB _u(31)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_LSB _u(16)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_WVALUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_RESET _u(0x00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_BITS _u(0x0000ff00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_MSB _u(15)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_LSB _u(8)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BREQUEST_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_RESET _u(0x00)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_BITS _u(0x000000ff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_MSB _u(7)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_LSB _u(0)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_LOW_BMREQUESTTYPE_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH
+// Description : Bytes 4-7 of the setup packet from the host.
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_OFFSET _u(0x00000004)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_BITS _u(0xffff0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_MSB _u(31)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_LSB _u(16)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WLENGTH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX
+// Description : None
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_MSB _u(15)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_LSB _u(0)
+#define USB_DEVICE_DPRAM_SETUP_PACKET_HIGH_WINDEX_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_OFFSET _u(0x00000008)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_OFFSET _u(0x0000000c)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_OFFSET _u(0x00000010)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_OFFSET _u(0x00000014)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_OFFSET _u(0x00000018)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_OFFSET _u(0x0000001c)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_OFFSET _u(0x00000020)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_OFFSET _u(0x00000024)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_OFFSET _u(0x00000028)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_OFFSET _u(0x0000002c)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_OFFSET _u(0x00000030)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_OFFSET _u(0x00000034)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_OFFSET _u(0x00000038)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_OFFSET _u(0x0000003c)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_OFFSET _u(0x00000040)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_OFFSET _u(0x00000044)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_OFFSET _u(0x00000048)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_OFFSET _u(0x0000004c)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_OFFSET _u(0x00000050)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_OFFSET _u(0x00000054)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_OFFSET _u(0x00000058)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_OFFSET _u(0x0000005c)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_OFFSET _u(0x00000060)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_OFFSET _u(0x00000064)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_OFFSET _u(0x00000068)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_OFFSET _u(0x0000006c)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_OFFSET _u(0x00000070)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_OFFSET _u(0x00000074)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_IN_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_OFFSET _u(0x00000078)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_IN_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_OUT_CONTROL
+// Description : None
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_OFFSET _u(0x0000007c)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BITS _u(0xfc03ffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE
+// Description : Enable this endpoint. The device will not reply to any packets
+// for this endpoint if this bit is not set.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED
+// Description : This endpoint is double buffered.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_DOUBLE_BUFFERED_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF
+// Description : Trigger an interrupt each time a buffer is done.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF
+// Description : Trigger an interrupt each time both buffers are done. Only
+// valid in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_BITS _u(0x10000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_LSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_PER_DOUBLE_BUFF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE
+// Description : 0x0 -> Control
+// 0x1 -> Isochronous
+// 0x2 -> Bulk
+// 0x3 -> Interrupt
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_BITS _u(0x0c000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_MSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_CONTROL _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_ISOCHRONOUS _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_BULK _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_ENDPOINT_TYPE_VALUE_INTERRUPT _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL
+// Description : Trigger an interrupt if a STALL is sent. Intended for debug
+// only.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_BITS _u(0x00020000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_MSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_LSB _u(17)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK
+// Description : Trigger an interrupt if a NAK is sent. Intended for debug only.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_BITS _u(0x00010000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_MSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_INTERRUPT_ON_NAK_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS
+// Description : 64 byte aligned buffer address for this EP (bits 0-5 are
+// ignored). Relative to the start of the DPRAM.
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_RESET _u(0x0000)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_BITS _u(0x0000ffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_OUT_CONTROL_BUFFER_ADDRESS_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_OFFSET _u(0x00000080)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP0_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_OFFSET _u(0x00000084)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP0_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_OFFSET _u(0x00000088)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_OFFSET _u(0x0000008c)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP1_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_OFFSET _u(0x00000090)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_OFFSET _u(0x00000094)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP2_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_OFFSET _u(0x00000098)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_OFFSET _u(0x0000009c)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP3_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_OFFSET _u(0x000000a0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_OFFSET _u(0x000000a4)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP4_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_OFFSET _u(0x000000a8)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ac)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP5_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_OFFSET _u(0x000000b0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_OFFSET _u(0x000000b4)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP6_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_OFFSET _u(0x000000b8)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_OFFSET _u(0x000000bc)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP7_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_OFFSET _u(0x000000c0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_OFFSET _u(0x000000c4)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP8_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_OFFSET _u(0x000000c8)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_OFFSET _u(0x000000cc)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP9_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_OFFSET _u(0x000000d0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_OFFSET _u(0x000000d4)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP10_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_OFFSET _u(0x000000d8)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_OFFSET _u(0x000000dc)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP11_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_OFFSET _u(0x000000e0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_OFFSET _u(0x000000e4)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP12_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_OFFSET _u(0x000000e8)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_OFFSET _u(0x000000ec)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP13_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_OFFSET _u(0x000000f0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_OFFSET _u(0x000000f4)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP14_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_OFFSET _u(0x000000f8)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSE
+// T
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_IN_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+// Register : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL
+// Description : Buffer control for both buffers of an endpoint. Fields ending
+// in a _1 are for buffer 1.
+// Fields ending in a _0 are for buffer 0. Buffer 1 controls are
+// only valid if the endpoint is in double buffered mode.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_OFFSET _u(0x000000fc)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_BITS _u(0xffffffff)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1
+// Description : Buffer 1 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_BITS _u(0x80000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_MSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_LSB _u(31)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1
+// Description : Buffer 1 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_BITS _u(0x40000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_MSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_LSB _u(30)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1
+// Description : The data pid of buffer 1.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_BITS _u(0x20000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_MSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_LSB _u(29)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFS
+// ET
+// Description : The number of bytes buffer 1 is offset from buffer 0 in
+// Isochronous mode. Only valid in double buffered mode for an
+// Isochronous endpoint.
+// For a non Isochronous endpoint the offset is always 64 bytes.
+// 0x0 -> 128
+// 0x1 -> 256
+// 0x2 -> 512
+// 0x3 -> 1024
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_BITS _u(0x18000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_MSB _u(28)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_LSB _u(27)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_ACCESS "RW"
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_128 _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_256 _u(0x1)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_512 _u(0x2)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_DOUBLE_BUFFER_ISO_OFFSET_VALUE_1024 _u(0x3)
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1
+// Description : Buffer 1 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_BITS _u(0x04000000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_MSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_LSB _u(26)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1
+// Description : The length of the data in buffer 1.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_BITS _u(0x03ff0000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_MSB _u(25)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_LSB _u(16)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0
+// Description : Buffer 0 is full. For an IN transfer (TX to the host) the bit
+// is set to indicate the data is valid. For an OUT transfer (RX
+// from the host) this bit should be left as a 0. The host will
+// set it when it has filled the buffer with data.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_BITS _u(0x00008000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_MSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_LSB _u(15)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_FULL_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0
+// Description : Buffer 0 is the last buffer of the transfer.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_BITS _u(0x00004000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_MSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_LSB _u(14)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LAST_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0
+// Description : The data pid of buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_BITS _u(0x00002000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_MSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_LSB _u(13)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_PID_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET
+// Description : Reset the buffer selector to buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_BITS _u(0x00001000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_MSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_LSB _u(12)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_RESET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL
+// Description : Reply with a stall (valid for both buffers).
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_BITS _u(0x00000800)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_MSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_LSB _u(11)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_STALL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0
+// Description : Buffer 0 is available. This bit is set to indicate the buffer
+// can be used by the controller. The controller clears the
+// available bit when writing the status back.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_RESET _u(0x0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_BITS _u(0x00000400)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_MSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_LSB _u(10)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_AVAILABLE_0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0
+// Description : The length of the data in buffer 0.
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_RESET _u(0x000)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_BITS _u(0x000003ff)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_MSB _u(9)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_LSB _u(0)
+#define USB_DEVICE_DPRAM_EP15_OUT_BUFFER_CONTROL_LENGTH_0_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_USB_DEVICE_DPRAM_DEFINED
diff --git a/arkanoid/pico/hardware/regs/vreg_and_chip_reset.h b/arkanoid/pico/hardware/regs/vreg_and_chip_reset.h
new file mode 100644
index 0000000..356ff56
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/vreg_and_chip_reset.h
@@ -0,0 +1,151 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : VREG_AND_CHIP_RESET
+// Version : 1
+// Bus type : apb
+// Description : control and status for on-chip voltage regulator and chip
+// level reset subsystem
+// =============================================================================
+#ifndef HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
+#define HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
+// =============================================================================
+// Register : VREG_AND_CHIP_RESET_VREG
+// Description : Voltage regulator control and status
+#define VREG_AND_CHIP_RESET_VREG_OFFSET _u(0x00000000)
+#define VREG_AND_CHIP_RESET_VREG_BITS _u(0x000010f3)
+#define VREG_AND_CHIP_RESET_VREG_RESET _u(0x000000b1)
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_VREG_ROK
+// Description : regulation status
+// 0=not in regulation, 1=in regulation
+#define VREG_AND_CHIP_RESET_VREG_ROK_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_VREG_ROK_BITS _u(0x00001000)
+#define VREG_AND_CHIP_RESET_VREG_ROK_MSB _u(12)
+#define VREG_AND_CHIP_RESET_VREG_ROK_LSB _u(12)
+#define VREG_AND_CHIP_RESET_VREG_ROK_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_VREG_VSEL
+// Description : output voltage select
+// 0000 to 0101 - 0.80V
+// 0110 - 0.85V
+// 0111 - 0.90V
+// 1000 - 0.95V
+// 1001 - 1.00V
+// 1010 - 1.05V
+// 1011 - 1.10V (default)
+// 1100 - 1.15V
+// 1101 - 1.20V
+// 1110 - 1.25V
+// 1111 - 1.30V
+#define VREG_AND_CHIP_RESET_VREG_VSEL_RESET _u(0xb)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_BITS _u(0x000000f0)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_MSB _u(7)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_LSB _u(4)
+#define VREG_AND_CHIP_RESET_VREG_VSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_VREG_HIZ
+// Description : high impedance mode select
+// 0=not in high impedance mode, 1=in high impedance mode
+#define VREG_AND_CHIP_RESET_VREG_HIZ_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_BITS _u(0x00000002)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_MSB _u(1)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_LSB _u(1)
+#define VREG_AND_CHIP_RESET_VREG_HIZ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_VREG_EN
+// Description : enable
+// 0=not enabled, 1=enabled
+#define VREG_AND_CHIP_RESET_VREG_EN_RESET _u(0x1)
+#define VREG_AND_CHIP_RESET_VREG_EN_BITS _u(0x00000001)
+#define VREG_AND_CHIP_RESET_VREG_EN_MSB _u(0)
+#define VREG_AND_CHIP_RESET_VREG_EN_LSB _u(0)
+#define VREG_AND_CHIP_RESET_VREG_EN_ACCESS "RW"
+// =============================================================================
+// Register : VREG_AND_CHIP_RESET_BOD
+// Description : brown-out detection control
+#define VREG_AND_CHIP_RESET_BOD_OFFSET _u(0x00000004)
+#define VREG_AND_CHIP_RESET_BOD_BITS _u(0x000000f1)
+#define VREG_AND_CHIP_RESET_BOD_RESET _u(0x00000091)
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_BOD_VSEL
+// Description : threshold select
+// 0000 - 0.473V
+// 0001 - 0.516V
+// 0010 - 0.559V
+// 0011 - 0.602V
+// 0100 - 0.645V
+// 0101 - 0.688V
+// 0110 - 0.731V
+// 0111 - 0.774V
+// 1000 - 0.817V
+// 1001 - 0.860V (default)
+// 1010 - 0.903V
+// 1011 - 0.946V
+// 1100 - 0.989V
+// 1101 - 1.032V
+// 1110 - 1.075V
+// 1111 - 1.118V
+#define VREG_AND_CHIP_RESET_BOD_VSEL_RESET _u(0x9)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_BITS _u(0x000000f0)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_MSB _u(7)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_LSB _u(4)
+#define VREG_AND_CHIP_RESET_BOD_VSEL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_BOD_EN
+// Description : enable
+// 0=not enabled, 1=enabled
+#define VREG_AND_CHIP_RESET_BOD_EN_RESET _u(0x1)
+#define VREG_AND_CHIP_RESET_BOD_EN_BITS _u(0x00000001)
+#define VREG_AND_CHIP_RESET_BOD_EN_MSB _u(0)
+#define VREG_AND_CHIP_RESET_BOD_EN_LSB _u(0)
+#define VREG_AND_CHIP_RESET_BOD_EN_ACCESS "RW"
+// =============================================================================
+// Register : VREG_AND_CHIP_RESET_CHIP_RESET
+// Description : Chip reset control and status
+#define VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET _u(0x00000008)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_BITS _u(0x01110100)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG
+// Description : This is set by psm_restart from the debugger.
+// Its purpose is to branch bootcode to a safe mode when the
+// debugger has issued a psm_restart in order to recover from a
+// boot lock-up.
+// In the safe mode the debugger can repair the boot code, clear
+// this flag then reboot the processor.
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_BITS _u(0x01000000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_MSB _u(24)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_LSB _u(24)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_PSM_RESTART_FLAG_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART
+// Description : Last reset was from the debug port
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_BITS _u(0x00100000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_MSB _u(20)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_LSB _u(20)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_PSM_RESTART_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN
+// Description : Last reset was from the RUN pin
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_BITS _u(0x00010000)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_MSB _u(16)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_LSB _u(16)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_RUN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR
+// Description : Last reset was from the power-on reset or brown-out detection
+// blocks
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_RESET _u(0x0)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_BITS _u(0x00000100)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_MSB _u(8)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_LSB _u(8)
+#define VREG_AND_CHIP_RESET_CHIP_RESET_HAD_POR_ACCESS "RO"
+// =============================================================================
+#endif // HARDWARE_REGS_VREG_AND_CHIP_RESET_DEFINED
diff --git a/arkanoid/pico/hardware/regs/watchdog.h b/arkanoid/pico/hardware/regs/watchdog.h
new file mode 100644
index 0000000..6a9853d
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/watchdog.h
@@ -0,0 +1,226 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : WATCHDOG
+// Version : 1
+// Bus type : apb
+// Description : None
+// =============================================================================
+#ifndef HARDWARE_REGS_WATCHDOG_DEFINED
+#define HARDWARE_REGS_WATCHDOG_DEFINED
+// =============================================================================
+// Register : WATCHDOG_CTRL
+// Description : Watchdog control
+// The rst_wdsel register determines which subsystems are reset
+// when the watchdog is triggered.
+// The watchdog can be triggered in software.
+#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
+#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
+#define WATCHDOG_CTRL_RESET _u(0x07000000)
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_CTRL_TRIGGER
+// Description : Trigger a watchdog reset
+#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
+#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
+#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
+#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
+#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_CTRL_ENABLE
+// Description : When not enabled the watchdog timer is paused
+#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
+#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
+#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
+#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
+#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_CTRL_PAUSE_DBG1
+// Description : Pause the watchdog timer when processor 1 is in debug mode
+#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
+#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
+#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
+#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_CTRL_PAUSE_DBG0
+// Description : Pause the watchdog timer when processor 0 is in debug mode
+#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
+#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
+#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
+#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_CTRL_PAUSE_JTAG
+// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
+#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
+#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
+#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
+#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
+#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_CTRL_TIME
+// Description : Indicates the number of ticks / 2 (see errata RP2040-E1) before
+// a watchdog reset will be triggered
+#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
+#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
+#define WATCHDOG_CTRL_TIME_MSB _u(23)
+#define WATCHDOG_CTRL_TIME_LSB _u(0)
+#define WATCHDOG_CTRL_TIME_ACCESS "RO"
+// =============================================================================
+// Register : WATCHDOG_LOAD
+// Description : Load the watchdog timer. The maximum setting is 0xffffff which
+// corresponds to 0xffffff / 2 ticks before triggering a watchdog
+// reset (see errata RP2040-E1).
+#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
+#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
+#define WATCHDOG_LOAD_RESET _u(0x00000000)
+#define WATCHDOG_LOAD_MSB _u(23)
+#define WATCHDOG_LOAD_LSB _u(0)
+#define WATCHDOG_LOAD_ACCESS "WF"
+// =============================================================================
+// Register : WATCHDOG_REASON
+// Description : Logs the reason for the last reset. Both bits are zero for the
+// case of a hardware reset.
+#define WATCHDOG_REASON_OFFSET _u(0x00000008)
+#define WATCHDOG_REASON_BITS _u(0x00000003)
+#define WATCHDOG_REASON_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_REASON_FORCE
+// Description : None
+#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
+#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
+#define WATCHDOG_REASON_FORCE_MSB _u(1)
+#define WATCHDOG_REASON_FORCE_LSB _u(1)
+#define WATCHDOG_REASON_FORCE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_REASON_TIMER
+// Description : None
+#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
+#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
+#define WATCHDOG_REASON_TIMER_MSB _u(0)
+#define WATCHDOG_REASON_TIMER_LSB _u(0)
+#define WATCHDOG_REASON_TIMER_ACCESS "RO"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH0
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
+#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH0_MSB _u(31)
+#define WATCHDOG_SCRATCH0_LSB _u(0)
+#define WATCHDOG_SCRATCH0_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH1
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
+#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH1_MSB _u(31)
+#define WATCHDOG_SCRATCH1_LSB _u(0)
+#define WATCHDOG_SCRATCH1_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH2
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
+#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH2_MSB _u(31)
+#define WATCHDOG_SCRATCH2_LSB _u(0)
+#define WATCHDOG_SCRATCH2_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH3
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
+#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH3_MSB _u(31)
+#define WATCHDOG_SCRATCH3_LSB _u(0)
+#define WATCHDOG_SCRATCH3_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH4
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
+#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH4_MSB _u(31)
+#define WATCHDOG_SCRATCH4_LSB _u(0)
+#define WATCHDOG_SCRATCH4_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH5
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
+#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH5_MSB _u(31)
+#define WATCHDOG_SCRATCH5_LSB _u(0)
+#define WATCHDOG_SCRATCH5_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH6
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
+#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH6_MSB _u(31)
+#define WATCHDOG_SCRATCH6_LSB _u(0)
+#define WATCHDOG_SCRATCH6_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_SCRATCH7
+// Description : Scratch register. Information persists through soft reset of
+// the chip.
+#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
+#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
+#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
+#define WATCHDOG_SCRATCH7_MSB _u(31)
+#define WATCHDOG_SCRATCH7_LSB _u(0)
+#define WATCHDOG_SCRATCH7_ACCESS "RW"
+// =============================================================================
+// Register : WATCHDOG_TICK
+// Description : Controls the tick generator
+#define WATCHDOG_TICK_OFFSET _u(0x0000002c)
+#define WATCHDOG_TICK_BITS _u(0x000fffff)
+#define WATCHDOG_TICK_RESET _u(0x00000200)
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_TICK_COUNT
+// Description : Count down timer: the remaining number clk_tick cycles before
+// the next tick is generated.
+#define WATCHDOG_TICK_COUNT_RESET "-"
+#define WATCHDOG_TICK_COUNT_BITS _u(0x000ff800)
+#define WATCHDOG_TICK_COUNT_MSB _u(19)
+#define WATCHDOG_TICK_COUNT_LSB _u(11)
+#define WATCHDOG_TICK_COUNT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_TICK_RUNNING
+// Description : Is the tick generator running?
+#define WATCHDOG_TICK_RUNNING_RESET "-"
+#define WATCHDOG_TICK_RUNNING_BITS _u(0x00000400)
+#define WATCHDOG_TICK_RUNNING_MSB _u(10)
+#define WATCHDOG_TICK_RUNNING_LSB _u(10)
+#define WATCHDOG_TICK_RUNNING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_TICK_ENABLE
+// Description : start / stop tick generation
+#define WATCHDOG_TICK_ENABLE_RESET _u(0x1)
+#define WATCHDOG_TICK_ENABLE_BITS _u(0x00000200)
+#define WATCHDOG_TICK_ENABLE_MSB _u(9)
+#define WATCHDOG_TICK_ENABLE_LSB _u(9)
+#define WATCHDOG_TICK_ENABLE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : WATCHDOG_TICK_CYCLES
+// Description : Total number of clk_tick cycles before the next tick.
+#define WATCHDOG_TICK_CYCLES_RESET _u(0x000)
+#define WATCHDOG_TICK_CYCLES_BITS _u(0x000001ff)
+#define WATCHDOG_TICK_CYCLES_MSB _u(8)
+#define WATCHDOG_TICK_CYCLES_LSB _u(0)
+#define WATCHDOG_TICK_CYCLES_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_WATCHDOG_DEFINED
diff --git a/arkanoid/pico/hardware/regs/xip.h b/arkanoid/pico/hardware/regs/xip.h
new file mode 100644
index 0000000..3964f67
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/xip.h
@@ -0,0 +1,187 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : XIP
+// Version : 1
+// Bus type : ahb
+// Description : QSPI flash execute-in-place block
+// =============================================================================
+#ifndef HARDWARE_REGS_XIP_DEFINED
+#define HARDWARE_REGS_XIP_DEFINED
+// =============================================================================
+// Register : XIP_CTRL
+// Description : Cache control
+#define XIP_CTRL_OFFSET _u(0x00000000)
+#define XIP_CTRL_BITS _u(0x0000000b)
+#define XIP_CTRL_RESET _u(0x00000003)
+// -----------------------------------------------------------------------------
+// Field : XIP_CTRL_POWER_DOWN
+// Description : When 1, the cache memories are powered down. They retain state,
+// but can not be accessed. This reduces static power dissipation.
+// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache
+// cannot
+// be enabled when powered down.
+// Cache-as-SRAM accesses will produce a bus error response when
+// the cache is powered down.
+#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
+#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
+#define XIP_CTRL_POWER_DOWN_MSB _u(3)
+#define XIP_CTRL_POWER_DOWN_LSB _u(3)
+#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : XIP_CTRL_ERR_BADWRITE
+// Description : When 1, writes to any alias other than 0x0 (caching,
+// allocating)
+// will produce a bus fault. When 0, these writes are silently
+// ignored.
+// In either case, writes to the 0x0 alias will deallocate on tag
+// match,
+// as usual.
+#define XIP_CTRL_ERR_BADWRITE_RESET _u(0x1)
+#define XIP_CTRL_ERR_BADWRITE_BITS _u(0x00000002)
+#define XIP_CTRL_ERR_BADWRITE_MSB _u(1)
+#define XIP_CTRL_ERR_BADWRITE_LSB _u(1)
+#define XIP_CTRL_ERR_BADWRITE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : XIP_CTRL_EN
+// Description : When 1, enable the cache. When the cache is disabled, all XIP
+// accesses
+// will go straight to the flash, without querying the cache. When
+// enabled,
+// cacheable XIP accesses will query the cache, and the flash will
+// not be accessed if the tag matches and the valid bit is set.
+//
+// If the cache is enabled, cache-as-SRAM accesses have no effect
+// on the
+// cache data RAM, and will produce a bus error response.
+#define XIP_CTRL_EN_RESET _u(0x1)
+#define XIP_CTRL_EN_BITS _u(0x00000001)
+#define XIP_CTRL_EN_MSB _u(0)
+#define XIP_CTRL_EN_LSB _u(0)
+#define XIP_CTRL_EN_ACCESS "RW"
+// =============================================================================
+// Register : XIP_FLUSH
+// Description : Cache Flush control
+// Write 1 to flush the cache. This clears the tag memory, but
+// the data memory retains its contents. (This means cache-as-SRAM
+// contents is not affected by flush or reset.)
+// Reading will hold the bus (stall the processor) until the flush
+// completes. Alternatively STAT can be polled until completion.
+#define XIP_FLUSH_OFFSET _u(0x00000004)
+#define XIP_FLUSH_BITS _u(0x00000001)
+#define XIP_FLUSH_RESET _u(0x00000000)
+#define XIP_FLUSH_MSB _u(0)
+#define XIP_FLUSH_LSB _u(0)
+#define XIP_FLUSH_ACCESS "SC"
+// =============================================================================
+// Register : XIP_STAT
+// Description : Cache Status
+#define XIP_STAT_OFFSET _u(0x00000008)
+#define XIP_STAT_BITS _u(0x00000007)
+#define XIP_STAT_RESET _u(0x00000002)
+// -----------------------------------------------------------------------------
+// Field : XIP_STAT_FIFO_FULL
+// Description : When 1, indicates the XIP streaming FIFO is completely full.
+// The streaming FIFO is 2 entries deep, so the full and empty
+// flag allow its level to be ascertained.
+#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
+#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
+#define XIP_STAT_FIFO_FULL_MSB _u(2)
+#define XIP_STAT_FIFO_FULL_LSB _u(2)
+#define XIP_STAT_FIFO_FULL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : XIP_STAT_FIFO_EMPTY
+// Description : When 1, indicates the XIP streaming FIFO is completely empty.
+#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
+#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
+#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
+#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
+#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : XIP_STAT_FLUSH_READY
+// Description : Reads as 0 while a cache flush is in progress, and 1 otherwise.
+// The cache is flushed whenever the XIP block is reset, and also
+// when requested via the FLUSH register.
+#define XIP_STAT_FLUSH_READY_RESET _u(0x0)
+#define XIP_STAT_FLUSH_READY_BITS _u(0x00000001)
+#define XIP_STAT_FLUSH_READY_MSB _u(0)
+#define XIP_STAT_FLUSH_READY_LSB _u(0)
+#define XIP_STAT_FLUSH_READY_ACCESS "RO"
+// =============================================================================
+// Register : XIP_CTR_HIT
+// Description : Cache Hit counter
+// A 32 bit saturating counter that increments upon each cache
+// hit,
+// i.e. when an XIP access is serviced directly from cached data.
+// Write any value to clear.
+#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
+#define XIP_CTR_HIT_BITS _u(0xffffffff)
+#define XIP_CTR_HIT_RESET _u(0x00000000)
+#define XIP_CTR_HIT_MSB _u(31)
+#define XIP_CTR_HIT_LSB _u(0)
+#define XIP_CTR_HIT_ACCESS "WC"
+// =============================================================================
+// Register : XIP_CTR_ACC
+// Description : Cache Access counter
+// A 32 bit saturating counter that increments upon each XIP
+// access,
+// whether the cache is hit or not. This includes noncacheable
+// accesses.
+// Write any value to clear.
+#define XIP_CTR_ACC_OFFSET _u(0x00000010)
+#define XIP_CTR_ACC_BITS _u(0xffffffff)
+#define XIP_CTR_ACC_RESET _u(0x00000000)
+#define XIP_CTR_ACC_MSB _u(31)
+#define XIP_CTR_ACC_LSB _u(0)
+#define XIP_CTR_ACC_ACCESS "WC"
+// =============================================================================
+// Register : XIP_STREAM_ADDR
+// Description : FIFO stream address
+// The address of the next word to be streamed from flash to the
+// streaming FIFO.
+// Increments automatically after each flash access.
+// Write the initial access address here before starting a
+// streaming read.
+#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
+#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
+#define XIP_STREAM_ADDR_RESET _u(0x00000000)
+#define XIP_STREAM_ADDR_MSB _u(31)
+#define XIP_STREAM_ADDR_LSB _u(2)
+#define XIP_STREAM_ADDR_ACCESS "RW"
+// =============================================================================
+// Register : XIP_STREAM_CTR
+// Description : FIFO stream control
+// Write a nonzero value to start a streaming read. This will then
+// progress in the background, using flash idle cycles to transfer
+// a linear data block from flash to the streaming FIFO.
+// Decrements automatically (1 at a time) as the stream
+// progresses, and halts on reaching 0.
+// Write 0 to halt an in-progress stream, and discard any
+// in-flight
+// read, so that a new stream can immediately be started (after
+// draining the FIFO and reinitialising STREAM_ADDR)
+#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
+#define XIP_STREAM_CTR_BITS _u(0x003fffff)
+#define XIP_STREAM_CTR_RESET _u(0x00000000)
+#define XIP_STREAM_CTR_MSB _u(21)
+#define XIP_STREAM_CTR_LSB _u(0)
+#define XIP_STREAM_CTR_ACCESS "RW"
+// =============================================================================
+// Register : XIP_STREAM_FIFO
+// Description : FIFO stream data
+// Streamed data is buffered here, for retrieval by the system
+// DMA.
+// This FIFO can also be accessed via the XIP_AUX slave, to avoid
+// exposing
+// the DMA to bus stalls caused by other XIP traffic.
+#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
+#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
+#define XIP_STREAM_FIFO_RESET _u(0x00000000)
+#define XIP_STREAM_FIFO_MSB _u(31)
+#define XIP_STREAM_FIFO_LSB _u(0)
+#define XIP_STREAM_FIFO_ACCESS "RF"
+// =============================================================================
+#endif // HARDWARE_REGS_XIP_DEFINED
diff --git a/arkanoid/pico/hardware/regs/xosc.h b/arkanoid/pico/hardware/regs/xosc.h
new file mode 100644
index 0000000..ec84d3d
--- /dev/null
+++ b/arkanoid/pico/hardware/regs/xosc.h
@@ -0,0 +1,160 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : XOSC
+// Version : 1
+// Bus type : apb
+// Description : Controls the crystal oscillator
+// =============================================================================
+#ifndef HARDWARE_REGS_XOSC_DEFINED
+#define HARDWARE_REGS_XOSC_DEFINED
+// =============================================================================
+// Register : XOSC_CTRL
+// Description : Crystal Oscillator Control
+#define XOSC_CTRL_OFFSET _u(0x00000000)
+#define XOSC_CTRL_BITS _u(0x00ffffff)
+#define XOSC_CTRL_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : XOSC_CTRL_ENABLE
+// Description : On power-up this field is initialised to DISABLE and the chip
+// runs from the ROSC.
+// If the chip has subsequently been programmed to run from the
+// XOSC then setting this field to DISABLE may lock-up the chip.
+// If this is a concern then run the clk_ref from the ROSC and
+// enable the clk_sys RESUS feature.
+// The 12-bit code is intended to give some protection against
+// accidental writes. An invalid setting will enable the
+// oscillator.
+// 0xd1e -> DISABLE
+// 0xfab -> ENABLE
+#define XOSC_CTRL_ENABLE_RESET "-"
+#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000)
+#define XOSC_CTRL_ENABLE_MSB _u(23)
+#define XOSC_CTRL_ENABLE_LSB _u(12)
+#define XOSC_CTRL_ENABLE_ACCESS "RW"
+#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
+#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
+// -----------------------------------------------------------------------------
+// Field : XOSC_CTRL_FREQ_RANGE
+// Description : Frequency range. This resets to 0xAA0 and cannot be changed.
+// 0xaa0 -> 1_15MHZ
+// 0xaa1 -> RESERVED_1
+// 0xaa2 -> RESERVED_2
+// 0xaa3 -> RESERVED_3
+#define XOSC_CTRL_FREQ_RANGE_RESET "-"
+#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
+#define XOSC_CTRL_FREQ_RANGE_MSB _u(11)
+#define XOSC_CTRL_FREQ_RANGE_LSB _u(0)
+#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
+#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_1 _u(0xaa1)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_2 _u(0xaa2)
+#define XOSC_CTRL_FREQ_RANGE_VALUE_RESERVED_3 _u(0xaa3)
+// =============================================================================
+// Register : XOSC_STATUS
+// Description : Crystal Oscillator Status
+#define XOSC_STATUS_OFFSET _u(0x00000004)
+#define XOSC_STATUS_BITS _u(0x81001003)
+#define XOSC_STATUS_RESET _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field : XOSC_STATUS_STABLE
+// Description : Oscillator is running and stable
+#define XOSC_STATUS_STABLE_RESET _u(0x0)
+#define XOSC_STATUS_STABLE_BITS _u(0x80000000)
+#define XOSC_STATUS_STABLE_MSB _u(31)
+#define XOSC_STATUS_STABLE_LSB _u(31)
+#define XOSC_STATUS_STABLE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : XOSC_STATUS_BADWRITE
+// Description : An invalid value has been written to CTRL_ENABLE or
+// CTRL_FREQ_RANGE or DORMANT
+#define XOSC_STATUS_BADWRITE_RESET _u(0x0)
+#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000)
+#define XOSC_STATUS_BADWRITE_MSB _u(24)
+#define XOSC_STATUS_BADWRITE_LSB _u(24)
+#define XOSC_STATUS_BADWRITE_ACCESS "WC"
+// -----------------------------------------------------------------------------
+// Field : XOSC_STATUS_ENABLED
+// Description : Oscillator is enabled but not necessarily running and stable,
+// resets to 0
+#define XOSC_STATUS_ENABLED_RESET "-"
+#define XOSC_STATUS_ENABLED_BITS _u(0x00001000)
+#define XOSC_STATUS_ENABLED_MSB _u(12)
+#define XOSC_STATUS_ENABLED_LSB _u(12)
+#define XOSC_STATUS_ENABLED_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field : XOSC_STATUS_FREQ_RANGE
+// Description : The current frequency range setting, always reads 0
+// 0x0 -> 1_15MHZ
+// 0x1 -> RESERVED_1
+// 0x2 -> RESERVED_2
+// 0x3 -> RESERVED_3
+#define XOSC_STATUS_FREQ_RANGE_RESET "-"
+#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003)
+#define XOSC_STATUS_FREQ_RANGE_MSB _u(1)
+#define XOSC_STATUS_FREQ_RANGE_LSB _u(0)
+#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
+#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_1 _u(0x1)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_2 _u(0x2)
+#define XOSC_STATUS_FREQ_RANGE_VALUE_RESERVED_3 _u(0x3)
+// =============================================================================
+// Register : XOSC_DORMANT
+// Description : Crystal Oscillator pause control
+// This is used to save power by pausing the XOSC
+// On power-up this field is initialised to WAKE
+// An invalid write will also select WAKE
+// WARNING: stop the PLLs before selecting dormant mode
+// WARNING: setup the irq before selecting dormant mode
+// 0x636f6d61 -> DORMANT
+// 0x77616b65 -> WAKE
+#define XOSC_DORMANT_OFFSET _u(0x00000008)
+#define XOSC_DORMANT_BITS _u(0xffffffff)
+#define XOSC_DORMANT_RESET "-"
+#define XOSC_DORMANT_MSB _u(31)
+#define XOSC_DORMANT_LSB _u(0)
+#define XOSC_DORMANT_ACCESS "RW"
+#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
+#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
+// =============================================================================
+// Register : XOSC_STARTUP
+// Description : Controls the startup delay
+#define XOSC_STARTUP_OFFSET _u(0x0000000c)
+#define XOSC_STARTUP_BITS _u(0x00103fff)
+#define XOSC_STARTUP_RESET _u(0x000000c4)
+// -----------------------------------------------------------------------------
+// Field : XOSC_STARTUP_X4
+// Description : Multiplies the startup_delay by 4. This is of little value to
+// the user given that the delay can be programmed directly.
+#define XOSC_STARTUP_X4_RESET _u(0x0)
+#define XOSC_STARTUP_X4_BITS _u(0x00100000)
+#define XOSC_STARTUP_X4_MSB _u(20)
+#define XOSC_STARTUP_X4_LSB _u(20)
+#define XOSC_STARTUP_X4_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field : XOSC_STARTUP_DELAY
+// Description : in multiples of 256*xtal_period. The reset value of 0xc4
+// corresponds to approx 50 000 cycles.
+#define XOSC_STARTUP_DELAY_RESET _u(0x00c4)
+#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
+#define XOSC_STARTUP_DELAY_MSB _u(13)
+#define XOSC_STARTUP_DELAY_LSB _u(0)
+#define XOSC_STARTUP_DELAY_ACCESS "RW"
+// =============================================================================
+// Register : XOSC_COUNT
+// Description : A down counter running at the xosc frequency which counts to
+// zero and stops.
+// To start the counter write a non-zero value.
+// Can be used for short software pauses when setting up time
+// sensitive hardware.
+#define XOSC_COUNT_OFFSET _u(0x0000001c)
+#define XOSC_COUNT_BITS _u(0x000000ff)
+#define XOSC_COUNT_RESET _u(0x00000000)
+#define XOSC_COUNT_MSB _u(7)
+#define XOSC_COUNT_LSB _u(0)
+#define XOSC_COUNT_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_XOSC_DEFINED
diff --git a/arkanoid/pico/hardware/resets.h b/arkanoid/pico/hardware/resets.h
new file mode 100644
index 0000000..213dbe6
--- /dev/null
+++ b/arkanoid/pico/hardware/resets.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_RESETS_H
+#define _HARDWARE_RESETS_H
+
+#include "../pico.h"
+#include "structs/resets.h"
+
+/** \file resets.h
+ * \defgroup hardware_resets hardware_resets
+ *
+ * Hardware Reset API
+ *
+ * The reset controller allows software control of the resets to all of the peripherals that are not
+ * critical to boot the processor in the RP2040.
+ *
+ * \subsubsection reset_bitmask
+ * \addtogroup hardware_resets
+ *
+ * Multiple blocks are referred to using a bitmask as follows:
+ *
+ * Block to reset | Bit
+ * ---------------|----
+ * USB | 24
+ * UART 1 | 23
+ * UART 0 | 22
+ * Timer | 21
+ * TB Manager | 20
+ * SysInfo | 19
+ * System Config | 18
+ * SPI 1 | 17
+ * SPI 0 | 16
+ * RTC | 15
+ * PWM | 14
+ * PLL USB | 13
+ * PLL System | 12
+ * PIO 1 | 11
+ * PIO 0 | 10
+ * Pads - QSPI | 9
+ * Pads - bank 0 | 8
+ * JTAG | 7
+ * IO Bank 1 | 6
+ * IO Bank 0 | 5
+ * I2C 1 | 4
+ * I2C 0 | 3
+ * DMA | 2
+ * Bus Control | 1
+ * ADC 0 | 0
+ *
+ * \subsection reset_example Example
+ * \addtogroup hardware_resets
+ * \include hello_reset.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/// \tag::reset_funcs[]
+
+/*! \brief Reset the specified HW blocks
+ * \ingroup hardware_resets
+ *
+ * \param bits Bit pattern indicating blocks to reset. See \ref reset_bitmask
+ */
+static inline void reset_block(uint32_t bits) {
+ hw_set_bits(&resets_hw->reset, bits);
+}
+
+/*! \brief bring specified HW blocks out of reset
+ * \ingroup hardware_resets
+ *
+ * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask
+ */
+static inline void unreset_block(uint32_t bits) {
+ hw_clear_bits(&resets_hw->reset, bits);
+}
+
+/*! \brief Bring specified HW blocks out of reset and wait for completion
+ * \ingroup hardware_resets
+ *
+ * \param bits Bit pattern indicating blocks to unreset. See \ref reset_bitmask
+ */
+static inline void unreset_block_wait(uint32_t bits) {
+ hw_clear_bits(&resets_hw->reset, bits);
+ while (~resets_hw->reset_done & bits)
+ tight_loop_contents();
+}
+/// \end::reset_funcs[]
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/rtc.c b/arkanoid/pico/hardware/rtc.c
new file mode 100644
index 0000000..f3d2c12
--- /dev/null
+++ b/arkanoid/pico/hardware/rtc.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../pico.h"
+
+#include "irq.h"
+#include "rtc.h"
+#include "resets.h"
+#include "clocks.h"
+
+// Set this when setting an alarm
+static rtc_callback_t _callback = NULL;
+static bool _alarm_repeats = false;
+
+bool rtc_running(void) {
+ return (rtc_hw->ctrl & RTC_CTRL_RTC_ACTIVE_BITS);
+}
+
+void rtc_init(void) {
+ // Get clk_rtc freq and make sure it is running
+ uint rtc_freq = clock_get_hz(clk_rtc);
+ assert(rtc_freq != 0);
+
+ // Take rtc out of reset now that we know clk_rtc is running
+ reset_block(RESETS_RESET_RTC_BITS);
+ unreset_block_wait(RESETS_RESET_RTC_BITS);
+
+ // Set up the 1 second divider.
+ // If rtc_freq is 400 then clkdiv_m1 should be 399
+ rtc_freq -= 1;
+
+ // Check the freq is not too big to divide
+ assert(rtc_freq <= RTC_CLKDIV_M1_BITS);
+
+ // Write divide value
+ rtc_hw->clkdiv_m1 = rtc_freq;
+}
+
+static bool valid_datetime(datetime_t *t) {
+ // Valid ranges taken from RTC doc. Note when setting an RTC alarm
+ // these values are allowed to be -1 to say "don't match this value"
+ if (!(t->year >= 0 && t->year <= 4095)) return false;
+ if (!(t->month >= 1 && t->month <= 12)) return false;
+ if (!(t->day >= 1 && t->day <= 31)) return false;
+ if (!(t->dotw >= 0 && t->dotw <= 6)) return false;
+ if (!(t->hour >= 0 && t->hour <= 23)) return false;
+ if (!(t->min >= 0 && t->min <= 59)) return false;
+ if (!(t->sec >= 0 && t->sec <= 59)) return false;
+ return true;
+}
+
+bool rtc_set_datetime(datetime_t *t) {
+ if (!valid_datetime(t)) {
+ return false;
+ }
+
+ // Disable RTC
+ rtc_hw->ctrl = 0;
+ // Wait while it is still active
+ while (rtc_running()) {
+ tight_loop_contents();
+ }
+
+ // Write to setup registers
+ rtc_hw->setup_0 = (((uint)t->year) << RTC_SETUP_0_YEAR_LSB ) |
+ (((uint)t->month) << RTC_SETUP_0_MONTH_LSB) |
+ (((uint)t->day) << RTC_SETUP_0_DAY_LSB);
+ rtc_hw->setup_1 = (((uint)t->dotw) << RTC_SETUP_1_DOTW_LSB) |
+ (((uint)t->hour) << RTC_SETUP_1_HOUR_LSB) |
+ (((uint)t->min) << RTC_SETUP_1_MIN_LSB) |
+ (((uint)t->sec) << RTC_SETUP_1_SEC_LSB);
+
+ // Load setup values into rtc clock domain
+ rtc_hw->ctrl = RTC_CTRL_LOAD_BITS;
+
+ // Enable RTC and wait for it to be running
+ rtc_hw->ctrl = RTC_CTRL_RTC_ENABLE_BITS;
+ while (!rtc_running()) {
+ tight_loop_contents();
+ }
+
+ return true;
+}
+
+bool rtc_get_datetime(datetime_t *t) {
+ // Make sure RTC is running
+ if (!rtc_running()) {
+ return false;
+ }
+
+ // Note: RTC_0 should be read before RTC_1
+ uint32_t rtc_0 = rtc_hw->rtc_0;
+ uint32_t rtc_1 = rtc_hw->rtc_1;
+
+ t->dotw = (rtc_0 & RTC_RTC_0_DOTW_BITS ) >> RTC_RTC_0_DOTW_LSB;
+ t->hour = (rtc_0 & RTC_RTC_0_HOUR_BITS ) >> RTC_RTC_0_HOUR_LSB;
+ t->min = (rtc_0 & RTC_RTC_0_MIN_BITS ) >> RTC_RTC_0_MIN_LSB;
+ t->sec = (rtc_0 & RTC_RTC_0_SEC_BITS ) >> RTC_RTC_0_SEC_LSB;
+ t->year = (rtc_1 & RTC_RTC_1_YEAR_BITS ) >> RTC_RTC_1_YEAR_LSB;
+ t->month = (rtc_1 & RTC_RTC_1_MONTH_BITS) >> RTC_RTC_1_MONTH_LSB;
+ t->day = (rtc_1 & RTC_RTC_1_DAY_BITS ) >> RTC_RTC_1_DAY_LSB;
+
+ return true;
+}
+
+void rtc_enable_alarm(void) {
+ // Set matching and wait for it to be enabled
+ hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS);
+ while(!(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS)) {
+ tight_loop_contents();
+ }
+}
+
+static void rtc_irq_handler(void) {
+ // Always disable the alarm to clear the current IRQ.
+ // Even if it is a repeatable alarm, we don't want it to keep firing.
+ // If it matches on a second it can keep firing for that second.
+ rtc_disable_alarm();
+
+ if (_alarm_repeats) {
+ // If it is a repeatable alarm, re enable the alarm.
+ rtc_enable_alarm();
+ }
+
+ // Call user callback function
+ if (_callback) {
+ _callback();
+ }
+}
+
+static bool rtc_alarm_repeats(datetime_t *t) {
+ // If any value is set to -1 then we don't match on that value
+ // hence the alarm will eventually repeat
+ if (t->year < 0) return true;
+ if (t->month < 0) return true;
+ if (t->day < 0) return true;
+ if (t->dotw < 0) return true;
+ if (t->hour < 0) return true;
+ if (t->min < 0) return true;
+ if (t->sec < 0) return true;
+ return false;
+}
+
+void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback) {
+ rtc_disable_alarm();
+
+ // Only add to setup if it isn't -1
+ rtc_hw->irq_setup_0 = ((t->year < 0) ? 0 : (((uint)t->year) << RTC_IRQ_SETUP_0_YEAR_LSB )) |
+ ((t->month < 0) ? 0 : (((uint)t->month) << RTC_IRQ_SETUP_0_MONTH_LSB)) |
+ ((t->day < 0) ? 0 : (((uint)t->day) << RTC_IRQ_SETUP_0_DAY_LSB ));
+ rtc_hw->irq_setup_1 = ((t->dotw < 0) ? 0 : (((uint)t->dotw) << RTC_IRQ_SETUP_1_DOTW_LSB)) |
+ ((t->hour < 0) ? 0 : (((uint)t->hour) << RTC_IRQ_SETUP_1_HOUR_LSB)) |
+ ((t->min < 0) ? 0 : (((uint)t->min) << RTC_IRQ_SETUP_1_MIN_LSB )) |
+ ((t->sec < 0) ? 0 : (((uint)t->sec) << RTC_IRQ_SETUP_1_SEC_LSB ));
+
+ // Set the match enable bits for things we care about
+ if (t->year >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_YEAR_ENA_BITS);
+ if (t->month >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MONTH_ENA_BITS);
+ if (t->day >= 0) hw_set_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_DAY_ENA_BITS);
+ if (t->dotw >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_DOTW_ENA_BITS);
+ if (t->hour >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_HOUR_ENA_BITS);
+ if (t->min >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_MIN_ENA_BITS);
+ if (t->sec >= 0) hw_set_bits(&rtc_hw->irq_setup_1, RTC_IRQ_SETUP_1_SEC_ENA_BITS);
+
+ // Does it repeat? I.e. do we not match on any of the bits
+ _alarm_repeats = rtc_alarm_repeats(t);
+
+ // Store function pointer we can call later
+ _callback = user_callback;
+
+ irq_set_exclusive_handler(RTC_IRQ, rtc_irq_handler);
+
+ // Enable the IRQ at the peri
+ rtc_hw->inte = RTC_INTE_RTC_BITS;
+
+ // Enable the IRQ at the proc
+ irq_set_enabled(RTC_IRQ, true);
+
+ rtc_enable_alarm();
+}
+
+void rtc_disable_alarm(void) {
+ // Disable matching and wait for it to stop being active
+ hw_clear_bits(&rtc_hw->irq_setup_0, RTC_IRQ_SETUP_0_MATCH_ENA_BITS);
+ while(rtc_hw->irq_setup_0 & RTC_IRQ_SETUP_0_MATCH_ACTIVE_BITS) {
+ tight_loop_contents();
+ }
+}
diff --git a/arkanoid/pico/hardware/rtc.h b/arkanoid/pico/hardware/rtc.h
new file mode 100644
index 0000000..5ec08a5
--- /dev/null
+++ b/arkanoid/pico/hardware/rtc.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_RTC_H
+#define _HARDWARE_RTC_H
+
+#include "../pico.h"
+#include "structs/rtc.h"
+
+/** \file rtc.h
+ * \defgroup hardware_rtc hardware_rtc
+ *
+ * Hardware Real Time Clock API
+ *
+ * The RTC keeps track of time in human readable format and generates events when the time is equal
+ * to a preset value. Think of a digital clock, not epoch time used by most computers. There are seven
+ * fields, one each for year (12 bit), month (4 bit), day (5 bit), day of the week (3 bit), hour (5 bit)
+ * minute (6 bit) and second (6 bit), storing the data in binary format.
+ *
+ * \sa datetime_t
+ *
+ * \subsection rtc_example Example
+ * \addtogroup hardware_rtc
+ *
+ * \include hello_rtc.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! Callback function type for RTC alarms
+ * \ingroup hardware_rtc
+ *
+ * \sa rtc_set_alarm()
+ */
+typedef void (*rtc_callback_t)(void);
+
+/*! \brief Initialise the RTC system
+ * \ingroup hardware_rtc
+ */
+void rtc_init(void);
+
+/*! \brief Set the RTC to the specified time
+ * \ingroup hardware_rtc
+ *
+ * \param t Pointer to a \ref datetime_t structure contains time to set
+ * \return true if set, false if the passed in datetime was invalid.
+ */
+bool rtc_set_datetime(datetime_t *t);
+
+/*! \brief Get the current time from the RTC
+ * \ingroup hardware_rtc
+ *
+ * \param t Pointer to a \ref datetime_t structure to receive the current RTC time
+ * \return true if datetime is valid, false if the RTC is not running.
+ */
+bool rtc_get_datetime(datetime_t *t);
+
+/*! \brief Is the RTC running?
+ * \ingroup hardware_rtc
+ *
+ */
+bool rtc_running(void);
+
+/*! \brief Set a time in the future for the RTC to call a user provided callback
+ * \ingroup hardware_rtc
+ *
+ * \param t Pointer to a \ref datetime_t structure containing a time in the future to fire the alarm. Any values set to -1 will not be matched on.
+ * \param user_callback pointer to a \ref rtc_callback_t to call when the alarm fires
+ */
+void rtc_set_alarm(datetime_t *t, rtc_callback_t user_callback);
+
+/*! \brief Enable the RTC alarm (if inactive)
+ * \ingroup hardware_rtc
+ */
+void rtc_enable_alarm(void);
+
+/*! \brief Disable the RTC alarm (if active)
+ * \ingroup hardware_rtc
+ */
+void rtc_disable_alarm(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/spi.c b/arkanoid/pico/hardware/spi.c
new file mode 100644
index 0000000..76a729d
--- /dev/null
+++ b/arkanoid/pico/hardware/spi.c
@@ -0,0 +1,212 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "resets.h"
+#include "clocks.h"
+#include "spi.h"
+
+static inline void spi_reset(spi_inst_t *spi) {
+ invalid_params_if(SPI, spi != spi0 && spi != spi1);
+ reset_block(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS);
+}
+
+static inline void spi_unreset(spi_inst_t *spi) {
+ invalid_params_if(SPI, spi != spi0 && spi != spi1);
+ unreset_block_wait(spi == spi0 ? RESETS_RESET_SPI0_BITS : RESETS_RESET_SPI1_BITS);
+}
+
+uint spi_init(spi_inst_t *spi, uint baudrate) {
+ spi_reset(spi);
+ spi_unreset(spi);
+
+ uint baud = spi_set_baudrate(spi, baudrate);
+ spi_set_format(spi, 8, SPI_CPOL_0, SPI_CPHA_0, SPI_MSB_FIRST);
+ // Always enable DREQ signals -- harmless if DMA is not listening
+ hw_set_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS);
+
+ // Finally enable the SPI
+ hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
+ return baud;
+}
+
+void spi_deinit(spi_inst_t *spi) {
+ hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_SSE_BITS);
+ hw_clear_bits(&spi_get_hw(spi)->dmacr, SPI_SSPDMACR_TXDMAE_BITS | SPI_SSPDMACR_RXDMAE_BITS);
+ spi_reset(spi);
+}
+
+uint spi_set_baudrate(spi_inst_t *spi, uint baudrate) {
+ uint freq_in = clock_get_hz(clk_peri);
+ uint prescale, postdiv;
+ invalid_params_if(SPI, baudrate > freq_in);
+
+ // Find smallest prescale value which puts output frequency in range of
+ // post-divide. Prescale is an even number from 2 to 254 inclusive.
+ for (prescale = 2; prescale <= 254; prescale += 2) {
+ if (freq_in < (prescale + 2) * 256 * (uint64_t) baudrate)
+ break;
+ }
+ invalid_params_if(SPI, prescale > 254); // Frequency too low
+
+ // Find largest post-divide which makes output <= baudrate. Post-divide is
+ // an integer in the range 1 to 256 inclusive.
+ for (postdiv = 256; postdiv > 1; --postdiv) {
+ if (freq_in / (prescale * (postdiv - 1)) > baudrate)
+ break;
+ }
+
+ spi_get_hw(spi)->cpsr = prescale;
+ hw_write_masked(&spi_get_hw(spi)->cr0, (postdiv - 1) << SPI_SSPCR0_SCR_LSB, SPI_SSPCR0_SCR_BITS);
+
+ // Return the frequency we were able to achieve
+ return freq_in / (prescale * postdiv);
+}
+
+uint spi_get_baudrate(const spi_inst_t *spi) {
+ uint prescale = spi_get_const_hw(spi)->cpsr;
+ uint postdiv = ((spi_get_const_hw(spi)->cr0 & SPI_SSPCR0_SCR_BITS) >> SPI_SSPCR0_SCR_LSB) + 1;
+ return clock_get_hz(clk_peri) / (prescale * postdiv);
+}
+
+// Write len bytes from src to SPI. Simultaneously read len bytes from SPI to dst.
+// Note this function is guaranteed to exit in a known amount of time (bits sent * time per bit)
+int __not_in_flash_func(spi_write_read_blocking)(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len) {
+ invalid_params_if(SPI, 0 > (int)len);
+
+ // Never have more transfers in flight than will fit into the RX FIFO,
+ // else FIFO will overflow if this code is heavily interrupted.
+ const size_t fifo_depth = 8;
+ size_t rx_remaining = len, tx_remaining = len;
+
+ while (rx_remaining || tx_remaining) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+ spi_get_hw(spi)->dr = (uint32_t) *src++;
+ --tx_remaining;
+ }
+ if (rx_remaining && spi_is_readable(spi)) {
+ *dst++ = (uint8_t) spi_get_hw(spi)->dr;
+ --rx_remaining;
+ }
+ }
+
+ return (int)len;
+}
+
+// Write len bytes directly from src to the SPI, and discard any data received back
+int __not_in_flash_func(spi_write_blocking)(spi_inst_t *spi, const uint8_t *src, size_t len) {
+ invalid_params_if(SPI, 0 > (int)len);
+ // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX
+ // is full, PL022 inhibits RX pushes, and sets a sticky flag on
+ // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set.
+ for (size_t i = 0; i < len; ++i) {
+ while (!spi_is_writable(spi))
+ tight_loop_contents();
+ spi_get_hw(spi)->dr = (uint32_t)src[i];
+ }
+ // Drain RX FIFO, then wait for shifting to finish (which may be *after*
+ // TX FIFO drains), then drain RX FIFO again
+ while (spi_is_readable(spi))
+ (void)spi_get_hw(spi)->dr;
+ while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS)
+ tight_loop_contents();
+ while (spi_is_readable(spi))
+ (void)spi_get_hw(spi)->dr;
+
+ // Don't leave overrun flag set
+ spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS;
+
+ return (int)len;
+}
+
+// Read len bytes directly from the SPI to dst.
+// repeated_tx_data is output repeatedly on SO as data is read in from SI.
+// Generally this can be 0, but some devices require a specific value here,
+// e.g. SD cards expect 0xff
+int __not_in_flash_func(spi_read_blocking)(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len) {
+ invalid_params_if(SPI, 0 > (int)len);
+ const size_t fifo_depth = 8;
+ size_t rx_remaining = len, tx_remaining = len;
+
+ while (rx_remaining || tx_remaining) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+ spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data;
+ --tx_remaining;
+ }
+ if (rx_remaining && spi_is_readable(spi)) {
+ *dst++ = (uint8_t) spi_get_hw(spi)->dr;
+ --rx_remaining;
+ }
+ }
+
+ return (int)len;
+}
+
+// Write len halfwords from src to SPI. Simultaneously read len halfwords from SPI to dst.
+int __not_in_flash_func(spi_write16_read16_blocking)(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len) {
+ invalid_params_if(SPI, 0 > (int)len);
+ // Never have more transfers in flight than will fit into the RX FIFO,
+ // else FIFO will overflow if this code is heavily interrupted.
+ const size_t fifo_depth = 8;
+ size_t rx_remaining = len, tx_remaining = len;
+
+ while (rx_remaining || tx_remaining) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+ spi_get_hw(spi)->dr = (uint32_t) *src++;
+ --tx_remaining;
+ }
+ if (rx_remaining && spi_is_readable(spi)) {
+ *dst++ = (uint16_t) spi_get_hw(spi)->dr;
+ --rx_remaining;
+ }
+ }
+
+ return (int)len;
+}
+
+// Write len bytes directly from src to the SPI, and discard any data received back
+int __not_in_flash_func(spi_write16_blocking)(spi_inst_t *spi, const uint16_t *src, size_t len) {
+ invalid_params_if(SPI, 0 > (int)len);
+ // Deliberately overflow FIFO, then clean up afterward, to minimise amount
+ // of APB polling required per halfword
+ for (size_t i = 0; i < len; ++i) {
+ while (!spi_is_writable(spi))
+ tight_loop_contents();
+ spi_get_hw(spi)->dr = (uint32_t)src[i];
+ }
+
+ while (spi_is_readable(spi))
+ (void)spi_get_hw(spi)->dr;
+ while (spi_get_hw(spi)->sr & SPI_SSPSR_BSY_BITS)
+ tight_loop_contents();
+ while (spi_is_readable(spi))
+ (void)spi_get_hw(spi)->dr;
+
+ // Don't leave overrun flag set
+ spi_get_hw(spi)->icr = SPI_SSPICR_RORIC_BITS;
+
+ return (int)len;
+}
+
+// Read len halfwords directly from the SPI to dst.
+// repeated_tx_data is output repeatedly on SO as data is read in from SI.
+int __not_in_flash_func(spi_read16_blocking)(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len) {
+ invalid_params_if(SPI, 0 > (int)len);
+ const size_t fifo_depth = 8;
+ size_t rx_remaining = len, tx_remaining = len;
+
+ while (rx_remaining || tx_remaining) {
+ if (tx_remaining && spi_is_writable(spi) && rx_remaining < tx_remaining + fifo_depth) {
+ spi_get_hw(spi)->dr = (uint32_t) repeated_tx_data;
+ --tx_remaining;
+ }
+ if (rx_remaining && spi_is_readable(spi)) {
+ *dst++ = (uint16_t) spi_get_hw(spi)->dr;
+ --rx_remaining;
+ }
+ }
+
+ return (int)len;
+}
diff --git a/arkanoid/pico/hardware/spi.h b/arkanoid/pico/hardware/spi.h
new file mode 100644
index 0000000..dabcc7c
--- /dev/null
+++ b/arkanoid/pico/hardware/spi.h
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_SPI_H
+#define _HARDWARE_SPI_H
+
+#include "../pico.h"
+#include "../time.h"
+#include "structs/spi.h"
+#include "regs/dreq.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SPI, Enable/disable assertions in the SPI module, type=bool, default=0, group=hardware_spi
+#ifndef PARAM_ASSERTIONS_ENABLED_SPI
+#define PARAM_ASSERTIONS_ENABLED_SPI 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file spi.h
+ * \defgroup hardware_spi hardware_spi
+ *
+ * Hardware SPI API
+ *
+ * RP2040 has 2 identical instances of the Serial Peripheral Interface (SPI) controller.
+ *
+ * The PrimeCell SSP is a master or slave interface for synchronous serial communication with peripheral devices that have
+ * Motorola SPI, National Semiconductor Microwire, or Texas Instruments synchronous serial interfaces.
+ *
+ * Controller can be defined as master or slave using the \ref spi_set_slave function.
+ *
+ * Each controller can be connected to a number of GPIO pins, see the datasheet GPIO function selection table for more information.
+ */
+
+// PICO_CONFIG: PICO_DEFAULT_SPI, Define the default SPI for a board, min=0, max=1, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_SCK_PIN, Define the default SPI SCK pin, min=0, max=29, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_TX_PIN, Define the default SPI TX pin, min=0, max=29, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_RX_PIN, Define the default SPI RX pin, min=0, max=29, group=hardware_spi
+// PICO_CONFIG: PICO_DEFAULT_SPI_CSN_PIN, Define the default SPI CSN pin, min=0, max=29, group=hardware_spi
+
+/**
+ * Opaque type representing an SPI instance.
+ */
+typedef struct spi_inst spi_inst_t;
+
+/** Identifier for the first (SPI 0) hardware SPI instance (for use in SPI functions).
+ *
+ * e.g. spi_init(spi0, 48000)
+ *
+ * \ingroup hardware_spi
+ */
+#define spi0 ((spi_inst_t * const)spi0_hw)
+
+/** Identifier for the second (SPI 1) hardware SPI instance (for use in SPI functions).
+ *
+ * e.g. spi_init(spi1, 48000)
+ *
+ * \ingroup hardware_spi
+ */
+#define spi1 ((spi_inst_t * const)spi1_hw)
+
+#if !defined(PICO_DEFAULT_SPI_INSTANCE) && defined(PICO_DEFAULT_SPI)
+#define PICO_DEFAULT_SPI_INSTANCE (__CONCAT(spi,PICO_DEFAULT_SPI))
+#endif
+
+#ifdef PICO_DEFAULT_SPI_INSTANCE
+#define spi_default PICO_DEFAULT_SPI_INSTANCE
+#endif
+
+/** \brief Enumeration of SPI CPHA (clock phase) values.
+ * \ingroup hardware_spi
+ */
+typedef enum {
+ SPI_CPHA_0 = 0,
+ SPI_CPHA_1 = 1
+} spi_cpha_t;
+
+/** \brief Enumeration of SPI CPOL (clock polarity) values.
+ * \ingroup hardware_spi
+ */
+typedef enum {
+ SPI_CPOL_0 = 0,
+ SPI_CPOL_1 = 1
+} spi_cpol_t;
+
+/** \brief Enumeration of SPI bit-order values.
+ * \ingroup hardware_spi
+ */
+typedef enum {
+ SPI_LSB_FIRST = 0,
+ SPI_MSB_FIRST = 1
+} spi_order_t;
+
+// ----------------------------------------------------------------------------
+// Setup
+
+/*! \brief Initialise SPI instances
+ * \ingroup hardware_spi
+ * Puts the SPI into a known state, and enable it. Must be called before other
+ * functions.
+ *
+ * \note There is no guarantee that the baudrate requested can be achieved exactly; the nearest will be chosen
+ * and returned
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param baudrate Baudrate requested in Hz
+ * \return the actual baud rate set
+ */
+uint spi_init(spi_inst_t *spi, uint baudrate);
+
+/*! \brief Deinitialise SPI instances
+ * \ingroup hardware_spi
+ * Puts the SPI into a disabled state. Init will need to be called to reenable the device
+ * functions.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ */
+void spi_deinit(spi_inst_t *spi);
+
+/*! \brief Set SPI baudrate
+ * \ingroup hardware_spi
+ *
+ * Set SPI frequency as close as possible to baudrate, and return the actual
+ * achieved rate.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param baudrate Baudrate required in Hz, should be capable of a bitrate of at least 2Mbps, or higher, depending on system clock settings.
+ * \return The actual baudrate set
+ */
+uint spi_set_baudrate(spi_inst_t *spi, uint baudrate);
+
+/*! \brief Get SPI baudrate
+ * \ingroup hardware_spi
+ *
+ * Get SPI baudrate which was set by \see spi_set_baudrate
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return The actual baudrate set
+ */
+uint spi_get_baudrate(const spi_inst_t *spi);
+
+/*! \brief Convert SPI instance to hardware instance number
+ * \ingroup hardware_spi
+ *
+ * \param spi SPI instance
+ * \return Number of SPI, 0 or 1.
+ */
+static inline uint spi_get_index(const spi_inst_t *spi) {
+ invalid_params_if(SPI, spi != spi0 && spi != spi1);
+ return spi == spi1 ? 1 : 0;
+}
+
+static inline spi_hw_t *spi_get_hw(spi_inst_t *spi) {
+ spi_get_index(spi); // check it is a hw spi
+ return (spi_hw_t *)spi;
+}
+
+static inline const spi_hw_t *spi_get_const_hw(const spi_inst_t *spi) {
+ spi_get_index(spi); // check it is a hw spi
+ return (const spi_hw_t *)spi;
+}
+
+/*! \brief Configure SPI
+ * \ingroup hardware_spi
+ *
+ * Configure how the SPI serialises and deserialises data on the wire
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param data_bits Number of data bits per transfer. Valid values 4..16.
+ * \param cpol SSPCLKOUT polarity, applicable to Motorola SPI frame format only.
+ * \param cpha SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ * \param order Must be SPI_MSB_FIRST, no other values supported on the PL022
+ */
+static inline void spi_set_format(spi_inst_t *spi, uint data_bits, spi_cpol_t cpol, spi_cpha_t cpha, __unused spi_order_t order) {
+ invalid_params_if(SPI, data_bits < 4 || data_bits > 16);
+ // LSB-first not supported on PL022:
+ invalid_params_if(SPI, order != SPI_MSB_FIRST);
+ invalid_params_if(SPI, cpol != SPI_CPOL_0 && cpol != SPI_CPOL_1);
+ invalid_params_if(SPI, cpha != SPI_CPHA_0 && cpha != SPI_CPHA_1);
+ hw_write_masked(&spi_get_hw(spi)->cr0,
+ ((uint)(data_bits - 1)) << SPI_SSPCR0_DSS_LSB |
+ ((uint)cpol) << SPI_SSPCR0_SPO_LSB |
+ ((uint)cpha) << SPI_SSPCR0_SPH_LSB,
+ SPI_SSPCR0_DSS_BITS |
+ SPI_SSPCR0_SPO_BITS |
+ SPI_SSPCR0_SPH_BITS);
+}
+
+/*! \brief Set SPI master/slave
+ * \ingroup hardware_spi
+ *
+ * Configure the SPI for master- or slave-mode operation. By default,
+ * spi_init() sets master-mode.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param slave true to set SPI device as a slave device, false for master.
+ */
+static inline void spi_set_slave(spi_inst_t *spi, bool slave) {
+ if (slave)
+ hw_set_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS);
+ else
+ hw_clear_bits(&spi_get_hw(spi)->cr1, SPI_SSPCR1_MS_BITS);
+}
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+/*! \brief Check whether a write can be done on SPI device
+ * \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return false if no space is available to write. True if a write is possible
+ */
+static inline bool spi_is_writable(const spi_inst_t *spi) {
+ return (spi_get_const_hw(spi)->sr & SPI_SSPSR_TNF_BITS);
+}
+
+/*! \brief Check whether a read can be done on SPI device
+ * \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return true if a read is possible i.e. data is present
+ */
+static inline bool spi_is_readable(const spi_inst_t *spi) {
+ return (spi_get_const_hw(spi)->sr & SPI_SSPSR_RNE_BITS);
+}
+
+/*! \brief Check whether SPI is busy
+ * \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \return true if SPI is busy
+ */
+static inline bool spi_is_busy(const spi_inst_t *spi) {
+ return (spi_get_const_hw(spi)->sr & SPI_SSPSR_BSY_BITS);
+}
+
+/*! \brief Write/Read to/from an SPI device
+ * \ingroup hardware_spi
+ *
+ * Write \p len bytes from \p src to SPI. Simultaneously read \p len bytes from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of BOTH buffers
+ * \return Number of bytes written/read
+*/
+int spi_write_read_blocking(spi_inst_t *spi, const uint8_t *src, uint8_t *dst, size_t len);
+
+/*! \brief Write to an SPI device, blocking
+ * \ingroup hardware_spi
+ *
+ * Write \p len bytes from \p src to SPI, and discard any data received back
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param len Length of \p src
+ * \return Number of bytes written/read
+ */
+int spi_write_blocking(spi_inst_t *spi, const uint8_t *src, size_t len);
+
+/*! \brief Read from an SPI device
+ * \ingroup hardware_spi
+ *
+ * Read \p len bytes from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ * \p repeated_tx_data is output repeatedly on TX as data is read in from RX.
+ * Generally this can be 0, but some devices require a specific value here,
+ * e.g. SD cards expect 0xff
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param repeated_tx_data Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of buffer \p dst
+ * \return Number of bytes written/read
+ */
+int spi_read_blocking(spi_inst_t *spi, uint8_t repeated_tx_data, uint8_t *dst, size_t len);
+
+// ----------------------------------------------------------------------------
+// SPI-specific operations and aliases
+
+// FIXME need some instance-private data for select() and deselect() if we are going that route
+
+/*! \brief Write/Read half words to/from an SPI device
+ * \ingroup hardware_spi
+ *
+ * Write \p len halfwords from \p src to SPI. Simultaneously read \p len halfwords from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read/write 8 data_bits.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of BOTH buffers in halfwords
+ * \return Number of halfwords written/read
+*/
+int spi_write16_read16_blocking(spi_inst_t *spi, const uint16_t *src, uint16_t *dst, size_t len);
+
+/*! \brief Write to an SPI device
+ * \ingroup hardware_spi
+ *
+ * Write \p len halfwords from \p src to SPI. Discard any data received back.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ *
+ * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only write 8 data_bits.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param src Buffer of data to write
+ * \param len Length of buffers
+ * \return Number of halfwords written/read
+*/
+int spi_write16_blocking(spi_inst_t *spi, const uint16_t *src, size_t len);
+
+/*! \brief Read from an SPI device
+ * \ingroup hardware_spi
+ *
+ * Read \p len halfwords from SPI to \p dst.
+ * Blocks until all data is transferred. No timeout, as SPI hardware always transfers at a known data rate.
+ * \p repeated_tx_data is output repeatedly on TX as data is read in from RX.
+ * Generally this can be 0, but some devices require a specific value here,
+ * e.g. SD cards expect 0xff
+ *
+ * \note SPI should be initialised with 16 data_bits using \ref spi_set_format first, otherwise this function will only read 8 data_bits.
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param repeated_tx_data Buffer of data to write
+ * \param dst Buffer for read data
+ * \param len Length of buffer \p dst in halfwords
+ * \return Number of halfwords written/read
+ */
+int spi_read16_blocking(spi_inst_t *spi, uint16_t repeated_tx_data, uint16_t *dst, size_t len);
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular SPI instance
+ * \ingroup hardware_spi
+ *
+ * \param spi SPI instance specifier, either \ref spi0 or \ref spi1
+ * \param is_tx true for sending data to the SPI instance, false for receiving data from the SPI instance
+ */
+static inline uint spi_get_dreq(spi_inst_t *spi, bool is_tx) {
+ static_assert(DREQ_SPI0_RX == DREQ_SPI0_TX + 1, "");
+ static_assert(DREQ_SPI1_RX == DREQ_SPI1_TX + 1, "");
+ static_assert(DREQ_SPI1_TX == DREQ_SPI0_TX + 2, "");
+ return DREQ_SPI0_TX + spi_get_index(spi) * 2 + !is_tx;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/adc.h b/arkanoid/pico/hardware/structs/adc.h
new file mode 100644
index 0000000..acf51fd
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/adc.h
@@ -0,0 +1,91 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_ADC_H
+#define _HARDWARE_STRUCTS_ADC_H
+
+#include "../address_mapped.h"
+#include "../regs/adc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/adc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(ADC_CS_OFFSET) // ADC_CS
+ // ADC Control and Status
+ // 0x001f0000 [20:16] : RROBIN (0): Round-robin sampling
+ // 0x00007000 [14:12] : AINSEL (0): Select analog mux input
+ // 0x00000400 [10] : ERR_STICKY (0): Some past ADC conversion encountered an error
+ // 0x00000200 [9] : ERR (0): The most recent ADC conversion encountered an error; result is undefined or noisy
+ // 0x00000100 [8] : READY (0): 1 if the ADC is ready to start a new conversion
+ // 0x00000008 [3] : START_MANY (0): Continuously perform conversions whilst this bit is 1
+ // 0x00000004 [2] : START_ONCE (0): Start a single conversion
+ // 0x00000002 [1] : TS_EN (0): Power on temperature sensor
+ // 0x00000001 [0] : EN (0): Power on ADC and enable its clock
+ io_rw_32 cs;
+
+ _REG_(ADC_RESULT_OFFSET) // ADC_RESULT
+ // Result of most recent ADC conversion
+ // 0x00000fff [11:0] : RESULT (0)
+ io_ro_32 result;
+
+ _REG_(ADC_FCS_OFFSET) // ADC_FCS
+ // FIFO control and status
+ // 0x0f000000 [27:24] : THRESH (0): DREQ/IRQ asserted when level >= threshold
+ // 0x000f0000 [19:16] : LEVEL (0): The number of conversion results currently waiting in the FIFO
+ // 0x00000800 [11] : OVER (0): 1 if the FIFO has been overflowed
+ // 0x00000400 [10] : UNDER (0): 1 if the FIFO has been underflowed
+ // 0x00000200 [9] : FULL (0)
+ // 0x00000100 [8] : EMPTY (0)
+ // 0x00000008 [3] : DREQ_EN (0): If 1: assert DMA requests when FIFO contains data
+ // 0x00000004 [2] : ERR (0): If 1: conversion error bit appears in the FIFO alongside the result
+ // 0x00000002 [1] : SHIFT (0): If 1: FIFO results are right-shifted to be one byte in size
+ // 0x00000001 [0] : EN (0): If 1: write result to the FIFO after each conversion
+ io_rw_32 fcs;
+
+ _REG_(ADC_FIFO_OFFSET) // ADC_FIFO
+ // Conversion result FIFO
+ // 0x00008000 [15] : ERR (0): 1 if this particular sample experienced a conversion error
+ // 0x00000fff [11:0] : VAL (0)
+ io_ro_32 fifo;
+
+ _REG_(ADC_DIV_OFFSET) // ADC_DIV
+ // Clock divider
+ // 0x00ffff00 [23:8] : INT (0): Integer part of clock divisor
+ // 0x000000ff [7:0] : FRAC (0): Fractional part of clock divisor
+ io_rw_32 div;
+
+ _REG_(ADC_INTR_OFFSET) // ADC_INTR
+ // Raw Interrupts
+ // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level
+ io_ro_32 intr;
+
+ _REG_(ADC_INTE_OFFSET) // ADC_INTE
+ // Interrupt Enable
+ // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level
+ io_rw_32 inte;
+
+ _REG_(ADC_INTF_OFFSET) // ADC_INTF
+ // Interrupt Force
+ // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level
+ io_rw_32 intf;
+
+ _REG_(ADC_INTS_OFFSET) // ADC_INTS
+ // Interrupt status after masking & forcing
+ // 0x00000001 [0] : FIFO (0): Triggered when the sample FIFO reaches a certain level
+ io_ro_32 ints;
+} adc_hw_t;
+
+#define adc_hw ((adc_hw_t *const)ADC_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/bus_ctrl.h b/arkanoid/pico/hardware/structs/bus_ctrl.h
new file mode 100644
index 0000000..c1f73c5
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/bus_ctrl.h
@@ -0,0 +1,77 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_BUS_CTRL_H
+#define _HARDWARE_STRUCTS_BUS_CTRL_H
+
+#include "../address_mapped.h"
+#include "../regs/busctrl.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/busctrl.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+enum bus_ctrl_perf_counter {
+ arbiter_rom_perf_event_access = 19,
+ arbiter_rom_perf_event_access_contested = 18,
+ arbiter_xip_main_perf_event_access = 17,
+ arbiter_xip_main_perf_event_access_contested = 16,
+ arbiter_sram0_perf_event_access = 15,
+ arbiter_sram0_perf_event_access_contested = 14,
+ arbiter_sram1_perf_event_access = 13,
+ arbiter_sram1_perf_event_access_contested = 12,
+ arbiter_sram2_perf_event_access = 11,
+ arbiter_sram2_perf_event_access_contested = 10,
+ arbiter_sram3_perf_event_access = 9,
+ arbiter_sram3_perf_event_access_contested = 8,
+ arbiter_sram4_perf_event_access = 7,
+ arbiter_sram4_perf_event_access_contested = 6,
+ arbiter_sram5_perf_event_access = 5,
+ arbiter_sram5_perf_event_access_contested = 4,
+ arbiter_fastperi_perf_event_access = 3,
+ arbiter_fastperi_perf_event_access_contested = 2,
+ arbiter_apb_perf_event_access = 1,
+ arbiter_apb_perf_event_access_contested = 0
+};
+
+typedef struct {
+ _REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
+ // Bus fabric performance counter 0
+ // 0x00ffffff [23:0] : PERFCTR0 (0): Busfabric saturating performance counter 0
+ io_rw_32 value;
+
+ _REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
+ // Bus fabric performance event select for PERFCTR0
+ // 0x0000001f [4:0] : PERFSEL0 (0x1f): Select an event for PERFCTR0
+ io_rw_32 sel;
+} bus_ctrl_perf_hw_t;
+
+typedef struct {
+ _REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
+ // Set the priority of each master for bus arbitration
+ // 0x00001000 [12] : DMA_W (0): 0 - low priority, 1 - high priority
+ // 0x00000100 [8] : DMA_R (0): 0 - low priority, 1 - high priority
+ // 0x00000010 [4] : PROC1 (0): 0 - low priority, 1 - high priority
+ // 0x00000001 [0] : PROC0 (0): 0 - low priority, 1 - high priority
+ io_rw_32 priority;
+
+ _REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
+ // Bus priority acknowledge
+ // 0x00000001 [0] : BUS_PRIORITY_ACK (0): Goes to 1 once all arbiters have registered the new global priority levels
+ io_ro_32 priority_ack;
+
+ bus_ctrl_perf_hw_t counter[4];
+} bus_ctrl_hw_t;
+
+#define bus_ctrl_hw ((bus_ctrl_hw_t *const)BUSCTRL_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/clocks.h b/arkanoid/pico/hardware/structs/clocks.h
new file mode 100644
index 0000000..ba3c0bd
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/clocks.h
@@ -0,0 +1,326 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_CLOCKS_H
+#define _HARDWARE_STRUCTS_CLOCKS_H
+
+#include "../address_mapped.h"
+#include "../regs/clocks.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/clocks.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/*! \brief Enumeration identifying a hardware clock
+ * \ingroup hardware_clocks
+ */
+/// \tag::clkenum[]
+enum clock_index {
+ clk_gpout0 = 0, ///< GPIO Muxing 0
+ clk_gpout1, ///< GPIO Muxing 1
+ clk_gpout2, ///< GPIO Muxing 2
+ clk_gpout3, ///< GPIO Muxing 3
+ clk_ref, ///< Watchdog and timers reference clock
+ clk_sys, ///< Processors, bus fabric, memory, memory mapped registers
+ clk_peri, ///< Peripheral clock for UART and SPI
+ clk_usb, ///< USB clock
+ clk_adc, ///< ADC clock
+ clk_rtc, ///< Real time clock
+ CLK_COUNT
+};
+/// \end::clkenum[]
+
+/// \tag::clock_hw[]
+typedef struct {
+ _REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
+ // Clock control, can be changed on-the-fly (except for auxsrc)
+ // 0x00100000 [20] : NUDGE (0): An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+ // 0x00030000 [17:16] : PHASE (0): This delays the enable signal by up to 3 cycles of the input clock
+ // 0x00001000 [12] : DC50 (0): Enables duty cycle correction for odd divisors
+ // 0x00000800 [11] : ENABLE (0): Starts and stops the clock generator cleanly
+ // 0x00000400 [10] : KILL (0): Asynchronously kills the clock generator
+ // 0x000001e0 [8:5] : AUXSRC (0): Selects the auxiliary clock source, will glitch when switching
+ io_rw_32 ctrl;
+
+ _REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
+ // Clock divisor, can be changed on-the-fly
+ // 0xffffff00 [31:8] : INT (1): Integer component of the divisor, 0 -> divide by 2^16
+ // 0x000000ff [7:0] : FRAC (0): Fractional component of the divisor
+ io_rw_32 div;
+
+ _REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
+ // Indicates which SRC is currently selected by the glitchless mux (one-hot)
+ io_ro_32 selected;
+} clock_hw_t;
+/// \end::clock_hw[]
+
+typedef struct {
+ _REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
+ // 0x00010000 [16] : CLEAR (0): For clearing the resus after the fault that triggered it has been corrected
+ // 0x00001000 [12] : FRCE (0): Force a resus, for test purposes only
+ // 0x00000100 [8] : ENABLE (0): Enable resus
+ // 0x000000ff [7:0] : TIMEOUT (0xff): This is expressed as a number of clk_ref cycles
+ io_rw_32 ctrl;
+
+ _REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
+ // 0x00000001 [0] : RESUSSED (0): Clock has been resuscitated, correct the error then send ctrl_clear=1
+ io_ro_32 status;
+} clock_resus_hw_t;
+
+typedef struct {
+ _REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
+ // Reference clock frequency in kHz
+ // 0x000fffff [19:0] : FC0_REF_KHZ (0)
+ io_rw_32 ref_khz;
+
+ _REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
+ // Minimum pass frequency in kHz
+ // 0x01ffffff [24:0] : FC0_MIN_KHZ (0)
+ io_rw_32 min_khz;
+
+ _REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
+ // Maximum pass frequency in kHz
+ // 0x01ffffff [24:0] : FC0_MAX_KHZ (0x1ffffff)
+ io_rw_32 max_khz;
+
+ _REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
+ // Delays the start of frequency counting to allow the mux to settle
+ // 0x00000007 [2:0] : FC0_DELAY (1)
+ io_rw_32 delay;
+
+ _REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
+ // The test interval is 0
+ // 0x0000000f [3:0] : FC0_INTERVAL (0x8)
+ io_rw_32 interval;
+
+ _REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
+ // Clock sent to frequency counter, set to 0 when not required
+ // 0x000000ff [7:0] : FC0_SRC (0)
+ io_rw_32 src;
+
+ _REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
+ // Frequency counter status
+ // 0x10000000 [28] : DIED (0): Test clock stopped during test
+ // 0x01000000 [24] : FAST (0): Test clock faster than expected, only valid when status_done=1
+ // 0x00100000 [20] : SLOW (0): Test clock slower than expected, only valid when status_done=1
+ // 0x00010000 [16] : FAIL (0): Test failed
+ // 0x00001000 [12] : WAITING (0): Waiting for test clock to start
+ // 0x00000100 [8] : RUNNING (0): Test running
+ // 0x00000010 [4] : DONE (0): Test complete
+ // 0x00000001 [0] : PASS (0): Test passed
+ io_ro_32 status;
+
+ _REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
+ // Result of frequency measurement, only valid when status_done=1
+ // 0x3fffffe0 [29:5] : KHZ (0)
+ // 0x0000001f [4:0] : FRAC (0)
+ io_ro_32 result;
+} fc_hw_t;
+
+typedef struct {
+ clock_hw_t clk[CLK_COUNT]; // 10
+
+ clock_resus_hw_t resus;
+
+ fc_hw_t fc0;
+
+ _REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
+ // enable clock in wake mode
+ // 0x80000000 [31] : clk_sys_sram3 (1)
+ // 0x40000000 [30] : clk_sys_sram2 (1)
+ // 0x20000000 [29] : clk_sys_sram1 (1)
+ // 0x10000000 [28] : clk_sys_sram0 (1)
+ // 0x08000000 [27] : clk_sys_spi1 (1)
+ // 0x04000000 [26] : clk_peri_spi1 (1)
+ // 0x02000000 [25] : clk_sys_spi0 (1)
+ // 0x01000000 [24] : clk_peri_spi0 (1)
+ // 0x00800000 [23] : clk_sys_sio (1)
+ // 0x00400000 [22] : clk_sys_rtc (1)
+ // 0x00200000 [21] : clk_rtc_rtc (1)
+ // 0x00100000 [20] : clk_sys_rosc (1)
+ // 0x00080000 [19] : clk_sys_rom (1)
+ // 0x00040000 [18] : clk_sys_resets (1)
+ // 0x00020000 [17] : clk_sys_pwm (1)
+ // 0x00010000 [16] : clk_sys_psm (1)
+ // 0x00008000 [15] : clk_sys_pll_usb (1)
+ // 0x00004000 [14] : clk_sys_pll_sys (1)
+ // 0x00002000 [13] : clk_sys_pio1 (1)
+ // 0x00001000 [12] : clk_sys_pio0 (1)
+ // 0x00000800 [11] : clk_sys_pads (1)
+ // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1)
+ // 0x00000200 [9] : clk_sys_jtag (1)
+ // 0x00000100 [8] : clk_sys_io (1)
+ // 0x00000080 [7] : clk_sys_i2c1 (1)
+ // 0x00000040 [6] : clk_sys_i2c0 (1)
+ // 0x00000020 [5] : clk_sys_dma (1)
+ // 0x00000010 [4] : clk_sys_busfabric (1)
+ // 0x00000008 [3] : clk_sys_busctrl (1)
+ // 0x00000004 [2] : clk_sys_adc (1)
+ // 0x00000002 [1] : clk_adc_adc (1)
+ // 0x00000001 [0] : clk_sys_clocks (1)
+ io_rw_32 wake_en0;
+
+ _REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
+ // enable clock in wake mode
+ // 0x00004000 [14] : clk_sys_xosc (1)
+ // 0x00002000 [13] : clk_sys_xip (1)
+ // 0x00001000 [12] : clk_sys_watchdog (1)
+ // 0x00000800 [11] : clk_usb_usbctrl (1)
+ // 0x00000400 [10] : clk_sys_usbctrl (1)
+ // 0x00000200 [9] : clk_sys_uart1 (1)
+ // 0x00000100 [8] : clk_peri_uart1 (1)
+ // 0x00000080 [7] : clk_sys_uart0 (1)
+ // 0x00000040 [6] : clk_peri_uart0 (1)
+ // 0x00000020 [5] : clk_sys_timer (1)
+ // 0x00000010 [4] : clk_sys_tbman (1)
+ // 0x00000008 [3] : clk_sys_sysinfo (1)
+ // 0x00000004 [2] : clk_sys_syscfg (1)
+ // 0x00000002 [1] : clk_sys_sram5 (1)
+ // 0x00000001 [0] : clk_sys_sram4 (1)
+ io_rw_32 wake_en1;
+
+ _REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
+ // enable clock in sleep mode
+ // 0x80000000 [31] : clk_sys_sram3 (1)
+ // 0x40000000 [30] : clk_sys_sram2 (1)
+ // 0x20000000 [29] : clk_sys_sram1 (1)
+ // 0x10000000 [28] : clk_sys_sram0 (1)
+ // 0x08000000 [27] : clk_sys_spi1 (1)
+ // 0x04000000 [26] : clk_peri_spi1 (1)
+ // 0x02000000 [25] : clk_sys_spi0 (1)
+ // 0x01000000 [24] : clk_peri_spi0 (1)
+ // 0x00800000 [23] : clk_sys_sio (1)
+ // 0x00400000 [22] : clk_sys_rtc (1)
+ // 0x00200000 [21] : clk_rtc_rtc (1)
+ // 0x00100000 [20] : clk_sys_rosc (1)
+ // 0x00080000 [19] : clk_sys_rom (1)
+ // 0x00040000 [18] : clk_sys_resets (1)
+ // 0x00020000 [17] : clk_sys_pwm (1)
+ // 0x00010000 [16] : clk_sys_psm (1)
+ // 0x00008000 [15] : clk_sys_pll_usb (1)
+ // 0x00004000 [14] : clk_sys_pll_sys (1)
+ // 0x00002000 [13] : clk_sys_pio1 (1)
+ // 0x00001000 [12] : clk_sys_pio0 (1)
+ // 0x00000800 [11] : clk_sys_pads (1)
+ // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (1)
+ // 0x00000200 [9] : clk_sys_jtag (1)
+ // 0x00000100 [8] : clk_sys_io (1)
+ // 0x00000080 [7] : clk_sys_i2c1 (1)
+ // 0x00000040 [6] : clk_sys_i2c0 (1)
+ // 0x00000020 [5] : clk_sys_dma (1)
+ // 0x00000010 [4] : clk_sys_busfabric (1)
+ // 0x00000008 [3] : clk_sys_busctrl (1)
+ // 0x00000004 [2] : clk_sys_adc (1)
+ // 0x00000002 [1] : clk_adc_adc (1)
+ // 0x00000001 [0] : clk_sys_clocks (1)
+ io_rw_32 sleep_en0;
+
+ _REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
+ // enable clock in sleep mode
+ // 0x00004000 [14] : clk_sys_xosc (1)
+ // 0x00002000 [13] : clk_sys_xip (1)
+ // 0x00001000 [12] : clk_sys_watchdog (1)
+ // 0x00000800 [11] : clk_usb_usbctrl (1)
+ // 0x00000400 [10] : clk_sys_usbctrl (1)
+ // 0x00000200 [9] : clk_sys_uart1 (1)
+ // 0x00000100 [8] : clk_peri_uart1 (1)
+ // 0x00000080 [7] : clk_sys_uart0 (1)
+ // 0x00000040 [6] : clk_peri_uart0 (1)
+ // 0x00000020 [5] : clk_sys_timer (1)
+ // 0x00000010 [4] : clk_sys_tbman (1)
+ // 0x00000008 [3] : clk_sys_sysinfo (1)
+ // 0x00000004 [2] : clk_sys_syscfg (1)
+ // 0x00000002 [1] : clk_sys_sram5 (1)
+ // 0x00000001 [0] : clk_sys_sram4 (1)
+ io_rw_32 sleep_en1;
+
+ _REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
+ // indicates the state of the clock enable
+ // 0x80000000 [31] : clk_sys_sram3 (0)
+ // 0x40000000 [30] : clk_sys_sram2 (0)
+ // 0x20000000 [29] : clk_sys_sram1 (0)
+ // 0x10000000 [28] : clk_sys_sram0 (0)
+ // 0x08000000 [27] : clk_sys_spi1 (0)
+ // 0x04000000 [26] : clk_peri_spi1 (0)
+ // 0x02000000 [25] : clk_sys_spi0 (0)
+ // 0x01000000 [24] : clk_peri_spi0 (0)
+ // 0x00800000 [23] : clk_sys_sio (0)
+ // 0x00400000 [22] : clk_sys_rtc (0)
+ // 0x00200000 [21] : clk_rtc_rtc (0)
+ // 0x00100000 [20] : clk_sys_rosc (0)
+ // 0x00080000 [19] : clk_sys_rom (0)
+ // 0x00040000 [18] : clk_sys_resets (0)
+ // 0x00020000 [17] : clk_sys_pwm (0)
+ // 0x00010000 [16] : clk_sys_psm (0)
+ // 0x00008000 [15] : clk_sys_pll_usb (0)
+ // 0x00004000 [14] : clk_sys_pll_sys (0)
+ // 0x00002000 [13] : clk_sys_pio1 (0)
+ // 0x00001000 [12] : clk_sys_pio0 (0)
+ // 0x00000800 [11] : clk_sys_pads (0)
+ // 0x00000400 [10] : clk_sys_vreg_and_chip_reset (0)
+ // 0x00000200 [9] : clk_sys_jtag (0)
+ // 0x00000100 [8] : clk_sys_io (0)
+ // 0x00000080 [7] : clk_sys_i2c1 (0)
+ // 0x00000040 [6] : clk_sys_i2c0 (0)
+ // 0x00000020 [5] : clk_sys_dma (0)
+ // 0x00000010 [4] : clk_sys_busfabric (0)
+ // 0x00000008 [3] : clk_sys_busctrl (0)
+ // 0x00000004 [2] : clk_sys_adc (0)
+ // 0x00000002 [1] : clk_adc_adc (0)
+ // 0x00000001 [0] : clk_sys_clocks (0)
+ io_ro_32 enabled0;
+
+ _REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
+ // indicates the state of the clock enable
+ // 0x00004000 [14] : clk_sys_xosc (0)
+ // 0x00002000 [13] : clk_sys_xip (0)
+ // 0x00001000 [12] : clk_sys_watchdog (0)
+ // 0x00000800 [11] : clk_usb_usbctrl (0)
+ // 0x00000400 [10] : clk_sys_usbctrl (0)
+ // 0x00000200 [9] : clk_sys_uart1 (0)
+ // 0x00000100 [8] : clk_peri_uart1 (0)
+ // 0x00000080 [7] : clk_sys_uart0 (0)
+ // 0x00000040 [6] : clk_peri_uart0 (0)
+ // 0x00000020 [5] : clk_sys_timer (0)
+ // 0x00000010 [4] : clk_sys_tbman (0)
+ // 0x00000008 [3] : clk_sys_sysinfo (0)
+ // 0x00000004 [2] : clk_sys_syscfg (0)
+ // 0x00000002 [1] : clk_sys_sram5 (0)
+ // 0x00000001 [0] : clk_sys_sram4 (0)
+ io_ro_32 enabled1;
+
+ _REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
+ // Raw Interrupts
+ // 0x00000001 [0] : CLK_SYS_RESUS (0)
+ io_ro_32 intr;
+
+ _REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
+ // Interrupt Enable
+ // 0x00000001 [0] : CLK_SYS_RESUS (0)
+ io_rw_32 inte;
+
+ _REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
+ // Interrupt Force
+ // 0x00000001 [0] : CLK_SYS_RESUS (0)
+ io_rw_32 intf;
+
+ _REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
+ // Interrupt status after masking & forcing
+ // 0x00000001 [0] : CLK_SYS_RESUS (0)
+ io_ro_32 ints;
+} clocks_hw_t;
+
+#define clocks_hw ((clocks_hw_t *const)CLOCKS_BASE)
+
+static_assert( CLK_COUNT == 10, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/dma.h b/arkanoid/pico/hardware/structs/dma.h
new file mode 100644
index 0000000..a8bdd41
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/dma.h
@@ -0,0 +1,203 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_DMA_H
+#define _HARDWARE_STRUCTS_DMA_H
+
+#include "../address_mapped.h"
+#include "../regs/dma.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/dma.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
+ // DMA Channel 0 Read Address pointer
+ io_rw_32 read_addr;
+
+ _REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
+ // DMA Channel 0 Write Address pointer
+ io_rw_32 write_addr;
+
+ _REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
+ // DMA Channel 0 Transfer Count
+ io_rw_32 transfer_count;
+
+ _REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
+ // DMA Channel 0 Control and Status
+ // 0x80000000 [31] : AHB_ERROR (0): Logical OR of the READ_ERROR and WRITE_ERROR flags
+ // 0x40000000 [30] : READ_ERROR (0): If 1, the channel received a read bus error
+ // 0x20000000 [29] : WRITE_ERROR (0): If 1, the channel received a write bus error
+ // 0x01000000 [24] : BUSY (0): This flag goes high when the channel starts a new transfer sequence, and low when the...
+ // 0x00800000 [23] : SNIFF_EN (0): If 1, this channel's data transfers are visible to the sniff hardware, and each...
+ // 0x00400000 [22] : BSWAP (0): Apply byte-swap transformation to DMA data
+ // 0x00200000 [21] : IRQ_QUIET (0): In QUIET mode, the channel does not generate IRQs at the end of every transfer block
+ // 0x001f8000 [20:15] : TREQ_SEL (0): Select a Transfer Request signal
+ // 0x00007800 [14:11] : CHAIN_TO (0): When this channel completes, it will trigger the channel indicated by CHAIN_TO
+ // 0x00000400 [10] : RING_SEL (0): Select whether RING_SIZE applies to read or write addresses
+ // 0x000003c0 [9:6] : RING_SIZE (0): Size of address wrap region
+ // 0x00000020 [5] : INCR_WRITE (0): If 1, the write address increments with each transfer
+ // 0x00000010 [4] : INCR_READ (0): If 1, the read address increments with each transfer
+ // 0x0000000c [3:2] : DATA_SIZE (0): Set the size of each bus transfer (byte/halfword/word)
+ // 0x00000002 [1] : HIGH_PRIORITY (0): HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in...
+ // 0x00000001 [0] : EN (0): DMA Channel Enable
+ io_rw_32 ctrl_trig;
+
+ _REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
+ // Alias for channel 0 CTRL register
+ io_rw_32 al1_ctrl;
+
+ _REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
+ // Alias for channel 0 READ_ADDR register
+ io_rw_32 al1_read_addr;
+
+ _REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
+ // Alias for channel 0 WRITE_ADDR register
+ io_rw_32 al1_write_addr;
+
+ _REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
+ // Alias for channel 0 TRANS_COUNT register
+ io_rw_32 al1_transfer_count_trig;
+
+ _REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
+ // Alias for channel 0 CTRL register
+ io_rw_32 al2_ctrl;
+
+ _REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
+ // Alias for channel 0 TRANS_COUNT register
+ io_rw_32 al2_transfer_count;
+
+ _REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
+ // Alias for channel 0 READ_ADDR register
+ io_rw_32 al2_read_addr;
+
+ _REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
+ // Alias for channel 0 WRITE_ADDR register
+ io_rw_32 al2_write_addr_trig;
+
+ _REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
+ // Alias for channel 0 CTRL register
+ io_rw_32 al3_ctrl;
+
+ _REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
+ // Alias for channel 0 WRITE_ADDR register
+ io_rw_32 al3_write_addr;
+
+ _REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
+ // Alias for channel 0 TRANS_COUNT register
+ io_rw_32 al3_transfer_count;
+
+ _REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
+ // Alias for channel 0 READ_ADDR register
+ io_rw_32 al3_read_addr_trig;
+} dma_channel_hw_t;
+
+typedef struct {
+ dma_channel_hw_t ch[NUM_DMA_CHANNELS]; // 12
+
+ uint32_t _pad0[64];
+
+ _REG_(DMA_INTR_OFFSET) // DMA_INTR
+ // Interrupt Status (raw)
+ // 0x0000ffff [15:0] : INTR (0): Raw interrupt status for DMA Channels 0
+ io_ro_32 intr;
+
+ _REG_(DMA_INTE0_OFFSET) // DMA_INTE0
+ // Interrupt Enables for IRQ 0
+ // 0x0000ffff [15:0] : INTE0 (0): Set bit n to pass interrupts from channel n to DMA IRQ 0
+ io_rw_32 inte0;
+
+ _REG_(DMA_INTF0_OFFSET) // DMA_INTF0
+ // Force Interrupts
+ // 0x0000ffff [15:0] : INTF0 (0): Write 1s to force the corresponding bits in INTE0
+ io_rw_32 intf0;
+
+ _REG_(DMA_INTS0_OFFSET) // DMA_INTS0
+ // Interrupt Status for IRQ 0
+ // 0x0000ffff [15:0] : INTS0 (0): Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted
+ io_rw_32 ints0;
+
+ uint32_t _pad1;
+
+ _REG_(DMA_INTE1_OFFSET) // DMA_INTE1
+ // Interrupt Enables for IRQ 1
+ // 0x0000ffff [15:0] : INTE1 (0): Set bit n to pass interrupts from channel n to DMA IRQ 1
+ io_rw_32 inte1;
+
+ _REG_(DMA_INTF1_OFFSET) // DMA_INTF1
+ // Force Interrupts for IRQ 1
+ // 0x0000ffff [15:0] : INTF1 (0): Write 1s to force the corresponding bits in INTE0
+ io_rw_32 intf1;
+
+ _REG_(DMA_INTS1_OFFSET) // DMA_INTS1
+ // Interrupt Status (masked) for IRQ 1
+ // 0x0000ffff [15:0] : INTS1 (0): Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted
+ io_rw_32 ints1;
+
+ _REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
+ // (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
+ //
+ // Pacing (X/Y) Fractional Timer
+ // 0xffff0000 [31:16] : X (0): Pacing Timer Dividend
+ // 0x0000ffff [15:0] : Y (0): Pacing Timer Divisor
+ io_rw_32 timer[NUM_DMA_TIMERS]; // 4
+
+ _REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
+ // Trigger one or more channels simultaneously
+ // 0x0000ffff [15:0] : MULTI_CHAN_TRIGGER (0): Each bit in this register corresponds to a DMA channel
+ io_rw_32 multi_channel_trigger;
+
+ _REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
+ // Sniffer Control
+ // 0x00000800 [11] : OUT_INV (0): If set, the result appears inverted (bitwise complement) when read
+ // 0x00000400 [10] : OUT_REV (0): If set, the result appears bit-reversed when read
+ // 0x00000200 [9] : BSWAP (0): Locally perform a byte reverse on the sniffed data, before feeding into checksum
+ // 0x000001e0 [8:5] : CALC (0)
+ // 0x0000001e [4:1] : DMACH (0): DMA channel for Sniffer to observe
+ // 0x00000001 [0] : EN (0): Enable sniffer
+ io_rw_32 sniff_ctrl;
+
+ _REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
+ // Data accumulator for sniff hardware
+ io_rw_32 sniff_data;
+
+ uint32_t _pad2;
+
+ _REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
+ // Debug RAF, WAF, TDF levels
+ // 0x00ff0000 [23:16] : RAF_LVL (0): Current Read-Address-FIFO fill level
+ // 0x0000ff00 [15:8] : WAF_LVL (0): Current Write-Address-FIFO fill level
+ // 0x000000ff [7:0] : TDF_LVL (0): Current Transfer-Data-FIFO fill level
+ io_ro_32 fifo_levels;
+
+ _REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
+ // Abort an in-progress transfer sequence on one or more channels
+ // 0x0000ffff [15:0] : CHAN_ABORT (0): Each bit corresponds to a channel
+ io_rw_32 abort;
+} dma_hw_t;
+
+typedef struct {
+ struct dma_debug_hw_channel {
+ io_rw_32 ctrdeq;
+ io_ro_32 tcr;
+ uint32_t pad[14];
+ } ch[NUM_DMA_CHANNELS];
+} dma_debug_hw_t;
+
+#define dma_hw ((dma_hw_t *const)DMA_BASE)
+#define dma_debug_hw ((dma_debug_hw_t *const)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
+
+static_assert( NUM_DMA_TIMERS == 4, "");
+static_assert( NUM_DMA_CHANNELS == 12, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/i2c.h b/arkanoid/pico/hardware/structs/i2c.h
new file mode 100644
index 0000000..03aa135
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/i2c.h
@@ -0,0 +1,333 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_I2C_H
+#define _HARDWARE_STRUCTS_I2C_H
+
+#include "../address_mapped.h"
+#include "../regs/i2c.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/i2c.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
+ // I2C Control Register
+ // 0x00000400 [10] : STOP_DET_IF_MASTER_ACTIVE (0): Master issues the STOP_DET interrupt irrespective of whether...
+ // 0x00000200 [9] : RX_FIFO_FULL_HLD_CTRL (0): This bit controls whether DW_apb_i2c should hold the bus when the Rx...
+ // 0x00000100 [8] : TX_EMPTY_CTRL (0): This bit controls the generation of the TX_EMPTY interrupt, as described in...
+ // 0x00000080 [7] : STOP_DET_IFADDRESSED (0): In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is...
+ // 0x00000040 [6] : IC_SLAVE_DISABLE (1): This bit controls whether I2C has its slave disabled, which means once...
+ // 0x00000020 [5] : IC_RESTART_EN (1): Determines whether RESTART conditions may be sent when acting as a master
+ // 0x00000010 [4] : IC_10BITADDR_MASTER (0): Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit...
+ // 0x00000008 [3] : IC_10BITADDR_SLAVE (0): When acting as a slave, this bit controls whether the DW_apb_i2c...
+ // 0x00000006 [2:1] : SPEED (0x2): These bits control at which speed the DW_apb_i2c operates; its setting is relevant...
+ // 0x00000001 [0] : MASTER_MODE (1): This bit controls whether the DW_apb_i2c master is enabled
+ io_rw_32 con;
+
+ _REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
+ // I2C Target Address Register
+ // 0x00000800 [11] : SPECIAL (0): This bit indicates whether software performs a Device-ID or General Call or START...
+ // 0x00000400 [10] : GC_OR_START (0): If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this...
+ // 0x000003ff [9:0] : IC_TAR (0x55): This is the target address for any master transaction
+ io_rw_32 tar;
+
+ _REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
+ // I2C Slave Address Register
+ // 0x000003ff [9:0] : IC_SAR (0x55): The IC_SAR holds the slave address when the I2C is operating as a slave
+ io_rw_32 sar;
+
+ uint32_t _pad0;
+
+ _REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
+ // I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the...
+ // 0x00000800 [11] : FIRST_DATA_BYTE (0): Indicates the first data byte received after the address phase for receive...
+ // 0x00000400 [10] : RESTART (0): This bit controls whether a RESTART is issued before the byte is sent or received
+ // 0x00000200 [9] : STOP (0): This bit controls whether a STOP is issued after the byte is sent or received
+ // 0x00000100 [8] : CMD (0): This bit controls whether a read or a write is performed
+ // 0x000000ff [7:0] : DAT (0): This register contains the data to be transmitted or received on the I2C bus
+ io_rw_32 data_cmd;
+
+ _REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
+ // Standard Speed I2C Clock SCL High Count Register
+ // 0x0000ffff [15:0] : IC_SS_SCL_HCNT (0x28): This register must be set before any I2C bus transaction can take place...
+ io_rw_32 ss_scl_hcnt;
+
+ _REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
+ // Standard Speed I2C Clock SCL Low Count Register
+ // 0x0000ffff [15:0] : IC_SS_SCL_LCNT (0x2f): This register must be set before any I2C bus transaction can take place...
+ io_rw_32 ss_scl_lcnt;
+
+ _REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
+ // Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
+ // 0x0000ffff [15:0] : IC_FS_SCL_HCNT (0x6): This register must be set before any I2C bus transaction can take place...
+ io_rw_32 fs_scl_hcnt;
+
+ _REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
+ // Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
+ // 0x0000ffff [15:0] : IC_FS_SCL_LCNT (0xd): This register must be set before any I2C bus transaction can take place...
+ io_rw_32 fs_scl_lcnt;
+
+ uint32_t _pad1[2];
+
+ _REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
+ // I2C Interrupt Status Register
+ // 0x00001000 [12] : R_RESTART_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit
+ // 0x00000800 [11] : R_GEN_CALL (0): See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
+ // 0x00000400 [10] : R_START_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit
+ // 0x00000200 [9] : R_STOP_DET (0): See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
+ // 0x00000100 [8] : R_ACTIVITY (0): See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
+ // 0x00000080 [7] : R_RX_DONE (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
+ // 0x00000040 [6] : R_TX_ABRT (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
+ // 0x00000020 [5] : R_RD_REQ (0): See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
+ // 0x00000010 [4] : R_TX_EMPTY (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
+ // 0x00000008 [3] : R_TX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
+ // 0x00000004 [2] : R_RX_FULL (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
+ // 0x00000002 [1] : R_RX_OVER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
+ // 0x00000001 [0] : R_RX_UNDER (0): See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
+ io_ro_32 intr_stat;
+
+ _REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
+ // I2C Interrupt Mask Register
+ // 0x00001000 [12] : M_RESTART_DET (0): This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register
+ // 0x00000800 [11] : M_GEN_CALL (1): This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
+ // 0x00000400 [10] : M_START_DET (0): This bit masks the R_START_DET interrupt in IC_INTR_STAT register
+ // 0x00000200 [9] : M_STOP_DET (0): This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
+ // 0x00000100 [8] : M_ACTIVITY (0): This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
+ // 0x00000080 [7] : M_RX_DONE (1): This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
+ // 0x00000040 [6] : M_TX_ABRT (1): This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
+ // 0x00000020 [5] : M_RD_REQ (1): This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
+ // 0x00000010 [4] : M_TX_EMPTY (1): This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
+ // 0x00000008 [3] : M_TX_OVER (1): This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
+ // 0x00000004 [2] : M_RX_FULL (1): This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
+ // 0x00000002 [1] : M_RX_OVER (1): This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
+ // 0x00000001 [0] : M_RX_UNDER (1): This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
+ io_rw_32 intr_mask;
+
+ _REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
+ // I2C Raw Interrupt Status Register
+ // 0x00001000 [12] : RESTART_DET (0): Indicates whether a RESTART condition has occurred on the I2C interface when...
+ // 0x00000800 [11] : GEN_CALL (0): Set only when a General Call address is received and it is acknowledged
+ // 0x00000400 [10] : START_DET (0): Indicates whether a START or RESTART condition has occurred on the I2C interface...
+ // 0x00000200 [9] : STOP_DET (0): Indicates whether a STOP condition has occurred on the I2C interface regardless...
+ // 0x00000100 [8] : ACTIVITY (0): This bit captures DW_apb_i2c activity and stays set until it is cleared
+ // 0x00000080 [7] : RX_DONE (0): When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the...
+ // 0x00000040 [6] : TX_ABRT (0): This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the...
+ // 0x00000020 [5] : RD_REQ (0): This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is...
+ // 0x00000010 [4] : TX_EMPTY (0): The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL...
+ // 0x00000008 [3] : TX_OVER (0): Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the...
+ // 0x00000004 [2] : RX_FULL (0): Set when the receive buffer reaches or goes above the RX_TL threshold in the...
+ // 0x00000002 [1] : RX_OVER (0): Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an...
+ // 0x00000001 [0] : RX_UNDER (0): Set if the processor attempts to read the receive buffer when it is empty by...
+ io_ro_32 raw_intr_stat;
+
+ _REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
+ // I2C Receive FIFO Threshold Register
+ // 0x000000ff [7:0] : RX_TL (0): Receive FIFO Threshold Level
+ io_rw_32 rx_tl;
+
+ _REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
+ // I2C Transmit FIFO Threshold Register
+ // 0x000000ff [7:0] : TX_TL (0): Transmit FIFO Threshold Level
+ io_rw_32 tx_tl;
+
+ _REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
+ // Clear Combined and Individual Interrupt Register
+ // 0x00000001 [0] : CLR_INTR (0): Read this register to clear the combined interrupt, all individual interrupts,...
+ io_ro_32 clr_intr;
+
+ _REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
+ // Clear RX_UNDER Interrupt Register
+ // 0x00000001 [0] : CLR_RX_UNDER (0): Read this register to clear the RX_UNDER interrupt (bit 0) of the...
+ io_ro_32 clr_rx_under;
+
+ _REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
+ // Clear RX_OVER Interrupt Register
+ // 0x00000001 [0] : CLR_RX_OVER (0): Read this register to clear the RX_OVER interrupt (bit 1) of the...
+ io_ro_32 clr_rx_over;
+
+ _REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
+ // Clear TX_OVER Interrupt Register
+ // 0x00000001 [0] : CLR_TX_OVER (0): Read this register to clear the TX_OVER interrupt (bit 3) of the...
+ io_ro_32 clr_tx_over;
+
+ _REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
+ // Clear RD_REQ Interrupt Register
+ // 0x00000001 [0] : CLR_RD_REQ (0): Read this register to clear the RD_REQ interrupt (bit 5) of the...
+ io_ro_32 clr_rd_req;
+
+ _REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
+ // Clear TX_ABRT Interrupt Register
+ // 0x00000001 [0] : CLR_TX_ABRT (0): Read this register to clear the TX_ABRT interrupt (bit 6) of the...
+ io_ro_32 clr_tx_abrt;
+
+ _REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
+ // Clear RX_DONE Interrupt Register
+ // 0x00000001 [0] : CLR_RX_DONE (0): Read this register to clear the RX_DONE interrupt (bit 7) of the...
+ io_ro_32 clr_rx_done;
+
+ _REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
+ // Clear ACTIVITY Interrupt Register
+ // 0x00000001 [0] : CLR_ACTIVITY (0): Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore
+ io_ro_32 clr_activity;
+
+ _REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
+ // Clear STOP_DET Interrupt Register
+ // 0x00000001 [0] : CLR_STOP_DET (0): Read this register to clear the STOP_DET interrupt (bit 9) of the...
+ io_ro_32 clr_stop_det;
+
+ _REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
+ // Clear START_DET Interrupt Register
+ // 0x00000001 [0] : CLR_START_DET (0): Read this register to clear the START_DET interrupt (bit 10) of the...
+ io_ro_32 clr_start_det;
+
+ _REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
+ // Clear GEN_CALL Interrupt Register
+ // 0x00000001 [0] : CLR_GEN_CALL (0): Read this register to clear the GEN_CALL interrupt (bit 11) of...
+ io_ro_32 clr_gen_call;
+
+ _REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
+ // I2C Enable Register
+ // 0x00000004 [2] : TX_CMD_BLOCK (0): In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx...
+ // 0x00000002 [1] : ABORT (0): When set, the controller initiates the transfer abort
+ // 0x00000001 [0] : ENABLE (0): Controls whether the DW_apb_i2c is enabled
+ io_rw_32 enable;
+
+ _REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
+ // I2C Status Register
+ // 0x00000040 [6] : SLV_ACTIVITY (0): Slave FSM Activity Status
+ // 0x00000020 [5] : MST_ACTIVITY (0): Master FSM Activity Status
+ // 0x00000010 [4] : RFF (0): Receive FIFO Completely Full
+ // 0x00000008 [3] : RFNE (0): Receive FIFO Not Empty
+ // 0x00000004 [2] : TFE (1): Transmit FIFO Completely Empty
+ // 0x00000002 [1] : TFNF (1): Transmit FIFO Not Full
+ // 0x00000001 [0] : ACTIVITY (0): I2C Activity Status
+ io_ro_32 status;
+
+ _REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
+ // I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer
+ // 0x0000001f [4:0] : TXFLR (0): Transmit FIFO Level
+ io_ro_32 txflr;
+
+ _REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
+ // I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer
+ // 0x0000001f [4:0] : RXFLR (0): Receive FIFO Level
+ io_ro_32 rxflr;
+
+ _REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
+ // I2C SDA Hold Time Length Register
+ // 0x00ff0000 [23:16] : IC_SDA_RX_HOLD (0): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
+ // 0x0000ffff [15:0] : IC_SDA_TX_HOLD (1): Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c...
+ io_rw_32 sda_hold;
+
+ _REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
+ // I2C Transmit Abort Source Register
+ // 0xff800000 [31:23] : TX_FLUSH_CNT (0): This field indicates the number of Tx FIFO Data Commands which are flushed...
+ // 0x00010000 [16] : ABRT_USER_ABRT (0): This is a master-mode-only bit
+ // 0x00008000 [15] : ABRT_SLVRD_INTX (0): 1: When the processor side responds to a slave mode request for data to be...
+ // 0x00004000 [14] : ABRT_SLV_ARBLOST (0): This field indicates that a Slave has lost the bus while transmitting...
+ // 0x00002000 [13] : ABRT_SLVFLUSH_TXFIFO (0): This field specifies that the Slave has received a read command and...
+ // 0x00001000 [12] : ARB_LOST (0): This field specifies that the Master has lost arbitration, or if...
+ // 0x00000800 [11] : ABRT_MASTER_DIS (0): This field indicates that the User tries to initiate a Master operation...
+ // 0x00000400 [10] : ABRT_10B_RD_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+ // 0x00000200 [9] : ABRT_SBYTE_NORSTRT (0): To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed...
+ // 0x00000100 [8] : ABRT_HS_NORSTRT (0): This field indicates that the restart is disabled (IC_RESTART_EN bit...
+ // 0x00000080 [7] : ABRT_SBYTE_ACKDET (0): This field indicates that the Master has sent a START Byte and the START...
+ // 0x00000040 [6] : ABRT_HS_ACKDET (0): This field indicates that the Master is in High Speed mode and the High...
+ // 0x00000020 [5] : ABRT_GCALL_READ (0): This field indicates that DW_apb_i2c in the master mode has sent a General...
+ // 0x00000010 [4] : ABRT_GCALL_NOACK (0): This field indicates that DW_apb_i2c in master mode has sent a General...
+ // 0x00000008 [3] : ABRT_TXDATA_NOACK (0): This field indicates the master-mode only bit
+ // 0x00000004 [2] : ABRT_10ADDR2_NOACK (0): This field indicates that the Master is in 10-bit address mode and that...
+ // 0x00000002 [1] : ABRT_10ADDR1_NOACK (0): This field indicates that the Master is in 10-bit address mode and the...
+ // 0x00000001 [0] : ABRT_7B_ADDR_NOACK (0): This field indicates that the Master is in 7-bit addressing mode and...
+ io_ro_32 tx_abrt_source;
+
+ _REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
+ // Generate Slave Data NACK Register
+ // 0x00000001 [0] : NACK (0): Generate NACK
+ io_rw_32 slv_data_nack_only;
+
+ _REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
+ // DMA Control Register
+ // 0x00000002 [1] : TDMAE (0): Transmit DMA Enable
+ // 0x00000001 [0] : RDMAE (0): Receive DMA Enable
+ io_rw_32 dma_cr;
+
+ _REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
+ // DMA Transmit Data Level Register
+ // 0x0000000f [3:0] : DMATDL (0): Transmit Data Level
+ io_rw_32 dma_tdlr;
+
+ _REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
+ // I2C Receive Data Level Register
+ // 0x0000000f [3:0] : DMARDL (0): Receive Data Level
+ io_rw_32 dma_rdlr;
+
+ _REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
+ // I2C SDA Setup Register
+ // 0x000000ff [7:0] : SDA_SETUP (0x64): SDA Setup
+ io_rw_32 sda_setup;
+
+ _REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
+ // I2C ACK General Call Register
+ // 0x00000001 [0] : ACK_GEN_CALL (1): ACK General Call
+ io_rw_32 ack_general_call;
+
+ _REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
+ // I2C Enable Status Register
+ // 0x00000004 [2] : SLV_RX_DATA_LOST (0): Slave Received Data Lost
+ // 0x00000002 [1] : SLV_DISABLED_WHILE_BUSY (0): Slave Disabled While Busy (Transmit, Receive)
+ // 0x00000001 [0] : IC_EN (0): ic_en Status
+ io_ro_32 enable_status;
+
+ _REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
+ // I2C SS, FS or FM+ spike suppression limit
+ // 0x000000ff [7:0] : IC_FS_SPKLEN (0x7): This register must be set before any I2C bus transaction can take place to...
+ io_rw_32 fs_spklen;
+
+ uint32_t _pad2;
+
+ _REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
+ // Clear RESTART_DET Interrupt Register
+ // 0x00000001 [0] : CLR_RESTART_DET (0): Read this register to clear the RESTART_DET interrupt (bit 12) of...
+ io_ro_32 clr_restart_det;
+
+ uint32_t _pad3[18];
+
+ _REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
+ // Component Parameter Register 1
+ // 0x00ff0000 [23:16] : TX_BUFFER_DEPTH (0): TX Buffer Depth = 16
+ // 0x0000ff00 [15:8] : RX_BUFFER_DEPTH (0): RX Buffer Depth = 16
+ // 0x00000080 [7] : ADD_ENCODED_PARAMS (0): Encoded parameters not visible
+ // 0x00000040 [6] : HAS_DMA (0): DMA handshaking signals are enabled
+ // 0x00000020 [5] : INTR_IO (0): COMBINED Interrupt outputs
+ // 0x00000010 [4] : HC_COUNT_VALUES (0): Programmable count values for each mode
+ // 0x0000000c [3:2] : MAX_SPEED_MODE (0): MAX SPEED MODE = FAST MODE
+ // 0x00000003 [1:0] : APB_DATA_WIDTH (0): APB data bus width is 32 bits
+ io_ro_32 comp_param_1;
+
+ _REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
+ // I2C Component Version Register
+ // 0xffffffff [31:0] : IC_COMP_VERSION (0x3230312a)
+ io_ro_32 comp_version;
+
+ _REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
+ // I2C Component Type Register
+ // 0xffffffff [31:0] : IC_COMP_TYPE (0x44570140): Designware Component Type number = 0x44_57_01_40
+ io_ro_32 comp_type;
+} i2c_hw_t;
+
+#define i2c0_hw ((i2c_hw_t *const)I2C0_BASE)
+#define i2c1_hw ((i2c_hw_t *const)I2C1_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/interp.h b/arkanoid/pico/hardware/structs/interp.h
new file mode 100644
index 0000000..7b02bf2
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/interp.h
@@ -0,0 +1,82 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_INTERP_H
+#define _HARDWARE_STRUCTS_INTERP_H
+
+#include "../address_mapped.h"
+#include "../regs/sio.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/sio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
+ // (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
+ //
+ // Read/write access to accumulator 0
+ io_rw_32 accum[2];
+
+ _REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
+ // (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
+ //
+ // Read/write access to BASE0 register
+ io_rw_32 base[3];
+
+ _REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
+ // (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
+ //
+ // Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
+ io_ro_32 pop[3];
+
+ _REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
+ // (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
+ //
+ // Read LANE0 result, without altering any internal state (PEEK)
+ io_ro_32 peek[3];
+
+ _REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
+ // (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
+ //
+ // Control register for lane 0
+ // 0x02000000 [25] : OVERF (0): Set if either OVERF0 or OVERF1 is set
+ // 0x01000000 [24] : OVERF1 (0): Indicates if any masked-off MSBs in ACCUM1 are set
+ // 0x00800000 [23] : OVERF0 (0): Indicates if any masked-off MSBs in ACCUM0 are set
+ // 0x00200000 [21] : BLEND (0): Only present on INTERP0 on each core
+ // 0x00180000 [20:19] : FORCE_MSB (0): ORed into bits 29:28 of the lane result presented to the processor on the bus
+ // 0x00040000 [18] : ADD_RAW (0): If 1, mask + shift is bypassed for LANE0 result
+ // 0x00020000 [17] : CROSS_RESULT (0): If 1, feed the opposite lane's result into this lane's accumulator on POP
+ // 0x00010000 [16] : CROSS_INPUT (0): If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware
+ // 0x00008000 [15] : SIGNED (0): If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+ // 0x00007c00 [14:10] : MASK_MSB (0): The most-significant bit allowed to pass by the mask (inclusive)
+ // 0x000003e0 [9:5] : MASK_LSB (0): The least-significant bit allowed to pass by the mask (inclusive)
+ // 0x0000001f [4:0] : SHIFT (0): Logical right-shift applied to accumulator before masking
+ io_rw_32 ctrl[2];
+
+ _REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
+ // (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
+ //
+ // Values written here are atomically added to ACCUM0
+ // 0x00ffffff [23:0] : INTERP0_ACCUM0_ADD (0)
+ io_rw_32 add_raw[2];
+
+ _REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
+ // On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously
+ io_wo_32 base01;
+} interp_hw_t;
+
+#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
+#define interp0_hw (&interp_hw_array[0])
+#define interp1_hw (&interp_hw_array[1])
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/iobank0.h b/arkanoid/pico/hardware/structs/iobank0.h
new file mode 100644
index 0000000..6bad35a
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/iobank0.h
@@ -0,0 +1,216 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_IOBANK0_H
+#define _HARDWARE_STRUCTS_IOBANK0_H
+
+#include "../address_mapped.h"
+#include "../regs/io_bank0.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/io_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
+ // GPIO status
+ // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied
+ // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied
+ // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied
+ // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied
+ // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied
+ // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+ // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied
+ // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+ io_ro_32 status;
+
+ _REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
+ // GPIO control including function select and overrides
+ // 0x30000000 [29:28] : IRQOVER (0)
+ // 0x00030000 [17:16] : INOVER (0)
+ // 0x00003000 [13:12] : OEOVER (0)
+ // 0x00000300 [9:8] : OUTOVER (0)
+ // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
+ io_rw_32 ctrl;
+} iobank0_status_ctrl_hw_t;
+
+typedef struct {
+ _REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
+ // (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
+ //
+ // Interrupt Enable for proc0
+ // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
+ // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
+ // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
+ // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
+ // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
+ // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
+ // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
+ // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
+ // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
+ io_rw_32 inte[4];
+
+ _REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
+ // (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
+ //
+ // Interrupt Force for proc0
+ // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
+ // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
+ // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
+ // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
+ // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
+ // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
+ // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
+ // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
+ // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
+ io_rw_32 intf[4];
+
+ _REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
+ // (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
+ //
+ // Interrupt status after masking & forcing for proc0
+ // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
+ // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
+ // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
+ // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
+ // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
+ // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
+ // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
+ // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
+ // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
+ io_ro_32 ints[4];
+} io_irq_ctrl_hw_t;
+
+/// \tag::iobank0_hw[]
+typedef struct {
+ iobank0_status_ctrl_hw_t io[NUM_BANK0_GPIOS]; // 30
+
+ _REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
+ // (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
+ //
+ // Raw Interrupts
+ // 0x80000000 [31] : GPIO7_EDGE_HIGH (0)
+ // 0x40000000 [30] : GPIO7_EDGE_LOW (0)
+ // 0x20000000 [29] : GPIO7_LEVEL_HIGH (0)
+ // 0x10000000 [28] : GPIO7_LEVEL_LOW (0)
+ // 0x08000000 [27] : GPIO6_EDGE_HIGH (0)
+ // 0x04000000 [26] : GPIO6_EDGE_LOW (0)
+ // 0x02000000 [25] : GPIO6_LEVEL_HIGH (0)
+ // 0x01000000 [24] : GPIO6_LEVEL_LOW (0)
+ // 0x00800000 [23] : GPIO5_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO5_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO5_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO5_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO4_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO4_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO4_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO4_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO3_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO3_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO3_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO3_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO2_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO2_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO2_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO2_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO1_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO1_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO1_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO1_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO0_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO0_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO0_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO0_LEVEL_LOW (0)
+ io_rw_32 intr[4];
+
+ io_irq_ctrl_hw_t proc0_irq_ctrl;
+
+ io_irq_ctrl_hw_t proc1_irq_ctrl;
+
+ io_irq_ctrl_hw_t dormant_wake_irq_ctrl;
+} iobank0_hw_t;
+
+#define iobank0_hw ((iobank0_hw_t *const)IO_BANK0_BASE)
+/// \end::iobank0_hw[]
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/ioqspi.h b/arkanoid/pico/hardware/structs/ioqspi.h
new file mode 100644
index 0000000..b21607f
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/ioqspi.h
@@ -0,0 +1,174 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_IOQSPI_H
+#define _HARDWARE_STRUCTS_IOQSPI_H
+
+#include "../address_mapped.h"
+#include "../regs/io_qspi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/io_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
+ // GPIO status
+ // 0x04000000 [26] : IRQTOPROC (0): interrupt to processors, after override is applied
+ // 0x01000000 [24] : IRQFROMPAD (0): interrupt from pad before override is applied
+ // 0x00080000 [19] : INTOPERI (0): input signal to peripheral, after override is applied
+ // 0x00020000 [17] : INFROMPAD (0): input signal from pad, before override is applied
+ // 0x00002000 [13] : OETOPAD (0): output enable to pad after register override is applied
+ // 0x00001000 [12] : OEFROMPERI (0): output enable from selected peripheral, before register override is applied
+ // 0x00000200 [9] : OUTTOPAD (0): output signal to pad after register override is applied
+ // 0x00000100 [8] : OUTFROMPERI (0): output signal from selected peripheral, before register override is applied
+ io_ro_32 status;
+
+ _REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
+ // GPIO control including function select and overrides
+ // 0x30000000 [29:28] : IRQOVER (0)
+ // 0x00030000 [17:16] : INOVER (0)
+ // 0x00003000 [13:12] : OEOVER (0)
+ // 0x00000300 [9:8] : OUTOVER (0)
+ // 0x0000001f [4:0] : FUNCSEL (0x1f): 0-31 -> selects pin function according to the gpio table
+ io_rw_32 ctrl;
+} ioqspi_status_ctrl_hw_t;
+
+typedef struct {
+ _REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
+ // Interrupt Enable for proc0
+ // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+ io_rw_32 inte;
+
+ _REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
+ // Interrupt Force for proc0
+ // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+ io_rw_32 intf;
+
+ _REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
+ // Interrupt status after masking & forcing for proc0
+ // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+ io_ro_32 ints;
+} io_qspi_ctrl_hw_t;
+
+typedef struct {
+ ioqspi_status_ctrl_hw_t io[NUM_QSPI_GPIOS]; // 6
+
+ _REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
+ // Raw Interrupts
+ // 0x00800000 [23] : GPIO_QSPI_SD3_EDGE_HIGH (0)
+ // 0x00400000 [22] : GPIO_QSPI_SD3_EDGE_LOW (0)
+ // 0x00200000 [21] : GPIO_QSPI_SD3_LEVEL_HIGH (0)
+ // 0x00100000 [20] : GPIO_QSPI_SD3_LEVEL_LOW (0)
+ // 0x00080000 [19] : GPIO_QSPI_SD2_EDGE_HIGH (0)
+ // 0x00040000 [18] : GPIO_QSPI_SD2_EDGE_LOW (0)
+ // 0x00020000 [17] : GPIO_QSPI_SD2_LEVEL_HIGH (0)
+ // 0x00010000 [16] : GPIO_QSPI_SD2_LEVEL_LOW (0)
+ // 0x00008000 [15] : GPIO_QSPI_SD1_EDGE_HIGH (0)
+ // 0x00004000 [14] : GPIO_QSPI_SD1_EDGE_LOW (0)
+ // 0x00002000 [13] : GPIO_QSPI_SD1_LEVEL_HIGH (0)
+ // 0x00001000 [12] : GPIO_QSPI_SD1_LEVEL_LOW (0)
+ // 0x00000800 [11] : GPIO_QSPI_SD0_EDGE_HIGH (0)
+ // 0x00000400 [10] : GPIO_QSPI_SD0_EDGE_LOW (0)
+ // 0x00000200 [9] : GPIO_QSPI_SD0_LEVEL_HIGH (0)
+ // 0x00000100 [8] : GPIO_QSPI_SD0_LEVEL_LOW (0)
+ // 0x00000080 [7] : GPIO_QSPI_SS_EDGE_HIGH (0)
+ // 0x00000040 [6] : GPIO_QSPI_SS_EDGE_LOW (0)
+ // 0x00000020 [5] : GPIO_QSPI_SS_LEVEL_HIGH (0)
+ // 0x00000010 [4] : GPIO_QSPI_SS_LEVEL_LOW (0)
+ // 0x00000008 [3] : GPIO_QSPI_SCLK_EDGE_HIGH (0)
+ // 0x00000004 [2] : GPIO_QSPI_SCLK_EDGE_LOW (0)
+ // 0x00000002 [1] : GPIO_QSPI_SCLK_LEVEL_HIGH (0)
+ // 0x00000001 [0] : GPIO_QSPI_SCLK_LEVEL_LOW (0)
+ io_rw_32 intr;
+
+ io_qspi_ctrl_hw_t proc0_qspi_ctrl;
+
+ io_qspi_ctrl_hw_t proc1_qspi_ctrl;
+
+ io_qspi_ctrl_hw_t dormant_wake_qspi_ctrl;
+} ioqspi_hw_t;
+
+#define ioqspi_hw ((ioqspi_hw_t *const)IO_QSPI_BASE)
+
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/mpu.h b/arkanoid/pico/hardware/structs/mpu.h
new file mode 100644
index 0000000..bf09782
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/mpu.h
@@ -0,0 +1,61 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_MPU_H
+#define _HARDWARE_STRUCTS_MPU_H
+
+#include "../address_mapped.h"
+#include "../regs/m0plus.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
+ // Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports
+ // 0x00ff0000 [23:16] : IREGION (0): Instruction region
+ // 0x0000ff00 [15:8] : DREGION (0x8): Number of regions supported by the MPU
+ // 0x00000001 [0] : SEPARATE (0): Indicates support for separate instruction and data address maps
+ io_ro_32 type;
+
+ _REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
+ // Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled...
+ // 0x00000004 [2] : PRIVDEFENA (0): Controls whether the default memory map is enabled as a background region for...
+ // 0x00000002 [1] : HFNMIENA (0): Controls the use of the MPU for HardFaults and NMIs
+ // 0x00000001 [0] : ENABLE (0): Enables the MPU
+ io_rw_32 ctrl;
+
+ _REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
+ // Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR
+ // 0x0000000f [3:0] : REGION (0): Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers
+ io_rw_32 rnr;
+
+ _REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
+ // Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR
+ // 0xffffff00 [31:8] : ADDR (0): Base address of the region
+ // 0x00000010 [4] : VALID (0): On writes, indicates whether the write must update the base address of the region...
+ // 0x0000000f [3:0] : REGION (0): On writes, specifies the number of the region whose base address to update provided...
+ io_rw_32 rbar;
+
+ _REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
+ // Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region...
+ // 0xffff0000 [31:16] : ATTRS (0): The MPU Region Attribute field
+ // 0x0000ff00 [15:8] : SRD (0): Subregion Disable
+ // 0x0000003e [5:1] : SIZE (0): Indicates the region size
+ // 0x00000001 [0] : ENABLE (0): Enables the region
+ io_rw_32 rasr;
+} mpu_hw_t;
+
+#define mpu_hw ((mpu_hw_t *const)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/pads_qspi.h b/arkanoid/pico/hardware/structs/pads_qspi.h
new file mode 100644
index 0000000..07fa454
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/pads_qspi.h
@@ -0,0 +1,47 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H
+#define _HARDWARE_STRUCTS_PADS_QSPI_H
+
+#include "../address_mapped.h"
+#include "../regs/pads_qspi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/pads_qspi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
+ // Voltage select
+ // 0x00000001 [0] : VOLTAGE_SELECT (0)
+ io_rw_32 voltage_select;
+
+ _REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
+ // (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
+ //
+ // Pad control register
+ // 0x00000080 [7] : OD (0): Output disable
+ // 0x00000040 [6] : IE (1): Input enable
+ // 0x00000030 [5:4] : DRIVE (1): Drive strength
+ // 0x00000008 [3] : PUE (0): Pull up enable
+ // 0x00000004 [2] : PDE (1): Pull down enable
+ // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger
+ // 0x00000001 [0] : SLEWFAST (0): Slew rate control
+ io_rw_32 io[NUM_QSPI_GPIOS]; // 6
+} pads_qspi_hw_t;
+
+#define pads_qspi_hw ((pads_qspi_hw_t *const)PADS_QSPI_BASE)
+
+static_assert( NUM_QSPI_GPIOS == 6, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/padsbank0.h b/arkanoid/pico/hardware/structs/padsbank0.h
new file mode 100644
index 0000000..471e361
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/padsbank0.h
@@ -0,0 +1,47 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PADSBANK0_H
+#define _HARDWARE_STRUCTS_PADSBANK0_H
+
+#include "../address_mapped.h"
+#include "../regs/pads_bank0.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/pads_bank0.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
+ // Voltage select
+ // 0x00000001 [0] : VOLTAGE_SELECT (0)
+ io_rw_32 voltage_select;
+
+ _REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
+ // (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
+ //
+ // Pad control register
+ // 0x00000080 [7] : OD (0): Output disable
+ // 0x00000040 [6] : IE (1): Input enable
+ // 0x00000030 [5:4] : DRIVE (1): Drive strength
+ // 0x00000008 [3] : PUE (0): Pull up enable
+ // 0x00000004 [2] : PDE (1): Pull down enable
+ // 0x00000002 [1] : SCHMITT (1): Enable schmitt trigger
+ // 0x00000001 [0] : SLEWFAST (0): Slew rate control
+ io_rw_32 io[NUM_BANK0_GPIOS]; // 30
+} padsbank0_hw_t;
+
+#define padsbank0_hw ((padsbank0_hw_t *const)PADS_BANK0_BASE)
+
+static_assert( NUM_BANK0_GPIOS == 30, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/pio.h b/arkanoid/pico/hardware/structs/pio.h
new file mode 100644
index 0000000..e52766d
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/pio.h
@@ -0,0 +1,284 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PIO_H
+#define _HARDWARE_STRUCTS_PIO_H
+
+#include "../address_mapped.h"
+#include "../regs/pio.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/pio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct pio_sm_hw {
+ _REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
+ // Clock divisor register for state machine 0
+ // 0xffff0000 [31:16] : INT (1): Effective frequency is sysclk/(int + frac/256)
+ // 0x0000ff00 [15:8] : FRAC (0): Fractional part of clock divisor
+ io_rw_32 clkdiv;
+
+ _REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
+ // Execution/behavioural settings for state machine 0
+ // 0x80000000 [31] : EXEC_STALLED (0): If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine
+ // 0x40000000 [30] : SIDE_EN (0): If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable,...
+ // 0x20000000 [29] : SIDE_PINDIR (0): If 1, side-set data is asserted to pin directions, instead of pin values
+ // 0x1f000000 [28:24] : JMP_PIN (0): The GPIO number to use as condition for JMP PIN
+ // 0x00f80000 [23:19] : OUT_EN_SEL (0): Which data bit to use for inline OUT enable
+ // 0x00040000 [18] : INLINE_OUT_EN (0): If 1, use a bit of OUT data as an auxiliary write enable
+ // 0x00020000 [17] : OUT_STICKY (0): Continuously assert the most recent OUT/SET to the pins
+ // 0x0001f000 [16:12] : WRAP_TOP (0x1f): After reaching this address, execution is wrapped to wrap_bottom
+ // 0x00000f80 [11:7] : WRAP_BOTTOM (0): After reaching wrap_top, execution is wrapped to this address
+ // 0x00000010 [4] : STATUS_SEL (0): Comparison used for the MOV x, STATUS instruction
+ // 0x0000000f [3:0] : STATUS_N (0): Comparison level for the MOV x, STATUS instruction
+ io_rw_32 execctrl;
+
+ _REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
+ // Control behaviour of the input/output shift registers for state machine 0
+ // 0x80000000 [31] : FJOIN_RX (0): When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep
+ // 0x40000000 [30] : FJOIN_TX (0): When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep
+ // 0x3e000000 [29:25] : PULL_THRESH (0): Number of bits shifted out of OSR before autopull, or conditional pull (PULL...
+ // 0x01f00000 [24:20] : PUSH_THRESH (0): Number of bits shifted into ISR before autopush, or conditional push (PUSH...
+ // 0x00080000 [19] : OUT_SHIFTDIR (1): 1 = shift out of output shift register to right
+ // 0x00040000 [18] : IN_SHIFTDIR (1): 1 = shift input shift register to right (data enters from left)
+ // 0x00020000 [17] : AUTOPULL (0): Pull automatically when the output shift register is emptied, i
+ // 0x00010000 [16] : AUTOPUSH (0): Push automatically when the input shift register is filled, i
+ io_rw_32 shiftctrl;
+
+ _REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
+ // Current instruction address of state machine 0
+ // 0x0000001f [4:0] : SM0_ADDR (0)
+ io_ro_32 addr;
+
+ _REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
+ // Read to see the instruction currently addressed by state machine 0's program counter
+ // 0x0000ffff [15:0] : SM0_INSTR (0)
+ io_rw_32 instr;
+
+ _REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
+ // State machine pin control
+ // 0xe0000000 [31:29] : SIDESET_COUNT (0): The number of MSBs of the Delay/Side-set instruction field which are used...
+ // 0x1c000000 [28:26] : SET_COUNT (0x5): The number of pins asserted by a SET
+ // 0x03f00000 [25:20] : OUT_COUNT (0): The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction
+ // 0x000f8000 [19:15] : IN_BASE (0): The pin which is mapped to the least-significant bit of a state machine's IN data bus
+ // 0x00007c00 [14:10] : SIDESET_BASE (0): The lowest-numbered pin that will be affected by a side-set operation
+ // 0x000003e0 [9:5] : SET_BASE (0): The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction
+ // 0x0000001f [4:0] : OUT_BASE (0): The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV...
+ io_rw_32 pinctrl;
+} pio_sm_hw_t;
+
+typedef struct {
+ _REG_(PIO_CTRL_OFFSET) // PIO_CTRL
+ // PIO control register
+ // 0x00000f00 [11:8] : CLKDIV_RESTART (0): Restart a state machine's clock divider from an initial phase of 0
+ // 0x000000f0 [7:4] : SM_RESTART (0): Write 1 to instantly clear internal SM state which may be otherwise difficult...
+ // 0x0000000f [3:0] : SM_ENABLE (0): Enable/disable each of the four state machines by writing 1/0 to each of these four bits
+ io_rw_32 ctrl;
+
+ _REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
+ // FIFO status register
+ // 0x0f000000 [27:24] : TXEMPTY (0xf): State machine TX FIFO is empty
+ // 0x000f0000 [19:16] : TXFULL (0): State machine TX FIFO is full
+ // 0x00000f00 [11:8] : RXEMPTY (0xf): State machine RX FIFO is empty
+ // 0x0000000f [3:0] : RXFULL (0): State machine RX FIFO is full
+ io_ro_32 fstat;
+
+ _REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
+ // FIFO debug register
+ // 0x0f000000 [27:24] : TXSTALL (0): State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with...
+ // 0x000f0000 [19:16] : TXOVER (0): TX FIFO overflow (i
+ // 0x00000f00 [11:8] : RXUNDER (0): RX FIFO underflow (i
+ // 0x0000000f [3:0] : RXSTALL (0): State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with...
+ io_rw_32 fdebug;
+
+ _REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
+ // FIFO levels
+ // 0xf0000000 [31:28] : RX3 (0)
+ // 0x0f000000 [27:24] : TX3 (0)
+ // 0x00f00000 [23:20] : RX2 (0)
+ // 0x000f0000 [19:16] : TX2 (0)
+ // 0x0000f000 [15:12] : RX1 (0)
+ // 0x00000f00 [11:8] : TX1 (0)
+ // 0x000000f0 [7:4] : RX0 (0)
+ // 0x0000000f [3:0] : TX0 (0)
+ io_ro_32 flevel;
+
+ _REG_(PIO_TXF0_OFFSET) // PIO_TXF0
+ // (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
+ //
+ // Direct write access to the TX FIFO for this state machine
+ io_wo_32 txf[NUM_PIO_STATE_MACHINES]; // 4
+
+ _REG_(PIO_RXF0_OFFSET) // PIO_RXF0
+ // (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
+ //
+ // Direct read access to the RX FIFO for this state machine
+ io_ro_32 rxf[NUM_PIO_STATE_MACHINES]; // 4
+
+ _REG_(PIO_IRQ_OFFSET) // PIO_IRQ
+ // State machine IRQ flags register
+ // 0x000000ff [7:0] : IRQ (0)
+ io_rw_32 irq;
+
+ _REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
+ // Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
+ // 0x000000ff [7:0] : IRQ_FORCE (0)
+ io_wo_32 irq_force;
+
+ _REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
+ // There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
+ io_rw_32 input_sync_bypass;
+
+ _REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
+ // Read to sample the pad output values PIO is currently driving to the GPIOs
+ io_ro_32 dbg_padout;
+
+ _REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
+ // Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
+ io_ro_32 dbg_padoe;
+
+ _REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
+ // The PIO hardware has some free parameters that may vary between chip products
+ // 0x003f0000 [21:16] : IMEM_SIZE (0): The size of the instruction memory, measured in units of one instruction
+ // 0x00000f00 [11:8] : SM_COUNT (0): The number of state machines this PIO instance is equipped with
+ // 0x0000003f [5:0] : FIFO_DEPTH (0): The depth of the state machine TX/RX FIFOs, measured in words
+ io_ro_32 dbg_cfginfo;
+
+ _REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
+ // (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
+ //
+ // Write-only access to instruction memory location 0
+ // 0x0000ffff [15:0] : INSTR_MEM0 (0)
+ io_wo_32 instr_mem[PIO_INSTRUCTION_COUNT]; // 32
+
+ pio_sm_hw_t sm[NUM_PIO_STATE_MACHINES]; // 4
+
+ _REG_(PIO_INTR_OFFSET) // PIO_INTR
+ // Raw Interrupts
+ // 0x00000800 [11] : SM3 (0)
+ // 0x00000400 [10] : SM2 (0)
+ // 0x00000200 [9] : SM1 (0)
+ // 0x00000100 [8] : SM0 (0)
+ // 0x00000080 [7] : SM3_TXNFULL (0)
+ // 0x00000040 [6] : SM2_TXNFULL (0)
+ // 0x00000020 [5] : SM1_TXNFULL (0)
+ // 0x00000010 [4] : SM0_TXNFULL (0)
+ // 0x00000008 [3] : SM3_RXNEMPTY (0)
+ // 0x00000004 [2] : SM2_RXNEMPTY (0)
+ // 0x00000002 [1] : SM1_RXNEMPTY (0)
+ // 0x00000001 [0] : SM0_RXNEMPTY (0)
+ io_ro_32 intr;
+
+ _REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
+ // Interrupt Enable for irq0
+ // 0x00000800 [11] : SM3 (0)
+ // 0x00000400 [10] : SM2 (0)
+ // 0x00000200 [9] : SM1 (0)
+ // 0x00000100 [8] : SM0 (0)
+ // 0x00000080 [7] : SM3_TXNFULL (0)
+ // 0x00000040 [6] : SM2_TXNFULL (0)
+ // 0x00000020 [5] : SM1_TXNFULL (0)
+ // 0x00000010 [4] : SM0_TXNFULL (0)
+ // 0x00000008 [3] : SM3_RXNEMPTY (0)
+ // 0x00000004 [2] : SM2_RXNEMPTY (0)
+ // 0x00000002 [1] : SM1_RXNEMPTY (0)
+ // 0x00000001 [0] : SM0_RXNEMPTY (0)
+ io_rw_32 inte0;
+
+ _REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
+ // Interrupt Force for irq0
+ // 0x00000800 [11] : SM3 (0)
+ // 0x00000400 [10] : SM2 (0)
+ // 0x00000200 [9] : SM1 (0)
+ // 0x00000100 [8] : SM0 (0)
+ // 0x00000080 [7] : SM3_TXNFULL (0)
+ // 0x00000040 [6] : SM2_TXNFULL (0)
+ // 0x00000020 [5] : SM1_TXNFULL (0)
+ // 0x00000010 [4] : SM0_TXNFULL (0)
+ // 0x00000008 [3] : SM3_RXNEMPTY (0)
+ // 0x00000004 [2] : SM2_RXNEMPTY (0)
+ // 0x00000002 [1] : SM1_RXNEMPTY (0)
+ // 0x00000001 [0] : SM0_RXNEMPTY (0)
+ io_rw_32 intf0;
+
+ _REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
+ // Interrupt status after masking & forcing for irq0
+ // 0x00000800 [11] : SM3 (0)
+ // 0x00000400 [10] : SM2 (0)
+ // 0x00000200 [9] : SM1 (0)
+ // 0x00000100 [8] : SM0 (0)
+ // 0x00000080 [7] : SM3_TXNFULL (0)
+ // 0x00000040 [6] : SM2_TXNFULL (0)
+ // 0x00000020 [5] : SM1_TXNFULL (0)
+ // 0x00000010 [4] : SM0_TXNFULL (0)
+ // 0x00000008 [3] : SM3_RXNEMPTY (0)
+ // 0x00000004 [2] : SM2_RXNEMPTY (0)
+ // 0x00000002 [1] : SM1_RXNEMPTY (0)
+ // 0x00000001 [0] : SM0_RXNEMPTY (0)
+ io_ro_32 ints0;
+
+ _REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
+ // Interrupt Enable for irq1
+ // 0x00000800 [11] : SM3 (0)
+ // 0x00000400 [10] : SM2 (0)
+ // 0x00000200 [9] : SM1 (0)
+ // 0x00000100 [8] : SM0 (0)
+ // 0x00000080 [7] : SM3_TXNFULL (0)
+ // 0x00000040 [6] : SM2_TXNFULL (0)
+ // 0x00000020 [5] : SM1_TXNFULL (0)
+ // 0x00000010 [4] : SM0_TXNFULL (0)
+ // 0x00000008 [3] : SM3_RXNEMPTY (0)
+ // 0x00000004 [2] : SM2_RXNEMPTY (0)
+ // 0x00000002 [1] : SM1_RXNEMPTY (0)
+ // 0x00000001 [0] : SM0_RXNEMPTY (0)
+ io_rw_32 inte1;
+
+ _REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
+ // Interrupt Force for irq1
+ // 0x00000800 [11] : SM3 (0)
+ // 0x00000400 [10] : SM2 (0)
+ // 0x00000200 [9] : SM1 (0)
+ // 0x00000100 [8] : SM0 (0)
+ // 0x00000080 [7] : SM3_TXNFULL (0)
+ // 0x00000040 [6] : SM2_TXNFULL (0)
+ // 0x00000020 [5] : SM1_TXNFULL (0)
+ // 0x00000010 [4] : SM0_TXNFULL (0)
+ // 0x00000008 [3] : SM3_RXNEMPTY (0)
+ // 0x00000004 [2] : SM2_RXNEMPTY (0)
+ // 0x00000002 [1] : SM1_RXNEMPTY (0)
+ // 0x00000001 [0] : SM0_RXNEMPTY (0)
+ io_rw_32 intf1;
+
+ _REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
+ // Interrupt status after masking & forcing for irq1
+ // 0x00000800 [11] : SM3 (0)
+ // 0x00000400 [10] : SM2 (0)
+ // 0x00000200 [9] : SM1 (0)
+ // 0x00000100 [8] : SM0 (0)
+ // 0x00000080 [7] : SM3_TXNFULL (0)
+ // 0x00000040 [6] : SM2_TXNFULL (0)
+ // 0x00000020 [5] : SM1_TXNFULL (0)
+ // 0x00000010 [4] : SM0_TXNFULL (0)
+ // 0x00000008 [3] : SM3_RXNEMPTY (0)
+ // 0x00000004 [2] : SM2_RXNEMPTY (0)
+ // 0x00000002 [1] : SM1_RXNEMPTY (0)
+ // 0x00000001 [0] : SM0_RXNEMPTY (0)
+ io_ro_32 ints1;
+} pio_hw_t;
+
+#define pio0_hw ((pio_hw_t *const)PIO0_BASE)
+#define pio1_hw ((pio_hw_t *const)PIO1_BASE)
+
+static_assert( NUM_PIO_STATE_MACHINES == 4, "");
+static_assert( PIO_INSTRUCTION_COUNT == 32, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/pll.h b/arkanoid/pico/hardware/structs/pll.h
new file mode 100644
index 0000000..8331052
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/pll.h
@@ -0,0 +1,56 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PLL_H
+#define _HARDWARE_STRUCTS_PLL_H
+
+#include "../address_mapped.h"
+#include "../regs/pll.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/pll.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/// \tag::pll_hw[]
+typedef struct {
+ _REG_(PLL_CS_OFFSET) // PLL_CS
+ // Control and Status
+ // 0x80000000 [31] : LOCK (0): PLL is locked
+ // 0x00000100 [8] : BYPASS (0): Passes the reference clock to the output instead of the divided VCO
+ // 0x0000003f [5:0] : REFDIV (1): Divides the PLL input reference clock
+ io_rw_32 cs;
+
+ _REG_(PLL_PWR_OFFSET) // PLL_PWR
+ // Controls the PLL power modes
+ // 0x00000020 [5] : VCOPD (1): PLL VCO powerdown
+ // 0x00000008 [3] : POSTDIVPD (1): PLL post divider powerdown
+ // 0x00000004 [2] : DSMPD (1): PLL DSM powerdown
+ // 0x00000001 [0] : PD (1): PLL powerdown
+ io_rw_32 pwr;
+
+ _REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
+ // Feedback divisor
+ // 0x00000fff [11:0] : FBDIV_INT (0): see ctrl reg description for constraints
+ io_rw_32 fbdiv_int;
+
+ _REG_(PLL_PRIM_OFFSET) // PLL_PRIM
+ // Controls the PLL post dividers for the primary output
+ // 0x00070000 [18:16] : POSTDIV1 (0x7): divide by 1-7
+ // 0x00007000 [14:12] : POSTDIV2 (0x7): divide by 1-7
+ io_rw_32 prim;
+} pll_hw_t;
+
+#define pll_sys_hw ((pll_hw_t *const)PLL_SYS_BASE)
+#define pll_usb_hw ((pll_hw_t *const)PLL_USB_BASE)
+/// \end::pll_hw[]
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/psm.h b/arkanoid/pico/hardware/structs/psm.h
new file mode 100644
index 0000000..d293a23
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/psm.h
@@ -0,0 +1,111 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PSM_H
+#define _HARDWARE_STRUCTS_PSM_H
+
+#include "../address_mapped.h"
+#include "../regs/psm.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/psm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
+ // Force block out of reset (i
+ // 0x00010000 [16] : proc1 (0)
+ // 0x00008000 [15] : proc0 (0)
+ // 0x00004000 [14] : sio (0)
+ // 0x00002000 [13] : vreg_and_chip_reset (0)
+ // 0x00001000 [12] : xip (0)
+ // 0x00000800 [11] : sram5 (0)
+ // 0x00000400 [10] : sram4 (0)
+ // 0x00000200 [9] : sram3 (0)
+ // 0x00000100 [8] : sram2 (0)
+ // 0x00000080 [7] : sram1 (0)
+ // 0x00000040 [6] : sram0 (0)
+ // 0x00000020 [5] : rom (0)
+ // 0x00000010 [4] : busfabric (0)
+ // 0x00000008 [3] : resets (0)
+ // 0x00000004 [2] : clocks (0)
+ // 0x00000002 [1] : xosc (0)
+ // 0x00000001 [0] : rosc (0)
+ io_rw_32 frce_on;
+
+ _REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
+ // Force into reset (i
+ // 0x00010000 [16] : proc1 (0)
+ // 0x00008000 [15] : proc0 (0)
+ // 0x00004000 [14] : sio (0)
+ // 0x00002000 [13] : vreg_and_chip_reset (0)
+ // 0x00001000 [12] : xip (0)
+ // 0x00000800 [11] : sram5 (0)
+ // 0x00000400 [10] : sram4 (0)
+ // 0x00000200 [9] : sram3 (0)
+ // 0x00000100 [8] : sram2 (0)
+ // 0x00000080 [7] : sram1 (0)
+ // 0x00000040 [6] : sram0 (0)
+ // 0x00000020 [5] : rom (0)
+ // 0x00000010 [4] : busfabric (0)
+ // 0x00000008 [3] : resets (0)
+ // 0x00000004 [2] : clocks (0)
+ // 0x00000002 [1] : xosc (0)
+ // 0x00000001 [0] : rosc (0)
+ io_rw_32 frce_off;
+
+ _REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
+ // Set to 1 if this peripheral should be reset when the watchdog fires
+ // 0x00010000 [16] : proc1 (0)
+ // 0x00008000 [15] : proc0 (0)
+ // 0x00004000 [14] : sio (0)
+ // 0x00002000 [13] : vreg_and_chip_reset (0)
+ // 0x00001000 [12] : xip (0)
+ // 0x00000800 [11] : sram5 (0)
+ // 0x00000400 [10] : sram4 (0)
+ // 0x00000200 [9] : sram3 (0)
+ // 0x00000100 [8] : sram2 (0)
+ // 0x00000080 [7] : sram1 (0)
+ // 0x00000040 [6] : sram0 (0)
+ // 0x00000020 [5] : rom (0)
+ // 0x00000010 [4] : busfabric (0)
+ // 0x00000008 [3] : resets (0)
+ // 0x00000004 [2] : clocks (0)
+ // 0x00000002 [1] : xosc (0)
+ // 0x00000001 [0] : rosc (0)
+ io_rw_32 wdsel;
+
+ _REG_(PSM_DONE_OFFSET) // PSM_DONE
+ // Indicates the peripheral's registers are ready to access
+ // 0x00010000 [16] : proc1 (0)
+ // 0x00008000 [15] : proc0 (0)
+ // 0x00004000 [14] : sio (0)
+ // 0x00002000 [13] : vreg_and_chip_reset (0)
+ // 0x00001000 [12] : xip (0)
+ // 0x00000800 [11] : sram5 (0)
+ // 0x00000400 [10] : sram4 (0)
+ // 0x00000200 [9] : sram3 (0)
+ // 0x00000100 [8] : sram2 (0)
+ // 0x00000080 [7] : sram1 (0)
+ // 0x00000040 [6] : sram0 (0)
+ // 0x00000020 [5] : rom (0)
+ // 0x00000010 [4] : busfabric (0)
+ // 0x00000008 [3] : resets (0)
+ // 0x00000004 [2] : clocks (0)
+ // 0x00000002 [1] : xosc (0)
+ // 0x00000001 [0] : rosc (0)
+ io_ro_32 done;
+} psm_hw_t;
+
+#define psm_hw ((psm_hw_t *const)PSM_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/pwm.h b/arkanoid/pico/hardware/structs/pwm.h
new file mode 100644
index 0000000..18818f6
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/pwm.h
@@ -0,0 +1,126 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_PWM_H
+#define _HARDWARE_STRUCTS_PWM_H
+
+#include "../address_mapped.h"
+#include "../regs/pwm.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/pwm.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct pwm_slice_hw {
+ _REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
+ // Control and status register
+ // 0x00000080 [7] : PH_ADV (0): Advance the phase of the counter by 1 count, while it is running
+ // 0x00000040 [6] : PH_RET (0): Retard the phase of the counter by 1 count, while it is running
+ // 0x00000030 [5:4] : DIVMODE (0)
+ // 0x00000008 [3] : B_INV (0): Invert output B
+ // 0x00000004 [2] : A_INV (0): Invert output A
+ // 0x00000002 [1] : PH_CORRECT (0): 1: Enable phase-correct modulation
+ // 0x00000001 [0] : EN (0): Enable the PWM channel
+ io_rw_32 csr;
+
+ _REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
+ // INT and FRAC form a fixed-point fractional number
+ // 0x00000ff0 [11:4] : INT (1)
+ // 0x0000000f [3:0] : FRAC (0)
+ io_rw_32 div;
+
+ _REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
+ // Direct access to the PWM counter
+ // 0x0000ffff [15:0] : CH0_CTR (0)
+ io_rw_32 ctr;
+
+ _REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
+ // Counter compare values
+ // 0xffff0000 [31:16] : B (0)
+ // 0x0000ffff [15:0] : A (0)
+ io_rw_32 cc;
+
+ _REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
+ // Counter wrap value
+ // 0x0000ffff [15:0] : CH0_TOP (0xffff)
+ io_rw_32 top;
+} pwm_slice_hw_t;
+
+typedef struct {
+ pwm_slice_hw_t slice[NUM_PWM_SLICES]; // 8
+
+ _REG_(PWM_EN_OFFSET) // PWM_EN
+ // This register aliases the CSR_EN bits for all channels
+ // 0x00000080 [7] : CH7 (0)
+ // 0x00000040 [6] : CH6 (0)
+ // 0x00000020 [5] : CH5 (0)
+ // 0x00000010 [4] : CH4 (0)
+ // 0x00000008 [3] : CH3 (0)
+ // 0x00000004 [2] : CH2 (0)
+ // 0x00000002 [1] : CH1 (0)
+ // 0x00000001 [0] : CH0 (0)
+ io_rw_32 en;
+
+ _REG_(PWM_INTR_OFFSET) // PWM_INTR
+ // Raw Interrupts
+ // 0x00000080 [7] : CH7 (0)
+ // 0x00000040 [6] : CH6 (0)
+ // 0x00000020 [5] : CH5 (0)
+ // 0x00000010 [4] : CH4 (0)
+ // 0x00000008 [3] : CH3 (0)
+ // 0x00000004 [2] : CH2 (0)
+ // 0x00000002 [1] : CH1 (0)
+ // 0x00000001 [0] : CH0 (0)
+ io_rw_32 intr;
+
+ _REG_(PWM_INTE_OFFSET) // PWM_INTE
+ // Interrupt Enable
+ // 0x00000080 [7] : CH7 (0)
+ // 0x00000040 [6] : CH6 (0)
+ // 0x00000020 [5] : CH5 (0)
+ // 0x00000010 [4] : CH4 (0)
+ // 0x00000008 [3] : CH3 (0)
+ // 0x00000004 [2] : CH2 (0)
+ // 0x00000002 [1] : CH1 (0)
+ // 0x00000001 [0] : CH0 (0)
+ io_rw_32 inte;
+
+ _REG_(PWM_INTF_OFFSET) // PWM_INTF
+ // Interrupt Force
+ // 0x00000080 [7] : CH7 (0)
+ // 0x00000040 [6] : CH6 (0)
+ // 0x00000020 [5] : CH5 (0)
+ // 0x00000010 [4] : CH4 (0)
+ // 0x00000008 [3] : CH3 (0)
+ // 0x00000004 [2] : CH2 (0)
+ // 0x00000002 [1] : CH1 (0)
+ // 0x00000001 [0] : CH0 (0)
+ io_rw_32 intf;
+
+ _REG_(PWM_INTS_OFFSET) // PWM_INTS
+ // Interrupt status after masking & forcing
+ // 0x00000080 [7] : CH7 (0)
+ // 0x00000040 [6] : CH6 (0)
+ // 0x00000020 [5] : CH5 (0)
+ // 0x00000010 [4] : CH4 (0)
+ // 0x00000008 [3] : CH3 (0)
+ // 0x00000004 [2] : CH2 (0)
+ // 0x00000002 [1] : CH1 (0)
+ // 0x00000001 [0] : CH0 (0)
+ io_ro_32 ints;
+} pwm_hw_t;
+
+#define pwm_hw ((pwm_hw_t *const)PWM_BASE)
+
+static_assert( NUM_PWM_SLICES == 8, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/resets.h b/arkanoid/pico/hardware/structs/resets.h
new file mode 100644
index 0000000..2baeb51
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/resets.h
@@ -0,0 +1,116 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_RESETS_H
+#define _HARDWARE_STRUCTS_RESETS_H
+
+#include "../address_mapped.h"
+#include "../regs/resets.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/resets.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/// \tag::resets_hw[]
+typedef struct {
+ _REG_(RESETS_RESET_OFFSET) // RESETS_RESET
+ // Reset control
+ // 0x01000000 [24] : usbctrl (1)
+ // 0x00800000 [23] : uart1 (1)
+ // 0x00400000 [22] : uart0 (1)
+ // 0x00200000 [21] : timer (1)
+ // 0x00100000 [20] : tbman (1)
+ // 0x00080000 [19] : sysinfo (1)
+ // 0x00040000 [18] : syscfg (1)
+ // 0x00020000 [17] : spi1 (1)
+ // 0x00010000 [16] : spi0 (1)
+ // 0x00008000 [15] : rtc (1)
+ // 0x00004000 [14] : pwm (1)
+ // 0x00002000 [13] : pll_usb (1)
+ // 0x00001000 [12] : pll_sys (1)
+ // 0x00000800 [11] : pio1 (1)
+ // 0x00000400 [10] : pio0 (1)
+ // 0x00000200 [9] : pads_qspi (1)
+ // 0x00000100 [8] : pads_bank0 (1)
+ // 0x00000080 [7] : jtag (1)
+ // 0x00000040 [6] : io_qspi (1)
+ // 0x00000020 [5] : io_bank0 (1)
+ // 0x00000010 [4] : i2c1 (1)
+ // 0x00000008 [3] : i2c0 (1)
+ // 0x00000004 [2] : dma (1)
+ // 0x00000002 [1] : busctrl (1)
+ // 0x00000001 [0] : adc (1)
+ io_rw_32 reset;
+
+ _REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
+ // Watchdog select
+ // 0x01000000 [24] : usbctrl (0)
+ // 0x00800000 [23] : uart1 (0)
+ // 0x00400000 [22] : uart0 (0)
+ // 0x00200000 [21] : timer (0)
+ // 0x00100000 [20] : tbman (0)
+ // 0x00080000 [19] : sysinfo (0)
+ // 0x00040000 [18] : syscfg (0)
+ // 0x00020000 [17] : spi1 (0)
+ // 0x00010000 [16] : spi0 (0)
+ // 0x00008000 [15] : rtc (0)
+ // 0x00004000 [14] : pwm (0)
+ // 0x00002000 [13] : pll_usb (0)
+ // 0x00001000 [12] : pll_sys (0)
+ // 0x00000800 [11] : pio1 (0)
+ // 0x00000400 [10] : pio0 (0)
+ // 0x00000200 [9] : pads_qspi (0)
+ // 0x00000100 [8] : pads_bank0 (0)
+ // 0x00000080 [7] : jtag (0)
+ // 0x00000040 [6] : io_qspi (0)
+ // 0x00000020 [5] : io_bank0 (0)
+ // 0x00000010 [4] : i2c1 (0)
+ // 0x00000008 [3] : i2c0 (0)
+ // 0x00000004 [2] : dma (0)
+ // 0x00000002 [1] : busctrl (0)
+ // 0x00000001 [0] : adc (0)
+ io_rw_32 wdsel;
+
+ _REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
+ // Reset done
+ // 0x01000000 [24] : usbctrl (0)
+ // 0x00800000 [23] : uart1 (0)
+ // 0x00400000 [22] : uart0 (0)
+ // 0x00200000 [21] : timer (0)
+ // 0x00100000 [20] : tbman (0)
+ // 0x00080000 [19] : sysinfo (0)
+ // 0x00040000 [18] : syscfg (0)
+ // 0x00020000 [17] : spi1 (0)
+ // 0x00010000 [16] : spi0 (0)
+ // 0x00008000 [15] : rtc (0)
+ // 0x00004000 [14] : pwm (0)
+ // 0x00002000 [13] : pll_usb (0)
+ // 0x00001000 [12] : pll_sys (0)
+ // 0x00000800 [11] : pio1 (0)
+ // 0x00000400 [10] : pio0 (0)
+ // 0x00000200 [9] : pads_qspi (0)
+ // 0x00000100 [8] : pads_bank0 (0)
+ // 0x00000080 [7] : jtag (0)
+ // 0x00000040 [6] : io_qspi (0)
+ // 0x00000020 [5] : io_bank0 (0)
+ // 0x00000010 [4] : i2c1 (0)
+ // 0x00000008 [3] : i2c0 (0)
+ // 0x00000004 [2] : dma (0)
+ // 0x00000002 [1] : busctrl (0)
+ // 0x00000001 [0] : adc (0)
+ io_ro_32 reset_done;
+} resets_hw_t;
+
+#define resets_hw ((resets_hw_t *const)RESETS_BASE)
+/// \end::resets_hw[]
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/rosc.h b/arkanoid/pico/hardware/structs/rosc.h
new file mode 100644
index 0000000..db9c4e1
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/rosc.h
@@ -0,0 +1,86 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_ROSC_H
+#define _HARDWARE_STRUCTS_ROSC_H
+
+#include "../address_mapped.h"
+#include "../regs/rosc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/rosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
+ // Ring Oscillator control
+ // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to ENABLE
+ // 0x00000fff [11:0] : FREQ_RANGE (0xaa0): Controls the number of delay stages in the ROSC ring
+ io_rw_32 ctrl;
+
+ _REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
+ // The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
+ // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+ // 0x00007000 [14:12] : DS3 (0): Stage 3 drive strength
+ // 0x00000700 [10:8] : DS2 (0): Stage 2 drive strength
+ // 0x00000070 [6:4] : DS1 (0): Stage 1 drive strength
+ // 0x00000007 [2:0] : DS0 (0): Stage 0 drive strength
+ io_rw_32 freqa;
+
+ _REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
+ // For a detailed description see freqa register
+ // 0xffff0000 [31:16] : PASSWD (0): Set to 0x9696 to apply the settings
+ // 0x00007000 [14:12] : DS7 (0): Stage 7 drive strength
+ // 0x00000700 [10:8] : DS6 (0): Stage 6 drive strength
+ // 0x00000070 [6:4] : DS5 (0): Stage 5 drive strength
+ // 0x00000007 [2:0] : DS4 (0): Stage 4 drive strength
+ io_rw_32 freqb;
+
+ _REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
+ // Ring Oscillator pause control
+ io_rw_32 dormant;
+
+ _REG_(ROSC_DIV_OFFSET) // ROSC_DIV
+ // Controls the output divider
+ // 0x00000fff [11:0] : DIV (0): set to 0xaa0 + div where
+ io_rw_32 div;
+
+ _REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
+ // Controls the phase shifted output
+ // 0x00000ff0 [11:4] : PASSWD (0): set to 0xaa
+ // 0x00000008 [3] : ENABLE (1): enable the phase-shifted output
+ // 0x00000004 [2] : FLIP (0): invert the phase-shifted output
+ // 0x00000003 [1:0] : SHIFT (0): phase shift the phase-shifted output by SHIFT input clocks
+ io_rw_32 phase;
+
+ _REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
+ // Ring Oscillator Status
+ // 0x80000000 [31] : STABLE (0): Oscillator is running and stable
+ // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or...
+ // 0x00010000 [16] : DIV_RUNNING (0): post-divider is running
+ // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable
+ io_rw_32 status;
+
+ _REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
+ // This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or...
+ // 0x00000001 [0] : RANDOMBIT (1)
+ io_ro_32 randombit;
+
+ _REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
+ // A down counter running at the ROSC frequency which counts to zero and stops
+ // 0x000000ff [7:0] : COUNT (0)
+ io_rw_32 count;
+} rosc_hw_t;
+
+#define rosc_hw ((rosc_hw_t *const)ROSC_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/rtc.h b/arkanoid/pico/hardware/structs/rtc.h
new file mode 100644
index 0000000..b82b845
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/rtc.h
@@ -0,0 +1,114 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_RTC_H
+#define _HARDWARE_STRUCTS_RTC_H
+
+#include "../address_mapped.h"
+#include "../regs/rtc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/rtc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
+ // Divider minus 1 for the 1 second counter
+ // 0x0000ffff [15:0] : CLKDIV_M1 (0)
+ io_rw_32 clkdiv_m1;
+
+ _REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
+ // RTC setup register 0
+ // 0x00fff000 [23:12] : YEAR (0): Year
+ // 0x00000f00 [11:8] : MONTH (0): Month (1
+ // 0x0000001f [4:0] : DAY (0): Day of the month (1
+ io_rw_32 setup_0;
+
+ _REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
+ // RTC setup register 1
+ // 0x07000000 [26:24] : DOTW (0): Day of the week: 1-Monday
+ // 0x001f0000 [20:16] : HOUR (0): Hours
+ // 0x00003f00 [13:8] : MIN (0): Minutes
+ // 0x0000003f [5:0] : SEC (0): Seconds
+ io_rw_32 setup_1;
+
+ _REG_(RTC_CTRL_OFFSET) // RTC_CTRL
+ // RTC Control and status
+ // 0x00000100 [8] : FORCE_NOTLEAPYEAR (0): If set, leapyear is forced off
+ // 0x00000010 [4] : LOAD (0): Load RTC
+ // 0x00000002 [1] : RTC_ACTIVE (0): RTC enabled (running)
+ // 0x00000001 [0] : RTC_ENABLE (0): Enable RTC
+ io_rw_32 ctrl;
+
+ _REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
+ // Interrupt setup register 0
+ // 0x20000000 [29] : MATCH_ACTIVE (0)
+ // 0x10000000 [28] : MATCH_ENA (0): Global match enable
+ // 0x04000000 [26] : YEAR_ENA (0): Enable year matching
+ // 0x02000000 [25] : MONTH_ENA (0): Enable month matching
+ // 0x01000000 [24] : DAY_ENA (0): Enable day matching
+ // 0x00fff000 [23:12] : YEAR (0): Year
+ // 0x00000f00 [11:8] : MONTH (0): Month (1
+ // 0x0000001f [4:0] : DAY (0): Day of the month (1
+ io_rw_32 irq_setup_0;
+
+ _REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
+ // Interrupt setup register 1
+ // 0x80000000 [31] : DOTW_ENA (0): Enable day of the week matching
+ // 0x40000000 [30] : HOUR_ENA (0): Enable hour matching
+ // 0x20000000 [29] : MIN_ENA (0): Enable minute matching
+ // 0x10000000 [28] : SEC_ENA (0): Enable second matching
+ // 0x07000000 [26:24] : DOTW (0): Day of the week
+ // 0x001f0000 [20:16] : HOUR (0): Hours
+ // 0x00003f00 [13:8] : MIN (0): Minutes
+ // 0x0000003f [5:0] : SEC (0): Seconds
+ io_rw_32 irq_setup_1;
+
+ _REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
+ // RTC register 1
+ // 0x00fff000 [23:12] : YEAR (0): Year
+ // 0x00000f00 [11:8] : MONTH (0): Month (1
+ // 0x0000001f [4:0] : DAY (0): Day of the month (1
+ io_ro_32 rtc_1;
+
+ _REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
+ // RTC register 0
+ // 0x07000000 [26:24] : DOTW (0): Day of the week
+ // 0x001f0000 [20:16] : HOUR (0): Hours
+ // 0x00003f00 [13:8] : MIN (0): Minutes
+ // 0x0000003f [5:0] : SEC (0): Seconds
+ io_ro_32 rtc_0;
+
+ _REG_(RTC_INTR_OFFSET) // RTC_INTR
+ // Raw Interrupts
+ // 0x00000001 [0] : RTC (0)
+ io_ro_32 intr;
+
+ _REG_(RTC_INTE_OFFSET) // RTC_INTE
+ // Interrupt Enable
+ // 0x00000001 [0] : RTC (0)
+ io_rw_32 inte;
+
+ _REG_(RTC_INTF_OFFSET) // RTC_INTF
+ // Interrupt Force
+ // 0x00000001 [0] : RTC (0)
+ io_rw_32 intf;
+
+ _REG_(RTC_INTS_OFFSET) // RTC_INTS
+ // Interrupt status after masking & forcing
+ // 0x00000001 [0] : RTC (0)
+ io_ro_32 ints;
+} rtc_hw_t;
+
+#define rtc_hw ((rtc_hw_t *const)RTC_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/scb.h b/arkanoid/pico/hardware/structs/scb.h
new file mode 100644
index 0000000..2590b70
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/scb.h
@@ -0,0 +1,69 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SCB_H
+#define _HARDWARE_STRUCTS_SCB_H
+
+#include "../address_mapped.h"
+#include "../regs/m0plus.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
+ // Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor...
+ // 0xff000000 [31:24] : IMPLEMENTER (0x41): Implementor code: 0x41 = ARM
+ // 0x00f00000 [23:20] : VARIANT (0): Major revision number n in the rnpm revision status:
+ // 0x000f0000 [19:16] : ARCHITECTURE (0xc): Constant that defines the architecture of the processor:
+ // 0x0000fff0 [15:4] : PARTNO (0xc60): Number of processor within family: 0xC60 = Cortex-M0+
+ // 0x0000000f [3:0] : REVISION (1): Minor revision number m in the rnpm revision status:
+ io_ro_32 cpuid;
+
+ _REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
+ // Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending...
+ // 0x80000000 [31] : NMIPENDSET (0): Setting this bit will activate an NMI
+ // 0x10000000 [28] : PENDSVSET (0): PendSV set-pending bit
+ // 0x08000000 [27] : PENDSVCLR (0): PendSV clear-pending bit
+ // 0x04000000 [26] : PENDSTSET (0): SysTick exception set-pending bit
+ // 0x02000000 [25] : PENDSTCLR (0): SysTick exception clear-pending bit
+ // 0x00800000 [23] : ISRPREEMPT (0): The system can only access this bit when the core is halted
+ // 0x00400000 [22] : ISRPENDING (0): External interrupt pending flag
+ // 0x001ff000 [20:12] : VECTPENDING (0): Indicates the exception number for the highest priority pending exception: 0 =...
+ // 0x000001ff [8:0] : VECTACTIVE (0): Active exception number field
+ io_rw_32 icsr;
+
+ _REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
+ // The VTOR holds the vector table offset address
+ // 0xffffff00 [31:8] : TBLOFF (0): Bits [31:8] of the indicate the vector table offset address
+ io_rw_32 vtor;
+
+ _REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
+ // Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state...
+ // 0xffff0000 [31:16] : VECTKEY (0): Register key:
+ // 0x00008000 [15] : ENDIANESS (0): Data endianness implemented:
+ // 0x00000004 [2] : SYSRESETREQ (0): Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be...
+ // 0x00000002 [1] : VECTCLRACTIVE (0): Clears all active state information for fixed and configurable exceptions
+ io_rw_32 aircr;
+
+ _REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
+ // System Control Register
+ // 0x00000010 [4] : SEVONPEND (0): Send Event on Pending bit:
+ // 0x00000004 [2] : SLEEPDEEP (0): Controls whether the processor uses sleep or deep sleep as its low power mode:
+ // 0x00000002 [1] : SLEEPONEXIT (0): Indicates sleep-on-exit when returning from Handler mode to Thread mode:
+ io_rw_32 scr;
+} armv6m_scb_t;
+
+#define scb_hw ((armv6m_scb_t *const)(PPB_BASE + M0PLUS_CPUID_OFFSET))
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/sio.h b/arkanoid/pico/hardware/structs/sio.h
new file mode 100644
index 0000000..0d9e7c8
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/sio.h
@@ -0,0 +1,176 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SIO_H
+#define _HARDWARE_STRUCTS_SIO_H
+
+#include "../address_mapped.h"
+#include "../regs/sio.h"
+#include "interp.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/sio.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(SIO_CPUID_OFFSET) // SIO_CPUID
+ // Processor core identifier
+ io_ro_32 cpuid;
+
+ _REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
+ // Input value for GPIO pins
+ // 0x3fffffff [29:0] : GPIO_IN (0): Input value for GPIO0
+ io_ro_32 gpio_in;
+
+ _REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
+ // Input value for QSPI pins
+ // 0x0000003f [5:0] : GPIO_HI_IN (0): Input value on QSPI IO in order 0
+ io_ro_32 gpio_hi_in;
+
+ uint32_t _pad0;
+
+ _REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
+ // GPIO output value
+ // 0x3fffffff [29:0] : GPIO_OUT (0): Set output level (1/0 -> high/low) for GPIO0
+ io_rw_32 gpio_out;
+
+ _REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
+ // GPIO output value set
+ // 0x3fffffff [29:0] : GPIO_OUT_SET (0): Perform an atomic bit-set on GPIO_OUT, i
+ io_wo_32 gpio_set;
+
+ _REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
+ // GPIO output value clear
+ // 0x3fffffff [29:0] : GPIO_OUT_CLR (0): Perform an atomic bit-clear on GPIO_OUT, i
+ io_wo_32 gpio_clr;
+
+ _REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
+ // GPIO output value XOR
+ // 0x3fffffff [29:0] : GPIO_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_OUT, i
+ io_wo_32 gpio_togl;
+
+ _REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
+ // GPIO output enable
+ // 0x3fffffff [29:0] : GPIO_OE (0): Set output enable (1/0 -> output/input) for GPIO0
+ io_rw_32 gpio_oe;
+
+ _REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
+ // GPIO output enable set
+ // 0x3fffffff [29:0] : GPIO_OE_SET (0): Perform an atomic bit-set on GPIO_OE, i
+ io_wo_32 gpio_oe_set;
+
+ _REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
+ // GPIO output enable clear
+ // 0x3fffffff [29:0] : GPIO_OE_CLR (0): Perform an atomic bit-clear on GPIO_OE, i
+ io_wo_32 gpio_oe_clr;
+
+ _REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
+ // GPIO output enable XOR
+ // 0x3fffffff [29:0] : GPIO_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_OE, i
+ io_wo_32 gpio_oe_togl;
+
+ _REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
+ // QSPI output value
+ // 0x0000003f [5:0] : GPIO_HI_OUT (0): Set output level (1/0 -> high/low) for QSPI IO0
+ io_rw_32 gpio_hi_out;
+
+ _REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
+ // QSPI output value set
+ // 0x0000003f [5:0] : GPIO_HI_OUT_SET (0): Perform an atomic bit-set on GPIO_HI_OUT, i
+ io_wo_32 gpio_hi_set;
+
+ _REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
+ // QSPI output value clear
+ // 0x0000003f [5:0] : GPIO_HI_OUT_CLR (0): Perform an atomic bit-clear on GPIO_HI_OUT, i
+ io_wo_32 gpio_hi_clr;
+
+ _REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
+ // QSPI output value XOR
+ // 0x0000003f [5:0] : GPIO_HI_OUT_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OUT, i
+ io_wo_32 gpio_hi_togl;
+
+ _REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
+ // QSPI output enable
+ // 0x0000003f [5:0] : GPIO_HI_OE (0): Set output enable (1/0 -> output/input) for QSPI IO0
+ io_rw_32 gpio_hi_oe;
+
+ _REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
+ // QSPI output enable set
+ // 0x0000003f [5:0] : GPIO_HI_OE_SET (0): Perform an atomic bit-set on GPIO_HI_OE, i
+ io_wo_32 gpio_hi_oe_set;
+
+ _REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
+ // QSPI output enable clear
+ // 0x0000003f [5:0] : GPIO_HI_OE_CLR (0): Perform an atomic bit-clear on GPIO_HI_OE, i
+ io_wo_32 gpio_hi_oe_clr;
+
+ _REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
+ // QSPI output enable XOR
+ // 0x0000003f [5:0] : GPIO_HI_OE_XOR (0): Perform an atomic bitwise XOR on GPIO_HI_OE, i
+ io_wo_32 gpio_hi_oe_togl;
+
+ _REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
+ // Status register for inter-core FIFOs (mailboxes)
+ // 0x00000008 [3] : ROE (0): Sticky flag indicating the RX FIFO was read when empty
+ // 0x00000004 [2] : WOF (0): Sticky flag indicating the TX FIFO was written when full
+ // 0x00000002 [1] : RDY (1): Value is 1 if this core's TX FIFO is not full (i
+ // 0x00000001 [0] : VLD (0): Value is 1 if this core's RX FIFO is not empty (i
+ io_rw_32 fifo_st;
+
+ _REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
+ // Write access to this core's TX FIFO
+ io_wo_32 fifo_wr;
+
+ _REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
+ // Read access to this core's RX FIFO
+ io_ro_32 fifo_rd;
+
+ _REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
+ // Spinlock state
+ io_ro_32 spinlock_st;
+
+ _REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
+ // Divider unsigned dividend
+ io_rw_32 div_udividend;
+
+ _REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
+ // Divider unsigned divisor
+ io_rw_32 div_udivisor;
+
+ _REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
+ // Divider signed dividend
+ io_rw_32 div_sdividend;
+
+ _REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
+ // Divider signed divisor
+ io_rw_32 div_sdivisor;
+
+ _REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
+ // Divider result quotient
+ io_rw_32 div_quotient;
+
+ _REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
+ // Divider result remainder
+ io_rw_32 div_remainder;
+
+ _REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
+ // Control and status register for divider
+ // 0x00000002 [1] : DIRTY (0): Changes to 1 when any register is written, and back to 0 when QUOTIENT is read
+ // 0x00000001 [0] : READY (1): Reads as 0 when a calculation is in progress, 1 otherwise
+ io_ro_32 div_csr;
+ uint32_t _pad1;
+ interp_hw_t interp[2];
+} sio_hw_t;
+
+#define sio_hw ((sio_hw_t *const)SIO_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/spi.h b/arkanoid/pico/hardware/structs/spi.h
new file mode 100644
index 0000000..c67813d
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/spi.h
@@ -0,0 +1,100 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SPI_H
+#define _HARDWARE_STRUCTS_SPI_H
+
+#include "../address_mapped.h"
+#include "../regs/spi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/spi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
+ // Control register 0, SSPCR0 on page 3-4
+ // 0x0000ff00 [15:8] : SCR (0): Serial clock rate
+ // 0x00000080 [7] : SPH (0): SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ // 0x00000040 [6] : SPO (0): SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+ // 0x00000030 [5:4] : FRF (0): Frame format: 00 Motorola SPI frame format
+ // 0x0000000f [3:0] : DSS (0): Data Size Select: 0000 Reserved, undefined operation
+ io_rw_32 cr0;
+
+ _REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
+ // Control register 1, SSPCR1 on page 3-5
+ // 0x00000008 [3] : SOD (0): Slave-mode output disable
+ // 0x00000004 [2] : MS (0): Master or slave mode select
+ // 0x00000002 [1] : SSE (0): Synchronous serial port enable: 0 SSP operation disabled
+ // 0x00000001 [0] : LBM (0): Loop back mode: 0 Normal serial port operation enabled
+ io_rw_32 cr1;
+
+ _REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
+ // Data register, SSPDR on page 3-6
+ // 0x0000ffff [15:0] : DATA (0): Transmit/Receive FIFO: Read Receive FIFO
+ io_rw_32 dr;
+
+ _REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
+ // Status register, SSPSR on page 3-7
+ // 0x00000010 [4] : BSY (0): PrimeCell SSP busy flag, RO: 0 SSP is idle
+ // 0x00000008 [3] : RFF (0): Receive FIFO full, RO: 0 Receive FIFO is not full
+ // 0x00000004 [2] : RNE (0): Receive FIFO not empty, RO: 0 Receive FIFO is empty
+ // 0x00000002 [1] : TNF (1): Transmit FIFO not full, RO: 0 Transmit FIFO is full
+ // 0x00000001 [0] : TFE (1): Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
+ io_ro_32 sr;
+
+ _REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
+ // Clock prescale register, SSPCPSR on page 3-8
+ // 0x000000ff [7:0] : CPSDVSR (0): Clock prescale divisor
+ io_rw_32 cpsr;
+
+ _REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
+ // Interrupt mask set or clear register, SSPIMSC on page 3-9
+ // 0x00000008 [3] : TXIM (0): Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked
+ // 0x00000004 [2] : RXIM (0): Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked
+ // 0x00000002 [1] : RTIM (0): Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout...
+ // 0x00000001 [0] : RORIM (0): Receive overrun interrupt mask: 0 Receive FIFO written to while full condition...
+ io_rw_32 imsc;
+
+ _REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
+ // Raw interrupt status register, SSPRIS on page 3-10
+ // 0x00000008 [3] : TXRIS (1): Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+ // 0x00000004 [2] : RXRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+ // 0x00000002 [1] : RTRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+ // 0x00000001 [0] : RORRIS (0): Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+ io_ro_32 ris;
+
+ _REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
+ // Masked interrupt status register, SSPMIS on page 3-11
+ // 0x00000008 [3] : TXMIS (0): Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+ // 0x00000004 [2] : RXMIS (0): Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+ // 0x00000002 [1] : RTMIS (0): Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+ // 0x00000001 [0] : RORMIS (0): Gives the receive over run masked interrupt status, after masking, of the...
+ io_ro_32 mis;
+
+ _REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
+ // Interrupt clear register, SSPICR on page 3-11
+ // 0x00000002 [1] : RTIC (0): Clears the SSPRTINTR interrupt
+ // 0x00000001 [0] : RORIC (0): Clears the SSPRORINTR interrupt
+ io_rw_32 icr;
+
+ _REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
+ // DMA control register, SSPDMACR on page 3-12
+ // 0x00000002 [1] : TXDMAE (0): Transmit DMA Enable
+ // 0x00000001 [0] : RXDMAE (0): Receive DMA Enable
+ io_rw_32 dmacr;
+} spi_hw_t;
+
+#define spi0_hw ((spi_hw_t *const)SPI0_BASE)
+#define spi1_hw ((spi_hw_t *const)SPI1_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/ssi.h b/arkanoid/pico/hardware/structs/ssi.h
new file mode 100644
index 0000000..65bd27b
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/ssi.h
@@ -0,0 +1,210 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SSI_H
+#define _HARDWARE_STRUCTS_SSI_H
+
+#include "../address_mapped.h"
+#include "../regs/ssi.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/ssi.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0
+ // Control register 0
+ // 0x01000000 [24] : SSTE (0): Slave select toggle enable
+ // 0x00600000 [22:21] : SPI_FRF (0): SPI frame format
+ // 0x001f0000 [20:16] : DFS_32 (0): Data frame size in 32b transfer mode
+ // 0x0000f000 [15:12] : CFS (0): Control frame size
+ // 0x00000800 [11] : SRL (0): Shift register loop (test mode)
+ // 0x00000400 [10] : SLV_OE (0): Slave output enable
+ // 0x00000300 [9:8] : TMOD (0): Transfer mode
+ // 0x00000080 [7] : SCPOL (0): Serial clock polarity
+ // 0x00000040 [6] : SCPH (0): Serial clock phase
+ // 0x00000030 [5:4] : FRF (0): Frame format
+ // 0x0000000f [3:0] : DFS (0): Data frame size
+ io_rw_32 ctrlr0;
+
+ _REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1
+ // Master Control register 1
+ // 0x0000ffff [15:0] : NDF (0): Number of data frames
+ io_rw_32 ctrlr1;
+
+ _REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR
+ // SSI Enable
+ // 0x00000001 [0] : SSI_EN (0): SSI enable
+ io_rw_32 ssienr;
+
+ _REG_(SSI_MWCR_OFFSET) // SSI_MWCR
+ // Microwire Control
+ // 0x00000004 [2] : MHS (0): Microwire handshaking
+ // 0x00000002 [1] : MDD (0): Microwire control
+ // 0x00000001 [0] : MWMOD (0): Microwire transfer mode
+ io_rw_32 mwcr;
+
+ _REG_(SSI_SER_OFFSET) // SSI_SER
+ // Slave enable
+ // 0x00000001 [0] : SER (0): For each bit:
+ io_rw_32 ser;
+
+ _REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR
+ // Baud rate
+ // 0x0000ffff [15:0] : SCKDV (0): SSI clock divider
+ io_rw_32 baudr;
+
+ _REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR
+ // TX FIFO threshold level
+ // 0x000000ff [7:0] : TFT (0): Transmit FIFO threshold
+ io_rw_32 txftlr;
+
+ _REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR
+ // RX FIFO threshold level
+ // 0x000000ff [7:0] : RFT (0): Receive FIFO threshold
+ io_rw_32 rxftlr;
+
+ _REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR
+ // TX FIFO level
+ // 0x000000ff [7:0] : TFTFL (0): Transmit FIFO level
+ io_ro_32 txflr;
+
+ _REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR
+ // RX FIFO level
+ // 0x000000ff [7:0] : RXTFL (0): Receive FIFO level
+ io_ro_32 rxflr;
+
+ _REG_(SSI_SR_OFFSET) // SSI_SR
+ // Status register
+ // 0x00000040 [6] : DCOL (0): Data collision error
+ // 0x00000020 [5] : TXE (0): Transmission error
+ // 0x00000010 [4] : RFF (0): Receive FIFO full
+ // 0x00000008 [3] : RFNE (0): Receive FIFO not empty
+ // 0x00000004 [2] : TFE (0): Transmit FIFO empty
+ // 0x00000002 [1] : TFNF (0): Transmit FIFO not full
+ // 0x00000001 [0] : BUSY (0): SSI busy flag
+ io_ro_32 sr;
+
+ _REG_(SSI_IMR_OFFSET) // SSI_IMR
+ // Interrupt mask
+ // 0x00000020 [5] : MSTIM (0): Multi-master contention interrupt mask
+ // 0x00000010 [4] : RXFIM (0): Receive FIFO full interrupt mask
+ // 0x00000008 [3] : RXOIM (0): Receive FIFO overflow interrupt mask
+ // 0x00000004 [2] : RXUIM (0): Receive FIFO underflow interrupt mask
+ // 0x00000002 [1] : TXOIM (0): Transmit FIFO overflow interrupt mask
+ // 0x00000001 [0] : TXEIM (0): Transmit FIFO empty interrupt mask
+ io_rw_32 imr;
+
+ _REG_(SSI_ISR_OFFSET) // SSI_ISR
+ // Interrupt status
+ // 0x00000020 [5] : MSTIS (0): Multi-master contention interrupt status
+ // 0x00000010 [4] : RXFIS (0): Receive FIFO full interrupt status
+ // 0x00000008 [3] : RXOIS (0): Receive FIFO overflow interrupt status
+ // 0x00000004 [2] : RXUIS (0): Receive FIFO underflow interrupt status
+ // 0x00000002 [1] : TXOIS (0): Transmit FIFO overflow interrupt status
+ // 0x00000001 [0] : TXEIS (0): Transmit FIFO empty interrupt status
+ io_ro_32 isr;
+
+ _REG_(SSI_RISR_OFFSET) // SSI_RISR
+ // Raw interrupt status
+ // 0x00000020 [5] : MSTIR (0): Multi-master contention raw interrupt status
+ // 0x00000010 [4] : RXFIR (0): Receive FIFO full raw interrupt status
+ // 0x00000008 [3] : RXOIR (0): Receive FIFO overflow raw interrupt status
+ // 0x00000004 [2] : RXUIR (0): Receive FIFO underflow raw interrupt status
+ // 0x00000002 [1] : TXOIR (0): Transmit FIFO overflow raw interrupt status
+ // 0x00000001 [0] : TXEIR (0): Transmit FIFO empty raw interrupt status
+ io_ro_32 risr;
+
+ _REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR
+ // TX FIFO overflow interrupt clear
+ // 0x00000001 [0] : TXOICR (0): Clear-on-read transmit FIFO overflow interrupt
+ io_ro_32 txoicr;
+
+ _REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR
+ // RX FIFO overflow interrupt clear
+ // 0x00000001 [0] : RXOICR (0): Clear-on-read receive FIFO overflow interrupt
+ io_ro_32 rxoicr;
+
+ _REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR
+ // RX FIFO underflow interrupt clear
+ // 0x00000001 [0] : RXUICR (0): Clear-on-read receive FIFO underflow interrupt
+ io_ro_32 rxuicr;
+
+ _REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR
+ // Multi-master interrupt clear
+ // 0x00000001 [0] : MSTICR (0): Clear-on-read multi-master contention interrupt
+ io_ro_32 msticr;
+
+ _REG_(SSI_ICR_OFFSET) // SSI_ICR
+ // Interrupt clear
+ // 0x00000001 [0] : ICR (0): Clear-on-read all active interrupts
+ io_ro_32 icr;
+
+ _REG_(SSI_DMACR_OFFSET) // SSI_DMACR
+ // DMA control
+ // 0x00000002 [1] : TDMAE (0): Transmit DMA enable
+ // 0x00000001 [0] : RDMAE (0): Receive DMA enable
+ io_rw_32 dmacr;
+
+ _REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR
+ // DMA TX data level
+ // 0x000000ff [7:0] : DMATDL (0): Transmit data watermark level
+ io_rw_32 dmatdlr;
+
+ _REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR
+ // DMA RX data level
+ // 0x000000ff [7:0] : DMARDL (0): Receive data watermark level (DMARDLR+1)
+ io_rw_32 dmardlr;
+
+ _REG_(SSI_IDR_OFFSET) // SSI_IDR
+ // Identification register
+ // 0xffffffff [31:0] : IDCODE (0x51535049): Peripheral dentification code
+ io_ro_32 idr;
+
+ _REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID
+ // Version ID
+ // 0xffffffff [31:0] : SSI_COMP_VERSION (0x3430312a): SNPS component version (format X
+ io_ro_32 ssi_version_id;
+
+ _REG_(SSI_DR0_OFFSET) // SSI_DR0
+ // Data Register 0 (of 36)
+ // 0xffffffff [31:0] : DR (0): First data register of 36
+ io_rw_32 dr0;
+
+ uint32_t _pad0[35];
+
+ _REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY
+ // RX sample delay
+ // 0x000000ff [7:0] : RSD (0): RXD sample delay (in SCLK cycles)
+ io_rw_32 rx_sample_dly;
+
+ _REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
+ // SPI control
+ // 0xff000000 [31:24] : XIP_CMD (0x3): SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
+ // 0x00040000 [18] : SPI_RXDS_EN (0): Read data strobe enable
+ // 0x00020000 [17] : INST_DDR_EN (0): Instruction DDR transfer enable
+ // 0x00010000 [16] : SPI_DDR_EN (0): SPI DDR transfer enable
+ // 0x0000f800 [15:11] : WAIT_CYCLES (0): Wait cycles between control frame transmit and data reception (in SCLK cycles)
+ // 0x00000300 [9:8] : INST_L (0): Instruction length (0/4/8/16b)
+ // 0x0000003c [5:2] : ADDR_L (0): Address length (0b-60b in 4b increments)
+ // 0x00000003 [1:0] : TRANS_TYPE (0): Address and instruction transfer format
+ io_rw_32 spi_ctrlr0;
+
+ _REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE
+ // TX drive edge
+ // 0x000000ff [7:0] : TDE (0): TXD drive edge
+ io_rw_32 txd_drive_edge;
+} ssi_hw_t;
+
+#define ssi_hw ((ssi_hw_t *const)XIP_SSI_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/syscfg.h b/arkanoid/pico/hardware/structs/syscfg.h
new file mode 100644
index 0000000..66fd464
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/syscfg.h
@@ -0,0 +1,77 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SYSCFG_H
+#define _HARDWARE_STRUCTS_SYSCFG_H
+
+#include "../address_mapped.h"
+#include "../regs/syscfg.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/syscfg.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK
+ // Processor core 0 NMI source mask
+ io_rw_32 proc0_nmi_mask;
+
+ _REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK
+ // Processor core 1 NMI source mask
+ io_rw_32 proc1_nmi_mask;
+
+ _REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
+ // Configuration for processors
+ // 0xf0000000 [31:28] : PROC1_DAP_INSTID (1): Configure proc1 DAP instance ID
+ // 0x0f000000 [27:24] : PROC0_DAP_INSTID (0): Configure proc0 DAP instance ID
+ // 0x00000002 [1] : PROC1_HALTED (0): Indication that proc1 has halted
+ // 0x00000001 [0] : PROC0_HALTED (0): Indication that proc0 has halted
+ io_rw_32 proc_config;
+
+ _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
+ // For each bit, if 1, bypass the input synchronizer between that GPIO
+ // 0x3fffffff [29:0] : PROC_IN_SYNC_BYPASS (0)
+ io_rw_32 proc_in_sync_bypass;
+
+ _REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
+ // For each bit, if 1, bypass the input synchronizer between that GPIO
+ // 0x0000003f [5:0] : PROC_IN_SYNC_BYPASS_HI (0)
+ io_rw_32 proc_in_sync_bypass_hi;
+
+ _REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
+ // Directly control the SWD debug port of either processor
+ // 0x00000080 [7] : PROC1_ATTACH (0): Attach processor 1 debug port to syscfg controls, and disconnect it from...
+ // 0x00000040 [6] : PROC1_SWCLK (1): Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
+ // 0x00000020 [5] : PROC1_SWDI (1): Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
+ // 0x00000010 [4] : PROC1_SWDO (0): Observe the value of processor 1 SWDIO output
+ // 0x00000008 [3] : PROC0_ATTACH (0): Attach processor 0 debug port to syscfg controls, and disconnect it from...
+ // 0x00000004 [2] : PROC0_SWCLK (1): Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
+ // 0x00000002 [1] : PROC0_SWDI (1): Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
+ // 0x00000001 [0] : PROC0_SWDO (0): Observe the value of processor 0 SWDIO output
+ io_rw_32 dbgforce;
+
+ _REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
+ // Control power downs to memories
+ // 0x00000080 [7] : ROM (0)
+ // 0x00000040 [6] : USB (0)
+ // 0x00000020 [5] : SRAM5 (0)
+ // 0x00000010 [4] : SRAM4 (0)
+ // 0x00000008 [3] : SRAM3 (0)
+ // 0x00000004 [2] : SRAM2 (0)
+ // 0x00000002 [1] : SRAM1 (0)
+ // 0x00000001 [0] : SRAM0 (0)
+ io_rw_32 mempowerdown;
+} syscfg_hw_t;
+
+#define syscfg_hw ((syscfg_hw_t *const)SYSCFG_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/systick.h b/arkanoid/pico/hardware/structs/systick.h
new file mode 100644
index 0000000..560617d
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/systick.h
@@ -0,0 +1,52 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_SYSTICK_H
+#define _HARDWARE_STRUCTS_SYSTICK_H
+
+#include "../address_mapped.h"
+#include "../regs/m0plus.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/m0plus.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
+ // Use the SysTick Control and Status Register to enable the SysTick features
+ // 0x00010000 [16] : COUNTFLAG (0): Returns 1 if timer counted to 0 since last time this was read
+ // 0x00000004 [2] : CLKSOURCE (0): SysTick clock source
+ // 0x00000002 [1] : TICKINT (0): Enables SysTick exception request:
+ // 0x00000001 [0] : ENABLE (0): Enable SysTick counter:
+ io_rw_32 csr;
+
+ _REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
+ // Use the SysTick Reload Value Register to specify the start value to load into the current value register when the...
+ // 0x00ffffff [23:0] : RELOAD (0): Value to load into the SysTick Current Value Register when the counter reaches 0
+ io_rw_32 rvr;
+
+ _REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
+ // Use the SysTick Current Value Register to find the current value in the register
+ // 0x00ffffff [23:0] : CURRENT (0): Reads return the current value of the SysTick counter
+ io_rw_32 cvr;
+
+ _REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
+ // Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply
+ // 0x80000000 [31] : NOREF (0): If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the...
+ // 0x40000000 [30] : SKEW (0): If reads as 1, the calibration value for 10ms is inexact (due to clock frequency)
+ // 0x00ffffff [23:0] : TENMS (0): An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock...
+ io_ro_32 calib;
+} systick_hw_t;
+
+#define systick_hw ((systick_hw_t *const)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/timer.h b/arkanoid/pico/hardware/structs/timer.h
new file mode 100644
index 0000000..7d4ea9c
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/timer.h
@@ -0,0 +1,107 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_TIMER_H
+#define _HARDWARE_STRUCTS_TIMER_H
+
+#include "../address_mapped.h"
+#include "../regs/timer.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/timer.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW
+ // Write to bits 63:32 of time
+ io_wo_32 timehw;
+
+ _REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW
+ // Write to bits 31:0 of time
+ io_wo_32 timelw;
+
+ _REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR
+ // Read from bits 63:32 of time
+ io_ro_32 timehr;
+
+ _REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR
+ // Read from bits 31:0 of time
+ io_ro_32 timelr;
+
+ _REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0
+ // (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes)
+ //
+ // Arm alarm 0, and configure the time it will fire
+ io_rw_32 alarm[NUM_TIMERS]; // 4
+
+ _REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED
+ // Indicates the armed/disarmed status of each alarm
+ // 0x0000000f [3:0] : ARMED (0)
+ io_rw_32 armed;
+
+ _REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH
+ // Raw read from bits 63:32 of time (no side effects)
+ io_ro_32 timerawh;
+
+ _REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL
+ // Raw read from bits 31:0 of time (no side effects)
+ io_ro_32 timerawl;
+
+ _REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE
+ // Set bits high to enable pause when the corresponding debug ports are active
+ // 0x00000004 [2] : DBG1 (1): Pause when processor 1 is in debug mode
+ // 0x00000002 [1] : DBG0 (1): Pause when processor 0 is in debug mode
+ io_rw_32 dbgpause;
+
+ _REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE
+ // Set high to pause the timer
+ // 0x00000001 [0] : PAUSE (0)
+ io_rw_32 pause;
+
+ _REG_(TIMER_INTR_OFFSET) // TIMER_INTR
+ // Raw Interrupts
+ // 0x00000008 [3] : ALARM_3 (0)
+ // 0x00000004 [2] : ALARM_2 (0)
+ // 0x00000002 [1] : ALARM_1 (0)
+ // 0x00000001 [0] : ALARM_0 (0)
+ io_rw_32 intr;
+
+ _REG_(TIMER_INTE_OFFSET) // TIMER_INTE
+ // Interrupt Enable
+ // 0x00000008 [3] : ALARM_3 (0)
+ // 0x00000004 [2] : ALARM_2 (0)
+ // 0x00000002 [1] : ALARM_1 (0)
+ // 0x00000001 [0] : ALARM_0 (0)
+ io_rw_32 inte;
+
+ _REG_(TIMER_INTF_OFFSET) // TIMER_INTF
+ // Interrupt Force
+ // 0x00000008 [3] : ALARM_3 (0)
+ // 0x00000004 [2] : ALARM_2 (0)
+ // 0x00000002 [1] : ALARM_1 (0)
+ // 0x00000001 [0] : ALARM_0 (0)
+ io_rw_32 intf;
+
+ _REG_(TIMER_INTS_OFFSET) // TIMER_INTS
+ // Interrupt status after masking & forcing
+ // 0x00000008 [3] : ALARM_3 (0)
+ // 0x00000004 [2] : ALARM_2 (0)
+ // 0x00000002 [1] : ALARM_1 (0)
+ // 0x00000001 [0] : ALARM_0 (0)
+ io_ro_32 ints;
+} timer_hw_t;
+
+#define timer_hw ((timer_hw_t *const)TIMER_BASE)
+
+static_assert( NUM_TIMERS == 4, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/uart.h b/arkanoid/pico/hardware/structs/uart.h
new file mode 100644
index 0000000..58918f8
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/uart.h
@@ -0,0 +1,177 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_UART_H
+#define _HARDWARE_STRUCTS_UART_H
+
+#include "../address_mapped.h"
+#include "../regs/uart.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/uart.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(UART_UARTDR_OFFSET) // UART_UARTDR
+ // Data Register, UARTDR
+ // 0x00000800 [11] : OE (0): Overrun error
+ // 0x00000400 [10] : BE (0): Break error
+ // 0x00000200 [9] : PE (0): Parity error
+ // 0x00000100 [8] : FE (0): Framing error
+ // 0x000000ff [7:0] : DATA (0): Receive (read) data character
+ io_rw_32 dr;
+
+ _REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
+ // Receive Status Register/Error Clear Register, UARTRSR/UARTECR
+ // 0x00000008 [3] : OE (0): Overrun error
+ // 0x00000004 [2] : BE (0): Break error
+ // 0x00000002 [1] : PE (0): Parity error
+ // 0x00000001 [0] : FE (0): Framing error
+ io_rw_32 rsr;
+
+ uint32_t _pad0[4];
+
+ _REG_(UART_UARTFR_OFFSET) // UART_UARTFR
+ // Flag Register, UARTFR
+ // 0x00000100 [8] : RI (0): Ring indicator
+ // 0x00000080 [7] : TXFE (1): Transmit FIFO empty
+ // 0x00000040 [6] : RXFF (0): Receive FIFO full
+ // 0x00000020 [5] : TXFF (0): Transmit FIFO full
+ // 0x00000010 [4] : RXFE (1): Receive FIFO empty
+ // 0x00000008 [3] : BUSY (0): UART busy
+ // 0x00000004 [2] : DCD (0): Data carrier detect
+ // 0x00000002 [1] : DSR (0): Data set ready
+ // 0x00000001 [0] : CTS (0): Clear to send
+ io_ro_32 fr;
+
+ uint32_t _pad1;
+
+ _REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
+ // IrDA Low-Power Counter Register, UARTILPR
+ // 0x000000ff [7:0] : ILPDVSR (0): 8-bit low-power divisor value
+ io_rw_32 ilpr;
+
+ _REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
+ // Integer Baud Rate Register, UARTIBRD
+ // 0x0000ffff [15:0] : BAUD_DIVINT (0): The integer baud rate divisor
+ io_rw_32 ibrd;
+
+ _REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
+ // Fractional Baud Rate Register, UARTFBRD
+ // 0x0000003f [5:0] : BAUD_DIVFRAC (0): The fractional baud rate divisor
+ io_rw_32 fbrd;
+
+ _REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
+ // Line Control Register, UARTLCR_H
+ // 0x00000080 [7] : SPS (0): Stick parity select
+ // 0x00000060 [6:5] : WLEN (0): Word length
+ // 0x00000010 [4] : FEN (0): Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become...
+ // 0x00000008 [3] : STP2 (0): Two stop bits select
+ // 0x00000004 [2] : EPS (0): Even parity select
+ // 0x00000002 [1] : PEN (0): Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 =...
+ // 0x00000001 [0] : BRK (0): Send break
+ io_rw_32 lcr_h;
+
+ _REG_(UART_UARTCR_OFFSET) // UART_UARTCR
+ // Control Register, UARTCR
+ // 0x00008000 [15] : CTSEN (0): CTS hardware flow control enable
+ // 0x00004000 [14] : RTSEN (0): RTS hardware flow control enable
+ // 0x00002000 [13] : OUT2 (0): This bit is the complement of the UART Out2 (nUARTOut2) modem status output
+ // 0x00001000 [12] : OUT1 (0): This bit is the complement of the UART Out1 (nUARTOut1) modem status output
+ // 0x00000800 [11] : RTS (0): Request to send
+ // 0x00000400 [10] : DTR (0): Data transmit ready
+ // 0x00000200 [9] : RXE (1): Receive enable
+ // 0x00000100 [8] : TXE (1): Transmit enable
+ // 0x00000080 [7] : LBE (0): Loopback enable
+ // 0x00000004 [2] : SIRLP (0): SIR low-power IrDA mode
+ // 0x00000002 [1] : SIREN (0): SIR enable: 0 = IrDA SIR ENDEC is disabled
+ // 0x00000001 [0] : UARTEN (0): UART enable: 0 = UART is disabled
+ io_rw_32 cr;
+
+ _REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
+ // Interrupt FIFO Level Select Register, UARTIFLS
+ // 0x00000038 [5:3] : RXIFLSEL (0x2): Receive interrupt FIFO level select
+ // 0x00000007 [2:0] : TXIFLSEL (0x2): Transmit interrupt FIFO level select
+ io_rw_32 ifls;
+
+ _REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
+ // Interrupt Mask Set/Clear Register, UARTIMSC
+ // 0x00000400 [10] : OEIM (0): Overrun error interrupt mask
+ // 0x00000200 [9] : BEIM (0): Break error interrupt mask
+ // 0x00000100 [8] : PEIM (0): Parity error interrupt mask
+ // 0x00000080 [7] : FEIM (0): Framing error interrupt mask
+ // 0x00000040 [6] : RTIM (0): Receive timeout interrupt mask
+ // 0x00000020 [5] : TXIM (0): Transmit interrupt mask
+ // 0x00000010 [4] : RXIM (0): Receive interrupt mask
+ // 0x00000008 [3] : DSRMIM (0): nUARTDSR modem interrupt mask
+ // 0x00000004 [2] : DCDMIM (0): nUARTDCD modem interrupt mask
+ // 0x00000002 [1] : CTSMIM (0): nUARTCTS modem interrupt mask
+ // 0x00000001 [0] : RIMIM (0): nUARTRI modem interrupt mask
+ io_rw_32 imsc;
+
+ _REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
+ // Raw Interrupt Status Register, UARTRIS
+ // 0x00000400 [10] : OERIS (0): Overrun error interrupt status
+ // 0x00000200 [9] : BERIS (0): Break error interrupt status
+ // 0x00000100 [8] : PERIS (0): Parity error interrupt status
+ // 0x00000080 [7] : FERIS (0): Framing error interrupt status
+ // 0x00000040 [6] : RTRIS (0): Receive timeout interrupt status
+ // 0x00000020 [5] : TXRIS (0): Transmit interrupt status
+ // 0x00000010 [4] : RXRIS (0): Receive interrupt status
+ // 0x00000008 [3] : DSRRMIS (0): nUARTDSR modem interrupt status
+ // 0x00000004 [2] : DCDRMIS (0): nUARTDCD modem interrupt status
+ // 0x00000002 [1] : CTSRMIS (0): nUARTCTS modem interrupt status
+ // 0x00000001 [0] : RIRMIS (0): nUARTRI modem interrupt status
+ io_ro_32 ris;
+
+ _REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
+ // Masked Interrupt Status Register, UARTMIS
+ // 0x00000400 [10] : OEMIS (0): Overrun error masked interrupt status
+ // 0x00000200 [9] : BEMIS (0): Break error masked interrupt status
+ // 0x00000100 [8] : PEMIS (0): Parity error masked interrupt status
+ // 0x00000080 [7] : FEMIS (0): Framing error masked interrupt status
+ // 0x00000040 [6] : RTMIS (0): Receive timeout masked interrupt status
+ // 0x00000020 [5] : TXMIS (0): Transmit masked interrupt status
+ // 0x00000010 [4] : RXMIS (0): Receive masked interrupt status
+ // 0x00000008 [3] : DSRMMIS (0): nUARTDSR modem masked interrupt status
+ // 0x00000004 [2] : DCDMMIS (0): nUARTDCD modem masked interrupt status
+ // 0x00000002 [1] : CTSMMIS (0): nUARTCTS modem masked interrupt status
+ // 0x00000001 [0] : RIMMIS (0): nUARTRI modem masked interrupt status
+ io_ro_32 mis;
+
+ _REG_(UART_UARTICR_OFFSET) // UART_UARTICR
+ // Interrupt Clear Register, UARTICR
+ // 0x00000400 [10] : OEIC (0): Overrun error interrupt clear
+ // 0x00000200 [9] : BEIC (0): Break error interrupt clear
+ // 0x00000100 [8] : PEIC (0): Parity error interrupt clear
+ // 0x00000080 [7] : FEIC (0): Framing error interrupt clear
+ // 0x00000040 [6] : RTIC (0): Receive timeout interrupt clear
+ // 0x00000020 [5] : TXIC (0): Transmit interrupt clear
+ // 0x00000010 [4] : RXIC (0): Receive interrupt clear
+ // 0x00000008 [3] : DSRMIC (0): nUARTDSR modem interrupt clear
+ // 0x00000004 [2] : DCDMIC (0): nUARTDCD modem interrupt clear
+ // 0x00000002 [1] : CTSMIC (0): nUARTCTS modem interrupt clear
+ // 0x00000001 [0] : RIMIC (0): nUARTRI modem interrupt clear
+ io_rw_32 icr;
+
+ _REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
+ // DMA Control Register, UARTDMACR
+ // 0x00000004 [2] : DMAONERR (0): DMA on error
+ // 0x00000002 [1] : TXDMAE (0): Transmit DMA enable
+ // 0x00000001 [0] : RXDMAE (0): Receive DMA enable
+ io_rw_32 dmacr;
+} uart_hw_t;
+
+#define uart0_hw ((uart_hw_t *const)UART0_BASE)
+#define uart1_hw ((uart_hw_t *const)UART1_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/usb.h b/arkanoid/pico/hardware/structs/usb.h
new file mode 100644
index 0000000..cb2f933
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/usb.h
@@ -0,0 +1,578 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_USB_H
+#define _HARDWARE_STRUCTS_USB_H
+
+#include "../address_mapped.h"
+#include "../regs/usb.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/usb.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+// 0-15
+#define USB_NUM_ENDPOINTS 16
+
+// allow user to restrict number of endpoints available to save RAN
+#ifndef USB_MAX_ENDPOINTS
+#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS
+#endif
+
+// 1-15
+#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1)
+
+// Endpoint buffer control bits
+#define USB_BUF_CTRL_FULL 0x00008000u
+#define USB_BUF_CTRL_LAST 0x00004000u
+#define USB_BUF_CTRL_DATA0_PID 0x00000000u
+#define USB_BUF_CTRL_DATA1_PID 0x00002000u
+#define USB_BUF_CTRL_SEL 0x00001000u
+#define USB_BUF_CTRL_STALL 0x00000800u
+#define USB_BUF_CTRL_AVAIL 0x00000400u
+#define USB_BUF_CTRL_LEN_MASK 0x000003FFu
+#define USB_BUF_CTRL_LEN_LSB 0
+
+// ep_inout_ctrl bits
+#define EP_CTRL_ENABLE_BITS (1u << 31u)
+#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30)
+#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29)
+#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
+#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
+#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
+#define EP_CTRL_BUFFER_TYPE_LSB 26u
+#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
+
+#define USB_DPRAM_SIZE 4096u
+
+// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
+// Allow user to claim some of the USB RAM for themselves
+#ifndef USB_DPRAM_MAX
+#define USB_DPRAM_MAX USB_DPRAM_SIZE
+#endif
+
+// Define maximum packet sizes
+#define USB_MAX_ISO_PACKET_SIZE 1023
+#define USB_MAX_PACKET_SIZE 64
+
+typedef struct {
+ // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
+ volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
+
+ // Starts at ep1
+ struct usb_device_dpram_ep_ctrl {
+ io_rw_32 in;
+ io_rw_32 out;
+ } ep_ctrl[USB_NUM_ENDPOINTS - 1];
+
+ // Starts at ep0
+ struct usb_device_dpram_ep_buf_ctrl {
+ io_rw_32 in;
+ io_rw_32 out;
+ } ep_buf_ctrl[USB_NUM_ENDPOINTS];
+
+ // EP0 buffers are fixed. Assumes single buffered mode for EP0
+ uint8_t ep0_buf_a[0x40];
+ uint8_t ep0_buf_b[0x40];
+
+ // Rest of DPRAM can be carved up as needed
+ uint8_t epx_data[USB_DPRAM_MAX - 0x180];
+} usb_device_dpram_t;
+
+static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, "");
+static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, "");
+
+typedef struct {
+ // 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
+ volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
+
+ // Interrupt endpoint control 1 -> 15
+ struct usb_host_dpram_ep_ctrl {
+ io_rw_32 ctrl;
+ io_rw_32 spare;
+ } int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
+
+ io_rw_32 epx_buf_ctrl;
+ io_rw_32 _spare0;
+
+ // Interrupt endpoint buffer control
+ struct usb_host_dpram_ep_buf_ctrl {
+ io_rw_32 ctrl;
+ io_rw_32 spare;
+ } int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
+
+ io_rw_32 epx_ctrl;
+
+ uint8_t _spare1[124];
+
+ // Should start at 0x180
+ uint8_t epx_data[USB_DPRAM_MAX - 0x180];
+} usb_host_dpram_t;
+
+static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
+static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
+
+typedef struct {
+ _REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
+ // Device address and endpoint control
+ // 0x000f0000 [19:16] : ENDPOINT (0): Device endpoint to send data to
+ // 0x0000007f [6:0] : ADDRESS (0): In device mode, the address that the device should respond to
+ io_rw_32 dev_addr_ctrl;
+
+ _REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
+ // (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
+ //
+ // Interrupt endpoint 1
+ // 0x04000000 [26] : INTEP_PREAMBLE (0): Interrupt EP requires preamble (is a low speed device on a full speed hub)
+ // 0x02000000 [25] : INTEP_DIR (0): Direction of the interrupt endpoint
+ // 0x000f0000 [19:16] : ENDPOINT (0): Endpoint number of the interrupt endpoint
+ // 0x0000007f [6:0] : ADDRESS (0): Device address
+ io_rw_32 int_ep_addr_ctrl[USB_HOST_INTERRUPT_ENDPOINTS]; // 15
+
+ _REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
+ // Main control register
+ // 0x80000000 [31] : SIM_TIMING (0): Reduced timings for simulation
+ // 0x00000002 [1] : HOST_NDEVICE (0): Device mode = 0, Host mode = 1
+ // 0x00000001 [0] : CONTROLLER_EN (0): Enable controller
+ io_rw_32 main_ctrl;
+
+ _REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
+ // Set the SOF (Start of Frame) frame number in the host controller
+ // 0x000007ff [10:0] : COUNT (0)
+ io_wo_32 sof_rw;
+
+ _REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
+ // Read the last SOF (Start of Frame) frame number seen
+ // 0x000007ff [10:0] : COUNT (0)
+ io_ro_32 sof_rd;
+
+ _REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
+ // SIE control register
+ // 0x80000000 [31] : EP0_INT_STALL (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
+ // 0x40000000 [30] : EP0_DOUBLE_BUF (0): Device: EP0 single buffered = 0, double buffered = 1
+ // 0x20000000 [29] : EP0_INT_1BUF (0): Device: Set bit in BUFF_STATUS for every buffer completed on EP0
+ // 0x10000000 [28] : EP0_INT_2BUF (0): Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
+ // 0x08000000 [27] : EP0_INT_NAK (0): Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
+ // 0x04000000 [26] : DIRECT_EN (0): Direct bus drive enable
+ // 0x02000000 [25] : DIRECT_DP (0): Direct control of DP
+ // 0x01000000 [24] : DIRECT_DM (0): Direct control of DM
+ // 0x00040000 [18] : TRANSCEIVER_PD (0): Power down bus transceiver
+ // 0x00020000 [17] : RPU_OPT (0): Device: Pull-up strength (0=1K2, 1=2k3)
+ // 0x00010000 [16] : PULLUP_EN (0): Device: Enable pull up resistor
+ // 0x00008000 [15] : PULLDOWN_EN (0): Host: Enable pull down resistors
+ // 0x00002000 [13] : RESET_BUS (0): Host: Reset bus
+ // 0x00001000 [12] : RESUME (0): Device: Remote wakeup
+ // 0x00000800 [11] : VBUS_EN (0): Host: Enable VBUS
+ // 0x00000400 [10] : KEEP_ALIVE_EN (0): Host: Enable keep alive packet (for low speed bus)
+ // 0x00000200 [9] : SOF_EN (0): Host: Enable SOF generation (for full speed bus)
+ // 0x00000100 [8] : SOF_SYNC (0): Host: Delay packet(s) until after SOF
+ // 0x00000040 [6] : PREAMBLE_EN (0): Host: Preable enable for LS device on FS hub
+ // 0x00000010 [4] : STOP_TRANS (0): Host: Stop transaction
+ // 0x00000008 [3] : RECEIVE_DATA (0): Host: Receive transaction (IN to host)
+ // 0x00000004 [2] : SEND_DATA (0): Host: Send transaction (OUT from host)
+ // 0x00000002 [1] : SEND_SETUP (0): Host: Send Setup packet
+ // 0x00000001 [0] : START_TRANS (0): Host: Start transaction
+ io_rw_32 sie_ctrl;
+
+ _REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
+ // SIE status register
+ // 0x80000000 [31] : DATA_SEQ_ERROR (0): Data Sequence Error
+ // 0x40000000 [30] : ACK_REC (0): ACK received
+ // 0x20000000 [29] : STALL_REC (0): Host: STALL received
+ // 0x10000000 [28] : NAK_REC (0): Host: NAK received
+ // 0x08000000 [27] : RX_TIMEOUT (0): RX timeout is raised by both the host and device if an ACK is not received in...
+ // 0x04000000 [26] : RX_OVERFLOW (0): RX overflow is raised by the Serial RX engine if the incoming data is too fast
+ // 0x02000000 [25] : BIT_STUFF_ERROR (0): Bit Stuff Error
+ // 0x01000000 [24] : CRC_ERROR (0): CRC Error
+ // 0x00080000 [19] : BUS_RESET (0): Device: bus reset received
+ // 0x00040000 [18] : TRANS_COMPLETE (0): Transaction complete
+ // 0x00020000 [17] : SETUP_REC (0): Device: Setup packet received
+ // 0x00010000 [16] : CONNECTED (0): Device: connected
+ // 0x00000800 [11] : RESUME (0): Host: Device has initiated a remote resume
+ // 0x00000400 [10] : VBUS_OVER_CURR (0): VBUS over current detected
+ // 0x00000300 [9:8] : SPEED (0): Host: device speed
+ // 0x00000010 [4] : SUSPENDED (0): Bus in suspended state
+ // 0x0000000c [3:2] : LINE_STATE (0): USB bus line state
+ // 0x00000001 [0] : VBUS_DETECTED (0): Device: VBUS Detected
+ io_rw_32 sie_status;
+
+ _REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
+ // interrupt endpoint control register
+ // 0x0000fffe [15:1] : INT_EP_ACTIVE (0): Host: Enable interrupt endpoint 1 -> 15
+ io_rw_32 int_ep_ctrl;
+
+ _REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
+ // Buffer status register
+ // 0x80000000 [31] : EP15_OUT (0)
+ // 0x40000000 [30] : EP15_IN (0)
+ // 0x20000000 [29] : EP14_OUT (0)
+ // 0x10000000 [28] : EP14_IN (0)
+ // 0x08000000 [27] : EP13_OUT (0)
+ // 0x04000000 [26] : EP13_IN (0)
+ // 0x02000000 [25] : EP12_OUT (0)
+ // 0x01000000 [24] : EP12_IN (0)
+ // 0x00800000 [23] : EP11_OUT (0)
+ // 0x00400000 [22] : EP11_IN (0)
+ // 0x00200000 [21] : EP10_OUT (0)
+ // 0x00100000 [20] : EP10_IN (0)
+ // 0x00080000 [19] : EP9_OUT (0)
+ // 0x00040000 [18] : EP9_IN (0)
+ // 0x00020000 [17] : EP8_OUT (0)
+ // 0x00010000 [16] : EP8_IN (0)
+ // 0x00008000 [15] : EP7_OUT (0)
+ // 0x00004000 [14] : EP7_IN (0)
+ // 0x00002000 [13] : EP6_OUT (0)
+ // 0x00001000 [12] : EP6_IN (0)
+ // 0x00000800 [11] : EP5_OUT (0)
+ // 0x00000400 [10] : EP5_IN (0)
+ // 0x00000200 [9] : EP4_OUT (0)
+ // 0x00000100 [8] : EP4_IN (0)
+ // 0x00000080 [7] : EP3_OUT (0)
+ // 0x00000040 [6] : EP3_IN (0)
+ // 0x00000020 [5] : EP2_OUT (0)
+ // 0x00000010 [4] : EP2_IN (0)
+ // 0x00000008 [3] : EP1_OUT (0)
+ // 0x00000004 [2] : EP1_IN (0)
+ // 0x00000002 [1] : EP0_OUT (0)
+ // 0x00000001 [0] : EP0_IN (0)
+ io_rw_32 buf_status;
+
+ _REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
+ // Which of the double buffers should be handled
+ // 0x80000000 [31] : EP15_OUT (0)
+ // 0x40000000 [30] : EP15_IN (0)
+ // 0x20000000 [29] : EP14_OUT (0)
+ // 0x10000000 [28] : EP14_IN (0)
+ // 0x08000000 [27] : EP13_OUT (0)
+ // 0x04000000 [26] : EP13_IN (0)
+ // 0x02000000 [25] : EP12_OUT (0)
+ // 0x01000000 [24] : EP12_IN (0)
+ // 0x00800000 [23] : EP11_OUT (0)
+ // 0x00400000 [22] : EP11_IN (0)
+ // 0x00200000 [21] : EP10_OUT (0)
+ // 0x00100000 [20] : EP10_IN (0)
+ // 0x00080000 [19] : EP9_OUT (0)
+ // 0x00040000 [18] : EP9_IN (0)
+ // 0x00020000 [17] : EP8_OUT (0)
+ // 0x00010000 [16] : EP8_IN (0)
+ // 0x00008000 [15] : EP7_OUT (0)
+ // 0x00004000 [14] : EP7_IN (0)
+ // 0x00002000 [13] : EP6_OUT (0)
+ // 0x00001000 [12] : EP6_IN (0)
+ // 0x00000800 [11] : EP5_OUT (0)
+ // 0x00000400 [10] : EP5_IN (0)
+ // 0x00000200 [9] : EP4_OUT (0)
+ // 0x00000100 [8] : EP4_IN (0)
+ // 0x00000080 [7] : EP3_OUT (0)
+ // 0x00000040 [6] : EP3_IN (0)
+ // 0x00000020 [5] : EP2_OUT (0)
+ // 0x00000010 [4] : EP2_IN (0)
+ // 0x00000008 [3] : EP1_OUT (0)
+ // 0x00000004 [2] : EP1_IN (0)
+ // 0x00000002 [1] : EP0_OUT (0)
+ // 0x00000001 [0] : EP0_IN (0)
+ io_ro_32 buf_cpu_should_handle;
+
+ _REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
+ // Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer
+ // 0x80000000 [31] : EP15_OUT (0)
+ // 0x40000000 [30] : EP15_IN (0)
+ // 0x20000000 [29] : EP14_OUT (0)
+ // 0x10000000 [28] : EP14_IN (0)
+ // 0x08000000 [27] : EP13_OUT (0)
+ // 0x04000000 [26] : EP13_IN (0)
+ // 0x02000000 [25] : EP12_OUT (0)
+ // 0x01000000 [24] : EP12_IN (0)
+ // 0x00800000 [23] : EP11_OUT (0)
+ // 0x00400000 [22] : EP11_IN (0)
+ // 0x00200000 [21] : EP10_OUT (0)
+ // 0x00100000 [20] : EP10_IN (0)
+ // 0x00080000 [19] : EP9_OUT (0)
+ // 0x00040000 [18] : EP9_IN (0)
+ // 0x00020000 [17] : EP8_OUT (0)
+ // 0x00010000 [16] : EP8_IN (0)
+ // 0x00008000 [15] : EP7_OUT (0)
+ // 0x00004000 [14] : EP7_IN (0)
+ // 0x00002000 [13] : EP6_OUT (0)
+ // 0x00001000 [12] : EP6_IN (0)
+ // 0x00000800 [11] : EP5_OUT (0)
+ // 0x00000400 [10] : EP5_IN (0)
+ // 0x00000200 [9] : EP4_OUT (0)
+ // 0x00000100 [8] : EP4_IN (0)
+ // 0x00000080 [7] : EP3_OUT (0)
+ // 0x00000040 [6] : EP3_IN (0)
+ // 0x00000020 [5] : EP2_OUT (0)
+ // 0x00000010 [4] : EP2_IN (0)
+ // 0x00000008 [3] : EP1_OUT (0)
+ // 0x00000004 [2] : EP1_IN (0)
+ // 0x00000002 [1] : EP0_OUT (0)
+ // 0x00000001 [0] : EP0_IN (0)
+ io_rw_32 abort;
+
+ _REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
+ // Device only: Used in conjunction with `EP_ABORT`
+ // 0x80000000 [31] : EP15_OUT (0)
+ // 0x40000000 [30] : EP15_IN (0)
+ // 0x20000000 [29] : EP14_OUT (0)
+ // 0x10000000 [28] : EP14_IN (0)
+ // 0x08000000 [27] : EP13_OUT (0)
+ // 0x04000000 [26] : EP13_IN (0)
+ // 0x02000000 [25] : EP12_OUT (0)
+ // 0x01000000 [24] : EP12_IN (0)
+ // 0x00800000 [23] : EP11_OUT (0)
+ // 0x00400000 [22] : EP11_IN (0)
+ // 0x00200000 [21] : EP10_OUT (0)
+ // 0x00100000 [20] : EP10_IN (0)
+ // 0x00080000 [19] : EP9_OUT (0)
+ // 0x00040000 [18] : EP9_IN (0)
+ // 0x00020000 [17] : EP8_OUT (0)
+ // 0x00010000 [16] : EP8_IN (0)
+ // 0x00008000 [15] : EP7_OUT (0)
+ // 0x00004000 [14] : EP7_IN (0)
+ // 0x00002000 [13] : EP6_OUT (0)
+ // 0x00001000 [12] : EP6_IN (0)
+ // 0x00000800 [11] : EP5_OUT (0)
+ // 0x00000400 [10] : EP5_IN (0)
+ // 0x00000200 [9] : EP4_OUT (0)
+ // 0x00000100 [8] : EP4_IN (0)
+ // 0x00000080 [7] : EP3_OUT (0)
+ // 0x00000040 [6] : EP3_IN (0)
+ // 0x00000020 [5] : EP2_OUT (0)
+ // 0x00000010 [4] : EP2_IN (0)
+ // 0x00000008 [3] : EP1_OUT (0)
+ // 0x00000004 [2] : EP1_IN (0)
+ // 0x00000002 [1] : EP0_OUT (0)
+ // 0x00000001 [0] : EP0_IN (0)
+ io_rw_32 abort_done;
+
+ _REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
+ // Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0
+ // 0x00000002 [1] : EP0_OUT (0)
+ // 0x00000001 [0] : EP0_IN (0)
+ io_rw_32 ep_stall_arm;
+
+ _REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
+ // Used by the host controller
+ // 0x03ff0000 [25:16] : DELAY_FS (0x10): NAK polling interval for a full speed device
+ // 0x000003ff [9:0] : DELAY_LS (0x10): NAK polling interval for a low speed device
+ io_rw_32 nak_poll;
+
+ _REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
+ // Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
+ // 0x80000000 [31] : EP15_OUT (0)
+ // 0x40000000 [30] : EP15_IN (0)
+ // 0x20000000 [29] : EP14_OUT (0)
+ // 0x10000000 [28] : EP14_IN (0)
+ // 0x08000000 [27] : EP13_OUT (0)
+ // 0x04000000 [26] : EP13_IN (0)
+ // 0x02000000 [25] : EP12_OUT (0)
+ // 0x01000000 [24] : EP12_IN (0)
+ // 0x00800000 [23] : EP11_OUT (0)
+ // 0x00400000 [22] : EP11_IN (0)
+ // 0x00200000 [21] : EP10_OUT (0)
+ // 0x00100000 [20] : EP10_IN (0)
+ // 0x00080000 [19] : EP9_OUT (0)
+ // 0x00040000 [18] : EP9_IN (0)
+ // 0x00020000 [17] : EP8_OUT (0)
+ // 0x00010000 [16] : EP8_IN (0)
+ // 0x00008000 [15] : EP7_OUT (0)
+ // 0x00004000 [14] : EP7_IN (0)
+ // 0x00002000 [13] : EP6_OUT (0)
+ // 0x00001000 [12] : EP6_IN (0)
+ // 0x00000800 [11] : EP5_OUT (0)
+ // 0x00000400 [10] : EP5_IN (0)
+ // 0x00000200 [9] : EP4_OUT (0)
+ // 0x00000100 [8] : EP4_IN (0)
+ // 0x00000080 [7] : EP3_OUT (0)
+ // 0x00000040 [6] : EP3_IN (0)
+ // 0x00000020 [5] : EP2_OUT (0)
+ // 0x00000010 [4] : EP2_IN (0)
+ // 0x00000008 [3] : EP1_OUT (0)
+ // 0x00000004 [2] : EP1_IN (0)
+ // 0x00000002 [1] : EP0_OUT (0)
+ // 0x00000001 [0] : EP0_IN (0)
+ io_rw_32 ep_nak_stall_status;
+
+ _REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
+ // Where to connect the USB controller
+ // 0x00000008 [3] : SOFTCON (0)
+ // 0x00000004 [2] : TO_DIGITAL_PAD (0)
+ // 0x00000002 [1] : TO_EXTPHY (0)
+ // 0x00000001 [0] : TO_PHY (0)
+ io_rw_32 muxing;
+
+ _REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
+ // Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
+ // 0x00000020 [5] : OVERCURR_DETECT_EN (0)
+ // 0x00000010 [4] : OVERCURR_DETECT (0)
+ // 0x00000008 [3] : VBUS_DETECT_OVERRIDE_EN (0)
+ // 0x00000004 [2] : VBUS_DETECT (0)
+ // 0x00000002 [1] : VBUS_EN_OVERRIDE_EN (0)
+ // 0x00000001 [0] : VBUS_EN (0)
+ io_rw_32 pwr;
+
+ _REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
+ // This register allows for direct control of the USB phy
+ // 0x00400000 [22] : DM_OVV (0): DM over voltage
+ // 0x00200000 [21] : DP_OVV (0): DP over voltage
+ // 0x00100000 [20] : DM_OVCN (0): DM overcurrent
+ // 0x00080000 [19] : DP_OVCN (0): DP overcurrent
+ // 0x00040000 [18] : RX_DM (0): DPM pin state
+ // 0x00020000 [17] : RX_DP (0): DPP pin state
+ // 0x00010000 [16] : RX_DD (0): Differential RX
+ // 0x00008000 [15] : TX_DIFFMODE (0): TX_DIFFMODE=0: Single ended mode
+ // 0x00004000 [14] : TX_FSSLEW (0): TX_FSSLEW=0: Low speed slew rate
+ // 0x00002000 [13] : TX_PD (0): TX power down override (if override enable is set)
+ // 0x00001000 [12] : RX_PD (0): RX power down override (if override enable is set)
+ // 0x00000800 [11] : TX_DM (0): Output data
+ // 0x00000400 [10] : TX_DP (0): Output data
+ // 0x00000200 [9] : TX_DM_OE (0): Output enable
+ // 0x00000100 [8] : TX_DP_OE (0): Output enable
+ // 0x00000040 [6] : DM_PULLDN_EN (0): DM pull down enable
+ // 0x00000020 [5] : DM_PULLUP_EN (0): DM pull up enable
+ // 0x00000010 [4] : DM_PULLUP_HISEL (0): Enable the second DM pull up resistor
+ // 0x00000004 [2] : DP_PULLDN_EN (0): DP pull down enable
+ // 0x00000002 [1] : DP_PULLUP_EN (0): DP pull up enable
+ // 0x00000001 [0] : DP_PULLUP_HISEL (0): Enable the second DP pull up resistor
+ io_rw_32 phy_direct;
+
+ _REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
+ // Override enable for each control in usbphy_direct
+ // 0x00008000 [15] : TX_DIFFMODE_OVERRIDE_EN (0)
+ // 0x00001000 [12] : DM_PULLUP_OVERRIDE_EN (0)
+ // 0x00000800 [11] : TX_FSSLEW_OVERRIDE_EN (0)
+ // 0x00000400 [10] : TX_PD_OVERRIDE_EN (0)
+ // 0x00000200 [9] : RX_PD_OVERRIDE_EN (0)
+ // 0x00000100 [8] : TX_DM_OVERRIDE_EN (0)
+ // 0x00000080 [7] : TX_DP_OVERRIDE_EN (0)
+ // 0x00000040 [6] : TX_DM_OE_OVERRIDE_EN (0)
+ // 0x00000020 [5] : TX_DP_OE_OVERRIDE_EN (0)
+ // 0x00000010 [4] : DM_PULLDN_EN_OVERRIDE_EN (0)
+ // 0x00000008 [3] : DP_PULLDN_EN_OVERRIDE_EN (0)
+ // 0x00000004 [2] : DP_PULLUP_EN_OVERRIDE_EN (0)
+ // 0x00000002 [1] : DM_PULLUP_HISEL_OVERRIDE_EN (0)
+ // 0x00000001 [0] : DP_PULLUP_HISEL_OVERRIDE_EN (0)
+ io_rw_32 phy_direct_override;
+
+ _REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
+ // Used to adjust trim values of USB phy pull down resistors
+ // 0x00001f00 [12:8] : DM_PULLDN_TRIM (0x1f): Value to drive to USB PHY
+ // 0x0000001f [4:0] : DP_PULLDN_TRIM (0x1f): Value to drive to USB PHY
+ io_rw_32 phy_trim;
+
+ uint32_t _pad0;
+
+ _REG_(USB_INTR_OFFSET) // USB_INTR
+ // Raw Interrupts
+ // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+ // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+ // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+ // 0x00010000 [16] : SETUP_REQ (0): Device
+ // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+ // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
+ // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
+ // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
+ // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
+ // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
+ // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
+ // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+ // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+ // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+ // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+ // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+ // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+ // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+ // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
+ // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+ io_ro_32 intr;
+
+ _REG_(USB_INTE_OFFSET) // USB_INTE
+ // Interrupt Enable
+ // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+ // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+ // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+ // 0x00010000 [16] : SETUP_REQ (0): Device
+ // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+ // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
+ // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
+ // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
+ // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
+ // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
+ // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
+ // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+ // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+ // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+ // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+ // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+ // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+ // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+ // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
+ // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+ io_rw_32 inte;
+
+ _REG_(USB_INTF_OFFSET) // USB_INTF
+ // Interrupt Force
+ // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+ // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+ // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+ // 0x00010000 [16] : SETUP_REQ (0): Device
+ // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+ // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
+ // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
+ // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
+ // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
+ // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
+ // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
+ // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+ // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+ // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+ // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+ // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+ // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+ // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+ // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
+ // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+ io_rw_32 intf;
+
+ _REG_(USB_INTS_OFFSET) // USB_INTS
+ // Interrupt status after masking & forcing
+ // 0x00080000 [19] : EP_STALL_NAK (0): Raised when any bit in EP_STATUS_STALL_NAK is set
+ // 0x00040000 [18] : ABORT_DONE (0): Raised when any bit in ABORT_DONE is set
+ // 0x00020000 [17] : DEV_SOF (0): Set every time the device receives a SOF (Start of Frame) packet
+ // 0x00010000 [16] : SETUP_REQ (0): Device
+ // 0x00008000 [15] : DEV_RESUME_FROM_HOST (0): Set when the device receives a resume from the host
+ // 0x00004000 [14] : DEV_SUSPEND (0): Set when the device suspend state changes
+ // 0x00002000 [13] : DEV_CONN_DIS (0): Set when the device connection state changes
+ // 0x00001000 [12] : BUS_RESET (0): Source: SIE_STATUS
+ // 0x00000800 [11] : VBUS_DETECT (0): Source: SIE_STATUS
+ // 0x00000400 [10] : STALL (0): Source: SIE_STATUS
+ // 0x00000200 [9] : ERROR_CRC (0): Source: SIE_STATUS
+ // 0x00000100 [8] : ERROR_BIT_STUFF (0): Source: SIE_STATUS
+ // 0x00000080 [7] : ERROR_RX_OVERFLOW (0): Source: SIE_STATUS
+ // 0x00000040 [6] : ERROR_RX_TIMEOUT (0): Source: SIE_STATUS
+ // 0x00000020 [5] : ERROR_DATA_SEQ (0): Source: SIE_STATUS
+ // 0x00000010 [4] : BUFF_STATUS (0): Raised when any bit in BUFF_STATUS is set
+ // 0x00000008 [3] : TRANS_COMPLETE (0): Raised every time SIE_STATUS
+ // 0x00000004 [2] : HOST_SOF (0): Host: raised every time the host sends a SOF (Start of Frame)
+ // 0x00000002 [1] : HOST_RESUME (0): Host: raised when a device wakes up the host
+ // 0x00000001 [0] : HOST_CONN_DIS (0): Host: raised when a device is connected or disconnected (i
+ io_ro_32 ints;
+} usb_hw_t;
+
+#define usb_hw ((usb_hw_t *const)USBCTRL_REGS_BASE)
+
+#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
+#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
+
+static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, "");
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/vreg_and_chip_reset.h b/arkanoid/pico/hardware/structs/vreg_and_chip_reset.h
new file mode 100644
index 0000000..216b9f0
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/vreg_and_chip_reset.h
@@ -0,0 +1,49 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
+#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
+
+#include "../address_mapped.h"
+#include "../regs/vreg_and_chip_reset.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/vreg_and_chip_reset.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG
+ // Voltage regulator control and status
+ // 0x00001000 [12] : ROK (0): regulation status
+ // 0x000000f0 [7:4] : VSEL (0xb): output voltage select
+ // 0x00000002 [1] : HIZ (0): high impedance mode select
+ // 0x00000001 [0] : EN (1): enable
+ io_rw_32 vreg;
+
+ _REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD
+ // brown-out detection control
+ // 0x000000f0 [7:4] : VSEL (0x9): threshold select
+ // 0x00000001 [0] : EN (1): enable
+ io_rw_32 bod;
+
+ _REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET
+ // Chip reset control and status
+ // 0x01000000 [24] : PSM_RESTART_FLAG (0): This is set by psm_restart from the debugger
+ // 0x00100000 [20] : HAD_PSM_RESTART (0): Last reset was from the debug port
+ // 0x00010000 [16] : HAD_RUN (0): Last reset was from the RUN pin
+ // 0x00000100 [8] : HAD_POR (0): Last reset was from the power-on reset or brown-out detection blocks
+ io_rw_32 chip_reset;
+} vreg_and_chip_reset_hw_t;
+
+#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *const)VREG_AND_CHIP_RESET_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/watchdog.h b/arkanoid/pico/hardware/structs/watchdog.h
new file mode 100644
index 0000000..28ece31
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/watchdog.h
@@ -0,0 +1,62 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_WATCHDOG_H
+#define _HARDWARE_STRUCTS_WATCHDOG_H
+
+#include "../address_mapped.h"
+#include "../regs/watchdog.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/watchdog.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL
+ // Watchdog control
+ // 0x80000000 [31] : TRIGGER (0): Trigger a watchdog reset
+ // 0x40000000 [30] : ENABLE (0): When not enabled the watchdog timer is paused
+ // 0x04000000 [26] : PAUSE_DBG1 (1): Pause the watchdog timer when processor 1 is in debug mode
+ // 0x02000000 [25] : PAUSE_DBG0 (1): Pause the watchdog timer when processor 0 is in debug mode
+ // 0x01000000 [24] : PAUSE_JTAG (1): Pause the watchdog timer when JTAG is accessing the bus fabric
+ // 0x00ffffff [23:0] : TIME (0): Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will...
+ io_rw_32 ctrl;
+
+ _REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD
+ // Load the watchdog timer
+ // 0x00ffffff [23:0] : LOAD (0)
+ io_wo_32 load;
+
+ _REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON
+ // Logs the reason for the last reset
+ // 0x00000002 [1] : FORCE (0)
+ // 0x00000001 [0] : TIMER (0)
+ io_ro_32 reason;
+
+ _REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0
+ // (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes)
+ //
+ // Scratch register
+ io_rw_32 scratch[8];
+
+ _REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK
+ // Controls the tick generator
+ // 0x000ff800 [19:11] : COUNT (0): Count down timer: the remaining number clk_tick cycles before the next tick is generated
+ // 0x00000400 [10] : RUNNING (0): Is the tick generator running?
+ // 0x00000200 [9] : ENABLE (1): start / stop tick generation
+ // 0x000001ff [8:0] : CYCLES (0): Total number of clk_tick cycles before the next tick
+ io_rw_32 tick;
+} watchdog_hw_t;
+
+#define watchdog_hw ((watchdog_hw_t *const)WATCHDOG_BASE)
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/xip_ctrl.h b/arkanoid/pico/hardware/structs/xip_ctrl.h
new file mode 100644
index 0000000..2a1de36
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/xip_ctrl.h
@@ -0,0 +1,72 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_XIP_CTRL_H
+#define _HARDWARE_STRUCTS_XIP_CTRL_H
+
+#include "../address_mapped.h"
+#include "../regs/xip.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/xip.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+typedef struct {
+ _REG_(XIP_CTRL_OFFSET) // XIP_CTRL
+ // Cache control
+ // 0x00000008 [3] : POWER_DOWN (0): When 1, the cache memories are powered down
+ // 0x00000002 [1] : ERR_BADWRITE (1): When 1, writes to any alias other than 0x0 (caching, allocating)
+ // 0x00000001 [0] : EN (1): When 1, enable the cache
+ io_rw_32 ctrl;
+
+ _REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
+ // Cache Flush control
+ // 0x00000001 [0] : FLUSH (0): Write 1 to flush the cache
+ io_rw_32 flush;
+
+ _REG_(XIP_STAT_OFFSET) // XIP_STAT
+ // Cache Status
+ // 0x00000004 [2] : FIFO_FULL (0): When 1, indicates the XIP streaming FIFO is completely full
+ // 0x00000002 [1] : FIFO_EMPTY (1): When 1, indicates the XIP streaming FIFO is completely empty
+ // 0x00000001 [0] : FLUSH_READY (0): Reads as 0 while a cache flush is in progress, and 1 otherwise
+ io_ro_32 stat;
+
+ _REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
+ // Cache Hit counter
+ io_rw_32 ctr_hit;
+
+ _REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
+ // Cache Access counter
+ io_rw_32 ctr_acc;
+
+ _REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
+ // FIFO stream address
+ // 0xfffffffc [31:2] : STREAM_ADDR (0): The address of the next word to be streamed from flash to the streaming FIFO
+ io_rw_32 stream_addr;
+
+ _REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
+ // FIFO stream control
+ // 0x003fffff [21:0] : STREAM_CTR (0): Write a nonzero value to start a streaming read
+ io_rw_32 stream_ctr;
+
+ _REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
+ // FIFO stream data
+ io_ro_32 stream_fifo;
+} xip_ctrl_hw_t;
+
+#define xip_ctrl_hw ((xip_ctrl_hw_t *const)XIP_CTRL_BASE)
+
+#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS
+#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS
+#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS
+
+#endif
diff --git a/arkanoid/pico/hardware/structs/xosc.h b/arkanoid/pico/hardware/structs/xosc.h
new file mode 100644
index 0000000..feb52a4
--- /dev/null
+++ b/arkanoid/pico/hardware/structs/xosc.h
@@ -0,0 +1,60 @@
+// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
+
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_STRUCTS_XOSC_H
+#define _HARDWARE_STRUCTS_XOSC_H
+
+#include "../address_mapped.h"
+#include "../regs/xosc.h"
+
+// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc
+//
+// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
+// _REG_(x) will link to the corresponding register in ../regs/xosc.h.
+//
+// Bit-field descriptions are of the form:
+// BITMASK [BITRANGE]: FIELDNAME (RESETVALUE): DESCRIPTION
+
+/// \tag::xosc_hw[]
+typedef struct {
+ _REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL
+ // Crystal Oscillator Control
+ // 0x00fff000 [23:12] : ENABLE (0): On power-up this field is initialised to DISABLE and the chip runs from the ROSC
+ // 0x00000fff [11:0] : FREQ_RANGE (0): Frequency range
+ io_rw_32 ctrl;
+
+ _REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS
+ // Crystal Oscillator Status
+ // 0x80000000 [31] : STABLE (0): Oscillator is running and stable
+ // 0x01000000 [24] : BADWRITE (0): An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
+ // 0x00001000 [12] : ENABLED (0): Oscillator is enabled but not necessarily running and stable, resets to 0
+ // 0x00000003 [1:0] : FREQ_RANGE (0): The current frequency range setting, always reads 0
+ io_rw_32 status;
+
+ _REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT
+ // Crystal Oscillator pause control
+ io_rw_32 dormant;
+
+ _REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP
+ // Controls the startup delay
+ // 0x00100000 [20] : X4 (0): Multiplies the startup_delay by 4
+ // 0x00003fff [13:0] : DELAY (0xc4): in multiples of 256*xtal_period
+ io_rw_32 startup;
+
+ uint32_t _pad0[3];
+
+ _REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT
+ // A down counter running at the xosc frequency which counts to zero and stops
+ // 0x000000ff [7:0] : COUNT (0)
+ io_rw_32 count;
+} xosc_hw_t;
+
+#define xosc_hw ((xosc_hw_t *const)XOSC_BASE)
+/// \end::xosc_hw[]
+
+#endif
diff --git a/arkanoid/pico/hardware/sync.c b/arkanoid/pico/hardware/sync.c
new file mode 100644
index 0000000..f926fa8
--- /dev/null
+++ b/arkanoid/pico/hardware/sync.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "sync.h"
+#include "claim.h"
+
+static_assert(PICO_SPINLOCK_ID_STRIPED_LAST >= PICO_SPINLOCK_ID_STRIPED_FIRST, "");
+static uint8_t striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST;
+static uint32_t claimed;
+
+static void check_lock_num(uint __unused lock_num) {
+ invalid_params_if(SYNC, lock_num >= 32);
+}
+
+void spin_locks_reset(void) {
+ for (uint i = 0; i < NUM_SPIN_LOCKS; i++) {
+ spin_unlock_unsafe(spin_lock_instance(i));
+ }
+}
+
+spin_lock_t *spin_lock_init(uint lock_num) {
+ assert(lock_num < NUM_SPIN_LOCKS);
+ spin_lock_t *lock = spin_lock_instance(lock_num);
+ spin_unlock_unsafe(lock);
+ return lock;
+}
+
+uint next_striped_spin_lock_num() {
+ uint rc = striped_spin_lock_num++;
+ if (striped_spin_lock_num > PICO_SPINLOCK_ID_STRIPED_LAST) {
+ striped_spin_lock_num = PICO_SPINLOCK_ID_STRIPED_FIRST;
+ }
+ return rc;
+}
+
+void spin_lock_claim(uint lock_num) {
+ check_lock_num(lock_num);
+ hw_claim_or_assert((uint8_t *) &claimed, lock_num, "Spinlock %d is already claimed");
+}
+
+void spin_lock_claim_mask(uint32_t mask) {
+ for(uint i = 0; mask; i++, mask >>= 1u) {
+ if (mask & 1u) spin_lock_claim(i);
+ }
+}
+
+void spin_lock_unclaim(uint lock_num) {
+ check_lock_num(lock_num);
+ spin_unlock_unsafe(spin_lock_instance(lock_num));
+ hw_claim_clear((uint8_t *) &claimed, lock_num);
+}
+
+int spin_lock_claim_unused(bool required) {
+ return hw_claim_unused_from_range((uint8_t*)&claimed, required, PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, PICO_SPINLOCK_ID_CLAIM_FREE_LAST, "No spinlocks are available");
+}
+
+bool spin_lock_is_claimed(uint lock_num) {
+ check_lock_num(lock_num);
+ return hw_is_claimed((uint8_t *) &claimed, lock_num);
+}
+
diff --git a/arkanoid/pico/hardware/sync.h b/arkanoid/pico/hardware/sync.h
new file mode 100644
index 0000000..123da2e
--- /dev/null
+++ b/arkanoid/pico/hardware/sync.h
@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_SYNC_H
+#define _HARDWARE_SYNC_H
+
+#include "../pico.h"
+#include "address_mapped.h"
+#include "regs/sio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file sync.h
+ * \defgroup hardware_sync hardware_sync
+ *
+ * Low level hardware spin locks, barrier and processor event APIs
+ *
+ * Spin Locks
+ * ----------
+ *
+ * The RP2040 provides 32 hardware spin locks, which can be used to manage mutually-exclusive access to shared software
+ * and hardware resources.
+ *
+ * Generally each spin lock itself is a shared resource,
+ * i.e. the same hardware spin lock can be used by multiple higher level primitives (as long as the spin locks are neither held for long periods, nor
+ * held concurrently with other spin locks by the same core - which could lead to deadlock). A hardware spin lock that is exclusively owned can be used
+ * individually without more flexibility and without regard to other software. Note that no hardware spin lock may
+ * be acquired re-entrantly (i.e. hardware spin locks are not on their own safe for use by both thread code and IRQs) however the default spinlock related
+ * methods here (e.g. \ref spin_lock_blocking) always disable interrupts while the lock is held as use by IRQ handlers and user code is common/desirable,
+ * and spin locks are only expected to be held for brief periods.
+ *
+ * The SDK uses the following default spin lock assignments, classifying which spin locks are reserved for exclusive/special purposes
+ * vs those suitable for more general shared use:
+ *
+ * Number (ID) | Description
+ * :---------: | -----------
+ * 0-13 | Currently reserved for exclusive use by the SDK and other libraries. If you use these spin locks, you risk breaking SDK or other library functionality. Each reserved spin lock used individually has its own PICO_SPINLOCK_ID so you can search for those.
+ * 14,15 | (\ref PICO_SPINLOCK_ID_OS1 and \ref PICO_SPINLOCK_ID_OS2). Currently reserved for exclusive use by an operating system (or other system level software) co-existing with the SDK.
+ * 16-23 | (\ref PICO_SPINLOCK_ID_STRIPED_FIRST - \ref PICO_SPINLOCK_ID_STRIPED_LAST). Spin locks from this range are assigned in a round-robin fashion via \ref next_striped_spin_lock_num(). These spin locks are shared, but assigning numbers from a range reduces the probability that two higher level locking primitives using _striped_ spin locks will actually be using the same spin lock.
+ * 24-31 | (\ref PICO_SPINLOCK_ID_CLAIM_FREE_FIRST - \ref PICO_SPINLOCK_ID_CLAIM_FREE_LAST). These are reserved for exclusive use and are allocated on a first come first served basis at runtime via \ref spin_lock_claim_unused()
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_SYNC, Enable/disable assertions in the HW sync module, type=bool, default=0, group=hardware_sync
+#ifndef PARAM_ASSERTIONS_ENABLED_SYNC
+#define PARAM_ASSERTIONS_ENABLED_SYNC 0
+#endif
+
+/** \brief A spin lock identifier
+ * \ingroup hardware_sync
+ */
+typedef volatile uint32_t spin_lock_t;
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_IRQ
+#define PICO_SPINLOCK_ID_IRQ 9
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_TIMER
+#define PICO_SPINLOCK_ID_TIMER 10
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM
+#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS1
+#define PICO_SPINLOCK_ID_OS1 14
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_OS2
+#define PICO_SPINLOCK_ID_OS2 15
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_STRIPED_FIRST
+#define PICO_SPINLOCK_ID_STRIPED_FIRST 16
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_STRIPED_LAST
+#define PICO_SPINLOCK_ID_STRIPED_LAST 23
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST
+#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24
+#endif
+
+#ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END
+#warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST
+#endif
+
+// PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_LAST, Highest Spinlock ID in the 'claim free' range, min=0, max=31, default=31, group=hardware_sync
+#ifndef PICO_SPINLOCK_ID_CLAIM_FREE_LAST
+#define PICO_SPINLOCK_ID_CLAIM_FREE_LAST 31
+#endif
+
+/*! \brief Insert a SEV instruction in to the code path.
+ * \ingroup hardware_sync
+
+ * The SEV (send event) instruction sends an event to both cores.
+ */
+__force_inline static void __sev(void) {
+ __asm volatile ("sev");
+}
+
+/*! \brief Insert a WFE instruction in to the code path.
+ * \ingroup hardware_sync
+ *
+ * The WFE (wait for event) instruction waits until one of a number of
+ * events occurs, including events signalled by the SEV instruction on either core.
+ */
+__force_inline static void __wfe(void) {
+ __asm volatile ("wfe");
+}
+
+/*! \brief Insert a WFI instruction in to the code path.
+ * \ingroup hardware_sync
+*
+ * The WFI (wait for interrupt) instruction waits for a interrupt to wake up the core.
+ */
+__force_inline static void __wfi(void) {
+ __asm volatile ("wfi");
+}
+
+/*! \brief Insert a DMB instruction in to the code path.
+ * \ingroup hardware_sync
+ *
+ * The DMB (data memory barrier) acts as a memory barrier, all memory accesses prior to this
+ * instruction will be observed before any explicit access after the instruction.
+ */
+__force_inline static void __dmb(void) {
+ __asm volatile ("dmb" : : : "memory");
+}
+
+/*! \brief Insert a DSB instruction in to the code path.
+ * \ingroup hardware_sync
+ *
+ * The DSB (data synchronization barrier) acts as a special kind of data
+ * memory barrier (DMB). The DSB operation completes when all explicit memory
+ * accesses before this instruction complete.
+ */
+__force_inline static void __dsb(void) {
+ __asm volatile ("dsb" : : : "memory");
+}
+
+/*! \brief Insert a ISB instruction in to the code path.
+ * \ingroup hardware_sync
+ *
+ * ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor,
+ * so that all instructions following the ISB are fetched from cache or memory again, after
+ * the ISB instruction has been completed.
+ */
+__force_inline static void __isb(void) {
+ __asm volatile ("isb");
+}
+
+/*! \brief Acquire a memory fence
+ * \ingroup hardware_sync
+ */
+__force_inline static void __mem_fence_acquire(void) {
+ // the original code below makes it hard for us to be included from C++ via a header
+ // which itself is in an extern "C", so just use __dmb instead, which is what
+ // is required on Cortex M0+
+ __dmb();
+//#ifndef __cplusplus
+// atomic_thread_fence(memory_order_acquire);
+//#else
+// std::atomic_thread_fence(std::memory_order_acquire);
+//#endif
+}
+
+/*! \brief Release a memory fence
+ * \ingroup hardware_sync
+ *
+ */
+__force_inline static void __mem_fence_release(void) {
+ // the original code below makes it hard for us to be included from C++ via a header
+ // which itself is in an extern "C", so just use __dmb instead, which is what
+ // is required on Cortex M0+
+ __dmb();
+//#ifndef __cplusplus
+// atomic_thread_fence(memory_order_release);
+//#else
+// std::atomic_thread_fence(std::memory_order_release);
+//#endif
+}
+
+/*! \brief Save and disable interrupts
+ * \ingroup hardware_sync
+ *
+ * \return The prior interrupt enable status for restoration later via restore_interrupts()
+ */
+__force_inline static uint32_t save_and_disable_interrupts(void) {
+ uint32_t status;
+ __asm volatile ("mrs %0, PRIMASK" : "=r" (status)::);
+ __asm volatile ("cpsid i");
+ return status;
+}
+
+/*! \brief Restore interrupts to a specified state
+ * \ingroup hardware_sync
+ *
+ * \param status Previous interrupt status from save_and_disable_interrupts()
+ */
+__force_inline static void restore_interrupts(uint32_t status) {
+ __asm volatile ("msr PRIMASK,%0"::"r" (status) : );
+}
+
+/*! \brief Get HW Spinlock instance from number
+ * \ingroup hardware_sync
+ *
+ * \param lock_num Spinlock ID
+ * \return The spinlock instance
+ */
+__force_inline static spin_lock_t *spin_lock_instance(uint lock_num) {
+ invalid_params_if(SYNC, lock_num >= NUM_SPIN_LOCKS);
+ return (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET + lock_num * 4);
+}
+
+/*! \brief Get HW Spinlock number from instance
+ * \ingroup hardware_sync
+ *
+ * \param lock The Spinlock instance
+ * \return The Spinlock ID
+ */
+__force_inline static uint spin_lock_get_num(spin_lock_t *lock) {
+ invalid_params_if(SYNC, (uint) lock < SIO_BASE + SIO_SPINLOCK0_OFFSET ||
+ (uint) lock >= NUM_SPIN_LOCKS * sizeof(spin_lock_t) + SIO_BASE + SIO_SPINLOCK0_OFFSET ||
+ ((uint) lock - SIO_BASE + SIO_SPINLOCK0_OFFSET) % sizeof(spin_lock_t) != 0);
+ return (uint) (lock - (spin_lock_t *) (SIO_BASE + SIO_SPINLOCK0_OFFSET));
+}
+
+/*! \brief Acquire a spin lock without disabling interrupts (hence unsafe)
+ * \ingroup hardware_sync
+ *
+ * \param lock Spinlock instance
+ */
+__force_inline static void spin_lock_unsafe_blocking(spin_lock_t *lock) {
+ // Note we don't do a wfe or anything, because by convention these spin_locks are VERY SHORT LIVED and NEVER BLOCK and run
+ // with INTERRUPTS disabled (to ensure that)... therefore nothing on our core could be blocking us, so we just need to wait on another core
+ // anyway which should be finished soon
+ while (__builtin_expect(!*lock, 0));
+ __mem_fence_acquire();
+}
+
+/*! \brief Release a spin lock without re-enabling interrupts
+ * \ingroup hardware_sync
+ *
+ * \param lock Spinlock instance
+ */
+__force_inline static void spin_unlock_unsafe(spin_lock_t *lock) {
+ __mem_fence_release();
+ *lock = 0;
+}
+
+/*! \brief Acquire a spin lock safely
+ * \ingroup hardware_sync
+ *
+ * This function will disable interrupts prior to acquiring the spinlock
+ *
+ * \param lock Spinlock instance
+ * \return interrupt status to be used when unlocking, to restore to original state
+ */
+__force_inline static uint32_t spin_lock_blocking(spin_lock_t *lock) {
+ uint32_t save = save_and_disable_interrupts();
+ spin_lock_unsafe_blocking(lock);
+ return save;
+}
+
+/*! \brief Check to see if a spinlock is currently acquired elsewhere.
+ * \ingroup hardware_sync
+ *
+ * \param lock Spinlock instance
+ */
+inline static bool is_spin_locked(spin_lock_t *lock) {
+ check_hw_size(spin_lock_t, 4);
+ uint lock_num = spin_lock_get_num(lock);
+ return 0 != (*(io_ro_32 *) (SIO_BASE + SIO_SPINLOCK_ST_OFFSET) & (1u << lock_num));
+}
+
+/*! \brief Release a spin lock safely
+ * \ingroup hardware_sync
+ *
+ * This function will re-enable interrupts according to the parameters.
+ *
+ * \param lock Spinlock instance
+ * \param saved_irq Return value from the \ref spin_lock_blocking() function.
+ * \return interrupt status to be used when unlocking, to restore to original state
+ *
+ * \sa spin_lock_blocking()
+ */
+__force_inline static void spin_unlock(spin_lock_t *lock, uint32_t saved_irq) {
+ spin_unlock_unsafe(lock);
+ restore_interrupts(saved_irq);
+}
+
+/*! \brief Get the current core number
+ * \ingroup hardware_sync
+ *
+ * \return The core number the call was made from
+ */
+__force_inline static uint get_core_num(void) {
+ return (*(uint32_t *) (SIO_BASE + SIO_CPUID_OFFSET));
+}
+
+/*! \brief Initialise a spin lock
+ * \ingroup hardware_sync
+ *
+ * The spin lock is initially unlocked
+ *
+ * \param lock_num The spin lock number
+ * \return The spin lock instance
+ */
+spin_lock_t *spin_lock_init(uint lock_num);
+
+/*! \brief Release all spin locks
+ * \ingroup hardware_sync
+ */
+void spin_locks_reset(void);
+
+/*! \brief Return a spin lock number from the _striped_ range
+ * \ingroup hardware_sync
+ *
+ * Returns a spin lock number in the range PICO_SPINLOCK_ID_STRIPED_FIRST to PICO_SPINLOCK_ID_STRIPED_LAST
+ * in a round robin fashion. This does not grant the caller exclusive access to the spin lock, so the caller
+ * must:
+ *
+ * -# Abide (with other callers) by the contract of only holding this spin lock briefly (and with IRQs disabled - the default via \ref spin_lock_blocking()),
+ * and not whilst holding other spin locks.
+ * -# Be OK with any contention caused by the - brief due to the above requirement - contention with other possible users of the spin lock.
+ *
+ * \return lock_num a spin lock number the caller may use (non exclusively)
+ * \see PICO_SPINLOCK_ID_STRIPED_FIRST
+ * \see PICO_SPINLOCK_ID_STRIPED_LAST
+ */
+uint next_striped_spin_lock_num(void);
+
+/*! \brief Mark a spin lock as used
+ * \ingroup hardware_sync
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if the spin lock
+ * is already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param lock_num the spin lock number
+ */
+void spin_lock_claim(uint lock_num);
+
+/*! \brief Mark multiple spin locks as used
+ * \ingroup hardware_sync
+ *
+ * Method for cooperative claiming of hardware. Will cause a panic if any of the spin locks
+ * are already claimed. Use of this method by libraries detects accidental
+ * configurations that would fail in unpredictable ways.
+ *
+ * \param lock_num_mask Bitfield of all required spin locks to claim (bit 0 == spin lock 0, bit 1 == spin lock 1 etc)
+ */
+void spin_lock_claim_mask(uint32_t lock_num_mask);
+
+/*! \brief Mark a spin lock as no longer used
+ * \ingroup hardware_sync
+ *
+ * Method for cooperative claiming of hardware.
+ *
+ * \param lock_num the spin lock number to release
+ */
+void spin_lock_unclaim(uint lock_num);
+
+/*! \brief Claim a free spin lock
+ * \ingroup hardware_sync
+ *
+ * \param required if true the function will panic if none are available
+ * \return the spin lock number or -1 if required was false, and none were free
+ */
+int spin_lock_claim_unused(bool required);
+
+/*! \brief Determine if a spin lock is claimed
+ * \ingroup hardware_sync
+ *
+ * \param lock_num the spin lock number
+ * \return true if claimed, false otherwise
+ * \see spin_lock_claim
+ * \see spin_lock_claim_mask
+ */
+bool spin_lock_is_claimed(uint lock_num);
+
+#define remove_volatile_cast(t, x) ({__mem_fence_acquire(); (t)(x); })
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/timer.c b/arkanoid/pico/hardware/timer.c
new file mode 100644
index 0000000..f3b0608
--- /dev/null
+++ b/arkanoid/pico/hardware/timer.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "timer.h"
+#include "irq.h"
+#include "sync.h"
+#include "claim.h"
+
+check_hw_layout(timer_hw_t, ints, TIMER_INTS_OFFSET);
+
+static hardware_alarm_callback_t alarm_callbacks[NUM_TIMERS];
+static uint32_t target_hi[NUM_TIMERS];
+static uint8_t timer_callbacks_pending;
+
+static_assert(NUM_TIMERS <= 4, "");
+static uint8_t claimed;
+
+void hardware_alarm_claim(uint alarm_num) {
+ check_hardware_alarm_num_param(alarm_num);
+ hw_claim_or_assert(&claimed, alarm_num, "Hardware alarm %d already claimed");
+}
+
+void hardware_alarm_unclaim(uint alarm_num) {
+ check_hardware_alarm_num_param(alarm_num);
+ hw_claim_clear(&claimed, alarm_num);
+}
+
+bool hardware_alarm_is_claimed(uint alarm_num) {
+ check_hardware_alarm_num_param(alarm_num);
+ return hw_is_claimed(&claimed, alarm_num);
+}
+
+/// tag::time_us_64[]
+uint64_t time_us_64() {
+ // Need to make sure that the upper 32 bits of the timer
+ // don't change, so read that first
+ uint32_t hi = timer_hw->timerawh;
+ uint32_t lo;
+ do {
+ // Read the lower 32 bits
+ lo = timer_hw->timerawl;
+ // Now read the upper 32 bits again and
+ // check that it hasn't incremented. If it has loop around
+ // and read the lower 32 bits again to get an accurate value
+ uint32_t next_hi = timer_hw->timerawh;
+ if (hi == next_hi) break;
+ hi = next_hi;
+ } while (true);
+ return ((uint64_t) hi << 32u) | lo;
+}
+/// end::time_us_64[]
+
+/// \tag::busy_wait[]
+void busy_wait_us_32(uint32_t delay_us) {
+ if (0 <= (int32_t)delay_us) {
+ // we only allow 31 bits, otherwise we could have a race in the loop below with
+ // values very close to 2^32
+ uint32_t start = timer_hw->timerawl;
+ while (timer_hw->timerawl - start < delay_us) {
+ tight_loop_contents();
+ }
+ } else {
+ busy_wait_us(delay_us);
+ }
+}
+
+void busy_wait_us(uint64_t delay_us) {
+ uint64_t base = time_us_64();
+ uint64_t target = base + delay_us;
+ if (target < base) {
+ target = (uint64_t)-1;
+ }
+ absolute_time_t t;
+ update_us_since_boot(&t, target);
+ busy_wait_until(t);
+}
+
+void busy_wait_ms(uint32_t delay_ms)
+{
+ if (delay_ms <= 0x7fffffffu / 1000) {
+ busy_wait_us_32(delay_ms * 1000);
+ } else {
+ busy_wait_us(delay_ms * 1000ull);
+ }
+}
+
+void busy_wait_until(absolute_time_t t) {
+ uint64_t target = to_us_since_boot(t);
+ uint32_t hi_target = (uint32_t)(target >> 32u);
+ uint32_t hi = timer_hw->timerawh;
+ while (hi < hi_target) {
+ hi = timer_hw->timerawh;
+ tight_loop_contents();
+ }
+ while (hi == hi_target && timer_hw->timerawl < (uint32_t) target) {
+ hi = timer_hw->timerawh;
+ tight_loop_contents();
+ }
+}
+/// \end::busy_wait[]
+
+static inline uint harware_alarm_irq_number(uint alarm_num) {
+ return TIMER_IRQ_0 + alarm_num;
+}
+
+static void hardware_alarm_irq_handler(void) {
+ // Determine which timer this IRQ is for
+ uint32_t ipsr;
+ __asm volatile ("mrs %0, ipsr" : "=r" (ipsr)::);
+ uint alarm_num = (ipsr & 0x3fu) - 16 - TIMER_IRQ_0;
+ check_hardware_alarm_num_param(alarm_num);
+
+ hardware_alarm_callback_t callback = NULL;
+
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+ uint32_t save = spin_lock_blocking(lock);
+ // Clear the timer IRQ (inside lock, because we check whether we have handled the IRQ yet in alarm_set by looking at the interrupt status
+ timer_hw->intr = 1u << alarm_num;
+
+ // make sure the IRQ is still valid
+ if (timer_callbacks_pending & (1u << alarm_num)) {
+ // Now check whether we have a timer event to handle that isn't already obsolete (this could happen if we
+ // were already in the IRQ handler before someone else changed the timer setup
+ if (timer_hw->timerawh >= target_hi[alarm_num]) {
+ // we have reached the right high word as well as low word value
+ callback = alarm_callbacks[alarm_num];
+ timer_callbacks_pending &= (uint8_t)~(1u << alarm_num);
+ } else {
+ // try again in 2^32 us
+ timer_hw->alarm[alarm_num] = timer_hw->alarm[alarm_num]; // re-arm the timer
+ }
+ }
+
+ spin_unlock(lock, save);
+
+ if (callback) {
+ callback(alarm_num);
+ }
+}
+
+void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback) {
+ // todo check current core owner
+ // note this should probably be subsumed by irq_set_exclusive_handler anyway, since that
+ // should disallow IRQ handlers on both cores
+ check_hardware_alarm_num_param(alarm_num);
+ uint irq_num = harware_alarm_irq_number(alarm_num);
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+ uint32_t save = spin_lock_blocking(lock);
+ if (callback) {
+ if (hardware_alarm_irq_handler != irq_get_vtable_handler(irq_num)) {
+ // note that set_exclusive will silently allow you to set the handler to the same thing
+ // since it is idempotent, which means we don't need to worry about locking ourselves
+ irq_set_exclusive_handler(irq_num, hardware_alarm_irq_handler);
+ irq_set_enabled(irq_num, true);
+ // Enable interrupt in block and at processor
+ hw_set_bits(&timer_hw->inte, 1u << alarm_num);
+ }
+ alarm_callbacks[alarm_num] = callback;
+ } else {
+ alarm_callbacks[alarm_num] = NULL;
+ timer_callbacks_pending &= (uint8_t)~(1u << alarm_num);
+ irq_remove_handler(irq_num, hardware_alarm_irq_handler);
+ irq_set_enabled(irq_num, false);
+ }
+ spin_unlock(lock, save);
+}
+
+bool hardware_alarm_set_target(uint alarm_num, absolute_time_t target) {
+ bool missed;
+ uint64_t now = time_us_64();
+ uint64_t t = to_us_since_boot(target);
+ if (now >= t) {
+ missed = true;
+ } else {
+ missed = false;
+
+ // 1) actually set the hardware timer
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+ uint32_t save = spin_lock_blocking(lock);
+ uint8_t old_timer_callbacks_pending = timer_callbacks_pending;
+ timer_callbacks_pending |= (uint8_t)(1u << alarm_num);
+ timer_hw->intr = 1u << alarm_num; // clear any IRQ
+ timer_hw->alarm[alarm_num] = (uint32_t) t;
+ // Set the alarm. Writing time should arm it
+ target_hi[alarm_num] = (uint32_t)(t >> 32u);
+
+ // 2) check for races
+ if (!(timer_hw->armed & 1u << alarm_num)) {
+ // not armed, so has already fired .. IRQ must be pending (we are still under lock)
+ assert(timer_hw->ints & 1u << alarm_num);
+ } else {
+ if (time_us_64() >= t) {
+ // we are already at or past the right time; there is no point in us racing against the IRQ
+ // we are about to generate. note however that, if there was already a timer pending before,
+ // then we still let the IRQ fire, as whatever it was, is not handled by our setting missed=true here
+ missed = true;
+ if (timer_callbacks_pending != old_timer_callbacks_pending) {
+ // disarm the timer
+ timer_hw->armed = 1u << alarm_num;
+ // clear the IRQ...
+ timer_hw->intr = 1u << alarm_num;
+ // ... including anything pending on the processor - perhaps unnecessary, but
+ // our timer flag says we aren't expecting anything.
+ irq_clear(harware_alarm_irq_number(alarm_num));
+ // and clear our flag so that if the IRQ handler is already active (because it is on
+ // the other core) it will also skip doing anything
+ timer_callbacks_pending = old_timer_callbacks_pending;
+ }
+ }
+ }
+ spin_unlock(lock, save);
+ // note at this point any pending timer IRQ can likely run
+ }
+ return missed;
+}
+
+void hardware_alarm_cancel(uint alarm_num) {
+ check_hardware_alarm_num_param(alarm_num);
+
+ spin_lock_t *lock = spin_lock_instance(PICO_SPINLOCK_ID_TIMER);
+ uint32_t save = spin_lock_blocking(lock);
+ timer_hw->armed = 1u << alarm_num;
+ timer_callbacks_pending &= (uint8_t)~(1u << alarm_num);
+ spin_unlock(lock, save);
+}
+
+
diff --git a/arkanoid/pico/hardware/timer.h b/arkanoid/pico/hardware/timer.h
new file mode 100644
index 0000000..e1227f3
--- /dev/null
+++ b/arkanoid/pico/hardware/timer.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_TIMER_H
+#define _HARDWARE_TIMER_H
+
+#include "../pico.h"
+#include "structs/timer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file timer.h
+ * \defgroup hardware_timer hardware_timer
+ *
+ * Low-level hardware timer API
+ *
+ * This API provides medium level access to the timer HW.
+ * See also \ref pico_time which provides higher levels functionality using the hardware timer.
+ *
+ * The timer peripheral on RP2040 supports the following features:
+ * - single 64-bit counter, incrementing once per microsecond
+ * - Latching two-stage read of counter, for race-free read over 32 bit bus
+ * - Four alarms: match on the lower 32 bits of counter, IRQ on match.
+ *
+ * By default the timer uses a one microsecond reference that is generated in the Watchdog (see Section 4.8.2) which is derived
+ * from the clk_ref.
+ *
+ * The timer has 4 alarms, and can output a separate interrupt for each alarm. The alarms match on the lower 32 bits of the 64
+ * bit counter which means they can be fired a maximum of 2^32 microseconds into the future. This is equivalent to:
+ * - 2^32 ÷ 10^6: ~4295 seconds
+ * - 4295 ÷ 60: ~72 minutes
+ *
+ * The timer is expected to be used for short sleeps, if you want a longer alarm see the \ref hardware_rtc functions.
+ *
+ * \subsection timer_example Example
+ * \addtogroup hardware_timer
+ *
+ * \include hello_timer.c
+ *
+ * \see pico_time
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIMER, Enable/disable assertions in the timer module, type=bool, default=0, group=hardware_timer
+#ifndef PARAM_ASSERTIONS_ENABLED_TIMER
+#define PARAM_ASSERTIONS_ENABLED_TIMER 0
+#endif
+
+static inline void check_hardware_alarm_num_param(__unused uint alarm_num) {
+ invalid_params_if(TIMER, alarm_num >= NUM_TIMERS);
+}
+
+/*! \brief Return a 32 bit timestamp value in microseconds
+* \ingroup hardware_timer
+*
+* Returns the low 32 bits of the hardware timer.
+* \note This value wraps roughly every 1 hour 11 minutes and 35 seconds.
+*
+* \return the 32 bit timestamp
+*/
+static inline uint32_t time_us_32(void) {
+ return timer_hw->timerawl;
+}
+
+/*! \brief Return the current 64 bit timestamp value in microseconds
+* \ingroup hardware_timer
+*
+* Returns the full 64 bits of the hardware timer. The \ref pico_time and other functions rely on the fact that this
+* value monotonically increases from power up. As such it is expected that this value counts upwards and never wraps
+* (we apologize for introducing a potential year 5851444 bug).
+*
+* \return the 64 bit timestamp
+*/
+uint64_t time_us_64(void);
+
+/*! \brief Busy wait wasting cycles for the given (32 bit) number of microseconds
+ * \ingroup hardware_timer
+ *
+ * \param delay_us delay amount in microseconds
+ */
+void busy_wait_us_32(uint32_t delay_us);
+
+/*! \brief Busy wait wasting cycles for the given (64 bit) number of microseconds
+ * \ingroup hardware_timer
+ *
+ * \param delay_us delay amount in microseconds
+ */
+void busy_wait_us(uint64_t delay_us);
+
+/*! \brief Busy wait wasting cycles for the given number of milliseconds
+ * \ingroup hardware_timer
+ *
+ * \param delay_ms delay amount in milliseconds
+ */
+void busy_wait_ms(uint32_t delay_ms);
+
+/*! \brief Busy wait wasting cycles until after the specified timestamp
+ * \ingroup hardware_timer
+ *
+ * \param t Absolute time to wait until
+ */
+void busy_wait_until(absolute_time_t t);
+
+/*! \brief Check if the specified timestamp has been reached
+ * \ingroup hardware_timer
+ *
+ * \param t Absolute time to compare against current time
+ * \return true if it is now after the specified timestamp
+ */
+static inline bool time_reached(absolute_time_t t) {
+ uint64_t target = to_us_since_boot(t);
+ uint32_t hi_target = (uint32_t)(target >> 32u);
+ uint32_t hi = timer_hw->timerawh;
+ return (hi >= hi_target && (timer_hw->timerawl >= (uint32_t) target || hi != hi_target));
+}
+
+/*! Callback function type for hardware alarms
+ * \ingroup hardware_timer
+ *
+ * \param alarm_num the hardware alarm number
+ * \sa hardware_alarm_set_callback()
+ */
+typedef void (*hardware_alarm_callback_t)(uint alarm_num);
+
+/*! \brief cooperatively claim the use of this hardware alarm_num
+ * \ingroup hardware_timer
+ *
+ * This method hard asserts if the hardware alarm is currently claimed.
+ *
+ * \param alarm_num the hardware alarm to claim
+ * \sa hardware_claiming
+ */
+void hardware_alarm_claim(uint alarm_num);
+
+/*! \brief cooperatively release the claim on use of this hardware alarm_num
+ * \ingroup hardware_timer
+ *
+ * \param alarm_num the hardware alarm to unclaim
+ * \sa hardware_claiming
+ */
+void hardware_alarm_unclaim(uint alarm_num);
+
+/*! \brief Determine if a hardware alarm has been claimed
+ * \ingroup hardware_timer
+ *
+ * \param alarm_num the hardware alarm number
+ * \return true if claimed, false otherwise
+ * \see hardware_alarm_claim
+ */
+bool hardware_alarm_is_claimed(uint alarm_num);
+
+/*! \brief Enable/Disable a callback for a hardware timer on this core
+ * \ingroup hardware_timer
+ *
+ * This method enables/disables the alarm IRQ for the specified hardware alarm on the
+ * calling core, and set the specified callback to be associated with that alarm.
+ *
+ * This callback will be used for the timeout set via hardware_alarm_set_target
+ *
+ * \note This will install the handler on the current core if the IRQ handler isn't already set.
+ * Therefore the user has the opportunity to call this up from the core of their choice
+ *
+ * \param alarm_num the hardware alarm number
+ * \param callback the callback to install, or NULL to unset
+ *
+ * \sa hardware_alarm_set_target()
+ */
+void hardware_alarm_set_callback(uint alarm_num, hardware_alarm_callback_t callback);
+
+/**
+ * \brief Set the current target for the specified hardware alarm
+ * \ingroup hardware_timer
+ *
+ * This will replace any existing target
+ *
+ * @param alarm_num the hardware alarm number
+ * @param t the target timestamp
+ * @return true if the target was "missed"; i.e. it was in the past, or occurred before a future hardware timeout could be set
+ */
+bool hardware_alarm_set_target(uint alarm_num, absolute_time_t t);
+
+/**
+ * \brief Cancel an existing target (if any) for a given hardware_alarm
+ * \ingroup hardware_timer
+ *
+ * @param alarm_num
+ */
+
+void hardware_alarm_cancel(uint alarm_num);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/hardware/uart.c b/arkanoid/pico/hardware/uart.c
new file mode 100644
index 0000000..9c28eb4
--- /dev/null
+++ b/arkanoid/pico/hardware/uart.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "address_mapped.h"
+#include "platform_defs.h"
+#include "uart.h"
+
+#include "structs/uart.h"
+#include "resets.h"
+#include "clocks.h"
+#include "timer.h"
+
+#include "assert.h"
+#include "../pico.h"
+
+check_hw_layout(uart_hw_t, fr, UART_UARTFR_OFFSET);
+check_hw_layout(uart_hw_t, dmacr, UART_UARTDMACR_OFFSET);
+
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+short uart_char_to_line_feed[NUM_UARTS];
+#endif
+
+/// \tag::uart_reset[]
+static inline void uart_reset(uart_inst_t *uart) {
+ invalid_params_if(UART, uart != uart0 && uart != uart1);
+ reset_block(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS);
+}
+
+static inline void uart_unreset(uart_inst_t *uart) {
+ invalid_params_if(UART, uart != uart0 && uart != uart1);
+ unreset_block_wait(uart_get_index(uart) ? RESETS_RESET_UART1_BITS : RESETS_RESET_UART0_BITS);
+}
+/// \end::uart_reset[]
+
+/// \tag::uart_init[]
+uint uart_init(uart_inst_t *uart, uint baudrate) {
+ invalid_params_if(UART, uart != uart0 && uart != uart1);
+
+ if (clock_get_hz(clk_peri) == 0)
+ return 0;
+
+ uart_reset(uart);
+ uart_unreset(uart);
+
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+ uart_set_translate_crlf(uart, PICO_UART_DEFAULT_CRLF);
+#endif
+
+ // Any LCR writes need to take place before enabling the UART
+ uint baud = uart_set_baudrate(uart, baudrate);
+ uart_set_format(uart, 8, 1, UART_PARITY_NONE);
+
+ // Enable the UART, both TX and RX
+ uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | UART_UARTCR_RXE_BITS;
+ // Enable FIFOs
+ hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS);
+ // Always enable DREQ signals -- no harm in this if DMA is not listening
+ uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS;
+
+ return baud;
+}
+/// \end::uart_init[]
+
+void uart_deinit(uart_inst_t *uart) {
+ invalid_params_if(UART, uart != uart0 && uart != uart1);
+ uart_reset(uart);
+}
+
+/// \tag::uart_set_baudrate[]
+uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) {
+ invalid_params_if(UART, baudrate == 0);
+ uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate);
+ uint32_t baud_ibrd = baud_rate_div >> 7;
+ uint32_t baud_fbrd;
+
+ if (baud_ibrd == 0) {
+ baud_ibrd = 1;
+ baud_fbrd = 0;
+ } else if (baud_ibrd >= 65535) {
+ baud_ibrd = 65535;
+ baud_fbrd = 0;
+ } else {
+ baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
+ }
+
+ // Load PL011's baud divisor registers
+ uart_get_hw(uart)->ibrd = baud_ibrd;
+ uart_get_hw(uart)->fbrd = baud_fbrd;
+
+ // PL011 needs a (dummy) line control register write to latch in the
+ // divisors. We don't want to actually change LCR contents here.
+ hw_set_bits(&uart_get_hw(uart)->lcr_h, 0);
+
+ // See datasheet
+ return (4 * clock_get_hz(clk_peri)) / (64 * baud_ibrd + baud_fbrd);
+}
+/// \end::uart_set_baudrate[]
+
+void uart_set_translate_crlf(uart_inst_t *uart, bool crlf) {
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+ uart_char_to_line_feed[uart_get_index(uart)] = crlf ? '\n' : 0x100;
+#else
+ panic_unsupported();
+#endif
+}
+
+bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us) {
+ uint32_t t = time_us_32();
+ do {
+ if (uart_is_readable(uart)) return true;
+ } while ((time_us_32() - t) <= us);
+ return false;
+}
diff --git a/arkanoid/pico/hardware/uart.h b/arkanoid/pico/hardware/uart.h
new file mode 100644
index 0000000..d1fd217
--- /dev/null
+++ b/arkanoid/pico/hardware/uart.h
@@ -0,0 +1,453 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_UART_H
+#define _HARDWARE_UART_H
+
+#include "../pico.h"
+#include "structs/uart.h"
+#include "regs/dreq.h"
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_UART, Enable/disable assertions in the UART module, type=bool, default=0, group=hardware_uart
+#ifndef PARAM_ASSERTIONS_ENABLED_UART
+#define PARAM_ASSERTIONS_ENABLED_UART 0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PICO_UART_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF translation support, type=bool, default=1, group=hardware_uart
+#ifndef PICO_UART_ENABLE_CRLF_SUPPORT
+#define PICO_UART_ENABLE_CRLF_SUPPORT 1
+#endif
+
+// PICO_CONFIG: PICO_UART_DEFAULT_CRLF, Enable/disable CR/LF translation on UART, type=bool, default=0, depends=PICO_UART_ENABLE_CRLF_SUPPORT, group=hardware_uart
+#ifndef PICO_UART_DEFAULT_CRLF
+#define PICO_UART_DEFAULT_CRLF 0
+#endif
+
+// PICO_CONFIG: PICO_DEFAULT_UART, Define the default UART used for printf etc, min=0, max=1, group=hardware_uart
+// PICO_CONFIG: PICO_DEFAULT_UART_TX_PIN, Define the default UART TX pin, min=0, max=29, group=hardware_uart
+// PICO_CONFIG: PICO_DEFAULT_UART_RX_PIN, Define the default UART RX pin, min=0, max=29, group=hardware_uart
+
+// PICO_CONFIG: PICO_DEFAULT_UART_BAUD_RATE, Define the default UART baudrate, max=921600, default=115200, group=hardware_uart
+#ifndef PICO_DEFAULT_UART_BAUD_RATE
+#define PICO_DEFAULT_UART_BAUD_RATE 115200 ///< Default baud rate
+#endif
+
+/** \file uart.h
+ * \defgroup hardware_uart hardware_uart
+ *
+ * Hardware UART API
+ *
+ * RP2040 has 2 identical instances of a UART peripheral, based on the ARM PL011. Each UART can be connected to a number
+ * of GPIO pins as defined in the GPIO muxing.
+ *
+ * Only the TX, RX, RTS, and CTS signals are
+ * connected, meaning that the modem mode and IrDA mode of the PL011 are not supported.
+ *
+ * \subsection uart_example Example
+ * \addtogroup hardware_uart
+ *
+ * \code
+ * int main() {
+ *
+ * // Initialise UART 0
+ * uart_init(uart0, 115200);
+ *
+ * // Set the GPIO pin mux to the UART - 0 is TX, 1 is RX
+ * gpio_set_function(0, GPIO_FUNC_UART);
+ * gpio_set_function(1, GPIO_FUNC_UART);
+ *
+ * uart_puts(uart0, "Hello world!");
+ * }
+ * \endcode
+ */
+
+// Currently always a pointer to hw but it might not be in the future
+typedef struct uart_inst uart_inst_t;
+
+/** The UART identifiers for use in UART functions.
+ *
+ * e.g. uart_init(uart1, 48000)
+ *
+ * \ingroup hardware_uart
+ * @{
+ */
+#define uart0 ((uart_inst_t * const)uart0_hw) ///< Identifier for UART instance 0
+#define uart1 ((uart_inst_t * const)uart1_hw) ///< Identifier for UART instance 1
+
+/** @} */
+
+#if !defined(PICO_DEFAULT_UART_INSTANCE) && defined(PICO_DEFAULT_UART)
+#define PICO_DEFAULT_UART_INSTANCE (__CONCAT(uart,PICO_DEFAULT_UART))
+#endif
+
+#ifdef PICO_DEFAULT_UART_INSTANCE
+#define uart_default PICO_DEFAULT_UART_INSTANCE
+#endif
+
+/*! \brief Convert UART instance to hardware instance number
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance
+ * \return Number of UART, 0 or 1.
+ */
+static inline uint uart_get_index(uart_inst_t *uart) {
+ invalid_params_if(UART, uart != uart0 && uart != uart1);
+ return uart == uart1 ? 1 : 0;
+}
+
+static inline uart_inst_t *uart_get_instance(uint instance) {
+ static_assert(NUM_UARTS == 2, "");
+ invalid_params_if(UART, instance >= NUM_UARTS);
+ return instance ? uart1 : uart0;
+}
+
+static inline uart_hw_t *uart_get_hw(uart_inst_t *uart) {
+ uart_get_index(uart); // check it is a hw uart
+ return (uart_hw_t *)uart;
+}
+
+/** \brief UART Parity enumeration
+ * \ingroup hardware_uart
+ */
+typedef enum {
+ UART_PARITY_NONE,
+ UART_PARITY_EVEN,
+ UART_PARITY_ODD
+} uart_parity_t;
+
+// ----------------------------------------------------------------------------
+// Setup
+
+/*! \brief Initialise a UART
+ * \ingroup hardware_uart
+ *
+ * Put the UART into a known state, and enable it. Must be called before other
+ * functions.
+ *
+ * \note There is no guarantee that the baudrate requested will be possible, the nearest will be chosen,
+ * and this function will return the configured baud rate.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param baudrate Baudrate of UART in Hz
+ * \return Actual set baudrate
+ */
+uint uart_init(uart_inst_t *uart, uint baudrate);
+
+/*! \brief DeInitialise a UART
+ * \ingroup hardware_uart
+ *
+ * Disable the UART if it is no longer used. Must be reinitialised before
+ * being used again.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ */
+void uart_deinit(uart_inst_t *uart);
+
+/*! \brief Set UART baud rate
+ * \ingroup hardware_uart
+ *
+ * Set baud rate as close as possible to requested, and return actual rate selected.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param baudrate Baudrate in Hz
+ * \return Actual set baudrate
+ */
+uint uart_set_baudrate(uart_inst_t *uart, uint baudrate);
+
+/*! \brief Set UART flow control CTS/RTS
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param cts If true enable flow control of TX by clear-to-send input
+ * \param rts If true enable assertion of request-to-send output by RX flow control
+ */
+static inline void uart_set_hw_flow(uart_inst_t *uart, bool cts, bool rts) {
+ hw_write_masked(&uart_get_hw(uart)->cr,
+ (bool_to_bit(cts) << UART_UARTCR_CTSEN_LSB) | (bool_to_bit(rts) << UART_UARTCR_RTSEN_LSB),
+ UART_UARTCR_RTSEN_BITS | UART_UARTCR_CTSEN_BITS);
+}
+
+/*! \brief Set UART data format
+ * \ingroup hardware_uart
+ *
+ * Configure the data format (bits etc() for the UART
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param data_bits Number of bits of data. 5..8
+ * \param stop_bits Number of stop bits 1..2
+ * \param parity Parity option.
+ */
+static inline void uart_set_format(uart_inst_t *uart, uint data_bits, uint stop_bits, uart_parity_t parity) {
+ invalid_params_if(UART, data_bits < 5 || data_bits > 8);
+ invalid_params_if(UART, stop_bits != 1 && stop_bits != 2);
+ invalid_params_if(UART, parity != UART_PARITY_NONE && parity != UART_PARITY_EVEN && parity != UART_PARITY_ODD);
+ hw_write_masked(&uart_get_hw(uart)->lcr_h,
+ ((data_bits - 5u) << UART_UARTLCR_H_WLEN_LSB) |
+ ((stop_bits - 1u) << UART_UARTLCR_H_STP2_LSB) |
+ (bool_to_bit(parity != UART_PARITY_NONE) << UART_UARTLCR_H_PEN_LSB) |
+ (bool_to_bit(parity == UART_PARITY_EVEN) << UART_UARTLCR_H_EPS_LSB),
+ UART_UARTLCR_H_WLEN_BITS |
+ UART_UARTLCR_H_STP2_BITS |
+ UART_UARTLCR_H_PEN_BITS |
+ UART_UARTLCR_H_EPS_BITS);
+}
+
+/*! \brief Setup UART interrupts
+ * \ingroup hardware_uart
+ *
+ * Enable the UART's interrupt output. An interrupt handler will need to be installed prior to calling
+ * this function.
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param rx_has_data If true an interrupt will be fired when the RX FIFO contains data.
+ * \param tx_needs_data If true an interrupt will be fired when the TX FIFO needs data.
+ */
+static inline void uart_set_irq_enables(uart_inst_t *uart, bool rx_has_data, bool tx_needs_data) {
+ // Both UARTRXINTR (RX) and UARTRTINTR (RX timeout) interrupts are
+ // required for rx_has_data. RX asserts when >=4 characters are in the RX
+ // FIFO (for RXIFLSEL=0). RT asserts when there are >=1 characters and no
+ // more have been received for 32 bit periods.
+ uart_get_hw(uart)->imsc = (bool_to_bit(tx_needs_data) << UART_UARTIMSC_TXIM_LSB) |
+ (bool_to_bit(rx_has_data) << UART_UARTIMSC_RXIM_LSB) |
+ (bool_to_bit(rx_has_data) << UART_UARTIMSC_RTIM_LSB);
+ if (rx_has_data) {
+ // Set minimum threshold
+ hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_RXIFLSEL_LSB,
+ UART_UARTIFLS_RXIFLSEL_BITS);
+ }
+ if (tx_needs_data) {
+ // Set maximum threshold
+ hw_write_masked(&uart_get_hw(uart)->ifls, 0 << UART_UARTIFLS_TXIFLSEL_LSB,
+ UART_UARTIFLS_TXIFLSEL_BITS);
+ }
+}
+
+/*! \brief Test if specific UART is enabled
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return true if the UART is enabled
+ */
+static inline bool uart_is_enabled(uart_inst_t *uart) {
+ return !!(uart_get_hw(uart)->cr & UART_UARTCR_UARTEN_BITS);
+}
+
+/*! \brief Enable/Disable the FIFOs on specified UART
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param enabled true to enable FIFO (default), false to disable
+ */
+static inline void uart_set_fifo_enabled(uart_inst_t *uart, bool enabled) {
+ hw_write_masked(&uart_get_hw(uart)->lcr_h,
+ (bool_to_bit(enabled) << UART_UARTLCR_H_FEN_LSB),
+ UART_UARTLCR_H_FEN_BITS);
+}
+
+
+// ----------------------------------------------------------------------------
+// Generic input/output
+
+/*! \brief Determine if space is available in the TX FIFO
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return false if no space available, true otherwise
+ */
+static inline bool uart_is_writable(uart_inst_t *uart) {
+ return !(uart_get_hw(uart)->fr & UART_UARTFR_TXFF_BITS);
+}
+
+/*! \brief Wait for the UART TX fifo to be drained
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ */
+static inline void uart_tx_wait_blocking(uart_inst_t *uart) {
+ while (uart_get_hw(uart)->fr & UART_UARTFR_BUSY_BITS) tight_loop_contents();
+}
+
+/*! \brief Determine whether data is waiting in the RX FIFO
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return 0 if no data available, otherwise the number of bytes, at least, that can be read
+ *
+ * \note HW limitations mean this function will return either 0 or 1.
+ */
+static inline bool uart_is_readable(uart_inst_t *uart) {
+ // PL011 doesn't expose levels directly, so return values are only 0 or 1
+ return !(uart_get_hw(uart)->fr & UART_UARTFR_RXFE_BITS);
+}
+
+/*! \brief Write to the UART for transmission.
+ * \ingroup hardware_uart
+ *
+ * This function will block until all the data has been sent to the UART
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param src The bytes to send
+ * \param len The number of bytes to send
+ */
+static inline void uart_write_blocking(uart_inst_t *uart, const uint8_t *src, size_t len) {
+ for (size_t i = 0; i < len; ++i) {
+ while (!uart_is_writable(uart))
+ tight_loop_contents();
+ uart_get_hw(uart)->dr = *src++;
+ }
+}
+
+/*! \brief Read from the UART
+ * \ingroup hardware_uart
+ *
+ * This function will block until all the data has been received from the UART
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param dst Buffer to accept received bytes
+ * \param len The number of bytes to receive.
+ */
+static inline void uart_read_blocking(uart_inst_t *uart, uint8_t *dst, size_t len) {
+ for (size_t i = 0; i < len; ++i) {
+ while (!uart_is_readable(uart))
+ tight_loop_contents();
+ *dst++ = (uint8_t) uart_get_hw(uart)->dr;
+ }
+}
+
+// ----------------------------------------------------------------------------
+// UART-specific operations and aliases
+
+/*! \brief Write single character to UART for transmission.
+ * \ingroup hardware_uart
+ *
+ * This function will block until the entire character has been sent
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param c The character to send
+ */
+static inline void uart_putc_raw(uart_inst_t *uart, char c) {
+ uart_write_blocking(uart, (const uint8_t *) &c, 1);
+}
+
+/*! \brief Write single character to UART for transmission, with optional CR/LF conversions
+ * \ingroup hardware_uart
+ *
+ * This function will block until the character has been sent
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param c The character to send
+ */
+static inline void uart_putc(uart_inst_t *uart, char c) {
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+ extern short uart_char_to_line_feed[NUM_UARTS];
+ if (uart_char_to_line_feed[uart_get_index(uart)] == c)
+ uart_putc_raw(uart, '\r');
+#endif
+ uart_putc_raw(uart, c);
+}
+
+/*! \brief Write string to UART for transmission, doing any CR/LF conversions
+ * \ingroup hardware_uart
+ *
+ * This function will block until the entire string has been sent
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param s The null terminated string to send
+ */
+static inline void uart_puts(uart_inst_t *uart, const char *s) {
+#if PICO_UART_ENABLE_CRLF_SUPPORT
+ bool last_was_cr = false;
+ while (*s) {
+ // Don't add extra carriage returns if one is present
+ if (last_was_cr)
+ uart_putc_raw(uart, *s);
+ else
+ uart_putc(uart, *s);
+ last_was_cr = *s++ == '\r';
+ }
+#else
+ while (*s)
+ uart_putc(uart, *s++);
+#endif
+}
+
+/*! \brief Read a single character to UART
+ * \ingroup hardware_uart
+ *
+ * This function will block until the character has been read
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \return The character read.
+ */
+static inline char uart_getc(uart_inst_t *uart) {
+ char c;
+ uart_read_blocking(uart, (uint8_t *) &c, 1);
+ return c;
+}
+
+/*! \brief Assert a break condition on the UART transmission.
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param en Assert break condition (TX held low) if true. Clear break condition if false.
+ */
+static inline void uart_set_break(uart_inst_t *uart, bool en) {
+ if (en)
+ hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_BRK_BITS);
+ else
+ hw_clear_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_BRK_BITS);
+}
+
+/*! \brief Set CR/LF conversion on UART
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param translate If true, convert line feeds to carriage return on transmissions
+ */
+void uart_set_translate_crlf(uart_inst_t *uart, bool translate);
+
+/*! \brief Wait for the default UART's TX FIFO to be drained
+ * \ingroup hardware_uart
+ */
+static inline void uart_default_tx_wait_blocking(void) {
+#ifdef uart_default
+ uart_tx_wait_blocking(uart_default);
+#else
+ assert(false);
+#endif
+}
+
+/*! \brief Wait for up to a certain number of microseconds for the RX FIFO to be non empty
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param us the number of microseconds to wait at most (may be 0 for an instantaneous check)
+ * \return true if the RX FIFO became non empty before the timeout, false otherwise
+ */
+bool uart_is_readable_within_us(uart_inst_t *uart, uint32_t us);
+
+/*! \brief Return the DREQ to use for pacing transfers to/from a particular UART instance
+ * \ingroup hardware_uart
+ *
+ * \param uart UART instance. \ref uart0 or \ref uart1
+ * \param is_tx true for sending data to the UART instance, false for receiving data from the UART instance
+ */
+static inline uint uart_get_dreq(uart_inst_t *uart, bool is_tx) {
+ static_assert(DREQ_UART0_RX == DREQ_UART0_TX + 1, "");
+ static_assert(DREQ_UART1_RX == DREQ_UART1_TX + 1, "");
+ static_assert(DREQ_UART1_TX == DREQ_UART0_TX + 2, "");
+ return DREQ_UART0_TX + uart_get_index(uart) * 2 + !is_tx;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/vreg.c b/arkanoid/pico/hardware/vreg.c
new file mode 100644
index 0000000..76982ca
--- /dev/null
+++ b/arkanoid/pico/hardware/vreg.c
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../pico.h"
+#include "vreg.h"
+
+void vreg_set_voltage(enum vreg_voltage voltage) {
+ hw_write_masked(&vreg_and_chip_reset_hw->vreg, ((uint)voltage) << VREG_AND_CHIP_RESET_VREG_VSEL_LSB, VREG_AND_CHIP_RESET_VREG_VSEL_BITS);
+}
diff --git a/arkanoid/pico/hardware/vreg.h b/arkanoid/pico/hardware/vreg.h
new file mode 100644
index 0000000..741ab9f
--- /dev/null
+++ b/arkanoid/pico/hardware/vreg.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_VREG_H_
+#define _HARDWARE_VREG_H_
+
+#include "../pico.h"
+#include "structs/vreg_and_chip_reset.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file vreg.h
+ * \defgroup hardware_vreg hardware_vreg
+ *
+ * Voltage Regulation API
+ *
+ */
+
+/** Possible voltage values that can be applied to the regulator
+ */
+enum vreg_voltage {
+ VREG_VOLTAGE_0_85 = 0b0110, ///< 0.85v
+ VREG_VOLTAGE_0_90 = 0b0111, ///< 0.90v
+ VREG_VOLTAGE_0_95 = 0b1000, ///< 0.95v
+ VREG_VOLTAGE_1_00 = 0b1001, ///< 1.00v
+ VREG_VOLTAGE_1_05 = 0b1010, ///< 1.05v
+ VREG_VOLTAGE_1_10 = 0b1011, ///< 1.10v
+ VREG_VOLTAGE_1_15 = 0b1100, ///< 1.15v
+ VREG_VOLTAGE_1_20 = 0b1101, ///< 1.20v
+ VREG_VOLTAGE_1_25 = 0b1110, ///< 1.25v
+ VREG_VOLTAGE_1_30 = 0b1111, ///< 1.30v
+
+ VREG_VOLTAGE_MIN = VREG_VOLTAGE_0_85, ///< Always the minimum possible voltage
+ VREG_VOLTAGE_DEFAULT = VREG_VOLTAGE_1_10, ///< Default voltage on power up.
+ VREG_VOLTAGE_MAX = VREG_VOLTAGE_1_30, ///< Always the maximum possible voltage
+};
+
+
+/*! \brief Set voltage
+ * \ingroup hardware_vreg
+ *
+ * \param voltage The voltage (from enumeration \ref vreg_voltage) to apply to the voltage regulator
+ **/
+void vreg_set_voltage(enum vreg_voltage voltage);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/hardware/watchdog.c b/arkanoid/pico/hardware/watchdog.c
new file mode 100644
index 0000000..f1fc91e
--- /dev/null
+++ b/arkanoid/pico/hardware/watchdog.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+
+#include "watchdog.h"
+#include "structs/watchdog.h"
+#include "structs/psm.h"
+
+/// \tag::watchdog_start_tick[]
+void watchdog_start_tick(uint cycles) {
+ // Important: This function also provides a tick reference to the timer
+ watchdog_hw->tick = cycles | WATCHDOG_TICK_ENABLE_BITS;
+}
+/// \end::watchdog_start_tick[]
+
+// Value to load when updating the watchdog
+
+// tag::watchdog_update[]
+static uint32_t load_value;
+
+void watchdog_update(void) {
+ watchdog_hw->load = load_value;
+}
+// end::watchdog_update[]
+
+uint32_t watchdog_get_count(void) {
+ return (watchdog_hw->ctrl & WATCHDOG_CTRL_TIME_BITS) / 2 ;
+}
+
+// tag::watchdog_enable[]
+// Helper function used by both watchdog_enable and watchdog_reboot
+void _watchdog_enable(uint32_t delay_ms, bool pause_on_debug) {
+ hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+
+ // Reset everything apart from ROSC and XOSC
+ hw_set_bits(&psm_hw->wdsel, PSM_WDSEL_BITS & ~(PSM_WDSEL_ROSC_BITS | PSM_WDSEL_XOSC_BITS));
+
+ uint32_t dbg_bits = WATCHDOG_CTRL_PAUSE_DBG0_BITS |
+ WATCHDOG_CTRL_PAUSE_DBG1_BITS |
+ WATCHDOG_CTRL_PAUSE_JTAG_BITS;
+
+ if (pause_on_debug) {
+ hw_set_bits(&watchdog_hw->ctrl, dbg_bits);
+ } else {
+ hw_clear_bits(&watchdog_hw->ctrl, dbg_bits);
+ }
+
+ if (!delay_ms) {
+ hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_TRIGGER_BITS);
+ } else {
+ // Note, we have x2 here as the watchdog HW currently decrements twice per tick
+ load_value = delay_ms * 1000 * 2;
+
+ if (load_value > 0xffffffu)
+ load_value = 0xffffffu;
+
+ watchdog_update();
+
+ hw_set_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+ }
+}
+// end::watchdog_enable[]
+
+#define WATCHDOG_NON_REBOOT_MAGIC 0x6ab73121
+
+void watchdog_enable(uint32_t delay_ms, bool pause_on_debug) {
+ // update scratch[4] to distinguish from magic used for reboot to specific address, or 0 used to reboot
+ // into regular flash path
+ watchdog_hw->scratch[4] = WATCHDOG_NON_REBOOT_MAGIC;
+ _watchdog_enable(delay_ms, pause_on_debug);
+}
+
+void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms) {
+ check_hw_layout(watchdog_hw_t, scratch[7], WATCHDOG_SCRATCH7_OFFSET);
+
+ // Clear enable before setting up scratch registers
+ hw_clear_bits(&watchdog_hw->ctrl, WATCHDOG_CTRL_ENABLE_BITS);
+
+ if (pc) {
+ pc |= 1u; // thumb mode
+ watchdog_hw->scratch[4] = 0xb007c0d3;
+ watchdog_hw->scratch[5] = pc ^ -0xb007c0d3;
+ watchdog_hw->scratch[6] = sp;
+ watchdog_hw->scratch[7] = pc;
+// printf("rebooting %08x/%08x in %dms...\n", (uint) pc, (uint) sp, (uint) delay_ms);
+ } else {
+ watchdog_hw->scratch[4] = 0;
+// printf("rebooting (regular)) in %dms...\n", (uint) delay_ms);
+ }
+
+ // Don't pause watchdog for debug
+ _watchdog_enable(delay_ms, 0);
+}
+
+bool watchdog_caused_reboot(void) {
+ // If any reason bits are set this is true
+ return watchdog_hw->reason;
+}
+
+bool watchdog_enable_caused_reboot(void) {
+ return watchdog_hw->reason && watchdog_hw->scratch[4] == WATCHDOG_NON_REBOOT_MAGIC;
+}
\ No newline at end of file
diff --git a/arkanoid/pico/hardware/watchdog.h b/arkanoid/pico/hardware/watchdog.h
new file mode 100644
index 0000000..28be52f
--- /dev/null
+++ b/arkanoid/pico/hardware/watchdog.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_WATCHDOG_H
+#define _HARDWARE_WATCHDOG_H
+
+#include "../pico.h"
+#include "structs/watchdog.h"
+
+/** \file watchdog.h
+ * \defgroup hardware_watchdog hardware_watchdog
+ *
+ * Hardware Watchdog Timer API
+ *
+ * Supporting functions for the Pico hardware watchdog timer.
+ *
+ * The RP2040 has a built in HW watchdog Timer. This is a countdown timer that can restart parts of the chip if it reaches zero.
+ * For example, this can be used to restart the processor if the software running on it gets stuck in an infinite loop
+ * or similar. The programmer has to periodically write a value to the watchdog to stop it reaching zero.
+ *
+ * \subsection watchdog_example Example
+ * \addtogroup hardware_watchdog
+ * \include hello_watchdog.c
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Define actions to perform at watchdog timeout
+ * \ingroup hardware_watchdog
+ *
+ * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms
+ * parameter will not be in microseconds. See the datasheet for more details.
+ *
+ * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately.
+ *
+ * \param pc If Zero, a standard boot will be performed, if non-zero this is the program counter to jump to on reset.
+ * \param sp If \p pc is non-zero, this will be the stack pointer used.
+ * \param delay_ms Initial load value. Maximum value 0x7fffff, approximately 8.3s.
+ */
+void watchdog_reboot(uint32_t pc, uint32_t sp, uint32_t delay_ms);
+
+/*! \brief Start the watchdog tick
+ * \ingroup hardware_watchdog
+ *
+ * \param cycles This needs to be a divider that when applied to the XOSC input, produces a 1MHz clock. So if the XOSC is
+ * 12MHz, this will need to be 12.
+ */
+void watchdog_start_tick(uint cycles);
+
+/*! \brief Reload the watchdog counter with the amount of time set in watchdog_enable
+ * \ingroup hardware_watchdog
+ *
+ */
+void watchdog_update(void);
+
+/**
+ * \brief Enable the watchdog
+ * \ingroup hardware_watchdog
+ *
+ * \note If \ref watchdog_start_tick value does not give a 1MHz clock to the watchdog system, then the \p delay_ms
+ * parameter will not be in microseconds. See the datasheet for more details.
+ *
+ * By default the SDK assumes a 12MHz XOSC and sets the \ref watchdog_start_tick appropriately.
+ *
+ * This method sets a marker in the watchdog scratch register 4 that is checked by \ref watchdog_enable_caused_reboot.
+ * If the device is subsequently reset via a call to watchdog_reboot (including for example by dragging a UF2
+ * onto the RPI-RP2), then this value will be cleared, and so \ref watchdog_enable_caused_reboot will
+ * return false.
+ *
+ * \param delay_ms Number of milliseconds before watchdog will reboot without watchdog_update being called. Maximum of 0x7fffff, which is approximately 8.3 seconds
+ * \param pause_on_debug If the watchdog should be paused when the debugger is stepping through code
+ */
+void watchdog_enable(uint32_t delay_ms, bool pause_on_debug);
+
+/**
+ * \brief Did the watchdog cause the last reboot?
+ * \ingroup hardware_watchdog
+ *
+ * @return true If the watchdog timer or a watchdog force caused the last reboot
+ * @return false If there has been no watchdog reboot since the last power on reset. A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled.
+ */
+bool watchdog_caused_reboot(void);
+
+/**
+ * \brief Did watchdog_enable cause the last reboot?
+ * \ingroup hardware_watchdog
+ *
+ * Perform additional checking along with \ref watchdog_caused_reboot to determine if a watchdog timeout initiated by
+ * \ref watchdog_enable caused the last reboot.
+ *
+ * This method checks for a special value in watchdog scratch register 4 placed there by \ref watchdog_enable.
+ * This would not be present if a watchdog reset is initiated by \ref watchdog_reboot or by the RP2040 bootrom
+ * (e.g. dragging a UF2 onto the RPI-RP2 drive).
+ *
+ * @return true If the watchdog timer or a watchdog force caused (see \reg watchdog_caused_reboot) the last reboot
+ * and the watchdog reboot happened after \ref watchdog_enable was called
+ * @return false If there has been no watchdog reboot since the last power on reset, or the watchdog reboot was not caused
+ * by a watchdog timeout after \ref watchdog_enable was called.
+ * A power on reset is typically caused by a power cycle or the run pin (reset button) being toggled.
+ */
+bool watchdog_enable_caused_reboot(void);
+
+/**
+ * @brief Returns the number of microseconds before the watchdog will reboot the chip.
+ * \ingroup hardware_watchdog
+ *
+ * @return The number of microseconds before the watchdog will reboot the chip.
+ */
+uint32_t watchdog_get_count(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/hardware/xosc.c b/arkanoid/pico/hardware/xosc.c
new file mode 100644
index 0000000..0b83ba0
--- /dev/null
+++ b/arkanoid/pico/hardware/xosc.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "../pico.h"
+
+// For MHZ definitions etc
+#include "clocks.h"
+
+#include "platform_defs.h"
+#include "regs/xosc.h"
+#include "xosc.h"
+
+#if XOSC_MHZ < 1 || XOSC_MHZ > 50
+#error XOSC_MHZ must be in the range 1-50
+#endif
+
+#define STARTUP_DELAY (((((XOSC_MHZ * MHZ) / 1000) + 128) / 256) * PICO_XOSC_STARTUP_DELAY_MULTIPLIER)
+
+// The DELAY field in xosc_hw->startup is 14 bits wide.
+#if STARTUP_DELAY >= (1 << 13)
+#error PICO_XOSC_STARTUP_DELAY_MULTIPLIER is too large: XOSC STARTUP.DELAY must be < 8192
+#endif
+
+void xosc_init(void) {
+ // Assumes 1-15 MHz input, checked above.
+ xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ;
+
+ // Set xosc startup delay
+ xosc_hw->startup = STARTUP_DELAY;
+
+ // Set the enable bit now that we have set freq range and startup delay
+ hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE << XOSC_CTRL_ENABLE_LSB);
+
+ // Wait for XOSC to be stable
+ while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS));
+}
+
+void xosc_disable(void) {
+ uint32_t tmp = xosc_hw->ctrl;
+ tmp &= (~XOSC_CTRL_ENABLE_BITS);
+ tmp |= (XOSC_CTRL_ENABLE_VALUE_DISABLE << XOSC_CTRL_ENABLE_LSB);
+ xosc_hw->ctrl = tmp;
+ // Wait for stable to go away
+ while(xosc_hw->status & XOSC_STATUS_STABLE_BITS);
+}
+
+void xosc_dormant(void) {
+ // WARNING: This stops the xosc until woken up by an irq
+ xosc_hw->dormant = XOSC_DORMANT_VALUE_DORMANT;
+ // Wait for it to become stable once woken up
+ while(!(xosc_hw->status & XOSC_STATUS_STABLE_BITS));
+}
diff --git a/arkanoid/pico/hardware/xosc.h b/arkanoid/pico/hardware/xosc.h
new file mode 100644
index 0000000..2a77581
--- /dev/null
+++ b/arkanoid/pico/hardware/xosc.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _HARDWARE_XOSC_H_
+#define _HARDWARE_XOSC_H_
+
+#include "../pico.h"
+#include "structs/xosc.h"
+
+
+// Allow lengthening startup delay to accommodate slow-starting oscillators
+
+// PICO_CONFIG: PICO_XOSC_STARTUP_DELAY_MULTIPLIER, Multiplier to lengthen xosc startup delay to accommodate slow-starting oscillators, type=int, min=1, default=1, group=hardware_xosc
+#ifndef PICO_XOSC_STARTUP_DELAY_MULTIPLIER
+#define PICO_XOSC_STARTUP_DELAY_MULTIPLIER 1
+#endif
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file xosc.h
+ * \defgroup hardware_xosc hardware_xosc
+ *
+ * Crystal Oscillator (XOSC) API
+ */
+
+/*! \brief Initialise the crystal oscillator system
+ * \ingroup hardware_xosc
+ *
+ * This function will block until the crystal oscillator has stabilised.
+ **/
+void xosc_init(void);
+
+/*! \brief Disable the Crystal oscillator
+ * \ingroup hardware_xosc
+ *
+ * Turns off the crystal oscillator source, and waits for it to become unstable
+ **/
+void xosc_disable(void);
+
+/*! \brief Set the crystal oscillator system to dormant
+ * \ingroup hardware_xosc
+ *
+ * Turns off the crystal oscillator until it is woken by an interrupt. This will block and hence
+ * the entire system will stop, until an interrupt wakes it up. This function will
+ * continue to block until the oscillator becomes stable after its wakeup.
+ **/
+void xosc_dormant(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/junk/assert.h b/arkanoid/pico/junk/assert.h
new file mode 100644
index 0000000..8910ebd
--- /dev/null
+++ b/arkanoid/pico/junk/assert.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_ASSERT_H
+#define _PICO_ASSERT_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+
+#include <cassert>
+
+extern "C" {
+#else
+#include <assert.h>
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLE_ALL, Global assert enable, type=bool, default=0, group=pico_base
+// PICO_CONFIG: PARAM_ASSERTIONS_DISABLE_ALL, Global assert disable, type=bool, default=0, group=pico_base
+
+#ifndef PARAM_ASSERTIONS_ENABLE_ALL
+#define PARAM_ASSERTIONS_ENABLE_ALL 0
+#endif
+
+#ifndef PARAM_ASSERTIONS_DISABLE_ALL
+#define PARAM_ASSERTIONS_DISABLE_ALL 0
+#endif
+
+#define PARAM_ASSERTIONS_ENABLED(x) ((PARAM_ASSERTIONS_ENABLED_ ## x || PARAM_ASSERTIONS_ENABLE_ALL) && !PARAM_ASSERTIONS_DISABLE_ALL)
+
+#define invalid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(!(test));})
+#define valid_params_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) assert(test);})
+#define hard_assert_if(x, test) ({if (PARAM_ASSERTIONS_ENABLED(x)) hard_assert(!(test));})
+
+#ifdef NDEBUG
+extern void hard_assertion_failure(void);
+static inline void hard_assert(bool condition, ...) {
+ if (!condition)
+ hard_assertion_failure();
+}
+#else
+#define hard_assert assert
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/junk/config.h b/arkanoid/pico/junk/config.h
new file mode 100644
index 0000000..fbe9c54
--- /dev/null
+++ b/arkanoid/pico/junk/config.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PICO_CONFIG_H_
+#define PICO_CONFIG_H_
+
+// -----------------------------------------------------
+// NOTE: THIS HEADER IS ALSO INCLUDED BY ASSEMBLY CODE SO
+// SHOULD ONLY CONSIST OF PREPROCESSOR DIRECTIVES
+// OR USE #ifndef __ASSEMBLER__ guards
+// -------------
+
+// PICO_CONFIG_HEADER_FILES and then PICO_SDK_<PLATFORM>_CONFIG_INCLUDE_FILES
+// entries are dumped in order at build time into this generated header
+
+#define RASPBERRYPI_PICO
+
+// --- UART ---
+#ifndef PICO_DEFAULT_UART
+#define PICO_DEFAULT_UART 0
+#endif
+#ifndef PICO_DEFAULT_UART_TX_PIN
+#define PICO_DEFAULT_UART_TX_PIN 0
+#endif
+#ifndef PICO_DEFAULT_UART_RX_PIN
+#define PICO_DEFAULT_UART_RX_PIN 1
+#endif
+
+// --- LED ---
+#ifndef PICO_DEFAULT_LED_PIN
+#define PICO_DEFAULT_LED_PIN 25
+#endif
+// no PICO_DEFAULT_WS2812_PIN
+
+// --- I2C ---
+#ifndef PICO_DEFAULT_I2C
+#define PICO_DEFAULT_I2C 0
+#endif
+#ifndef PICO_DEFAULT_I2C_SDA_PIN
+#define PICO_DEFAULT_I2C_SDA_PIN 4
+#endif
+#ifndef PICO_DEFAULT_I2C_SCL_PIN
+#define PICO_DEFAULT_I2C_SCL_PIN 5
+#endif
+
+// --- SPI ---
+#ifndef PICO_DEFAULT_SPI
+#define PICO_DEFAULT_SPI 0
+#endif
+#ifndef PICO_DEFAULT_SPI_SCK_PIN
+#define PICO_DEFAULT_SPI_SCK_PIN 18
+#endif
+#ifndef PICO_DEFAULT_SPI_TX_PIN
+#define PICO_DEFAULT_SPI_TX_PIN 19
+#endif
+#ifndef PICO_DEFAULT_SPI_RX_PIN
+#define PICO_DEFAULT_SPI_RX_PIN 16
+#endif
+#ifndef PICO_DEFAULT_SPI_CSN_PIN
+#define PICO_DEFAULT_SPI_CSN_PIN 17
+#endif
+
+// --- FLASH ---
+
+#define PICO_BOOT_STAGE2_CHOOSE_W25Q080 1
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 2
+#endif
+
+#ifndef PICO_FLASH_SIZE_BYTES
+#define PICO_FLASH_SIZE_BYTES (2 * 1024 * 1024)
+#endif
+
+// Drive high to force power supply into PWM mode (lower ripple on 3V3 at light loads)
+#define PICO_SMPS_MODE_PIN 23
+
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 1
+#endif
+
+
+#if LIB_CMSIS_CORE
+// PICO_CONFIG: PICO_CMSIS_RENAME_EXCEPTIONS, Whether to rename SDK exceptions such as isr_nmi to their CMSIS equivalent i.e. NMI_Handler, type=bool, default=1, group=cmsis_core
+
+// Note that since this header is included at the config stage, if you wish to override this you should do so via build compiler define
+#ifndef PICO_CMSIS_RENAME_EXCEPTIONS
+#define PICO_CMSIS_RENAME_EXCEPTIONS 1
+#endif
+
+#if PICO_CMSIS_RENAME_EXCEPTIONS
+#define isr_nmi NMI_Handler
+#define isr_hardfault HardFault_Handler
+#define isr_svcall SVC_Handler
+#define isr_pendsv PendSV_Handler
+#define isr_systick SysTick_Handler
+#define isr_irq0 TIMER_IRQ_0_Handler
+#define isr_irq1 TIMER_IRQ_1_Handler
+#define isr_irq2 TIMER_IRQ_2_Handler
+#define isr_irq3 TIMER_IRQ_3_Handler
+#define isr_irq4 PWM_IRQ_WRAP_Handler
+#define isr_irq5 USBCTRL_IRQ_Handler
+#define isr_irq6 XIP_IRQ_Handler
+#define isr_irq7 PIO0_IRQ_0_Handler
+#define isr_irq8 PIO0_IRQ_1_Handler
+#define isr_irq9 PIO1_IRQ_0_Handler
+#define isr_irq10 PIO1_IRQ_1_Handler
+#define isr_irq11 DMA_IRQ_0_Handler
+#define isr_irq12 DMA_IRQ_1_Handler
+#define isr_irq13 IO_IRQ_BANK0_Handler
+#define isr_irq14 IO_IRQ_QSPI_Handler
+#define isr_irq15 SIO_IRQ_PROC0_Handler
+#define isr_irq16 SIO_IRQ_PROC1_Handler
+#define isr_irq17 CLOCKS_IRQ_Handler
+#define isr_irq18 SPI0_IRQ_Handler
+#define isr_irq19 SPI1_IRQ_Handler
+#define isr_irq20 UART0_IRQ_Handler
+#define isr_irq21 UART1_IRQ_Handler
+#define isr_irq22 ADC_IRQ_FIFO_Handler
+#define isr_irq23 I2C0_IRQ_Handler
+#define isr_irq24 I2C1_IRQ_Handler
+#define isr_irq25 RTC_IRQ_Handler
+#endif
+
+#endif
+
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/junk/error.h b/arkanoid/pico/junk/error.h
new file mode 100644
index 0000000..fadb45e
--- /dev/null
+++ b/arkanoid/pico/junk/error.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_ERROR_H
+#define _PICO_ERROR_H
+
+#ifndef __ASSEMBLER__
+
+/*!
+ * Common return codes from pico_sdk methods that return a status
+ */
+enum {
+ PICO_OK = 0,
+ PICO_ERROR_NONE = 0,
+ PICO_ERROR_TIMEOUT = -1,
+ PICO_ERROR_GENERIC = -2,
+ PICO_ERROR_NO_DATA = -3,
+};
+
+#endif // !__ASSEMBLER__
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/junk/types.h b/arkanoid/pico/junk/types.h
new file mode 100644
index 0000000..d052052
--- /dev/null
+++ b/arkanoid/pico/junk/types.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_TYPES_H
+#define _PICO_TYPES_H
+
+#ifndef __ASSEMBLER__
+
+#include "assert.h"
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+typedef unsigned int uint;
+
+/*! \typedef absolute_time_t
+ \brief An opaque 64 bit timestamp in microseconds
+
+ The type is used instead of a raw uint64_t to prevent accidentally passing relative times or times in the wrong
+ time units where an absolute time is required. It is equivalent to uint64_t in release builds.
+
+ \see to_us_since_boot()
+ \see update_us_since_boot()
+ \ingroup timestamp
+*/
+#ifdef NDEBUG
+typedef uint64_t absolute_time_t;
+#else
+typedef struct {
+ uint64_t _private_us_since_boot;
+} absolute_time_t;
+#endif
+
+/*! fn to_us_since_boot
+ * \brief convert an absolute_time_t into a number of microseconds since boot.
+ * \param t the absolute time to convert
+ * \return a number of microseconds since boot, equivalent to t
+ * \ingroup timestamp
+ */
+static inline uint64_t to_us_since_boot(absolute_time_t t) {
+#ifdef NDEBUG
+ return t;
+#else
+ return t._private_us_since_boot;
+#endif
+}
+
+/*! fn update_us_since_boot
+ * \brief update an absolute_time_t value to represent a given number of microseconds since boot
+ * \param t the absolute time value to update
+ * \param us_since_boot the number of microseconds since boot to represent. Note this should be representable
+ * as a signed 64 bit integer
+ * \ingroup timestamp
+ */
+static inline void update_us_since_boot(absolute_time_t *t, uint64_t us_since_boot) {
+#ifdef NDEBUG
+ *t = us_since_boot;
+#else
+ assert(us_since_boot <= INT64_MAX);
+ t->_private_us_since_boot = us_since_boot;
+#endif
+}
+
+#ifdef NDEBUG
+#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = value
+#else
+#define ABSOLUTE_TIME_INITIALIZED_VAR(name, value) name = {value}
+#endif
+
+/** \struct datetime_t
+ * \ingroup util_datetime
+ * \brief Structure containing date and time information
+ *
+ * When setting an RTC alarm, set a field to -1 tells
+ * the RTC to not match on this field
+ */
+typedef struct {
+ int16_t year; ///< 0..4095
+ int8_t month; ///< 1..12, 1 is January
+ int8_t day; ///< 1..28,29,30,31 depending on month
+ int8_t dotw; ///< 0..6, 0 is Sunday
+ int8_t hour; ///< 0..23
+ int8_t min; ///< 0..59
+ int8_t sec; ///< 0..59
+} datetime_t;
+
+#define bool_to_bit(x) ((uint)!!(x))
+
+#endif
+#endif
diff --git a/arkanoid/pico/junk/version.h b/arkanoid/pico/junk/version.h
new file mode 100644
index 0000000..08fbfb5
--- /dev/null
+++ b/arkanoid/pico/junk/version.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+// ---------------------------------------
+// THIS FILE IS AUTOGENERATED; DO NOT EDIT
+// ---------------------------------------
+
+#ifndef _PICO_VERSION_H
+#define _PICO_VERSION_H
+
+#define PICO_SDK_VERSION_MAJOR ${PICO_SDK_VERSION_MAJOR}
+#define PICO_SDK_VERSION_MINOR ${PICO_SDK_VERSION_MINOR}
+#define PICO_SDK_VERSION_REVISION ${PICO_SDK_VERSION_REVISION}
+#define PICO_SDK_VERSION_STRING "${PICO_SDK_VERSION_STRING}"
+
+#endif
diff --git a/arkanoid/pico/lock_core.c b/arkanoid/pico/lock_core.c
new file mode 100644
index 0000000..80a8343
--- /dev/null
+++ b/arkanoid/pico/lock_core.c
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "lock_core.h"
+
+void lock_init(lock_core_t *core, uint lock_num) {
+ valid_params_if(LOCK_CORE, lock_num < NUM_SPIN_LOCKS);
+ core->spin_lock = spin_lock_instance(lock_num);
+}
+
diff --git a/arkanoid/pico/lock_core.h b/arkanoid/pico/lock_core.h
new file mode 100644
index 0000000..f91b711
--- /dev/null
+++ b/arkanoid/pico/lock_core.h
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_LOCK_CORE_H
+#define _PICO_LOCK_CORE_H
+
+#include "pico.h"
+#include "time.h"
+#include "hardware/sync.h"
+
+/** \file lock_core.h
+ * \defgroup lock_core lock_core
+ * \ingroup pico_sync
+ * \brief base synchronization/lock primitive support
+ *
+ * Most of the pico_sync locking primitives contain a lock_core_t structure member. This currently just holds a spin
+ * lock which is used only to protect the contents of the rest of the structure as part of implementing the synchronization
+ * primitive. As such, the spin_lock member of lock core is never still held on return from any function for the primitive.
+ *
+ * \ref critical_section is an exceptional case in that it does not have a lock_core_t and simply wraps a spin lock, providing
+ * methods to lock and unlock said spin lock.
+ *
+ * lock_core based structures work by locking the spin lock, checking state, and then deciding whether they additionally need to block
+ * or notify when the spin lock is released. In the blocking case, they will wake up again in the future, and try the process again.
+ *
+ * By default the SDK just uses the processors' events via SEV and WEV for notification and blocking as these are sufficient for
+ * cross core, and notification from interrupt handlers. However macros are defined in this file that abstract the wait
+ * and notify mechanisms to allow the SDK locking functions to effectively be used within an RTOS or other environment.
+ *
+ * When implementing an RTOS, it is desirable for the SDK synchronization primitives that wait, to block the calling task (and immediately yield),
+ * and those that notify, to wake a blocked task which isn't on processor. At least the wait macro implementation needs to be atomic with the protecting
+ * spin_lock unlock from the callers point of view; i.e. the task should unlock the spin lock when it starts its wait. Such implementation is
+ * up to the RTOS integration, however the macros are defined such that such operations are always combined into a single call
+ * (so they can be perfomed atomically) even though the default implementation does not need this, as a WFE which starts
+ * following the corresponding SEV is not missed.
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_LOCK_CORE, Enable/disable assertions in the lock core, type=bool, default=0, group=pico_sync
+#ifndef PARAM_ASSERTIONS_ENABLED_LOCK_CORE
+#define PARAM_ASSERTIONS_ENABLED_LOCK_CORE 0
+#endif
+
+/** \file lock_core.h
+ * \ingroup lock_core
+ *
+ * Base implementation for locking primitives protected by a spin lock. The spin lock is only used to protect
+ * access to the remaining lock state (in primitives using lock_core); it is never left locked outside
+ * of the function implementations
+ */
+struct lock_core {
+ // spin lock protecting this lock's state
+ spin_lock_t *spin_lock;
+
+ // note any lock members in containing structures need not be volatile;
+ // they are protected by memory/compiler barriers when gaining and release spin locks
+};
+
+typedef struct lock_core lock_core_t;
+
+/*! \brief Initialise a lock structure
+ * \ingroup lock_core
+ *
+ * Inititalize a lock structure, providing the spin lock number to use for protecting internal state.
+ *
+ * \param core Pointer to the lock_core to initialize
+ * \param lock_num Spin lock number to use for the lock. As the spin lock is only used internally to the locking primitive
+ * method implementations, this does not need to be globally unique, however could suffer contention
+ */
+void lock_init(lock_core_t *core, uint lock_num);
+
+#ifndef lock_owner_id_t
+/*! \brief type to use to store the 'owner' of a lock.
+ * \ingroup lock_core
+ * By default this is int8_t as it only needs to store the core number or -1, however it may be
+ * overridden if a larger type is required (e.g. for an RTOS task id)
+ */
+#define lock_owner_id_t int8_t
+#endif
+
+#ifndef LOCK_INVALID_OWNER_ID
+/*! \brief marker value to use for a lock_owner_id_t which does not refer to any valid owner
+ * \ingroup lock_core
+ */
+#define LOCK_INVALID_OWNER_ID ((lock_owner_id_t)-1)
+#endif
+
+#ifndef lock_get_caller_owner_id
+/*! \brief return the owner id for the caller
+ * \ingroup lock_core
+ * By default this returns the calling core number, but may be overridden (e.g. to return an RTOS task id)
+ */
+#define lock_get_caller_owner_id() ((lock_owner_id_t)get_core_num())
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id)>=0)
+#endif
+#endif
+
+#ifndef lock_is_owner_id_valid
+#define lock_is_owner_id_valid(id) ((id) != LOCK_INVALID_OWNER_ID)
+#endif
+
+#ifndef lock_internal_spin_unlock_with_wait
+/*! \brief Atomically unlock the lock's spin lock, and wait for a notification.
+ * \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify
+ * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify
+ * for the same lock, which completes after this call starts.
+ *
+ * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify
+ * has subsequently been called on the same lock instance, however this method is free to return at _any_ point before that;
+ * this macro is _always_ used in a loop which locks the spin lock, checks the internal locking primitive state and then
+ * waits again if the calling thread should not proceed.
+ *
+ * By default this macro simply unlocks the spin lock, and then performs a WFE, but may be overridden
+ * (e.g. to actually block the RTOS task).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the `PRIMASK`
+ * state when the spin lock was acquire
+ */
+#define lock_internal_spin_unlock_with_wait(lock, save) spin_unlock((lock)->spin_lock, save), __wfe()
+#endif
+
+#ifndef lock_internal_spin_unlock_with_notify
+/*! \brief Atomically unlock the lock's spin lock, and send a notification
+ * \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for this notification to happen during a
+ * lock_internal_spin_unlock_with_wait in a way that that wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up any lock_internal_spin_unlock_with_wait
+ * which started before this call completes.
+ *
+ * In an ideal implementation, this method would wake up only the corresponding lock_internal_spin_unlock_with_wait
+ * that has been called on the same lock instance, however it is free to wake up any of them, as they will check
+ * their condition and then re-wait if necessary/
+ *
+ * By default this macro simply unlocks the spin lock, and then performs a SEV, but may be overridden
+ * (e.g. to actually un-block RTOS task(s)).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK
+ * state when the spin lock was acquire)
+ */
+#define lock_internal_spin_unlock_with_notify(lock, save) spin_unlock((lock)->spin_lock, save), __sev()
+#endif
+
+#ifndef lock_internal_spin_unlock_with_best_effort_wait_or_timeout
+/*! \brief Atomically unlock the lock's spin lock, and wait for a notification or a timeout
+ * \ingroup lock_core
+ *
+ * _Atomic_ here refers to the fact that it should not be possible for a concurrent lock_internal_spin_unlock_with_notify
+ * to insert itself between the spin unlock and this wait in a way that the wait does not see the notification (i.e. causing
+ * a missed notification). In other words this method should always wake up in response to a lock_internal_spin_unlock_with_notify
+ * for the same lock, which completes after this call starts.
+ *
+ * In an ideal implementation, this method would return exactly after the corresponding lock_internal_spin_unlock_with_notify
+ * has subsequently been called on the same lock instance or the timeout has been reached, however this method is free to return
+ * at _any_ point before that; this macro is _always_ used in a loop which locks the spin lock, checks the internal locking
+ * primitive state and then waits again if the calling thread should not proceed.
+ *
+ * By default this simply unlocks the spin lock, and then calls \ref best_effort_wfe_or_timeout
+ * but may be overridden (e.g. to actually block the RTOS task with a timeout).
+ *
+ * \param lock the lock_core for the primitive which needs to block
+ * \param save the uint32_t value that should be passed to spin_unlock when the spin lock is unlocked. (i.e. the PRIMASK
+ * state when the spin lock was acquire)
+ * \param until the \ref absolute_time_t value
+ * \return true if the timeout has been reached
+ */
+#define lock_internal_spin_unlock_with_best_effort_wait_or_timeout(lock, save, until) ({ \
+ spin_unlock((lock)->spin_lock, save); \
+ best_effort_wfe_or_timeout(until); \
+})
+#endif
+
+#ifndef sync_internal_yield_until_before
+/*! \brief yield to other processing until some time before the requested time
+ * \ingroup lock_core
+ *
+ * This method is provided for cases where the caller has no useful work to do
+ * until the specified time.
+ *
+ * By default this method does nothing, however it can be overridden (for example by an
+ * RTOS which is able to block the current task until the scheduler tick before
+ * the given time)
+ *
+ * \param until the \ref absolute_time_t value
+ */
+#define sync_internal_yield_until_before(until) ((void)0)
+#endif
+
+#endif
diff --git a/arkanoid/pico/malloc.h b/arkanoid/pico/malloc.h
new file mode 100644
index 0000000..b4ae2b6
--- /dev/null
+++ b/arkanoid/pico/malloc.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_MALLOC_H
+#define _PICO_MALLOC_H
+
+/** \file malloc.h
+* \defgroup pico_malloc pico_malloc
+*
+* Multi-core safety for malloc, calloc and free
+*
+* This library does not provide any additional functions
+*/
+
+// PICO_CONFIG: PICO_USE_MALLOC_MUTEX, Whether to protect malloc etc with a mutex, type=bool, default=1 with pico_multicore, 0 otherwise, group=pico_malloc
+#if LIB_PICO_MULTICORE && !defined(PICO_USE_MALLOC_MUTEX)
+#define PICO_USE_MALLOC_MUTEX 1
+#endif
+
+// PICO_CONFIG: PICO_MALLOC_PANIC, Enable/disable panic when an allocation failure occurs, type=bool, default=1, group=pico_malloc
+#ifndef PICO_MALLOC_PANIC
+#define PICO_MALLOC_PANIC 1
+#endif
+
+// PICO_CONFIG: PICO_DEBUG_MALLOC, Enable/disable debug printf from malloc, type=bool, default=0, group=pico_malloc
+#ifndef PICO_DEBUG_MALLOC
+#define PICO_DEBUG_MALLOC 0
+#endif
+
+// PICO_CONFIG: PICO_DEBUG_MALLOC_LOW_WATER, Define the lower bound for allocation addresses to be printed by PICO_DEBUG_MALLOC, min=0, default=0, group=pico_malloc
+#ifndef PICO_DEBUG_MALLOC_LOW_WATER
+#define PICO_DEBUG_MALLOC_LOW_WATER 0
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/memmap_default.ld b/arkanoid/pico/memmap_default.ld
new file mode 100644
index 0000000..1bfd652
--- /dev/null
+++ b/arkanoid/pico/memmap_default.ld
@@ -0,0 +1,252 @@
+/* Based on GCC ARM embedded samples.
+ Defines the following symbols for use by code:
+ __exidx_start
+ __exidx_end
+ __etext
+ __data_start__
+ __preinit_array_start
+ __preinit_array_end
+ __init_array_start
+ __init_array_end
+ __fini_array_start
+ __fini_array_end
+ __data_end__
+ __bss_start__
+ __bss_end__
+ __end__
+ end
+ __HeapLimit
+ __StackLimit
+ __StackTop
+ __stack (== StackTop)
+*/
+
+MEMORY
+{
+ FLASH(rx) : ORIGIN = 0x10000000, LENGTH = 2048k
+ RAM(rwx) : ORIGIN = 0x20000000, LENGTH = 256k
+ SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
+ SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
+}
+
+ENTRY(_entry_point)
+
+SECTIONS
+{
+ /* Second stage bootloader is prepended to the image. It must be 256 bytes big
+ and checksummed. It is usually built by the boot_stage2 target
+ in the Raspberry Pi Pico SDK
+ */
+
+ .flash_begin : {
+ __flash_binary_start = .;
+ } > FLASH
+
+ .boot2 : {
+ __boot2_start__ = .;
+ *(.boot2*)
+ __boot2_end__ = .;
+ } > FLASH
+
+ ASSERT(__boot2_end__ - __boot2_start__ == 256,
+ "ERROR: Pico second stage bootloader must be 256 bytes in size")
+
+ /* The second stage will always enter the image at the start of .text.
+ The debugger will use the ELF entry point, which is the _entry_point
+ symbol if present, otherwise defaults to start of .text.
+ This can be used to transfer control back to the bootrom on debugger
+ launches only, to perform proper flash setup.
+ */
+
+ .text : {
+ __logical_binary_start = .;
+ KEEP (*(.vectors))
+ KEEP (*(.binary_info_header))
+ __binary_info_header_end = .;
+ KEEP (*(.reset))
+ /* TODO revisit this now memset/memcpy/float in ROM */
+ /* bit of a hack right now to exclude all floating point and time critical (e.g. memset, memcpy) code from
+ * FLASH ... we will include any thing excluded here in .data below by default */
+ *(.init)
+ *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .text*)
+ *(.fini)
+ /* Pull all c'tors into .text */
+ *crtbegin.o(.ctors)
+ *crtbegin?.o(.ctors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+ *(SORT(.ctors.*))
+ *(.ctors)
+ /* Followed by destructors */
+ *crtbegin.o(.dtors)
+ *crtbegin?.o(.dtors)
+ *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ *(SORT(.dtors.*))
+ *(.dtors)
+
+ *(.eh_frame*)
+ . = ALIGN(4);
+ } > FLASH
+
+ .rodata : {
+ *(EXCLUDE_FILE(*libgcc.a: *libc.a:*lib_a-mem*.o *libm.a:) .rodata*)
+ . = ALIGN(4);
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.flashdata*)))
+ . = ALIGN(4);
+ } > FLASH
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > FLASH
+
+ __exidx_start = .;
+ .ARM.exidx :
+ {
+ *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+ } > FLASH
+ __exidx_end = .;
+
+ /* Machine inspectable binary information */
+ . = ALIGN(4);
+ __binary_info_start = .;
+ .binary_info :
+ {
+ KEEP(*(.binary_info.keep.*))
+ *(.binary_info.*)
+ } > FLASH
+ __binary_info_end = .;
+ . = ALIGN(4);
+
+ /* End of .text-like segments */
+ __etext = .;
+
+ .ram_vector_table (COPY): {
+ *(.ram_vector_table)
+ } > RAM
+
+ .data : {
+ __data_start__ = .;
+ *(vtable)
+
+ *(.time_critical*)
+
+ /* remaining .text and .rodata; i.e. stuff we exclude above because we want it in RAM */
+ *(.text*)
+ . = ALIGN(4);
+ *(.rodata*)
+ . = ALIGN(4);
+
+ *(.data*)
+
+ . = ALIGN(4);
+ *(.after_data.*)
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__mutex_array_start = .);
+ KEEP(*(SORT(.mutex_array.*)))
+ KEEP(*(.mutex_array))
+ PROVIDE_HIDDEN (__mutex_array_end = .);
+
+ . = ALIGN(4);
+ /* preinit data */
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP(*(SORT(.preinit_array.*)))
+ KEEP(*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+
+ . = ALIGN(4);
+ /* init data */
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP(*(SORT(.init_array.*)))
+ KEEP(*(.init_array))
+ PROVIDE_HIDDEN (__init_array_end = .);
+
+ . = ALIGN(4);
+ /* finit data */
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ *(SORT(.fini_array.*))
+ *(.fini_array)
+ PROVIDE_HIDDEN (__fini_array_end = .);
+
+ *(.jcr)
+ . = ALIGN(4);
+ /* All data end */
+ __data_end__ = .;
+ } > RAM AT> FLASH
+
+ .uninitialized_data (COPY): {
+ . = ALIGN(4);
+ *(.uninitialized_data*)
+ } > RAM
+
+ /* Start and end symbols must be word-aligned */
+ .scratch_x : {
+ __scratch_x_start__ = .;
+ *(.scratch_x.*)
+ . = ALIGN(4);
+ __scratch_x_end__ = .;
+ } > SCRATCH_X AT > FLASH
+ __scratch_x_source__ = LOADADDR(.scratch_x);
+
+ .scratch_y : {
+ __scratch_y_start__ = .;
+ *(.scratch_y.*)
+ . = ALIGN(4);
+ __scratch_y_end__ = .;
+ } > SCRATCH_Y AT > FLASH
+ __scratch_y_source__ = LOADADDR(.scratch_y);
+
+ .bss : {
+ . = ALIGN(4);
+ __bss_start__ = .;
+ *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.bss*)))
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ } > RAM
+
+ .heap (COPY):
+ {
+ __end__ = .;
+ end = __end__;
+ *(.heap*)
+ __HeapLimit = .;
+ } > RAM
+
+ /* .stack*_dummy section doesn't contains any symbols. It is only
+ * used for linker to calculate size of stack sections, and assign
+ * values to stack symbols later
+ *
+ * stack1 section may be empty/missing if platform_launch_core1 is not used */
+
+ /* by default we put core 0 stack at the end of scratch Y, so that if core 1
+ * stack is not used then all of SCRATCH_X is free.
+ */
+ .stack1_dummy (COPY):
+ {
+ *(.stack1*)
+ } > SCRATCH_X
+ .stack_dummy (COPY):
+ {
+ *(.stack*)
+ } > SCRATCH_Y
+
+ .flash_end : {
+ __flash_binary_end = .;
+ } > FLASH
+
+ /* stack limit is poorly named, but historically is maximum heap ptr */
+ __StackLimit = ORIGIN(RAM) + LENGTH(RAM);
+ __StackOneTop = ORIGIN(SCRATCH_X) + LENGTH(SCRATCH_X);
+ __StackTop = ORIGIN(SCRATCH_Y) + LENGTH(SCRATCH_Y);
+ __StackOneBottom = __StackOneTop - SIZEOF(.stack1_dummy);
+ __StackBottom = __StackTop - SIZEOF(.stack_dummy);
+ PROVIDE(__stack = __StackTop);
+
+ /* Check if data + heap + stack exceeds RAM limit */
+ ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed")
+
+ ASSERT( __binary_info_header_end - __logical_binary_start <= 256, "Binary info must be in first 256 bytes of the binary")
+ /* todo assert on extra code */
+}
+
diff --git a/arkanoid/pico/multicore.c b/arkanoid/pico/multicore.c
new file mode 100644
index 0000000..7dbecdc
--- /dev/null
+++ b/arkanoid/pico/multicore.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "multicore.h"
+#include "hardware/sync.h"
+#include "hardware/irq.h"
+#include "hardware/structs/scb.h"
+#include "hardware/structs/sio.h"
+#include "hardware/regs/psm.h"
+#include "hardware/claim.h"
+#if PICO_USE_STACK_GUARDS
+#include "runtime.h"
+#endif
+
+static inline void multicore_fifo_push_blocking_inline(uint32_t data) {
+ // We wait for the fifo to have some space
+ while (!multicore_fifo_wready())
+ tight_loop_contents();
+
+ sio_hw->fifo_wr = data;
+
+ // Fire off an event to the other core
+ __sev();
+}
+
+void multicore_fifo_push_blocking(uint32_t data) {
+ multicore_fifo_push_blocking_inline(data);
+}
+
+bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us) {
+ absolute_time_t end_time = make_timeout_time_us(timeout_us);
+ // We wait for the fifo to have some space
+ while (!multicore_fifo_wready()) {
+ tight_loop_contents();
+ if (time_reached(end_time)) return false;
+ }
+
+ sio_hw->fifo_wr = data;
+
+ // Fire off an event to the other core
+ __sev();
+ return true;
+}
+
+static inline uint32_t multicore_fifo_pop_blocking_inline(void) {
+ // If nothing there yet, we wait for an event first,
+ // to try and avoid too much busy waiting
+ while (!multicore_fifo_rvalid())
+ __wfe();
+
+ return sio_hw->fifo_rd;
+}
+
+uint32_t multicore_fifo_pop_blocking() {
+ return multicore_fifo_pop_blocking_inline();
+}
+
+bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out) {
+ absolute_time_t end_time = make_timeout_time_us(timeout_us);
+ // If nothing there yet, we wait for an event first,
+ // to try and avoid too much busy waiting
+ while (!multicore_fifo_rvalid()) {
+ __wfe();
+ if (time_reached(end_time)) return false;
+ }
+
+ *out = sio_hw->fifo_rd;
+ return true;
+}
+
+// Default stack for core1 ... if multicore_launch_core1 is not included then .stack1 section will be garbage collected
+static uint32_t __attribute__((section(".stack1"))) core1_stack[PICO_CORE1_STACK_SIZE / sizeof(uint32_t)];
+
+static void __attribute__ ((naked)) core1_trampoline(void) {
+ __asm("pop {r0, r1, pc}");
+}
+
+int core1_wrapper(int (*entry)(void), void *stack_base) {
+#if PICO_USE_STACK_GUARDS
+ // install core1 stack guard
+ runtime_install_stack_guard(stack_base);
+#else
+ __unused void *ignore = stack_base;
+#endif
+ irq_init_priorities();
+ return (*entry)();
+}
+
+void multicore_reset_core1() {
+ // Use atomic aliases just in case core 1 is also manipulating some PSM state
+ io_rw_32 *power_off = (io_rw_32 *) (PSM_BASE + PSM_FRCE_OFF_OFFSET);
+ io_rw_32 *power_off_set = hw_set_alias(power_off);
+ io_rw_32 *power_off_clr = hw_clear_alias(power_off);
+
+ // Hard-reset core 1.
+ // Reading back confirms the core 1 reset is in the correct state, but also
+ // forces APB IO bridges to fence on any internal store buffering
+ *power_off_set = PSM_FRCE_OFF_PROC1_BITS;
+ while (!(*power_off & PSM_FRCE_OFF_PROC1_BITS)) tight_loop_contents();
+
+ // Bring core 1 back out of reset. It will drain its own mailbox FIFO, then push
+ // a 0 to our mailbox to tell us it has done this.
+ *power_off_clr = PSM_FRCE_OFF_PROC1_BITS;
+}
+
+void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes) {
+ assert(!(stack_size_bytes & 3u));
+ uint32_t *stack_ptr = stack_bottom + stack_size_bytes / sizeof(uint32_t);
+ // push 2 values onto top of stack for core1_trampoline
+ stack_ptr -= 3;
+ stack_ptr[0] = (uintptr_t) entry;
+ stack_ptr[1] = (uintptr_t) stack_bottom;
+ stack_ptr[2] = (uintptr_t) core1_wrapper;
+ multicore_launch_core1_raw(core1_trampoline, stack_ptr, scb_hw->vtor);
+}
+
+void multicore_launch_core1(void (*entry)(void)) {
+ extern uint32_t __StackOneBottom;
+ uint32_t *stack_limit = (uint32_t *) &__StackOneBottom;
+ // hack to reference core1_stack although that pointer is wrong.... core1_stack should always be <= stack_limit, if not boom!
+ uint32_t *stack = core1_stack <= stack_limit ? stack_limit : (uint32_t *) -1;
+ multicore_launch_core1_with_stack(entry, stack, sizeof(core1_stack));
+}
+
+void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table) {
+ // Allow for the fact that the caller may have already enabled the FIFO IRQ for their
+ // own purposes (expecting FIFO content after core 1 is launched). We must disable
+ // the IRQ during the handshake, then restore afterwards.
+ bool enabled = irq_is_enabled(SIO_IRQ_PROC0);
+ irq_set_enabled(SIO_IRQ_PROC0, false);
+
+ // Values to be sent in order over the FIFO from core 0 to core 1
+ //
+ // vector_table is value for VTOR register
+ // sp is initial stack pointer (SP)
+ // entry is the initial program counter (PC) (don't forget to set the thumb bit!)
+ const uint32_t cmd_sequence[] =
+ {0, 0, 1, (uintptr_t) vector_table, (uintptr_t) sp, (uintptr_t) entry};
+
+ uint seq = 0;
+ do {
+ uint cmd = cmd_sequence[seq];
+ // Always drain the READ FIFO (from core 1) before sending a 0
+ if (!cmd) {
+ multicore_fifo_drain();
+ // Execute a SEV as core 1 may be waiting for FIFO space via WFE
+ __sev();
+ }
+ multicore_fifo_push_blocking(cmd);
+ uint32_t response = multicore_fifo_pop_blocking();
+ // Move to next state on correct response (echo-d value) otherwise start over
+ seq = cmd == response ? seq + 1 : 0;
+ } while (seq < count_of(cmd_sequence));
+
+ irq_set_enabled(SIO_IRQ_PROC0, enabled);
+}
+
+#define LOCKOUT_MAGIC_START 0x73a8831eu
+#define LOCKOUT_MAGIC_END (~LOCKOUT_MAGIC_START)
+
+static_assert(SIO_IRQ_PROC1 == SIO_IRQ_PROC0 + 1, "");
+
+static mutex_t lockout_mutex;
+static bool lockout_in_progress;
+
+// note this method is in RAM because lockout is used when writing to flash
+// it only makes inline calls
+static void __isr __not_in_flash_func(multicore_lockout_handler)(void) {
+ multicore_fifo_clear_irq();
+ while (multicore_fifo_rvalid()) {
+ if (sio_hw->fifo_rd == LOCKOUT_MAGIC_START) {
+ uint32_t save = save_and_disable_interrupts();
+ multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_START);
+ while (multicore_fifo_pop_blocking_inline() != LOCKOUT_MAGIC_END) {
+ tight_loop_contents(); // not tight but endless potentially
+ }
+ restore_interrupts(save);
+ multicore_fifo_push_blocking_inline(LOCKOUT_MAGIC_END);
+ }
+ }
+}
+
+static void check_lockout_mutex_init(void) {
+ // use known available lock - we only need it briefly
+ uint32_t save = hw_claim_lock();
+ if (!mutex_is_initialized(&lockout_mutex)) {
+ mutex_init(&lockout_mutex);
+ }
+ hw_claim_unlock(save);
+}
+
+void multicore_lockout_victim_init() {
+ check_lockout_mutex_init();
+ uint core_num = get_core_num();
+ irq_set_exclusive_handler(SIO_IRQ_PROC0 + core_num, multicore_lockout_handler);
+ irq_set_enabled(SIO_IRQ_PROC0 + core_num, true);
+}
+
+static bool multicore_lockout_handshake(uint32_t magic, absolute_time_t until) {
+ uint irq_num = SIO_IRQ_PROC0 + get_core_num();
+ bool enabled = irq_is_enabled(irq_num);
+ if (enabled) irq_set_enabled(irq_num, false);
+ bool rc = false;
+ do {
+ int64_t next_timeout_us = absolute_time_diff_us(get_absolute_time(), until);
+ if (next_timeout_us < 0) {
+ break;
+ }
+ multicore_fifo_push_timeout_us(magic, (uint64_t)next_timeout_us);
+ next_timeout_us = absolute_time_diff_us(get_absolute_time(), until);
+ if (next_timeout_us < 0) {
+ break;
+ }
+ uint32_t word = 0;
+ if (!multicore_fifo_pop_timeout_us((uint64_t)next_timeout_us, &word)) {
+ break;
+ }
+ if (word == magic) {
+ rc = true;
+ }
+ } while (!rc);
+ if (enabled) irq_set_enabled(irq_num, true);
+ return rc;
+}
+
+static bool multicore_lockout_start_block_until(absolute_time_t until) {
+ check_lockout_mutex_init();
+ if (!mutex_enter_block_until(&lockout_mutex, until)) {
+ return false;
+ }
+ hard_assert(!lockout_in_progress);
+ bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_START, until);
+ lockout_in_progress = rc;
+ mutex_exit(&lockout_mutex);
+ return rc;
+}
+
+bool multicore_lockout_start_timeout_us(uint64_t timeout_us) {
+ return multicore_lockout_start_block_until(make_timeout_time_us(timeout_us));
+}
+
+void multicore_lockout_start_blocking() {
+ multicore_lockout_start_block_until(at_the_end_of_time);
+}
+
+static bool multicore_lockout_end_block_until(absolute_time_t until) {
+ assert(mutex_is_initialized(&lockout_mutex));
+ if (!mutex_enter_block_until(&lockout_mutex, until)) {
+ return false;
+ }
+ assert(lockout_in_progress);
+ bool rc = multicore_lockout_handshake(LOCKOUT_MAGIC_END, until);
+ if (rc) {
+ lockout_in_progress = false;
+ }
+ mutex_exit(&lockout_mutex);
+ return rc;
+}
+
+bool multicore_lockout_end_timeout_us(uint64_t timeout_us) {
+ return multicore_lockout_end_block_until(make_timeout_time_us(timeout_us));
+}
+
+void multicore_lockout_end_blocking() {
+ multicore_lockout_end_block_until(at_the_end_of_time);
+}
diff --git a/arkanoid/pico/multicore.h b/arkanoid/pico/multicore.h
new file mode 100644
index 0000000..f5b48ae
--- /dev/null
+++ b/arkanoid/pico/multicore.h
@@ -0,0 +1,310 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_MULTICORE_H
+#define _PICO_MULTICORE_H
+
+#include "junk/types.h"
+#include "sync.h"
+#include "hardware/structs/sio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file multicore.h
+ * \defgroup pico_multicore pico_multicore
+ * Adds support for running code on the second processor core (core 1)
+ *
+ * \subsection multicore_example Example
+ * \addtogroup pico_multicore
+ * \include multicore.c
+*/
+
+// PICO_CONFIG: PICO_CORE1_STACK_SIZE, Stack size for core 1, min=0x100, max=0x10000, default=PICO_STACK_SIZE (0x800), group=pico_multicore
+#ifndef PICO_CORE1_STACK_SIZE
+#ifdef PICO_STACK_SIZE
+#define PICO_CORE1_STACK_SIZE PICO_STACK_SIZE
+#else
+#define PICO_CORE1_STACK_SIZE 0x800
+#endif
+#endif
+
+/*! \brief Reset core 1
+ * \ingroup pico_multicore
+ *
+ * This function can be used to reset core 1 into its initial state (ready for launching code against via \ref multicore_launch_core1 and similar methods)
+ *
+ * \note this function should only be called from core 0
+ */
+void multicore_reset_core1(void);
+
+/*! \brief Run code on core 1
+ * \ingroup pico_multicore
+ *
+ * Wake up (a previously reset) core 1 and enter the given function on core 1 using the default core 1 stack (below core 0 stack).
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
+ *
+ * core 1 will use the same vector table as core 0
+ *
+ * \param entry Function entry point
+ * \see multicore_reset_core1
+ */
+void multicore_launch_core1(void (*entry)(void));
+
+/*! \brief Launch code on core 1 with stack
+ * \ingroup pico_multicore
+ *
+ * Wake up (a previously reset) core 1 and enter the given function on core 1 using the passed stack for core 1
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
+ *
+ * core 1 will use the same vector table as core 0
+ *
+ * \param entry Function entry point
+ * \param stack_bottom The bottom (lowest address) of the stack
+ * \param stack_size_bytes The size of the stack in bytes (must be a multiple of 4)
+ * \see multicore_reset_core1
+ */
+void multicore_launch_core1_with_stack(void (*entry)(void), uint32_t *stack_bottom, size_t stack_size_bytes);
+
+/*! \brief Launch code on core 1 with no stack protection
+ * \ingroup pico_multicore
+ *
+ * Wake up (a previously reset) core 1 and start it executing with a specific entry point, stack pointer
+ * and vector table.
+ *
+ * This is a low level function that does not provide a stack guard even if USE_STACK_GUARDS is defined
+ *
+ * core 1 must previously have been reset either as a result of a system reset or by calling \ref multicore_reset_core1
+ *
+ * \param entry Function entry point
+ * \param sp Pointer to the top of the core 1 stack
+ * \param vector_table address of the vector table to use for core 1
+ * \see multicore_reset_core1
+ */
+void multicore_launch_core1_raw(void (*entry)(void), uint32_t *sp, uint32_t vector_table);
+
+/*!
+ * \defgroup multicore_fifo fifo
+ * \ingroup pico_multicore
+ * \brief Functions for the inter-core FIFOs
+ *
+ * The RP2040 contains two FIFOs for passing data, messages or ordered events between the two cores. Each FIFO is 32 bits
+ * wide, and 8 entries deep. One of the FIFOs can only be written by core 0, and read by core 1. The other can only be written
+ * by core 1, and read by core 0.
+ *
+ * \note The inter-core FIFOs are a very precious resource and are frequently used for SDK functionality (e.g. during
+ * core 1 launch or by the \ref multicore_lockout functions). Additionally they are often required for the exclusive use
+ * of an RTOS (e.g. FreeRTOS SMP). For these reasons it is suggested that you do not use the FIFO for your own purposes
+ * unless none of the above concerns apply; the majority of cases for transferring data between cores can be eqaully
+ * well handled by using a \ref queue
+ */
+
+/*! \brief Check the read FIFO to see if there is data available (sent by the other core)
+ * \ingroup multicore_fifo
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \return true if the FIFO has data in it, false otherwise
+ */
+static inline bool multicore_fifo_rvalid(void) {
+ return !!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS);
+}
+
+/*! \brief Check the write FIFO to see if it has space for more data
+ * \ingroup multicore_fifo
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * @return true if the FIFO has room for more data, false otherwise
+ */
+static inline bool multicore_fifo_wready(void) {
+ return !!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS);
+}
+
+/*! \brief Push data on to the write FIFO (data to the other core).
+ * \ingroup multicore_fifo
+ *
+ * This function will block until there is space for the data to be sent.
+ * Use multicore_fifo_wready() to check if it is possible to write to the
+ * FIFO if you don't want to block.
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \param data A 32 bit value to push on to the FIFO
+ */
+void multicore_fifo_push_blocking(uint32_t data);
+
+/*! \brief Push data on to the write FIFO (data to the other core) with timeout.
+ * \ingroup multicore_fifo
+ *
+ * This function will block until there is space for the data to be sent
+ * or the timeout is reached
+ *
+ * \param data A 32 bit value to push on to the FIFO
+ * \param timeout_us the timeout in microseconds
+ * \return true if the data was pushed, false if the timeout occurred before data could be pushed
+ */
+bool multicore_fifo_push_timeout_us(uint32_t data, uint64_t timeout_us);
+
+/*! \brief Pop data from the read FIFO (data from the other core).
+ * \ingroup multicore_fifo
+ *
+ * This function will block until there is data ready to be read
+ * Use multicore_fifo_rvalid() to check if data is ready to be read if you don't
+ * want to block.
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \return 32 bit data from the read FIFO.
+ */
+uint32_t multicore_fifo_pop_blocking(void);
+
+/*! \brief Pop data from the read FIFO (data from the other core) with timeout.
+ * \ingroup multicore_fifo
+ *
+ * This function will block until there is data ready to be read or the timeout is reached
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \param timeout_us the timeout in microseconds
+ * \param out the location to store the popped data if available
+ * \return true if the data was popped and a value copied into `out`, false if the timeout occurred before data could be popped
+ */
+bool multicore_fifo_pop_timeout_us(uint64_t timeout_us, uint32_t *out);
+
+/*! \brief Discard any data in the read FIFO
+ * \ingroup multicore_fifo
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ */
+static inline void multicore_fifo_drain(void) {
+ while (multicore_fifo_rvalid())
+ (void) sio_hw->fifo_rd;
+}
+
+/*! \brief Clear FIFO interrupt
+ * \ingroup multicore_fifo
+ *
+ * Note that this only clears an interrupt that was caused by the ROE or WOF flags.
+ * To clear the VLD flag you need to use one of the 'pop' or 'drain' functions.
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+ * \see multicore_fifo_get_status
+*/
+static inline void multicore_fifo_clear_irq(void) {
+ // Write any value to clear the error flags
+ sio_hw->fifo_st = 0xff;
+}
+
+/*! \brief Get FIFO statuses
+ * \ingroup multicore_fifo
+ *
+ * \return The statuses as a bitfield
+ *
+ * Bit | Description
+ * ----|------------
+ * 3 | Sticky flag indicating the RX FIFO was read when empty (ROE). This read was ignored by the FIFO.
+ * 2 | Sticky flag indicating the TX FIFO was written when full (WOF). This write was ignored by the FIFO.
+ * 1 | Value is 1 if this core’s TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
+ * 0 | Value is 1 if this core’s RX FIFO is not empty (i.e. if FIFO_RD is valid)
+ *
+ * See the note in the \ref multicore_fifo section for considerations regarding use of the inter-core FIFOs
+ *
+*/
+static inline uint32_t multicore_fifo_get_status(void) {
+ return sio_hw->fifo_st;
+}
+
+/*!
+ * \defgroup multicore_lockout lockout
+ * \ingroup pico_multicore
+ * \brief Functions to enable one core to force the other core to pause execution in a known state.
+ *
+ * Sometimes it is useful to enter a critical section on both cores at once. On a single
+ * core system a critical section can trivially be entered by disabling interrupts, however on a multi-core
+ * system that is not sufficient, and unless the other core is polling in some way, then it will need to be interrupted
+ * in order to cooperatively enter a blocked state.
+ *
+ * These "lockout" functions use the inter core FIFOs to cause an interrupt on one core from the other, and manage
+ * waiting for the other core to enter the "locked out" state.
+ *
+ * The usage is that the "victim" core ... i.e the core that can be "locked out" by the other core calls
+ * \ref multicore_lockout_victim_init to hook the FIFO interrupt. Note that either or both cores may do this.
+ *
+ * \note When "locked out" the victim core is paused (it is actually executing a tight loop with code in RAM) and has interrupts disabled.
+ * This makes the lockout functions suitable for use by code that wants to write to flash (at which point no code may be executing
+ * from flash)
+ *
+ * The core which wishes to lockout the other core calls \ref multicore_lockout_start_blocking or
+ * \ref multicore_lockout_start_timeout_us to interrupt the other "victim" core and wait for it to be in a
+ * "locked out" state. Once the lockout is no longer needed it calls \ref multicore_lockout_end_blocking or
+ * \ref multicore_lockout_end_timeout_us to release the lockout and wait for confirmation.
+ *
+ * \note Because multicore lockout uses the intercore FIFOs, the FIFOs <b>cannot</b> be used for any other purpose
+ */
+
+/*! \brief Initialize the current core such that it can be a "victim" of lockout (i.e. forced to pause in a known state by the other core)
+ * \ingroup multicore_lockout
+ *
+ * This code hooks the intercore FIFO IRQ, and the FIFO may not be used for any other purpose after this.
+ */
+void multicore_lockout_victim_init(void);
+
+/*! \brief Request the other core to pause in a known state and wait for it to do so
+ * \ingroup multicore_lockout
+ *
+ * The other (victim) core must have previously executed \ref multicore_lockout_victim_init()
+ *
+ * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding
+ * \ref multicore_lockout_end_blocking
+ */
+void multicore_lockout_start_blocking(void);
+
+/*! \brief Request the other core to pause in a known state and wait up to a time limit for it to do so
+ * \ingroup multicore_lockout
+ *
+ * The other core must have previously executed \ref multicore_lockout_victim_init()
+ *
+ * \note multicore_lockout_start_ functions are not nestable, and must be paired with a call to a corresponding
+ * \ref multicore_lockout_end_blocking
+ *
+ * \param timeout_us the timeout in microseconds
+ * \return true if the other core entered the locked out state within the timeout, false otherwise
+ */
+bool multicore_lockout_start_timeout_us(uint64_t timeout_us);
+
+/*! \brief Release the other core from a locked out state amd wait for it to acknowledge
+ * \ingroup multicore_lockout
+ *
+ * \note The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function
+ * from this core
+ */
+void multicore_lockout_end_blocking(void);
+
+/*! \brief Release the other core from a locked out state amd wait up to a time limit for it to acknowledge
+ * \ingroup multicore_lockout
+ *
+ * The other core must previously have been "locked out" by calling a `multicore_lockout_start_` function
+ * from this core
+ *
+ * \note be very careful using small timeout values, as a timeout here will leave the "lockout" functionality
+ * in a bad state. It is probably preferable to use \ref multicore_lockout_end_blocking anyway as if you have
+ * already waited for the victim core to enter the lockout state, then the victim core will be ready to exit
+ * the lockout state very quickly.
+ *
+ * \param timeout_us the timeout in microseconds
+ * \return true if the other core successfully exited locked out state within the timeout, false otherwise
+ */
+bool multicore_lockout_end_timeout_us(uint64_t timeout_us);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/mutex.c b/arkanoid/pico/mutex.c
new file mode 100644
index 0000000..5e8ccee
--- /dev/null
+++ b/arkanoid/pico/mutex.c
@@ -0,0 +1,184 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "mutex.h"
+#include "time.h"
+
+void mutex_init(mutex_t *mtx) {
+ lock_init(&mtx->core, next_striped_spin_lock_num());
+ mtx->owner = LOCK_INVALID_OWNER_ID;
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+ mtx->recursive = false;
+#endif
+ __mem_fence_release();
+}
+
+void recursive_mutex_init(recursive_mutex_t *mtx) {
+ lock_init(&mtx->core, next_striped_spin_lock_num());
+ mtx->owner = LOCK_INVALID_OWNER_ID;
+ mtx->enter_count = 0;
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+ mtx->recursive = true;
+#endif
+ __mem_fence_release();
+}
+
+void __time_critical_func(mutex_enter_blocking)(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+ if (mtx->recursive) {
+ recursive_mutex_enter_blocking(mtx);
+ return;
+ }
+#endif
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ do {
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ if (!lock_is_owner_id_valid(mtx->owner)) {
+ mtx->owner = caller;
+ spin_unlock(mtx->core.spin_lock, save);
+ break;
+ }
+ lock_internal_spin_unlock_with_wait(&mtx->core, save);
+ } while (true);
+}
+
+void __time_critical_func(recursive_mutex_enter_blocking)(recursive_mutex_t *mtx) {
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ do {
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ if (mtx->owner == caller || !lock_is_owner_id_valid(mtx->owner)) {
+ mtx->owner = caller;
+ uint __unused total = ++mtx->enter_count;
+ spin_unlock(mtx->core.spin_lock, save);
+ assert(total); // check for overflow
+ return;
+ } else {
+ lock_internal_spin_unlock_with_wait(&mtx->core, save);
+ }
+ } while (true);
+}
+
+bool __time_critical_func(mutex_try_enter)(mutex_t *mtx, uint32_t *owner_out) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+ if (mtx->recursive) {
+ return recursive_mutex_try_enter(mtx, owner_out);
+ }
+#endif
+ bool entered;
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ if (!lock_is_owner_id_valid(mtx->owner)) {
+ mtx->owner = lock_get_caller_owner_id();
+ entered = true;
+ } else {
+ if (owner_out) *owner_out = (uint32_t) mtx->owner;
+ entered = false;
+ }
+ spin_unlock(mtx->core.spin_lock, save);
+ return entered;
+}
+
+bool __time_critical_func(recursive_mutex_try_enter)(recursive_mutex_t *mtx, uint32_t *owner_out) {
+ bool entered;
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+ mtx->owner = caller;
+ uint __unused total = ++mtx->enter_count;
+ assert(total); // check for overflow
+ entered = true;
+ } else {
+ if (owner_out) *owner_out = (uint32_t) mtx->owner;
+ entered = false;
+ }
+ spin_unlock(mtx->core.spin_lock, save);
+ return entered;
+}
+
+bool __time_critical_func(mutex_enter_timeout_ms)(mutex_t *mtx, uint32_t timeout_ms) {
+ return mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
+}
+
+bool __time_critical_func(recursive_mutex_enter_timeout_ms)(recursive_mutex_t *mtx, uint32_t timeout_ms) {
+ return recursive_mutex_enter_block_until(mtx, make_timeout_time_ms(timeout_ms));
+}
+
+bool __time_critical_func(mutex_enter_timeout_us)(mutex_t *mtx, uint32_t timeout_us) {
+ return mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
+}
+
+bool __time_critical_func(recursive_mutex_enter_timeout_us)(recursive_mutex_t *mtx, uint32_t timeout_us) {
+ return recursive_mutex_enter_block_until(mtx, make_timeout_time_us(timeout_us));
+}
+
+bool __time_critical_func(mutex_enter_block_until)(mutex_t *mtx, absolute_time_t until) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+ if (mtx->recursive) {
+ return recursive_mutex_enter_block_until(mtx, until);
+ }
+#endif
+ assert(mtx->core.spin_lock);
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ do {
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ if (!lock_is_owner_id_valid(mtx->owner)) {
+ mtx->owner = caller;
+ spin_unlock(mtx->core.spin_lock, save);
+ return true;
+ } else {
+ if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
+ // timed out
+ return false;
+ }
+ // not timed out; spin lock already unlocked, so loop again
+ }
+ } while (true);
+}
+
+bool __time_critical_func(recursive_mutex_enter_block_until)(recursive_mutex_t *mtx, absolute_time_t until) {
+ assert(mtx->core.spin_lock);
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ do {
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ if (!lock_is_owner_id_valid(mtx->owner) || mtx->owner == caller) {
+ mtx->owner = caller;
+ uint __unused total = ++mtx->enter_count;
+ spin_unlock(mtx->core.spin_lock, save);
+ assert(total); // check for overflow
+ return true;
+ } else {
+ if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&mtx->core, save, until)) {
+ // timed out
+ return false;
+ }
+ // not timed out; spin lock already unlocked, so loop again
+ }
+ } while (true);
+}
+
+void __time_critical_func(mutex_exit)(mutex_t *mtx) {
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+ if (mtx->recursive) {
+ recursive_mutex_exit(mtx);
+ return;
+ }
+#endif
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ assert(lock_is_owner_id_valid(mtx->owner));
+ mtx->owner = LOCK_INVALID_OWNER_ID;
+ lock_internal_spin_unlock_with_notify(&mtx->core, save);
+}
+
+void __time_critical_func(recursive_mutex_exit)(recursive_mutex_t *mtx) {
+ uint32_t save = spin_lock_blocking(mtx->core.spin_lock);
+ assert(lock_is_owner_id_valid(mtx->owner));
+ assert(mtx->enter_count);
+ if (!--mtx->enter_count) {
+ mtx->owner = LOCK_INVALID_OWNER_ID;
+ lock_internal_spin_unlock_with_notify(&mtx->core, save);
+ } else {
+ spin_unlock(mtx->core.spin_lock, save);
+ }
+}
\ No newline at end of file
diff --git a/arkanoid/pico/mutex.h b/arkanoid/pico/mutex.h
new file mode 100644
index 0000000..abb36d7
--- /dev/null
+++ b/arkanoid/pico/mutex.h
@@ -0,0 +1,297 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_MUTEX_H
+#define _PLATFORM_MUTEX_H
+
+#include "lock_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file mutex.h
+ * \defgroup mutex mutex
+ * \ingroup pico_sync
+ * \brief Mutex API for non IRQ mutual exclusion between cores
+ *
+ * Mutexes are application level locks usually used protecting data structures that might be used by
+ * multiple threads of execution. Unlike critical sections, the mutex protected code is not necessarily
+ * required/expected to complete quickly, as no other sytem wide locks are held on account of an acquired mutex.
+ *
+ * When acquired, the mutex has an owner (see \ref lock_get_caller_owner_id) which with the plain SDK is just
+ * the acquiring core, but in an RTOS it could be a task, or an IRQ handler context.
+ *
+ * Two variants of mutex are provided; \ref mutex_t (and associated mutex_ functions) is a regular mutex that cannot
+ * be acquired recursively by the same owner (a deadlock will occur if you try). \ref recursive_mutex_t
+ * (and associated recursive_mutex_ functions) is a recursive mutex that can be recursively obtained by
+ * the same caller, at the expense of some more overhead when acquiring and releasing.
+ *
+ * It is generally a bad idea to call blocking mutex_ or recursive_mutex_ functions from within an IRQ handler.
+ * It is valid to call \ref mutex_try_enter or \ref recursive_mutex_try_enter from within an IRQ handler, if the operation
+ * that would be conducted under lock can be skipped if the mutex is locked (at least by the same owner).
+ *
+ * NOTE: For backwards compatibility with version 1.2.0 of the SDK, if the define
+ * PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY is set to 1, then the the regular mutex_ functions
+ * may also be used for recursive mutexes. This flag will be removed in a future version of the SDK.
+ *
+ * See \ref critical_section.h for protecting access between multiple cores AND IRQ handlers
+ */
+
+/*! \brief recursive mutex instance
+ * \ingroup mutex
+ */
+typedef struct __packed_aligned {
+ lock_core_t core;
+ lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned
+ uint8_t enter_count; //! ownership count
+#if PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+ bool recursive;
+#endif
+} recursive_mutex_t;
+
+/*! \brief regular (non recursive) mutex instance
+ * \ingroup mutex
+ */
+#if !PICO_MUTEX_ENABLE_SDK120_COMPATIBILITY
+typedef struct __packed_aligned mutex {
+ lock_core_t core;
+ lock_owner_id_t owner; //! owner id LOCK_INVALID_OWNER_ID for unowned
+} mutex_t;
+#else
+typedef recursive_mutex_t mutex_t; // they are one and the same when backwards compatible with SDK1.2.0
+#endif
+
+/*! \brief Initialise a mutex structure
+ * \ingroup mutex
+ *
+ * \param mtx Pointer to mutex structure
+ */
+void mutex_init(mutex_t *mtx);
+
+/*! \brief Initialise a recursive mutex structure
+ * \ingroup mutex
+ *
+ * A recursive mutex may be entered in a nested fashion by the same owner
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_init(recursive_mutex_t *mtx);
+
+/*! \brief Take ownership of a mutex
+ * \ingroup mutex
+ *
+ * This function will block until the caller can be granted ownership of the mutex.
+ * On return the caller owns the mutex
+ *
+ * \param mtx Pointer to mutex structure
+ */
+void mutex_enter_blocking(mutex_t *mtx);
+
+/*! \brief Take ownership of a recursive mutex
+ * \ingroup mutex
+ *
+ * This function will block until the caller can be granted ownership of the mutex.
+ * On return the caller owns the mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_enter_blocking(recursive_mutex_t *mtx);
+
+/*! \brief Attempt to take ownership of a mutex
+ * \ingroup mutex
+ *
+ * If the mutex wasn't owned, this will claim the mutex for the caller and return true.
+ * Otherwise (if the mutex was already owned) this will return false and the
+ * caller will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param owner_out If mutex was already owned, and this pointer is non-zero, it will be filled in with the owner id of the current owner of the mutex
+ * \return true if mutex now owned, false otherwise
+ */
+bool mutex_try_enter(mutex_t *mtx, uint32_t *owner_out);
+
+/*! \brief Attempt to take ownership of a recursive mutex
+ * \ingroup mutex
+ *
+ * If the mutex wasn't owned or was owned by the caller, this will claim the mutex and return true.
+ * Otherwise (if the mutex was already owned by another owner) this will return false and the
+ * caller will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param owner_out If mutex was already owned by another owner, and this pointer is non-zero,
+ * it will be filled in with the owner id of the current owner of the mutex
+ * \return true if the recursive mutex (now) owned, false otherwise
+ */
+bool recursive_mutex_try_enter(recursive_mutex_t *mtx, uint32_t *owner_out);
+
+/*! \brief Wait for mutex with timeout
+ * \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_ms The timeout in milliseconds.
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
+ */
+bool mutex_enter_timeout_ms(mutex_t *mtx, uint32_t timeout_ms);
+
+/*! \brief Wait for recursive mutex with timeout
+ * \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param timeout_ms The timeout in milliseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_ms(recursive_mutex_t *mtx, uint32_t timeout_ms);
+
+/*! \brief Wait for mutex with timeout
+ * \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_us The timeout in microseconds.
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
+ */
+bool mutex_enter_timeout_us(mutex_t *mtx, uint32_t timeout_us);
+
+/*! \brief Wait for recursive mutex with timeout
+ * \ingroup mutex
+ *
+ * Wait for up to the specific time to take ownership of the recursive mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param timeout_us The timeout in microseconds.
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_timeout_us(recursive_mutex_t *mtx, uint32_t timeout_us);
+
+/*! \brief Wait for mutex until a specific time
+ * \ingroup mutex
+ *
+ * Wait until the specific time to take ownership of the mutex. If the caller
+ * can be granted ownership of the mutex before the timeout expires, then true will be returned
+ * and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to mutex structure
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
+ * \return true if mutex now owned, false if timeout occurred before ownership could be granted
+ */
+bool mutex_enter_block_until(mutex_t *mtx, absolute_time_t until);
+
+/*! \brief Wait for mutex until a specific time
+ * \ingroup mutex
+ *
+ * Wait until the specific time to take ownership of the mutex. If the caller
+ * already has ownership of the mutex or can be granted ownership of the mutex before the timeout expires,
+ * then true will be returned and the caller will own the mutex, otherwise false will be returned and the caller
+ * will NOT own the mutex.
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \param until The time after which to return if the caller cannot be granted ownership of the mutex
+ * \return true if the recursive mutex (now) owned, false if timeout occurred before ownership could be granted
+ */
+bool recursive_mutex_enter_block_until(recursive_mutex_t *mtx, absolute_time_t until);
+
+/*! \brief Release ownership of a mutex
+ * \ingroup mutex
+ *
+ * \param mtx Pointer to mutex structure
+ */
+void mutex_exit(mutex_t *mtx);
+
+/*! \brief Release ownership of a recursive mutex
+ * \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ */
+void recursive_mutex_exit(recursive_mutex_t *mtx);
+
+/*! \brief Test for mutex initialized state
+ * \ingroup mutex
+ *
+ * \param mtx Pointer to mutex structure
+ * \return true if the mutex is initialized, false otherwise
+ */
+static inline bool mutex_is_initialized(mutex_t *mtx) {
+ return mtx->core.spin_lock != 0;
+}
+
+/*! \brief Test for recursive mutex initialized state
+ * \ingroup mutex
+ *
+ * \param mtx Pointer to recursive mutex structure
+ * \return true if the recursive mutex is initialized, false otherwise
+ */
+static inline bool recursive_mutex_is_initialized(recursive_mutex_t *mtx) {
+ return mtx->core.spin_lock != 0;
+}
+
+/*! \brief Helper macro for static definition of mutexes
+ * \ingroup mutex
+ *
+ * A mutex defined as follows:
+ *
+ * ```c
+ * auto_init_mutex(my_mutex);
+ * ```
+ *
+ * Is equivalent to doing
+ *
+ * ```c
+ * static mutex_t my_mutex;
+ *
+ * void my_init_function() {
+ * mutex_init(&my_mutex);
+ * }
+ * ```
+ *
+ * But the initialization of the mutex is performed automatically during runtime initialization
+ */
+#define auto_init_mutex(name) static __attribute__((section(".mutex_array"))) mutex_t name
+
+/*! \brief Helper macro for static definition of recursive mutexes
+ * \ingroup mutex
+ *
+ * A recursive mutex defined as follows:
+ *
+ * ```c
+ * auto_init_recursive_mutex(my_recursive_mutex);
+ * ```
+ *
+ * Is equivalent to doing
+ *
+ * ```c
+ * static recursive_mutex_t my_recursive_mutex;
+ *
+ * void my_init_function() {
+ * recursive_mutex_init(&my_recursive_mutex);
+ * }
+ * ```
+ *
+ * But the initialization of the mutex is performed automatically during runtime initialization
+ */
+#define auto_init_recursive_mutex(name) static __attribute__((section(".mutex_array"))) recursive_mutex_t name = { .core.spin_lock = (spin_lock_t *)1 /* marker for runtime_init */ }
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/pheap.c b/arkanoid/pico/pheap.c
new file mode 100644
index 0000000..4528f50
--- /dev/null
+++ b/arkanoid/pico/pheap.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include "pheap.h"
+
+pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data) {
+ invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t))));
+ pheap_t *heap = calloc(1, sizeof(pheap_t));
+ heap->nodes = calloc(max_nodes, sizeof(pheap_node_t));
+ ph_post_alloc_init(heap, max_nodes, comparator, user_data);
+ return heap;
+}
+
+void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data) {
+ invalid_params_if(PHEAP, !max_nodes || max_nodes >= (1u << (8 * sizeof(pheap_node_id_t))));
+ heap->max_nodes = (pheap_node_id_t) max_nodes;
+ heap->comparator = comparator;
+ heap->user_data = user_data;
+ ph_clear(heap);
+}
+
+void ph_clear(pheap_t *heap) {
+ heap->root_id = 0;
+ heap->free_head_id = 1;
+ heap->free_tail_id = heap->max_nodes;
+ for(pheap_node_id_t i = 1; i < heap->max_nodes; i++) {
+ ph_get_node(heap, i)->sibling = (pheap_node_id_t)(i + 1);
+ }
+ ph_get_node(heap, heap->max_nodes)->sibling = 0;
+}
+
+void ph_destroy(pheap_t *heap) {
+ free(heap->nodes);
+ free(heap);
+}
+
+pheap_node_id_t ph_merge_two_pass(pheap_t *heap, pheap_node_id_t id) {
+ if (!id || !ph_get_node(heap, id)->sibling) {
+ return id;
+ } else {
+ pheap_node_id_t a, b, new_node;
+ a = id;
+ b = ph_get_node(heap, id)->sibling;
+ new_node = ph_get_node(heap, b)->sibling;
+ ph_get_node(heap, a)->sibling = ph_get_node(heap, b)->sibling = 0;
+ return ph_merge_nodes(heap, ph_merge_nodes(heap, a, b), ph_merge_two_pass(heap, new_node));
+ }
+}
+
+static pheap_node_id_t ph_remove_any_head(pheap_t *heap, pheap_node_id_t root_id, bool free) {
+ assert(root_id);
+// printf("Removing head %d (parent %d sibling %d)\n", root_id, ph_get_node(heap, root_id)->parent, ph_get_node(heap, root_id)->sibling);
+ assert(!ph_get_node(heap, root_id)->sibling);
+ assert(!ph_get_node(heap, root_id)->parent);
+ pheap_node_id_t new_root_id = ph_merge_two_pass(heap, ph_get_node(heap, root_id)->child);
+ if (free) {
+ if (heap->free_tail_id) {
+ ph_get_node(heap, heap->free_tail_id)->sibling = root_id;
+ }
+ heap->free_tail_id = root_id;
+ }
+ if (new_root_id) ph_get_node(heap, new_root_id)->parent = 0;
+ ph_get_node(heap, root_id)->sibling = 0;
+ return new_root_id;
+}
+
+pheap_node_id_t ph_remove_head(pheap_t *heap, bool free) {
+ pheap_node_id_t old_root_id = ph_peek_head(heap);
+ heap->root_id = ph_remove_any_head(heap, old_root_id, free);
+ return old_root_id;
+}
+
+bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id) {
+ // 1) trivial cases
+ if (!id) return false;
+ if (id == heap->root_id) {
+ ph_remove_and_free_head(heap);
+ return true;
+ }
+ // 2) unlink the node from the tree
+ pheap_node_t *node = ph_get_node(heap, id);
+ if (!node->parent) return false; // not in tree
+ pheap_node_t *parent = ph_get_node(heap, node->parent);
+ if (parent->child == id) {
+ parent->child = node->sibling;
+ } else {
+ pheap_node_id_t prev_sibling_id = parent->child;
+ bool __unused found = false;
+ do {
+ pheap_node_t *prev_sibling = ph_get_node(heap, prev_sibling_id);
+ if (prev_sibling->sibling == id) {
+ prev_sibling->sibling = node->sibling;
+ found = true;
+ break;
+ }
+ prev_sibling_id = prev_sibling->sibling;
+ } while (prev_sibling_id);
+ assert(found);
+ }
+ node->sibling = node->parent = 0;
+// ph_dump(heap, NULL, NULL);
+ // 3) remove it from the head of its own subtree
+ pheap_node_id_t new_sub_tree = ph_remove_any_head(heap, id, true);
+ assert(new_sub_tree != heap->root_id);
+ heap->root_id = ph_merge_nodes(heap, heap->root_id, new_sub_tree);
+ return true;
+}
+
+static uint ph_dump_node(pheap_t *heap, pheap_node_id_t id, void (*dump_key)(pheap_node_id_t, void *), void *user_data, uint indent) {
+ uint count = 0;
+ if (id) {
+ count++;
+ for (uint i = 0; i < indent * 2; i++) {
+ putchar(' ');
+ }
+ pheap_node_t *node = ph_get_node(heap, id);
+ printf("%d (c=%d s=%d p=%d) ", id, node->child, node->sibling, node->parent);
+ if (dump_key) dump_key(id, user_data);
+ printf("\n");
+ count += ph_dump_node(heap, node->child, dump_key, user_data, indent + 1);
+ count += ph_dump_node(heap, node->sibling, dump_key, user_data, indent);
+ }
+ return count;
+}
+
+void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t, void *), void *user_data) {
+ uint count = ph_dump_node(heap, heap->root_id, dump_key, user_data, 0);
+ printf("node_count %d\n", count);
+}
\ No newline at end of file
diff --git a/arkanoid/pico/pheap.h b/arkanoid/pico/pheap.h
new file mode 100644
index 0000000..25351b4
--- /dev/null
+++ b/arkanoid/pico/pheap.h
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_UTIL_PHEAP_H
+#define _PICO_UTIL_PHEAP_H
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_PHEAP, Enable/disable assertions in the pheap module, type=bool, default=0, group=pico_util
+#ifndef PARAM_ASSERTIONS_ENABLED_PHEAP
+#define PARAM_ASSERTIONS_ENABLED_PHEAP 0
+#endif
+
+/**
+ * \file pheap.h
+ * \defgroup util_pheap pheap
+ * Pairing Heap Implementation
+ * \ingroup pico_util
+ *
+ * pheap defines a simple pairing heap. the implementation simply tracks array indexes, it is up to
+ * the user to provide storage for heap entries and a comparison function.
+ *
+ * NOTE: this class is not safe for concurrent usage. It should be externally protected. Furthermore
+ * if used concurrently, the caller needs to protect around their use of the returned id.
+ * for example, ph_remove_and_free_head returns the id of an element that is no longer in the heap.
+ *
+ * The user can still use this to look at the data in their companion array, however obviously further operations
+ * on the heap may cause them to overwrite that data as the id may be reused on subsequent operations
+ *
+ */
+// PICO_CONFIG: PICO_PHEAP_MAX_ENTRIES, Maximum number of entries in the pheap, min=1, max=65534, default=255, group=pico_util
+#ifndef PICO_PHEAP_MAX_ENTRIES
+#define PICO_PHEAP_MAX_ENTRIES 255
+#endif
+
+// public heap_node ids are numbered from 1 (0 means none)
+#if PICO_PHEAP_MAX_ENTRIES < 256
+typedef uint8_t pheap_node_id_t;
+#elif PICO_PHEAP_MAX_ENTRIES < 65535
+typedef uint16_t pheap_node_id_t;
+#else
+#error invalid PICO_PHEAP_MAX_ENTRIES
+#endif
+
+typedef struct pheap_node {
+ pheap_node_id_t child, sibling, parent;
+} pheap_node_t;
+
+/**
+ * A user comparator function for nodes in a pairing heap.
+ *
+ * \return true if a < b in natural order. Note this relative ordering must be stable from call to call.
+ */
+typedef bool (*pheap_comparator)(void *user_data, pheap_node_id_t a, pheap_node_id_t b);
+
+typedef struct pheap {
+ pheap_node_t *nodes;
+ pheap_comparator comparator;
+ void *user_data;
+ pheap_node_id_t max_nodes;
+ pheap_node_id_t root_id;
+ // we remove from head and add to tail to stop reusing the same ids
+ pheap_node_id_t free_head_id;
+ pheap_node_id_t free_tail_id;
+} pheap_t;
+
+/**
+ * Create a pairing heap, which effectively maintains an efficient sorted ordering
+ * of nodes. The heap itself stores no user per-node state, it is expected
+ * that the user maintains a companion array. A comparator function must
+ * be provided so that the heap implementation can determine the relative ordering of nodes
+ *
+ * \param max_nodes the maximum number of nodes that may be in the heap (this is bounded by
+ * PICO_PHEAP_MAX_ENTRIES which defaults to 255 to be able to store indexes
+ * in a single byte).
+ * \param comparator the node comparison function
+ * \param user_data a user data pointer associated with the heap that is provided in callbacks
+ * \return a newly allocated and initialized heap
+ */
+pheap_t *ph_create(uint max_nodes, pheap_comparator comparator, void *user_data);
+
+/**
+ * Removes all nodes from the pairing heap
+ * \param heap the heap
+ */
+void ph_clear(pheap_t *heap);
+
+/**
+ * De-allocates a pairing heap
+ *
+ * Note this method must *ONLY* be called on heaps created by ph_create()
+ * \param heap the heap
+ */
+void ph_destroy(pheap_t *heap);
+
+// internal method
+static inline pheap_node_t *ph_get_node(pheap_t *heap, pheap_node_id_t id) {
+ assert(id && id <= heap->max_nodes);
+ return heap->nodes + id - 1;
+}
+
+// internal method
+static void ph_add_child_node(pheap_t *heap, pheap_node_id_t parent_id, pheap_node_id_t child_id) {
+ pheap_node_t *n = ph_get_node(heap, parent_id);
+ assert(parent_id);
+ assert(child_id);
+ assert(parent_id != child_id);
+ pheap_node_t *c = ph_get_node(heap, child_id);
+ c->parent = parent_id;
+ if (!n->child) {
+ n->child = child_id;
+ } else {
+ c->sibling = n->child;
+ n->child = child_id;
+ }
+}
+
+// internal method
+static pheap_node_id_t ph_merge_nodes(pheap_t *heap, pheap_node_id_t a, pheap_node_id_t b) {
+ if (!a) return b;
+ if (!b) return a;
+ if (heap->comparator(heap->user_data, a, b)) {
+ ph_add_child_node(heap, a, b);
+ return a;
+ } else {
+ ph_add_child_node(heap, b, a);
+ return b;
+ }
+}
+
+/**
+ * Allocate a new node from the unused space in the heap
+ *
+ * \param heap the heap
+ * \return an identifier for the node, or 0 if the heap is full
+ */
+static inline pheap_node_id_t ph_new_node(pheap_t *heap) {
+ if (!heap->free_head_id) return 0;
+ pheap_node_id_t id = heap->free_head_id;
+ pheap_node_t *hn = ph_get_node(heap, id);
+ heap->free_head_id = hn->sibling;
+ if (!heap->free_head_id) heap->free_tail_id = 0;
+ hn->child = hn->sibling = hn->parent = 0;
+ return id;
+}
+
+/**
+ * Inserts a node into the heap.
+ *
+ * This method inserts a node (previously allocated by ph_new_node())
+ * into the heap, determining the correct order by calling
+ * the heap's comparator
+ *
+ * \param heap the heap
+ * \param id the id of the node to insert
+ * \return the id of the new head of the pairing heap (i.e. node that compares first)
+ */
+static inline pheap_node_id_t ph_insert_node(pheap_t *heap, pheap_node_id_t id) {
+ assert(id);
+ pheap_node_t *hn = ph_get_node(heap, id);
+ hn->child = hn->sibling = hn->parent = 0;
+ heap->root_id = ph_merge_nodes(heap, heap->root_id, id);
+ return heap->root_id;
+}
+
+/**
+ * Returns the head node in the heap, i.e. the node
+ * which compares first, but without removing it from the heap.
+ *
+ * \param heap the heap
+ * \return the current head node id
+ */
+static inline pheap_node_id_t ph_peek_head(pheap_t *heap) {
+ return heap->root_id;
+}
+
+/**
+ * Remove the head node from the pairing heap. This head node is
+ * the node which compares first in the logical ordering provided
+ * by the comparator.
+ *
+ * Note that in the case of free == true, the returned id is no longer
+ * allocated and may be re-used by future node allocations, so the caller
+ * should retrieve any per node state from the companion array before modifying
+ * the heap further.
+ *
+ * @param heap the heap
+ * @param free true if the id is also to be freed; false if not - useful if the caller
+ * may wish to re-insert an item with the same id)
+ * @return the old head node id.
+ */
+pheap_node_id_t ph_remove_head(pheap_t *heap, bool free);
+
+/**
+ * Remove the head node from the pairing heap. This head node is
+ * the node which compares first in the logical ordering provided
+ * by the comparator.
+ *
+ * Note that the returned id will be freed, and thus may be re-used by future node allocations,
+ * so the caller should retrieve any per node state from the companion array before modifying
+ * the heap further.
+ *
+ * @param heap the heap
+ * @return the old head node id.
+ */
+static inline pheap_node_id_t ph_remove_and_free_head(pheap_t *heap) {
+ return ph_remove_head(heap, true);
+}
+
+/**
+ * Remove and free an arbitrary node from the pairing heap. This is a more
+ * costly operation than removing the head via ph_remove_and_free_head()
+ *
+ * @param heap the heap
+ * @param id the id of the node to free
+ * @return true if the the node was in the heap, false otherwise
+ */
+bool ph_remove_and_free_node(pheap_t *heap, pheap_node_id_t id);
+
+/**
+ * Determine if the heap contains a given node. Note containment refers
+ * to whether the node is inserted (ph_insert_node()) vs allocated (ph_new_node())
+ *
+ * @param heap the heap
+ * @param id the id of the node
+ * @return true if the heap contains a node with the given id, false otherwise.
+ */
+static inline bool ph_contains_node(pheap_t *heap, pheap_node_id_t id) {
+ return id == heap->root_id || ph_get_node(heap, id)->parent;
+}
+
+
+/**
+ * Free a node that is not currently in the heap, but has been allocated
+ *
+ * @param heap the heap
+ * @param id the id of the node
+ */
+static inline void ph_free_node(pheap_t *heap, pheap_node_id_t id) {
+ assert(id && !ph_contains_node(heap, id));
+ if (heap->free_tail_id) {
+ ph_get_node(heap, heap->free_tail_id)->sibling = id;
+ }
+ heap->free_tail_id = id;
+}
+
+/**
+ * Print a representation of the heap for debugging
+ *
+ * @param heap the heap
+ * @param dump_key a method to print a node value
+ * @param user_data the user data to pass to the dump_key method
+ */
+void ph_dump(pheap_t *heap, void (*dump_key)(pheap_node_id_t id, void *user_data), void *user_data);
+
+/**
+ * Initialize a statically allocated heap (ph_create() using the C heap).
+ * The heap member `nodes` must be allocated of size max_nodes.
+ *
+ * @param heap the heap
+ * @param max_nodes the max number of nodes in the heap (matching the size of the heap's nodes array)
+ * @param comparator the comparator for the heap
+ * @param user_data the user data for the heap.
+ */
+void ph_post_alloc_init(pheap_t *heap, uint max_nodes, pheap_comparator comparator, void *user_data);
+
+/**
+ * Define a statically allocated pairing heap. This must be initialized
+ * by ph_post_alloc_init
+ */
+#define PHEAP_DEFINE_STATIC(name, _max_nodes) \
+ static_assert(_max_nodes && _max_nodes < (1u << (8 * sizeof(pheap_node_id_t))), ""); \
+ static pheap_node_t name ## _nodes[_max_nodes]; \
+ static pheap_t name = { \
+ .nodes = name ## _nodes, \
+ .max_nodes = _max_nodes \
+ };
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/pico.h b/arkanoid/pico/pico.h
new file mode 100644
index 0000000..7b62222
--- /dev/null
+++ b/arkanoid/pico/pico.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PICO_H_
+#define PICO_H_
+
+/** \file pico.h
+ * \defgroup pico_base pico_base
+ *
+ * Core types and macros for the Raspberry Pi Pico SDK. This header is intended to be included by all source code
+ * as it includes configuration headers and overrides in the correct order
+ *
+ * This header may be included by assembly code
+*/
+
+#include "junk/types.h"
+#include "junk/version.h"
+#include "junk/config.h"
+#include "platform.h"
+#include "junk/error.h"
+
+#endif
diff --git a/arkanoid/pico/pico4ml/screen.c b/arkanoid/pico/pico4ml/screen.c
new file mode 100644
index 0000000..e57ed7a
--- /dev/null
+++ b/arkanoid/pico/pico4ml/screen.c
@@ -0,0 +1,270 @@
+#include "screen.h"
+#define DELAY 0x80
+
+
+int EPD_RST_PIN = 7;
+int EPD_DC_PIN = 9;
+int EPD_CS_PIN = 13;
+int EPD_CLK_PIN = 10;
+int EPD_MOSI_PIN = 11;
+
+// based on Adafruit ST7735 library for Arduino
+static const uint8_t
+ init_cmds1[] = { // Init for 7735R, part 1 (red or green tab)
+ 15, // 15 commands in list:
+ ST7735_SWRESET, DELAY, // 1: Software reset, 0 args, w/delay
+ 150, // 150 ms delay
+ ST7735_SLPOUT , DELAY, // 2: Out of sleep mode, 0 args, w/delay
+ 255, // 500 ms delay
+ ST7735_FRMCTR1, 3 , // 3: Frame rate ctrl - normal mode, 3 args:
+ 0x01, 0x2C, 0x2D, // Rate = fosc/(1x2+40) * (LINE+2C+2D)
+ ST7735_FRMCTR2, 3 , // 4: Frame rate control - idle mode, 3 args:
+ 0x01, 0x2C, 0x2D, // Rate = fosc/(1x2+40) * (LINE+2C+2D)
+ ST7735_FRMCTR3, 6 , // 5: Frame rate ctrl - partial mode, 6 args:
+ 0x01, 0x2C, 0x2D, // Dot inversion mode
+ 0x01, 0x2C, 0x2D, // Line inversion mode
+ ST7735_INVCTR , 1 , // 6: Display inversion ctrl, 1 arg, no delay:
+ 0x07, // No inversion
+ ST7735_PWCTR1 , 3 , // 7: Power control, 3 args, no delay:
+ 0xA2,
+ 0x02, // -4.6V
+ 0x84, // AUTO mode
+ ST7735_PWCTR2 , 1 , // 8: Power control, 1 arg, no delay:
+ 0xC5, // VGH25 = 2.4C VGSEL = -10 VGH = 3 * AVDD
+ ST7735_PWCTR3 , 2 , // 9: Power control, 2 args, no delay:
+ 0x0A, // Opamp current small
+ 0x00, // Boost frequency
+ ST7735_PWCTR4 , 2 , // 10: Power control, 2 args, no delay:
+ 0x8A, // BCLK/2, Opamp current small & Medium low
+ 0x2A,
+ ST7735_PWCTR5 , 2 , // 11: Power control, 2 args, no delay:
+ 0x8A, 0xEE,
+ ST7735_VMCTR1 , 1 , // 12: Power control, 1 arg, no delay:
+ 0x0E,
+ ST7735_INVOFF , 0 , // 13: Don't invert display, no args, no delay
+ ST7735_MADCTL , 1 , // 14: Memory access control (directions), 1 arg:
+ ST7735_ROTATION, // row addr/col addr, bottom to top refresh
+ ST7735_COLMOD , 1 , // 15: set color mode, 1 arg, no delay:
+ 0x05 }, // 16-bit color
+
+#if (defined(ST7735_IS_128X128) || defined(ST7735_IS_160X128))
+ init_cmds2[] = { // Init for 7735R, part 2 (1.44" display)
+ 2, // 2 commands in list:
+ ST7735_CASET , 4 , // 1: Column addr set, 4 args, no delay:
+ 0x00, 0x00, // XSTART = 0
+ 0x00, 0x7F, // XEND = 127
+ ST7735_RASET , 4 , // 2: Row addr set, 4 args, no delay:
+ 0x00, 0x00, // XSTART = 0
+ 0x00, 0x7F }, // XEND = 127
+#endif // ST7735_IS_128X128
+
+#ifdef ST7735_IS_160X80
+ init_cmds2[] = { // Init for 7735S, part 2 (160x80 display)
+ 3, // 3 commands in list:
+ ST7735_CASET , 4 , // 1: Column addr set, 4 args, no delay:
+ 0x00, 0x00, // XSTART = 0
+ 0x00, 0x4F, // XEND = 79
+ ST7735_RASET , 4 , // 2: Row addr set, 4 args, no delay:
+ 0x00, 0x00, // XSTART = 0
+ 0x00, 0x9F , // XEND = 159
+ }, // 3: Invert colors
+#endif
+
+ init_cmds3[] = { // Init for 7735R, part 3 (red or green tab)
+ 4, // 4 commands in list:
+ ST7735_GMCTRP1, 16 , // 1: Magical unicorn dust, 16 args, no delay:
+ 0x02, 0x1c, 0x07, 0x12,
+ 0x37, 0x32, 0x29, 0x2d,
+ 0x29, 0x25, 0x2B, 0x39,
+ 0x00, 0x01, 0x03, 0x10,
+ ST7735_GMCTRN1, 16 , // 2: Sparkles and rainbows, 16 args, no delay:
+ 0x03, 0x1d, 0x07, 0x06,
+ 0x2E, 0x2C, 0x29, 0x2D,
+ 0x2E, 0x2E, 0x37, 0x3F,
+ 0x00, 0x00, 0x02, 0x10,
+ ST7735_NORON , DELAY, // 3: Normal display on, no args, w/delay
+ 10, // 10 ms delay
+ ST7735_DISPON , DELAY, // 4: Main screen turn on, no args w/delay
+ 100 }; // 100 ms delay
+
+static void ST7735_Select() {
+ // HAL_GPIO_WritePin(ST7735_CS_GPIO_Port, ST7735_CS_Pin, GPIO_PIN_RESET);
+ gpio_put(EPD_CS_PIN, 0);
+}
+
+void ST7735_Unselect() {
+ //HAL_GPIO_WritePin(ST7735_CS_GPIO_Port, ST7735_CS_Pin, GPIO_PIN_SET);
+ gpio_put(EPD_CS_PIN, 1);
+}
+
+static void ST7735_Reset() {
+ gpio_put(EPD_RST_PIN, 0);
+ sleep_ms(5);
+ gpio_put(EPD_RST_PIN, 1);
+}
+
+static void ST7735_WriteCommand(uint8_t cmd) {
+ //HAL_GPIO_WritePin(ST7735_DC_GPIO_Port, ST7735_DC_Pin, GPIO_PIN_RESET);
+ gpio_put(EPD_DC_PIN, 0);
+ spi_write_blocking(spi1, &cmd, sizeof(cmd));
+ // HAL_SPI_Transmit(&ST7735_spi1, &cmd, sizeof(cmd), HAL_MAX_DELAY);
+}
+
+static void ST7735_WriteData(uint8_t* buff, size_t buff_size) {
+ //HAL_GPIO_WritePin(ST7735_DC_GPIO_Port, ST7735_DC_Pin, GPIO_PIN_SET);
+ gpio_put(EPD_DC_PIN, 1);
+ spi_write_blocking(spi1, buff, buff_size);
+ // HAL_SPI_Transmit(&ST7735_spi1, buff, buff_size, HAL_MAX_DELAY);
+}
+
+static void ST7735_ExecuteCommandList(const uint8_t *addr) {
+ uint8_t numCommands, numArgs;
+ uint16_t ms;
+
+ numCommands = *addr++;
+ while(numCommands--) {
+ uint8_t cmd = *addr++;
+ ST7735_WriteCommand(cmd);
+
+ numArgs = *addr++;
+ // If high bit set, delay follows args
+ ms = numArgs & DELAY;
+ numArgs &= ~DELAY;
+ if(numArgs) {
+ ST7735_WriteData((uint8_t*)addr, numArgs);
+ addr += numArgs;
+ }
+
+ if(ms) {
+ ms = *addr++;
+ if(ms == 255) ms = 500;
+ sleep_ms(ms);
+ }
+ }
+}
+
+static void ST7735_SetAddressWindow(uint8_t x0, uint8_t y0, uint8_t x1, uint8_t y1) {
+ // column address set
+ ST7735_WriteCommand(ST7735_CASET);
+ uint8_t data[] = { 0x00, x0 + ST7735_XSTART, 0x00, x1 + ST7735_XSTART };
+ ST7735_WriteData(data, sizeof(data));
+
+ // row address set
+ ST7735_WriteCommand(ST7735_RASET);
+ data[1] = y0 + ST7735_YSTART;
+ data[3] = y1 + ST7735_YSTART;
+ ST7735_WriteData(data, sizeof(data));
+
+ // write to RAM
+ ST7735_WriteCommand(ST7735_RAMWR);
+}
+
+void ST7735_Init() {
+ spi_init(spi1, 12000 * 1000);
+ gpio_set_function(EPD_CLK_PIN, GPIO_FUNC_SPI);
+ gpio_set_function(EPD_MOSI_PIN, GPIO_FUNC_SPI);
+
+ // GPIO Config
+ gpio_init(EPD_RST_PIN);
+ gpio_set_dir(EPD_RST_PIN, GPIO_OUT);
+ gpio_init(EPD_DC_PIN);
+ gpio_set_dir(EPD_DC_PIN, GPIO_OUT);
+ gpio_init(EPD_CS_PIN);
+ gpio_set_dir(EPD_CS_PIN, GPIO_OUT);
+
+ gpio_put(EPD_CS_PIN, 1);
+
+
+ ST7735_Select();
+ ST7735_Reset();
+ ST7735_ExecuteCommandList(init_cmds1);
+ ST7735_ExecuteCommandList(init_cmds2);
+ ST7735_ExecuteCommandList(init_cmds3);
+ ST7735_Unselect();
+}
+
+void ST7735_DrawPixel(uint16_t x, uint16_t y, uint16_t color) {
+ if((x >= ST7735_WIDTH) || (y >= ST7735_HEIGHT))
+ return;
+
+ ST7735_Select();
+
+ ST7735_SetAddressWindow(x, y, x+1, y+1);
+ uint8_t data[] = { color >> 8, color & 0xFF };
+ ST7735_WriteData(data, sizeof(data));
+
+ ST7735_Unselect();
+}
+
+void ST7735_FillRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h, uint16_t color) {
+ // clipping
+ if((x >= ST7735_WIDTH) || (y >= ST7735_HEIGHT)) return;
+ if((x + w - 1) >= ST7735_WIDTH) w = ST7735_WIDTH - x;
+ if((y + h - 1) >= ST7735_HEIGHT) h = ST7735_HEIGHT - y;
+
+ ST7735_Select();
+ ST7735_SetAddressWindow(x, y, x+w-1, y+h-1);
+
+ uint8_t data[] = { color >> 8, color & 0xFF };
+ //HAL_GPIO_WritePin(ST7735_DC_GPIO_Port, ST7735_DC_Pin, GPIO_PIN_SET);
+
+ gpio_put(EPD_DC_PIN, 1);
+ for(y = h; y > 0; y--) {
+ for(x = w; x > 0; x--) {
+ // HAL_SPI_Transmit(&ST7735_spi1, data, sizeof(data), HAL_MAX_DELAY);
+ spi_write_blocking(spi1, data, sizeof(data));
+ }
+ }
+
+ ST7735_Unselect();
+}
+
+void ST7735_FillScreen(uint16_t color) {
+ ST7735_FillRectangle(0, 0, ST7735_WIDTH, ST7735_HEIGHT, color);
+}
+
+void ST7735_DrawImage(uint16_t x, uint16_t y, uint16_t w, uint16_t h, const uint8_t* data) {
+ ST7735_Select();
+ ST7735_SetAddressWindow(x, y, x+w-1, y+h-1);
+ ST7735_WriteData((uint8_t*)data, sizeof(uint16_t)*w*h);
+ ST7735_Unselect();
+}
+
+void ST7735_InvertColors(bool invert) {
+ ST7735_Select();
+ ST7735_WriteCommand(invert ? ST7735_INVON : ST7735_INVOFF);
+ ST7735_Unselect();
+}
+
+void ST7735_WriteString(uint16_t x, uint16_t y, const uint8_t *font, const char* str, uint16_t color, uint16_t bgcolor) {
+ ST7735_Select();
+
+ while(*str) {
+ uint32_t fx, fy, b;
+
+ // We are now trying to draw a transposed font the correct way round. Suffer.
+ ST7735_SetAddressWindow(x, y, x+3, y+5);
+
+ for(fy = 0; fy < 6; fy++) {
+ for(fx = 0; fx < 4; fx++) {
+ // First line of the font.
+ int font_start_offset = ((*str) - 32);
+ b = font[font_start_offset + ((3 - fx) * 95)]; // Add 95 for each x-offset
+
+ // Shift by y-value
+ if((b << fy) & 0b100000) {
+ uint8_t data[] = { color >> 8, color & 0xFF };
+ ST7735_WriteData(data, sizeof(data));
+ } else {
+ uint8_t data[] = { bgcolor >> 8, bgcolor & 0xFF };
+ ST7735_WriteData(data, sizeof(data));
+ }
+ }
+ }
+
+ x += 5;
+ str++;
+ }
+
+ ST7735_Unselect();
+}
\ No newline at end of file
diff --git a/arkanoid/pico/pico4ml/screen.h b/arkanoid/pico/pico4ml/screen.h
new file mode 100644
index 0000000..849a9cd
--- /dev/null
+++ b/arkanoid/pico/pico4ml/screen.h
@@ -0,0 +1,136 @@
+#ifndef __ST7735_H__
+#define __ST7735_H__
+
+#include <stdbool.h>
+#include "../stdlib.h"
+#include "../hardware/spi.h"
+
+extern int EPD_RST_PIN;
+extern int EPD_DC_PIN;
+extern int EPD_CS_PIN;
+extern int EPD_CLK_PIN;
+extern int EPD_MOSI_PIN;
+
+#define ST7735_MADCTL_MY 0x80
+#define ST7735_MADCTL_MX 0x40
+#define ST7735_MADCTL_MV 0x20
+#define ST7735_MADCTL_ML 0x10
+#define ST7735_MADCTL_RGB 0x00
+#define ST7735_MADCTL_BGR 0x08
+#define ST7735_MADCTL_MH 0x04
+#define ST7735_RES_Pin GPIO_PIN_7
+#define ST7735_RES_GPIO_Port GPIOC
+#define ST7735_CS_Pin GPIO_PIN_6
+#define ST7735_CS_GPIO_Port GPIOB
+#define ST7735_DC_Pin GPIO_PIN_9
+#define ST7735_DC_GPIO_Port GPIOA
+
+// mini 160x80 display (it's unlikely you want the default orientation)
+
+#define ST7735_IS_160X80 1
+#define ST7735_XSTART 24
+#define ST7735_YSTART 0
+#define ST7735_WIDTH 80
+#define ST7735_HEIGHT 160
+//#define ST7735_ROTATION (ST7735_MADCTL_MX | ST7735_MADCTL_MY | ST7735_MADCTL_BGR)
+#define ST7735_ROTATION ( ST7735_MADCTL_BGR)
+
+// mini 160x80, rotate left
+/*
+#define ST7735_IS_160X80 1
+#define ST7735_XSTART 1
+#define ST7735_YSTART 26
+#define ST7735_WIDTH 160
+#define ST7735_HEIGHT 80
+#define ST7735_ROTATION (ST7735_MADCTL_MX | ST7735_MADCTL_MV | ST7735_MADCTL_BGR)
+*/
+
+// mini 160x80, rotate right
+/*
+#define ST7735_IS_160X80 1
+#define ST7735_XSTART 0
+#define ST7735_YSTART 24
+#define ST7735_WIDTH 160
+#define ST7735_HEIGHT 80
+#define ST7735_ROTATION (ST7735_MADCTL_MY | ST7735_MADCTL_MV | ST7735_MADCTL_BGR)
+*/
+/****************************/
+
+#define ST7735_NOP 0x00
+#define ST7735_SWRESET 0x01
+#define ST7735_RDDID 0x04
+#define ST7735_RDDST 0x09
+
+#define ST7735_SLPIN 0x10
+#define ST7735_SLPOUT 0x11
+#define ST7735_PTLON 0x12
+#define ST7735_NORON 0x13
+
+#define ST7735_INVOFF 0x20
+#define ST7735_INVON 0x21
+#define ST7735_DISPOFF 0x28
+#define ST7735_DISPON 0x29
+#define ST7735_CASET 0x2A
+#define ST7735_RASET 0x2B
+#define ST7735_RAMWR 0x2C
+#define ST7735_RAMRD 0x2E
+
+#define ST7735_PTLAR 0x30
+#define ST7735_COLMOD 0x3A
+#define ST7735_MADCTL 0x36
+
+#define ST7735_FRMCTR1 0xB1
+#define ST7735_FRMCTR2 0xB2
+#define ST7735_FRMCTR3 0xB3
+#define ST7735_INVCTR 0xB4
+#define ST7735_DISSET5 0xB6
+
+#define ST7735_PWCTR1 0xC0
+#define ST7735_PWCTR2 0xC1
+#define ST7735_PWCTR3 0xC2
+#define ST7735_PWCTR4 0xC3
+#define ST7735_PWCTR5 0xC4
+#define ST7735_VMCTR1 0xC5
+
+#define ST7735_RDID1 0xDA
+#define ST7735_RDID2 0xDB
+#define ST7735_RDID3 0xDC
+#define ST7735_RDID4 0xDD
+
+#define ST7735_PWCTR6 0xFC
+
+#define ST7735_GMCTRP1 0xE0
+#define ST7735_GMCTRN1 0xE1
+
+// Color definitions
+#define ST7735_BLACK 0x0000
+#define ST7735_BLUE 0x001F
+#define ST7735_RED 0xF800
+#define ST7735_GREEN 0x07E0
+#define ST7735_CYAN 0x07FF
+#define ST7735_MAGENTA 0xF81F
+#define ST7735_YELLOW 0xFFE0
+#define ST7735_WHITE 0xFFFF
+#define ST7735_COLOR565(r, g, b) (((r & 0xF8) << 8) | ((g & 0xFC) << 3) | ((b & 0xF8) >> 3))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// call before initializing any SPI devices
+void ST7735_Unselect();
+
+void ST7735_Init(void);
+void ST7735_DrawPixel(uint16_t x, uint16_t y, uint16_t color);
+void ST7735_FillRectangle(uint16_t x, uint16_t y, uint16_t w, uint16_t h,
+ uint16_t color);
+void ST7735_FillScreen(uint16_t color);
+void ST7735_DrawImage(uint16_t x, uint16_t y, uint16_t w, uint16_t h,
+ const uint8_t *data);
+void ST7735_InvertColors(bool invert);
+void ST7735_WriteString(uint16_t x, uint16_t y, const uint8_t *font, const char* str, uint16_t color, uint16_t bgcolor);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // __ST7735_H__
diff --git a/arkanoid/pico/pico_bootsel_via_double_reset.c b/arkanoid/pico/pico_bootsel_via_double_reset.c
new file mode 100644
index 0000000..7321f2d
--- /dev/null
+++ b/arkanoid/pico/pico_bootsel_via_double_reset.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "time.h"
+#include "bootrom.h"
+#include "binary_info.h"
+
+// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS, Window of opportunity for a second press of a reset button to enter BOOTSEL mode (milliseconds), type=int, default=200, group=pico_bootsel_via_double_reset
+#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS
+#define PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS 200
+#endif
+
+// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via reset double tap, type=int, min=0, max=29, group=pico_bootsel_via_double_reset
+
+// PICO_CONFIG: PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK, Optionally disable either the mass storage interface (bit 0) or the PICOBOOT interface (bit 1) when entering BOOTSEL mode via double reset, type=int, min=0, max=3, default=0, group=pico_bootsel_via_double_reset
+#ifndef PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK
+#define PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK 0u
+#endif
+
+/** \defgroup pico_bootsel_via_double_reset pico_bootsel_via_double_reset
+ *
+ * When the 'pico_bootsel_via_double_reset' library is linked, a function is
+ * injected before main() which will detect when the system has been reset
+ * twice in quick succession, and enter the USB ROM bootloader (BOOTSEL mode)
+ * when this happens. This allows a double tap of a reset button on a
+ * development board to be used to enter the ROM bootloader, provided this
+ * library is always linked.
+ */
+
+#if !PICO_NO_BI_BOOTSEL_VIA_DOUBLE_RESET
+bi_decl(bi_program_feature("double reset -> BOOTSEL"));
+#endif
+
+// Doesn't make any sense for a RAM only binary
+#if !PICO_NO_FLASH
+static const uint32_t magic_token[] = {
+ 0xf01681de, 0xbd729b29, 0xd359be7a,
+};
+
+static uint32_t __uninitialized_ram(magic_location)[count_of(magic_token)];
+
+/* Check for double reset and enter BOOTSEL mode if detected
+ *
+ * This function is registered to run automatically before main(). The
+ * algorithm is:
+ *
+ * 1. Check for magic token in memory; enter BOOTSEL mode if found.
+ * 2. Initialise that memory with that magic token.
+ * 3. Do nothing for a short while (few hundred ms).
+ * 4. Clear the magic token.
+ * 5. Continue with normal boot.
+ *
+ * Resetting the device twice quickly will interrupt step 3, leaving the token
+ * in place so that the second boot will go to the bootloader.
+ */
+static void __attribute__((constructor)) boot_double_tap_check(void) {
+ for (uint i = 0; i < count_of(magic_token); i++) {
+ if (magic_location[i] != magic_token[i]) {
+ // Arm, wait, then disarm and continue booting
+ for (i = 0; i < count_of(magic_token); i++) {
+ magic_location[i] = magic_token[i];
+ }
+ busy_wait_us(PICO_BOOTSEL_VIA_DOUBLE_RESET_TIMEOUT_MS * 1000);
+ magic_location[0] = 0;
+ return;
+ }
+ }
+ // Detected a double reset, so enter USB bootloader
+ magic_location[0] = 0;
+#ifdef PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED
+ const uint32_t led_mask = 1u << PICO_BOOTSEL_VIA_DOUBLE_RESET_ACTIVITY_LED;
+#else
+ const uint32_t led_mask = 0u;
+#endif
+ reset_usb_boot(
+ led_mask,
+ PICO_BOOTSEL_VIA_DOUBLE_RESET_INTERFACE_DISABLE_MASK
+ );
+}
+
+#endif
diff --git a/arkanoid/pico/pico_malloc.c b/arkanoid/pico/pico_malloc.c
new file mode 100644
index 0000000..8a3118c
--- /dev/null
+++ b/arkanoid/pico/pico_malloc.c
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include "pico.h"
+#include "malloc.h"
+
+#if PICO_USE_MALLOC_MUTEX
+#include "mutex.h"
+auto_init_mutex(malloc_mutex);
+#endif
+
+extern void *__real_malloc(size_t size);
+extern void *__real_calloc(size_t count, size_t size);
+extern void __real_free(void *mem);
+
+extern char __StackLimit; /* Set by linker. */
+
+static inline void check_alloc(__unused void *mem, __unused uint size) {
+#if PICO_MALLOC_PANIC
+ if (!mem || (((char *)mem) + size) > &__StackLimit) {
+ panic("Out of memory");
+ }
+#endif
+}
+
+void *__wrap_malloc(size_t size) {
+#if PICO_USE_MALLOC_MUTEX
+ mutex_enter_blocking(&malloc_mutex);
+#endif
+ void *rc = __real_malloc(size);
+#if PICO_USE_MALLOC_MUTEX
+ mutex_exit(&malloc_mutex);
+#endif
+#if PICO_DEBUG_MALLOC
+ if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) {
+ printf("malloc %d %p->%p\n", (uint) size, rc, ((uint8_t *) rc) + size);
+ }
+#endif
+ check_alloc(rc, size);
+ return rc;
+}
+
+void *__wrap_calloc(size_t count, size_t size) {
+#if PICO_USE_MALLOC_MUTEX
+ mutex_enter_blocking(&malloc_mutex);
+#endif
+ void *rc = __real_calloc(count, size);
+#if PICO_USE_MALLOC_MUTEX
+ mutex_exit(&malloc_mutex);
+#endif
+#if PICO_DEBUG_MALLOC
+ if (!rc || ((uint8_t *)rc) + size > (uint8_t*)PICO_DEBUG_MALLOC_LOW_WATER) {
+ printf("calloc %d %p->%p\n", (uint) (count * size), rc, ((uint8_t *) rc) + size);
+ }
+#endif
+ check_alloc(rc, size);
+ return rc;
+}
+
+void __wrap_free(void *mem) {
+#if PICO_USE_MALLOC_MUTEX
+ mutex_enter_blocking(&malloc_mutex);
+#endif
+ __real_free(mem);
+#if PICO_USE_MALLOC_MUTEX
+ mutex_exit(&malloc_mutex);
+#endif
+}
diff --git a/arkanoid/pico/platform.c b/arkanoid/pico/platform.c
new file mode 100644
index 0000000..9bbcf26
--- /dev/null
+++ b/arkanoid/pico/platform.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "pico.h"
+#include "hardware/address_mapped.h"
+#include "hardware/regs/tbman.h"
+#include "hardware/regs/sysinfo.h"
+
+// Note we leave the FPGA check in by default so that we can run bug repro
+// binaries coming in from the wild on the FPGA platform. It takes up around
+// 48 bytes if you include all the calls, so you can pass PICO_NO_FPGA_CHECK=1
+// to remove it. The FPGA check is used to skip initialisation of hardware
+// (mainly clock generators and oscillators) that aren't present on FPGA.
+
+#if !PICO_NO_FPGA_CHECK
+// Inline stub provided in header if this code is unused (so folding can be
+// done in each TU instead of relying on LTO)
+bool running_on_fpga() {
+ return !!((*(io_ro_32 *)TBMAN_BASE) & TBMAN_PLATFORM_FPGA_BITS);
+}
+#endif
+
+#define MANUFACTURER_RPI 0x927
+#define PART_RP2 0x2
+
+uint8_t rp2040_chip_version() {
+ // First register of sysinfo is chip id
+ uint32_t chip_id = *((io_ro_32*)(SYSINFO_BASE + SYSINFO_CHIP_ID_OFFSET));
+ uint32_t __unused manufacturer = chip_id & SYSINFO_CHIP_ID_MANUFACTURER_BITS;
+ uint32_t __unused part = (chip_id & SYSINFO_CHIP_ID_PART_BITS) >> SYSINFO_CHIP_ID_PART_LSB;
+ assert(manufacturer == MANUFACTURER_RPI);
+ assert(part == PART_RP2);
+ // Version 1 == B0/B1
+ uint version = (chip_id & SYSINFO_CHIP_ID_REVISION_BITS) >> SYSINFO_CHIP_ID_REVISION_LSB;
+ return (uint8_t)version;
+}
\ No newline at end of file
diff --git a/arkanoid/pico/platform.h b/arkanoid/pico/platform.h
new file mode 100644
index 0000000..791cab8
--- /dev/null
+++ b/arkanoid/pico/platform.h
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_PLATFORM_H_
+#define _PICO_PLATFORM_H_
+
+/** \file platform.h
+ * \defgroup pico_platform pico_platform
+ *
+ * Macros and definitions (and functions when included by non assembly code) for the RP2 family device / architecture
+ * to provide a common abstraction over low level compiler / platform specifics.
+ *
+ * This header may be included by assembly code
+ */
+
+#include "hardware/platform_defs.h"
+
+// Marker for builds targeting the RP2040
+#define PICO_RP2040 1
+
+// PICO_CONFIG: PICO_STACK_SIZE, Stack Size, min=0x100, default=0x800, advanced=true, group=pico_platform
+#ifndef PICO_STACK_SIZE
+#define PICO_STACK_SIZE _u(0x800)
+#endif
+
+// PICO_CONFIG: PICO_HEAP_SIZE, Heap size to reserve, min=0x100, default=0x800, advanced=true, group=pico_platform
+#ifndef PICO_HEAP_SIZE
+#define PICO_HEAP_SIZE _u(0x800)
+#endif
+
+// PICO_CONFIG: PICO_NO_RAM_VECTOR_TABLE, Enable/disable the RAM vector table, type=bool, default=0, advanced=true, group=pico_platform
+#ifndef PICO_NO_RAM_VECTOR_TABLE
+#define PICO_NO_RAM_VECTOR_TABLE 0
+#endif
+
+// PICO_CONFIG: PICO_RP2040_B0_SUPPORTED, Whether to include any specific software support for RP2040 B0 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B0_SUPPORTED
+#define PICO_RP2040_B0_SUPPORTED 1
+#endif
+
+// PICO_CONFIG: PICO_FLOAT_SUPPORT_ROM_V1, Include float support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_FLOAT_SUPPORT_ROM_V1
+#define PICO_FLOAT_SUPPORT_ROM_V1 1
+#endif
+
+// PICO_CONFIG: PICO_DOUBLE_SUPPORT_ROM_V1, Include double support code for RP2040 B0 when that chip revision is supported , type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_DOUBLE_SUPPORT_ROM_V1
+#define PICO_DOUBLE_SUPPORT_ROM_V1 1
+#endif
+
+
+// PICO_CONFIG: PICO_RP2040_B1_SUPPORTED, Whether to include any specific software support for RP2040 B1 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B1_SUPPORTED
+#define PICO_RP2040_B1_SUPPORTED 1
+#endif
+
+// PICO_CONFIG: PICO_RP2040_B2_SUPPORTED, Whether to include any specific software support for RP2040 B2 revision, type=bool, default=1, advanced=true, group=pico_platform
+#ifndef PICO_RP2040_B2_SUPPORTED
+#define PICO_RP2040_B2_SUPPORTED 1
+#endif
+
+// --- remainder of file is not included by assembly code ---
+
+#ifndef __ASSEMBLER__
+
+#include <sys/cdefs.h>
+#include "junk/types.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*! \brief Marker for an interrupt handler
+ * \ingroup pico_platform
+ * For example an IRQ handler function called my_interrupt_handler:
+ *
+ * void __isr my_interrupt_handler(void) {
+ */
+#define __isr
+
+/*! \brief Section attribute macro for placement in RAM after the `.data` section
+ * \ingroup pico_platform
+ *
+ * For example a 400 element `uint32_t` array placed after the .data section
+ *
+ * uint32_t __after_data("my_group_name") a_big_array[400];
+ *
+ * The section attribute is `.after_data.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ * garbage-collected independently
+ */
+#define __after_data(group) __attribute__((section(".after_data." group)))
+
+/*! \brief Section attribute macro for placement not in flash (i.e in RAM)
+ * \ingroup pico_platform
+ *
+ * For example a 3 element `uint32_t` array placed in RAM (even though it is `static const`)
+ *
+ * static const uint32_t __not_in_flash("my_group_name") an_array[3];
+ *
+ * The section attribute is `.time_critical.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ * garbage-collected independently
+ */
+#define __not_in_flash(group) __attribute__((section(".time_critical." group)))
+
+/*! \brief Section attribute macro for placement in the SRAM bank 4 (known as "scratch X")
+ * \ingroup pico_platform
+ *
+ * Scratch X is commonly used for critical data and functions accessed only by one core (when only
+ * one core is accessing the RAM bank, there is no opportunity for stalls)
+ *
+ * For example a `uint32_t` variable placed in "scratch X"
+ *
+ * uint32_t __scratch_x("my_group_name") foo = 23;
+ *
+ * The section attribute is `.scratch_x.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ * garbage-collected independently
+ */
+#define __scratch_x(group) __attribute__((section(".scratch_x." group)))
+
+/*! \brief Section attribute macro for placement in the SRAM bank 5 (known as "scratch Y")
+ * \ingroup pico_platform
+ *
+ * Scratch Y is commonly used for critical data and functions accessed only by one core (when only
+ * one core is accessing the RAM bank, there is no opportunity for stalls)
+ *
+ * For example a `uint32_t` variable placed in "scratch Y"
+ *
+ * uint32_t __scratch_y("my_group_name") foo = 23;
+ *
+ * The section attribute is `.scratch_y.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ * garbage-collected independently
+ */
+#define __scratch_y(group) __attribute__((section(".scratch_y." group)))
+
+/*! \brief Section attribute macro for data that is to be left uninitialized
+ * \ingroup pico_platform
+ *
+ * Data marked this way will retain its value across a reset (normally uninitialized data - in the .bss
+ * section) is initialized to zero during runtime initialization
+ *
+ * For example a `uint32_t` foo that will retain its value if the program is restarted by reset.
+ *
+ * uint32_t __uninitialized_ram("my_group_name") foo;
+ *
+ * The section attribute is `.uninitialized_ram.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ * garbage-collected independently
+ */
+#define __uninitialized_ram(group) __attribute__((section(".uninitialized_ram." #group))) group
+
+/*! \brief Section attribute macro for placement in flash even in a COPY_TO_RAM binary
+ * \ingroup pico_platform
+ *
+ * For example a `uint32_t` variable explicitly placed in flash (it will hard fault if you attempt to write it!)
+ *
+ * uint32_t __in_flash("my_group_name") foo = 23;
+ *
+ * The section attribute is `.flashdata.<group>`
+ *
+ * \param group a string suffix to use in the section name to distinguish groups that can be linker
+ * garbage-collected independently
+ */
+#define __in_flash(group) __attribute__((section(".flashdata" group)))
+
+/*! \brief Indicates a function should not be stored in flash
+ * \ingroup pico_platform
+ *
+ * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined
+ * into a flash function by the compiler)
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ * void __not_in_flash_func(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ *
+ * \see __no_inline_not_in_flash_func
+ */
+#define __not_in_flash_func(func_name) __not_in_flash(__STRING(func_name)) func_name
+
+/*! \brief Indicates a function is time/latency critical and should not run from flash
+ * \ingroup pico_platform
+ *
+ * Decorates a function name, such that the function will execute from RAM (assuming it is not inlined
+ * into a flash function by the compiler) to avoid possible flash latency. Currently this macro is identical
+ * in implementation to `__not_in_flash_func`, however the semantics are distinct and a `__time_critical_func`
+ * may in the future be treated more specially to reduce the overhead when calling such function from a flash
+ * function.
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ * void __time_critical(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ *
+ * \see __not_in_flash_func
+ */
+#define __time_critical_func(func_name) __not_in_flash_func(func_name)
+
+/*! \brief Indicate a function should not be stored in flash and should not be inlined
+ * \ingroup pico_platform
+ *
+ * Decorates a function name, such that the function will execute from RAM, explicitly marking it as
+ * noinline to prevent it being inlined into a flash function by the compiler
+ *
+ * For example a function called my_func taking an int parameter:
+ *
+ * void __no_inline_not_in_flash_func(my_func)(int some_arg) {
+ *
+ * The function is placed in the `.time_critical.<func_name>` linker section
+ */
+#define __no_inline_not_in_flash_func(func_name) __noinline __not_in_flash_func(func_name)
+
+#define __packed_aligned __packed __aligned(4)
+
+/*! \brief Attribute to force inlining of a function regardless of optimization level
+ * \ingroup pico_platform
+ *
+ * For example my_function here will always be inlined:
+ *
+ * int __force_inline my_function(int x) {
+ *
+ */
+#if defined(__GNUC__) && __GNUC__ <= 7
+#define __force_inline inline __always_inline
+#else
+#define __force_inline __always_inline
+#endif
+
+/*! \brief Macro to determine the number of elements in an array
+ * \ingroup pico_platform
+ */
+#ifndef count_of
+#define count_of(a) (sizeof(a)/sizeof((a)[0]))
+#endif
+
+/*! \brief Macro to return the maximum of two comparable values
+ * \ingroup pico_platform
+ */
+#ifndef MAX
+#define MAX(a, b) ((a)>(b)?(a):(b))
+#endif
+
+/*! \brief Macro to return the minimum of two comparable values
+ * \ingroup pico_platform
+ */
+#ifndef MIN
+#define MIN(a, b) ((b)>(a)?(a):(b))
+#endif
+
+/*! \brief Execute a breakpoint instruction
+ * \ingroup pico_platform
+ */
+static inline void __breakpoint(void) {
+ __asm__("bkpt #0");
+}
+
+/*! \brief Ensure that the compiler does not move memory access across this method call
+ * \ingroup pico_platform
+ *
+ * For example in the following code:
+ *
+ * *some_memory_location = var_a;
+ * __compiler_memory_barrier();
+ * uint32_t var_b = *some_other_memory_location
+ *
+ * The compiler will not move the load from `some_other_memory_location` above the memory barrier (which it otherwise
+ * might - even above the memory store!)
+ */
+__force_inline static void __compiler_memory_barrier(void) {
+ __asm__ volatile ("" : : : "memory");
+}
+
+/*! \brief Macro for converting memory addresses to 32 bit addresses suitable for DMA
+ * \ingroup pico_platform
+ *
+ * This is just a cast to `uintptr_t` on the RP2040, however you may want to use this when developing code
+ * that also runs in "host" mode. If the host mode is 64 bit and you are embedding data pointers
+ * in other data (e.g. DMA chaining), then there is a need in "host" mode to convert a 64 bit native
+ * pointer to a 32 bit value for storage, which can be done using this macro.
+ */
+#define host_safe_hw_ptr(x) ((uintptr_t)(x))
+#define native_safe_hw_ptr(x) host_safe_hw_ptr(x)
+
+
+/*! \brief Panics with the message "Unsupported"
+ * \ingroup pico_platform
+ * \see panic
+ */
+void __attribute__((noreturn)) panic_unsupported(void);
+
+/*! \brief Displays a panic message and halts execution
+ * \ingroup pico_platform
+ *
+ * An attempt is made to output the message to all registered STDOUT drivers
+ * after which this method executes a BKPT instruction.
+ *
+ * @param fmt format string (printf-like)
+ * @param ... printf-like arguments
+ */
+void __attribute__((noreturn)) panic(const char *fmt, ...);
+
+// PICO_CONFIG: PICO_NO_FPGA_CHECK, Remove the FPGA platform check for small code size reduction, type=bool, default=0, advanced=true, group=pico_runtime
+#ifndef PICO_NO_FPGA_CHECK
+#define PICO_NO_FPGA_CHECK 0
+#endif
+
+#if PICO_NO_FPGA_CHECK
+static inline bool running_on_fpga(void) {return false;}
+#else
+bool running_on_fpga(void);
+#endif
+
+/*! \brief Returns the RP2040 chip revision number
+ * \ingroup pico_platform
+ * @return the RP2040 chip revision number (1 for B0/B1, 2 for B2)
+ */
+uint8_t rp2040_chip_version(void);
+
+/*! \brief Returns the RP2040 rom version number
+ * \ingroup pico_platform
+ * @return the RP2040 rom version number (1 for RP2040-B0, 2 for RP2040-B1, 3 for RP2040-B2)
+ */
+static inline uint8_t rp2040_rom_version(void) {
+ return *(uint8_t*)0x13;
+}
+
+/*! \brief No-op function for the body of tight loops
+ * \ingroup pico_platform
+ *
+ * Np-op function intended to be called by any tight hardware polling loop. Using this ubiquitously
+ * makes it much easier to find tight loops, but also in the future \#ifdef-ed support for lockup
+ * debugging might be added
+ */
+static __force_inline void tight_loop_contents(void) {}
+
+/*! \brief Multiply two integers using an assembly `MUL` instruction
+ * \ingroup pico_platform
+ *
+ * This multiplies a by b using multiply instruction using the ARM mul instruction regardless of values (the compiler
+ * might otherwise choose to perform shifts/adds), i.e. this is a 1 cycle operation.
+ *
+ * \param a the first operand
+ * \param b the second operand
+ * \return a * b
+ */
+__force_inline static int32_t __mul_instruction(int32_t a, int32_t b) {
+ asm ("mul %0, %1" : "+l" (a) : "l" (b) : );
+ return a;
+}
+
+/*! \brief multiply two integer values using the fastest method possible
+ * \ingroup pico_platform
+ *
+ * Efficiently multiplies value a by possibly constant value b.
+ *
+ * If b is known to be constant and not zero or a power of 2, then a mul instruction is used rather than gcc's default
+ * which is often a slow combination of shifts and adds. If b is a power of 2 then a single shift is of course preferable
+ * and will be used
+ *
+ * \param a the first operand
+ * \param b the second operand
+ * \return a * b
+ */
+#define __fast_mul(a, b) __builtin_choose_expr(__builtin_constant_p(b) && !__builtin_constant_p(a), \
+(__builtin_popcount(b) >= 2 ? __mul_instruction(a,b) : (a)*(b)), \
+(a)*(b))
+
+/*! \brief Utility macro to assert two types are equivalent.
+ * \ingroup pico_platform
+ *
+ * This macro can be useful in other macros along with `typeof` to assert that two parameters are of equivalent type
+ * (or that a single parameter is of an expected type)
+ */
+#define __check_type_compatible(type_a, type_b) static_assert(__builtin_types_compatible_p(type_a, type_b), __STRING(type_a) " is not compatible with " __STRING(type_b));
+
+/*! \brief Get the current exception level on this core
+ * \ingroup pico_platform
+ *
+ * \return the exception number if the CPU is handling an exception, or 0 otherwise
+ */
+uint __get_current_exception(void);
+
+#define WRAPPER_FUNC(x) __wrap_ ## x
+#define REAL_FUNC(x) __real_ ## x
+
+#ifdef __cplusplus
+}
+#endif
+
+#else // __ASSEMBLER__
+
+#define WRAPPER_FUNC_NAME(x) __wrap_##x
+#define SECTION_NAME(x) .text.##x
+#define RAM_SECTION_NAME(x) .time_critical.##x
+
+#endif // !__ASSEMBLER__
+
+#endif
diff --git a/arkanoid/pico/queue.c b/arkanoid/pico/queue.c
new file mode 100644
index 0000000..485e250
--- /dev/null
+++ b/arkanoid/pico/queue.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdlib.h>
+#include <string.h>
+#include "queue.h"
+
+void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num) {
+ lock_init(&q->core, spinlock_num);
+ q->data = (uint8_t *)calloc(element_count + 1, element_size);
+ q->element_count = (uint16_t)element_count;
+ q->element_size = (uint16_t)element_size;
+ q->wptr = 0;
+ q->rptr = 0;
+}
+
+void queue_free(queue_t *q) {
+ free(q->data);
+}
+
+static inline void *element_ptr(queue_t *q, uint index) {
+ assert(index <= q->element_count);
+ return q->data + index * q->element_size;
+}
+
+static inline uint16_t inc_index(queue_t *q, uint16_t index) {
+ if (++index > q->element_count) { // > because we have element_count + 1 elements
+ index = 0;
+ }
+
+#if PICO_QUEUE_MAX_LEVEL
+ uint16_t level = queue_get_level_unsafe(q);
+ if (level > q->max_level) {
+ q->max_level = level;
+ }
+#endif
+
+ return index;
+}
+
+static bool queue_add_internal(queue_t *q, const void *data, bool block) {
+ do {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ if (queue_get_level_unsafe(q) != q->element_count) {
+ memcpy(element_ptr(q, q->wptr), data, q->element_size);
+ q->wptr = inc_index(q, q->wptr);
+ lock_internal_spin_unlock_with_notify(&q->core, save);
+ return true;
+ }
+ if (block) {
+ lock_internal_spin_unlock_with_wait(&q->core, save);
+ } else {
+ spin_unlock(q->core.spin_lock, save);
+ return false;
+ }
+ } while (true);
+}
+
+static bool queue_remove_internal(queue_t *q, void *data, bool block) {
+ do {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ if (queue_get_level_unsafe(q) != 0) {
+ memcpy(data, element_ptr(q, q->rptr), q->element_size);
+ q->rptr = inc_index(q, q->rptr);
+ lock_internal_spin_unlock_with_notify(&q->core, save);
+ return true;
+ }
+ if (block) {
+ lock_internal_spin_unlock_with_wait(&q->core, save);
+ } else {
+ spin_unlock(q->core.spin_lock, save);
+ return false;
+ }
+ } while (true);
+}
+
+static bool queue_peek_internal(queue_t *q, void *data, bool block) {
+ do {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ if (queue_get_level_unsafe(q) != 0) {
+ memcpy(data, element_ptr(q, q->rptr), q->element_size);
+ lock_internal_spin_unlock_with_notify(&q->core, save);
+ return true;
+ }
+ if (block) {
+ lock_internal_spin_unlock_with_wait(&q->core, save);
+ } else {
+ spin_unlock(q->core.spin_lock, save);
+ return false;
+ }
+ } while (true);
+}
+
+bool queue_try_add(queue_t *q, const void *data) {
+ return queue_add_internal(q, data, false);
+}
+
+bool queue_try_remove(queue_t *q, void *data) {
+ return queue_remove_internal(q, data, false);
+}
+
+bool queue_try_peek(queue_t *q, void *data) {
+ return queue_peek_internal(q, data, false);
+}
+
+void queue_add_blocking(queue_t *q, const void *data) {
+ queue_add_internal(q, data, true);
+}
+
+void queue_remove_blocking(queue_t *q, void *data) {
+ queue_remove_internal(q, data, true);
+}
+
+void queue_peek_blocking(queue_t *q, void *data) {
+ queue_peek_internal(q, data, true);
+}
diff --git a/arkanoid/pico/queue.h b/arkanoid/pico/queue.h
new file mode 100644
index 0000000..4117e41
--- /dev/null
+++ b/arkanoid/pico/queue.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _UTIL_QUEUE_H
+#define _UTIL_QUEUE_H
+
+#include "pico.h"
+#include "hardware/sync.h"
+
+// PICO_CONFIG: PICO_QUEUE_MAX_LEVEL, Maintain a field for the highest level that has been reached by a queue, type=bool, default=0, advanced=true, group=queue
+#ifndef PICO_QUEUE_MAX_LEVEL
+#define PICO_QUEUE_MAX_LEVEL 0
+#endif
+
+/** \file queue.h
+ * \defgroup queue queue
+ * Multi-core and IRQ safe queue implementation.
+ *
+ * Note that this queue stores values of a specified size, and pushed values are copied into the queue
+ * \ingroup pico_util
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "lock_core.h"
+
+typedef struct {
+ lock_core_t core;
+ uint8_t *data;
+ uint16_t wptr;
+ uint16_t rptr;
+ uint16_t element_size;
+ uint16_t element_count;
+#if PICO_QUEUE_MAX_LEVEL
+ uint16_t max_level;
+#endif
+} queue_t;
+
+/*! \brief Initialise a queue with a specific spinlock for concurrency protection
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param element_size Size of each value in the queue
+ * \param element_count Maximum number of entries in the queue
+ * \param spinlock_num The spin ID used to protect the queue
+ */
+void queue_init_with_spinlock(queue_t *q, uint element_size, uint element_count, uint spinlock_num);
+
+/*! \brief Initialise a queue, allocating a (possibly shared) spinlock
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param element_size Size of each value in the queue
+ * \param element_count Maximum number of entries in the queue
+ */
+static inline void queue_init(queue_t *q, uint element_size, uint element_count) {
+ return queue_init_with_spinlock(q, element_size, element_count, next_striped_spin_lock_num());
+}
+
+/*! \brief Destroy the specified queue.
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ *
+ * Does not deallocate the queue_t structure itself.
+ */
+void queue_free(queue_t *q);
+
+/*! \brief Unsafe check of level of the specified queue.
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return Number of entries in the queue
+ *
+ * This does not use the spinlock, so may return incorrect results if the
+ * spin lock is not externally locked
+ */
+static inline uint queue_get_level_unsafe(queue_t *q) {
+ int32_t rc = (int32_t)q->wptr - (int32_t)q->rptr;
+ if (rc < 0) {
+ rc += q->element_count + 1;
+ }
+ return (uint)rc;
+}
+
+/*! \brief Check of level of the specified queue.
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return Number of entries in the queue
+ */
+static inline uint queue_get_level(queue_t *q) {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ uint level = queue_get_level_unsafe(q);
+ spin_unlock(q->core.spin_lock, save);
+ return level;
+}
+
+/*! \brief Returns the highest level reached by the specified queue since it was created
+ * or since the max level was reset
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return Maximum level of the queue
+ */
+#if PICO_QUEUE_MAX_LEVEL
+static inline uint queue_get_max_level(queue_t *q) {
+ return q->max_level;
+}
+#endif
+
+/*! \brief Reset the highest level reached of the specified queue.
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ */
+#if PICO_QUEUE_MAX_LEVEL
+static inline void queue_reset_max_level(queue_t *q) {
+ uint32_t save = spin_lock_blocking(q->core.spin_lock);
+ q->max_level = queue_get_level_unsafe(q);
+ spin_unlock(q->core.spin_lock, save);
+}
+#endif
+
+/*! \brief Check if queue is empty
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return true if queue is empty, false otherwise
+ *
+ * This function is interrupt and multicore safe.
+ */
+static inline bool queue_is_empty(queue_t *q) {
+ return queue_get_level(q) == 0;
+}
+
+/*! \brief Check if queue is full
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \return true if queue is full, false otherwise
+ *
+ * This function is interrupt and multicore safe.
+ */
+static inline bool queue_is_full(queue_t *q) {
+ return queue_get_level(q) == q->element_count;
+}
+
+// nonblocking queue access functions:
+
+/*! \brief Non-blocking add value queue if not full
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to value to be copied into the queue
+ * \return true if the value was added
+ *
+ * If the queue is full this function will return immediately with false, otherwise
+ * the data is copied into a new value added to the queue, and this function will return true.
+ */
+bool queue_try_add(queue_t *q, const void *data);
+
+/*! \brief Non-blocking removal of entry from the queue if non empty
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the removed value
+ * \return true if a value was removed
+ *
+ * If the queue is not empty function will copy the removed value into the location provided and return
+ * immediately with true, otherwise the function will return immediately with false.
+ */
+bool queue_try_remove(queue_t *q, void *data);
+
+/*! \brief Non-blocking peek at the next item to be removed from the queue
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the peeked value
+ * \return true if there was a value to peek
+ *
+ * If the queue is not empty this function will return immediately with true with the peeked entry
+ * copied into the location specified by the data parameter, otherwise the function will return false.
+ */
+bool queue_try_peek(queue_t *q, void *data);
+
+// blocking queue access functions:
+
+/*! \brief Blocking add of value to queue
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to value to be copied into the queue
+ *
+ * If the queue is full this function will block, until a removal happens on the queue
+ */
+void queue_add_blocking(queue_t *q, const void *data);
+
+/*! \brief Blocking remove entry from queue
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the removed value
+ *
+ * If the queue is empty this function will block until a value is added.
+ */
+void queue_remove_blocking(queue_t *q, void *data);
+
+/*! \brief Blocking peek at next value to be removed from queue
+ * \ingroup queue
+ *
+ * \param q Pointer to a queue_t structure, used as a handle
+ * \param data Pointer to the location to receive the peeked value
+ *
+ * If the queue is empty function will block until a value is added
+ */
+void queue_peek_blocking(queue_t *q, void *data);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/reset_interface.c b/arkanoid/pico/reset_interface.c
new file mode 100644
index 0000000..b56ed98
--- /dev/null
+++ b/arkanoid/pico/reset_interface.c
@@ -0,0 +1,112 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "tinyusb/tusb.h"
+
+#include "bootrom.h"
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE && !(PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL || PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT)
+#warning PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE has been selected but neither PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL nor PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT have been selected.
+#endif
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#include "reset_interface.h"
+#include "hardware/watchdog.h"
+#include "tinyusb/usbd_pvt.h"
+
+static uint8_t itf_num;
+
+static void resetd_init(void) {
+}
+
+static void resetd_reset(uint8_t __unused rhport) {
+ itf_num = 0;
+}
+
+static uint16_t resetd_open(uint8_t __unused rhport, tusb_desc_interface_t const *itf_desc, uint16_t max_len) {
+ TU_VERIFY(TUSB_CLASS_VENDOR_SPECIFIC == itf_desc->bInterfaceClass &&
+ RESET_INTERFACE_SUBCLASS == itf_desc->bInterfaceSubClass &&
+ RESET_INTERFACE_PROTOCOL == itf_desc->bInterfaceProtocol, 0);
+
+ uint16_t const drv_len = sizeof(tusb_desc_interface_t);
+ TU_VERIFY(max_len >= drv_len, 0);
+
+ itf_num = itf_desc->bInterfaceNumber;
+ return drv_len;
+}
+
+// Support for parameterized reset via vendor interface control request
+static bool resetd_control_xfer_cb(uint8_t __unused rhport, uint8_t stage, tusb_control_request_t const * request) {
+ // nothing to do with DATA & ACK stage
+ if (stage != CONTROL_STAGE_SETUP) return true;
+
+ if (request->wIndex == itf_num) {
+
+#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL
+ if (request->bRequest == RESET_REQUEST_BOOTSEL) {
+#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED
+ uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED;
+#else
+ uint gpio_mask = 0u;
+#endif
+#if !PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED
+ if (request->wValue & 0x100) {
+ gpio_mask = 1u << (request->wValue >> 9u);
+ }
+#endif
+ reset_usb_boot(gpio_mask, (request->wValue & 0x7f) | PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK);
+ // does not return, otherwise we'd return true
+ }
+#endif
+
+#if PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT
+ if (request->bRequest == RESET_REQUEST_FLASH) {
+ watchdog_reboot(0, 0, PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS);
+ return true;
+ }
+#endif
+
+ }
+ return false;
+}
+
+static bool resetd_xfer_cb(uint8_t __unused rhport, uint8_t __unused ep_addr, xfer_result_t __unused result, uint32_t __unused xferred_bytes) {
+ return true;
+}
+
+static usbd_class_driver_t const _resetd_driver =
+{
+#if CFG_TUSB_DEBUG >= 2
+ .name = "RESET",
+#endif
+ .init = resetd_init,
+ .reset = resetd_reset,
+ .open = resetd_open,
+ .control_xfer_cb = resetd_control_xfer_cb,
+ .xfer_cb = resetd_xfer_cb,
+ .sof = NULL
+};
+
+// Implement callback to add our custom driver
+usbd_class_driver_t const *usbd_app_driver_get_cb(uint8_t *driver_count) {
+ *driver_count = 1;
+ return &_resetd_driver;
+}
+#endif
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE
+// Support for default BOOTSEL reset by changing baud rate
+void tud_cdc_line_coding_cb(__unused uint8_t itf, cdc_line_coding_t const* p_line_coding) {
+ if (p_line_coding->bit_rate == PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE) {
+#ifdef PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED
+ const uint gpio_mask = 1u << PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED;
+#else
+ const uint gpio_mask = 0u;
+#endif
+ reset_usb_boot(gpio_mask, PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK);
+ }
+}
+#endif
+
diff --git a/arkanoid/pico/reset_interface.h b/arkanoid/pico/reset_interface.h
new file mode 100644
index 0000000..b81587a
--- /dev/null
+++ b/arkanoid/pico/reset_interface.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_USB_RESET_INTERFACE_H
+#define _PICO_STDIO_USB_RESET_INTERFACE_H
+
+// definitions have been moved here
+#include "usb_reset_interface.h"
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/runtime.c b/arkanoid/pico/runtime.c
new file mode 100644
index 0000000..09c9999
--- /dev/null
+++ b/arkanoid/pico/runtime.c
@@ -0,0 +1,289 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+#include "pico.h"
+
+#include "hardware/regs/m0plus.h"
+#include "hardware/regs/resets.h"
+#include "hardware/structs/mpu.h"
+#include "hardware/structs/scb.h"
+#include "hardware/structs/padsbank0.h"
+
+#include "hardware/clocks.h"
+#include "hardware/irq.h"
+#include "hardware/resets.h"
+
+#include "mutex.h"
+#include "time.h"
+
+#if LIB_PICO_PRINTF_PICO
+#include "printf.h"
+#else
+#define weak_raw_printf printf
+#define weak_raw_vprintf vprintf
+#endif
+
+#if PICO_ENTER_USB_BOOT_ON_EXIT
+#include "bootrom.h"
+#endif
+
+extern char __StackLimit; /* Set by linker. */
+
+uint32_t __attribute__((section(".ram_vector_table"))) ram_vector_table[48];
+
+// this is called for each thread since they have their own MPU
+void runtime_install_stack_guard(void *stack_bottom) {
+ // this is called b4 runtime_init is complete, so beware printf or assert
+
+ // make sure no one is using the MPU yet
+ if (mpu_hw->ctrl) {
+ // Note that it would be tempting to change this to a panic, but it happens so early, printing is not a good idea
+ __breakpoint();
+ }
+
+ uintptr_t addr = (uintptr_t) stack_bottom;
+ // the minimum we can protect is 32 bytes on a 32 byte boundary, so round up which will
+ // just shorten the valid stack range a tad
+ addr = (addr + 31u) & ~31u;
+
+ // mask is 1 bit per 32 bytes of the 256 byte range... clear the bit for the segment we want
+ uint32_t subregion_select = 0xffu ^ (1u << ((addr >> 5u) & 7u));
+ mpu_hw->ctrl = 5; // enable mpu with background default map
+ mpu_hw->rbar = (addr & (uint)~0xff) | 0x8 | 0;
+ mpu_hw->rasr = 1 // enable region
+ | (0x7 << 1) // size 2^(7 + 1) = 256
+ | (subregion_select << 8)
+ | 0x10000000; // XN = disable instruction fetch; no other bits means no permissions
+}
+
+void runtime_init(void) {
+ // Reset all peripherals to put system into a known state,
+ // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash
+ // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot
+ // - and USB, syscfg, as this disturbs USB-to-SWD on core 1
+ reset_block(~(
+ RESETS_RESET_IO_QSPI_BITS |
+ RESETS_RESET_PADS_QSPI_BITS |
+ RESETS_RESET_PLL_USB_BITS |
+ RESETS_RESET_USBCTRL_BITS |
+ RESETS_RESET_SYSCFG_BITS |
+ RESETS_RESET_PLL_SYS_BITS
+ ));
+
+ // Remove reset from peripherals which are clocked only by clk_sys and
+ // clk_ref. Other peripherals stay in reset until we've configured clocks.
+ unreset_block_wait(RESETS_RESET_BITS & ~(
+ RESETS_RESET_ADC_BITS |
+ RESETS_RESET_RTC_BITS |
+ RESETS_RESET_SPI0_BITS |
+ RESETS_RESET_SPI1_BITS |
+ RESETS_RESET_UART0_BITS |
+ RESETS_RESET_UART1_BITS |
+ RESETS_RESET_USBCTRL_BITS
+ ));
+
+ // pre-init runs really early since we need it even for memcpy and divide!
+ // (basically anything in aeabi that uses bootrom)
+
+ // Start and end points of the constructor list,
+ // defined by the linker script.
+ extern void (*__preinit_array_start)(void);
+ extern void (*__preinit_array_end)(void);
+
+ // Call each function in the list.
+ // We have to take the address of the symbols, as __preinit_array_start *is*
+ // the first function pointer, not the address of it.
+ for (void (**p)(void) = &__preinit_array_start; p < &__preinit_array_end; ++p) {
+ (*p)();
+ }
+
+ // After calling preinit we have enough runtime to do the exciting maths
+ // in clocks_init
+ clocks_init();
+
+ // Peripheral clocks should now all be running
+ unreset_block_wait(RESETS_RESET_BITS);
+
+#if !PICO_IE_26_29_UNCHANGED_ON_RESET
+ // after resetting BANK0 we should disable IE on 26-29
+ hw_clear_alias(padsbank0_hw)->io[26] = hw_clear_alias(padsbank0_hw)->io[27] =
+ hw_clear_alias(padsbank0_hw)->io[28] = hw_clear_alias(padsbank0_hw)->io[29] = PADS_BANK0_GPIO0_IE_BITS;
+#endif
+
+ // this is an array of either mutex_t or recursive_mutex_t (i.e. not necessarily the same size)
+ // however each starts with a lock_core_t, and the spin_lock is initialized to address 1 for a recursive
+ // spinlock and 0 for a regular one.
+
+ static_assert(!(sizeof(mutex_t)&3), "");
+ static_assert(!(sizeof(recursive_mutex_t)&3), "");
+ static_assert(!offsetof(mutex_t, core), "");
+ static_assert(!offsetof(recursive_mutex_t, core), "");
+ extern lock_core_t __mutex_array_start;
+ extern lock_core_t __mutex_array_end;
+
+ for (lock_core_t *l = &__mutex_array_start; l < &__mutex_array_end; ) {
+ if (l->spin_lock) {
+ assert(1 == (uintptr_t)l->spin_lock); // indicator for a recursive mutex
+ recursive_mutex_t *rm = (recursive_mutex_t *)l;
+ recursive_mutex_init(rm);
+ l = &rm[1].core; // next
+ } else {
+ mutex_t *m = (mutex_t *)l;
+ mutex_init(m);
+ l = &m[1].core; // next
+ }
+ }
+
+#if !(PICO_NO_RAM_VECTOR_TABLE || PICO_NO_FLASH)
+ __builtin_memcpy(ram_vector_table, (uint32_t *) scb_hw->vtor, sizeof(ram_vector_table));
+ scb_hw->vtor = (uintptr_t) ram_vector_table;
+#endif
+
+#ifndef NDEBUG
+ if (__get_current_exception()) {
+ // crap; started in exception handler
+ __asm ("bkpt #0");
+ }
+#endif
+
+#if PICO_USE_STACK_GUARDS
+ // install core0 stack guard
+ extern char __StackBottom;
+ runtime_install_stack_guard(&__StackBottom);
+#endif
+
+ spin_locks_reset();
+ irq_init_priorities();
+ alarm_pool_init_default();
+
+ // Start and end points of the constructor list,
+ // defined by the linker script.
+ extern void (*__init_array_start)(void);
+ extern void (*__init_array_end)(void);
+
+ // Call each function in the list.
+ // We have to take the address of the symbols, as __init_array_start *is*
+ // the first function pointer, not the address of it.
+ for (void (**p)(void) = &__init_array_start; p < &__init_array_end; ++p) {
+ (*p)();
+ }
+
+}
+
+void _exit(__unused int status) {
+#if PICO_ENTER_USB_BOOT_ON_EXIT
+ reset_usb_boot(0,0);
+#else
+ while (1) {
+ __breakpoint();
+ }
+#endif
+}
+
+void *_sbrk(int incr) {
+ extern char end; /* Set by linker. */
+ static char *heap_end;
+ char *prev_heap_end;
+
+ if (heap_end == 0)
+ heap_end = &end;
+
+ prev_heap_end = heap_end;
+ char *next_heap_end = heap_end + incr;
+
+ if (__builtin_expect(next_heap_end > (&__StackLimit), false)) {
+#if PICO_USE_OPTIMISTIC_SBRK
+ if (heap_end == &__StackLimit) {
+// errno = ENOMEM;
+ return (char *) -1;
+ }
+ next_heap_end = &__StackLimit;
+#else
+ return (char *) -1;
+#endif
+ }
+
+ heap_end = next_heap_end;
+ return (void *) prev_heap_end;
+}
+
+// exit is not useful... no desire to pull in __call_exitprocs
+void exit(int status) {
+ _exit(status);
+}
+
+// incorrect warning from GCC 6
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wsuggest-attribute=format"
+void __assert_func(const char *file, int line, const char *func, const char *failedexpr) {
+ weak_raw_printf("assertion \"%s\" failed: file \"%s\", line %d%s%s\n",
+ failedexpr, file, line, func ? ", function: " : "",
+ func ? func : "");
+
+ _exit(1);
+}
+
+#pragma GCC diagnostic pop
+
+void __attribute__((noreturn)) panic_unsupported() {
+ panic("not supported");
+}
+
+// PICO_CONFIG: PICO_PANIC_FUNCTION, Name of a function to use in place of the stock panic function or empty string to simply breakpoint on panic, group=pico_runtime
+// note the default is not "panic" it is undefined
+#ifdef PICO_PANIC_FUNCTION
+#define PICO_PANIC_FUNCTION_EMPTY (__CONCAT(PICO_PANIC_FUNCTION, 1) == 1)
+#if !PICO_PANIC_FUNCTION_EMPTY
+extern void __attribute__((noreturn)) __printflike(1, 0) PICO_PANIC_FUNCTION(__unused const char *fmt, ...);
+#endif
+// Use a forwarding method here as it is a little simpler than renaming the symbol as it is used from assembler
+void __attribute__((naked, noreturn)) __printflike(1, 0) panic(__unused const char *fmt, ...) {
+ // if you get an undefined reference here, you didn't define your PICO_PANIC_FUNCTION!
+ __asm (
+ "push {lr}\n"
+#if !PICO_PANIC_FUNCTION_EMPTY
+ "bl " __XSTRING(PICO_PANIC_FUNCTION) "\n"
+#endif
+ "bkpt #0\n"
+ "1: b 1b\n" // loop for ever as we are no return
+ :
+ :
+ :
+ );
+}
+#else
+// todo consider making this try harder to output if we panic early
+// right now, print mutex may be uninitialised (in which case it deadlocks - although after printing "PANIC")
+// more importantly there may be no stdout/UART initialized yet
+// todo we may want to think about where we print panic messages to; writing to USB appears to work
+// though it doesn't seem like we can expect it to... fine for now
+void __attribute__((noreturn)) __printflike(1, 0) panic(const char *fmt, ...) {
+ puts("\n*** PANIC ***\n");
+ if (fmt) {
+#if LIB_PICO_PRINTF_NONE
+ puts(fmt);
+#else
+ va_list args;
+ va_start(args, fmt);
+#if PICO_PRINTF_ALWAYS_INCLUDED
+ vprintf(fmt, args);
+#else
+ weak_raw_vprintf(fmt, args);
+#endif
+ va_end(args);
+ puts("\n");
+#endif
+ }
+
+ _exit(1);
+}
+#endif
+
+void hard_assertion_failure(void) {
+ panic("Hard assert");
+}
diff --git a/arkanoid/pico/runtime.h b/arkanoid/pico/runtime.h
new file mode 100644
index 0000000..752ec6c
--- /dev/null
+++ b/arkanoid/pico/runtime.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_RUNTIME_H
+#define _PICO_RUNTIME_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file runtime.h
+* \defgroup pico_runtime pico_runtime
+* Aggregate runtime support including @ref pico_bit_ops, @ref pico_divider, @ref pico_double, @ref pico_int64_ops, @ref pico_float, @ref pico_malloc, @ref pico_mem_ops and @ref pico_standard_link
+*/
+
+
+void runtime_install_stack_guard(void *stack_bottom);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/sem.c b/arkanoid/pico/sem.c
new file mode 100644
index 0000000..34b3b24
--- /dev/null
+++ b/arkanoid/pico/sem.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "sem.h"
+#include "time.h"
+
+void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits) {
+ lock_init(&sem->core, next_striped_spin_lock_num());
+ sem->permits = initial_permits;
+ sem->max_permits = max_permits;
+ __mem_fence_release();
+}
+
+int __time_critical_func(sem_available)(semaphore_t *sem) {
+ return *(volatile typeof(sem->permits) *) &sem->permits;
+}
+
+void __time_critical_func(sem_acquire_blocking)(semaphore_t *sem) {
+ do {
+ uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+ if (sem->permits > 0) {
+ sem->permits--;
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ break;
+ }
+ lock_internal_spin_unlock_with_wait(&sem->core, save);
+ } while (true);
+}
+
+bool __time_critical_func(sem_acquire_timeout_ms)(semaphore_t *sem, uint32_t timeout_ms) {
+ return sem_acquire_block_until(sem, make_timeout_time_ms(timeout_ms));
+}
+
+bool __time_critical_func(sem_acquire_timeout_us)(semaphore_t *sem, uint32_t timeout_us) {
+ return sem_acquire_block_until(sem, make_timeout_time_us(timeout_us));
+}
+
+bool __time_critical_func(sem_acquire_block_until)(semaphore_t *sem, absolute_time_t until) {
+ do {
+ uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+ if (sem->permits > 0) {
+ sem->permits--;
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ return true;
+ }
+ if (lock_internal_spin_unlock_with_best_effort_wait_or_timeout(&sem->core, save, until)) {
+ return false;
+ }
+ } while (true);
+}
+
+// todo this should really have a blocking variant for when permits are maxed out
+bool __time_critical_func(sem_release)(semaphore_t *sem) {
+ uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+ int32_t count = sem->permits;
+ if (count < sem->max_permits) {
+ sem->permits = (int16_t)(count + 1);
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ return true;
+ } else {
+ spin_unlock(sem->core.spin_lock, save);
+ return false;
+ }
+}
+
+void __time_critical_func(sem_reset)(semaphore_t *sem, int16_t permits) {
+ assert(permits >= 0 && permits <= sem->max_permits);
+ uint32_t save = spin_lock_blocking(sem->core.spin_lock);
+ if (permits > sem->permits) {
+ sem->permits = permits;
+ lock_internal_spin_unlock_with_notify(&sem->core, save);
+ } else {
+ sem->permits = permits;
+ spin_unlock(sem->core.spin_lock, save);
+ }
+}
diff --git a/arkanoid/pico/sem.h b/arkanoid/pico/sem.h
new file mode 100644
index 0000000..446aa5e
--- /dev/null
+++ b/arkanoid/pico/sem.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PLATFORM_SEM_H
+#define _PLATFORM_SEM_H
+
+#include "lock_core.h"
+
+/** \file sem.h
+ * \defgroup sem sem
+ * \ingroup pico_sync
+ * \brief Semaphore API for restricting access to a resource
+ *
+ * A semaphore holds a number of available permits. `sem_acquire` methods will acquire a permit if available
+ * (reducing the available count by 1) or block if the number of available permits is 0.
+ * \ref sem_release() increases the number of available permits by one potentially unblocking a `sem_acquire` method.
+ *
+ * Note that \ref sem_release() may be called an arbitrary number of times, however the number of available
+ * permits is capped to the max_permit value specified during semaphore initialization.
+ *
+ * Although these semaphore related functions can be used from IRQ handlers, it is obviously preferable to only
+ * release semaphores from within an IRQ handler (i.e. avoid blocking)
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+typedef struct __packed_aligned semaphore {
+ struct lock_core core;
+ int16_t permits;
+ int16_t max_permits;
+} semaphore_t;
+
+
+/*! \brief Initialise a semaphore structure
+ * \ingroup sem
+ *
+ * \param sem Pointer to semaphore structure
+ * \param initial_permits How many permits are initially acquired
+ * \param max_permits Total number of permits allowed for this semaphore
+ */
+void sem_init(semaphore_t *sem, int16_t initial_permits, int16_t max_permits);
+
+/*! \brief Return number of available permits on the semaphore
+ * \ingroup sem
+ *
+ * \param sem Pointer to semaphore structure
+ * \return The number of permits available on the semaphore.
+ */
+int sem_available(semaphore_t *sem);
+
+/*! \brief Release a permit on a semaphore
+ * \ingroup sem
+ *
+ * Increases the number of permits by one (unless the number of permits is already at the maximum).
+ * A blocked `sem_acquire` will be released if the number of permits is increased.
+ *
+ * \param sem Pointer to semaphore structure
+ * \return true if the number of permits available was increased.
+ */
+bool sem_release(semaphore_t *sem);
+
+/*! \brief Reset semaphore to a specific number of available permits
+ * \ingroup sem
+ *
+ * Reset value should be from 0 to the max_permits specified in the init function
+ *
+ * \param sem Pointer to semaphore structure
+ * \param permits the new number of available permits
+ */
+void sem_reset(semaphore_t *sem, int16_t permits);
+
+/*! \brief Acquire a permit from the semaphore
+ * \ingroup sem
+ *
+ * This function will block and wait if no permits are available.
+ *
+ * \param sem Pointer to semaphore structure
+ */
+void sem_acquire_blocking(semaphore_t *sem);
+
+/*! \brief Acquire a permit from a semaphore, with timeout
+ * \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * defined timeout has been reached. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param timeout_ms Time to wait to acquire the semaphore, in milliseconds.
+ * \return false if timeout reached, true if permit was acquired.
+ */
+bool sem_acquire_timeout_ms(semaphore_t *sem, uint32_t timeout_ms);
+
+/*! \brief Acquire a permit from a semaphore, with timeout
+ * \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * defined timeout has been reached. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param timeout_us Time to wait to acquire the semaphore, in microseconds.
+ * \return false if timeout reached, true if permit was acquired.
+ */
+bool sem_acquire_timeout_us(semaphore_t *sem, uint32_t timeout_us);
+
+/*! \brief Wait to acquire a permit from a semaphore until a specific time
+ * \ingroup sem
+ *
+ * This function will block and wait if no permits are available, until the
+ * specified timeout time. If the timeout is reached the function will
+ * return false, otherwise it will return true.
+ *
+ * \param sem Pointer to semaphore structure
+ * \param until The time after which to return if the sem is not available.
+ * \return true if permit was acquired, false if the until time was reached before
+ * acquiring.
+ */
+bool sem_acquire_block_until(semaphore_t *sem, absolute_time_t until);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/sf_table.h b/arkanoid/pico/sf_table.h
new file mode 100644
index 0000000..4eb4b1c
--- /dev/null
+++ b/arkanoid/pico/sf_table.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_SF_TABLE_H
+#define _PICO_SF_TABLE_H
+
+// NOTE THESE FUNCTION IMPLEMENTATIONS MATCH THE BEHAVIOR DESCRIBED IN THE BOOTROM SECTION OF THE RP2040 DATASHEET
+
+#define SF_TABLE_FADD 0x00
+#define SF_TABLE_FSUB 0x04
+#define SF_TABLE_FMUL 0x08
+#define SF_TABLE_FDIV 0x0c
+#define SF_TABLE_FCMP_FAST 0x10
+#define SF_TABLE_FCMP_FAST_FLAGS 0x14
+#define SF_TABLE_FSQRT 0x18
+#define SF_TABLE_FLOAT2INT 0x1c
+#define SF_TABLE_FLOAT2FIX 0x20
+#define SF_TABLE_FLOAT2UINT 0x24
+#define SF_TABLE_FLOAT2UFIX 0x28
+#define SF_TABLE_INT2FLOAT 0x2c
+#define SF_TABLE_FIX2FLOAT 0x30
+#define SF_TABLE_UINT2FLOAT 0x34
+#define SF_TABLE_UFIX2FLOAT 0x38
+#define SF_TABLE_FCOS 0x3c
+#define SF_TABLE_FSIN 0x40
+#define SF_TABLE_FTAN 0x44
+#define SF_TABLE_V3_FSINCOS 0x48
+#define SF_TABLE_FEXP 0x4c
+#define SF_TABLE_FLN 0x50
+
+#define SF_TABLE_V1_SIZE 0x54
+
+#define SF_TABLE_FCMP_BASIC 0x54
+#define SF_TABLE_FATAN2 0x58
+#define SF_TABLE_INT642FLOAT 0x5c
+#define SF_TABLE_FIX642FLOAT 0x60
+#define SF_TABLE_UINT642FLOAT 0x64
+#define SF_TABLE_UFIX642FLOAT 0x68
+#define SF_TABLE_FLOAT2INT64 0x6c
+#define SF_TABLE_FLOAT2FIX64 0x70
+#define SF_TABLE_FLOAT2UINT64 0x74
+#define SF_TABLE_FLOAT2UFIX64 0x78
+#define SF_TABLE_FLOAT2DOUBLE 0x7c
+
+#define SF_TABLE_V2_SIZE 0x80
+
+#endif
diff --git a/arkanoid/pico/stdio.c b/arkanoid/pico/stdio.c
new file mode 100644
index 0000000..39fdd78
--- /dev/null
+++ b/arkanoid/pico/stdio.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <string.h>
+#include <stdio.h>
+#include <stdarg.h>
+
+#include "pico.h"
+#include "mutex.h"
+#if LIB_PICO_PRINTF_PICO
+#include "printf.h"
+#endif
+#include "stdio.h"
+#include "driver.h"
+#include "time.h"
+
+#if LIB_PICO_STDIO_UART
+#include "stdio_uart.h"
+#endif
+
+#if LIB_PICO_STDIO_USB
+#include "stdio_usb.h"
+#endif
+
+#if LIB_PICO_STDIO_SEMIHOSTING
+#include "stdio_semihosting.h"
+#endif
+
+static stdio_driver_t *drivers;
+static stdio_driver_t *filter;
+
+#if PICO_STDOUT_MUTEX
+auto_init_mutex(print_mutex);
+
+bool stdout_serialize_begin(void) {
+ lock_owner_id_t caller = lock_get_caller_owner_id();
+ // not using lock_owner_id_t to avoid backwards incompatibility change to mutex_try_enter API
+ static_assert(sizeof(lock_owner_id_t) <= 4, "");
+ uint32_t owner;
+ if (!mutex_try_enter(&print_mutex, &owner)) {
+ if (owner == (uint32_t)caller) {
+ return false;
+ }
+ // we are not a nested call, so lets wait
+ mutex_enter_blocking(&print_mutex);
+ }
+ return true;
+}
+
+void stdout_serialize_end(void) {
+ mutex_exit(&print_mutex);
+}
+
+#else
+static bool stdout_serialize_begin(void) {
+ return true;
+}
+static void stdout_serialize_end(void) {
+}
+#endif
+static void stdio_out_chars_no_crlf(stdio_driver_t *driver, const char *s, int len) {
+ driver->out_chars(s, len);
+}
+
+static void stdio_out_chars_crlf(stdio_driver_t *driver, const char *s, int len) {
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+ if (!driver->crlf_enabled) {
+ driver->out_chars(s, len);
+ return;
+ }
+ int first_of_chunk = 0;
+ static const char crlf_str[] = {'\r', '\n'};
+ for (int i = 0; i < len; i++) {
+ bool prev_char_was_cr = i > 0 ? s[i - 1] == '\r' : driver->last_ended_with_cr;
+ if (s[i] == '\n' && !prev_char_was_cr) {
+ if (i > first_of_chunk) {
+ driver->out_chars(&s[first_of_chunk], i - first_of_chunk);
+ }
+ driver->out_chars(crlf_str, 2);
+ first_of_chunk = i + 1;
+ }
+ }
+ if (first_of_chunk < len) {
+ driver->out_chars(&s[first_of_chunk], len - first_of_chunk);
+ }
+ if (len > 0) {
+ driver->last_ended_with_cr = s[len - 1] == '\r';
+ }
+#else
+ driver->out_chars(s, len);
+#endif
+}
+
+static bool stdio_put_string(const char *s, int len, bool newline, bool no_cr) {
+ bool serialized = stdout_serialize_begin();
+ if (!serialized) {
+#if PICO_STDIO_IGNORE_NESTED_STDOUT
+ return false;
+#endif
+ }
+ if (len == -1) len = (int)strlen(s);
+ void (*out_func)(stdio_driver_t *, const char *, int) = no_cr ? stdio_out_chars_no_crlf : stdio_out_chars_crlf;
+ for (stdio_driver_t *driver = drivers; driver; driver = driver->next) {
+ if (!driver->out_chars) continue;
+ if (filter && filter != driver) continue;
+ out_func(driver, s, len);
+ if (newline) {
+ const char c = '\n';
+ out_func(driver, &c, 1);
+ }
+ }
+ if (serialized) {
+ stdout_serialize_end();
+ }
+ return len;
+}
+
+static int stdio_get_until(char *buf, int len, absolute_time_t until) {
+ do {
+ // todo round robin might be nice on each call, but then again hopefully
+ // no source will starve the others
+ for (stdio_driver_t *driver = drivers; driver; driver = driver->next) {
+ if (filter && filter != driver) continue;
+ if (driver->in_chars) {
+ int read = driver->in_chars(buf, len);
+ if (read > 0) {
+ return read;
+ }
+ }
+ }
+ // we sleep here in case the in_chars methods acquire mutexes or disable IRQs and
+ // potentially starve out what they are waiting on (have seen this with USB)
+ busy_wait_us(1);
+ } while (!time_reached(until));
+ return PICO_ERROR_TIMEOUT;
+}
+
+int WRAPPER_FUNC(putchar)(int c) {
+ char cc = (char)c;
+ stdio_put_string(&cc, 1, false, false);
+ return c;
+}
+
+int WRAPPER_FUNC(puts)(const char *s) {
+ int len = (int)strlen(s);
+ stdio_put_string(s, len, true, false);
+ stdio_flush();
+ return len;
+}
+
+int putchar_raw(int c) {
+ char cc = (char)c;
+ stdio_put_string(&cc, 1, false, true);
+ return c;
+}
+
+int puts_raw(const char *s) {
+ int len = (int)strlen(s);
+ stdio_put_string(s, len, true, true);
+ stdio_flush();
+ return len;
+}
+
+int _read(int handle, char *buffer, int length) {
+ if (handle == 0) {
+ return stdio_get_until(buffer, length, at_the_end_of_time);
+ }
+ return -1;
+}
+
+int _write(int handle, char *buffer, int length) {
+ if (handle == 1) {
+ stdio_put_string(buffer, length, false, false);
+ return length;
+ }
+ return -1;
+}
+
+void stdio_set_driver_enabled(stdio_driver_t *driver, bool enable) {
+ stdio_driver_t *prev = drivers;
+ for (stdio_driver_t *d = drivers; d; d = d->next) {
+ if (d == driver) {
+ if (!enable) {
+ prev->next = d->next;
+ driver->next = NULL;
+ }
+ return;
+ }
+ prev = d;
+ }
+ if (enable) {
+ if (prev) prev->next = driver;
+ else drivers = driver;
+ }
+}
+
+void stdio_flush() {
+ for (stdio_driver_t *d = drivers; d; d = d->next) {
+ if (d->out_flush) d->out_flush();
+ }
+}
+
+typedef struct stdio_stack_buffer {
+ int used;
+ char buf[PICO_STDIO_STACK_BUFFER_SIZE];
+} stdio_stack_buffer_t;
+
+static void stdio_stack_buffer_flush(stdio_stack_buffer_t *buffer) {
+ if (buffer->used) {
+ for (stdio_driver_t *d = drivers; d; d = d->next) {
+ if (!d->out_chars) continue;
+ if (filter && filter != d) continue;
+ stdio_out_chars_crlf(d, buffer->buf, buffer->used);
+ }
+ buffer->used = 0;
+ }
+}
+
+static void stdio_buffered_printer(char c, void *arg) {
+ stdio_stack_buffer_t *buffer = (stdio_stack_buffer_t *)arg;
+ if (buffer->used == PICO_STDIO_STACK_BUFFER_SIZE) {
+ stdio_stack_buffer_flush(buffer);
+ }
+ buffer->buf[buffer->used++] = c;
+}
+
+int WRAPPER_FUNC(vprintf)(const char *format, va_list va) {
+ bool serialzed = stdout_serialize_begin();
+ if (!serialzed) {
+#if PICO_STDIO_IGNORE_NESTED_STDOUT
+ return 0;
+#endif
+ }
+ int ret;
+#if LIB_PICO_PRINTF_PICO
+ struct stdio_stack_buffer buffer = {.used = 0};
+ ret = vfctprintf(stdio_buffered_printer, &buffer, format, va);
+ stdio_stack_buffer_flush(&buffer);
+ stdio_flush();
+#elif LIB_PICO_PRINTF_NONE
+ extern void printf_none_assert();
+ printf_none_assert();
+#else
+ extern int REAL_FUNC(vprintf)(const char *format, va_list va);
+ ret = REAL_FUNC(vprintf)(format, va);
+#endif
+ if (serialzed) {
+ stdout_serialize_end();
+ }
+ return ret;
+}
+
+int __printflike(1, 0) WRAPPER_FUNC(printf)(const char* format, ...)
+{
+ va_list va;
+ va_start(va, format);
+ int ret = vprintf(format, va);
+ va_end(va);
+ return ret;
+}
+
+// TODO added
+
+int WRAPPER_FUNC(vscanf)(const char *format, va_list va) {
+ /*
+ bool serialzed = stdin_serialize_begin();
+ if (!serialzed) {
+#if PICO_STDIO_IGNORE_NESTED_STDOUT
+ return 0;
+#endif
+ }
+ */
+
+ while (true) {
+ printf("lol\n");
+ }
+ int ret;
+ extern int REAL_FUNC(vscanf)(const char *format, va_list va);
+ ret = REAL_FUNC(vscanf)(format, va);
+ return ret;
+}
+
+int __printflike(1, 0) WRAPPER_FUNC(scanf)(const char* format, ...)
+{
+ while (true) {
+ printf("lol\n");
+ }
+
+ va_list va;
+ va_start(va, format);
+ int ret = vscanf(format, va);
+ va_end(va);
+ return ret;
+}
+
+// TODO added end
+
+void stdio_init_all(void) {
+ // todo add explicit custom, or registered although you can call stdio_enable_driver explicitly anyway
+ // These are well known ones
+#if LIB_PICO_STDIO_UART
+ stdio_uart_init();
+#endif
+
+#if LIB_PICO_STDIO_SEMIHOSTING
+ stdio_semihosting_init();
+#endif
+
+#if LIB_PICO_STDIO_USB
+ stdio_usb_init();
+#endif
+}
+
+int WRAPPER_FUNC(getchar)(void) {
+ char buf[1];
+ int len = stdio_get_until(buf, 1, at_the_end_of_time);
+ if (len < 0) return len;
+ assert(len == 1);
+ return (uint8_t)buf[0];
+}
+
+int getchar_timeout_us(uint32_t timeout_us) {
+ char buf[1];
+ int rc = stdio_get_until(buf, sizeof(buf), make_timeout_time_us(timeout_us));
+ if (rc < 0) return rc;
+ assert(rc);
+ return (uint8_t)buf[0];
+}
+
+void stdio_filter_driver(stdio_driver_t *driver) {
+ filter = driver;
+}
+
+void stdio_set_translate_crlf(stdio_driver_t *driver, bool enabled) {
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+ if (enabled && !driver->crlf_enabled) {
+ driver->last_ended_with_cr = false;
+ }
+ driver->crlf_enabled = enabled;
+#else
+ panic_unsupported();
+#endif
+}
diff --git a/arkanoid/pico/stdio.h b/arkanoid/pico/stdio.h
new file mode 100644
index 0000000..e44c01d
--- /dev/null
+++ b/arkanoid/pico/stdio.h
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_H
+#define _PICO_STDIO_H
+
+/** \file stdio.h
+* \defgroup pico_stdio pico_stdio
+* Customized stdio support allowing for input and output from UART, USB, semi-hosting etc.
+*
+* Note the API for adding additional input output devices is not yet considered stable
+*/
+
+#include "pico.h"
+
+// PICO_CONFIG: PICO_STDOUT_MUTEX, Enable/disable mutex around stdout, type=bool, default=1, group=pico_stdio
+#ifndef PICO_STDOUT_MUTEX
+#define PICO_STDOUT_MUTEX 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_ENABLE_CRLF_SUPPORT, Enable/disable CR/LF output conversion support, type=bool, default=1, group=pico_stdio
+#ifndef PICO_STDIO_ENABLE_CRLF_SUPPORT
+#define PICO_STDIO_ENABLE_CRLF_SUPPORT 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_DEFAULT_CRLF, Default for CR/LF conversion enabled on all stdio outputs, type=bool, default=1, depends=PICO_STDIO_ENABLE_CRLF_SUPPORT, group=pico_stdio
+#ifndef PICO_STDIO_DEFAULT_CRLF
+#define PICO_STDIO_DEFAULT_CRLF 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_STACK_BUFFER_SIZE, Define printf buffer size (on stack)... this is just a working buffer not a max output size, min=0, max=512, default=128, group=pico_stdio
+#ifndef PICO_STDIO_STACK_BUFFER_SIZE
+#define PICO_STDIO_STACK_BUFFER_SIZE 128
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+typedef struct stdio_driver stdio_driver_t;
+
+/*! \brief Initialize all of the present standard stdio types that are linked into the binary.
+ * \ingroup pico_stdio
+ *
+ * Call this method once you have set up your clocks to enable the stdio support for UART, USB
+ * and semihosting based on the presence of the respective libraries in the binary.
+ *
+ * When stdio_usb is configured, this method can be optionally made to block, waiting for a connection
+ * via the variables specified in \ref stdio_usb_init (i.e. \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS)
+ *
+ * \see stdio_uart, stdio_usb, stdio_semihosting
+ */
+void stdio_init_all(void);
+
+/*! \brief Initialize all of the present standard stdio types that are linked into the binary.
+ * \ingroup pico_stdio
+ *
+ * Call this method once you have set up your clocks to enable the stdio support for UART, USB
+ * and semihosting based on the presence of the respective libraries in the binary.
+ *
+ * \see stdio_uart, stdio_usb, stdio_semihosting
+ */
+void stdio_flush(void);
+
+/*! \brief Return a character from stdin if there is one available within a timeout
+ * \ingroup pico_stdio
+ *
+ * \param timeout_us the timeout in microseconds, or 0 to not wait for a character if none available.
+ * \return the character from 0-255 or PICO_ERROR_TIMEOUT if timeout occurs
+ */
+int getchar_timeout_us(uint32_t timeout_us);
+
+/*! \brief Adds or removes a driver from the list of active drivers used for input/output
+ * \ingroup pico_stdio
+ *
+ * \note this method should always be called on an initialized driver and is not re-entrant
+ * \param driver the driver
+ * \param enabled true to add, false to remove
+ */
+void stdio_set_driver_enabled(stdio_driver_t *driver, bool enabled);
+
+/*! \brief Control limiting of output to a single driver
+ * \ingroup pico_stdio
+ *
+ * \note this method should always be called on an initialized driver
+ *
+ * \param driver if non-null then output only that driver will be used for input/output (assuming it is in the list of enabled drivers).
+ * if NULL then all enabled drivers will be used
+ */
+void stdio_filter_driver(stdio_driver_t *driver);
+
+/*! \brief control conversion of line feeds to carriage return on transmissions
+ * \ingroup pico_stdio
+ *
+ * \note this method should always be called on an initialized driver
+ *
+ * \param driver the driver
+ * \param translate If true, convert line feeds to carriage return on transmissions
+ */
+void stdio_set_translate_crlf(stdio_driver_t *driver, bool translate);
+
+/*! \brief putchar variant that skips any CR/LF conversion if enabled
+ * \ingroup pico_stdio
+ */
+int putchar_raw(int c);
+
+/*! \brief puts variant that skips any CR/LF conversion if enabled
+ * \ingroup pico_stdio
+ */
+int puts_raw(const char *s);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/stdio_semihosting.c b/arkanoid/pico/stdio_semihosting.c
new file mode 100644
index 0000000..55133b1
--- /dev/null
+++ b/arkanoid/pico/stdio_semihosting.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "driver.h"
+#include "stdio_semihosting.h"
+#include "binary_info.h"
+
+//static void __attribute__((naked)) semihosting_puts(const char *s) {
+// __asm (
+//
+// "mov r1, r0\n"
+// "mov r0, #4\n"
+// "bkpt 0xab\n"
+// "bx lr\n"
+// );
+//}
+
+static void __attribute__((naked)) semihosting_putc(__unused const char *c) {
+ __asm (
+
+ "mov r1, r0\n"
+ "mov r0, #3\n"
+ "bkpt 0xab\n"
+ "bx lr\n"
+ );
+}
+
+
+static void stdio_semihosting_out_chars(const char *buf, int length) {
+ for (int i = 0; i < length; i++) {
+ semihosting_putc(&buf[i]);
+ }
+}
+
+stdio_driver_t stdio_semihosting = {
+ .out_chars = stdio_semihosting_out_chars,
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+ .crlf_enabled = PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF
+#endif
+};
+
+void stdio_semihosting_init() {
+#if !PICO_NO_BI_STDIO_SEMIHOSTING
+ bi_decl_if_func_used(bi_program_feature("semihosting stdout"));
+#endif
+ stdio_set_driver_enabled(&stdio_semihosting, true);
+}
+
diff --git a/arkanoid/pico/stdio_semihosting.h b/arkanoid/pico/stdio_semihosting.h
new file mode 100644
index 0000000..a659998
--- /dev/null
+++ b/arkanoid/pico/stdio_semihosting.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_SEMIHOSTING_H
+#define _PICO_STDIO_SEMIHOSTING_H
+
+#include "stdio.h"
+
+/** \brief Experimental support for stdout using RAM semihosting
+ * \defgroup pico_stdio_semihosting pico_stdio_semihosting
+ * \ingroup pico_stdio
+ *
+ * Linking this library or calling `pico_enable_stdio_semihosting(TARGET)` in the CMake (which
+ * achieves the same thing) will add semihosting to the drivers used for standard output
+ */
+
+// PICO_CONFIG: PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF, Default state of CR/LF translation for semihosting output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_semihosting
+#ifndef PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF
+#define PICO_STDIO_SEMIHOSTING_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern stdio_driver_t stdio_semihosting;
+
+/*! \brief Explicitly initialize stdout over semihosting and add it to the current set of stdout targets
+ * \ingroup pico_stdio_semihosting
+ *
+ * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_semihosting` is included in the build
+ */
+void stdio_semihosting_init(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/stdio_uart.c b/arkanoid/pico/stdio_uart.c
new file mode 100644
index 0000000..c4f9880
--- /dev/null
+++ b/arkanoid/pico/stdio_uart.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "driver.h"
+#include "stdio_uart.h"
+#include "binary_info.h"
+#include "hardware/gpio.h"
+
+static uart_inst_t *uart_instance;
+
+#if PICO_NO_BI_STDIO_UART
+#define stdio_bi_decl_if_func_used(x)
+#else
+#define stdio_bi_decl_if_func_used bi_decl_if_func_used
+#endif
+
+void stdio_uart_init() {
+#ifdef uart_default
+ int tx_pin = -1;
+ int rx_pin = -1;
+#ifdef PICO_DEFAULT_UART_TX_PIN
+ tx_pin = PICO_DEFAULT_UART_TX_PIN;
+#ifdef PICO_DEFAULT_UART_RX_PIN
+ rx_pin = PICO_DEFAULT_UART_RX_PIN;
+ stdio_bi_decl_if_func_used(bi_program_feature("UART stdin / stdout"));
+ bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#else
+ stdio_bi_decl_if_func_used(bi_program_feature("UART stdout"));
+ bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#endif
+#elif defined(PICO_DEFAULT_UART_RX_PIN)
+ rx_pin = PICO_DEFAULT_UART_RX_PIN;
+ stdio_bi_decl_if_func_used(bi_program_feature("UART stdin"));
+ bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART));
+#endif
+#if !defined(PICO_DEFAULT_UART_BAUD_RATE)
+ panic("UART baud rate undefined");
+#else
+ stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, tx_pin, rx_pin);
+#endif
+#endif
+}
+
+void stdout_uart_init() {
+#if defined(uart_default) && defined(PICO_DEFAULT_UART_TX_PIN)
+ bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#if !defined(PICO_DEFAULT_UART_BAUD_RATE)
+ panic("UART baud rate undefined");
+#else
+ stdio_bi_decl_if_func_used(bi_program_feature("UART stdout"));
+ stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, PICO_DEFAULT_UART_TX_PIN, -1);
+#endif
+#endif
+}
+
+void stdin_uart_init() {
+#if defined(uart_default) && defined(PICO_DEFAULT_UART_RX_PIN)
+ bi_decl_if_func_used(bi_1pin_with_func(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART));
+#if !defined(PICO_DEFAULT_UART_BAUD_RATE)
+ panic("UART baud rate undefined");
+#else
+ stdio_bi_decl_if_func_used(bi_program_feature("UART stdin"));
+ stdio_uart_init_full(uart_default, PICO_DEFAULT_UART_BAUD_RATE, -1, PICO_DEFAULT_UART_RX_PIN);
+#endif
+#endif
+}
+
+void stdio_uart_init_full(struct uart_inst *uart, uint baud_rate, int tx_pin, int rx_pin) {
+ uart_instance = uart;
+ uart_init(uart_instance, baud_rate);
+ if (tx_pin >= 0) gpio_set_function((uint)tx_pin, GPIO_FUNC_UART);
+ if (rx_pin >= 0) gpio_set_function((uint)rx_pin, GPIO_FUNC_UART);
+ stdio_set_driver_enabled(&stdio_uart, true);
+}
+
+static void stdio_uart_out_chars(const char *buf, int length) {
+ for (int i = 0; i <length; i++) {
+ uart_putc(uart_instance, buf[i]);
+ }
+}
+
+int stdio_uart_in_chars(char *buf, int length) {
+ int i=0;
+ while (i<length && uart_is_readable(uart_instance)) {
+ buf[i++] = uart_getc(uart_instance);
+ }
+ return i ? i : PICO_ERROR_NO_DATA;
+}
+
+stdio_driver_t stdio_uart = {
+ .out_chars = stdio_uart_out_chars,
+ .in_chars = stdio_uart_in_chars,
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+ .crlf_enabled = PICO_STDIO_UART_DEFAULT_CRLF
+#endif
+};
diff --git a/arkanoid/pico/stdio_uart.h b/arkanoid/pico/stdio_uart.h
new file mode 100644
index 0000000..0d5c2f0
--- /dev/null
+++ b/arkanoid/pico/stdio_uart.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_UART_H
+#define _PICO_STDIO_UART_H
+
+#include "stdio.h"
+#include "hardware/uart.h"
+
+/** \brief Support for stdin/stdout using UART
+ * \defgroup pico_stdio_uart pico_stdio_uart
+ * \ingroup pico_stdio
+ *
+ * Linking this library or calling `pico_enable_stdio_uart(TARGET)` in the CMake (which
+ * achieves the same thing) will add UART to the drivers used for standard output
+ */
+
+// PICO_CONFIG: PICO_STDIO_UART_DEFAULT_CRLF, Default state of CR/LF translation for UART output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_uart
+#ifndef PICO_STDIO_UART_DEFAULT_CRLF
+#define PICO_STDIO_UART_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern stdio_driver_t stdio_uart;
+
+/*! \brief Explicitly initialize stdin/stdout over UART and add it to the current set of stdin/stdout drivers
+ * \ingroup pico_stdio_uart
+ *
+ * This method sets up PICO_DEFAULT_UART_TX_PIN for UART output (if defined), PICO_DEFAULT_UART_RX_PIN for input (if defined)
+ * and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE.
+ *
+ * \note this method is automatically called by \ref stdio_init_all() if `pico_stdio_uart` is included in the build
+ */
+void stdio_uart_init(void);
+
+/*! \brief Explicitly initialize stdout only (no stdin) over UART and add it to the current set of stdout drivers
+ * \ingroup pico_stdio_uart
+ *
+ * This method sets up PICO_DEFAULT_UART_TX_PIN for UART output (if defined) , and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE
+ */
+void stdout_uart_init(void);
+
+/*! \brief Explicitly initialize stdin only (no stdout) over UART and add it to the current set of stdin drivers
+ * \ingroup pico_stdio_uart
+ *
+ * This method sets up PICO_DEFAULT_UART_RX_PIN for UART input (if defined) , and configures the baud rate as PICO_DEFAULT_UART_BAUD_RATE
+ */
+void stdin_uart_init(void);
+
+/*! \brief Perform custom initialization initialize stdin/stdout over UART and add it to the current set of stdin/stdout drivers
+ * \ingroup pico_stdio_uart
+ *
+ * \param uart the uart instance to use, \ref uart0 or \ref uart1
+ * \param baud_rate the baud rate in Hz
+ * \param tx_pin the UART pin to use for stdout (or -1 for no stdout)
+ * \param rx_pin the UART pin to use for stdin (or -1 for no stdin)
+ */
+void stdio_uart_init_full(uart_inst_t *uart, uint baud_rate, int tx_pin, int rx_pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/stdio_usb.c b/arkanoid/pico/stdio_usb.c
new file mode 100644
index 0000000..a81600b
--- /dev/null
+++ b/arkanoid/pico/stdio_usb.c
@@ -0,0 +1,135 @@
+/**
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
+#include "tinyusb/tusb.h"
+
+#include "time.h"
+#include "driver.h"
+#include "binary_info.h"
+#include "mutex.h"
+#include "hardware/irq.h"
+
+static_assert(PICO_STDIO_USB_LOW_PRIORITY_IRQ > RTC_IRQ, ""); // note RTC_IRQ is currently the last one
+static mutex_t stdio_usb_mutex;
+
+static void low_priority_worker_irq(void) {
+ // if the mutex is already owned, then we are in user code
+ // in this file which will do a tud_task itself, so we'll just do nothing
+ // until the next tick; we won't starve
+ if (mutex_try_enter(&stdio_usb_mutex, NULL)) {
+ tud_task();
+ mutex_exit(&stdio_usb_mutex);
+ }
+}
+
+static int64_t timer_task(__unused alarm_id_t id, __unused void *user_data) {
+ irq_set_pending(PICO_STDIO_USB_LOW_PRIORITY_IRQ);
+ return PICO_STDIO_USB_TASK_INTERVAL_US;
+}
+
+static void stdio_usb_out_chars(const char *buf, int length) {
+ static uint64_t last_avail_time;
+ uint32_t owner;
+ if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
+ if (owner == get_core_num()) return; // would deadlock otherwise
+ mutex_enter_blocking(&stdio_usb_mutex);
+ }
+ if (tud_cdc_connected()) {
+ for (int i = 0; i < length;) {
+ int n = length - i;
+ int avail = (int) tud_cdc_write_available();
+ if (n > avail) n = avail;
+ if (n) {
+ int n2 = (int) tud_cdc_write(buf + i, (uint32_t)n);
+ tud_task();
+ tud_cdc_write_flush();
+ i += n2;
+ last_avail_time = time_us_64();
+ } else {
+ tud_task();
+ tud_cdc_write_flush();
+ if (!tud_cdc_connected() ||
+ (!tud_cdc_write_available() && time_us_64() > last_avail_time + PICO_STDIO_USB_STDOUT_TIMEOUT_US)) {
+ break;
+ }
+ }
+ }
+ } else {
+ // reset our timeout
+ last_avail_time = 0;
+ }
+ mutex_exit(&stdio_usb_mutex);
+}
+
+int stdio_usb_in_chars(char *buf, int length) {
+ uint32_t owner;
+ if (!mutex_try_enter(&stdio_usb_mutex, &owner)) {
+ if (owner == get_core_num()) return PICO_ERROR_NO_DATA; // would deadlock otherwise
+ mutex_enter_blocking(&stdio_usb_mutex);
+ }
+ int rc = PICO_ERROR_NO_DATA;
+ if (tud_cdc_connected() && tud_cdc_available()) {
+ int count = (int) tud_cdc_read(buf, (uint32_t) length);
+ rc = count ? count : PICO_ERROR_NO_DATA;
+ }
+ mutex_exit(&stdio_usb_mutex);
+ return rc;
+}
+
+stdio_driver_t stdio_usb = {
+ .out_chars = stdio_usb_out_chars,
+ .in_chars = stdio_usb_in_chars,
+#if PICO_STDIO_ENABLE_CRLF_SUPPORT
+ .crlf_enabled = PICO_STDIO_USB_DEFAULT_CRLF
+#endif
+};
+
+bool stdio_usb_init(void) {
+#if !PICO_NO_BI_STDIO_USB
+ bi_decl_if_func_used(bi_program_feature("USB stdin / stdout"));
+#endif
+
+ // initialize TinyUSB
+ tusb_init();
+
+ irq_set_exclusive_handler(PICO_STDIO_USB_LOW_PRIORITY_IRQ, low_priority_worker_irq);
+ irq_set_enabled(PICO_STDIO_USB_LOW_PRIORITY_IRQ, true);
+
+ mutex_init(&stdio_usb_mutex);
+ bool rc = add_alarm_in_us(PICO_STDIO_USB_TASK_INTERVAL_US, timer_task, NULL, true);
+ if (rc) {
+ stdio_set_driver_enabled(&stdio_usb, true);
+#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS
+#if PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS > 0
+ absolute_time_t until = make_timeout_time_ms(PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS);
+#else
+ absolute_time_t until = at_the_end_of_time;
+#endif
+ do {
+ if (stdio_usb_connected()) {
+#if PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS != 0
+ sleep_ms(PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS);
+#endif
+ break;
+ }
+ sleep_ms(10);
+ } while (!time_reached(until));
+#endif
+ }
+ return rc;
+}
+
+bool stdio_usb_connected(void) {
+ return tud_cdc_connected();
+}
+#else
+#include "stdio_usb.h"
+#warning stdio USB was configured, but is being disabled as TinyUSB is explicitly linked
+bool stdio_usb_init(void) {
+ return false;
+}
+#endif
diff --git a/arkanoid/pico/stdio_usb.h b/arkanoid/pico/stdio_usb.h
new file mode 100644
index 0000000..86169ae
--- /dev/null
+++ b/arkanoid/pico/stdio_usb.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDIO_USB_H
+#define _PICO_STDIO_USB_H
+
+#include "stdio.h"
+
+/** \brief Support for stdin/stdout over USB serial (CDC)
+ * \defgroup pico_stdio_usb pico_stdio_usb
+ * \ingroup pico_stdio
+ *
+ * Linking this library or calling `pico_enable_stdio_usb(TARGET)` in the CMake (which
+ * achieves the same thing) will add USB CDC to the drivers used for standard output
+ *
+ * Note this library is a developer convenience. It is not applicable in all cases; for one it takes full control of the USB device precluding your
+ * use of the USB in device or host mode. For this reason, this library will automatically disengage if you try to using it alongside \ref tinyusb_device or
+ * \ref tinyusb_host. It also takes control of a lower level IRQ and sets up a periodic background task.
+ *
+ * This library also includes (by default) functionality to enable the RP2040 to be reset over the USB interface.
+ */
+
+// PICO_CONFIG: PICO_STDIO_USB_DEFAULT_CRLF, Default state of CR/LF translation for USB output, type=bool, default=PICO_STDIO_DEFAULT_CRLF, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_DEFAULT_CRLF
+#define PICO_STDIO_USB_DEFAULT_CRLF PICO_STDIO_DEFAULT_CRLF
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_STDOUT_TIMEOUT_US, Number of microseconds to be blocked trying to write USB output before assuming the host has disappeared and discarding data, default=500000, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_STDOUT_TIMEOUT_US
+#define PICO_STDIO_USB_STDOUT_TIMEOUT_US 500000
+#endif
+
+// todo perhaps unnecessarily frequent?
+// PICO_CONFIG: PICO_STDIO_USB_TASK_INTERVAL_US, Period of microseconds between calling tud_task in the background, default=1000, advanced=true, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_TASK_INTERVAL_US
+#define PICO_STDIO_USB_TASK_INTERVAL_US 1000
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_LOW_PRIORITY_IRQ, low priority (non hardware) IRQ number to claim for tud_task() background execution, default=31, advanced=true, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_LOW_PRIORITY_IRQ
+#define PICO_STDIO_USB_LOW_PRIORITY_IRQ 31
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE, Enable/disable resetting into BOOTSEL mode if the host sets the baud rate to a magic value (PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE), type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE
+#define PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE, baud rate that if selected causes a reset into BOOTSEL mode (if PICO_STDIO_USB_ENABLE_RESET_VIA_BAUD_RATE is set), default=1200, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE
+#define PICO_STDIO_USB_RESET_MAGIC_BAUD_RATE 1200
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS, Maximum number of milliseconds to wait during initialization for a CDC connection from the host (negative means indefinite) during initialization, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS
+#define PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS 0
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS, Number of extra milliseconds to wait when using PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS after a host CDC connection is detected (some host terminals seem to sometimes lose transmissions sent right after connection), default=50, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS
+#define PICO_STDIO_USB_POST_CONNECT_WAIT_DELAY_MS 50
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED, Optionally define a pin to use as bootloader activity LED when BOOTSEL mode is entered via USB (either VIA_BAUD_RATE or VIA_VENDOR_INTERFACE), type=int, min=0, max=29, group=pico_stdio_usb
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED, Whether the pin specified by PICO_STDIO_USB_RESET_BOOTSEL_ACTIVITY_LED is fixed or can be modified by picotool over the VENDOR USB interface, type=bool, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED
+#define PICO_STDIO_USB_RESET_BOOTSEL_FIXED_ACTIVITY_LED 0
+#endif
+
+// Any modes disabled here can't be re-enabled by picotool via VENDOR_INTERFACE.
+// PICO_CONFIG: PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK, Optionally disable either the mass storage interface (bit 0) or the PICOBOOT interface (bit 1) when entering BOOTSEL mode via USB (either VIA_BAUD_RATE or VIA_VENDOR_INTERFACE), type=int, min=0, max=3, default=0, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK
+#define PICO_STDIO_USB_RESET_BOOTSEL_INTERFACE_DISABLE_MASK 0u
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE, Enable/disable resetting into BOOTSEL mode via an additional VENDOR USB interface - enables picotool based reset, type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#define PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL, If vendor reset interface is included allow rebooting to BOOTSEL mode, type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL
+#define PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_BOOTSEL 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT, If vendor reset interface is included allow rebooting with regular flash boot, type=bool, default=1, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT
+#define PICO_STDIO_USB_RESET_INTERFACE_SUPPORT_RESET_TO_FLASH_BOOT 1
+#endif
+
+// PICO_CONFIG: PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS, delays in ms before rebooting via regular flash boot, default=100, group=pico_stdio_usb
+#ifndef PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS
+#define PICO_STDIO_USB_RESET_RESET_TO_FLASH_DELAY_MS 100
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern stdio_driver_t stdio_usb;
+
+/*! \brief Explicitly initialize USB stdio and add it to the current set of stdin drivers
+ * \ingroup pico_stdio_usb
+ *
+ * \ref PICO_STDIO_USB_CONNECT_WAIT_TIMEOUT_MS can be set to cause this method to wait for a CDC connection
+ * from the host before returning, which is useful if you don't want any initial stdout output to be discarded
+ * before the connection is established.
+ *
+ * \return true if the USB CDC was initialized, false if an error occurred
+ */
+bool stdio_usb_init(void);
+
+/*! \brief Check if there is an active stdio CDC connection to a host
+ * \ingroup pico_stdio_usb
+ *
+ * \return true if stdio is connected over CDC
+ */
+bool stdio_usb_connected(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/stdio_usb_descriptors.c b/arkanoid/pico/stdio_usb_descriptors.c
new file mode 100644
index 0000000..43a00fc
--- /dev/null
+++ b/arkanoid/pico/stdio_usb_descriptors.c
@@ -0,0 +1,151 @@
+/*
+ * This file is based on a file originally part of the
+ * MicroPython project, http://micropython.org/
+ *
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2019 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#if !defined(LIB_TINYUSB_HOST) && !defined(LIB_TINYUSB_DEVICE)
+
+#include "tinyusb/tusb.h"
+#include "reset_interface.h"
+#include "unique_id.h"
+
+#define USBD_VID (0x2E8A) // Raspberry Pi
+#define USBD_PID (0x000a) // Raspberry Pi Pico SDK CDC
+
+#define TUD_RPI_RESET_DESC_LEN 9
+#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN)
+#else
+#define USBD_DESC_LEN (TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN + TUD_RPI_RESET_DESC_LEN)
+#endif
+#define USBD_MAX_POWER_MA (250)
+
+#define USBD_ITF_CDC (0) // needs 2 interfaces
+#if !PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+#define USBD_ITF_MAX (2)
+#else
+#define USBD_ITF_RPI_RESET (2)
+#define USBD_ITF_MAX (3)
+#endif
+
+#define USBD_CDC_EP_CMD (0x81)
+#define USBD_CDC_EP_OUT (0x02)
+#define USBD_CDC_EP_IN (0x82)
+#define USBD_CDC_CMD_MAX_SIZE (8)
+#define USBD_CDC_IN_OUT_MAX_SIZE (64)
+
+#define USBD_STR_0 (0x00)
+#define USBD_STR_MANUF (0x01)
+#define USBD_STR_PRODUCT (0x02)
+#define USBD_STR_SERIAL (0x03)
+#define USBD_STR_CDC (0x04)
+#define USBD_STR_RPI_RESET (0x05)
+
+// Note: descriptors returned from callbacks must exist long enough for transfer to complete
+
+static const tusb_desc_device_t usbd_desc_device = {
+ .bLength = sizeof(tusb_desc_device_t),
+ .bDescriptorType = TUSB_DESC_DEVICE,
+ .bcdUSB = 0x0200,
+ .bDeviceClass = TUSB_CLASS_MISC,
+ .bDeviceSubClass = MISC_SUBCLASS_COMMON,
+ .bDeviceProtocol = MISC_PROTOCOL_IAD,
+ .bMaxPacketSize0 = CFG_TUD_ENDPOINT0_SIZE,
+ .idVendor = USBD_VID,
+ .idProduct = USBD_PID,
+ .bcdDevice = 0x0100,
+ .iManufacturer = USBD_STR_MANUF,
+ .iProduct = USBD_STR_PRODUCT,
+ .iSerialNumber = USBD_STR_SERIAL,
+ .bNumConfigurations = 1,
+};
+
+#define TUD_RPI_RESET_DESCRIPTOR(_itfnum, _stridx) \
+ /* Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUSB_CLASS_VENDOR_SPECIFIC, RESET_INTERFACE_SUBCLASS, RESET_INTERFACE_PROTOCOL, _stridx,
+
+static const uint8_t usbd_desc_cfg[USBD_DESC_LEN] = {
+ TUD_CONFIG_DESCRIPTOR(1, USBD_ITF_MAX, USBD_STR_0, USBD_DESC_LEN,
+ 0, USBD_MAX_POWER_MA),
+
+ TUD_CDC_DESCRIPTOR(USBD_ITF_CDC, USBD_STR_CDC, USBD_CDC_EP_CMD,
+ USBD_CDC_CMD_MAX_SIZE, USBD_CDC_EP_OUT, USBD_CDC_EP_IN, USBD_CDC_IN_OUT_MAX_SIZE),
+
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+ TUD_RPI_RESET_DESCRIPTOR(USBD_ITF_RPI_RESET, USBD_STR_RPI_RESET)
+#endif
+};
+
+static char usbd_serial_str[PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2 + 1];
+
+static const char *const usbd_desc_str[] = {
+ [USBD_STR_MANUF] = "Raspberry Pi",
+ [USBD_STR_PRODUCT] = "Pico",
+ [USBD_STR_SERIAL] = usbd_serial_str,
+ [USBD_STR_CDC] = "Board CDC",
+#if PICO_STDIO_USB_ENABLE_RESET_VIA_VENDOR_INTERFACE
+ [USBD_STR_RPI_RESET] = "Reset",
+#endif
+};
+
+const uint8_t *tud_descriptor_device_cb(void) {
+ return (const uint8_t *)&usbd_desc_device;
+}
+
+const uint8_t *tud_descriptor_configuration_cb(__unused uint8_t index) {
+ return usbd_desc_cfg;
+}
+
+const uint16_t *tud_descriptor_string_cb(uint8_t index, __unused uint16_t langid) {
+ #define DESC_STR_MAX (20)
+ static uint16_t desc_str[DESC_STR_MAX];
+
+ // Assign the SN using the unique flash id
+ if (!usbd_serial_str[0]) {
+ pico_get_unique_board_id_string(usbd_serial_str, sizeof(usbd_serial_str));
+ }
+
+ uint8_t len;
+ if (index == 0) {
+ desc_str[1] = 0x0409; // supported language is English
+ len = 1;
+ } else {
+ if (index >= sizeof(usbd_desc_str) / sizeof(usbd_desc_str[0])) {
+ return NULL;
+ }
+ const char *str = usbd_desc_str[index];
+ for (len = 0; len < DESC_STR_MAX - 1 && str[len]; ++len) {
+ desc_str[1 + len] = str[len];
+ }
+ }
+
+ // first byte is length (including header), second byte is string type
+ desc_str[0] = (uint16_t) ((TUSB_DESC_STRING << 8) | (2 * len + 2));
+
+ return desc_str;
+}
+
+#endif
diff --git a/arkanoid/pico/stdlib.c b/arkanoid/pico/stdlib.c
new file mode 100644
index 0000000..05b937a
--- /dev/null
+++ b/arkanoid/pico/stdlib.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "stdlib.h"
+#include "hardware/pll.h"
+#include "hardware/clocks.h"
+#if LIB_PICO_STDIO_UART
+#include "stdio_uart.h"
+#else
+#include "binary_info.h"
+#endif
+
+// everything running off the USB oscillator
+void set_sys_clock_48mhz() {
+ if (!running_on_fpga()) {
+ // Change clk_sys to be 48MHz. The simplest way is to take this from PLL_USB
+ // which has a source frequency of 48MHz
+ clock_configure(clk_sys,
+ CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+ CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+ 48 * MHZ,
+ 48 * MHZ);
+
+ // Turn off PLL sys for good measure
+ pll_deinit(pll_sys);
+
+ // CLK peri is clocked from clk_sys so need to change clk_peri's freq
+ clock_configure(clk_peri,
+ 0,
+ CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS,
+ 48 * MHZ,
+ 48 * MHZ);
+ }
+}
+
+void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2) {
+ if (!running_on_fpga()) {
+ clock_configure(clk_sys,
+ CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+ CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+ 48 * MHZ,
+ 48 * MHZ);
+
+ pll_init(pll_sys, 1, vco_freq, post_div1, post_div2);
+ uint32_t freq = vco_freq / (post_div1 * post_div2);
+
+ // Configure clocks
+ // CLK_REF = XOSC (12MHz) / 1 = 12MHz
+ clock_configure(clk_ref,
+ CLOCKS_CLK_REF_CTRL_SRC_VALUE_XOSC_CLKSRC,
+ 0, // No aux mux
+ 12 * MHZ,
+ 12 * MHZ);
+
+ // CLK SYS = PLL SYS (125MHz) / 1 = 125MHz
+ clock_configure(clk_sys,
+ CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX,
+ CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS,
+ freq, freq);
+
+ clock_configure(clk_peri,
+ 0, // Only AUX mux on ADC
+ CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB,
+ 48 * MHZ,
+ 48 * MHZ);
+ }
+}
+
+bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_out, uint *postdiv1_out, uint *postdiv_out) {
+ uint crystal_freq_khz = clock_get_hz(clk_ref) / 1000;
+ for (uint fbdiv = 320; fbdiv >= 16; fbdiv--) {
+ uint vco = fbdiv * crystal_freq_khz;
+ if (vco < 400000 || vco > 1600000) continue;
+ for (uint postdiv1 = 7; postdiv1 >= 1; postdiv1--) {
+ for (uint postdiv2 = postdiv1; postdiv2 >= 1; postdiv2--) {
+ uint out = vco / (postdiv1 * postdiv2);
+ if (out == freq_khz && !(vco % (postdiv1 * postdiv2))) {
+ *vco_out = vco * 1000;
+ *postdiv1_out = postdiv1;
+ *postdiv_out = postdiv2;
+ return true;
+ }
+ }
+ }
+ }
+ return false;
+}
+
+void setup_default_uart() {
+#if LIB_PICO_STDIO_UART
+ stdio_uart_init();
+#elif defined(PICO_DEFAULT_UART_BAUD_RATE) && defined(PICO_DEFAULT_UART_TX_PIN) && defined(PICO_DEFAULT_UART_RX_PIN)
+ // this is mostly for backwards compatibility - stdio_uart_init is a bit more nuanced, and usually likely to be present
+ uart_init(uart_default, PICO_DEFAULT_UART_BAUD_RATE);
+ if (PICO_DEFAULT_UART_TX_PIN >= 0)
+ gpio_set_function(PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART);
+ if (PICO_DEFAULT_UART_RX_PIN >= 0)
+ gpio_set_function(PICO_DEFAULT_UART_RX_PIN, GPIO_FUNC_UART);
+ bi_decl_if_func_used(bi_2pins_with_func(PICO_DEFAULT_UART_RX_PIN, PICO_DEFAULT_UART_TX_PIN, GPIO_FUNC_UART));
+#endif
+}
diff --git a/arkanoid/pico/stdlib.h b/arkanoid/pico/stdlib.h
new file mode 100644
index 0000000..e8b346d
--- /dev/null
+++ b/arkanoid/pico/stdlib.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_STDLIB_H
+#define _PICO_STDLIB_H
+
+#include "pico.h"
+#include "stdio.h"
+#include "time.h"
+#include "hardware/gpio.h"
+#include "hardware/uart.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file stdlib.h
+ * \defgroup pico_stdlib pico_stdlib
+ *
+ * Aggregation of a core subset of Raspberry Pi Pico SDK libraries used by most executables along with some additional
+ * utility methods. Including pico_stdlib gives you everything you need to get a basic program running
+ * which prints to stdout or flashes a LED
+ *
+ * This library aggregates:
+ * - @ref hardware_uart
+ * - @ref hardware_gpio
+ * - @ref pico_binary_info
+ * - @ref pico_runtime
+ * - @ref pico_platform
+ * - @ref pico_printf
+ * - @ref pico_stdio
+ * - @ref pico_standard_link
+ * - @ref pico_util
+ *
+ * There are some basic default values used by these functions that will default to
+ * usable values, however, they can be customised in a board definition header via
+ * config.h or similar
+ */
+
+// Note PICO_STDIO_UART, PICO_STDIO_USB, PICO_STDIO_SEMIHOSTING are set by the
+// respective INTERFACE libraries, so these defines are set if the library
+// is included for the target executable
+
+#if LIB_PICO_STDIO_UART
+#include "stdio_uart.h"
+#endif
+
+#if LIB_PICO_STDIO_USB
+#include "stdio_usb.h"
+#endif
+
+#if LIB_PICO_STDIO_SEMIHOSTING
+#include "stdio_semihosting.h"
+#endif
+
+// PICO_CONFIG: PICO_DEFAULT_LED_PIN, Optionally define a pin that drives a regular LED on the board, group=pico_stdlib
+
+// PICO_CONFIG: PICO_DEFAULT_LED_PIN_INVERTED, 1 if LED is inverted or 0 if not, type=int, default=0, group=pico_stdlib
+#ifndef PICO_DEFAULT_LED_PIN_INVERTED
+#define PICO_DEFAULT_LED_PIN_INVERTED 0
+#endif
+
+// PICO_CONFIG: PICO_DEFAULT_WS2812_PIN, Optionally define a pin that controls data to a WS2812 compatible LED on the board, group=pico_stdlib
+// PICO_CONFIG: PICO_DEFAULT_WS2812_POWER_PIN, Optionally define a pin that controls power to a WS2812 compatible LED on the board, group=pico_stdlib
+
+/*! \brief Set up the default UART and assign it to the default GPIO's
+ * \ingroup pico_stdlib
+ *
+ * By default this will use UART 0, with TX to pin GPIO 0,
+ * RX to pin GPIO 1, and the baudrate to 115200
+ *
+ * Calling this method also initializes stdin/stdout over UART if the
+ * @ref pico_stdio_uart library is linked.
+ *
+ * Defaults can be changed using configuration defines,
+ * PICO_DEFAULT_UART_INSTANCE,
+ * PICO_DEFAULT_UART_BAUD_RATE
+ * PICO_DEFAULT_UART_TX_PIN
+ * PICO_DEFAULT_UART_RX_PIN
+ */
+void setup_default_uart(void);
+
+/*! \brief Initialise the system clock to 48MHz
+ * \ingroup pico_stdlib
+ *
+ * Set the system clock to 48MHz, and set the peripheral clock to match.
+ */
+void set_sys_clock_48mhz(void);
+
+/*! \brief Initialise the system clock
+ * \ingroup pico_stdlib
+ *
+ * \param vco_freq The voltage controller oscillator frequency to be used by the SYS PLL
+ * \param post_div1 The first post divider for the SYS PLL
+ * \param post_div2 The second post divider for the SYS PLL.
+ *
+ * See the PLL documentation in the datasheet for details of driving the PLLs.
+ */
+void set_sys_clock_pll(uint32_t vco_freq, uint post_div1, uint post_div2);
+
+/*! \brief Check if a given system clock frequency is valid/attainable
+ * \ingroup pico_stdlib
+ *
+ * \param freq_khz Requested frequency
+ * \param vco_freq_out On success, the voltage controller oscillator frequeucny to be used by the SYS PLL
+ * \param post_div1_out On success, The first post divider for the SYS PLL
+ * \param post_div2_out On success, The second post divider for the SYS PLL.
+ * @return true if the frequency is possible and the output parameters have been written.
+ */
+bool check_sys_clock_khz(uint32_t freq_khz, uint *vco_freq_out, uint *post_div1_out, uint *post_div2_out);
+
+/*! \brief Attempt to set a system clock frequency in khz
+ * \ingroup pico_stdlib
+ *
+ * Note that not all clock frequencies are possible; it is preferred that you
+ * use src/rp2_common/hardware_clocks/scripts/vcocalc.py to calculate the parameters
+ * for use with set_sys_clock_pll
+ *
+ * \param freq_khz Requested frequency
+ * \param required if true then this function will assert if the frequency is not attainable.
+ * \return true if the clock was configured
+ */
+static inline bool set_sys_clock_khz(uint32_t freq_khz, bool required) {
+ uint vco, postdiv1, postdiv2;
+ if (check_sys_clock_khz(freq_khz, &vco, &postdiv1, &postdiv2)) {
+ set_sys_clock_pll(vco, postdiv1, postdiv2);
+ return true;
+ } else if (required) {
+ panic("System clock of %u kHz cannot be exactly achieved", freq_khz);
+ }
+ return false;
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/arkanoid/pico/structure.h b/arkanoid/pico/structure.h
new file mode 100644
index 0000000..49d2fd6
--- /dev/null
+++ b/arkanoid/pico/structure.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_BINARY_INFO_STRUCTURE_H
+#define _PICO_BINARY_INFO_STRUCTURE_H
+
+// NOTE: This file may be included by non SDK code, so does not use SDK includes
+
+// NOTE: ALL CHANGES MUST BE BACKWARDS COMPATIBLE
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#ifndef __packed
+#define __packed __attribute__((packed))
+#endif
+
+typedef struct _binary_info_core binary_info_t;
+
+#define BINARY_INFO_TYPE_RAW_DATA 1
+#define BINARY_INFO_TYPE_SIZED_DATA 2
+#define BINARY_INFO_TYPE_BINARY_INFO_LIST_ZERO_TERMINATED 3
+#define BINARY_INFO_TYPE_BSON 4
+#define BINARY_INFO_TYPE_ID_AND_INT 5
+#define BINARY_INFO_TYPE_ID_AND_STRING 6
+// traditional block device
+#define BINARY_INFO_TYPE_BLOCK_DEVICE 7
+#define BINARY_INFO_TYPE_PINS_WITH_FUNC 8
+#define BINARY_INFO_TYPE_PINS_WITH_NAME 9
+#define BINARY_INFO_TYPE_PINS_WITH_NAMES 9
+#define BINARY_INFO_TYPE_NAMED_GROUP 10
+
+// note plan is to reserve c1 = 0->31 for "collision tags"; i.e.
+// for which you should always use random IDs with the binary_info,
+// giving you 4 + 8 + 32 = 44 bits to avoid collisions
+#define BINARY_INFO_MAKE_TAG(c1, c2) ((((uint)c2&0xffu)<<8u)|((uint)c1&0xffu))
+
+// Raspberry Pi defined. do not use
+#define BINARY_INFO_TAG_RASPBERRY_PI BINARY_INFO_MAKE_TAG('R','P')
+
+#define BINARY_INFO_ID_RP_PROGRAM_NAME 0x02031c86
+#define BINARY_INFO_ID_RP_PROGRAM_VERSION_STRING 0x11a9bc3a
+#define BINARY_INFO_ID_RP_PROGRAM_BUILD_DATE_STRING 0x9da22254
+#define BINARY_INFO_ID_RP_BINARY_END 0x68f465de
+#define BINARY_INFO_ID_RP_PROGRAM_URL 0x1856239a
+#define BINARY_INFO_ID_RP_PROGRAM_DESCRIPTION 0xb6a07c19
+#define BINARY_INFO_ID_RP_PROGRAM_FEATURE 0xa1f4b453
+#define BINARY_INFO_ID_RP_PROGRAM_BUILD_ATTRIBUTE 0x4275f0d3
+#define BINARY_INFO_ID_RP_SDK_VERSION 0x5360b3ab
+#define BINARY_INFO_ID_RP_PICO_BOARD 0xb63cffbb
+#define BINARY_INFO_ID_RP_BOOT2_NAME 0x7f8882e1
+
+#if PICO_ON_DEVICE
+#define bi_ptr_of(x) x *
+#else
+#define bi_ptr_of(x) uint32_t
+#endif
+typedef struct __packed _binary_info_core {
+ uint16_t type;
+ uint16_t tag;
+} binary_info_core_t;
+
+typedef struct __packed _binary_info_raw_data {
+ struct _binary_info_core core;
+ uint8_t bytes[1];
+} binary_info_raw_data_t;
+
+typedef struct __packed _binary_info_sized_data {
+ struct _binary_info_core core;
+ uint32_t length;
+ uint8_t bytes[1];
+} binary_info_sized_data_t;
+
+typedef struct __packed _binary_info_list_zero_terminated {
+ struct _binary_info_core core;
+ bi_ptr_of(binary_info_t) list;
+} binary_info_list_zero_terminated_t;
+
+typedef struct __packed _binary_info_id_and_int {
+ struct _binary_info_core core;
+ uint32_t id;
+ int32_t value;
+} binary_info_id_and_int_t;
+
+typedef struct __packed _binary_info_id_and_string {
+ struct _binary_info_core core;
+ uint32_t id;
+ bi_ptr_of(const char) value;
+} binary_info_id_and_string_t;
+
+typedef struct __packed _binary_info_block_device {
+ struct _binary_info_core core;
+ bi_ptr_of(const char) name; // optional static name (independent of what is formatted)
+ uint32_t address;
+ uint32_t size;
+ bi_ptr_of(binary_info_t) extra; // additional info
+ uint16_t flags;
+} binary_info_block_device_t;
+
+#define BI_PINS_ENCODING_RANGE 1
+#define BI_PINS_ENCODING_MULTI 2
+
+typedef struct __packed _binary_info_pins_with_func {
+ struct _binary_info_core core;
+ // p4_5 : p3_5 : p2_5 : p1_5 : p0_5 : func_4 : 001_3 //individual pins p0,p1,p2,p3,p4 ... if fewer than 5 then duplicate p
+ // phi_5 : plo_5 : func_4 : 010_3 // pin range plo-phi inclusive
+ uint32_t pin_encoding;
+} binary_info_pins_with_func_t;
+
+typedef struct __packed _binary_info_pins_with_name {
+ struct _binary_info_core core;
+ uint32_t pin_mask;
+ bi_ptr_of(const char) label;
+} binary_info_pins_with_name_t;
+
+#define BI_NAMED_GROUP_SHOW_IF_EMPTY 0x0001 // default is to hide
+#define BI_NAMED_GROUP_SEPARATE_COMMAS 0x0002 // default is newlines
+#define BI_NAMED_GROUP_SORT_ALPHA 0x0004 // default is no sort
+#define BI_NAMED_GROUP_ADVANCED 0x0008 // if set, then only shown in say info -a
+
+typedef struct __packed _binary_info_named_group {
+ struct _binary_info_core core;
+ uint32_t parent_id;
+ uint16_t flags;
+ uint16_t group_tag;
+ uint32_t group_id;
+ bi_ptr_of(const char) label;
+} binary_info_named_group_t;
+
+enum {
+ BINARY_INFO_BLOCK_DEV_FLAG_READ =
+ 1 << 0, // if not readable, then it is basically hidden, but tools may choose to avoid overwriting it
+ BINARY_INFO_BLOCK_DEV_FLAG_WRITE = 1 << 1,
+ BINARY_INFO_BLOCK_DEV_FLAG_REFORMAT = 1 << 2, // may be reformatted..
+
+ BINARY_INFO_BLOCK_DEV_FLAG_PT_UNKNOWN = 0 << 4, // unknown free to look
+ BINARY_INFO_BLOCK_DEV_FLAG_PT_MBR = 1 << 4, // expect MBR
+ BINARY_INFO_BLOCK_DEV_FLAG_PT_GPT = 2 << 4, // expect GPT
+ BINARY_INFO_BLOCK_DEV_FLAG_PT_NONE = 3 << 4, // no partition table
+};
+
+#ifdef __cplusplus
+}
+#endif
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/sync.h b/arkanoid/pico/sync.h
new file mode 100644
index 0000000..6800cc0
--- /dev/null
+++ b/arkanoid/pico/sync.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_SYNC_H
+#define _PICO_SYNC_H
+
+/** \file sync.h
+ * \defgroup pico_sync pico_sync
+ * Synchronization primitives and mutual exclusion
+ */
+
+#include "sem.h"
+#include "mutex.h"
+#include "critical_section.h"
+
+#endif
diff --git a/arkanoid/pico/time.c b/arkanoid/pico/time.c
new file mode 100644
index 0000000..77212b6
--- /dev/null
+++ b/arkanoid/pico/time.c
@@ -0,0 +1,413 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <limits.h>
+#include <inttypes.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include "pico.h"
+#include "time.h"
+#include "pheap.h"
+#include "sync.h"
+
+const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(nil_time, 0);
+const absolute_time_t ABSOLUTE_TIME_INITIALIZED_VAR(at_the_end_of_time, INT64_MAX);
+
+typedef struct alarm_pool_entry {
+ absolute_time_t target;
+ alarm_callback_t callback;
+ void *user_data;
+} alarm_pool_entry_t;
+
+typedef struct alarm_pool {
+ pheap_t *heap;
+ spin_lock_t *lock;
+ alarm_pool_entry_t *entries;
+ // one byte per entry, used to provide more longevity to public IDs than heap node ids do
+ // (this is increment every time the heap node id is re-used)
+ uint8_t *entry_ids_high;
+ alarm_id_t alarm_in_progress; // this is set during a callback from the IRQ handler... it can be cleared by alarm_cancel to prevent repeats
+ uint8_t hardware_alarm_num;
+} alarm_pool_t;
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+// To avoid bringing in calloc, we statically allocate the arrays and the heap
+PHEAP_DEFINE_STATIC(default_alarm_pool_heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS);
+static alarm_pool_entry_t default_alarm_pool_entries[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
+static uint8_t default_alarm_pool_entry_ids_high[PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS];
+static lock_core_t sleep_notifier;
+
+static alarm_pool_t default_alarm_pool = {
+ .heap = &default_alarm_pool_heap,
+ .entries = default_alarm_pool_entries,
+ .entry_ids_high = default_alarm_pool_entry_ids_high,
+};
+
+static inline bool default_alarm_pool_initialized(void) {
+ return default_alarm_pool.lock != NULL;
+}
+#endif
+
+static alarm_pool_t *pools[NUM_TIMERS];
+static void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num);
+
+
+static inline alarm_pool_entry_t *get_entry(alarm_pool_t *pool, pheap_node_id_t id) {
+ assert(id && id <= pool->heap->max_nodes);
+ return pool->entries + id - 1;
+}
+
+static inline uint8_t *get_entry_id_high(alarm_pool_t *pool, pheap_node_id_t id) {
+ assert(id && id <= pool->heap->max_nodes);
+ return pool->entry_ids_high + id - 1;
+}
+
+bool timer_pool_entry_comparator(void *user_data, pheap_node_id_t a, pheap_node_id_t b) {
+ alarm_pool_t *pool = (alarm_pool_t *)user_data;
+ return to_us_since_boot(get_entry(pool, a)->target) < to_us_since_boot(get_entry(pool, b)->target);
+}
+
+static inline alarm_id_t make_public_id(uint8_t id_high, pheap_node_id_t id) {
+ return (alarm_id_t)(((uint)id_high << 8u * sizeof(id)) | id);
+}
+
+void alarm_pool_init_default() {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+ // allow multiple calls for ease of use from host tests
+ if (!default_alarm_pool_initialized()) {
+ ph_post_alloc_init(default_alarm_pool.heap, PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS,
+ timer_pool_entry_comparator, &default_alarm_pool);
+ alarm_pool_post_alloc_init(&default_alarm_pool,
+ PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM);
+ }
+ lock_init(&sleep_notifier, PICO_SPINLOCK_ID_TIMER);
+#endif
+}
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+alarm_pool_t *alarm_pool_get_default() {
+ assert(default_alarm_pool_initialized());
+ return &default_alarm_pool;
+}
+#endif
+
+static pheap_node_id_t add_alarm_under_lock(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback,
+ void *user_data, pheap_node_id_t reuse_id, bool create_if_past, bool *missed) {
+ pheap_node_id_t id;
+ if (reuse_id) {
+ assert(!ph_contains_node(pool->heap, reuse_id));
+ id = reuse_id;
+ } else {
+ id = ph_new_node(pool->heap);
+ }
+ if (id) {
+ alarm_pool_entry_t *entry = get_entry(pool, id);
+ entry->target = time;
+ entry->callback = callback;
+ entry->user_data = user_data;
+ if (id == ph_insert_node(pool->heap, id)) {
+ bool is_missed = hardware_alarm_set_target(pool->hardware_alarm_num, time);
+ if (is_missed && !create_if_past) {
+ ph_remove_and_free_node(pool->heap, id);
+ }
+ if (missed) *missed = is_missed;
+ }
+ }
+ return id;
+}
+
+static void alarm_pool_alarm_callback(uint alarm_num) {
+ // note this is called from timer IRQ handler
+ alarm_pool_t *pool = pools[alarm_num];
+ bool again;
+ do {
+ absolute_time_t now = get_absolute_time();
+ alarm_callback_t callback = NULL;
+ absolute_time_t target = nil_time;
+ void *user_data = NULL;
+ uint8_t id_high;
+ again = false;
+ uint32_t save = spin_lock_blocking(pool->lock);
+ pheap_node_id_t next_id = ph_peek_head(pool->heap);
+ if (next_id) {
+ alarm_pool_entry_t *entry = get_entry(pool, next_id);
+ if (absolute_time_diff_us(now, entry->target) <= 0) {
+ // we don't free the id in case we need to re-add the timer
+ pheap_node_id_t __unused removed_id = ph_remove_head(pool->heap, false);
+ assert(removed_id == next_id); // will be true under lock
+ target = entry->target;
+ callback = entry->callback;
+ user_data = entry->user_data;
+ assert(callback);
+ id_high = *get_entry_id_high(pool, next_id);
+ pool->alarm_in_progress = make_public_id(id_high, removed_id);
+ } else {
+ if (hardware_alarm_set_target(alarm_num, entry->target)) {
+ again = true;
+ }
+ }
+ }
+ spin_unlock(pool->lock, save);
+ if (callback) {
+ int64_t repeat = callback(make_public_id(id_high, next_id), user_data);
+ save = spin_lock_blocking(pool->lock);
+ // todo think more about whether we want to keep calling
+ if (repeat < 0 && pool->alarm_in_progress) {
+ assert(pool->alarm_in_progress == make_public_id(id_high, next_id));
+ add_alarm_under_lock(pool, delayed_by_us(target, (uint64_t)-repeat), callback, user_data, next_id, true, NULL);
+ } else if (repeat > 0 && pool->alarm_in_progress) {
+ assert(pool->alarm_in_progress == make_public_id(id_high, next_id));
+ add_alarm_under_lock(pool, delayed_by_us(get_absolute_time(), (uint64_t)repeat), callback, user_data, next_id,
+ true, NULL);
+ } else {
+ // need to return the id to the heap
+ ph_free_node(pool->heap, next_id);
+ (*get_entry_id_high(pool, next_id))++; // we bump it for next use of id
+ }
+ pool->alarm_in_progress = 0;
+ spin_unlock(pool->lock, save);
+ again = true;
+ }
+ } while (again);
+}
+
+// note the timer is create with IRQs on this core
+alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers) {
+ alarm_pool_t *pool = (alarm_pool_t *) malloc(sizeof(alarm_pool_t));
+ pool->heap = ph_create(max_timers, timer_pool_entry_comparator, pool);
+ pool->entries = (alarm_pool_entry_t *)calloc(max_timers, sizeof(alarm_pool_entry_t));
+ pool->entry_ids_high = (uint8_t *)calloc(max_timers, sizeof(uint8_t));
+ alarm_pool_post_alloc_init(pool, hardware_alarm_num);
+ return pool;
+}
+
+void alarm_pool_post_alloc_init(alarm_pool_t *pool, uint hardware_alarm_num) {
+ hardware_alarm_claim(hardware_alarm_num);
+ hardware_alarm_cancel(hardware_alarm_num);
+ hardware_alarm_set_callback(hardware_alarm_num, alarm_pool_alarm_callback);
+ pool->lock = spin_lock_instance(next_striped_spin_lock_num());
+ pool->hardware_alarm_num = (uint8_t) hardware_alarm_num;
+ pools[hardware_alarm_num] = pool;
+}
+
+void alarm_pool_destroy(alarm_pool_t *pool) {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+ if (pool == &default_alarm_pool) {
+ assert(false); // attempt to delete default alarm pool
+ return;
+ }
+#endif
+ assert(pools[pool->hardware_alarm_num] == pool);
+ pools[pool->hardware_alarm_num] = NULL;
+ // todo clear out timers
+ ph_destroy(pool->heap);
+ hardware_alarm_set_callback(pool->hardware_alarm_num, NULL);
+ hardware_alarm_unclaim(pool->hardware_alarm_num);
+ free(pool->entry_ids_high);
+ free(pool->entries);
+ free(pool);
+}
+
+alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback,
+ void *user_data, bool fire_if_past) {
+ bool missed = false;
+
+ alarm_id_t public_id;
+ do {
+ uint8_t id_high = 0;
+ uint32_t save = spin_lock_blocking(pool->lock);
+
+ pheap_node_id_t id = add_alarm_under_lock(pool, time, callback, user_data, 0, false, &missed);
+ if (id) id_high = *get_entry_id_high(pool, id);
+
+ spin_unlock(pool->lock, save);
+
+ if (!id) {
+ // no space in pheap to allocate an alarm
+ return -1;
+ }
+
+ // note that if missed was true, then the id was never added to the pheap (because we
+ // passed false for create_if_past arg above)
+ public_id = missed ? 0 : make_public_id(id_high, id);
+ if (missed && fire_if_past) {
+ // ... so if fire_if_past == true we call the callback
+ int64_t repeat = callback(public_id, user_data);
+ // if not repeated we have no id to return so set public_id to 0,
+ // otherwise we need to repeat, but will assign a new id next time
+ // todo arguably this does mean that the id passed to the first callback may differ from subsequent calls
+ if (!repeat) {
+ public_id = 0;
+ break;
+ } else if (repeat < 0) {
+ time = delayed_by_us(time, (uint64_t)-repeat);
+ } else {
+ time = delayed_by_us(get_absolute_time(), (uint64_t)repeat);
+ }
+ } else {
+ // either:
+ // a) missed == false && public_id is > 0
+ // b) missed == true && fire_if_past == false && public_id = 0
+ // but we are done in either case
+ break;
+ }
+ } while (true);
+ return public_id;
+}
+
+bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id) {
+ bool rc = false;
+ uint32_t save = spin_lock_blocking(pool->lock);
+ pheap_node_id_t id = (pheap_node_id_t) alarm_id;
+ if (ph_contains_node(pool->heap, id)) {
+ assert(alarm_id != pool->alarm_in_progress); // it shouldn't be in the heap if it is in progress
+ // check we have the right high value
+ uint8_t id_high = (uint8_t)((uint)alarm_id >> 8u * sizeof(pheap_node_id_t));
+ if (id_high == *get_entry_id_high(pool, id)) {
+ rc = ph_remove_and_free_node(pool->heap, id);
+ // note we don't bother to remove the actual hardware alarm timeout...
+ // it will either do callbacks or not depending on other alarms, and reset the next timeout itself
+ assert(rc);
+ }
+ } else {
+ if (alarm_id == pool->alarm_in_progress) {
+ // make sure the alarm doesn't repeat
+ pool->alarm_in_progress = 0;
+ }
+ }
+ spin_unlock(pool->lock, save);
+ return rc;
+}
+
+uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool) {
+ return pool->hardware_alarm_num;
+}
+
+static void alarm_pool_dump_key(pheap_node_id_t id, void *user_data) {
+ alarm_pool_t *pool = (alarm_pool_t *)user_data;
+#if PICO_ON_DEVICE
+ printf("%lld (hi %02x)", to_us_since_boot(get_entry(pool, id)->target), *get_entry_id_high(pool, id));
+#else
+ printf("%"PRIu64, to_us_since_boot(get_entry(pool, id)->target));
+#endif
+}
+
+static int64_t repeating_timer_callback(__unused alarm_id_t id, void *user_data) {
+ repeating_timer_t *rt = (repeating_timer_t *)user_data;
+ assert(rt->alarm_id == id);
+ if (rt->callback(rt)) {
+ return rt->delay_us;
+ } else {
+ rt->alarm_id = 0;
+ return 0;
+ }
+}
+
+bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+ if (!delay_us) delay_us = 1;
+ out->pool = pool;
+ out->callback = callback;
+ out->delay_us = delay_us;
+ out->user_data = user_data;
+ out->alarm_id = alarm_pool_add_alarm_at(pool, make_timeout_time_us((uint64_t)(delay_us >= 0 ? delay_us : -delay_us)),
+ repeating_timer_callback, out, true);
+ // note that if out->alarm_id is 0, then the callback was called during the above call (fire_if_past == true)
+ // and then the callback removed itself.
+ return out->alarm_id >= 0;
+}
+
+bool cancel_repeating_timer(repeating_timer_t *timer) {
+ bool rc = false;
+ if (timer->alarm_id) {
+ rc = alarm_pool_cancel_alarm(timer->pool, timer->alarm_id);
+ timer->alarm_id = 0;
+ }
+ return rc;
+}
+
+void alarm_pool_dump(alarm_pool_t *pool) {
+ uint32_t save = spin_lock_blocking(pool->lock);
+ ph_dump(pool->heap, alarm_pool_dump_key, pool);
+ spin_unlock(pool->lock, save);
+}
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+static int64_t sleep_until_callback(__unused alarm_id_t id, __unused void *user_data) {
+ uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock);
+ lock_internal_spin_unlock_with_notify(&sleep_notifier, save);
+ return 0;
+}
+#endif
+
+void sleep_until(absolute_time_t t) {
+#if PICO_ON_DEVICE && !defined(NDEBUG)
+ if (__get_current_exception()) {
+ panic("Attempted to sleep inside of an exception handler; use busy_wait if you must");
+ }
+#endif
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+ uint64_t t_us = to_us_since_boot(t);
+ uint64_t t_before_us = t_us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US;
+ // needs to work in the first PICO_TIME_SLEEP_OVERHEAD_ADJUST_US of boot
+ if (t_before_us > t_us) t_before_us = 0;
+ absolute_time_t t_before;
+ update_us_since_boot(&t_before, t_before_us);
+ if (absolute_time_diff_us(get_absolute_time(), t_before) > 0) {
+ if (add_alarm_at(t_before, sleep_until_callback, NULL, false) >= 0) {
+ // able to add alarm for just before the time
+ while (!time_reached(t_before)) {
+ uint32_t save = spin_lock_blocking(sleep_notifier.spin_lock);
+ lock_internal_spin_unlock_with_wait(&sleep_notifier, save);
+ }
+ }
+ }
+#else
+ // hook in case we're in RTOS; note we assume using the alarm pool is better always if available.
+ sync_internal_yield_until_before(t);
+#endif
+ // now wait until the exact time
+ busy_wait_until(t);
+}
+
+void sleep_us(uint64_t us) {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+ sleep_until(make_timeout_time_us(us));
+#else
+ if (us < PICO_TIME_SLEEP_OVERHEAD_ADJUST_US) {
+ busy_wait_us(us);
+ } else {
+ // hook in case we're in RTOS; note we assume using the alarm pool is better always if available.
+ absolute_time_t t = make_timeout_time_us(us - PICO_TIME_SLEEP_OVERHEAD_ADJUST_US);
+ sync_internal_yield_until_before(t);
+
+ // then wait the rest of thw way
+ busy_wait_until(t);
+ }
+#endif
+}
+
+void sleep_ms(uint32_t ms) {
+ sleep_us(ms * 1000ull);
+}
+
+bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp) {
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+ alarm_id_t id;
+ id = add_alarm_at(timeout_timestamp, sleep_until_callback, NULL, false);
+ if (id <= 0) {
+ tight_loop_contents();
+ return time_reached(timeout_timestamp);
+ } else {
+ __wfe();
+ // we need to clean up if it wasn't us that caused the wfe; if it was this will be a noop.
+ cancel_alarm(id);
+ return time_reached(timeout_timestamp);
+ }
+#else
+ tight_loop_contents();
+ return time_reached(timeout_timestamp);
+#endif
+}
diff --git a/arkanoid/pico/time.h b/arkanoid/pico/time.h
new file mode 100644
index 0000000..c00b7a8
--- /dev/null
+++ b/arkanoid/pico/time.h
@@ -0,0 +1,716 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_TIME_H
+#define _PICO_TIME_H
+
+#include "pico.h"
+#include "hardware/timer.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file time.h
+ * \defgroup pico_time pico_time
+ *
+ * API for accurate timestamps, sleeping, and time based callbacks
+ *
+ * \note The functions defined here provide a much more powerful and user friendly wrapping around the
+ * low level hardware timer functionality. For these functions (and any other SDK functionality
+ * e.g. timeouts, that relies on them) to work correctly, the hardware timer should not be modified. i.e. it is expected
+ * to be monotonically increasing once per microsecond. Fortunately there is no need to modify the hardware
+ * timer as any functionality you can think of that isn't already covered here can easily be modelled
+ * by adding or subtracting a constant value from the unmodified hardware timer.
+ *
+ * \sa \ref hardware_timer
+ */
+
+// PICO_CONFIG: PARAM_ASSERTIONS_ENABLED_TIME, Enable/disable assertions in the time module, type=bool, default=0, group=pico_time
+#ifndef PARAM_ASSERTIONS_ENABLED_TIME
+#define PARAM_ASSERTIONS_ENABLED_TIME 0
+#endif
+
+// PICO_CONFIG: PICO_TIME_SLEEP_OVERHEAD_ADJUST_US, How many microseconds to wake up early (and then busy_wait) to account for timer overhead when sleeping in low power mode, type=int, default=6, group=pico_time
+#ifndef PICO_TIME_SLEEP_OVERHEAD_ADJUST_US
+#define PICO_TIME_SLEEP_OVERHEAD_ADJUST_US 6
+#endif
+/*!
+ * \defgroup timestamp timestamp
+ * \ingroup pico_time
+ * \brief Timestamp functions relating to points in time (including the current time)
+ *
+ * These are functions for dealing with timestamps (i.e. instants in time) represented by the type absolute_time_t. This opaque
+ * type is provided to help prevent accidental mixing of timestamps and relative time values.
+ */
+
+/*! \brief Return a representation of the current time.
+ * \ingroup timestamp
+ *
+ * Returns an opaque high fidelity representation of the current time sampled during the call.
+ *
+ * \return the absolute time (now) of the hardware timer
+ *
+ * \sa absolute_time_t
+ * \sa sleep_until()
+ * \sa time_us_64()
+ */
+static inline absolute_time_t get_absolute_time(void) {
+ absolute_time_t t;
+ update_us_since_boot(&t, time_us_64());
+ return t;
+}
+
+static inline uint32_t us_to_ms(uint64_t us) {
+ if (us >> 32u) {
+ return (uint32_t)(us / 1000u);
+ } else {
+ return ((uint32_t)us) / 1000u;
+ }
+}
+
+/*! fn to_ms_since_boot
+ * \ingroup timestamp
+ * \brief Convert a timestamp into a number of milliseconds since boot.
+ * \param t an absolute_time_t value to convert
+ * \return the number of microseconds since boot represented by t
+ * \sa to_us_since_boot()
+ */
+static inline uint32_t to_ms_since_boot(absolute_time_t t) {
+ uint64_t us = to_us_since_boot(t);
+ return us_to_ms(us);
+}
+
+/*! \brief Return a timestamp value obtained by adding a number of microseconds to another timestamp
+ * \ingroup timestamp
+ *
+ * \param t the base timestamp
+ * \param us the number of microseconds to add
+ * \return the timestamp representing the resulting time
+ */
+static inline absolute_time_t delayed_by_us(const absolute_time_t t, uint64_t us) {
+ absolute_time_t t2;
+ uint64_t base = to_us_since_boot(t);
+ uint64_t delayed = base + us;
+ if (delayed < base) {
+ delayed = (uint64_t)-1;
+ }
+ update_us_since_boot(&t2, delayed);
+ return t2;
+}
+
+/*! \brief Return a timestamp value obtained by adding a number of milliseconds to another timestamp
+ * \ingroup timestamp
+ *
+ * \param t the base timestamp
+ * \param ms the number of milliseconds to add
+ * \return the timestamp representing the resulting time
+ */
+static inline absolute_time_t delayed_by_ms(const absolute_time_t t, uint32_t ms) {
+ absolute_time_t t2;
+ uint64_t base = to_us_since_boot(t);
+ uint64_t delayed = base + ms * 1000ull;
+ if (delayed < base) {
+ delayed = (uint64_t)-1;
+ }
+ update_us_since_boot(&t2, delayed);
+ return t2;
+}
+
+/*! \brief Convenience method to get the timestamp a number of microseconds from the current time
+ * \ingroup timestamp
+ *
+ * \param us the number of microseconds to add to the current timestamp
+ * \return the future timestamp
+ */
+static inline absolute_time_t make_timeout_time_us(uint64_t us) {
+ return delayed_by_us(get_absolute_time(), us);
+}
+
+/*! \brief Convenience method to get the timestamp a number of milliseconds from the current time
+ * \ingroup timestamp
+ *
+ * \param ms the number of milliseconds to add to the current timestamp
+ * \return the future timestamp
+ */
+static inline absolute_time_t make_timeout_time_ms(uint32_t ms) {
+ return delayed_by_ms(get_absolute_time(), ms);
+}
+
+/*! \brief Return the difference in microseconds between two timestamps
+ * \ingroup timestamp
+ *
+ * \note be careful when diffing against large timestamps (e.g. \ref at_the_end_of_time)
+ * as the signed integer may overflow.
+ *
+ * \param from the first timestamp
+ * \param to the second timestamp
+ * \return the number of microseconds between the two timestamps (positive if `to` is after `from` except
+ * in case of overflow)
+ */
+static inline int64_t absolute_time_diff_us(absolute_time_t from, absolute_time_t to) {
+ return (int64_t)(to_us_since_boot(to) - to_us_since_boot(from));
+}
+
+/*! \brief The timestamp representing the end of time; this is actually not the maximum possible
+ * timestamp, but is set to 0x7fffffff_ffffffff microseconds to avoid sign overflows with time
+ * arithmetic. This is still over 7 million years, so should be sufficient.
+ * \ingroup timestamp
+ */
+extern const absolute_time_t at_the_end_of_time;
+
+/*! \brief The timestamp representing a null timestamp
+ * \ingroup timestamp
+ */
+extern const absolute_time_t nil_time;
+
+/*! \brief Determine if the given timestamp is nil
+ * \ingroup timestamp
+ * \param t the timestamp
+ * \return true if the timestamp is nil
+ * \sa nil_time
+ */
+static inline bool is_nil_time(absolute_time_t t) {
+ return !to_us_since_boot(t);
+}
+
+/*!
+ * \defgroup sleep sleep
+ * \ingroup pico_time
+ * \brief Sleep functions for delaying execution in a lower power state.
+ *
+ * These functions allow the calling core to sleep. This is a lower powered sleep; waking and re-checking time on every processor
+ * event (WFE)
+ *
+ * \note These functions should not be called from an IRQ handler.
+ *
+ * \note Lower powered sleep requires use of the \link alarm_pool_get_default default alarm pool\endlink which may
+ * be disabled by the #PICO_TIME_DEFAULT_ALARM_POOL_DISABLED define or currently full in which case these functions
+ * become busy waits instead.
+ *
+ * \note Whilst \a sleep_ functions are preferable to \a busy_wait functions from a power perspective, the \a busy_wait equivalent function
+ * may return slightly sooner after the target is reached.
+ *
+ * \sa busy_wait_until() \sa busy_wait_us() \sa busy_wait_us_32()
+ */
+
+/*! \brief Wait until after the given timestamp to return
+ * \ingroup sleep
+ *
+ * \note This method attempts to perform a lower power (WFE) sleep
+ *
+ * \param target the time after which to return
+ * \sa sleep_us()
+ * \sa busy_wait_until()
+ * */
+void sleep_until(absolute_time_t target);
+
+/*! \brief Wait for the given number of microseconds before returning
+ * \ingroup sleep
+ *
+ * \note This method attempts to perform a lower power (WFE) sleep
+ *
+ * \param us the number of microseconds to sleep
+ * \sa busy_wait_us()
+ */
+void sleep_us(uint64_t us);
+
+/*! \brief Wait for the given number of milliseconds before returning
+ * \ingroup sleep
+ *
+ * \note This method attempts to perform a lower power sleep (using WFE) as much as possible.
+ *
+ * \param ms the number of milliseconds to sleep
+ */
+void sleep_ms(uint32_t ms);
+
+/*! \brief Helper method for blocking on a timeout
+ * \ingroup sleep
+ *
+ * This method will return in response to an event (as per __wfe) or
+ * when the target time is reached, or at any point before.
+ *
+ * This method can be used to implement a lower power polling loop waiting on
+ * some condition signalled by an event (__sev()).
+ *
+ * This is called \a best_effort because under certain circumstances (notably the default timer pool
+ * being disabled or full) the best effort is simply to return immediately without a __wfe, thus turning the calling
+ * code into a busy wait.
+ *
+ * Example usage:
+ * ```c
+ * bool my_function_with_timeout_us(uint64_t timeout_us) {
+ * absolute_time_t timeout_time = make_timeout_time_us(timeout_us);
+ * do {
+ * // each time round the loop, we check to see if the condition
+ * // we are waiting on has happened
+ * if (my_check_done()) {
+ * // do something
+ * return true;
+ * }
+ * // will try to sleep until timeout or the next processor event
+ * } while (!best_effort_wfe_or_timeout(timeout_time));
+ * return false; // timed out
+ * }
+ * ```
+ *
+ * @param timeout_timestamp the timeout time
+ * @return true if the target time is reached, false otherwise
+ */
+bool best_effort_wfe_or_timeout(absolute_time_t timeout_timestamp);
+
+/*!
+ * \defgroup alarm alarm
+ * \ingroup pico_time
+ * \brief Alarm functions for scheduling future execution
+ *
+ * Alarms are added to alarm pools, which may hold a certain fixed number of active alarms. Each alarm pool
+ * utilizes one of four underlying hardware alarms, thus you may have up to four alarm pools. An alarm pool
+ * calls (except when the callback would happen before or during being set) the callback on the core from which
+ * the alarm pool was created. Callbacks are called from the hardware alarm IRQ handler, so care must
+ * be taken in their implementation.
+ *
+ * A default pool is created the core specified by PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ * on core 0, and may be used by the method variants that take no alarm pool parameter.
+ *
+ * \sa struct alarm_pool
+ * \sa hardware_timer
+ */
+
+// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_DISABLED, Disable the default alarm pool, type=bool, default=0, advanced=true, group=pico_time
+#ifndef PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief If 1 then the default alarm pool is disabled (so no hardware alarm is claimed for the pool)
+ *
+ * \note Setting to 1 may cause some code not to compile as default timer pool related methods are removed
+ *
+ * \note When the default alarm pool is disabled, \a sleep_ methods and timeouts are no longer lower powered
+ * (they become \a busy_wait_)
+ *
+ * \ingroup alarm
+ * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ * \sa alarm_pool_get_default()
+ */
+#define PICO_TIME_DEFAULT_ALARM_POOL_DISABLED 0
+#endif
+
+// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM, Select which HW alarm is used for the default alarm pool, min=0, max=3, default=3, advanced=true, group=pico_time
+#ifndef PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+/*!
+ * \brief Selects which hardware alarm is used for the default alarm pool
+ * \ingroup alarm
+ * \sa alarm_pool_get_default()
+ */
+#define PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM 3
+#endif
+
+// PICO_CONFIG: PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS, Selects the maximum number of concurrent timers in the default alarm pool, min=0, max=255, default=16, advanced=true, group=pico_time
+#ifndef PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS
+/*!
+ * \brief Selects the maximum number of concurrent timers in the default alarm pool
+ * \ingroup alarm
+ *
+ * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255
+ * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ * \sa alarm_pool_get_default()
+ */
+#define PICO_TIME_DEFAULT_ALARM_POOL_MAX_TIMERS 16
+#endif
+
+/**
+ * \brief The identifier for an alarm
+ *
+ * \note this identifier is signed because -1 is used as an error condition when creating alarms
+ *
+ * \note alarm ids may be reused, however for convenience the implementation makes an attempt to defer
+ * reusing as long as possible. You should certainly expect it to be hundreds of ids before one is
+ * reused, although in most cases it is more. Nonetheless care must still be taken when cancelling
+ * alarms or other functionality based on alarms when the alarm may have expired, as eventually
+ * the alarm id may be reused for another alarm.
+ *
+ * \ingroup alarm
+ */
+typedef int32_t alarm_id_t; // note this is signed because we use -1 as a meaningful error value
+
+/**
+ * \brief User alarm callback
+ * \ingroup alarm
+ * \param id the alarm_id as returned when the alarm was added
+ * \param user_data the user data passed when the alarm was added
+ * \return <0 to reschedule the same alarm this many us from the time the alarm was previously scheduled to fire
+ * \return >0 to reschedule the same alarm this many us from the time this method returns
+ * \return 0 to not reschedule the alarm
+ */
+typedef int64_t (*alarm_callback_t)(alarm_id_t id, void *user_data);
+
+typedef struct alarm_pool alarm_pool_t;
+
+/**
+ * \brief Create the default alarm pool (if not already created or disabled)
+ * \ingroup alarm
+ */
+void alarm_pool_init_default(void);
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief The default alarm pool used when alarms are added without specifying an alarm pool,
+ * and also used by the SDK to support lower power sleeps and timeouts.
+ *
+ * \ingroup alarm
+ * \sa #PICO_TIME_DEFAULT_ALARM_POOL_HARDWARE_ALARM_NUM
+ */
+alarm_pool_t *alarm_pool_get_default(void);
+#endif
+
+/**
+ * \brief Create an alarm pool
+ *
+ * The alarm pool will call callbacks from an alarm IRQ Handler on the core of this function is called from.
+ *
+ * In many situations there is never any need for anything other than the default alarm pool, however you
+ * might want to create another if you want alarm callbacks on core 1 or require alarm pools of
+ * different priority (IRQ priority based preemption of callbacks)
+ *
+ * \note This method will hard assert if the hardware alarm is already claimed.
+ *
+ * \ingroup alarm
+ * \param hardware_alarm_num the hardware alarm to use to back this pool
+ * \param max_timers the maximum number of timers
+ * \note For implementation reasons this is limited to PICO_PHEAP_MAX_ENTRIES which defaults to 255
+ * \sa alarm_pool_get_default()
+ * \sa hardware_claiming
+ */
+alarm_pool_t *alarm_pool_create(uint hardware_alarm_num, uint max_timers);
+
+/**
+ * \brief Return the hardware alarm used by an alarm pool
+ * \ingroup alarm
+ * \param pool the pool
+ * \return the hardware alarm used by the pool
+ */
+uint alarm_pool_hardware_alarm_num(alarm_pool_t *pool);
+
+/**
+ * \brief Destroy the alarm pool, cancelling all alarms and freeing up the underlying hardware alarm
+ * \ingroup alarm
+ * \param pool the pool
+ * \return the hardware alarm used by the pool
+ */
+void alarm_pool_destroy(alarm_pool_t *pool);
+
+/*!
+ * \brief Add an alarm callback to be called at a specific time
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)
+ * @param time the timestamp when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ * then the callback should be called during (by) this function instead
+ * @return >0 the alarm id for an active (at the time of return) alarm
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ * The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ * or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+alarm_id_t alarm_pool_add_alarm_at(alarm_pool_t *pool, absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past);
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in microseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)
+ * @param us the delay (from now) in microseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ * then the callback should be called during (by) this function instead
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ * The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ * or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t alarm_pool_add_alarm_in_us(alarm_pool_t *pool, uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+ return alarm_pool_add_alarm_at(pool, delayed_by_us(get_absolute_time(), us), callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in milliseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the callback (this determines which hardware alarm is used, and which core calls the callback)
+ * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ * then the callback should be called during (by) this function instead
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ * The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ * or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t alarm_pool_add_alarm_in_ms(alarm_pool_t *pool, uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+ return alarm_pool_add_alarm_at(pool, delayed_by_ms(get_absolute_time(), ms), callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Cancel an alarm
+ * \ingroup alarm
+ * \param pool the alarm_pool containing the alarm
+ * \param alarm_id the alarm
+ * \return true if the alarm was cancelled, false if it didn't exist
+ * \sa alarm_id_t for a note on reuse of IDs
+ */
+bool alarm_pool_cancel_alarm(alarm_pool_t *pool, alarm_id_t alarm_id);
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief Add an alarm callback to be called at a specific time
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param time the timestamp when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls before or during this call before the alarm can be set,
+ * then the callback should be called during (by) this function instead
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ * The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ * or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t add_alarm_at(absolute_time_t time, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+ return alarm_pool_add_alarm_at(alarm_pool_get_default(), time, callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in microseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param us the delay (from now) in microseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ * then the callback should be called during (by) this function instead
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ * The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ * or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t add_alarm_in_us(uint64_t us, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+ return alarm_pool_add_alarm_in_us(alarm_pool_get_default(), us, callback, user_data, fire_if_past);
+}
+
+/*!
+ * \brief Add an alarm callback to be called after a delay specified in milliseconds
+ * \ingroup alarm
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param ms the delay (from now) in milliseconds when (after which) the callback should fire
+ * @param callback the callback function
+ * @param user_data user data to pass to the callback function
+ * @param fire_if_past if true, and the alarm time falls during this call before the alarm can be set,
+ * then the callback should be called during (by) this function instead
+ * @return >0 the alarm id
+ * @return 0 if the alarm time passed before or during the call AND there is no active alarm to return the id of.
+ * The latter can either happen because fire_if_past was false (i.e. no timer was ever created),
+ * or if the callback <i>was</i> called during this method but the callback cancelled itself by returning 0
+ * @return -1 if there were no alarm slots available
+ */
+static inline alarm_id_t add_alarm_in_ms(uint32_t ms, alarm_callback_t callback, void *user_data, bool fire_if_past) {
+ return alarm_pool_add_alarm_in_ms(alarm_pool_get_default(), ms, callback, user_data, fire_if_past);
+}
+/*!
+ * \brief Cancel an alarm from the default alarm pool
+ * \ingroup alarm
+ * \param alarm_id the alarm
+ * \return true if the alarm was cancelled, false if it didn't exist
+ * \sa alarm_id_t for a note on reuse of IDs
+ */
+static inline bool cancel_alarm(alarm_id_t alarm_id) {
+ return alarm_pool_cancel_alarm(alarm_pool_get_default(), alarm_id);
+}
+
+#endif
+
+/*!
+ * \defgroup repeating_timer repeating_timer
+ * \ingroup pico_time
+ * \brief Repeating Timer functions for simple scheduling of repeated execution
+ *
+ * \note The regular \a alarm_ functionality can be used to make repeating alarms (by return non zero from the callback),
+ * however these methods abstract that further (at the cost of a user structure to store the repeat delay in (which
+ * the alarm framework does not have space for).
+ */
+
+typedef struct repeating_timer repeating_timer_t;
+
+/**
+ * \brief Callback for a repeating timer
+ * \ingroup repeating_timer
+ * \param rt repeating time structure containing information about the repeating time. user_data is of primary important to the user
+ * \return true to continue repeating, false to stop.
+ */
+typedef bool (*repeating_timer_callback_t)(repeating_timer_t *rt);
+
+/**
+ * \brief Information about a repeating timer
+ * \ingroup repeating_timer
+ * \return
+ */
+struct repeating_timer {
+ int64_t delay_us;
+ alarm_pool_t *pool;
+ alarm_id_t alarm_id;
+ repeating_timer_callback_t callback;
+ void *user_data;
+};
+
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback)
+ * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+bool alarm_pool_add_repeating_timer_us(alarm_pool_t *pool, int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out);
+
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core the alarm pool was created on. If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param pool the alarm pool to use for scheduling the repeating timer (this determines which hardware alarm is used, and which core calls the callback)
+ * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+static inline bool alarm_pool_add_repeating_timer_ms(alarm_pool_t *pool, int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+ return alarm_pool_add_repeating_timer_us(pool, delay_ms * (int64_t)1000, callback, user_data, out);
+}
+
+#if !PICO_TIME_DEFAULT_ALARM_POOL_DISABLED
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in microseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param delay_us the repeat delay in microseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+static inline bool add_repeating_timer_us(int64_t delay_us, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+ return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_us, callback, user_data, out);
+}
+
+/*!
+ * \brief Add a repeating timer that is called repeatedly at the specified interval in milliseconds
+ * \ingroup repeating_timer
+ *
+ * Generally the callback is called as soon as possible after the time specified from an IRQ handler
+ * on the core of the default alarm pool (generally core 0). If the callback is in the past or happens before
+ * the alarm setup could be completed, then this method will optionally call the callback itself
+ * and then return a return code to indicate that the target time has passed.
+ *
+ * \note It is safe to call this method from an IRQ handler (including alarm callbacks), and from either core.
+ *
+ * @param delay_ms the repeat delay in milliseconds; if >0 then this is the delay between one callback ending and the next starting; if <0 then this is the negative of the time between the starts of the callbacks. The value of 0 is treated as 1 microsecond
+ * @param callback the repeating timer callback function
+ * @param user_data user data to pass to store in the repeating_timer structure for use by the callback.
+ * @param out the pointer to the user owned structure to store the repeating timer info in. BEWARE this storage location must outlive the repeating timer, so be careful of using stack space
+ * @return false if there were no alarm slots available to create the timer, true otherwise.
+ */
+static inline bool add_repeating_timer_ms(int32_t delay_ms, repeating_timer_callback_t callback, void *user_data, repeating_timer_t *out) {
+ return alarm_pool_add_repeating_timer_us(alarm_pool_get_default(), delay_ms * (int64_t)1000, callback, user_data, out);
+}
+#endif
+
+/**
+ * \brief Cancel a repeating timer
+ * \ingroup repeating_timer
+ * \param timer the repeating timer to cancel
+ * \return true if the repeating timer was cancelled, false if it didn't exist
+ * \sa alarm_id_t for a note on reuse of IDs
+ */
+bool cancel_repeating_timer(repeating_timer_t *timer);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/timeout_helper.c b/arkanoid/pico/timeout_helper.c
new file mode 100644
index 0000000..cdd99e2
--- /dev/null
+++ b/arkanoid/pico/timeout_helper.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "timeout_helper.h"
+
+static bool check_single_timeout_us(timeout_state_t *ts) {
+ return time_reached(ts->next_timeout);
+}
+
+check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target) {
+ ts->next_timeout = target;
+ return check_single_timeout_us;
+}
+
+static bool check_per_iteration_timeout_us(timeout_state_t *ts) {
+ if (time_reached(ts->next_timeout)) {
+ return true;
+ }
+ ts->next_timeout = make_timeout_time_us(ts->param);
+ return false;
+}
+
+check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us) {
+ ts->next_timeout = make_timeout_time_us(per_iteration_timeout_us);
+ ts->param = per_iteration_timeout_us;
+ return check_per_iteration_timeout_us;
+}
diff --git a/arkanoid/pico/timeout_helper.h b/arkanoid/pico/timeout_helper.h
new file mode 100644
index 0000000..5d37ab4
--- /dev/null
+++ b/arkanoid/pico/timeout_helper.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_TIMEOUT_HELPER_H
+#define _PICO_TIMEOUT_HELPER_H
+
+#include "time.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct timeout_state {
+ absolute_time_t next_timeout;
+ uint64_t param;
+} timeout_state_t;
+
+typedef bool (*check_timeout_fn)(timeout_state_t *ts);
+
+check_timeout_fn init_single_timeout_until(timeout_state_t *ts, absolute_time_t target);
+check_timeout_fn init_per_iteration_timeout_us(timeout_state_t *ts, uint64_t per_iteration_timeout_us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico/tinyusb/cdc/cdc.h b/arkanoid/pico/tinyusb/cdc/cdc.h
new file mode 100644
index 0000000..0417b2a
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc.h
@@ -0,0 +1,409 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup group_class
+ * \defgroup ClassDriver_CDC Communication Device Class (CDC)
+ * Currently only Abstract Control Model subclass is supported
+ * @{ */
+
+#ifndef _TUSB_CDC_H__
+#define _TUSB_CDC_H__
+
+#include "../tusb_common.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \defgroup ClassDriver_CDC_Common Common Definitions
+ * @{ */
+
+// TODO remove
+/// CDC Pipe ID, used to indicate which pipe the API is addressing to (Notification, Out, In)
+typedef enum
+{
+ CDC_PIPE_NOTIFICATION , ///< Notification pipe
+ CDC_PIPE_DATA_IN , ///< Data in pipe
+ CDC_PIPE_DATA_OUT , ///< Data out pipe
+ CDC_PIPE_ERROR , ///< Invalid Pipe ID
+}cdc_pipeid_t;
+
+//--------------------------------------------------------------------+
+// CDC Communication Interface Class
+//--------------------------------------------------------------------+
+
+/// Communication Interface Subclass Codes
+typedef enum
+{
+ CDC_COMM_SUBCLASS_DIRECT_LINE_CONTROL_MODEL = 0x01 , ///< Direct Line Control Model [USBPSTN1.2]
+ CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL = 0x02 , ///< Abstract Control Model [USBPSTN1.2]
+ CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL = 0x03 , ///< Telephone Control Model [USBPSTN1.2]
+ CDC_COMM_SUBCLASS_MULTICHANNEL_CONTROL_MODEL = 0x04 , ///< Multi-Channel Control Model [USBISDN1.2]
+ CDC_COMM_SUBCLASS_CAPI_CONTROL_MODEL = 0x05 , ///< CAPI Control Model [USBISDN1.2]
+ CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL = 0x06 , ///< Ethernet Networking Control Model [USBECM1.2]
+ CDC_COMM_SUBCLASS_ATM_NETWORKING_CONTROL_MODEL = 0x07 , ///< ATM Networking Control Model [USBATM1.2]
+ CDC_COMM_SUBCLASS_WIRELESS_HANDSET_CONTROL_MODEL = 0x08 , ///< Wireless Handset Control Model [USBWMC1.1]
+ CDC_COMM_SUBCLASS_DEVICE_MANAGEMENT = 0x09 , ///< Device Management [USBWMC1.1]
+ CDC_COMM_SUBCLASS_MOBILE_DIRECT_LINE_MODEL = 0x0A , ///< Mobile Direct Line Model [USBWMC1.1]
+ CDC_COMM_SUBCLASS_OBEX = 0x0B , ///< OBEX [USBWMC1.1]
+ CDC_COMM_SUBCLASS_ETHERNET_EMULATION_MODEL = 0x0C , ///< Ethernet Emulation Model [USBEEM1.0]
+ CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL = 0x0D ///< Network Control Model [USBNCM1.0]
+} cdc_comm_sublcass_type_t;
+
+/// Communication Interface Protocol Codes
+typedef enum
+{
+ CDC_COMM_PROTOCOL_NONE = 0x00 , ///< No specific protocol
+ CDC_COMM_PROTOCOL_ATCOMMAND = 0x01 , ///< AT Commands: V.250 etc
+ CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101 = 0x02 , ///< AT Commands defined by PCCA-101
+ CDC_COMM_PROTOCOL_ATCOMMAND_PCCA_101_AND_ANNEXO = 0x03 , ///< AT Commands defined by PCCA-101 & Annex O
+ CDC_COMM_PROTOCOL_ATCOMMAND_GSM_707 = 0x04 , ///< AT Commands defined by GSM 07.07
+ CDC_COMM_PROTOCOL_ATCOMMAND_3GPP_27007 = 0x05 , ///< AT Commands defined by 3GPP 27.007
+ CDC_COMM_PROTOCOL_ATCOMMAND_CDMA = 0x06 , ///< AT Commands defined by TIA for CDMA
+ CDC_COMM_PROTOCOL_ETHERNET_EMULATION_MODEL = 0x07 ///< Ethernet Emulation Model
+} cdc_comm_protocol_type_t;
+
+//------------- SubType Descriptor in COMM Functional Descriptor -------------//
+/// Communication Interface SubType Descriptor
+typedef enum
+{
+ CDC_FUNC_DESC_HEADER = 0x00 , ///< Header Functional Descriptor, which marks the beginning of the concatenated set of functional descriptors for the interface.
+ CDC_FUNC_DESC_CALL_MANAGEMENT = 0x01 , ///< Call Management Functional Descriptor.
+ CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT = 0x02 , ///< Abstract Control Management Functional Descriptor.
+ CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT = 0x03 , ///< Direct Line Management Functional Descriptor.
+ CDC_FUNC_DESC_TELEPHONE_RINGER = 0x04 , ///< Telephone Ringer Functional Descriptor.
+ CDC_FUNC_DESC_TELEPHONE_CALL_AND_LINE_STATE_REPORTING_CAPACITY = 0x05 , ///< Telephone Call and Line State Reporting Capabilities Functional Descriptor.
+ CDC_FUNC_DESC_UNION = 0x06 , ///< Union Functional Descriptor
+ CDC_FUNC_DESC_COUNTRY_SELECTION = 0x07 , ///< Country Selection Functional Descriptor
+ CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES = 0x08 , ///< Telephone Operational ModesFunctional Descriptor
+ CDC_FUNC_DESC_USB_TERMINAL = 0x09 , ///< USB Terminal Functional Descriptor
+ CDC_FUNC_DESC_NETWORK_CHANNEL_TERMINAL = 0x0A , ///< Network Channel Terminal Descriptor
+ CDC_FUNC_DESC_PROTOCOL_UNIT = 0x0B , ///< Protocol Unit Functional Descriptor
+ CDC_FUNC_DESC_EXTENSION_UNIT = 0x0C , ///< Extension Unit Functional Descriptor
+ CDC_FUNC_DESC_MULTICHANEL_MANAGEMENT = 0x0D , ///< Multi-Channel Management Functional Descriptor
+ CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT = 0x0E , ///< CAPI Control Management Functional Descriptor
+ CDC_FUNC_DESC_ETHERNET_NETWORKING = 0x0F , ///< Ethernet Networking Functional Descriptor
+ CDC_FUNC_DESC_ATM_NETWORKING = 0x10 , ///< ATM Networking Functional Descriptor
+ CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL = 0x11 , ///< Wireless Handset Control Model Functional Descriptor
+ CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL = 0x12 , ///< Mobile Direct Line Model Functional Descriptor
+ CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL = 0x13 , ///< MDLM Detail Functional Descriptor
+ CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL = 0x14 , ///< Device Management Model Functional Descriptor
+ CDC_FUNC_DESC_OBEX = 0x15 , ///< OBEX Functional Descriptor
+ CDC_FUNC_DESC_COMMAND_SET = 0x16 , ///< Command Set Functional Descriptor
+ CDC_FUNC_DESC_COMMAND_SET_DETAIL = 0x17 , ///< Command Set Detail Functional Descriptor
+ CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL = 0x18 , ///< Telephone Control Model Functional Descriptor
+ CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER = 0x19 , ///< OBEX Service Identifier Functional Descriptor
+ CDC_FUNC_DESC_NCM = 0x1A , ///< NCM Functional Descriptor
+}cdc_func_desc_type_t;
+
+//--------------------------------------------------------------------+
+// CDC Data Interface Class
+//--------------------------------------------------------------------+
+
+// SUBCLASS code of Data Interface is not used and should/must be zero
+
+// Data Interface Protocol Codes
+typedef enum{
+ CDC_DATA_PROTOCOL_ISDN_BRI = 0x30, ///< Physical interface protocol for ISDN BRI
+ CDC_DATA_PROTOCOL_HDLC = 0x31, ///< HDLC
+ CDC_DATA_PROTOCOL_TRANSPARENT = 0x32, ///< Transparent
+ CDC_DATA_PROTOCOL_Q921_MANAGEMENT = 0x50, ///< Management protocol for Q.921 data link protocol
+ CDC_DATA_PROTOCOL_Q921_DATA_LINK = 0x51, ///< Data link protocol for Q.931
+ CDC_DATA_PROTOCOL_Q921_TEI_MULTIPLEXOR = 0x52, ///< TEI-multiplexor for Q.921 data link protocol
+ CDC_DATA_PROTOCOL_V42BIS_DATA_COMPRESSION = 0x90, ///< Data compression procedures
+ CDC_DATA_PROTOCOL_EURO_ISDN = 0x91, ///< Euro-ISDN protocol control
+ CDC_DATA_PROTOCOL_V24_RATE_ADAPTION_TO_ISDN = 0x92, ///< V.24 rate adaptation to ISDN
+ CDC_DATA_PROTOCOL_CAPI_COMMAND = 0x93, ///< CAPI Commands
+ CDC_DATA_PROTOCOL_HOST_BASED_DRIVER = 0xFD, ///< Host based driver. Note: This protocol code should only be used in messages between host and device to identify the host driver portion of a protocol stack.
+ CDC_DATA_PROTOCOL_IN_PROTOCOL_UNIT_FUNCTIONAL_DESCRIPTOR = 0xFE ///< The protocol(s) are described using a ProtocolUnit Functional Descriptors on Communications Class Interface
+}cdc_data_protocol_type_t;
+
+//--------------------------------------------------------------------+
+// Management Element Request (Control Endpoint)
+//--------------------------------------------------------------------+
+
+/// Communication Interface Management Element Request Codes
+typedef enum
+{
+ CDC_REQUEST_SEND_ENCAPSULATED_COMMAND = 0x00, ///< is used to issue a command in the format of the supported control protocol of the Communications Class interface
+ CDC_REQUEST_GET_ENCAPSULATED_RESPONSE = 0x01, ///< is used to request a response in the format of the supported control protocol of the Communications Class interface.
+ CDC_REQUEST_SET_COMM_FEATURE = 0x02,
+ CDC_REQUEST_GET_COMM_FEATURE = 0x03,
+ CDC_REQUEST_CLEAR_COMM_FEATURE = 0x04,
+
+ CDC_REQUEST_SET_AUX_LINE_STATE = 0x10,
+ CDC_REQUEST_SET_HOOK_STATE = 0x11,
+ CDC_REQUEST_PULSE_SETUP = 0x12,
+ CDC_REQUEST_SEND_PULSE = 0x13,
+ CDC_REQUEST_SET_PULSE_TIME = 0x14,
+ CDC_REQUEST_RING_AUX_JACK = 0x15,
+
+ CDC_REQUEST_SET_LINE_CODING = 0x20,
+ CDC_REQUEST_GET_LINE_CODING = 0x21,
+ CDC_REQUEST_SET_CONTROL_LINE_STATE = 0x22,
+ CDC_REQUEST_SEND_BREAK = 0x23,
+
+ CDC_REQUEST_SET_RINGER_PARMS = 0x30,
+ CDC_REQUEST_GET_RINGER_PARMS = 0x31,
+ CDC_REQUEST_SET_OPERATION_PARMS = 0x32,
+ CDC_REQUEST_GET_OPERATION_PARMS = 0x33,
+ CDC_REQUEST_SET_LINE_PARMS = 0x34,
+ CDC_REQUEST_GET_LINE_PARMS = 0x35,
+ CDC_REQUEST_DIAL_DIGITS = 0x36,
+ CDC_REQUEST_SET_UNIT_PARAMETER = 0x37,
+ CDC_REQUEST_GET_UNIT_PARAMETER = 0x38,
+ CDC_REQUEST_CLEAR_UNIT_PARAMETER = 0x39,
+ CDC_REQUEST_GET_PROFILE = 0x3A,
+
+ CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS = 0x40,
+ CDC_REQUEST_SET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x41,
+ CDC_REQUEST_GET_ETHERNET_POWER_MANAGEMENT_PATTERN_FILTER = 0x42,
+ CDC_REQUEST_SET_ETHERNET_PACKET_FILTER = 0x43,
+ CDC_REQUEST_GET_ETHERNET_STATISTIC = 0x44,
+
+ CDC_REQUEST_SET_ATM_DATA_FORMAT = 0x50,
+ CDC_REQUEST_GET_ATM_DEVICE_STATISTICS = 0x51,
+ CDC_REQUEST_SET_ATM_DEFAULT_VC = 0x52,
+ CDC_REQUEST_GET_ATM_VC_STATISTICS = 0x53,
+
+ CDC_REQUEST_MDLM_SEMANTIC_MODEL = 0x60,
+}cdc_management_request_t;
+
+//--------------------------------------------------------------------+
+// Management Elemenent Notification (Notification Endpoint)
+//--------------------------------------------------------------------+
+
+/// 6.3 Notification Codes
+typedef enum
+{
+ CDC_NOTIF_NETWORK_CONNECTION = 0x00, ///< This notification allows the device to notify the host about network connection status.
+ CDC_NOTIF_RESPONSE_AVAILABLE = 0x01, ///< This notification allows the device to notify the hostthat a response is available. This response can be retrieved with a subsequent \ref CDC_REQUEST_GET_ENCAPSULATED_RESPONSE request.
+ CDC_NOTIF_AUX_JACK_HOOK_STATE = 0x08,
+ CDC_NOTIF_RING_DETECT = 0x09,
+ CDC_NOTIF_SERIAL_STATE = 0x20,
+ CDC_NOTIF_CALL_STATE_CHANGE = 0x28,
+ CDC_NOTIF_LINE_STATE_CHANGE = 0x29,
+ CDC_NOTIF_CONNECTION_SPEED_CHANGE = 0x2A, ///< This notification allows the device to inform the host-networking driver that a change in either the upstream or the downstream bit rate of the connection has occurred
+ CDC_NOTIF_MDLM_SEMANTIC_MODEL_NOTIFICATION = 0x40,
+}cdc_notification_request_t;
+
+//--------------------------------------------------------------------+
+// Class Specific Functional Descriptor (Communication Interface)
+//--------------------------------------------------------------------+
+
+// Start of all packed definitions for compiler without per-type packed
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+/// Header Functional Descriptor (Communication Interface)
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUNC_DESC_
+ uint16_t bcdCDC ; ///< CDC release number in Binary-Coded Decimal
+}cdc_desc_func_header_t;
+
+/// Union Functional Descriptor (Communication Interface)
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+ uint8_t bControlInterface ; ///< Interface number of Communication Interface
+ uint8_t bSubordinateInterface ; ///< Array of Interface number of Data Interface
+}cdc_desc_func_union_t;
+
+#define cdc_desc_func_union_n_t(no_slave)\
+ struct TU_ATTR_PACKED { \
+ uint8_t bLength ;\
+ uint8_t bDescriptorType ;\
+ uint8_t bDescriptorSubType ;\
+ uint8_t bControlInterface ;\
+ uint8_t bSubordinateInterface[no_slave] ;\
+}
+
+/// Country Selection Functional Descriptor (Communication Interface)
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+ uint8_t iCountryCodeRelDate ; ///< Index of a string giving the release date for the implemented ISO 3166 Country Codes.
+ uint16_t wCountryCode ; ///< Country code in the format as defined in [ISO3166], release date as specified inoffset 3 for the first supported country.
+}cdc_desc_func_country_selection_t;
+
+#define cdc_desc_func_country_selection_n_t(no_country) \
+ struct TU_ATTR_PACKED { \
+ uint8_t bLength ;\
+ uint8_t bDescriptorType ;\
+ uint8_t bDescriptorSubType ;\
+ uint8_t iCountryCodeRelDate ;\
+ uint16_t wCountryCode[no_country] ;\
+}
+
+//--------------------------------------------------------------------+
+// PUBLIC SWITCHED TELEPHONE NETWORK (PSTN) SUBCLASS
+//--------------------------------------------------------------------+
+
+/// \brief Call Management Functional Descriptor
+/// \details This functional descriptor describes the processing of calls for the Communications Class interface.
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+
+ struct {
+ uint8_t handle_call : 1; ///< 0 - Device sends/receives call management information only over the Communications Class interface. 1 - Device can send/receive call management information over a Data Class interface.
+ uint8_t send_recv_call : 1; ///< 0 - Device does not handle call management itself. 1 - Device handles call management itself.
+ uint8_t TU_RESERVED : 6;
+ } bmCapabilities;
+
+ uint8_t bDataInterface;
+}cdc_desc_func_call_management_t;
+
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t support_comm_request : 1; ///< Device supports the request combination of Set_Comm_Feature, Clear_Comm_Feature, and Get_Comm_Feature.
+ uint8_t support_line_request : 1; ///< Device supports the request combination of Set_Line_Coding, Set_Control_Line_State, Get_Line_Coding, and the notification Serial_State.
+ uint8_t support_send_break : 1; ///< Device supports the request Send_Break
+ uint8_t support_notification_network_connection : 1; ///< Device supports the notification Network_Connection.
+ uint8_t TU_RESERVED : 4;
+}cdc_acm_capability_t;
+
+TU_VERIFY_STATIC(sizeof(cdc_acm_capability_t) == 1, "mostly problem with compiler");
+
+/// Abstract Control Management Functional Descriptor
+/// This functional descriptor describes the commands supported by by the Communications Class interface with SubClass code of \ref CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+ cdc_acm_capability_t bmCapabilities ;
+}cdc_desc_func_acm_t;
+
+/// \brief Direct Line Management Functional Descriptor
+/// \details This functional descriptor describes the commands supported by the Communications Class interface with SubClass code of \ref CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+ struct {
+ uint8_t require_pulse_setup : 1; ///< Device requires extra Pulse_Setup request during pulse dialing sequence to disengage holding circuit.
+ uint8_t support_aux_request : 1; ///< Device supports the request combination of Set_Aux_Line_State, Ring_Aux_Jack, and notification Aux_Jack_Hook_State.
+ uint8_t support_pulse_request : 1; ///< Device supports the request combination of Pulse_Setup, Send_Pulse, and Set_Pulse_Time.
+ uint8_t TU_RESERVED : 5;
+ } bmCapabilities;
+}cdc_desc_func_direct_line_management_t;
+
+/// \brief Telephone Ringer Functional Descriptor
+/// \details The Telephone Ringer functional descriptor describes the ringer capabilities supported by the Communications Class interface,
+/// with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+ uint8_t bRingerVolSteps ;
+ uint8_t bNumRingerPatterns ;
+}cdc_desc_func_telephone_ringer_t;
+
+/// \brief Telephone Operational Modes Functional Descriptor
+/// \details The Telephone Operational Modes functional descriptor describes the operational modes supported by
+/// the Communications Class interface, with the SubClass code of \ref CDC_COMM_SUBCLASS_TELEPHONE_CONTROL_MODEL
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+ struct {
+ uint8_t simple_mode : 1;
+ uint8_t standalone_mode : 1;
+ uint8_t computer_centric_mode : 1;
+ uint8_t TU_RESERVED : 5;
+ } bmCapabilities;
+}cdc_desc_func_telephone_operational_modes_t;
+
+/// \brief Telephone Call and Line State Reporting Capabilities Descriptor
+/// \details The Telephone Call and Line State Reporting Capabilities functional descriptor describes the abilities of a
+/// telephone device to report optional call and line states.
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< Descriptor Type, must be Class-Specific
+ uint8_t bDescriptorSubType ; ///< Descriptor SubType one of above CDC_FUCN_DESC_
+ struct {
+ uint32_t interrupted_dialtone : 1; ///< 0 : Reports only dialtone (does not differentiate between normal and interrupted dialtone). 1 : Reports interrupted dialtone in addition to normal dialtone
+ uint32_t ringback_busy_fastbusy : 1; ///< 0 : Reports only dialing state. 1 : Reports ringback, busy, and fast busy states.
+ uint32_t caller_id : 1; ///< 0 : Does not report caller ID. 1 : Reports caller ID information.
+ uint32_t incoming_distinctive : 1; ///< 0 : Reports only incoming ringing. 1 : Reports incoming distinctive ringing patterns.
+ uint32_t dual_tone_multi_freq : 1; ///< 0 : Cannot report dual tone multi-frequency (DTMF) digits input remotely over the telephone line. 1 : Can report DTMF digits input remotely over the telephone line.
+ uint32_t line_state_change : 1; ///< 0 : Does not support line state change notification. 1 : Does support line state change notification
+ uint32_t TU_RESERVED : 26;
+ } bmCapabilities;
+}cdc_desc_func_telephone_call_state_reporting_capabilities_t;
+
+// TODO remove
+static inline uint8_t cdc_functional_desc_typeof(uint8_t const * p_desc)
+{
+ return p_desc[2];
+}
+
+//--------------------------------------------------------------------+
+// Requests
+//--------------------------------------------------------------------+
+typedef struct TU_ATTR_PACKED
+{
+ uint32_t bit_rate;
+ uint8_t stop_bits; ///< 0: 1 stop bit - 1: 1.5 stop bits - 2: 2 stop bits
+ uint8_t parity; ///< 0: None - 1: Odd - 2: Even - 3: Mark - 4: Space
+ uint8_t data_bits; ///< can be 5, 6, 7, 8 or 16
+} cdc_line_coding_t;
+
+TU_VERIFY_STATIC(sizeof(cdc_line_coding_t) == 7, "size is not correct");
+
+typedef struct TU_ATTR_PACKED
+{
+ uint16_t dte_is_present : 1; ///< Indicates to DCE if DTE is presentor not. This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR.
+ uint16_t half_duplex_carrier_control : 1;
+ uint16_t : 14;
+} cdc_line_control_state_t;
+
+TU_VERIFY_STATIC(sizeof(cdc_line_control_state_t) == 2, "size is not correct");
+
+TU_ATTR_PACKED_END // End of all packed definitions
+TU_ATTR_BIT_FIELD_ORDER_END
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/cdc/cdc_device.c b/arkanoid/pico/tinyusb/cdc/cdc_device.c
new file mode 100644
index 0000000..a67dc2b
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc_device.c
@@ -0,0 +1,484 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../tusb_option.h"
+
+#if (TUSB_OPT_DEVICE_ENABLED && CFG_TUD_CDC)
+
+#include "../usbd.h"
+#include "../usbd_pvt.h"
+
+#include "cdc_device.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+enum
+{
+ BULK_PACKET_SIZE = (TUD_OPT_HIGH_SPEED ? 512 : 64)
+};
+
+typedef struct
+{
+ uint8_t itf_num;
+ uint8_t ep_notif;
+ uint8_t ep_in;
+ uint8_t ep_out;
+
+ // Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
+ uint8_t line_state;
+
+ /*------------- From this point, data is not cleared by bus reset -------------*/
+ char wanted_char;
+ cdc_line_coding_t line_coding;
+
+ // FIFO
+ tu_fifo_t rx_ff;
+ tu_fifo_t tx_ff;
+
+ uint8_t rx_ff_buf[CFG_TUD_CDC_RX_BUFSIZE];
+ uint8_t tx_ff_buf[CFG_TUD_CDC_TX_BUFSIZE];
+
+#if CFG_FIFO_MUTEX
+ osal_mutex_def_t rx_ff_mutex;
+ osal_mutex_def_t tx_ff_mutex;
+#endif
+
+ // Endpoint Transfer buffer
+ CFG_TUSB_MEM_ALIGN uint8_t epout_buf[CFG_TUD_CDC_EP_BUFSIZE];
+ CFG_TUSB_MEM_ALIGN uint8_t epin_buf[CFG_TUD_CDC_EP_BUFSIZE];
+
+}cdcd_interface_t;
+
+#define ITF_MEM_RESET_SIZE offsetof(cdcd_interface_t, wanted_char)
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+CFG_TUSB_MEM_SECTION static cdcd_interface_t _cdcd_itf[CFG_TUD_CDC];
+
+static void _prep_out_transaction (cdcd_interface_t* p_cdc)
+{
+ uint8_t const rhport = TUD_OPT_RHPORT;
+ uint16_t available = tu_fifo_remaining(&p_cdc->rx_ff);
+
+ // Prepare for incoming data but only allow what we can store in the ring buffer.
+ // TODO Actually we can still carry out the transfer, keeping count of received bytes
+ // and slowly move it to the FIFO when read().
+ // This pre-check reduces endpoint claiming
+ TU_VERIFY(available >= sizeof(p_cdc->epout_buf), );
+
+ // claim endpoint
+ TU_VERIFY(usbd_edpt_claim(rhport, p_cdc->ep_out), );
+
+ // fifo can be changed before endpoint is claimed
+ available = tu_fifo_remaining(&p_cdc->rx_ff);
+
+ if ( available >= sizeof(p_cdc->epout_buf) )
+ {
+ usbd_edpt_xfer(rhport, p_cdc->ep_out, p_cdc->epout_buf, sizeof(p_cdc->epout_buf));
+ }else
+ {
+ // Release endpoint since we don't make any transfer
+ usbd_edpt_release(rhport, p_cdc->ep_out);
+ }
+}
+
+//--------------------------------------------------------------------+
+// APPLICATION API
+//--------------------------------------------------------------------+
+bool tud_cdc_n_connected(uint8_t itf)
+{
+ // DTR (bit 0) active is considered as connected
+ return tud_ready() && tu_bit_test(_cdcd_itf[itf].line_state, 0);
+}
+
+uint8_t tud_cdc_n_get_line_state (uint8_t itf)
+{
+ return _cdcd_itf[itf].line_state;
+}
+
+void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding)
+{
+ (*coding) = _cdcd_itf[itf].line_coding;
+}
+
+void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted)
+{
+ _cdcd_itf[itf].wanted_char = wanted;
+}
+
+
+//--------------------------------------------------------------------+
+// READ API
+//--------------------------------------------------------------------+
+uint32_t tud_cdc_n_available(uint8_t itf)
+{
+ return tu_fifo_count(&_cdcd_itf[itf].rx_ff);
+}
+
+uint32_t tud_cdc_n_read(uint8_t itf, void* buffer, uint32_t bufsize)
+{
+ cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
+ uint32_t num_read = tu_fifo_read_n(&p_cdc->rx_ff, buffer, bufsize);
+ _prep_out_transaction(p_cdc);
+ return num_read;
+}
+
+bool tud_cdc_n_peek(uint8_t itf, uint8_t* chr)
+{
+ return tu_fifo_peek(&_cdcd_itf[itf].rx_ff, chr);
+}
+
+void tud_cdc_n_read_flush (uint8_t itf)
+{
+ cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
+ tu_fifo_clear(&p_cdc->rx_ff);
+ _prep_out_transaction(p_cdc);
+}
+
+//--------------------------------------------------------------------+
+// WRITE API
+//--------------------------------------------------------------------+
+uint32_t tud_cdc_n_write(uint8_t itf, void const* buffer, uint32_t bufsize)
+{
+ cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
+ uint16_t ret = tu_fifo_write_n(&p_cdc->tx_ff, buffer, bufsize);
+
+ // flush if queue more than packet size
+ if ( tu_fifo_count(&p_cdc->tx_ff) >= BULK_PACKET_SIZE )
+ {
+ tud_cdc_n_write_flush(itf);
+ }
+
+ return ret;
+}
+
+uint32_t tud_cdc_n_write_flush (uint8_t itf)
+{
+ cdcd_interface_t* p_cdc = &_cdcd_itf[itf];
+
+ // Skip if usb is not ready yet
+ TU_VERIFY( tud_ready(), 0 );
+
+ // No data to send
+ if ( !tu_fifo_count(&p_cdc->tx_ff) ) return 0;
+
+ uint8_t const rhport = TUD_OPT_RHPORT;
+
+ // Claim the endpoint
+ TU_VERIFY( usbd_edpt_claim(rhport, p_cdc->ep_in), 0 );
+
+ // Pull data from FIFO
+ uint16_t const count = tu_fifo_read_n(&p_cdc->tx_ff, p_cdc->epin_buf, sizeof(p_cdc->epin_buf));
+
+ if ( count )
+ {
+ TU_ASSERT( usbd_edpt_xfer(rhport, p_cdc->ep_in, p_cdc->epin_buf, count), 0 );
+ return count;
+ }else
+ {
+ // Release endpoint since we don't make any transfer
+ // Note: data is dropped if terminal is not connected
+ usbd_edpt_release(rhport, p_cdc->ep_in);
+ return 0;
+ }
+}
+
+uint32_t tud_cdc_n_write_available (uint8_t itf)
+{
+ return tu_fifo_remaining(&_cdcd_itf[itf].tx_ff);
+}
+
+bool tud_cdc_n_write_clear (uint8_t itf)
+{
+ return tu_fifo_clear(&_cdcd_itf[itf].tx_ff);
+}
+
+//--------------------------------------------------------------------+
+// USBD Driver API
+//--------------------------------------------------------------------+
+void cdcd_init(void)
+{
+ tu_memclr(_cdcd_itf, sizeof(_cdcd_itf));
+
+ for(uint8_t i=0; i<CFG_TUD_CDC; i++)
+ {
+ cdcd_interface_t* p_cdc = &_cdcd_itf[i];
+
+ p_cdc->wanted_char = -1;
+
+ // default line coding is : stop bit = 1, parity = none, data bits = 8
+ p_cdc->line_coding.bit_rate = 115200;
+ p_cdc->line_coding.stop_bits = 0;
+ p_cdc->line_coding.parity = 0;
+ p_cdc->line_coding.data_bits = 8;
+
+ // Config RX fifo
+ tu_fifo_config(&p_cdc->rx_ff, p_cdc->rx_ff_buf, TU_ARRAY_SIZE(p_cdc->rx_ff_buf), 1, false);
+
+ // Config TX fifo as overwritable at initialization and will be changed to non-overwritable
+ // if terminal supports DTR bit. Without DTR we do not know if data is actually polled by terminal.
+ // In this way, the most current data is prioritized.
+ tu_fifo_config(&p_cdc->tx_ff, p_cdc->tx_ff_buf, TU_ARRAY_SIZE(p_cdc->tx_ff_buf), 1, true);
+
+#if CFG_FIFO_MUTEX
+ tu_fifo_config_mutex(&p_cdc->rx_ff, NULL, osal_mutex_create(&p_cdc->rx_ff_mutex));
+ tu_fifo_config_mutex(&p_cdc->tx_ff, osal_mutex_create(&p_cdc->tx_ff_mutex), NULL);
+#endif
+ }
+}
+
+void cdcd_reset(uint8_t rhport)
+{
+ (void) rhport;
+
+ for(uint8_t i=0; i<CFG_TUD_CDC; i++)
+ {
+ cdcd_interface_t* p_cdc = &_cdcd_itf[i];
+
+ tu_memclr(p_cdc, ITF_MEM_RESET_SIZE);
+ tu_fifo_clear(&p_cdc->rx_ff);
+ tu_fifo_clear(&p_cdc->tx_ff);
+ tu_fifo_set_overwritable(&p_cdc->tx_ff, true);
+ }
+}
+
+uint16_t cdcd_open(uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len)
+{
+ // Only support ACM subclass
+ TU_VERIFY( TUSB_CLASS_CDC == itf_desc->bInterfaceClass &&
+ CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass, 0);
+
+ // Find available interface
+ cdcd_interface_t * p_cdc = NULL;
+ for(uint8_t cdc_id=0; cdc_id<CFG_TUD_CDC; cdc_id++)
+ {
+ if ( _cdcd_itf[cdc_id].ep_in == 0 )
+ {
+ p_cdc = &_cdcd_itf[cdc_id];
+ break;
+ }
+ }
+ TU_ASSERT(p_cdc, 0);
+
+ //------------- Control Interface -------------//
+ p_cdc->itf_num = itf_desc->bInterfaceNumber;
+
+ uint16_t drv_len = sizeof(tusb_desc_interface_t);
+ uint8_t const * p_desc = tu_desc_next( itf_desc );
+
+ // Communication Functional Descriptors
+ while ( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
+ {
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+ }
+
+ if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
+ {
+ // notification endpoint
+ tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+
+ TU_ASSERT( usbd_edpt_open(rhport, desc_ep), 0 );
+ p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+ }
+
+ //------------- Data Interface (if any) -------------//
+ if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+ (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
+ {
+ // next to endpoint descriptor
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+
+ // Open endpoint pair
+ TU_ASSERT( usbd_open_edpt_pair(rhport, p_desc, 2, TUSB_XFER_BULK, &p_cdc->ep_out, &p_cdc->ep_in), 0 );
+
+ drv_len += 2*sizeof(tusb_desc_endpoint_t);
+ }
+
+ // Prepare for incoming data
+ _prep_out_transaction(p_cdc);
+
+ return drv_len;
+}
+
+// Invoked when a control transfer occurred on an interface of this class
+// Driver response accordingly to the request and the transfer stage (setup/data/ack)
+// return false to stall control endpoint (e.g unsupported request)
+bool cdcd_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request)
+{
+ // Handle class request only
+ TU_VERIFY(request->bmRequestType_bit.type == TUSB_REQ_TYPE_CLASS);
+
+ uint8_t itf = 0;
+ cdcd_interface_t* p_cdc = _cdcd_itf;
+
+ // Identify which interface to use
+ for ( ; ; itf++, p_cdc++)
+ {
+ if (itf >= TU_ARRAY_SIZE(_cdcd_itf)) return false;
+
+ if ( p_cdc->itf_num == request->wIndex ) break;
+ }
+
+ switch ( request->bRequest )
+ {
+ case CDC_REQUEST_SET_LINE_CODING:
+ if (stage == CONTROL_STAGE_SETUP)
+ {
+ TU_LOG2(" Set Line Coding\r\n");
+ tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
+ }
+ else if ( stage == CONTROL_STAGE_ACK)
+ {
+ if ( tud_cdc_line_coding_cb ) tud_cdc_line_coding_cb(itf, &p_cdc->line_coding);
+ }
+ break;
+
+ case CDC_REQUEST_GET_LINE_CODING:
+ if (stage == CONTROL_STAGE_SETUP)
+ {
+ TU_LOG2(" Get Line Coding\r\n");
+ tud_control_xfer(rhport, request, &p_cdc->line_coding, sizeof(cdc_line_coding_t));
+ }
+ break;
+
+ case CDC_REQUEST_SET_CONTROL_LINE_STATE:
+ if (stage == CONTROL_STAGE_SETUP)
+ {
+ tud_control_status(rhport, request);
+ }
+ else if (stage == CONTROL_STAGE_ACK)
+ {
+ // CDC PSTN v1.2 section 6.3.12
+ // Bit 0: Indicates if DTE is present or not.
+ // This signal corresponds to V.24 signal 108/2 and RS-232 signal DTR (Data Terminal Ready)
+ // Bit 1: Carrier control for half-duplex modems.
+ // This signal corresponds to V.24 signal 105 and RS-232 signal RTS (Request to Send)
+ bool const dtr = tu_bit_test(request->wValue, 0);
+ bool const rts = tu_bit_test(request->wValue, 1);
+
+ p_cdc->line_state = (uint8_t) request->wValue;
+
+ // Disable fifo overwriting if DTR bit is set
+ tu_fifo_set_overwritable(&p_cdc->tx_ff, !dtr);
+
+ TU_LOG2(" Set Control Line State: DTR = %d, RTS = %d\r\n", dtr, rts);
+
+ // Invoke callback
+ if ( tud_cdc_line_state_cb ) tud_cdc_line_state_cb(itf, dtr, rts);
+ }
+ break;
+ case CDC_REQUEST_SEND_BREAK:
+ if (stage == CONTROL_STAGE_SETUP)
+ {
+ tud_control_status(rhport, request);
+ }
+ else if (stage == CONTROL_STAGE_ACK)
+ {
+ TU_LOG2(" Send Break\r\n");
+ if ( tud_cdc_send_break_cb ) tud_cdc_send_break_cb(itf, request->wValue);
+ }
+ break;
+
+ default: return false; // stall unsupported request
+ }
+
+ return true;
+}
+
+bool cdcd_xfer_cb(uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+ (void) result;
+
+ uint8_t itf;
+ cdcd_interface_t* p_cdc;
+
+ // Identify which interface to use
+ for (itf = 0; itf < CFG_TUD_CDC; itf++)
+ {
+ p_cdc = &_cdcd_itf[itf];
+ if ( ( ep_addr == p_cdc->ep_out ) || ( ep_addr == p_cdc->ep_in ) ) break;
+ }
+ TU_ASSERT(itf < CFG_TUD_CDC);
+
+ // Received new data
+ if ( ep_addr == p_cdc->ep_out )
+ {
+ tu_fifo_write_n(&p_cdc->rx_ff, &p_cdc->epout_buf, xferred_bytes);
+
+ // Check for wanted char and invoke callback if needed
+ if ( tud_cdc_rx_wanted_cb && (((signed char) p_cdc->wanted_char) != -1) )
+ {
+ for ( uint32_t i = 0; i < xferred_bytes; i++ )
+ {
+ if ( (p_cdc->wanted_char == p_cdc->epout_buf[i]) && !tu_fifo_empty(&p_cdc->rx_ff) )
+ {
+ tud_cdc_rx_wanted_cb(itf, p_cdc->wanted_char);
+ }
+ }
+ }
+
+ // invoke receive callback (if there is still data)
+ if (tud_cdc_rx_cb && !tu_fifo_empty(&p_cdc->rx_ff) ) tud_cdc_rx_cb(itf);
+
+ // prepare for OUT transaction
+ _prep_out_transaction(p_cdc);
+ }
+
+ // Data sent to host, we continue to fetch from tx fifo to send.
+ // Note: This will cause incorrect baudrate set in line coding.
+ // Though maybe the baudrate is not really important !!!
+ if ( ep_addr == p_cdc->ep_in )
+ {
+ // invoke transmit callback to possibly refill tx fifo
+ if ( tud_cdc_tx_complete_cb ) tud_cdc_tx_complete_cb(itf);
+
+ if ( 0 == tud_cdc_n_write_flush(itf) )
+ {
+ // If there is no data left, a ZLP should be sent if
+ // xferred_bytes is multiple of EP Packet size and not zero
+ if ( !tu_fifo_count(&p_cdc->tx_ff) && xferred_bytes && (0 == (xferred_bytes & (BULK_PACKET_SIZE-1))) )
+ {
+ if ( usbd_edpt_claim(rhport, p_cdc->ep_in) )
+ {
+ usbd_edpt_xfer(rhport, p_cdc->ep_in, NULL, 0);
+ }
+ }
+ }
+ }
+
+ // nothing to do with notif endpoint for now
+
+ return true;
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/cdc/cdc_device.h b/arkanoid/pico/tinyusb/cdc/cdc_device.h
new file mode 100644
index 0000000..b729b0d
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc_device.h
@@ -0,0 +1,260 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_CDC_DEVICE_H_
+#define _TUSB_CDC_DEVICE_H_
+
+#include "../tusb_common.h"
+#include "cdc.h"
+
+//--------------------------------------------------------------------+
+// Class Driver Configuration
+//--------------------------------------------------------------------+
+#if !defined(CFG_TUD_CDC_EP_BUFSIZE) && defined(CFG_TUD_CDC_EPSIZE)
+ #warning CFG_TUD_CDC_EPSIZE is renamed to CFG_TUD_CDC_EP_BUFSIZE, please update to use the new name
+ #define CFG_TUD_CDC_EP_BUFSIZE CFG_TUD_CDC_EPSIZE
+#endif
+
+#ifndef CFG_TUD_CDC_EP_BUFSIZE
+ #define CFG_TUD_CDC_EP_BUFSIZE (TUD_OPT_HIGH_SPEED ? 512 : 64)
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \addtogroup CDC_Serial Serial
+ * @{
+ * \defgroup CDC_Serial_Device Device
+ * @{ */
+
+//--------------------------------------------------------------------+
+// Application API (Multiple Ports)
+// CFG_TUD_CDC > 1
+//--------------------------------------------------------------------+
+
+// Check if terminal is connected to this port
+bool tud_cdc_n_connected (uint8_t itf);
+
+// Get current line state. Bit 0: DTR (Data Terminal Ready), Bit 1: RTS (Request to Send)
+uint8_t tud_cdc_n_get_line_state (uint8_t itf);
+
+// Get current line encoding: bit rate, stop bits parity etc ..
+void tud_cdc_n_get_line_coding (uint8_t itf, cdc_line_coding_t* coding);
+
+// Set special character that will trigger tud_cdc_rx_wanted_cb() callback on receiving
+void tud_cdc_n_set_wanted_char (uint8_t itf, char wanted);
+
+// Get the number of bytes available for reading
+uint32_t tud_cdc_n_available (uint8_t itf);
+
+// Read received bytes
+uint32_t tud_cdc_n_read (uint8_t itf, void* buffer, uint32_t bufsize);
+
+// Read a byte, return -1 if there is none
+static inline
+int32_t tud_cdc_n_read_char (uint8_t itf);
+
+// Clear the received FIFO
+void tud_cdc_n_read_flush (uint8_t itf);
+
+// Get a byte from FIFO at the specified position without removing it
+bool tud_cdc_n_peek (uint8_t itf, uint8_t* ui8);
+
+// Write bytes to TX FIFO, data may remain in the FIFO for a while
+uint32_t tud_cdc_n_write (uint8_t itf, void const* buffer, uint32_t bufsize);
+
+// Write a byte
+static inline
+uint32_t tud_cdc_n_write_char (uint8_t itf, char ch);
+
+// Write a null-terminated string
+static inline
+uint32_t tud_cdc_n_write_str (uint8_t itf, char const* str);
+
+// Force sending data if possible, return number of forced bytes
+uint32_t tud_cdc_n_write_flush (uint8_t itf);
+
+// Return the number of bytes (characters) available for writing to TX FIFO buffer in a single n_write operation.
+uint32_t tud_cdc_n_write_available (uint8_t itf);
+
+// Clear the transmit FIFO
+bool tud_cdc_n_write_clear (uint8_t itf);
+
+//--------------------------------------------------------------------+
+// Application API (Single Port)
+//--------------------------------------------------------------------+
+static inline bool tud_cdc_connected (void);
+static inline uint8_t tud_cdc_get_line_state (void);
+static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding);
+static inline void tud_cdc_set_wanted_char (char wanted);
+
+static inline uint32_t tud_cdc_available (void);
+static inline int32_t tud_cdc_read_char (void);
+static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize);
+static inline void tud_cdc_read_flush (void);
+static inline bool tud_cdc_peek (uint8_t* ui8);
+
+static inline uint32_t tud_cdc_write_char (char ch);
+static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize);
+static inline uint32_t tud_cdc_write_str (char const* str);
+static inline uint32_t tud_cdc_write_flush (void);
+static inline uint32_t tud_cdc_write_available (void);
+static inline bool tud_cdc_write_clear (void);
+
+//--------------------------------------------------------------------+
+// Application Callback API (weak is optional)
+//--------------------------------------------------------------------+
+
+// Invoked when received new data
+TU_ATTR_WEAK void tud_cdc_rx_cb(uint8_t itf);
+
+// Invoked when received `wanted_char`
+TU_ATTR_WEAK void tud_cdc_rx_wanted_cb(uint8_t itf, char wanted_char);
+
+// Invoked when space becomes available in TX buffer
+TU_ATTR_WEAK void tud_cdc_tx_complete_cb(uint8_t itf);
+
+// Invoked when line state DTR & RTS are changed via SET_CONTROL_LINE_STATE
+TU_ATTR_WEAK void tud_cdc_line_state_cb(uint8_t itf, bool dtr, bool rts);
+
+// Invoked when line coding is change via SET_LINE_CODING
+TU_ATTR_WEAK void tud_cdc_line_coding_cb(uint8_t itf, cdc_line_coding_t const* p_line_coding);
+
+// Invoked when received send break
+TU_ATTR_WEAK void tud_cdc_send_break_cb(uint8_t itf, uint16_t duration_ms);
+
+//--------------------------------------------------------------------+
+// Inline Functions
+//--------------------------------------------------------------------+
+static inline int32_t tud_cdc_n_read_char (uint8_t itf)
+{
+ uint8_t ch;
+ return tud_cdc_n_read(itf, &ch, 1) ? (int32_t) ch : -1;
+}
+
+static inline uint32_t tud_cdc_n_write_char(uint8_t itf, char ch)
+{
+ return tud_cdc_n_write(itf, &ch, 1);
+}
+
+static inline uint32_t tud_cdc_n_write_str (uint8_t itf, char const* str)
+{
+ return tud_cdc_n_write(itf, str, strlen(str));
+}
+
+static inline bool tud_cdc_connected (void)
+{
+ return tud_cdc_n_connected(0);
+}
+
+static inline uint8_t tud_cdc_get_line_state (void)
+{
+ return tud_cdc_n_get_line_state(0);
+}
+
+static inline void tud_cdc_get_line_coding (cdc_line_coding_t* coding)
+{
+ tud_cdc_n_get_line_coding(0, coding);
+}
+
+static inline void tud_cdc_set_wanted_char (char wanted)
+{
+ tud_cdc_n_set_wanted_char(0, wanted);
+}
+
+static inline uint32_t tud_cdc_available (void)
+{
+ return tud_cdc_n_available(0);
+}
+
+static inline int32_t tud_cdc_read_char (void)
+{
+ return tud_cdc_n_read_char(0);
+}
+
+static inline uint32_t tud_cdc_read (void* buffer, uint32_t bufsize)
+{
+ return tud_cdc_n_read(0, buffer, bufsize);
+}
+
+static inline void tud_cdc_read_flush (void)
+{
+ tud_cdc_n_read_flush(0);
+}
+
+static inline bool tud_cdc_peek (uint8_t* ui8)
+{
+ return tud_cdc_n_peek(0, ui8);
+}
+
+static inline uint32_t tud_cdc_write_char (char ch)
+{
+ return tud_cdc_n_write_char(0, ch);
+}
+
+static inline uint32_t tud_cdc_write (void const* buffer, uint32_t bufsize)
+{
+ return tud_cdc_n_write(0, buffer, bufsize);
+}
+
+static inline uint32_t tud_cdc_write_str (char const* str)
+{
+ return tud_cdc_n_write_str(0, str);
+}
+
+static inline uint32_t tud_cdc_write_flush (void)
+{
+ return tud_cdc_n_write_flush(0);
+}
+
+static inline uint32_t tud_cdc_write_available(void)
+{
+ return tud_cdc_n_write_available(0);
+}
+
+static inline bool tud_cdc_write_clear(void)
+{
+ return tud_cdc_n_write_clear(0);
+}
+
+/** @} */
+/** @} */
+
+//--------------------------------------------------------------------+
+// INTERNAL USBD-CLASS DRIVER API
+//--------------------------------------------------------------------+
+void cdcd_init (void);
+void cdcd_reset (uint8_t rhport);
+uint16_t cdcd_open (uint8_t rhport, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
+bool cdcd_control_xfer_cb (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+bool cdcd_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CDC_DEVICE_H_ */
diff --git a/arkanoid/pico/tinyusb/cdc/cdc_host.c b/arkanoid/pico/tinyusb/cdc/cdc_host.c
new file mode 100644
index 0000000..33944e7
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc_host.c
@@ -0,0 +1,249 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../tusb_option.h"
+
+#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_CDC)
+
+#include "../host/usbh.h"
+#include "../host/usbh_classdriver.h"
+
+#include "cdc_host.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+typedef struct {
+ uint8_t itf_num;
+ uint8_t itf_protocol;
+
+ uint8_t ep_notif;
+ uint8_t ep_in;
+ uint8_t ep_out;
+
+ cdc_acm_capability_t acm_capability;
+
+} cdch_data_t;
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+static cdch_data_t cdch_data[CFG_TUH_DEVICE_MAX];
+
+static inline cdch_data_t* get_itf(uint8_t dev_addr)
+{
+ return &cdch_data[dev_addr-1];
+}
+
+bool tuh_cdc_mounted(uint8_t dev_addr)
+{
+ cdch_data_t* cdc = get_itf(dev_addr);
+ return cdc->ep_in && cdc->ep_out;
+}
+
+bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid)
+{
+ if ( !tuh_cdc_mounted(dev_addr) ) return false;
+
+ cdch_data_t const * p_cdc = get_itf(dev_addr);
+
+ switch (pipeid)
+ {
+ case CDC_PIPE_NOTIFICATION:
+ return usbh_edpt_busy(dev_addr, p_cdc->ep_notif );
+
+ case CDC_PIPE_DATA_IN:
+ return usbh_edpt_busy(dev_addr, p_cdc->ep_in );
+
+ case CDC_PIPE_DATA_OUT:
+ return usbh_edpt_busy(dev_addr, p_cdc->ep_out );
+
+ default:
+ return false;
+ }
+}
+
+//--------------------------------------------------------------------+
+// APPLICATION API (parameter validation needed)
+//--------------------------------------------------------------------+
+bool tuh_cdc_serial_is_mounted(uint8_t dev_addr)
+{
+ // TODO consider all AT Command as serial candidate
+ return tuh_cdc_mounted(dev_addr) &&
+ (cdch_data[dev_addr-1].itf_protocol <= CDC_COMM_PROTOCOL_ATCOMMAND_CDMA);
+}
+
+bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify)
+{
+ (void) is_notify;
+ TU_VERIFY( tuh_cdc_mounted(dev_addr) );
+ TU_VERIFY( p_data != NULL && length, TUSB_ERROR_INVALID_PARA);
+
+ uint8_t const ep_out = cdch_data[dev_addr-1].ep_out;
+ if ( usbh_edpt_busy(dev_addr, ep_out) ) return false;
+
+ return usbh_edpt_xfer(dev_addr, ep_out, (void *) p_data, length);
+}
+
+bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify)
+{
+ (void) is_notify;
+ TU_VERIFY( tuh_cdc_mounted(dev_addr) );
+ TU_VERIFY( p_buffer != NULL && length, TUSB_ERROR_INVALID_PARA);
+
+ uint8_t const ep_in = cdch_data[dev_addr-1].ep_in;
+ if ( usbh_edpt_busy(dev_addr, ep_in) ) return false;
+
+ return usbh_edpt_xfer(dev_addr, ep_in, p_buffer, length);
+}
+
+bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb)
+{
+ cdch_data_t const * p_cdc = get_itf(dev_addr);
+ tusb_control_request_t const request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_INTERFACE,
+ .type = TUSB_REQ_TYPE_CLASS,
+ .direction = TUSB_DIR_OUT
+ },
+ .bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE,
+ .wValue = (rts ? 2 : 0) | (dtr ? 1 : 0),
+ .wIndex = p_cdc->itf_num,
+ .wLength = 0
+ };
+
+ TU_ASSERT( tuh_control_xfer(dev_addr, &request, NULL, complete_cb) );
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// USBH-CLASS DRIVER API
+//--------------------------------------------------------------------+
+void cdch_init(void)
+{
+ tu_memclr(cdch_data, sizeof(cdch_data));
+}
+
+bool cdch_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+{
+ (void) max_len;
+
+ // Only support ACM subclass
+ // Protocol 0xFF can be RNDIS device for windows XP
+ TU_VERIFY( TUSB_CLASS_CDC == itf_desc->bInterfaceClass &&
+ CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL == itf_desc->bInterfaceSubClass &&
+ 0xFF != itf_desc->bInterfaceProtocol);
+
+ cdch_data_t * p_cdc = get_itf(dev_addr);
+
+ p_cdc->itf_num = itf_desc->bInterfaceNumber;
+ p_cdc->itf_protocol = itf_desc->bInterfaceProtocol;
+
+ //------------- Communication Interface -------------//
+ uint16_t drv_len = tu_desc_len(itf_desc);
+ uint8_t const * p_desc = tu_desc_next(itf_desc);
+
+ // Communication Functional Descriptors
+ while( TUSB_DESC_CS_INTERFACE == tu_desc_type(p_desc) && drv_len <= max_len )
+ {
+ if ( CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT == cdc_functional_desc_typeof(p_desc) )
+ {
+ // save ACM bmCapabilities
+ p_cdc->acm_capability = ((cdc_desc_func_acm_t const *) p_desc)->bmCapabilities;
+ }
+
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+ }
+
+ if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
+ {
+ // notification endpoint
+ tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+
+ TU_ASSERT( usbh_edpt_open(rhport, dev_addr, desc_ep) );
+ p_cdc->ep_notif = desc_ep->bEndpointAddress;
+
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+ }
+
+ //------------- Data Interface (if any) -------------//
+ if ( (TUSB_DESC_INTERFACE == tu_desc_type(p_desc)) &&
+ (TUSB_CLASS_CDC_DATA == ((tusb_desc_interface_t const *) p_desc)->bInterfaceClass) )
+ {
+ // next to endpoint descriptor
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+
+ // data endpoints expected to be in pairs
+ for(uint32_t i=0; i<2; i++)
+ {
+ tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+ TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && TUSB_XFER_BULK == desc_ep->bmAttributes.xfer);
+
+ TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep));
+
+ if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
+ {
+ p_cdc->ep_in = desc_ep->bEndpointAddress;
+ }else
+ {
+ p_cdc->ep_out = desc_ep->bEndpointAddress;
+ }
+
+ drv_len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next( p_desc );
+ }
+ }
+
+ return true;
+}
+
+bool cdch_set_config(uint8_t dev_addr, uint8_t itf_num)
+{
+ (void) dev_addr; (void) itf_num;
+ return true;
+}
+
+bool cdch_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes)
+{
+ (void) ep_addr;
+ tuh_cdc_xfer_isr( dev_addr, event, 0, xferred_bytes );
+ return true;
+}
+
+void cdch_close(uint8_t dev_addr)
+{
+ TU_VERIFY(dev_addr <= CFG_TUH_DEVICE_MAX, );
+
+ cdch_data_t * p_cdc = get_itf(dev_addr);
+ tu_memclr(p_cdc, sizeof(cdch_data_t));
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/cdc/cdc_host.h b/arkanoid/pico/tinyusb/cdc/cdc_host.h
new file mode 100644
index 0000000..0d43513
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc_host.h
@@ -0,0 +1,134 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_CDC_HOST_H_
+#define _TUSB_CDC_HOST_H_
+
+#include "cdc.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// CDC APPLICATION PUBLIC API
+//--------------------------------------------------------------------+
+/** \ingroup ClassDriver_CDC Communication Device Class (CDC)
+ * \addtogroup CDC_Serial Serial
+ * @{
+ * \defgroup CDC_Serial_Host Host
+ * @{ */
+
+bool tuh_cdc_set_control_line_state(uint8_t dev_addr, bool dtr, bool rts, tuh_control_complete_cb_t complete_cb);
+
+static inline bool tuh_cdc_connect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
+{
+ return tuh_cdc_set_control_line_state(dev_addr, true, true, complete_cb);
+}
+
+static inline bool tuh_cdc_disconnect(uint8_t dev_addr, tuh_control_complete_cb_t complete_cb)
+{
+ return tuh_cdc_set_control_line_state(dev_addr, false, false, complete_cb);
+}
+
+/** \brief Check if device support CDC Serial interface or not
+ * \param[in] dev_addr device address
+ * \retval true if device supports
+ * \retval false if device does not support or is not mounted
+ */
+bool tuh_cdc_serial_is_mounted(uint8_t dev_addr);
+
+/** \brief Check if the interface is currently busy or not
+ * \param[in] dev_addr device address
+ * \param[in] pipeid value from \ref cdc_pipeid_t to indicate target pipe.
+ * \retval true if the interface is busy, meaning the stack is still transferring/waiting data from/to device
+ * \retval false if the interface is not busy, meaning the stack successfully transferred data from/to device
+ * \note This function is used to check if previous transfer is complete (success or error), so that the next transfer
+ * can be scheduled. User needs to make sure the corresponding interface is mounted
+ * (by \ref tuh_cdc_serial_is_mounted) before calling this function.
+ */
+bool tuh_cdc_is_busy(uint8_t dev_addr, cdc_pipeid_t pipeid);
+
+/** \brief Perform USB OUT transfer to device
+ * \param[in] dev_addr device address
+ * \param[in] p_data Buffer containing data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION)
+ * \param[in] length Number of bytes to be transferred via USB bus
+ * \retval TUSB_ERROR_NONE on success
+ * \retval TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
+ * \retval TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
+ * \retval TUSB_ERROR_INVALID_PARA if input parameters are not correct
+ * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
+ * interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
+ */
+bool tuh_cdc_send(uint8_t dev_addr, void const * p_data, uint32_t length, bool is_notify);
+
+/** \brief Perform USB IN transfer to get data from device
+ * \param[in] dev_addr device address
+ * \param[in] p_buffer Buffer containing received data. Must be accessible by USB controller (see \ref CFG_TUSB_MEM_SECTION)
+ * \param[in] length Number of bytes to be transferred via USB bus
+ * \retval TUSB_ERROR_NONE on success
+ * \retval TUSB_ERROR_INTERFACE_IS_BUSY if the interface is already transferring data with device
+ * \retval TUSB_ERROR_DEVICE_NOT_READY if device is not yet configured (by SET CONFIGURED request)
+ * \retval TUSB_ERROR_INVALID_PARA if input parameters are not correct
+ * \note This function is non-blocking and returns immediately. The result of USB transfer will be reported by the
+ * interface's callback function. \a p_data must be declared with \ref CFG_TUSB_MEM_SECTION.
+ */
+bool tuh_cdc_receive(uint8_t dev_addr, void * p_buffer, uint32_t length, bool is_notify);
+
+//--------------------------------------------------------------------+
+// CDC APPLICATION CALLBACKS
+//--------------------------------------------------------------------+
+
+/** \brief Callback function that is invoked when an transferring event occurred
+ * \param[in] dev_addr Address of device
+ * \param[in] event an value from \ref xfer_result_t
+ * \param[in] pipe_id value from \ref cdc_pipeid_t indicate the pipe
+ * \param[in] xferred_bytes Number of bytes transferred via USB bus
+ * \note event can be one of following
+ * - XFER_RESULT_SUCCESS : previously scheduled transfer completes successfully.
+ * - XFER_RESULT_FAILED : previously scheduled transfer encountered a transaction error.
+ * - XFER_RESULT_STALLED : previously scheduled transfer is stalled by device.
+ * \note
+ */
+void tuh_cdc_xfer_isr(uint8_t dev_addr, xfer_result_t event, cdc_pipeid_t pipe_id, uint32_t xferred_bytes);
+
+/// @} // group CDC_Serial_Host
+/// @}
+
+//--------------------------------------------------------------------+
+// Internal Class Driver API
+//--------------------------------------------------------------------+
+void cdch_init (void);
+bool cdch_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+bool cdch_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool cdch_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void cdch_close (uint8_t dev_addr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CDC_HOST_H_ */
diff --git a/arkanoid/pico/tinyusb/cdc/cdc_rndis.h b/arkanoid/pico/tinyusb/cdc/cdc_rndis.h
new file mode 100644
index 0000000..e0f129f
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc_rndis.h
@@ -0,0 +1,301 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup ClassDriver_CDC Communication Device Class (CDC)
+ * \defgroup CDC_RNDIS Remote Network Driver Interface Specification (RNDIS)
+ * @{
+ * \defgroup CDC_RNDIS_Common Common Definitions
+ * @{ */
+
+#ifndef _TUSB_CDC_RNDIS_H_
+#define _TUSB_CDC_RNDIS_H_
+
+#include "cdc.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifdef __CC_ARM
+#pragma diag_suppress 66 // Suppress Keil warnings #66-D: enumeration value is out of "int" range
+#endif
+
+/// RNDIS Message Types
+typedef enum
+{
+ RNDIS_MSG_PACKET = 0x00000001UL, ///< The host and device use this to send network data to one another.
+
+ RNDIS_MSG_INITIALIZE = 0x00000002UL, ///< Sent by the host to initialize the device.
+ RNDIS_MSG_INITIALIZE_CMPLT = 0x80000002UL, ///< Device response to an initialize message.
+
+ RNDIS_MSG_HALT = 0x00000003UL, ///< Sent by the host to halt the device. This does not have a response. It is optional for the device to send this message to the host.
+
+ RNDIS_MSG_QUERY = 0x00000004UL, ///< Sent by the host to send a query OID.
+ RNDIS_MSG_QUERY_CMPLT = 0x80000004UL, ///< Device response to a query OID.
+
+ RNDIS_MSG_SET = 0x00000005UL, ///< Sent by the host to send a set OID.
+ RNDIS_MSG_SET_CMPLT = 0x80000005UL, ///< Device response to a set OID.
+
+ RNDIS_MSG_RESET = 0x00000006UL, ///< Sent by the host to perform a soft reset on the device.
+ RNDIS_MSG_RESET_CMPLT = 0x80000006UL, ///< Device response to reset message.
+
+ RNDIS_MSG_INDICATE_STATUS = 0x00000007UL, ///< Sent by the device to indicate its status or an error when an unrecognized message is received.
+
+ RNDIS_MSG_KEEP_ALIVE = 0x00000008UL, ///< During idle periods, sent every few seconds by the host to check that the device is still responsive. It is optional for the device to send this message to check if the host is active.
+ RNDIS_MSG_KEEP_ALIVE_CMPLT = 0x80000008UL ///< The device response to a keepalivemessage. The host can respond with this message to a keepalive message from the device when the device implements the optional KeepAliveTimer.
+}rndis_msg_type_t;
+
+/// RNDIS Message Status Values
+typedef enum
+{
+ RNDIS_STATUS_SUCCESS = 0x00000000UL, ///< Success
+ RNDIS_STATUS_FAILURE = 0xC0000001UL, ///< Unspecified error
+ RNDIS_STATUS_INVALID_DATA = 0xC0010015UL, ///< Invalid data error
+ RNDIS_STATUS_NOT_SUPPORTED = 0xC00000BBUL, ///< Unsupported request error
+ RNDIS_STATUS_MEDIA_CONNECT = 0x4001000BUL, ///< Device is connected to a network medium.
+ RNDIS_STATUS_MEDIA_DISCONNECT = 0x4001000CUL ///< Device is disconnected from the medium.
+}rndis_msg_status_t;
+
+#ifdef __CC_ARM
+#pragma diag_default 66 // return Keil 66 to normal severity
+#endif
+
+//--------------------------------------------------------------------+
+// MESSAGE STRUCTURE
+//--------------------------------------------------------------------+
+
+//------------- Initialize -------------//
+/// \brief Initialize Message
+/// \details This message MUST be sent by the host to initialize the device.
+typedef struct {
+ uint32_t type ; ///< Message type, must be \ref RNDIS_MSG_INITIALIZE
+ uint32_t length ; ///< Message length in bytes, must be 0x18
+ uint32_t request_id ; ///< A 32-bit integer value, generated by the host, used to match the host's sent request to the response from the device.
+ uint32_t major_version ; ///< The major version of the RNDIS Protocol implemented by the host.
+ uint32_t minor_version ; ///< The minor version of the RNDIS Protocol implemented by the host
+ uint32_t max_xfer_size ; ///< The maximum size, in bytes, of any single bus data transfer that the host expects to receive from the device.
+}rndis_msg_initialize_t;
+
+/// \brief Initialize Complete Message
+/// \details This message MUST be sent by the device in response to an initialize message.
+typedef struct {
+ uint32_t type ; ///< Message Type, must be \ref RNDIS_MSG_INITIALIZE_CMPLT
+ uint32_t length ; ///< Message length in bytes, must be 0x30
+ uint32_t request_id ; ///< A 32-bit integer value from \a request_id field of the \ref rndis_msg_initialize_t to which this message is a response.
+ uint32_t status ; ///< The initialization status of the device, has value from \ref rndis_msg_status_t
+ uint32_t major_version ; ///< the highest-numbered RNDIS Protocol version supported by the device.
+ uint32_t minor_version ; ///< the highest-numbered RNDIS Protocol version supported by the device.
+ uint32_t device_flags ; ///< MUST be set to 0x000000010. Other values are reserved for future use.
+ uint32_t medium ; ///< is 0x00 for RNDIS_MEDIUM_802_3
+ uint32_t max_packet_per_xfer ; ///< The maximum number of concatenated \ref RNDIS_MSG_PACKET messages that the device can handle in a single bus transfer to it. This value MUST be at least 1.
+ uint32_t max_xfer_size ; ///< The maximum size, in bytes, of any single bus data transfer that the device expects to receive from the host.
+ uint32_t packet_alignment_factor ; ///< The byte alignment the device expects for each RNDIS message that is part of a multimessage transfer to it. The value is specified as an exponent of 2; for example, the host uses 2<SUP>{PacketAlignmentFactor}</SUP> as the alignment value.
+ uint32_t reserved[2] ;
+} rndis_msg_initialize_cmplt_t;
+
+//------------- Query -------------//
+/// \brief Query Message
+/// \details This message MUST be sent by the host to query an OID.
+typedef struct {
+ uint32_t type ; ///< Message Type, must be \ref RNDIS_MSG_QUERY
+ uint32_t length ; ///< Message length in bytes, including the header and the \a oid_buffer
+ uint32_t request_id ; ///< A 32-bit integer value, generated by the host, used to match the host's sent request to the response from the device.
+ uint32_t oid ; ///< The integer value of the host operating system-defined identifier, for the parameter of the device being queried for.
+ uint32_t buffer_length ; ///< The length, in bytes, of the input data required for the OID query. This MUST be set to 0 when there is no input data associated with the OID.
+ uint32_t buffer_offset ; ///< The offset, in bytes, from the beginning of \a request_id field where the input data for the query is located in the message. This value MUST be set to 0 when there is no input data associated with the OID.
+ uint32_t reserved ;
+ uint8_t oid_buffer[] ; ///< Flexible array contains the input data supplied by the host, required for the OID query request processing by the device, as per the host NDIS specification.
+} rndis_msg_query_t, rndis_msg_set_t;
+
+TU_VERIFY_STATIC(sizeof(rndis_msg_query_t) == 28, "Make sure flexible array member does not affect layout");
+
+/// \brief Query Complete Message
+/// \details This message MUST be sent by the device in response to a query OID message.
+typedef struct {
+ uint32_t type ; ///< Message Type, must be \ref RNDIS_MSG_QUERY_CMPLT
+ uint32_t length ; ///< Message length in bytes, including the header and the \a oid_buffer
+ uint32_t request_id ; ///< A 32-bit integer value from \a request_id field of the \ref rndis_msg_query_t to which this message is a response.
+ uint32_t status ; ///< The status of processing for the query request, has value from \ref rndis_msg_status_t.
+ uint32_t buffer_length ; ///< The length, in bytes, of the data in the response to the query. This MUST be set to 0 when there is no OIDInputBuffer.
+ uint32_t buffer_offset ; ///< The offset, in bytes, from the beginning of \a request_id field where the response data for the query is located in the message. This MUST be set to 0 when there is no \ref oid_buffer.
+ uint8_t oid_buffer[] ; ///< Flexible array member contains the response data to the OID query request as specified by the host.
+} rndis_msg_query_cmplt_t;
+
+TU_VERIFY_STATIC(sizeof(rndis_msg_query_cmplt_t) == 24, "Make sure flexible array member does not affect layout");
+
+//------------- Reset -------------//
+/// \brief Reset Message
+/// \details This message MUST be sent by the host to perform a soft reset on the device.
+typedef struct {
+ uint32_t type ; ///< Message Type, must be \ref RNDIS_MSG_RESET
+ uint32_t length ; ///< Message length in bytes, MUST be 0x06
+ uint32_t reserved ;
+} rndis_msg_reset_t;
+
+/// \brief Reset Complete Message
+/// \details This message MUST be sent by the device in response to a reset message.
+typedef struct {
+ uint32_t type ; ///< Message Type, must be \ref RNDIS_MSG_RESET_CMPLT
+ uint32_t length ; ///< Message length in bytes, MUST be 0x10
+ uint32_t status ; ///< The status of processing for the \ref rndis_msg_reset_t, has value from \ref rndis_msg_status_t.
+ uint32_t addressing_reset ; ///< This field indicates whether the addressing information, which is the multicast address list or packet filter, has been lost during the reset operation. This MUST be set to 0x00000001 if the device requires that the host to resend addressing information or MUST be set to zero otherwise.
+} rndis_msg_reset_cmplt_t;
+
+//typedef struct {
+// uint32_t type;
+// uint32_t length;
+// uint32_t status;
+// uint32_t buffer_length;
+// uint32_t buffer_offset;
+// uint32_t diagnostic_status; // optional
+// uint32_t diagnostic_error_offset; // optional
+// uint32_t status_buffer[0]; // optional
+//} rndis_msg_indicate_status_t;
+
+/// \brief Keep Alive Message
+/// \details This message MUST be sent by the host to check that device is still responsive. It is optional for the device to send this message to check if the host is active
+typedef struct {
+ uint32_t type ; ///< Message Type
+ uint32_t length ; ///< Message length in bytes, MUST be 0x10
+ uint32_t request_id ;
+} rndis_msg_keep_alive_t, rndis_msg_halt_t;
+
+/// \brief Set Complete Message
+/// \brief This message MUST be sent in response to a the request message
+typedef struct {
+ uint32_t type ; ///< Message Type
+ uint32_t length ; ///< Message length in bytes, MUST be 0x10
+ uint32_t request_id ; ///< must be the same as requesting message
+ uint32_t status ; ///< The status of processing for the request message request by the device to which this message is the response.
+} rndis_msg_set_cmplt_t, rndis_msg_keep_alive_cmplt_t;
+
+/// \brief Packet Data Message
+/// \brief This message MUST be used by the host and the device to send network data to one another.
+typedef struct {
+ uint32_t type ; ///< Message Type, must be \ref RNDIS_MSG_PACKET
+ uint32_t length ; ///< Message length in bytes, The total length of this RNDIS message including the header, payload, and padding.
+ uint32_t data_offset ; ///< Specifies the offset, in bytes, from the start of this \a data_offset field of this message to the start of the data. This MUST be an integer multiple of 4.
+ uint32_t data_length ; ///< Specifies the number of bytes in the payload of this message.
+ uint32_t out_of_band_data_offet ; ///< Specifies the offset, in bytes, of the first out-of-band data record from the start of the DataOffset field in this message. MUST be an integer multiple of 4 when out-of-band data is present or set to 0 otherwise. When there are multiple out-ofband data records, each subsequent record MUST immediately follow the previous out-of-band data record.
+ uint32_t out_of_band_data_length ; ///< Specifies, in bytes, the total length of the out-of-band data.
+ uint32_t num_out_of_band_data_elements ; ///< Specifies the number of out-of-band records in this message.
+ uint32_t per_packet_info_offset ; ///< Specifies the offset, in bytes, of the start of per-packet-info data record from the start of the \a data_offset field in this message. MUST be an integer multiple of 4 when per-packet-info data record is present or MUST be set to 0 otherwise. When there are multiple per-packet-info data records, each subsequent record MUST immediately follow the previous record.
+ uint32_t per_packet_info_length ; ///< Specifies, in bytes, the total length of per-packetinformation contained in this message.
+ uint32_t reserved[2] ;
+ uint32_t payload[0] ; ///< Network data contained in this message.
+
+ // uint8_t padding[0]
+ // Additional bytes of zeros added at the end of the message to comply with
+ // the internal and external padding requirements. Internal padding SHOULD be as per the
+ // specification of the out-of-band data record and per-packet-info data record. The external
+ //padding size SHOULD be determined based on the PacketAlignmentFactor field specification
+ //in REMOTE_NDIS_INITIALIZE_CMPLT message by the device, when multiple
+ //REMOTE_NDIS_PACKET_MSG messages are bundled together in a single bus-native message.
+ //In this case, all but the very last REMOTE_NDIS_PACKET_MSG MUST respect the
+ //PacketAlignmentFactor field.
+
+ // rndis_msg_packet_t [0] : (optional) more packet if multiple packet per bus transaction is supported
+} rndis_msg_packet_t;
+
+
+typedef struct {
+ uint32_t size ; ///< Length, in bytes, of this header and appended data and padding. This value MUST be an integer multiple of 4.
+ uint32_t type ; ///< MUST be as per host operating system specification.
+ uint32_t offset ; ///< The byte offset from the beginning of this record to the beginning of data.
+ uint32_t data[0] ; ///< Flexible array contains data
+} rndis_msg_out_of_band_data_t, rndis_msg_per_packet_info_t;
+
+//--------------------------------------------------------------------+
+// NDIS Object ID
+//--------------------------------------------------------------------+
+
+/// NDIS Object ID
+typedef enum
+{
+ //------------- General Required OIDs -------------//
+ RNDIS_OID_GEN_SUPPORTED_LIST = 0x00010101, ///< List of supported OIDs
+ RNDIS_OID_GEN_HARDWARE_STATUS = 0x00010102, ///< Hardware status
+ RNDIS_OID_GEN_MEDIA_SUPPORTED = 0x00010103, ///< Media types supported (encoded)
+ RNDIS_OID_GEN_MEDIA_IN_USE = 0x00010104, ///< Media types in use (encoded)
+ RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD = 0x00010105, ///<
+ RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE = 0x00010106, ///< Maximum frame size in bytes
+ RNDIS_OID_GEN_LINK_SPEED = 0x00010107, ///< Link speed in units of 100 bps
+ RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE = 0x00010108, ///< Transmit buffer space
+ RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE = 0x00010109, ///< Receive buffer space
+ RNDIS_OID_GEN_TRANSMIT_BLOCK_SIZE = 0x0001010A, ///< Minimum amount of storage, in bytes, that a single packet occupies in the transmit buffer space of the NIC
+ RNDIS_OID_GEN_RECEIVE_BLOCK_SIZE = 0x0001010B, ///< Amount of storage, in bytes, that a single packet occupies in the receive buffer space of the NIC
+ RNDIS_OID_GEN_VENDOR_ID = 0x0001010C, ///< Vendor NIC code
+ RNDIS_OID_GEN_VENDOR_DESCRIPTION = 0x0001010D, ///< Vendor network card description
+ RNDIS_OID_GEN_CURRENT_PACKET_FILTER = 0x0001010E, ///< Current packet filter (encoded)
+ RNDIS_OID_GEN_CURRENT_LOOKAHEAD = 0x0001010F, ///< Current lookahead size in bytes
+ RNDIS_OID_GEN_DRIVER_VERSION = 0x00010110, ///< NDIS version number used by the driver
+ RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE = 0x00010111, ///< Maximum total packet length in bytes
+ RNDIS_OID_GEN_PROTOCOL_OPTIONS = 0x00010112, ///< Optional protocol flags (encoded)
+ RNDIS_OID_GEN_MAC_OPTIONS = 0x00010113, ///< Optional NIC flags (encoded)
+ RNDIS_OID_GEN_MEDIA_CONNECT_STATUS = 0x00010114, ///< Whether the NIC is connected to the network
+ RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS = 0x00010115, ///< The maximum number of send packets the driver can accept per call to its MiniportSendPacketsfunction
+
+ //------------- General Optional OIDs -------------//
+ RNDIS_OID_GEN_VENDOR_DRIVER_VERSION = 0x00010116, ///< Vendor-assigned version number of the driver
+ RNDIS_OID_GEN_SUPPORTED_GUIDS = 0x00010117, ///< The custom GUIDs (Globally Unique Identifier) supported by the miniport driver
+ RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES = 0x00010118, ///< List of network-layer addresses associated with the binding between a transport and the driver
+ RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET = 0x00010119, ///< Size of packets' additional headers
+ RNDIS_OID_GEN_MEDIA_CAPABILITIES = 0x00010201, ///<
+ RNDIS_OID_GEN_PHYSICAL_MEDIUM = 0x00010202, ///< Physical media supported by the miniport driver (encoded)
+
+ //------------- 802.3 Objects (Ethernet) -------------//
+ RNDIS_OID_802_3_PERMANENT_ADDRESS = 0x01010101, ///< Permanent station address
+ RNDIS_OID_802_3_CURRENT_ADDRESS = 0x01010102, ///< Current station address
+ RNDIS_OID_802_3_MULTICAST_LIST = 0x01010103, ///< Current multicast address list
+ RNDIS_OID_802_3_MAXIMUM_LIST_SIZE = 0x01010104, ///< Maximum size of multicast address list
+} rndis_oid_type_t;
+
+/// RNDIS Packet Filter Bits \ref RNDIS_OID_GEN_CURRENT_PACKET_FILTER.
+typedef enum
+{
+ RNDIS_PACKET_TYPE_DIRECTED = 0x00000001, ///< Directed packets. Directed packets contain a destination address equal to the station address of the NIC.
+ RNDIS_PACKET_TYPE_MULTICAST = 0x00000002, ///< Multicast address packets sent to addresses in the multicast address list.
+ RNDIS_PACKET_TYPE_ALL_MULTICAST = 0x00000004, ///< All multicast address packets, not just the ones enumerated in the multicast address list.
+ RNDIS_PACKET_TYPE_BROADCAST = 0x00000008, ///< Broadcast packets.
+ RNDIS_PACKET_TYPE_SOURCE_ROUTING = 0x00000010, ///< All source routing packets. If the protocol driver sets this bit, the NDIS library attempts to act as a source routing bridge.
+ RNDIS_PACKET_TYPE_PROMISCUOUS = 0x00000020, ///< Specifies all packets regardless of whether VLAN filtering is enabled or not and whether the VLAN identifier matches or not.
+ RNDIS_PACKET_TYPE_SMT = 0x00000040, ///< SMT packets that an FDDI NIC receives.
+ RNDIS_PACKET_TYPE_ALL_LOCAL = 0x00000080, ///< All packets sent by installed protocols and all packets indicated by the NIC that is identified by a given NdisBindingHandle.
+ RNDIS_PACKET_TYPE_GROUP = 0x00001000, ///< Packets sent to the current group address.
+ RNDIS_PACKET_TYPE_ALL_FUNCTIONAL = 0x00002000, ///< All functional address packets, not just the ones in the current functional address.
+ RNDIS_PACKET_TYPE_FUNCTIONAL = 0x00004000, ///< Functional address packets sent to addresses included in the current functional address.
+ RNDIS_PACKET_TYPE_MAC_FRAME = 0x00008000, ///< NIC driver frames that a Token Ring NIC receives.
+ RNDIS_PACKET_TYPE_NO_LOCAL = 0x00010000,
+} rndis_packet_filter_type_t;
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CDC_RNDIS_H_ */
+
+/** @} */
+/** @} */
diff --git a/arkanoid/pico/tinyusb/cdc/cdc_rndis_host.c b/arkanoid/pico/tinyusb/cdc/cdc_rndis_host.c
new file mode 100644
index 0000000..248a3c4
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc_rndis_host.c
@@ -0,0 +1,279 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../tusb_option.h"
+
+#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_CDC && CFG_TUH_CDC_RNDIS)
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "../tusb_common.h"
+#include "cdc_host.h"
+#include "cdc_rndis_host.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+#define RNDIS_MSG_PAYLOAD_MAX (1024*4)
+
+CFG_TUSB_MEM_SECTION static uint8_t msg_notification[CFG_TUH_DEVICE_MAX][8];
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t msg_payload[RNDIS_MSG_PAYLOAD_MAX];
+
+static rndish_data_t rndish_data[CFG_TUH_DEVICE_MAX];
+
+// TODO Microsoft requires message length for any get command must be at least 4096 bytes
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+static tusb_error_t rndis_body_subtask(void);
+static tusb_error_t send_message_get_response_subtask( uint8_t dev_addr, cdch_data_t *p_cdc,
+ uint8_t * p_mess, uint32_t mess_length,
+ uint8_t *p_response );
+
+//--------------------------------------------------------------------+
+// APPLICATION API
+//--------------------------------------------------------------------+
+tusb_error_t tusbh_cdc_rndis_get_mac_addr(uint8_t dev_addr, uint8_t mac_address[6])
+{
+ TU_ASSERT( tusbh_cdc_rndis_is_mounted(dev_addr), TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED);
+ TU_VERIFY( mac_address, TUSB_ERROR_INVALID_PARA);
+
+ memcpy(mac_address, rndish_data[dev_addr-1].mac_address, 6);
+
+ return TUSB_ERROR_NONE;
+}
+
+//--------------------------------------------------------------------+
+// IMPLEMENTATION
+//--------------------------------------------------------------------+
+
+// To enable the TASK_ASSERT style (quick return on false condition) in a real RTOS, a task must act as a wrapper
+// and is used mainly to call subtasks. Within a subtask return statement can be called freely, the task with
+// forever loop cannot have any return at all.
+OSAL_TASK_FUNCTION(cdch_rndis_task) (void* param;)
+{
+ OSAL_TASK_BEGIN
+ rndis_body_subtask();
+ OSAL_TASK_END
+}
+
+static tusb_error_t rndis_body_subtask(void)
+{
+ static uint8_t relative_addr;
+
+ OSAL_SUBTASK_BEGIN
+
+ for (relative_addr = 0; relative_addr < CFG_TUH_DEVICE_MAX; relative_addr++)
+ {
+
+ }
+
+ osal_task_delay(100);
+
+ OSAL_SUBTASK_END
+}
+
+//--------------------------------------------------------------------+
+// RNDIS-CDC Driver API
+//--------------------------------------------------------------------+
+void rndish_init(void)
+{
+ tu_memclr(rndish_data, sizeof(rndish_data_t)*CFG_TUH_DEVICE_MAX);
+
+ //------------- Task creation -------------//
+
+ //------------- semaphore creation for notificaiton pipe -------------//
+ for(uint8_t i=0; i<CFG_TUH_DEVICE_MAX; i++)
+ {
+ rndish_data[i].sem_notification_hdl = osal_semaphore_create( OSAL_SEM_REF(rndish_data[i].semaphore_notification) );
+ }
+}
+
+void rndish_close(uint8_t dev_addr)
+{
+ osal_semaphore_reset( rndish_data[dev_addr-1].sem_notification_hdl );
+// tu_memclr(&rndish_data[dev_addr-1], sizeof(rndish_data_t)); TODO need to move semaphore & its handle out before memclr
+}
+
+
+static rndis_msg_initialize_t const msg_init =
+{
+ .type = RNDIS_MSG_INITIALIZE,
+ .length = sizeof(rndis_msg_initialize_t),
+ .request_id = 1, // TODO should use some magic number
+ .major_version = 1,
+ .minor_version = 0,
+ .max_xfer_size = 0x4000 // TODO mimic windows
+};
+
+static rndis_msg_query_t const msg_query_permanent_addr =
+{
+ .type = RNDIS_MSG_QUERY,
+ .length = sizeof(rndis_msg_query_t)+6,
+ .request_id = 1,
+ .oid = RNDIS_OID_802_3_PERMANENT_ADDRESS,
+ .buffer_length = 6,
+ .buffer_offset = 20,
+};
+
+static rndis_msg_set_t const msg_set_packet_filter =
+{
+ .type = RNDIS_MSG_SET,
+ .length = sizeof(rndis_msg_set_t)+4,
+ .request_id = 1,
+ .oid = RNDIS_OID_GEN_CURRENT_PACKET_FILTER,
+ .buffer_length = 4,
+ .buffer_offset = 20,
+};
+
+tusb_error_t rndish_open_subtask(uint8_t dev_addr, cdch_data_t *p_cdc)
+{
+ tusb_error_t error;
+
+ OSAL_SUBTASK_BEGIN
+
+ //------------- Message Initialize -------------//
+ memcpy(msg_payload, &msg_init, sizeof(rndis_msg_initialize_t));
+ STASK_INVOKE(
+ send_message_get_response_subtask( dev_addr, p_cdc,
+ msg_payload, sizeof(rndis_msg_initialize_t),
+ msg_payload),
+ error
+ );
+ if ( TUSB_ERROR_NONE != error ) STASK_RETURN(error);
+
+ // TODO currently not support multiple data packets per xfer
+ rndis_msg_initialize_cmplt_t * const p_init_cmpt = (rndis_msg_initialize_cmplt_t *) msg_payload;
+ STASK_ASSERT(p_init_cmpt->type == RNDIS_MSG_INITIALIZE_CMPLT && p_init_cmpt->status == RNDIS_STATUS_SUCCESS &&
+ p_init_cmpt->max_packet_per_xfer == 1 && p_init_cmpt->max_xfer_size <= RNDIS_MSG_PAYLOAD_MAX);
+ rndish_data[dev_addr-1].max_xfer_size = p_init_cmpt->max_xfer_size;
+
+ //------------- Message Query 802.3 Permanent Address -------------//
+ memcpy(msg_payload, &msg_query_permanent_addr, sizeof(rndis_msg_query_t));
+ tu_memclr(msg_payload + sizeof(rndis_msg_query_t), 6); // 6 bytes for MAC address
+
+ STASK_INVOKE(
+ send_message_get_response_subtask( dev_addr, p_cdc,
+ msg_payload, sizeof(rndis_msg_query_t) + 6,
+ msg_payload),
+ error
+ );
+ if ( TUSB_ERROR_NONE != error ) STASK_RETURN(error);
+
+ rndis_msg_query_cmplt_t * const p_query_cmpt = (rndis_msg_query_cmplt_t *) msg_payload;
+ STASK_ASSERT(p_query_cmpt->type == RNDIS_MSG_QUERY_CMPLT && p_query_cmpt->status == RNDIS_STATUS_SUCCESS);
+ memcpy(rndish_data[dev_addr-1].mac_address, msg_payload + 8 + p_query_cmpt->buffer_offset, 6);
+
+ //------------- Set OID_GEN_CURRENT_PACKET_FILTER to (DIRECTED | MULTICAST | BROADCAST) -------------//
+ memcpy(msg_payload, &msg_set_packet_filter, sizeof(rndis_msg_set_t));
+ tu_memclr(msg_payload + sizeof(rndis_msg_set_t), 4); // 4 bytes for filter flags
+ ((rndis_msg_set_t*) msg_payload)->oid_buffer[0] = (RNDIS_PACKET_TYPE_DIRECTED | RNDIS_PACKET_TYPE_MULTICAST | RNDIS_PACKET_TYPE_BROADCAST);
+
+ STASK_INVOKE(
+ send_message_get_response_subtask( dev_addr, p_cdc,
+ msg_payload, sizeof(rndis_msg_set_t) + 4,
+ msg_payload),
+ error
+ );
+ if ( TUSB_ERROR_NONE != error ) STASK_RETURN(error);
+
+ rndis_msg_set_cmplt_t * const p_set_cmpt = (rndis_msg_set_cmplt_t *) msg_payload;
+ STASK_ASSERT(p_set_cmpt->type == RNDIS_MSG_SET_CMPLT && p_set_cmpt->status == RNDIS_STATUS_SUCCESS);
+
+ tusbh_cdc_rndis_mounted_cb(dev_addr);
+
+ OSAL_SUBTASK_END
+}
+
+void rndish_xfer_isr(cdch_data_t *p_cdc, pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes)
+{
+ if ( pipehandle_is_equal(pipe_hdl, p_cdc->pipe_notification) )
+ {
+ osal_semaphore_post( rndish_data[pipe_hdl.dev_addr-1].sem_notification_hdl );
+ }
+}
+
+//--------------------------------------------------------------------+
+// INTERNAL & HELPER
+//--------------------------------------------------------------------+
+static tusb_error_t send_message_get_response_subtask( uint8_t dev_addr, cdch_data_t *p_cdc,
+ uint8_t * p_mess, uint32_t mess_length,
+ uint8_t *p_response)
+{
+ tusb_error_t error;
+
+ OSAL_SUBTASK_BEGIN
+
+ //------------- Send RNDIS Control Message -------------//
+ STASK_INVOKE(
+ usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_OUT, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_INTERFACE),
+ CDC_REQUEST_SEND_ENCAPSULATED_COMMAND, 0, p_cdc->interface_number,
+ mess_length, p_mess),
+ error
+ );
+ if ( TUSB_ERROR_NONE != error ) STASK_RETURN(error);
+
+ //------------- waiting for Response Available notification -------------//
+ (void) usbh_edpt_xfer(p_cdc->pipe_notification, msg_notification[dev_addr-1], 8);
+ osal_semaphore_wait(rndish_data[dev_addr-1].sem_notification_hdl, OSAL_TIMEOUT_NORMAL, &error);
+ if ( TUSB_ERROR_NONE != error ) STASK_RETURN(error);
+ STASK_ASSERT(msg_notification[dev_addr-1][0] == 1);
+
+ //------------- Get RNDIS Message Initialize Complete -------------//
+ STASK_INVOKE(
+ usbh_control_xfer_subtask( dev_addr, bm_request_type(TUSB_DIR_IN, TUSB_REQ_TYPE_CLASS, TUSB_REQ_RCPT_INTERFACE),
+ CDC_REQUEST_GET_ENCAPSULATED_RESPONSE, 0, p_cdc->interface_number,
+ RNDIS_MSG_PAYLOAD_MAX, p_response),
+ error
+ );
+ if ( TUSB_ERROR_NONE != error ) STASK_RETURN(error);
+
+ OSAL_SUBTASK_END
+}
+
+//static tusb_error_t send_process_msg_initialize_subtask(uint8_t dev_addr, cdch_data_t *p_cdc)
+//{
+// tusb_error_t error;
+//
+// OSAL_SUBTASK_BEGIN
+//
+// *((rndis_msg_initialize_t*) msg_payload) = (rndis_msg_initialize_t)
+// {
+// .type = RNDIS_MSG_INITIALIZE,
+// .length = sizeof(rndis_msg_initialize_t),
+// .request_id = 1, // TODO should use some magic number
+// .major_version = 1,
+// .minor_version = 0,
+// .max_xfer_size = 0x4000 // TODO mimic windows
+// };
+//
+//
+//
+// OSAL_SUBTASK_END
+//}
+#endif
diff --git a/arkanoid/pico/tinyusb/cdc/cdc_rndis_host.h b/arkanoid/pico/tinyusb/cdc/cdc_rndis_host.h
new file mode 100644
index 0000000..9e7ff02
--- /dev/null
+++ b/arkanoid/pico/tinyusb/cdc/cdc_rndis_host.h
@@ -0,0 +1,63 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup CDC_RNDIS
+ * \defgroup CDC_RNSID_Host Host
+ * @{ */
+
+#ifndef _TUSB_CDC_RNDIS_HOST_H_
+#define _TUSB_CDC_RNDIS_HOST_H_
+
+#include "../tusb_common.h"
+#include "../host/usbh.h"
+#include "cdc_rndis.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// INTERNAL RNDIS-CDC Driver API
+//--------------------------------------------------------------------+
+typedef struct {
+ OSAL_SEM_DEF(semaphore_notification);
+ osal_semaphore_handle_t sem_notification_hdl; // used to wait on notification pipe
+ uint32_t max_xfer_size; // got from device's msg initialize complete
+ uint8_t mac_address[6];
+}rndish_data_t;
+
+void rndish_init(void);
+tusb_error_t rndish_open_subtask(uint8_t dev_addr, cdch_data_t *p_cdc);
+void rndish_xfer_isr(cdch_data_t *p_cdc, pipe_handle_t pipe_hdl, xfer_result_t event, uint32_t xferred_bytes);
+void rndish_close(uint8_t dev_addr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_CDC_RNDIS_HOST_H_ */
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/dcd.h b/arkanoid/pico/tinyusb/dcd.h
new file mode 100644
index 0000000..754e09e
--- /dev/null
+++ b/arkanoid/pico/tinyusb/dcd.h
@@ -0,0 +1,190 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_DCD_H_
+#define _TUSB_DCD_H_
+
+#include "tusb_common.h"
+#include "osal.h"
+#include "tusb_fifo.h"
+#include "dcd_attr.h"
+
+// TODO this file has been merged with portable/ dcd_rp2040.c
+
+#include "tusb_option.h"
+
+//--------------------------------------------------------------------+
+// Configuration
+//--------------------------------------------------------------------+
+
+#ifndef CFG_TUD_ENDPPOINT_MAX
+ #define CFG_TUD_ENDPPOINT_MAX DCD_ATTR_ENDPOINT_MAX
+#endif
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF PROTYPES
+//--------------------------------------------------------------------+
+
+typedef enum
+{
+ DCD_EVENT_INVALID = 0,
+ DCD_EVENT_BUS_RESET,
+ DCD_EVENT_UNPLUGGED,
+ DCD_EVENT_SOF,
+ DCD_EVENT_SUSPEND, // TODO LPM Sleep L1 support
+ DCD_EVENT_RESUME,
+
+ DCD_EVENT_SETUP_RECEIVED,
+ DCD_EVENT_XFER_COMPLETE,
+
+ // Not an DCD event, just a convenient way to defer ISR function
+ USBD_EVENT_FUNC_CALL,
+
+ DCD_EVENT_COUNT
+} dcd_eventid_t;
+
+typedef struct TU_ATTR_ALIGNED(4)
+{
+ uint8_t rhport;
+ uint8_t event_id;
+
+ union
+ {
+ // BUS RESET
+ struct {
+ tusb_speed_t speed;
+ } bus_reset;
+
+ // SETUP_RECEIVED
+ tusb_control_request_t setup_received;
+
+ // XFER_COMPLETE
+ struct {
+ uint8_t ep_addr;
+ uint8_t result;
+ uint32_t len;
+ }xfer_complete;
+
+ // FUNC_CALL
+ struct {
+ void (*func) (void*);
+ void* param;
+ }func_call;
+ };
+} dcd_event_t;
+
+//TU_VERIFY_STATIC(sizeof(dcd_event_t) <= 12, "size is not correct");
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// Initialize controller to device mode
+void dcd_init (uint8_t rhport);
+
+// Interrupt Handler
+#if __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+void dcd_int_handler(uint8_t rhport);
+#if __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+// Enable device interrupt
+void dcd_int_enable (uint8_t rhport);
+
+// Disable device interrupt
+void dcd_int_disable(uint8_t rhport);
+
+// Receive Set Address request, mcu port must also include status IN response
+void dcd_set_address(uint8_t rhport, uint8_t dev_addr);
+
+// Wake up host
+void dcd_remote_wakeup(uint8_t rhport);
+
+// Connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(uint8_t rhport) TU_ATTR_WEAK;
+
+// Disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(uint8_t rhport) TU_ATTR_WEAK;
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// Invoked when a control transfer's status stage is complete.
+// May help DCD to prepare for next control transfer, this API is optional.
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request) TU_ATTR_WEAK;
+
+// Configure endpoint's registers according to descriptor
+bool dcd_edpt_open (uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
+
+// Close all non-control endpoints, cancel all pending transfers if any.
+// Invoked when switching from a non-zero Configuration by SET_CONFIGURE therefore
+// required for multiple configuration support.
+void dcd_edpt_close_all (uint8_t rhport);
+
+// Close an endpoint.
+// Since it is weak, caller must TU_ASSERT this function's existence before calling it.
+void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr) TU_ATTR_WEAK;
+
+// Submit a transfer, When complete dcd_event_xfer_complete() is invoked to notify the stack
+bool dcd_edpt_xfer (uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+
+// Submit an transfer using fifo, When complete dcd_event_xfer_complete() is invoked to notify the stack
+// This API is optional, may be useful for register-based for transferring data.
+bool dcd_edpt_xfer_fifo (uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes) TU_ATTR_WEAK;
+
+// Stall endpoint, any queuing transfer should be removed from endpoint
+void dcd_edpt_stall (uint8_t rhport, uint8_t ep_addr);
+
+// clear stall, data toggle is also reset to DATA0
+// This API never calls with control endpoints, since it is auto cleared when receiving setup packet
+void dcd_edpt_clear_stall (uint8_t rhport, uint8_t ep_addr);
+
+//--------------------------------------------------------------------+
+// Event API (implemented by stack)
+//--------------------------------------------------------------------+
+
+// Called by DCD to notify device stack
+extern void dcd_event_handler(dcd_event_t const * event, bool in_isr);
+
+// helper to send bus signal event
+extern void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr);
+
+// helper to send bus reset event
+extern void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr);
+
+// helper to send setup received
+extern void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr);
+
+// helper to send transfer complete event
+extern void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr);
+
+
+#endif /* _TUSB_DCD_H_ */
diff --git a/arkanoid/pico/tinyusb/dcd_attr.h b/arkanoid/pico/tinyusb/dcd_attr.h
new file mode 100644
index 0000000..44f2cc1
--- /dev/null
+++ b/arkanoid/pico/tinyusb/dcd_attr.h
@@ -0,0 +1,167 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_DCD_ATTR_H_
+#define TUSB_DCD_ATTR_H_
+
+#include "tusb_option.h"
+
+// Attribute includes
+// - ENDPOINT_MAX: max (logical) number of endpoint
+// - ENDPOINT_EXCLUSIVE_NUMBER: endpoint number with different direction IN and OUT aren't allowed,
+// e.g EP1 OUT & EP1 IN cannot exist together
+// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
+
+//------------- NXP -------------//
+#if TU_CHECK_MCU(LPC11UXX) || TU_CHECK_MCU(LPC13XX) || TU_CHECK_MCU(LPC15XX)
+ #define DCD_ATTR_ENDPOINT_MAX 5
+
+#elif TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+ #define DCD_ATTR_ENDPOINT_MAX 16
+
+#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+ // TODO USB0 has 6, USB1 has 4
+ #define DCD_ATTR_ENDPOINT_MAX 6
+
+#elif TU_CHECK_MCU(LPC51UXX)
+ #define DCD_ATTR_ENDPOINT_MAX 5
+
+#elif TU_CHECK_MCU(LPC54XXX)
+ // TODO USB0 has 5, USB1 has 6
+ #define DCD_ATTR_ENDPOINT_MAX 6
+
+#elif TU_CHECK_MCU(LPC55XX)
+ // TODO USB0 has 5, USB1 has 6
+ #define DCD_ATTR_ENDPOINT_MAX 6
+
+#elif TU_CHECK_MCU(MIMXRT10XX)
+ #define DCD_ATTR_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(MKL25ZXX) || TU_CHECK_MCU(K32L2BXX)
+ #define DCD_ATTR_ENDPOINT_MAX 16
+
+#elif TU_CHECK_MCU(MM32F327X)
+ #define DCD_ATTR_ENDPOINT_MAX 16
+
+//------------- Nordic -------------//
+#elif TU_CHECK_MCU(NRF5X)
+ // 8 CBI + 1 ISO
+ #define DCD_ATTR_ENDPOINT_MAX 9
+
+//------------- Microchip -------------//
+#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
+ TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+ #define DCD_ATTR_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(SAMG)
+ #define DCD_ATTR_ENDPOINT_MAX 6
+ #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+
+#elif TU_CHECK_MCU(SAMX7X)
+ #define DCD_ATTR_ENDPOINT_MAX 10
+ #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+
+//------------- ST -------------//
+#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
+ TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
+ // F1: F102, F103
+ // L4: L4x2, L4x3
+ #define DCD_ATTR_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
+ // F1: F105, F107 only has 4
+ // L4: L4x5, L4x6 has 6
+ // For most mcu, FS has 4, HS has 6
+ #define DCD_ATTR_ENDPOINT_MAX 6
+
+#elif TU_CHECK_MCU(STM32F7)
+ // FS has 6, HS has 9
+ #define DCD_ATTR_ENDPOINT_MAX 9
+
+#elif TU_CHECK_MCU(STM32H7)
+ #define DCD_ATTR_ENDPOINT_MAX 9
+
+//------------- Sony -------------//
+#elif TU_CHECK_MCU(CXD56)
+ #define DCD_ATTR_ENDPOINT_MAX 7
+ #define DCD_ATTR_ENDPOINT_EXCLUSIVE_NUMBER
+
+//------------- TI -------------//
+#elif TU_CHECK_MCU(MSP430x5xx)
+ #define DCD_ATTR_ENDPOINT_MAX 8
+
+//------------- ValentyUSB -------------//
+#elif TU_CHECK_MCU(VALENTYUSB_EPTRI)
+ #define DCD_ATTR_ENDPOINT_MAX 16
+
+//------------- Nuvoton -------------//
+#elif TU_CHECK_MCU(NUC121) || TU_CHECK_MCU(NUC126)
+ #define DCD_ATTR_ENDPOINT_MAX 8
+
+#elif TU_CHECK_MCU(NUC120)
+ #define DCD_ATTR_ENDPOINT_MAX 6
+
+#elif TU_CHECK_MCU(NUC505)
+ #define DCD_ATTR_ENDPOINT_MAX 12
+
+//------------- Espressif -------------//
+#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+ #define DCD_ATTR_ENDPOINT_MAX 6
+
+//------------- Dialog -------------//
+#elif TU_CHECK_MCU(DA1469X)
+ #define DCD_ATTR_ENDPOINT_MAX 4
+
+//------------- Raspberry Pi -------------//
+#elif TU_CHECK_MCU(RP2040)
+ #define DCD_ATTR_ENDPOINT_MAX 16
+
+//------------- Silabs -------------//
+#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
+ #define DCD_ATTR_ENDPOINT_MAX 7
+
+//------------- Renesas -------------//
+#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
+ #define DCD_ATTR_ENDPOINT_MAX 10
+
+//#elif TU_CHECK_MCU(MM32F327X)
+// #define DCD_ATTR_ENDPOINT_MAX not known yet
+
+//------------- GigaDevice -------------//
+#elif TU_CHECK_MCU(GD32VF103)
+ #define DCD_ATTR_ENDPOINT_MAX 4
+
+#else
+ #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
+ #define DCD_ATTR_ENDPOINT_MAX 8
+#endif
+
+// Default to fullspeed if not defined
+//#ifndef PORT_HIGHSPEED
+// #define DCD_ATTR_PORT_HIGHSPEED 0x00
+//#endif
+
+#endif
diff --git a/arkanoid/pico/tinyusb/dcd_rp2040.c b/arkanoid/pico/tinyusb/dcd_rp2040.c
new file mode 100644
index 0000000..85e4d4a
--- /dev/null
+++ b/arkanoid/pico/tinyusb/dcd_rp2040.c
@@ -0,0 +1,494 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
+
+#include "../pico.h"
+#include "rp2040_usb.h"
+
+#if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
+#include "pico/fix/rp2040_usb_device_enumeration.h"
+#endif
+
+#include "dcd.h"
+
+// Current implementation force vbus detection as always present, causing device think it is always plugged into host.
+// Therefore it cannot detect disconnect event, mistaken it as suspend.
+// Note: won't work if change to 0 (for now)
+#define FORCE_VBUS_DETECT 1
+
+/*------------------------------------------------------------------*/
+/* Low level controller
+ *------------------------------------------------------------------*/
+
+#define usb_hw_set hw_set_alias(usb_hw)
+#define usb_hw_clear hw_clear_alias(usb_hw)
+
+// Init these in dcd_init
+static uint8_t *next_buffer_ptr;
+
+// USB_MAX_ENDPOINTS Endpoints, direction TUSB_DIR_OUT for out and TUSB_DIR_IN for in.
+static struct hw_endpoint hw_endpoints[USB_MAX_ENDPOINTS][2];
+
+static inline struct hw_endpoint *hw_endpoint_get_by_num(uint8_t num, tusb_dir_t dir)
+{
+ return &hw_endpoints[num][dir];
+}
+
+static struct hw_endpoint *hw_endpoint_get_by_addr(uint8_t ep_addr)
+{
+ uint8_t num = tu_edpt_number(ep_addr);
+ tusb_dir_t dir = tu_edpt_dir(ep_addr);
+ return hw_endpoint_get_by_num(num, dir);
+}
+
+static void _hw_endpoint_alloc(struct hw_endpoint *ep, uint8_t transfer_type)
+{
+ // size must be multiple of 64
+ uint size = tu_div_ceil(ep->wMaxPacketSize, 64) * 64u;
+
+ // double buffered Bulk endpoint
+ if ( transfer_type == TUSB_XFER_BULK )
+ {
+ size *= 2u;
+ }
+
+ ep->hw_data_buf = next_buffer_ptr;
+ next_buffer_ptr += size;
+
+ assert(((uintptr_t )next_buffer_ptr & 0b111111u) == 0);
+ uint dpram_offset = hw_data_offset(ep->hw_data_buf);
+ assert(hw_data_offset(next_buffer_ptr) <= USB_DPRAM_MAX);
+
+ pico_info(" Alloced %d bytes at offset 0x%x (0x%p)\r\n", size, dpram_offset, ep->hw_data_buf);
+
+ // Fill in endpoint control register with buffer offset
+ uint32_t const reg = EP_CTRL_ENABLE_BITS | ((uint)transfer_type << EP_CTRL_BUFFER_TYPE_LSB) | dpram_offset;
+
+ *ep->endpoint_control = reg;
+}
+
+#if 0 // todo unused
+static void _hw_endpoint_close(struct hw_endpoint *ep)
+{
+ // Clear hardware registers and then zero the struct
+ // Clears endpoint enable
+ *ep->endpoint_control = 0;
+ // Clears buffer available, etc
+ *ep->buffer_control = 0;
+ // Clear any endpoint state
+ memset(ep, 0, sizeof(struct hw_endpoint));
+}
+
+static void hw_endpoint_close(uint8_t ep_addr)
+{
+ struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+ _hw_endpoint_close(ep);
+}
+#endif
+
+static void hw_endpoint_init(uint8_t ep_addr, uint16_t wMaxPacketSize, uint8_t transfer_type)
+{
+ struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+
+ const uint8_t num = tu_edpt_number(ep_addr);
+ const tusb_dir_t dir = tu_edpt_dir(ep_addr);
+
+ ep->ep_addr = ep_addr;
+
+ // For device, IN is a tx transfer and OUT is an rx transfer
+ ep->rx = (dir == TUSB_DIR_OUT);
+
+ ep->next_pid = 0u;
+ ep->wMaxPacketSize = wMaxPacketSize;
+ ep->transfer_type = transfer_type;
+
+ // Every endpoint has a buffer control register in dpram
+ if ( dir == TUSB_DIR_IN )
+ {
+ ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].in;
+ }
+ else
+ {
+ ep->buffer_control = &usb_dpram->ep_buf_ctrl[num].out;
+ }
+
+ // Clear existing buffer control state
+ *ep->buffer_control = 0;
+
+ if ( num == 0 )
+ {
+ // EP0 has no endpoint control register because the buffer offsets are fixed
+ ep->endpoint_control = NULL;
+
+ // Buffer offset is fixed (also double buffered)
+ ep->hw_data_buf = (uint8_t*) &usb_dpram->ep0_buf_a[0];
+ }
+ else
+ {
+ // Set the endpoint control register (starts at EP1, hence num-1)
+ if ( dir == TUSB_DIR_IN )
+ {
+ ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].in;
+ }
+ else
+ {
+ ep->endpoint_control = &usb_dpram->ep_ctrl[num - 1].out;
+ }
+
+ // alloc a buffer and fill in endpoint control register
+ _hw_endpoint_alloc(ep, transfer_type);
+ }
+}
+
+static void hw_endpoint_xfer(uint8_t ep_addr, uint8_t *buffer, uint16_t total_bytes)
+{
+ struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+ hw_endpoint_xfer_start(ep, buffer, total_bytes);
+}
+
+static void hw_handle_buff_status(void)
+{
+ uint32_t remaining_buffers = usb_hw->buf_status;
+ pico_trace("buf_status = 0x%08x\n", remaining_buffers);
+ uint bit = 1u;
+ for (uint8_t i = 0; remaining_buffers && i < USB_MAX_ENDPOINTS * 2; i++)
+ {
+ if (remaining_buffers & bit)
+ {
+ // clear this in advance
+ usb_hw_clear->buf_status = bit;
+
+ // IN transfer for even i, OUT transfer for odd i
+ struct hw_endpoint *ep = hw_endpoint_get_by_num(i >> 1u, !(i & 1u));
+
+ // Continue xfer
+ bool done = hw_endpoint_xfer_continue(ep);
+ if (done)
+ {
+ // Notify
+ dcd_event_xfer_complete(0, ep->ep_addr, ep->xferred_len, XFER_RESULT_SUCCESS, true);
+ hw_endpoint_reset_transfer(ep);
+ }
+ remaining_buffers &= ~bit;
+ }
+ bit <<= 1u;
+ }
+}
+
+static void reset_ep0_pid(void)
+{
+ // If we have finished this transfer on EP0 set pid back to 1 for next
+ // setup transfer. Also clear a stall in case
+ uint8_t addrs[] = {0x0, 0x80};
+ for (uint i = 0 ; i < TU_ARRAY_SIZE(addrs); i++)
+ {
+ struct hw_endpoint *ep = hw_endpoint_get_by_addr(addrs[i]);
+ ep->next_pid = 1u;
+ }
+}
+
+static void reset_non_control_endpoints(void)
+{
+ // Disable all non-control
+ for ( uint8_t i = 0; i < USB_MAX_ENDPOINTS-1; i++ )
+ {
+ usb_dpram->ep_ctrl[i].in = 0;
+ usb_dpram->ep_ctrl[i].out = 0;
+ }
+
+ // clear non-control hw endpoints
+ tu_memclr(hw_endpoints[1], sizeof(hw_endpoints) - 2*sizeof(hw_endpoint_t));
+ next_buffer_ptr = &usb_dpram->epx_data[0];
+}
+
+static void dcd_rp2040_irq(void)
+{
+ uint32_t const status = usb_hw->ints;
+ uint32_t handled = 0;
+
+ if (status & USB_INTS_SETUP_REQ_BITS)
+ {
+ handled |= USB_INTS_SETUP_REQ_BITS;
+ uint8_t const *setup = (uint8_t const *)&usb_dpram->setup_packet;
+
+ // reset pid to both 1 (data and ack)
+ reset_ep0_pid();
+
+ // Pass setup packet to tiny usb
+ dcd_event_setup_received(0, setup, true);
+ usb_hw_clear->sie_status = USB_SIE_STATUS_SETUP_REC_BITS;
+ }
+
+ if (status & USB_INTS_BUFF_STATUS_BITS)
+ {
+ handled |= USB_INTS_BUFF_STATUS_BITS;
+ hw_handle_buff_status();
+ }
+
+#if FORCE_VBUS_DETECT == 0
+ // Since we force VBUS detect On, device will always think it is connected and
+ // couldn't distinguish between disconnect and suspend
+ if (status & USB_INTS_DEV_CONN_DIS_BITS)
+ {
+ handled |= USB_INTS_DEV_CONN_DIS_BITS;
+
+ if ( usb_hw->sie_status & USB_SIE_STATUS_CONNECTED_BITS )
+ {
+ // Connected: nothing to do
+ }else
+ {
+ // Disconnected
+ dcd_event_bus_signal(0, DCD_EVENT_UNPLUGGED, true);
+ }
+
+ usb_hw_clear->sie_status = USB_SIE_STATUS_CONNECTED_BITS;
+ }
+#endif
+
+ // SE0 for 2.5 us or more (will last at least 10ms)
+ if (status & USB_INTS_BUS_RESET_BITS)
+ {
+ pico_trace("BUS RESET\n");
+
+ handled |= USB_INTS_BUS_RESET_BITS;
+
+ usb_hw->dev_addr_ctrl = 0;
+ reset_non_control_endpoints();
+ dcd_event_bus_reset(0, TUSB_SPEED_FULL, true);
+ usb_hw_clear->sie_status = USB_SIE_STATUS_BUS_RESET_BITS;
+
+#if TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX
+ // Only run enumeration walk-around if pull up is enabled
+ if ( usb_hw->sie_ctrl & USB_SIE_CTRL_PULLUP_EN_BITS ) rp2040_usb_device_enumeration_fix();
+#endif
+ }
+
+ /* Note from pico datasheet 4.1.2.6.4 (v1.2)
+ * If you enable the suspend interrupt, it is likely you will see a suspend interrupt when
+ * the device is first connected but the bus is idle. The bus can be idle for a few ms before
+ * the host begins sending start of frame packets. You will also see a suspend interrupt
+ * when the device is disconnected if you do not have a VBUS detect circuit connected. This is
+ * because without VBUS detection, it is impossible to tell the difference between
+ * being disconnected and suspended.
+ */
+ if (status & USB_INTS_DEV_SUSPEND_BITS)
+ {
+ handled |= USB_INTS_DEV_SUSPEND_BITS;
+ dcd_event_bus_signal(0, DCD_EVENT_SUSPEND, true);
+ usb_hw_clear->sie_status = USB_SIE_STATUS_SUSPENDED_BITS;
+ }
+
+ if (status & USB_INTS_DEV_RESUME_FROM_HOST_BITS)
+ {
+ handled |= USB_INTS_DEV_RESUME_FROM_HOST_BITS;
+ dcd_event_bus_signal(0, DCD_EVENT_RESUME, true);
+ usb_hw_clear->sie_status = USB_SIE_STATUS_RESUME_BITS;
+ }
+
+ if (status ^ handled)
+ {
+ panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
+ }
+}
+
+#define USB_INTS_ERROR_BITS ( \
+ USB_INTS_ERROR_DATA_SEQ_BITS | \
+ USB_INTS_ERROR_BIT_STUFF_BITS | \
+ USB_INTS_ERROR_CRC_BITS | \
+ USB_INTS_ERROR_RX_OVERFLOW_BITS | \
+ USB_INTS_ERROR_RX_TIMEOUT_BITS)
+
+/*------------------------------------------------------------------*/
+/* Controller API
+ *------------------------------------------------------------------*/
+
+void dcd_init (uint8_t rhport)
+{
+ assert(rhport == 0);
+
+ // Reset hardware to default state
+ rp2040_usb_init();
+
+#if FORCE_VBUS_DETECT
+ // Force VBUS detect so the device thinks it is plugged into a host
+ usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+#endif
+
+ irq_set_exclusive_handler(USBCTRL_IRQ, dcd_rp2040_irq);
+
+ // Init control endpoints
+ tu_memclr(hw_endpoints[0], 2*sizeof(hw_endpoint_t));
+ hw_endpoint_init(0x0, 64, TUSB_XFER_CONTROL);
+ hw_endpoint_init(0x80, 64, TUSB_XFER_CONTROL);
+
+ // Init non-control endpoints
+ reset_non_control_endpoints();
+
+ // Initializes the USB peripheral for device mode and enables it.
+ // Don't need to enable the pull up here. Force VBUS
+ usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS;
+
+ // Enable individual controller IRQS here. Processor interrupt enable will be used
+ // for the global interrupt enable...
+ // Note: Force VBUS detect cause disconnection not detectable
+ usb_hw->sie_ctrl = USB_SIE_CTRL_EP0_INT_1BUF_BITS;
+ usb_hw->inte = USB_INTS_BUFF_STATUS_BITS | USB_INTS_BUS_RESET_BITS | USB_INTS_SETUP_REQ_BITS |
+ USB_INTS_DEV_SUSPEND_BITS | USB_INTS_DEV_RESUME_FROM_HOST_BITS |
+ (FORCE_VBUS_DETECT ? 0 : USB_INTS_DEV_CONN_DIS_BITS);
+
+ dcd_connect(rhport);
+}
+
+void dcd_int_enable(__unused uint8_t rhport)
+{
+ assert(rhport == 0);
+ irq_set_enabled(USBCTRL_IRQ, true);
+}
+
+void dcd_int_disable(__unused uint8_t rhport)
+{
+ assert(rhport == 0);
+ irq_set_enabled(USBCTRL_IRQ, false);
+}
+
+void dcd_set_address (__unused uint8_t rhport, __unused uint8_t dev_addr)
+{
+ assert(rhport == 0);
+
+ // Can't set device address in hardware until status xfer has complete
+ // Send 0len complete response on EP0 IN
+ hw_endpoint_xfer(0x80, NULL, 0);
+}
+
+void dcd_remote_wakeup(__unused uint8_t rhport)
+{
+ pico_info("dcd_remote_wakeup %d\n", rhport);
+ assert(rhport == 0);
+ usb_hw_set->sie_ctrl = USB_SIE_CTRL_RESUME_BITS;
+}
+
+// disconnect by disabling internal pull-up resistor on D+/D-
+void dcd_disconnect(__unused uint8_t rhport)
+{
+ (void) rhport;
+ usb_hw_clear->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
+}
+
+// connect by enabling internal pull-up resistor on D+/D-
+void dcd_connect(__unused uint8_t rhport)
+{
+ (void) rhport;
+ usb_hw_set->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
+}
+
+/*------------------------------------------------------------------*/
+/* DCD Endpoint port
+ *------------------------------------------------------------------*/
+
+void dcd_edpt0_status_complete(uint8_t rhport, tusb_control_request_t const * request)
+{
+ (void) rhport;
+
+ if ( request->bmRequestType_bit.recipient == TUSB_REQ_RCPT_DEVICE &&
+ request->bmRequestType_bit.type == TUSB_REQ_TYPE_STANDARD &&
+ request->bRequest == TUSB_REQ_SET_ADDRESS )
+ {
+ usb_hw->dev_addr_ctrl = (uint8_t) request->wValue;
+ }
+}
+
+bool dcd_edpt_open (__unused uint8_t rhport, tusb_desc_endpoint_t const * desc_edpt)
+{
+ assert(rhport == 0);
+ hw_endpoint_init(desc_edpt->bEndpointAddress, desc_edpt->wMaxPacketSize.size, desc_edpt->bmAttributes.xfer);
+ return true;
+}
+
+void dcd_edpt_close_all (uint8_t rhport)
+{
+ (void) rhport;
+
+ // may need to use EP Abort
+ reset_non_control_endpoints();
+}
+
+bool dcd_edpt_xfer(__unused uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+ assert(rhport == 0);
+ hw_endpoint_xfer(ep_addr, buffer, total_bytes);
+ return true;
+}
+
+void dcd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+
+ if ( tu_edpt_number(ep_addr) == 0 )
+ {
+ // A stall on EP0 has to be armed so it can be cleared on the next setup packet
+ usb_hw_set->ep_stall_arm = (tu_edpt_dir(ep_addr) == TUSB_DIR_IN) ? USB_EP_STALL_ARM_EP0_IN_BITS : USB_EP_STALL_ARM_EP0_OUT_BITS;
+ }
+
+ struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+
+ // stall and clear current pending buffer
+ // may need to use EP_ABORT
+ _hw_endpoint_buffer_control_set_value32(ep, USB_BUF_CTRL_STALL);
+}
+
+void dcd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+
+ if (tu_edpt_number(ep_addr))
+ {
+ struct hw_endpoint *ep = hw_endpoint_get_by_addr(ep_addr);
+
+ // clear stall also reset toggle to DATA0, ready for next transfer
+ ep->next_pid = 0;
+ _hw_endpoint_buffer_control_clear_mask32(ep, USB_BUF_CTRL_STALL);
+ }
+}
+
+void dcd_edpt_close (uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+ (void) ep_addr;
+
+ // usbd.c says: In progress transfers on this EP may be delivered after this call
+ pico_trace("dcd_edpt_close %02x\n", ep_addr);
+}
+
+void dcd_int_handler(uint8_t rhport)
+{
+ (void) rhport;
+ dcd_rp2040_irq();
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/hcd_rp2040.c b/arkanoid/pico/tinyusb/hcd_rp2040.c
new file mode 100644
index 0000000..07d0a43
--- /dev/null
+++ b/arkanoid/pico/tinyusb/hcd_rp2040.c
@@ -0,0 +1,563 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Double Buffered
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_HOST_ENABLED && CFG_TUSB_MCU == OPT_MCU_RP2040
+
+#include "../pico.h"
+#include "rp2040_usb.h"
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "osal.h"
+
+#include "hcd.h"
+#include "usbh.h"
+
+#define ROOT_PORT 0
+
+//--------------------------------------------------------------------+
+// Low level rp2040 controller functions
+//--------------------------------------------------------------------+
+
+#ifndef PICO_USB_HOST_INTERRUPT_ENDPOINTS
+#define PICO_USB_HOST_INTERRUPT_ENDPOINTS (USB_MAX_ENDPOINTS - 1)
+#endif
+static_assert(PICO_USB_HOST_INTERRUPT_ENDPOINTS <= USB_MAX_ENDPOINTS, "");
+
+// Host mode uses one shared endpoint register for non-interrupt endpoint
+static struct hw_endpoint ep_pool[1 + PICO_USB_HOST_INTERRUPT_ENDPOINTS];
+#define epx (ep_pool[0])
+
+#define usb_hw_set hw_set_alias(usb_hw)
+#define usb_hw_clear hw_clear_alias(usb_hw)
+
+// Flags we set by default in sie_ctrl (we add other bits on top)
+enum {
+ SIE_CTRL_BASE = USB_SIE_CTRL_SOF_EN_BITS | USB_SIE_CTRL_KEEP_ALIVE_EN_BITS |
+ USB_SIE_CTRL_PULLDOWN_EN_BITS | USB_SIE_CTRL_EP0_INT_1BUF_BITS
+};
+
+static struct hw_endpoint *get_dev_ep(uint8_t dev_addr, uint8_t ep_addr)
+{
+ uint8_t num = tu_edpt_number(ep_addr);
+ if ( num == 0 ) return &epx;
+
+ for ( uint32_t i = 1; i < TU_ARRAY_SIZE(ep_pool); i++ )
+ {
+ struct hw_endpoint *ep = &ep_pool[i];
+ if ( ep->configured && (ep->dev_addr == dev_addr) && (ep->ep_addr == ep_addr) ) return ep;
+ }
+
+ return NULL;
+}
+
+static inline uint8_t dev_speed(void)
+{
+ return (usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS) >> USB_SIE_STATUS_SPEED_LSB;
+}
+
+static bool need_pre(uint8_t dev_addr)
+{
+ // If this device is different to the speed of the root device
+ // (i.e. is a low speed device on a full speed hub) then need pre
+ return hcd_port_speed_get(0) != tuh_speed_get(dev_addr);
+}
+
+static void hw_xfer_complete(struct hw_endpoint *ep, xfer_result_t xfer_result)
+{
+ // Mark transfer as done before we tell the tinyusb stack
+ uint8_t dev_addr = ep->dev_addr;
+ uint8_t ep_addr = ep->ep_addr;
+ uint xferred_len = ep->xferred_len;
+ hw_endpoint_reset_transfer(ep);
+ hcd_event_xfer_complete(dev_addr, ep_addr, xferred_len, xfer_result, true);
+}
+
+static void _handle_buff_status_bit(uint bit, struct hw_endpoint *ep)
+{
+ usb_hw_clear->buf_status = bit;
+ bool done = hw_endpoint_xfer_continue(ep);
+ if (done)
+ {
+ hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
+ }
+}
+
+static void hw_handle_buff_status(void)
+{
+ uint32_t remaining_buffers = usb_hw->buf_status;
+ pico_trace("buf_status 0x%08x\n", remaining_buffers);
+
+ // Check EPX first
+ uint bit = 0b1;
+ if (remaining_buffers & bit)
+ {
+ remaining_buffers &= ~bit;
+ struct hw_endpoint *ep = &epx;
+
+ uint32_t ep_ctrl = *ep->endpoint_control;
+ if (ep_ctrl & EP_CTRL_DOUBLE_BUFFERED_BITS)
+ {
+ TU_LOG(3, "Double Buffered: ");
+ }else
+ {
+ TU_LOG(3, "Single Buffered: ");
+ }
+ TU_LOG_HEX(3, ep_ctrl);
+
+ _handle_buff_status_bit(bit, ep);
+ }
+
+ // Check interrupt endpoints
+ for (uint i = 1; i <= USB_HOST_INTERRUPT_ENDPOINTS && remaining_buffers; i++)
+ {
+ // EPX is bit 0
+ // IEP1 is bit 2
+ // IEP2 is bit 4
+ // IEP3 is bit 6
+ // etc
+ bit = 1 << (i*2);
+
+ if (remaining_buffers & bit)
+ {
+ remaining_buffers &= ~bit;
+ _handle_buff_status_bit(bit, &ep_pool[i]);
+ }
+ }
+
+ if (remaining_buffers)
+ {
+ panic("Unhandled buffer %d\n", remaining_buffers);
+ }
+}
+
+static void hw_trans_complete(void)
+{
+ struct hw_endpoint *ep = &epx;
+ assert(ep->active);
+
+ if (usb_hw->sie_ctrl & USB_SIE_CTRL_SEND_SETUP_BITS)
+ {
+ pico_trace("Sent setup packet\n");
+ hw_xfer_complete(ep, XFER_RESULT_SUCCESS);
+ }
+ else
+ {
+ // Don't care. Will handle this in buff status
+ return;
+ }
+}
+
+static void hcd_rp2040_irq(void)
+{
+ uint32_t status = usb_hw->ints;
+ uint32_t handled = 0;
+
+ if (status & USB_INTS_HOST_CONN_DIS_BITS)
+ {
+ handled |= USB_INTS_HOST_CONN_DIS_BITS;
+
+ if (dev_speed())
+ {
+ hcd_event_device_attach(ROOT_PORT, true);
+ }
+ else
+ {
+ hcd_event_device_remove(ROOT_PORT, true);
+ }
+
+ // Clear speed change interrupt
+ usb_hw_clear->sie_status = USB_SIE_STATUS_SPEED_BITS;
+ }
+
+ if (status & USB_INTS_BUFF_STATUS_BITS)
+ {
+ handled |= USB_INTS_BUFF_STATUS_BITS;
+ TU_LOG(2, "Buffer complete\n");
+ hw_handle_buff_status();
+ }
+
+ if (status & USB_INTS_TRANS_COMPLETE_BITS)
+ {
+ handled |= USB_INTS_TRANS_COMPLETE_BITS;
+ usb_hw_clear->sie_status = USB_SIE_STATUS_TRANS_COMPLETE_BITS;
+ TU_LOG(2, "Transfer complete\n");
+ hw_trans_complete();
+ }
+
+ if (status & USB_INTS_STALL_BITS)
+ {
+ // We have rx'd a stall from the device
+ pico_trace("Stall REC\n");
+ handled |= USB_INTS_STALL_BITS;
+ usb_hw_clear->sie_status = USB_SIE_STATUS_STALL_REC_BITS;
+ hw_xfer_complete(&epx, XFER_RESULT_STALLED);
+ }
+
+ if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS)
+ {
+ handled |= USB_INTS_ERROR_RX_TIMEOUT_BITS;
+ usb_hw_clear->sie_status = USB_SIE_STATUS_RX_TIMEOUT_BITS;
+ }
+
+ if (status & USB_INTS_ERROR_DATA_SEQ_BITS)
+ {
+ usb_hw_clear->sie_status = USB_SIE_STATUS_DATA_SEQ_ERROR_BITS;
+ TU_LOG(3, " Seq Error: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(*epx.buffer_control), tu_u32_high16(*epx.buffer_control));
+ panic("Data Seq Error \n");
+ }
+
+ if (status ^ handled)
+ {
+ panic("Unhandled IRQ 0x%x\n", (uint) (status ^ handled));
+ }
+}
+
+static struct hw_endpoint *_next_free_interrupt_ep(void)
+{
+ struct hw_endpoint *ep = NULL;
+ for (uint i = 1; i < TU_ARRAY_SIZE(ep_pool); i++)
+ {
+ ep = &ep_pool[i];
+ if (!ep->configured)
+ {
+ // Will be configured by _hw_endpoint_init / _hw_endpoint_allocate
+ ep->interrupt_num = i - 1;
+ return ep;
+ }
+ }
+ return ep;
+}
+
+static struct hw_endpoint *_hw_endpoint_allocate(uint8_t transfer_type)
+{
+ struct hw_endpoint *ep = NULL;
+
+ if (transfer_type == TUSB_XFER_INTERRUPT)
+ {
+ ep = _next_free_interrupt_ep();
+ pico_info("Allocate interrupt ep %d\n", ep->interrupt_num);
+ assert(ep);
+ ep->buffer_control = &usbh_dpram->int_ep_buffer_ctrl[ep->interrupt_num].ctrl;
+ ep->endpoint_control = &usbh_dpram->int_ep_ctrl[ep->interrupt_num].ctrl;
+ // 0 for epx (double buffered): TODO increase to 1024 for ISO
+ // 2x64 for intep0
+ // 3x64 for intep1
+ // etc
+ ep->hw_data_buf = &usbh_dpram->epx_data[64 * (ep->interrupt_num + 2)];
+ }
+ else
+ {
+ ep = &epx;
+ ep->buffer_control = &usbh_dpram->epx_buf_ctrl;
+ ep->endpoint_control = &usbh_dpram->epx_ctrl;
+ ep->hw_data_buf = &usbh_dpram->epx_data[0];
+ }
+
+ return ep;
+}
+
+static void _hw_endpoint_init(struct hw_endpoint *ep, uint8_t dev_addr, uint8_t ep_addr, uint wMaxPacketSize, uint8_t transfer_type, uint8_t bmInterval)
+{
+ // Already has data buffer, endpoint control, and buffer control allocated at this point
+ assert(ep->endpoint_control);
+ assert(ep->buffer_control);
+ assert(ep->hw_data_buf);
+
+ uint8_t const num = tu_edpt_number(ep_addr);
+ tusb_dir_t const dir = tu_edpt_dir(ep_addr);
+
+ ep->ep_addr = ep_addr;
+ ep->dev_addr = dev_addr;
+
+ // For host, IN to host == RX, anything else rx == false
+ ep->rx = (dir == TUSB_DIR_IN);
+
+ // Response to a setup packet on EP0 starts with pid of 1
+ ep->next_pid = (num == 0 ? 1u : 0u);
+ ep->wMaxPacketSize = wMaxPacketSize;
+ ep->transfer_type = transfer_type;
+
+ pico_trace("hw_endpoint_init dev %d ep %d %s xfer %d\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->transfer_type);
+ pico_trace("dev %d ep %d %s setup buffer @ 0x%p\n", ep->dev_addr, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)], ep->hw_data_buf);
+ uint dpram_offset = hw_data_offset(ep->hw_data_buf);
+ // Bits 0-5 should be 0
+ assert(!(dpram_offset & 0b111111));
+
+ // Fill in endpoint control register with buffer offset
+ uint32_t ep_reg = EP_CTRL_ENABLE_BITS
+ | EP_CTRL_INTERRUPT_PER_BUFFER
+ | (ep->transfer_type << EP_CTRL_BUFFER_TYPE_LSB)
+ | dpram_offset;
+ ep_reg |= bmInterval ? (bmInterval - 1) << EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB : 0;
+ *ep->endpoint_control = ep_reg;
+ pico_trace("endpoint control (0x%p) <- 0x%x\n", ep->endpoint_control, ep_reg);
+ ep->configured = true;
+
+ if (bmInterval)
+ {
+ // This is an interrupt endpoint
+ // so need to set up interrupt endpoint address control register with:
+ // device address
+ // endpoint number / direction
+ // preamble
+ uint32_t reg = dev_addr | (num << USB_ADDR_ENDP1_ENDPOINT_LSB);
+ // Assert the interrupt endpoint is IN_TO_HOST
+ // TODO Interrupt can also be OUT
+ assert(dir == TUSB_DIR_IN);
+
+ if (need_pre(dev_addr))
+ {
+ reg |= USB_ADDR_ENDP1_INTEP_PREAMBLE_BITS;
+ }
+ usb_hw->int_ep_addr_ctrl[ep->interrupt_num] = reg;
+
+ // Finally, enable interrupt that endpoint
+ usb_hw_set->int_ep_ctrl = 1 << (ep->interrupt_num + 1);
+
+ // If it's an interrupt endpoint we need to set up the buffer control
+ // register
+ }
+}
+
+//--------------------------------------------------------------------+
+// HCD API
+//--------------------------------------------------------------------+
+bool hcd_init(uint8_t rhport)
+{
+ pico_trace("hcd_init %d\n", rhport);
+ assert(rhport == 0);
+
+ // Reset any previous state
+ rp2040_usb_init();
+
+ // Force VBUS detect to always present, for now we assume vbus is always provided (without using VBUS En)
+ usb_hw->pwr = USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS;
+
+ irq_set_exclusive_handler(USBCTRL_IRQ, hcd_rp2040_irq);
+
+ // clear epx and interrupt eps
+ memset(&ep_pool, 0, sizeof(ep_pool));
+
+ // Enable in host mode with SOF / Keep alive on
+ usb_hw->main_ctrl = USB_MAIN_CTRL_CONTROLLER_EN_BITS | USB_MAIN_CTRL_HOST_NDEVICE_BITS;
+ usb_hw->sie_ctrl = SIE_CTRL_BASE;
+ usb_hw->inte = USB_INTE_BUFF_STATUS_BITS |
+ USB_INTE_HOST_CONN_DIS_BITS |
+ USB_INTE_HOST_RESUME_BITS |
+ USB_INTE_STALL_BITS |
+ USB_INTE_TRANS_COMPLETE_BITS |
+ USB_INTE_ERROR_RX_TIMEOUT_BITS |
+ USB_INTE_ERROR_DATA_SEQ_BITS ;
+
+ return true;
+}
+
+void hcd_port_reset(uint8_t rhport)
+{
+ pico_trace("hcd_port_reset\n");
+ assert(rhport == 0);
+ // TODO: Nothing to do here yet. Perhaps need to reset some state?
+}
+
+bool hcd_port_connect_status(uint8_t rhport)
+{
+ pico_trace("hcd_port_connect_status\n");
+ assert(rhport == 0);
+ return usb_hw->sie_status & USB_SIE_STATUS_SPEED_BITS;
+}
+
+tusb_speed_t hcd_port_speed_get(uint8_t rhport)
+{
+ assert(rhport == 0);
+ // TODO: Should enumval this register
+ switch (dev_speed())
+ {
+ case 1:
+ return TUSB_SPEED_LOW;
+ case 2:
+ return TUSB_SPEED_FULL;
+ default:
+ panic("Invalid speed\n");
+ return TUSB_SPEED_INVALID;
+ }
+}
+
+// Close all opened endpoint belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr)
+{
+ (void) rhport;
+ (void) dev_addr;
+
+ pico_trace("hcd_device_close %d\n", dev_addr);
+}
+
+uint32_t hcd_frame_number(uint8_t rhport)
+{
+ (void) rhport;
+ return usb_hw->sof_rd;
+}
+
+void hcd_int_enable(uint8_t rhport)
+{
+ assert(rhport == 0);
+ irq_set_enabled(USBCTRL_IRQ, true);
+}
+
+void hcd_int_disable(uint8_t rhport)
+{
+ // todo we should check this is disabling from the correct core; note currently this is never called
+ assert(rhport == 0);
+ irq_set_enabled(USBCTRL_IRQ, false);
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc)
+{
+ (void) rhport;
+
+ pico_trace("hcd_edpt_open dev_addr %d, ep_addr %d\n", dev_addr, ep_desc->bEndpointAddress);
+
+ // Allocated differently based on if it's an interrupt endpoint or not
+ struct hw_endpoint *ep = _hw_endpoint_allocate(ep_desc->bmAttributes.xfer);
+
+ _hw_endpoint_init(ep,
+ dev_addr,
+ ep_desc->bEndpointAddress,
+ ep_desc->wMaxPacketSize.size,
+ ep_desc->bmAttributes.xfer,
+ ep_desc->bInterval);
+
+ return true;
+}
+
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen)
+{
+ (void) rhport;
+
+ pico_trace("hcd_edpt_xfer dev_addr %d, ep_addr 0x%x, len %d\n", dev_addr, ep_addr, buflen);
+
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ tusb_dir_t const ep_dir = tu_edpt_dir(ep_addr);
+
+ // Get appropriate ep. Either EPX or interrupt endpoint
+ struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
+ assert(ep);
+
+ // Control endpoint can change direction 0x00 <-> 0x80
+ if ( ep_addr != ep->ep_addr )
+ {
+ assert(ep_num == 0);
+
+ // Direction has flipped on endpoint control so re init it but with same properties
+ _hw_endpoint_init(ep, dev_addr, ep_addr, ep->wMaxPacketSize, ep->transfer_type, 0);
+ }
+
+ // If a normal transfer (non-interrupt) then initiate using
+ // sie ctrl registers. Otherwise interrupt ep registers should
+ // already be configured
+ if (ep == &epx) {
+ hw_endpoint_xfer_start(ep, buffer, buflen);
+
+ // That has set up buffer control, endpoint control etc
+ // for host we have to initiate the transfer
+ usb_hw->dev_addr_ctrl = dev_addr | (ep_num << USB_ADDR_ENDP_ENDPOINT_LSB);
+
+ uint32_t flags = USB_SIE_CTRL_START_TRANS_BITS | SIE_CTRL_BASE |
+ (ep_dir ? USB_SIE_CTRL_RECEIVE_DATA_BITS : USB_SIE_CTRL_SEND_DATA_BITS);
+ // Set pre if we are a low speed device on full speed hub
+ flags |= need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0;
+
+ usb_hw->sie_ctrl = flags;
+ }else
+ {
+ hw_endpoint_xfer_start(ep, buffer, buflen);
+ }
+
+ return true;
+}
+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8])
+{
+ (void) rhport;
+
+ // Copy data into setup packet buffer
+ memcpy((void*)&usbh_dpram->setup_packet[0], setup_packet, 8);
+
+ // Configure EP0 struct with setup info for the trans complete
+ struct hw_endpoint *ep = _hw_endpoint_allocate(0);
+
+ // EP0 out
+ _hw_endpoint_init(ep, dev_addr, 0x00, ep->wMaxPacketSize, 0, 0);
+ assert(ep->configured);
+
+ ep->remaining_len = 8;
+ ep->active = true;
+
+ // Set device address
+ usb_hw->dev_addr_ctrl = dev_addr;
+
+ // Set pre if we are a low speed device on full speed hub
+ uint32_t const flags = SIE_CTRL_BASE | USB_SIE_CTRL_SEND_SETUP_BITS | USB_SIE_CTRL_START_TRANS_BITS |
+ (need_pre(dev_addr) ? USB_SIE_CTRL_PREAMBLE_EN_BITS : 0);
+
+ usb_hw->sie_ctrl = flags;
+
+ return true;
+}
+
+
+//bool hcd_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+//{
+// // EPX is shared, so multiple device addresses and endpoint addresses share that
+// // so if any transfer is active on epx, we are busy. Interrupt endpoints have their own
+// // EPX so ep->active will only be busy if there is a pending transfer on that interrupt endpoint
+// // on that device
+// pico_trace("hcd_edpt_busy dev addr %d ep_addr 0x%x\n", dev_addr, ep_addr);
+// struct hw_endpoint *ep = get_dev_ep(dev_addr, ep_addr);
+// assert(ep);
+// bool busy = ep->active;
+// pico_trace("busy == %d\n", busy);
+// return busy;
+//}
+
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr)
+{
+ (void) dev_addr;
+ (void) ep_addr;
+
+ panic("hcd_clear_stall");
+ return true;
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/host/hcd.h b/arkanoid/pico/tinyusb/host/hcd.h
new file mode 100644
index 0000000..eebdfad
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/hcd.h
@@ -0,0 +1,179 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_HCD_H_
+#define _TUSB_HCD_H_
+
+#include "../tusb_common.h"
+#include "../osal.h"
+#include "../tusb_fifo.h"
+#include "hcd_attr.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+ //--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+typedef enum
+{
+ HCD_EVENT_DEVICE_ATTACH,
+ HCD_EVENT_DEVICE_REMOVE,
+ HCD_EVENT_XFER_COMPLETE,
+
+ // Not an HCD event, just a convenient way to defer ISR function
+ USBH_EVENT_FUNC_CALL,
+
+ HCD_EVENT_COUNT
+} hcd_eventid_t;
+
+typedef struct
+{
+ uint8_t rhport;
+ uint8_t event_id;
+ uint8_t dev_addr;
+
+ union
+ {
+ // Attach, Remove
+ struct {
+ uint8_t hub_addr;
+ uint8_t hub_port;
+ uint8_t speed;
+ } connection;
+
+ // XFER_COMPLETE
+ struct {
+ uint8_t ep_addr;
+ uint8_t result;
+ uint32_t len;
+ } xfer_complete;
+
+ // FUNC_CALL
+ struct {
+ void (*func) (void*);
+ void* param;
+ }func_call;
+ };
+
+} hcd_event_t;
+
+#if TUSB_OPT_HOST_ENABLED
+// Max number of endpoints per device
+enum {
+ // TODO better computation
+ HCD_MAX_ENDPOINT = CFG_TUH_DEVICE_MAX*(CFG_TUH_HUB + CFG_TUH_HID*2 + CFG_TUH_MSC*2 + CFG_TUH_CDC*3),
+ HCD_MAX_XFER = HCD_MAX_ENDPOINT*2,
+};
+
+//#define HCD_MAX_ENDPOINT 16
+//#define HCD_MAX_XFER 16
+
+typedef struct {
+ uint8_t rhport;
+ uint8_t hub_addr;
+ uint8_t hub_port;
+ uint8_t speed;
+} hcd_devtree_info_t;
+
+#endif
+
+//--------------------------------------------------------------------+
+// Controller API
+//--------------------------------------------------------------------+
+
+// Initialize controller to host mode
+bool hcd_init(uint8_t rhport);
+
+// Interrupt Handler
+void hcd_int_handler(uint8_t rhport);
+
+// Enable USB interrupt
+void hcd_int_enable (uint8_t rhport);
+
+// Disable USB interrupt
+void hcd_int_disable(uint8_t rhport);
+
+// Get frame number (1ms)
+uint32_t hcd_frame_number(uint8_t rhport);
+
+//--------------------------------------------------------------------+
+// Port API
+//--------------------------------------------------------------------+
+
+// Get the current connect status of roothub port
+bool hcd_port_connect_status(uint8_t rhport);
+
+// Reset USB bus on the port
+void hcd_port_reset(uint8_t rhport);
+
+// TODO implement later
+void hcd_port_reset_end(uint8_t rhport);
+
+// Get port link speed
+tusb_speed_t hcd_port_speed_get(uint8_t rhport);
+
+// HCD closes all opened endpoints belong to this device
+void hcd_device_close(uint8_t rhport, uint8_t dev_addr);
+
+//--------------------------------------------------------------------+
+// Endpoints API
+//--------------------------------------------------------------------+
+
+bool hcd_setup_send(uint8_t rhport, uint8_t dev_addr, uint8_t const setup_packet[8]);
+bool hcd_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * ep_desc);
+bool hcd_edpt_xfer(uint8_t rhport, uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t buflen);
+bool hcd_edpt_clear_stall(uint8_t dev_addr, uint8_t ep_addr);
+
+//--------------------------------------------------------------------+
+// USBH implemented API
+//--------------------------------------------------------------------+
+
+// Get device tree information of a device
+// USB device tree can be complicated and manged by USBH, this help HCD to retrieve
+// needed topology info to carry out its work
+extern void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info);
+
+//------------- Event API -------------//
+
+// Called by HCD to notify stack
+extern void hcd_event_handler(hcd_event_t const* event, bool in_isr);
+
+// Helper to send device attach event
+extern void hcd_event_device_attach(uint8_t rhport, bool in_isr);
+
+// Helper to send device removal event
+extern void hcd_event_device_remove(uint8_t rhport, bool in_isr);
+
+// Helper to send USB transfer event
+extern void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_HCD_H_ */
diff --git a/arkanoid/pico/tinyusb/host/hcd_attr.h b/arkanoid/pico/tinyusb/host/hcd_attr.h
new file mode 100644
index 0000000..56619e5
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/hcd_attr.h
@@ -0,0 +1,105 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef TUSB_HCD_ATTR_H_
+#define TUSB_HCD_ATTR_H_
+
+#include "../tusb_option.h"
+
+// Attribute includes
+// - ENDPOINT_MAX: max (logical) number of endpoint
+// - PORT_HIGHSPEED: mask to indicate which port support highspeed mode, bit0 for port0 and so on.
+
+//------------- NXP -------------//
+#if TU_CHECK_MCU(LPC175X_6X) || TU_CHECK_MCU(LPC177X_8X) || TU_CHECK_MCU(LPC40XX)
+ #define HCD_ATTR_OHCI
+
+#elif TU_CHECK_MCU(LPC18XX) || TU_CHECK_MCU(LPC43XX)
+ #define HCD_ATTR_EHCI_TRANSDIMENSION
+
+#elif TU_CHECK_MCU(LPC54XXX)
+ // #define HCD_ATTR_EHCI_NXP_PTD
+
+#elif TU_CHECK_MCU(LPC55XX)
+ // #define HCD_ATTR_EHCI_NXP_PTD
+
+#elif TU_CHECK_MCU(MIMXRT10XX)
+ #define HCD_ATTR_EHCI_TRANSDIMENSION
+
+#elif TU_CHECK_MCU(MKL25ZXX)
+
+//------------- Microchip -------------//
+#elif TU_CHECK_MCU(SAMD21) || TU_CHECK_MCU(SAMD51) || TU_CHECK_MCU(SAME5X) || \
+ TU_CHECK_MCU(SAMD11) || TU_CHECK_MCU(SAML21) || TU_CHECK_MCU(SAML22)
+
+#elif TU_CHECK_MCU(SAMG)
+
+#elif TU_CHECK_MCU(SAMX7X)
+
+//------------- ST -------------//
+#elif TU_CHECK_MCU(STM32F0) || TU_CHECK_MCU(STM32F1) || TU_CHECK_MCU(STM32F3) || \
+ TU_CHECK_MCU(STM32L0) || TU_CHECK_MCU(STM32L1) || TU_CHECK_MCU(STM32L4)
+
+#elif TU_CHECK_MCU(STM32F2) || TU_CHECK_MCU(STM32F4) || TU_CHECK_MCU(STM32F3)
+
+#elif TU_CHECK_MCU(STM32F7)
+
+#elif TU_CHECK_MCU(STM32H7)
+
+//------------- Sony -------------//
+#elif TU_CHECK_MCU(CXD56)
+
+//------------- Nuvoton -------------//
+#elif TU_CHECK_MCU(NUC505)
+
+//------------- Espressif -------------//
+#elif TU_CHECK_MCU(ESP32S2) || TU_CHECK_MCU(ESP32S3)
+
+//------------- Raspberry Pi -------------//
+#elif TU_CHECK_MCU(RP2040)
+
+//------------- Silabs -------------//
+#elif TU_CHECK_MCU(EFM32GG) || TU_CHECK_MCU(EFM32GG11) || TU_CHECK_MCU(EFM32GG12)
+
+//------------- Renesas -------------//
+#elif TU_CHECK_MCU(RX63X) || TU_CHECK_MCU(RX65X) || TU_CHECK_MCU(RX72N)
+
+//#elif TU_CHECK_MCU(MM32F327X)
+// #define DCD_ATTR_ENDPOINT_MAX not known yet
+
+//------------- GigaDevice -------------//
+#elif TU_CHECK_MCU(GD32VF103)
+
+#else
+// #warning "DCD_ATTR_ENDPOINT_MAX is not defined for this MCU, default to 8"
+#endif
+
+// Default to fullspeed if not defined
+//#ifndef PORT_HIGHSPEED
+// #define DCD_ATTR_PORT_HIGHSPEED 0x00
+//#endif
+
+#endif
diff --git a/arkanoid/pico/tinyusb/host/hub.c b/arkanoid/pico/tinyusb/host/hub.c
new file mode 100644
index 0000000..a56cad0
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/hub.c
@@ -0,0 +1,388 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../tusb_option.h"
+
+#if (TUSB_OPT_HOST_ENABLED && CFG_TUH_HUB)
+
+#include "usbh.h"
+#include "usbh_classdriver.h"
+#include "hub.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+typedef struct
+{
+ uint8_t itf_num;
+ uint8_t ep_in;
+ uint8_t port_count;
+ uint8_t status_change; // data from status change interrupt endpoint
+
+ hub_port_status_response_t port_status;
+} hub_interface_t;
+
+CFG_TUSB_MEM_SECTION static hub_interface_t hub_data[CFG_TUH_HUB];
+CFG_TUSB_MEM_SECTION TU_ATTR_ALIGNED(4) static uint8_t _hub_buffer[sizeof(descriptor_hub_desc_t)];
+
+TU_ATTR_ALWAYS_INLINE
+static inline hub_interface_t* get_itf(uint8_t dev_addr)
+{
+ return &hub_data[dev_addr-1-CFG_TUH_DEVICE_MAX];
+}
+
+#if CFG_TUSB_DEBUG
+static char const* const _hub_feature_str[] =
+{
+ [HUB_FEATURE_PORT_CONNECTION ] = "PORT_CONNECTION",
+ [HUB_FEATURE_PORT_ENABLE ] = "PORT_ENABLE",
+ [HUB_FEATURE_PORT_SUSPEND ] = "PORT_SUSPEND",
+ [HUB_FEATURE_PORT_OVER_CURRENT ] = "PORT_OVER_CURRENT",
+ [HUB_FEATURE_PORT_RESET ] = "PORT_RESET",
+ [HUB_FEATURE_PORT_POWER ] = "PORT_POWER",
+ [HUB_FEATURE_PORT_LOW_SPEED ] = "PORT_LOW_SPEED",
+ [HUB_FEATURE_PORT_CONNECTION_CHANGE ] = "PORT_CONNECTION_CHANGE",
+ [HUB_FEATURE_PORT_ENABLE_CHANGE ] = "PORT_ENABLE_CHANGE",
+ [HUB_FEATURE_PORT_SUSPEND_CHANGE ] = "PORT_SUSPEND_CHANGE",
+ [HUB_FEATURE_PORT_OVER_CURRENT_CHANGE ] = "PORT_OVER_CURRENT_CHANGE",
+ [HUB_FEATURE_PORT_RESET_CHANGE ] = "PORT_RESET_CHANGE",
+ [HUB_FEATURE_PORT_TEST ] = "PORT_TEST",
+ [HUB_FEATURE_PORT_INDICATOR ] = "PORT_INDICATOR",
+};
+#endif
+
+//--------------------------------------------------------------------+
+// HUB
+//--------------------------------------------------------------------+
+bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb)
+{
+ tusb_control_request_t const request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_OTHER,
+ .type = TUSB_REQ_TYPE_CLASS,
+ .direction = TUSB_DIR_OUT
+ },
+ .bRequest = HUB_REQUEST_CLEAR_FEATURE,
+ .wValue = feature,
+ .wIndex = hub_port,
+ .wLength = 0
+ };
+
+ TU_LOG2("HUB Clear Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
+ TU_ASSERT( tuh_control_xfer(hub_addr, &request, NULL, complete_cb) );
+ return true;
+}
+
+bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb)
+{
+ tusb_control_request_t const request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_OTHER,
+ .type = TUSB_REQ_TYPE_CLASS,
+ .direction = TUSB_DIR_OUT
+ },
+ .bRequest = HUB_REQUEST_SET_FEATURE,
+ .wValue = feature,
+ .wIndex = hub_port,
+ .wLength = 0
+ };
+
+ TU_LOG2("HUB Set Feature: %s, addr = %u port = %u\r\n", _hub_feature_str[feature], hub_addr, hub_port);
+ TU_ASSERT( tuh_control_xfer(hub_addr, &request, NULL, complete_cb) );
+ return true;
+}
+
+bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb)
+{
+ return hub_port_set_feature(hub_addr, hub_port, HUB_FEATURE_PORT_RESET, complete_cb);
+}
+
+bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb)
+{
+ tusb_control_request_t const request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_OTHER,
+ .type = TUSB_REQ_TYPE_CLASS,
+ .direction = TUSB_DIR_IN
+ },
+ .bRequest = HUB_REQUEST_GET_STATUS,
+ .wValue = 0,
+ .wIndex = hub_port,
+ .wLength = 4
+ };
+
+ TU_LOG2("HUB Get Port Status: addr = %u port = %u\r\n", hub_addr, hub_port);
+ TU_ASSERT( tuh_control_xfer( hub_addr, &request, resp, complete_cb) );
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// CLASS-USBH API (don't require to verify parameters)
+//--------------------------------------------------------------------+
+void hub_init(void)
+{
+ tu_memclr(hub_data, sizeof(hub_data));
+}
+
+bool hub_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len)
+{
+ TU_VERIFY(TUSB_CLASS_HUB == itf_desc->bInterfaceClass &&
+ 0 == itf_desc->bInterfaceSubClass);
+
+ // hub driver does not support multiple TT yet
+ TU_VERIFY(itf_desc->bInterfaceProtocol <= 1);
+
+ // msc driver length is fixed
+ uint16_t const drv_len = sizeof(tusb_desc_interface_t) + sizeof(tusb_desc_endpoint_t);
+ TU_ASSERT(drv_len <= max_len);
+
+ //------------- Interrupt Status endpoint -------------//
+ tusb_desc_endpoint_t const *desc_ep = (tusb_desc_endpoint_t const *) tu_desc_next(itf_desc);
+
+ TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType &&
+ TUSB_XFER_INTERRUPT == desc_ep->bmAttributes.xfer, 0);
+
+ TU_ASSERT(usbh_edpt_open(rhport, dev_addr, desc_ep));
+
+ hub_interface_t* p_hub = get_itf(dev_addr);
+
+ p_hub->itf_num = itf_desc->bInterfaceNumber;
+ p_hub->ep_in = desc_ep->bEndpointAddress;
+
+ return true;
+}
+
+void hub_close(uint8_t dev_addr)
+{
+ TU_VERIFY(dev_addr > CFG_TUH_DEVICE_MAX, );
+ hub_interface_t* p_hub = get_itf(dev_addr);
+
+ if (p_hub->ep_in) tu_memclr(p_hub, sizeof( hub_interface_t));
+}
+
+bool hub_status_pipe_queue(uint8_t dev_addr)
+{
+ hub_interface_t* hub_itf = get_itf(dev_addr);
+ return usbh_edpt_xfer(dev_addr, hub_itf->ep_in, &hub_itf->status_change, 1);
+}
+
+
+//--------------------------------------------------------------------+
+// Set Configure
+//--------------------------------------------------------------------+
+
+static bool config_set_port_power (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+
+bool hub_set_config(uint8_t dev_addr, uint8_t itf_num)
+{
+ hub_interface_t* p_hub = get_itf(dev_addr);
+ TU_ASSERT(itf_num == p_hub->itf_num);
+
+ // Get Hub Descriptor
+ tusb_control_request_t const request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_DEVICE,
+ .type = TUSB_REQ_TYPE_CLASS,
+ .direction = TUSB_DIR_IN
+ },
+ .bRequest = HUB_REQUEST_GET_DESCRIPTOR,
+ .wValue = 0,
+ .wIndex = 0,
+ .wLength = sizeof(descriptor_hub_desc_t)
+ };
+
+ TU_ASSERT( tuh_control_xfer(dev_addr, &request, _hub_buffer, config_set_port_power) );
+
+ return true;
+}
+
+static bool config_set_port_power (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ hub_interface_t* p_hub = get_itf(dev_addr);
+
+ // only use number of ports in hub descriptor
+ descriptor_hub_desc_t const* desc_hub = (descriptor_hub_desc_t const*) _hub_buffer;
+ p_hub->port_count = desc_hub->bNbrPorts;
+
+ // May need to GET_STATUS
+
+ // Set Port Power to be able to detect connection, starting with port 1
+ uint8_t const hub_port = 1;
+ return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete);
+}
+
+static bool config_port_power_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+ hub_interface_t* p_hub = get_itf(dev_addr);
+
+ if (request->wIndex == p_hub->port_count)
+ {
+ // All ports are power -> queue notification status endpoint and
+ // complete the SET CONFIGURATION
+ TU_ASSERT( usbh_edpt_xfer(dev_addr, p_hub->ep_in, &p_hub->status_change, 1) );
+
+ usbh_driver_set_config_complete(dev_addr, p_hub->itf_num);
+ }else
+ {
+ // power next port
+ uint8_t const hub_port = (uint8_t) (request->wIndex + 1);
+ return hub_port_set_feature(dev_addr, hub_port, HUB_FEATURE_PORT_POWER, config_port_power_complete);
+ }
+
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// Connection Changes
+//--------------------------------------------------------------------+
+
+static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool connection_port_reset_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+
+// callback as response of interrupt endpoint polling
+bool hub_xfer_cb(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+ (void) xferred_bytes; // TODO can be more than 1 for hub with lots of ports
+ (void) ep_addr;
+ TU_ASSERT(result == XFER_RESULT_SUCCESS);
+
+ hub_interface_t* p_hub = get_itf(dev_addr);
+
+ TU_LOG2(" Port Status Change = 0x%02X\r\n", p_hub->status_change);
+
+ // Hub ignore bit0 in status change
+ for (uint8_t port=1; port <= p_hub->port_count; port++)
+ {
+ if ( tu_bit_test(p_hub->status_change, port) )
+ {
+ hub_port_get_status(dev_addr, port, &p_hub->port_status, connection_get_status_complete);
+ break;
+ }
+ }
+
+ // NOTE: next status transfer is queued by usbh.c after handling this request
+
+ return true;
+}
+
+static bool connection_get_status_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ TU_ASSERT(result == XFER_RESULT_SUCCESS);
+
+ hub_interface_t* p_hub = get_itf(dev_addr);
+ uint8_t const port_num = (uint8_t) request->wIndex;
+
+ // Connection change
+ if (p_hub->port_status.change.connection)
+ {
+ // Port is powered and enabled
+ //TU_VERIFY(port_status.status_current.port_power && port_status.status_current.port_enable, );
+
+ // Acknowledge Port Connection Change
+ hub_port_clear_feature(dev_addr, port_num, HUB_FEATURE_PORT_CONNECTION_CHANGE, connection_clear_conn_change_complete);
+ }else
+ {
+ // Other changes are: Enable, Suspend, Over Current, Reset, L1 state
+ // TODO clear change
+
+ // prepare for next hub status
+ // TODO continue with status_change, or maybe we can do it again with status
+ hub_status_pipe_queue(dev_addr);
+ }
+
+ return true;
+}
+
+static bool connection_clear_conn_change_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ TU_ASSERT(result == XFER_RESULT_SUCCESS);
+
+ hub_interface_t* p_hub = get_itf(dev_addr);
+ uint8_t const port_num = (uint8_t) request->wIndex;
+
+ if ( p_hub->port_status.status.connection )
+ {
+ // Reset port if attach event
+ hub_port_reset(dev_addr, port_num, connection_port_reset_complete);
+ }else
+ {
+ // submit detach event
+ hcd_event_t event =
+ {
+ .rhport = usbh_get_rhport(dev_addr),
+ .event_id = HCD_EVENT_DEVICE_REMOVE,
+ .connection =
+ {
+ .hub_addr = dev_addr,
+ .hub_port = port_num
+ }
+ };
+
+ hcd_event_handler(&event, false);
+ }
+
+ return true;
+}
+
+static bool connection_port_reset_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ TU_ASSERT(result == XFER_RESULT_SUCCESS);
+
+ // hub_interface_t* p_hub = get_itf(dev_addr);
+ uint8_t const port_num = (uint8_t) request->wIndex;
+
+ // submit attach event
+ hcd_event_t event =
+ {
+ .rhport = usbh_get_rhport(dev_addr),
+ .event_id = HCD_EVENT_DEVICE_ATTACH,
+ .connection =
+ {
+ .hub_addr = dev_addr,
+ .hub_port = port_num
+ }
+ };
+
+ hcd_event_handler(&event, false);
+
+ return true;
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/host/hub.h b/arkanoid/pico/tinyusb/host/hub.h
new file mode 100644
index 0000000..02dc325
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/hub.h
@@ -0,0 +1,196 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup group_class
+ * \defgroup ClassDriver_Hub Hub (Host only)
+ * \details Like most PC's OS, Hub support is completely hidden from Application. In fact, application cannot determine whether
+ * a device is mounted directly via roothub or via a hub's port. All Hub-related procedures are performed and managed
+ * by tinyusb stack. Unless you are trying to develop the stack itself, there are nothing else can be used by Application.
+ * \note Due to my laziness, only 1-level of Hub is supported. In other way, the stack cannot mount a hub via another hub.
+ * @{
+ */
+
+#ifndef _TUSB_HUB_H_
+#define _TUSB_HUB_H_
+
+#include "../tusb_common.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//D1...D0: Logical Power Switching Mode
+//00: Ganged power switching (all ports’power at
+//once)
+//01: Individual port power switching
+//1X: Reserved. Used only on 1.0 compliant hubs
+//that implement no power switching
+//D2: Identifies a Compound Device
+//0: Hub is not part of a compound device.
+//1: Hub is part of a compound device.
+//D4...D3: Over-current Protection Mode
+//00: Global Over-current Protection. The hub
+//reports over-current as a summation of all
+//ports’current draw, without a breakdown of
+//individual port over-current status.
+//01: Individual Port Over-current Protection. The
+//hub reports over-current on a per-port basis.
+//Each port has an over-current status.
+//1X: No Over-current Protection. This option is
+//allowed only for bus-powered hubs that do not
+//implement over-current protection.
+//
+//D6...D5: TT Think TIme
+//00: TT requires at most 8 FS bit times of inter
+//transaction gap on a full-/low-speed
+//downstream bus.
+//01: TT requires at most 16 FS bit times.
+//10: TT requires at most 24 FS bit times.
+//11: TT requires at most 32 FS bit times.
+//D7: Port Indicators Supported
+//0: Port Indicators are not supported on its
+//downstream facing ports and the
+//PORT_INDICATOR request has no effect.
+//1: Port Indicators are supported on its
+//downstream facing ports and the
+//PORT_INDICATOR request controls the
+//indicators. See Section 11.5.3.
+//D15...D8: Reserved
+
+typedef struct TU_ATTR_PACKED{
+ uint8_t bLength ; ///< Size of descriptor
+ uint8_t bDescriptorType ; ///< Other_speed_Configuration Type
+ uint8_t bNbrPorts;
+ uint16_t wHubCharacteristics;
+ uint8_t bPwrOn2PwrGood;
+ uint8_t bHubContrCurrent;
+ uint8_t DeviceRemovable; // bitmap each bit for a port (from bit1)
+ uint8_t PortPwrCtrlMask; // just for compatibility, should be 0xff
+} descriptor_hub_desc_t;
+
+TU_VERIFY_STATIC( sizeof(descriptor_hub_desc_t) == 9, "size is not correct");
+
+enum {
+ HUB_REQUEST_GET_STATUS = 0 ,
+ HUB_REQUEST_CLEAR_FEATURE = 1 ,
+
+ HUB_REQUEST_SET_FEATURE = 3 ,
+
+ HUB_REQUEST_GET_DESCRIPTOR = 6 ,
+ HUB_REQUEST_SET_DESCRIPTOR = 7 ,
+ HUB_REQUEST_CLEAR_TT_BUFFER = 8 ,
+ HUB_REQUEST_RESET_TT = 9 ,
+ HUB_REQUEST_GET_TT_STATE = 10 ,
+ HUB_REQUEST_STOP_TT = 11
+};
+
+enum {
+ HUB_FEATURE_HUB_LOCAL_POWER_CHANGE = 0,
+ HUB_FEATURE_HUB_OVER_CURRENT_CHANGE
+};
+
+enum{
+ HUB_FEATURE_PORT_CONNECTION = 0,
+ HUB_FEATURE_PORT_ENABLE = 1,
+ HUB_FEATURE_PORT_SUSPEND = 2,
+ HUB_FEATURE_PORT_OVER_CURRENT = 3,
+ HUB_FEATURE_PORT_RESET = 4,
+
+ HUB_FEATURE_PORT_POWER = 8,
+ HUB_FEATURE_PORT_LOW_SPEED = 9,
+
+ HUB_FEATURE_PORT_CONNECTION_CHANGE = 16,
+ HUB_FEATURE_PORT_ENABLE_CHANGE = 17,
+ HUB_FEATURE_PORT_SUSPEND_CHANGE = 18,
+ HUB_FEATURE_PORT_OVER_CURRENT_CHANGE = 19,
+ HUB_FEATURE_PORT_RESET_CHANGE = 20,
+ HUB_FEATURE_PORT_TEST = 21,
+ HUB_FEATURE_PORT_INDICATOR = 22
+};
+
+// data in response of HUB_REQUEST_GET_STATUS, wIndex = 0 (hub)
+typedef struct {
+ union{
+ struct TU_ATTR_PACKED {
+ uint16_t local_power_source : 1;
+ uint16_t over_current : 1;
+ uint16_t : 14;
+ };
+
+ uint16_t value;
+ } status, change;
+} hub_status_response_t;
+
+TU_VERIFY_STATIC( sizeof(hub_status_response_t) == 4, "size is not correct");
+
+// data in response of HUB_REQUEST_GET_STATUS, wIndex = Port num
+typedef struct {
+ union {
+ struct TU_ATTR_PACKED {
+ uint16_t connection : 1;
+ uint16_t port_enable : 1;
+ uint16_t suspend : 1;
+ uint16_t over_current : 1;
+ uint16_t reset : 1;
+
+ uint16_t : 3;
+ uint16_t port_power : 1;
+ uint16_t low_speed : 1;
+ uint16_t high_speed : 1;
+ uint16_t port_test_mode : 1;
+ uint16_t port_indicator_control : 1;
+ uint16_t TU_RESERVED : 3;
+ };
+
+ uint16_t value;
+ } status, change;
+} hub_port_status_response_t;
+
+TU_VERIFY_STATIC( sizeof(hub_port_status_response_t) == 4, "size is not correct");
+
+bool hub_port_clear_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb);
+bool hub_port_set_feature(uint8_t hub_addr, uint8_t hub_port, uint8_t feature, tuh_control_complete_cb_t complete_cb);
+
+bool hub_port_reset(uint8_t hub_addr, uint8_t hub_port, tuh_control_complete_cb_t complete_cb);
+bool hub_port_get_status(uint8_t hub_addr, uint8_t hub_port, void* resp, tuh_control_complete_cb_t complete_cb);
+bool hub_status_pipe_queue(uint8_t dev_addr);
+
+//--------------------------------------------------------------------+
+// Internal Class Driver API
+//--------------------------------------------------------------------+
+void hub_init (void);
+bool hub_open (uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const *itf_desc, uint16_t max_len);
+bool hub_set_config (uint8_t dev_addr, uint8_t itf_num);
+bool hub_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+void hub_close (uint8_t dev_addr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_HUB_H_ */
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/host/usbh.c b/arkanoid/pico/tinyusb/host/usbh.c
new file mode 100644
index 0000000..cc63a55
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/usbh.c
@@ -0,0 +1,1195 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../tusb_option.h"
+
+#if TUSB_OPT_HOST_ENABLED
+
+#include "../tusb.h"
+#include "usbh.h"
+#include "usbh_classdriver.h"
+#include "hub.h"
+
+//--------------------------------------------------------------------+
+// USBH Configuration
+//--------------------------------------------------------------------+
+
+// TODO remove,update
+#ifndef CFG_TUH_EP_MAX
+#define CFG_TUH_EP_MAX 9
+#endif
+
+#ifndef CFG_TUH_TASK_QUEUE_SZ
+#define CFG_TUH_TASK_QUEUE_SZ 16
+#endif
+
+// Debug level of USBD
+#define USBH_DBG_LVL 2
+
+//--------------------------------------------------------------------+
+// USBH-HCD common data structure
+//--------------------------------------------------------------------+
+
+typedef struct {
+ //------------- port -------------//
+ uint8_t rhport;
+ uint8_t hub_addr;
+ uint8_t hub_port;
+ uint8_t speed;
+
+ //------------- device descriptor -------------//
+ uint16_t vid;
+ uint16_t pid;
+
+ uint8_t ep0_size;
+ uint8_t i_manufacturer;
+ uint8_t i_product;
+ uint8_t i_serial;
+
+ //------------- configuration descriptor -------------//
+ // uint8_t interface_count; // bNumInterfaces alias
+
+ //------------- device -------------//
+ struct TU_ATTR_PACKED
+ {
+ uint8_t connected : 1;
+ uint8_t addressed : 1;
+ uint8_t configured : 1;
+ uint8_t suspended : 1;
+ };
+
+ volatile uint8_t state; // device state, value from enum tusbh_device_state_t
+
+ uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid)
+ uint8_t ep2drv[CFG_TUH_EP_MAX][2]; // map endpoint to driver ( 0xff is invalid )
+
+ struct TU_ATTR_PACKED
+ {
+ volatile bool busy : 1;
+ volatile bool stalled : 1;
+ volatile bool claimed : 1;
+
+ // TODO merge ep2drv here, 4-bit should be sufficient
+ }ep_status[CFG_TUH_EP_MAX][2];
+
+ // Mutex for claiming endpoint, only needed when using with preempted RTOS
+#if CFG_TUSB_OS != OPT_OS_NONE
+ osal_mutex_def_t mutexdef;
+ osal_mutex_t mutex;
+#endif
+
+} usbh_device_t;
+
+typedef struct
+{
+ uint8_t rhport;
+ uint8_t hub_addr;
+ uint8_t hub_port;
+ uint8_t speed;
+
+ volatile uint8_t connected;
+} usbh_dev0_t;
+
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+// Invalid driver ID in itf2drv[] ep2drv[][] mapping
+enum { DRVID_INVALID = 0xFFu };
+enum { ADDR_INVALID = 0xFFu };
+
+#if CFG_TUSB_DEBUG >= 2
+ #define DRIVER_NAME(_name) .name = _name,
+#else
+ #define DRIVER_NAME(_name)
+#endif
+
+static usbh_class_driver_t const usbh_class_drivers[] =
+{
+ #if CFG_TUH_CDC
+ {
+ DRIVER_NAME("CDC")
+ .init = cdch_init,
+ .open = cdch_open,
+ .set_config = cdch_set_config,
+ .xfer_cb = cdch_xfer_cb,
+ .close = cdch_close
+ },
+ #endif
+
+ #if CFG_TUH_MSC
+ {
+ DRIVER_NAME("MSC")
+ .init = msch_init,
+ .open = msch_open,
+ .set_config = msch_set_config,
+ .xfer_cb = msch_xfer_cb,
+ .close = msch_close
+ },
+ #endif
+
+ #if CFG_TUH_HID
+ {
+ DRIVER_NAME("HID")
+ .init = hidh_init,
+ .open = hidh_open,
+ .set_config = hidh_set_config,
+ .xfer_cb = hidh_xfer_cb,
+ .close = hidh_close
+ },
+ #endif
+
+ #if CFG_TUH_HUB
+ {
+ DRIVER_NAME("HUB")
+ .init = hub_init,
+ .open = hub_open,
+ .set_config = hub_set_config,
+ .xfer_cb = hub_xfer_cb,
+ .close = hub_close
+ },
+ #endif
+
+ #if CFG_TUH_VENDOR
+ {
+ DRIVER_NAME("VENDOR")
+ .init = cush_init,
+ .open = cush_open_subtask,
+ .xfer_cb = cush_isr,
+ .close = cush_close
+ }
+ #endif
+};
+
+enum { USBH_CLASS_DRIVER_COUNT = TU_ARRAY_SIZE(usbh_class_drivers) };
+
+enum { RESET_DELAY = 500 }; // 200 USB specs say only 50ms but many devices require much longer
+
+enum { CONFIG_NUM = 1 }; // default to use configuration 1
+
+
+//--------------------------------------------------------------------+
+// INTERNAL OBJECT & FUNCTION DECLARATION
+//--------------------------------------------------------------------+
+
+static bool _usbh_initialized = false;
+
+// Device with address = 0 for enumeration
+static usbh_dev0_t _dev0;
+
+// all devices excluding zero-address
+// hub address start from CFG_TUH_DEVICE_MAX+1
+CFG_TUSB_MEM_SECTION usbh_device_t _usbh_devices[CFG_TUH_DEVICE_MAX + CFG_TUH_HUB];
+
+// Event queue
+// role device/host is used by OS NONE for mutex (disable usb isr)
+OSAL_QUEUE_DEF(OPT_MODE_HOST, _usbh_qdef, CFG_TUH_TASK_QUEUE_SZ, hcd_event_t);
+static osal_queue_t _usbh_q;
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN static uint8_t _usbh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
+
+//------------- Helper Function -------------//
+
+TU_ATTR_ALWAYS_INLINE
+static inline usbh_device_t* get_device(uint8_t dev_addr)
+{
+ TU_ASSERT(dev_addr, NULL);
+ return &_usbh_devices[dev_addr-1];
+}
+
+static bool enum_new_device(hcd_event_t* event);
+static void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port);
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size);
+
+// from usbh_control.c
+extern bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+
+//--------------------------------------------------------------------+
+// PUBLIC API (Parameter Verification is required)
+//--------------------------------------------------------------------+
+bool tuh_mounted(uint8_t dev_addr)
+{
+ return get_device(dev_addr)->configured;
+}
+
+bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid)
+{
+ *vid = *pid = 0;
+
+ TU_VERIFY(tuh_mounted(dev_addr));
+
+ usbh_device_t const* dev = get_device(dev_addr);
+
+ *vid = dev->vid;
+ *pid = dev->pid;
+
+ return true;
+}
+
+tusb_speed_t tuh_speed_get (uint8_t dev_addr)
+{
+ return (tusb_speed_t) (dev_addr ? get_device(dev_addr)->speed : _dev0.speed);
+}
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+void osal_task_delay(uint32_t msec)
+{
+ (void) msec;
+
+ const uint32_t start = hcd_frame_number(TUH_OPT_RHPORT);
+ while ( ( hcd_frame_number(TUH_OPT_RHPORT) - start ) < msec ) {}
+}
+#endif
+
+//--------------------------------------------------------------------+
+// CLASS-USBD API (don't require to verify parameters)
+//--------------------------------------------------------------------+
+
+bool tuh_inited(void)
+{
+ return _usbh_initialized;
+}
+
+bool tuh_init(uint8_t rhport)
+{
+ // skip if already initialized
+ if (_usbh_initialized) return _usbh_initialized;
+
+ TU_LOG2("USBH init\r\n");
+
+ tu_memclr(_usbh_devices, sizeof(_usbh_devices));
+ tu_memclr(&_dev0, sizeof(_dev0));
+
+ //------------- Enumeration & Reporter Task init -------------//
+ _usbh_q = osal_queue_create( &_usbh_qdef );
+ TU_ASSERT(_usbh_q != NULL);
+
+ //------------- Semaphore, Mutex for Control Pipe -------------//
+ for(uint8_t i=0; i<TU_ARRAY_SIZE(_usbh_devices); i++)
+ {
+ usbh_device_t * dev = &_usbh_devices[i];
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ dev->mutex = osal_mutex_create(&dev->mutexdef);
+ TU_ASSERT(dev->mutex);
+#endif
+
+ memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
+ memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
+ }
+
+ // Class drivers init
+ for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+ {
+ TU_LOG2("%s init\r\n", usbh_class_drivers[drv_id].name);
+ usbh_class_drivers[drv_id].init();
+ }
+
+ TU_ASSERT(hcd_init(rhport));
+ hcd_int_enable(rhport);
+
+ _usbh_initialized = true;
+ return true;
+}
+
+/* USB Host Driver task
+ * This top level thread manages all host controller event and delegates events to class-specific drivers.
+ * This should be called periodically within the mainloop or rtos thread.
+ *
+ @code
+ int main(void)
+ {
+ application_init();
+ tusb_init();
+
+ while(1) // the mainloop
+ {
+ application_code();
+ tuh_task(); // tinyusb host task
+ }
+ }
+ @endcode
+ */
+void tuh_task(void)
+{
+ // Skip if stack is not initialized
+ if ( !tusb_inited() ) return;
+
+ // Loop until there is no more events in the queue
+ while (1)
+ {
+ hcd_event_t event;
+ if ( !osal_queue_receive(_usbh_q, &event) ) return;
+
+ switch (event.event_id)
+ {
+ case HCD_EVENT_DEVICE_ATTACH:
+ // TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
+ // one device before enumerating another one.
+ TU_LOG2("USBH DEVICE ATTACH\r\n");
+ enum_new_device(&event);
+ break;
+
+ case HCD_EVENT_DEVICE_REMOVE:
+ TU_LOG2("USBH DEVICE REMOVED\r\n");
+ process_device_unplugged(event.rhport, event.connection.hub_addr, event.connection.hub_port);
+
+ #if CFG_TUH_HUB
+ // TODO remove
+ if ( event.connection.hub_addr != 0)
+ {
+ // done with hub, waiting for next data on status pipe
+ (void) hub_status_pipe_queue( event.connection.hub_addr );
+ }
+ #endif
+ break;
+
+ case HCD_EVENT_XFER_COMPLETE:
+ {
+ uint8_t const ep_addr = event.xfer_complete.ep_addr;
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const ep_dir = tu_edpt_dir(ep_addr);
+
+ TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+
+ if (event.dev_addr == 0)
+ {
+ // device 0 only has control endpoint
+ TU_ASSERT(epnum == 0, );
+ usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+ }
+ else
+ {
+ usbh_device_t* dev = get_device(event.dev_addr);
+ dev->ep_status[epnum][ep_dir].busy = false;
+ dev->ep_status[epnum][ep_dir].claimed = 0;
+
+ if ( 0 == epnum )
+ {
+ usbh_control_xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+ }else
+ {
+ uint8_t drv_id = dev->ep2drv[epnum][ep_dir];
+ TU_ASSERT(drv_id < USBH_CLASS_DRIVER_COUNT, );
+
+ TU_LOG2("%s xfer callback\r\n", usbh_class_drivers[drv_id].name);
+ usbh_class_drivers[drv_id].xfer_cb(event.dev_addr, ep_addr, event.xfer_complete.result, event.xfer_complete.len);
+ }
+ }
+ }
+ break;
+
+ case USBH_EVENT_FUNC_CALL:
+ if ( event.func_call.func ) event.func_call.func(event.func_call.param);
+ break;
+
+ default: break;
+ }
+ }
+}
+
+//--------------------------------------------------------------------+
+// USBH API For Class Driver
+//--------------------------------------------------------------------+
+
+uint8_t usbh_get_rhport(uint8_t dev_addr)
+{
+ return (dev_addr == 0) ? _dev0.rhport : get_device(dev_addr)->rhport;
+}
+
+uint8_t* usbh_get_enum_buf(void)
+{
+ return _usbh_ctrl_buf;
+}
+
+//--------------------------------------------------------------------+
+// HCD Event Handler
+//--------------------------------------------------------------------+
+
+void hcd_devtree_get_info(uint8_t dev_addr, hcd_devtree_info_t* devtree_info)
+{
+ if (dev_addr)
+ {
+ usbh_device_t const* dev = get_device(dev_addr);
+
+ devtree_info->rhport = dev->rhport;
+ devtree_info->hub_addr = dev->hub_addr;
+ devtree_info->hub_port = dev->hub_port;
+ devtree_info->speed = dev->speed;
+ }else
+ {
+ devtree_info->rhport = _dev0.rhport;
+ devtree_info->hub_addr = _dev0.hub_addr;
+ devtree_info->hub_port = _dev0.hub_port;
+ devtree_info->speed = _dev0.speed;
+ }
+}
+
+void hcd_event_handler(hcd_event_t const* event, bool in_isr)
+{
+ switch (event->event_id)
+ {
+ default:
+ osal_queue_send(_usbh_q, event, in_isr);
+ break;
+ }
+}
+
+void hcd_event_xfer_complete(uint8_t dev_addr, uint8_t ep_addr, uint32_t xferred_bytes, xfer_result_t result, bool in_isr)
+{
+ hcd_event_t event =
+ {
+ .rhport = 0, // TODO correct rhport
+ .event_id = HCD_EVENT_XFER_COMPLETE,
+ .dev_addr = dev_addr,
+ .xfer_complete =
+ {
+ .ep_addr = ep_addr,
+ .result = result,
+ .len = xferred_bytes
+ }
+ };
+
+ hcd_event_handler(&event, in_isr);
+}
+
+void hcd_event_device_attach(uint8_t rhport, bool in_isr)
+{
+ hcd_event_t event =
+ {
+ .rhport = rhport,
+ .event_id = HCD_EVENT_DEVICE_ATTACH
+ };
+
+ event.connection.hub_addr = 0;
+ event.connection.hub_port = 0;
+
+ hcd_event_handler(&event, in_isr);
+}
+
+void hcd_event_device_remove(uint8_t hostid, bool in_isr)
+{
+ hcd_event_t event =
+ {
+ .rhport = hostid,
+ .event_id = HCD_EVENT_DEVICE_REMOVE
+ };
+
+ event.connection.hub_addr = 0;
+ event.connection.hub_port = 0;
+
+ hcd_event_handler(&event, in_isr);
+}
+
+
+// a device unplugged on hostid, hub_addr, hub_port
+// return true if found and unmounted device, false if cannot find
+void process_device_unplugged(uint8_t rhport, uint8_t hub_addr, uint8_t hub_port)
+{
+ //------------- find the all devices (star-network) under port that is unplugged -------------//
+ // TODO mark as disconnected in ISR, also handle dev0
+ for ( uint8_t dev_id = 0; dev_id < TU_ARRAY_SIZE(_usbh_devices); dev_id++ )
+ {
+ usbh_device_t* dev = &_usbh_devices[dev_id];
+ uint8_t const dev_addr = dev_id+1;
+
+ // TODO Hub multiple level
+ if (dev->rhport == rhport &&
+ (hub_addr == 0 || dev->hub_addr == hub_addr) && // hub_addr == 0 & hub_port == 0 means roothub
+ (hub_port == 0 || dev->hub_port == hub_port) &&
+ dev->state != TUSB_DEVICE_STATE_UNPLUG)
+ {
+ // Invoke callback before close driver
+ if (tuh_umount_cb) tuh_umount_cb(dev_addr);
+
+ // Close class driver
+ for (uint8_t drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+ {
+ TU_LOG2("%s close\r\n", usbh_class_drivers[drv_id].name);
+ usbh_class_drivers[drv_id].close(dev_addr);
+ }
+
+ memset(dev->itf2drv, DRVID_INVALID, sizeof(dev->itf2drv)); // invalid mapping
+ memset(dev->ep2drv , DRVID_INVALID, sizeof(dev->ep2drv )); // invalid mapping
+
+ hcd_device_close(rhport, dev_addr);
+
+ dev->state = TUSB_DEVICE_STATE_UNPLUG;
+ }
+ }
+}
+
+//--------------------------------------------------------------------+
+// INTERNAL HELPER
+//--------------------------------------------------------------------+
+static uint8_t get_new_address(bool is_hub)
+{
+ uint8_t const start = (is_hub ? CFG_TUH_DEVICE_MAX : 0) + 1;
+ uint8_t const count = (is_hub ? CFG_TUH_HUB : CFG_TUH_DEVICE_MAX);
+
+ for (uint8_t i=0; i < count; i++)
+ {
+ uint8_t const addr = start + i;
+ if (get_device(addr)->state == TUSB_DEVICE_STATE_UNPLUG) return addr;
+ }
+ return ADDR_INVALID;
+}
+
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num)
+{
+ usbh_device_t* dev = get_device(dev_addr);
+
+ for(itf_num++; itf_num < sizeof(dev->itf2drv); itf_num++)
+ {
+ // continue with next valid interface
+ // TODO skip IAD binding interface such as CDCs
+ uint8_t const drv_id = dev->itf2drv[itf_num];
+ if (drv_id != DRVID_INVALID)
+ {
+ usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+ TU_LOG2("%s set config: itf = %u\r\n", driver->name, itf_num);
+ driver->set_config(dev_addr, itf_num);
+ break;
+ }
+ }
+
+ // all interface are configured
+ if (itf_num == sizeof(dev->itf2drv))
+ {
+ // Invoke callback if available
+ if (tuh_mount_cb) tuh_mount_cb(dev_addr);
+ }
+}
+
+//--------------------------------------------------------------------+
+// Enumeration Process
+// is a lengthy process with a seires of control transfer to configure
+// newly attached device. Each step is handled by a function in this
+// section
+// TODO due to the shared _usbh_ctrl_buf, we must complete enumerating
+// one device before enumerating another one.
+//--------------------------------------------------------------------+
+
+static bool enum_request_addr0_device_desc(void);
+static bool enum_request_set_addr(void);
+
+static bool enum_get_addr0_device_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_set_address_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_get_device_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_get_9byte_config_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_get_config_desc_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool enum_set_config_complete (uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+static bool parse_configuration_descriptor (uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg);
+
+#if CFG_TUH_HUB
+static bool enum_hub_clear_reset0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) dev_addr; (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+ enum_request_addr0_device_desc();
+ return true;
+}
+
+static bool enum_hub_clear_reset1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) dev_addr; (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ enum_request_set_addr();
+
+ // done with hub, waiting for next data on status pipe
+ (void) hub_status_pipe_queue( _dev0.hub_addr );
+
+ return true;
+}
+
+static bool enum_hub_get_status1_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) dev_addr; (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ hub_port_status_response_t port_status;
+ memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
+
+ // Acknowledge Port Reset Change if Reset Successful
+ if (port_status.change.reset)
+ {
+ TU_ASSERT( hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset1_complete) );
+ }
+
+ return true;
+}
+
+static bool enum_hub_get_status0_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) dev_addr; (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ hub_port_status_response_t port_status;
+ memcpy(&port_status, _usbh_ctrl_buf, sizeof(hub_port_status_response_t));
+
+ if ( !port_status.status.connection )
+ {
+ // device unplugged while delaying, nothing else to do, queue hub status
+ return hub_status_pipe_queue(dev_addr);
+ }
+
+ _dev0.speed = (port_status.status.high_speed) ? TUSB_SPEED_HIGH :
+ (port_status.status.low_speed ) ? TUSB_SPEED_LOW : TUSB_SPEED_FULL;
+
+ // Acknowledge Port Reset Change
+ if (port_status.change.reset)
+ {
+ hub_port_clear_feature(_dev0.hub_addr, _dev0.hub_port, HUB_FEATURE_PORT_RESET_CHANGE, enum_hub_clear_reset0_complete);
+ }
+
+ return true;
+}
+#endif
+
+static bool enum_new_device(hcd_event_t* event)
+{
+ _dev0.rhport = event->rhport; // TODO refractor integrate to device_pool
+ _dev0.hub_addr = event->connection.hub_addr;
+ _dev0.hub_port = event->connection.hub_port;
+
+ //------------- connected/disconnected directly with roothub -------------//
+ if (_dev0.hub_addr == 0)
+ {
+ // wait until device is stable TODO non blocking
+ osal_task_delay(RESET_DELAY);
+
+ // device unplugged while delaying
+ if ( !hcd_port_connect_status(_dev0.rhport) ) return true;
+
+ _dev0.speed = hcd_port_speed_get(_dev0.rhport );
+
+ enum_request_addr0_device_desc();
+ }
+#if CFG_TUH_HUB
+ //------------- connected/disconnected via hub -------------//
+ else
+ {
+ // wait until device is stable
+ osal_task_delay(RESET_DELAY);
+ TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status0_complete) );
+ }
+#endif // CFG_TUH_HUB
+
+ return true;
+}
+
+static bool enum_request_addr0_device_desc(void)
+{
+ // TODO probably doesn't need to open/close each enumeration
+ uint8_t const addr0 = 0;
+ TU_ASSERT( usbh_edpt_control_open(addr0, 8) );
+
+ //------------- Get first 8 bytes of device descriptor to get Control Endpoint Size -------------//
+ TU_LOG2("Get 8 byte of Device Descriptor\r\n");
+ tusb_control_request_t const request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_DEVICE,
+ .type = TUSB_REQ_TYPE_STANDARD,
+ .direction = TUSB_DIR_IN
+ },
+ .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+ .wValue = TUSB_DESC_DEVICE << 8,
+ .wIndex = 0,
+ .wLength = 8
+ };
+ TU_ASSERT( tuh_control_xfer(addr0, &request, _usbh_ctrl_buf, enum_get_addr0_device_desc_complete) );
+
+ return true;
+}
+
+// After Get Device Descriptor of Address 0
+static bool enum_get_addr0_device_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) request;
+ TU_ASSERT(0 == dev_addr);
+
+ if (XFER_RESULT_SUCCESS != result)
+ {
+#if CFG_TUH_HUB
+ // TODO remove, waiting for next data on status pipe
+ if (_dev0.hub_addr != 0) hub_status_pipe_queue(_dev0.hub_addr);
+#endif
+
+ return false;
+ }
+
+ tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+ TU_ASSERT( tu_desc_type(desc_device) == TUSB_DESC_DEVICE );
+
+ // Reset device again before Set Address
+ TU_LOG2("Port reset \r\n");
+
+ if (_dev0.hub_addr == 0)
+ {
+ // connected directly to roothub
+ hcd_port_reset( _dev0.rhport ); // reset port after 8 byte descriptor
+ osal_task_delay(RESET_DELAY);
+
+ enum_request_set_addr();
+ }
+#if CFG_TUH_HUB
+ else
+ {
+ // after RESET_DELAY the hub_port_reset() already complete
+ TU_ASSERT( hub_port_reset(_dev0.hub_addr, _dev0.hub_port, NULL) );
+ osal_task_delay(RESET_DELAY);
+
+ tuh_task(); // FIXME temporarily to clean up port_reset control transfer
+
+ TU_ASSERT( hub_port_get_status(_dev0.hub_addr, _dev0.hub_port, _usbh_ctrl_buf, enum_hub_get_status1_complete) );
+ }
+#endif
+
+ return true;
+}
+
+static bool enum_request_set_addr(void)
+{
+ uint8_t const addr0 = 0;
+ tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+
+ // Get new address
+ uint8_t const new_addr = get_new_address(desc_device->bDeviceClass == TUSB_CLASS_HUB);
+ TU_ASSERT(new_addr != ADDR_INVALID);
+
+ TU_LOG2("Set Address = %d\r\n", new_addr);
+
+ usbh_device_t* new_dev = get_device(new_addr);
+
+ new_dev->rhport = _dev0.rhport;
+ new_dev->hub_addr = _dev0.hub_addr;
+ new_dev->hub_port = _dev0.hub_port;
+ new_dev->speed = _dev0.speed;
+ new_dev->connected = 1;
+ new_dev->ep0_size = desc_device->bMaxPacketSize0;
+
+ tusb_control_request_t const new_request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_DEVICE,
+ .type = TUSB_REQ_TYPE_STANDARD,
+ .direction = TUSB_DIR_OUT
+ },
+ .bRequest = TUSB_REQ_SET_ADDRESS,
+ .wValue = new_addr,
+ .wIndex = 0,
+ .wLength = 0
+ };
+
+ TU_ASSERT( tuh_control_xfer(addr0, &new_request, NULL, enum_set_address_complete) );
+
+ return true;
+}
+
+// After SET_ADDRESS is complete
+static bool enum_set_address_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ TU_ASSERT(0 == dev_addr);
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ uint8_t const new_addr = (uint8_t const) request->wValue;
+
+ usbh_device_t* new_dev = get_device(new_addr);
+ new_dev->addressed = 1;
+
+ // TODO close device 0, may not be needed
+ hcd_device_close(_dev0.rhport, 0);
+
+ // open control pipe for new address
+ TU_ASSERT( usbh_edpt_control_open(new_addr, new_dev->ep0_size) );
+
+ // Get full device descriptor
+ TU_LOG2("Get Device Descriptor\r\n");
+ tusb_control_request_t const new_request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_DEVICE,
+ .type = TUSB_REQ_TYPE_STANDARD,
+ .direction = TUSB_DIR_IN
+ },
+ .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+ .wValue = TUSB_DESC_DEVICE << 8,
+ .wIndex = 0,
+ .wLength = sizeof(tusb_desc_device_t)
+ };
+
+ TU_ASSERT(tuh_control_xfer(new_addr, &new_request, _usbh_ctrl_buf, enum_get_device_desc_complete));
+
+ return true;
+}
+
+static bool enum_get_device_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ tusb_desc_device_t const * desc_device = (tusb_desc_device_t const*) _usbh_ctrl_buf;
+ usbh_device_t* dev = get_device(dev_addr);
+
+ dev->vid = desc_device->idVendor;
+ dev->pid = desc_device->idProduct;
+ dev->i_manufacturer = desc_device->iManufacturer;
+ dev->i_product = desc_device->iProduct;
+ dev->i_serial = desc_device->iSerialNumber;
+
+// if (tuh_attach_cb) tuh_attach_cb((tusb_desc_device_t*) _usbh_ctrl_buf);
+
+ TU_LOG2("Get 9 bytes of Configuration Descriptor\r\n");
+ tusb_control_request_t const new_request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_DEVICE,
+ .type = TUSB_REQ_TYPE_STANDARD,
+ .direction = TUSB_DIR_IN
+ },
+ .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+ .wValue = (TUSB_DESC_CONFIGURATION << 8) | (CONFIG_NUM - 1),
+ .wIndex = 0,
+ .wLength = 9
+ };
+
+ TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, _usbh_ctrl_buf, enum_get_9byte_config_desc_complete) );
+
+ return true;
+}
+
+static bool enum_get_9byte_config_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ // TODO not enough buffer to hold configuration descriptor
+ tusb_desc_configuration_t const * desc_config = (tusb_desc_configuration_t const*) _usbh_ctrl_buf;
+ uint16_t total_len;
+
+ // Use offsetof to avoid pointer to the odd/misaligned address
+ memcpy(&total_len, (uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength), 2);
+
+ TU_ASSERT(total_len <= CFG_TUH_ENUMERATION_BUFSIZE);
+
+ // Get full configuration descriptor
+ TU_LOG2("Get Configuration Descriptor\r\n");
+ tusb_control_request_t const new_request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_DEVICE,
+ .type = TUSB_REQ_TYPE_STANDARD,
+ .direction = TUSB_DIR_IN
+ },
+ .bRequest = TUSB_REQ_GET_DESCRIPTOR,
+ .wValue = (TUSB_DESC_CONFIGURATION << 8) | (CONFIG_NUM - 1),
+ .wIndex = 0,
+ .wLength = total_len
+
+ };
+
+ TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, _usbh_ctrl_buf, enum_get_config_desc_complete) );
+
+ return true;
+}
+
+static bool enum_get_config_desc_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ // Parse configuration & set up drivers
+ // Driver open aren't allowed to make any usb transfer yet
+ TU_ASSERT( parse_configuration_descriptor(dev_addr, (tusb_desc_configuration_t*) _usbh_ctrl_buf) );
+
+ TU_LOG2("Set Configuration = %d\r\n", CONFIG_NUM);
+ tusb_control_request_t const new_request =
+ {
+ .bmRequestType_bit =
+ {
+ .recipient = TUSB_REQ_RCPT_DEVICE,
+ .type = TUSB_REQ_TYPE_STANDARD,
+ .direction = TUSB_DIR_OUT
+ },
+ .bRequest = TUSB_REQ_SET_CONFIGURATION,
+ .wValue = CONFIG_NUM,
+ .wIndex = 0,
+ .wLength = 0
+ };
+
+ TU_ASSERT( tuh_control_xfer(dev_addr, &new_request, NULL, enum_set_config_complete) );
+
+ return true;
+}
+
+static bool enum_set_config_complete(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result)
+{
+ (void) request;
+ TU_ASSERT(XFER_RESULT_SUCCESS == result);
+
+ TU_LOG2("Device configured\r\n");
+ usbh_device_t* dev = get_device(dev_addr);
+ dev->configured = 1;
+ dev->state = TUSB_DEVICE_STATE_CONFIGURED;
+
+ // Start the Set Configuration process for interfaces (itf = DRVID_INVALID)
+ // Since driver can perform control transfer within its set_config, this is done asynchronously.
+ // The process continue with next interface when class driver complete its sequence with usbh_driver_set_config_complete()
+ // TODO use separated API instead of using DRVID_INVALID
+ usbh_driver_set_config_complete(dev_addr, DRVID_INVALID);
+
+ return true;
+}
+
+static bool parse_configuration_descriptor(uint8_t dev_addr, tusb_desc_configuration_t const* desc_cfg)
+{
+ usbh_device_t* dev = get_device(dev_addr);
+
+ uint8_t const* desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
+ uint8_t const* p_desc = tu_desc_next(desc_cfg);
+
+ // parse each interfaces
+ while( p_desc < desc_end )
+ {
+ uint8_t assoc_itf_count = 1;
+
+ // Class will always starts with Interface Association (if any) and then Interface descriptor
+ if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
+ {
+ tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
+ assoc_itf_count = desc_iad->bInterfaceCount;
+
+ p_desc = tu_desc_next(p_desc); // next to Interface
+
+ // IAD's first interface number and class should match with opened interface
+ //TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
+ // desc_iad->bFunctionClass == desc_itf->bInterfaceClass);
+ }
+
+ TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
+ tusb_desc_interface_t const* desc_itf = (tusb_desc_interface_t const*) p_desc;
+
+#if CFG_TUH_MIDI
+ // MIDI has 2 interfaces (Audio Control v1 + MIDIStreaming) but does not have IAD
+ // manually increase the associated count
+ if (1 == assoc_itf_count &&
+ TUSB_CLASS_AUDIO == desc_itf->bInterfaceClass &&
+ AUDIO_SUBCLASS_CONTROL == desc_itf->bInterfaceSubClass &&
+ AUDIO_FUNC_PROTOCOL_CODE_UNDEF == desc_itf->bInterfaceProtocol)
+ {
+ assoc_itf_count = 2;
+ }
+#endif
+
+ uint16_t const drv_len = tu_desc_get_interface_total_len(desc_itf, assoc_itf_count, desc_end-p_desc);
+ TU_ASSERT(drv_len >= sizeof(tusb_desc_interface_t));
+
+ if (desc_itf->bInterfaceClass == TUSB_CLASS_HUB && dev->hub_addr != 0)
+ {
+ // TODO Attach hub to Hub is not currently supported
+ // skip this interface
+ TU_LOG(USBH_DBG_LVL, "Only 1 level of HUB is supported\r\n");
+ }
+ else
+ {
+ // Find driver for this interface
+ uint8_t drv_id;
+ for (drv_id = 0; drv_id < USBH_CLASS_DRIVER_COUNT; drv_id++)
+ {
+ usbh_class_driver_t const * driver = &usbh_class_drivers[drv_id];
+
+ if ( driver->open(dev->rhport, dev_addr, desc_itf, drv_len) )
+ {
+ // open successfully
+ TU_LOG2(" %s opened\r\n", driver->name);
+
+ // bind (associated) interfaces to found driver
+ for(uint8_t i=0; i<assoc_itf_count; i++)
+ {
+ uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
+
+ // Interface number must not be used already
+ TU_ASSERT( DRVID_INVALID == dev->itf2drv[itf_num] );
+ dev->itf2drv[itf_num] = drv_id;
+ }
+
+ // bind all endpoints to found driver
+ tu_edpt_bind_driver(dev->ep2drv, desc_itf, drv_len, drv_id);
+
+ break; // exit driver find loop
+ }
+ }
+
+ if( drv_id >= USBH_CLASS_DRIVER_COUNT )
+ {
+ TU_LOG(USBH_DBG_LVL, "Interface %u: class = %u subclass = %u protocol = %u is not supported\r\n",
+ desc_itf->bInterfaceNumber, desc_itf->bInterfaceClass, desc_itf->bInterfaceSubClass, desc_itf->bInterfaceProtocol);
+ }
+ }
+
+ // next Interface or IAD descriptor
+ p_desc += drv_len;
+ }
+
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// Endpoint API
+//--------------------------------------------------------------------+
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr)
+{
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ usbh_device_t* dev = get_device(dev_addr);
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ // pre-check to help reducing mutex lock
+ TU_VERIFY((dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0));
+ osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+ // can only claim the endpoint if it is not busy and not claimed yet.
+ bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 0);
+ if (ret)
+ {
+ dev->ep_status[epnum][dir].claimed = 1;
+ }
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ osal_mutex_unlock(dev->mutex);
+#endif
+
+ return ret;
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr)
+{
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ usbh_device_t* dev = get_device(dev_addr);
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ osal_mutex_lock(dev->mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+ // can only release the endpoint if it is claimed and not busy
+ bool const ret = (dev->ep_status[epnum][dir].busy == 0) && (dev->ep_status[epnum][dir].claimed == 1);
+ if (ret)
+ {
+ dev->ep_status[epnum][dir].claimed = 0;
+ }
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ osal_mutex_unlock(dev->mutex);
+#endif
+
+ return ret;
+}
+
+// TODO has some duplication code with device, refactor later
+bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ usbh_device_t* dev = get_device(dev_addr);
+
+ TU_LOG2(" Queue EP %02X with %u bytes ... ", ep_addr, total_bytes);
+
+ // Attempt to transfer on a busy endpoint, sound like an race condition !
+ TU_ASSERT(dev->ep_status[epnum][dir].busy == 0);
+
+ // Set busy first since the actual transfer can be complete before hcd_edpt_xfer()
+ // could return and USBH task can preempt and clear the busy
+ dev->ep_status[epnum][dir].busy = true;
+
+ if ( hcd_edpt_xfer(dev->rhport, dev_addr, ep_addr, buffer, total_bytes) )
+ {
+ TU_LOG2("OK\r\n");
+ return true;
+ }else
+ {
+ // HCD error, mark endpoint as ready to allow next transfer
+ dev->ep_status[epnum][dir].busy = false;
+ dev->ep_status[epnum][dir].claimed = 0;
+ TU_LOG2("failed\r\n");
+ TU_BREAKPOINT();
+ return false;
+ }
+}
+
+static bool usbh_edpt_control_open(uint8_t dev_addr, uint8_t max_packet_size)
+{
+ TU_LOG2("Open EP0 with Size = %u (addr = %u)\r\n", max_packet_size, dev_addr);
+
+ tusb_desc_endpoint_t ep0_desc =
+ {
+ .bLength = sizeof(tusb_desc_endpoint_t),
+ .bDescriptorType = TUSB_DESC_ENDPOINT,
+ .bEndpointAddress = 0,
+ .bmAttributes = { .xfer = TUSB_XFER_CONTROL },
+ .wMaxPacketSize = { .size = max_packet_size },
+ .bInterval = 0
+ };
+
+ return hcd_edpt_open(usbh_get_rhport(dev_addr), dev_addr, &ep0_desc);
+}
+
+bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep)
+{
+ usbh_device_t* dev = get_device(dev_addr);
+ TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) dev->speed));
+
+ return hcd_edpt_open(rhport, dev_addr, desc_ep);
+}
+
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr)
+{
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ usbh_device_t* dev = get_device(dev_addr);
+
+ return dev->ep_status[epnum][dir].busy;
+}
+
+
+
+#endif
diff --git a/arkanoid/pico/tinyusb/host/usbh.h b/arkanoid/pico/tinyusb/host/usbh.h
new file mode 100644
index 0000000..fc8cf13
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/usbh.h
@@ -0,0 +1,99 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_USBH_H_
+#define _TUSB_USBH_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "../tusb_common.h"
+#include "hcd.h"
+
+//--------------------------------------------------------------------+
+// MACRO CONSTANT TYPEDEF
+//--------------------------------------------------------------------+
+
+typedef bool (*tuh_control_complete_cb_t)(uint8_t dev_addr, tusb_control_request_t const * request, xfer_result_t result);
+
+//--------------------------------------------------------------------+
+// APPLICATION API
+//--------------------------------------------------------------------+
+
+// Init host stack
+bool tuh_init(uint8_t rhport);
+
+// Check if host stack is already initialized
+bool tuh_inited(void);
+
+// Task function should be called in main/rtos loop
+void tuh_task(void);
+
+// Interrupt handler, name alias to HCD
+extern void hcd_int_handler(uint8_t rhport);
+#define tuh_int_handler hcd_int_handler
+
+bool tuh_vid_pid_get(uint8_t dev_addr, uint16_t* vid, uint16_t* pid);
+tusb_speed_t tuh_speed_get(uint8_t dev_addr);
+
+// Check if device is connected and configured
+bool tuh_mounted(uint8_t dev_addr);
+
+// Check if device is suspended
+static inline bool tuh_suspended(uint8_t dev_addr)
+{
+ // TODO implement suspend & resume on host
+ (void) dev_addr;
+ return false;
+}
+
+// Check if device is ready to communicate with
+TU_ATTR_ALWAYS_INLINE
+static inline bool tuh_ready(uint8_t dev_addr)
+{
+ return tuh_mounted(dev_addr) && !tuh_suspended(dev_addr);
+}
+
+// Carry out control transfer
+bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb);
+
+//--------------------------------------------------------------------+
+// APPLICATION CALLBACK
+//--------------------------------------------------------------------+
+//TU_ATTR_WEAK uint8_t tuh_attach_cb (tusb_desc_device_t const *desc_device);
+
+// Invoked when device is mounted (configured)
+TU_ATTR_WEAK void tuh_mount_cb (uint8_t dev_addr);
+
+/// Invoked when device is unmounted (bus reset/unplugged)
+TU_ATTR_WEAK void tuh_umount_cb(uint8_t dev_addr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/arkanoid/pico/tinyusb/host/usbh_classdriver.h b/arkanoid/pico/tinyusb/host/usbh_classdriver.h
new file mode 100644
index 0000000..542c585
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/usbh_classdriver.h
@@ -0,0 +1,83 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2021, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_USBH_CLASSDRIVER_H_
+#define _TUSB_USBH_CLASSDRIVER_H_
+
+#include "../osal.h"
+#include "../tusb_fifo.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Class Driver API
+//--------------------------------------------------------------------+
+
+typedef struct {
+ #if CFG_TUSB_DEBUG >= 2
+ char const* name;
+ #endif
+
+ void (* const init )(void);
+ bool (* const open )(uint8_t rhport, uint8_t dev_addr, tusb_desc_interface_t const * itf_desc, uint16_t max_len);
+ bool (* const set_config )(uint8_t dev_addr, uint8_t itf_num);
+ bool (* const xfer_cb )(uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+ void (* const close )(uint8_t dev_addr);
+} usbh_class_driver_t;
+
+// Call by class driver to tell USBH that it has complete the enumeration
+void usbh_driver_set_config_complete(uint8_t dev_addr, uint8_t itf_num);
+
+uint8_t usbh_get_rhport(uint8_t dev_addr);
+
+uint8_t* usbh_get_enum_buf(void);
+
+//--------------------------------------------------------------------+
+// USBH Endpoint API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool usbh_edpt_open(uint8_t rhport, uint8_t dev_addr, tusb_desc_endpoint_t const * desc_ep);
+
+// Submit a usb transfer
+bool usbh_edpt_xfer(uint8_t dev_addr, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+
+// Claim an endpoint before submitting a transfer.
+// If caller does not make any transfer, it must release endpoint for others.
+bool usbh_edpt_claim(uint8_t dev_addr, uint8_t ep_addr);
+
+bool usbh_edpt_release(uint8_t dev_addr, uint8_t ep_addr);
+
+// Check if endpoint transferring is complete
+bool usbh_edpt_busy(uint8_t dev_addr, uint8_t ep_addr);
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif
diff --git a/arkanoid/pico/tinyusb/host/usbh_control.c b/arkanoid/pico/tinyusb/host/usbh_control.c
new file mode 100644
index 0000000..5d85b80
--- /dev/null
+++ b/arkanoid/pico/tinyusb/host/usbh_control.c
@@ -0,0 +1,138 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020, Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "../tusb_option.h"
+
+#if TUSB_OPT_HOST_ENABLED
+
+#include "../tusb.h"
+#include "usbh_classdriver.h"
+
+enum
+{
+ STAGE_SETUP,
+ STAGE_DATA,
+ STAGE_ACK
+};
+
+typedef struct
+{
+ tusb_control_request_t request TU_ATTR_ALIGNED(4);
+
+ uint8_t stage;
+ uint8_t* buffer;
+ tuh_control_complete_cb_t complete_cb;
+} usbh_control_xfer_t;
+
+static usbh_control_xfer_t _ctrl_xfer;
+
+//CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+//static uint8_t _tuh_ctrl_buf[CFG_TUH_ENUMERATION_BUFSIZE];
+
+//--------------------------------------------------------------------+
+// MACRO TYPEDEF CONSTANT ENUM DECLARATION
+//--------------------------------------------------------------------+
+
+bool tuh_control_xfer (uint8_t dev_addr, tusb_control_request_t const* request, void* buffer, tuh_control_complete_cb_t complete_cb)
+{
+ // TODO need to claim the endpoint first
+ const uint8_t rhport = usbh_get_rhport(dev_addr);
+
+ _ctrl_xfer.request = (*request);
+ _ctrl_xfer.buffer = buffer;
+ _ctrl_xfer.stage = STAGE_SETUP;
+ _ctrl_xfer.complete_cb = complete_cb;
+
+ TU_LOG2("Control Setup (addr = %u): ", dev_addr);
+ TU_LOG2_VAR(request);
+ TU_LOG2("\r\n");
+
+ // Send setup packet
+ TU_ASSERT( hcd_setup_send(rhport, dev_addr, (uint8_t const*) &_ctrl_xfer.request) );
+
+ return true;
+}
+
+static void _xfer_complete(uint8_t dev_addr, xfer_result_t result)
+{
+ TU_LOG2("\r\n");
+ if (_ctrl_xfer.complete_cb) _ctrl_xfer.complete_cb(dev_addr, &_ctrl_xfer.request, result);
+}
+
+bool usbh_control_xfer_cb (uint8_t dev_addr, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+ (void) ep_addr;
+ (void) xferred_bytes;
+
+ const uint8_t rhport = usbh_get_rhport(dev_addr);
+
+ tusb_control_request_t const * request = &_ctrl_xfer.request;
+
+ if (XFER_RESULT_SUCCESS != result)
+ {
+ TU_LOG2("Control failed: result = %d\r\n", result);
+
+ // terminate transfer if any stage failed
+ _xfer_complete(dev_addr, result);
+ }else
+ {
+ switch(_ctrl_xfer.stage)
+ {
+ case STAGE_SETUP:
+ _ctrl_xfer.stage = STAGE_DATA;
+ if (request->wLength)
+ {
+ // DATA stage: initial data toggle is always 1
+ hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, request->bmRequestType_bit.direction), _ctrl_xfer.buffer, request->wLength);
+ return true;
+ }
+ __attribute__((fallthrough));
+
+ case STAGE_DATA:
+ _ctrl_xfer.stage = STAGE_ACK;
+
+ if (request->wLength)
+ {
+ TU_LOG2("Control data (addr = %u):\r\n", dev_addr);
+ TU_LOG2_MEM(_ctrl_xfer.buffer, request->wLength, 2);
+ }
+
+ // ACK stage: toggle is always 1
+ hcd_edpt_xfer(rhport, dev_addr, tu_edpt_addr(0, 1-request->bmRequestType_bit.direction), NULL, 0);
+ break;
+
+ case STAGE_ACK:
+ _xfer_complete(dev_addr, result);
+ break;
+
+ default: return false;
+ }
+ }
+
+ return true;
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/osal.h b/arkanoid/pico/tinyusb/osal.h
new file mode 100644
index 0000000..c2c4688
--- /dev/null
+++ b/arkanoid/pico/tinyusb/osal.h
@@ -0,0 +1,111 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_OSAL_H_
+#define _TUSB_OSAL_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/** \addtogroup group_osal
+ * @{ */
+
+#include "tusb_common.h"
+
+// Return immediately
+#define OSAL_TIMEOUT_NOTIMEOUT (0)
+// Default timeout
+#define OSAL_TIMEOUT_NORMAL (10)
+// Wait forever
+#define OSAL_TIMEOUT_WAIT_FOREVER (UINT32_MAX)
+
+#define OSAL_TIMEOUT_CONTROL_XFER OSAL_TIMEOUT_WAIT_FOREVER
+
+typedef void (*osal_task_func_t)( void * );
+
+#if CFG_TUSB_OS == OPT_OS_NONE
+ #include "osal_none.h"
+#elif CFG_TUSB_OS == OPT_OS_FREERTOS
+ #include "osal_freertos.h"
+#elif CFG_TUSB_OS == OPT_OS_MYNEWT
+ #include "osal_mynewt.h"
+#elif CFG_TUSB_OS == OPT_OS_PICO
+ #include "osal_pico.h"
+#elif CFG_TUSB_OS == OPT_OS_RTTHREAD
+ #include "osal_rtthread.h"
+#elif CFG_TUSB_OS == OPT_OS_CUSTOM
+ #include "tusb_os_custom.h" // implemented by application
+#else
+ #error OS is not supported yet
+#endif
+
+//--------------------------------------------------------------------+
+// OSAL Porting API
+//--------------------------------------------------------------------+
+
+#if __GNUC__
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wredundant-decls"
+#endif
+//------------- Semaphore -------------//
+static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef);
+static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr);
+static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec);
+
+static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl); // TODO removed
+
+//------------- Mutex -------------//
+static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef);
+static inline bool osal_mutex_lock (osal_mutex_t sem_hdl, uint32_t msec);
+static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl);
+
+//------------- Queue -------------//
+static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef);
+static inline bool osal_queue_receive(osal_queue_t qhdl, void* data);
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr);
+static inline bool osal_queue_empty(osal_queue_t qhdl);
+#if __GNUC__
+#pragma GCC diagnostic pop
+#endif
+
+#if 0 // TODO remove subtask related macros later
+// Sub Task
+#define OSAL_SUBTASK_BEGIN
+#define OSAL_SUBTASK_END return TUSB_ERROR_NONE;
+
+#define STASK_RETURN(_error) return _error;
+#define STASK_INVOKE(_subtask, _status) (_status) = _subtask
+#define STASK_ASSERT(_cond) TU_VERIFY(_cond, TUSB_ERROR_OSAL_TASK_FAILED)
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+/** @} */
+
+#endif /* _TUSB_OSAL_H_ */
diff --git a/arkanoid/pico/tinyusb/osal_freertos.h b/arkanoid/pico/tinyusb/osal_freertos.h
new file mode 100644
index 0000000..e2b9f19
--- /dev/null
+++ b/arkanoid/pico/tinyusb/osal_freertos.h
@@ -0,0 +1,172 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_OSAL_FREERTOS_H_
+#define _TUSB_OSAL_FREERTOS_H_
+
+// FreeRTOS Headers
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,FreeRTOS.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,semphr.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,queue.h)
+#include TU_INCLUDE_PATH(CFG_TUSB_OS_INC_PATH,task.h)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+static inline void osal_task_delay(uint32_t msec)
+{
+ vTaskDelay( pdMS_TO_TICKS(msec) );
+}
+
+//--------------------------------------------------------------------+
+// Semaphore API
+//--------------------------------------------------------------------+
+typedef StaticSemaphore_t osal_semaphore_def_t;
+typedef SemaphoreHandle_t osal_semaphore_t;
+
+static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+{
+ return xSemaphoreCreateBinaryStatic(semdef);
+}
+
+static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+{
+ if ( !in_isr )
+ {
+ return xSemaphoreGive(sem_hdl) != 0;
+ }
+ else
+ {
+ BaseType_t xHigherPriorityTaskWoken;
+ BaseType_t res = xSemaphoreGiveFromISR(sem_hdl, &xHigherPriorityTaskWoken);
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+ if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
+#else
+ portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+#endif
+
+ return res != 0;
+ }
+}
+
+static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+{
+ uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? portMAX_DELAY : pdMS_TO_TICKS(msec);
+ return xSemaphoreTake(sem_hdl, ticks);
+}
+
+static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl)
+{
+ xQueueReset(sem_hdl);
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API (priority inheritance)
+//--------------------------------------------------------------------+
+typedef StaticSemaphore_t osal_mutex_def_t;
+typedef SemaphoreHandle_t osal_mutex_t;
+
+static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+{
+ return xSemaphoreCreateMutexStatic(mdef);
+}
+
+static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+{
+ return osal_semaphore_wait(mutex_hdl, msec);
+}
+
+static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+{
+ return xSemaphoreGive(mutex_hdl);
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+
+// role host is used by OS NONE for mutex (disable usb isr) only
+#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+ static _type _name##_##buf[_depth];\
+ osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+
+typedef struct
+{
+ uint16_t depth;
+ uint16_t item_sz;
+ void* buf;
+
+ StaticQueue_t sq;
+}osal_queue_def_t;
+
+typedef QueueHandle_t osal_queue_t;
+
+static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+{
+ return xQueueCreateStatic(qdef->depth, qdef->item_sz, (uint8_t*) qdef->buf, &qdef->sq);
+}
+
+static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+{
+ return xQueueReceive(qhdl, data, portMAX_DELAY);
+}
+
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+{
+ if ( !in_isr )
+ {
+ return xQueueSendToBack(qhdl, data, OSAL_TIMEOUT_WAIT_FOREVER) != 0;
+ }
+ else
+ {
+ BaseType_t xHigherPriorityTaskWoken;
+ BaseType_t res = xQueueSendToBackFromISR(qhdl, data, &xHigherPriorityTaskWoken);
+
+#if CFG_TUSB_MCU == OPT_MCU_ESP32S2 || CFG_TUSB_MCU == OPT_MCU_ESP32S3
+ if ( xHigherPriorityTaskWoken ) portYIELD_FROM_ISR();
+#else
+ portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
+#endif
+
+ return res != 0;
+ }
+}
+
+static inline bool osal_queue_empty(osal_queue_t qhdl)
+{
+ return uxQueueMessagesWaiting(qhdl) == 0;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_OSAL_FREERTOS_H_ */
diff --git a/arkanoid/pico/tinyusb/osal_mynewt.h b/arkanoid/pico/tinyusb/osal_mynewt.h
new file mode 100644
index 0000000..34dfc7e
--- /dev/null
+++ b/arkanoid/pico/tinyusb/osal_mynewt.h
@@ -0,0 +1,174 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef OSAL_MYNEWT_H_
+#define OSAL_MYNEWT_H_
+
+#include "os/os.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+static inline void osal_task_delay(uint32_t msec)
+{
+ os_time_delay( os_time_ms_to_ticks32(msec) );
+}
+
+//--------------------------------------------------------------------+
+// Semaphore API
+//--------------------------------------------------------------------+
+typedef struct os_sem osal_semaphore_def_t;
+typedef struct os_sem* osal_semaphore_t;
+
+static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+{
+ return (os_sem_init(semdef, 0) == OS_OK) ? (osal_semaphore_t) semdef : NULL;
+}
+
+static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+{
+ (void) in_isr;
+ return os_sem_release(sem_hdl) == OS_OK;
+}
+
+static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec)
+{
+ uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
+ return os_sem_pend(sem_hdl, ticks) == OS_OK;
+}
+
+static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
+{
+ // TODO implement later
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API (priority inheritance)
+//--------------------------------------------------------------------+
+typedef struct os_mutex osal_mutex_def_t;
+typedef struct os_mutex* osal_mutex_t;
+
+static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+{
+ return (os_mutex_init(mdef) == OS_OK) ? (osal_mutex_t) mdef : NULL;
+}
+
+static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec)
+{
+ uint32_t const ticks = (msec == OSAL_TIMEOUT_WAIT_FOREVER) ? OS_TIMEOUT_NEVER : os_time_ms_to_ticks32(msec);
+ return os_mutex_pend(mutex_hdl, ticks) == OS_OK;
+}
+
+static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+{
+ return os_mutex_release(mutex_hdl) == OS_OK;
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+
+// role host is used by OS NONE for mutex (disable usb isr) only
+#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+ static _type _name##_##buf[_depth];\
+ static struct os_event _name##_##evbuf[_depth];\
+ osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf, .evbuf = _name##_##evbuf};\
+
+typedef struct
+{
+ uint16_t depth;
+ uint16_t item_sz;
+ void* buf;
+ void* evbuf;
+
+ struct os_mempool mpool;
+ struct os_mempool epool;
+
+ struct os_eventq evq;
+}osal_queue_def_t;
+
+typedef osal_queue_def_t* osal_queue_t;
+
+static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+{
+ if ( OS_OK != os_mempool_init(&qdef->mpool, qdef->depth, qdef->item_sz, qdef->buf, "usbd queue") ) return NULL;
+ if ( OS_OK != os_mempool_init(&qdef->epool, qdef->depth, sizeof(struct os_event), qdef->evbuf, "usbd evqueue") ) return NULL;
+
+ os_eventq_init(&qdef->evq);
+ return (osal_queue_t) qdef;
+}
+
+static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+{
+ struct os_event* ev;
+ ev = os_eventq_get(&qhdl->evq);
+
+ memcpy(data, ev->ev_arg, qhdl->item_sz); // copy message
+ os_memblock_put(&qhdl->mpool, ev->ev_arg); // put back mem block
+ os_memblock_put(&qhdl->epool, ev); // put back ev block
+
+ return true;
+}
+
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+{
+ (void) in_isr;
+
+ // get a block from mem pool for data
+ void* ptr = os_memblock_get(&qhdl->mpool);
+ if (!ptr) return false;
+ memcpy(ptr, data, qhdl->item_sz);
+
+ // get a block from event pool to put into queue
+ struct os_event* ev = (struct os_event*) os_memblock_get(&qhdl->epool);
+ if (!ev)
+ {
+ os_memblock_put(&qhdl->mpool, ptr);
+ return false;
+ }
+ tu_memclr(ev, sizeof(struct os_event));
+ ev->ev_arg = ptr;
+
+ os_eventq_put(&qhdl->evq, ev);
+
+ return true;
+}
+
+static inline bool osal_queue_empty(osal_queue_t qhdl)
+{
+ return STAILQ_EMPTY(&qhdl->evq.evq_list);
+}
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* OSAL_MYNEWT_H_ */
diff --git a/arkanoid/pico/tinyusb/osal_none.h b/arkanoid/pico/tinyusb/osal_none.h
new file mode 100644
index 0000000..50c8299
--- /dev/null
+++ b/arkanoid/pico/tinyusb/osal_none.h
@@ -0,0 +1,204 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_OSAL_NONE_H_
+#define _TUSB_OSAL_NONE_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+
+
+//--------------------------------------------------------------------+
+// Binary Semaphore API
+//--------------------------------------------------------------------+
+typedef struct
+{
+ volatile uint16_t count;
+}osal_semaphore_def_t;
+
+typedef osal_semaphore_def_t* osal_semaphore_t;
+
+static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+{
+ semdef->count = 0;
+ return semdef;
+}
+
+static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+{
+ (void) in_isr;
+ sem_hdl->count++;
+ return true;
+}
+
+// TODO blocking for now
+static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+{
+ (void) msec;
+
+ while (sem_hdl->count == 0) { }
+ sem_hdl->count--;
+
+ return true;
+}
+
+static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
+{
+ sem_hdl->count = 0;
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API
+// Within tinyusb, mutex is never used in ISR context
+//--------------------------------------------------------------------+
+typedef osal_semaphore_def_t osal_mutex_def_t;
+typedef osal_semaphore_t osal_mutex_t;
+
+static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+{
+ mdef->count = 1;
+ return mdef;
+}
+
+static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+{
+ return osal_semaphore_wait(mutex_hdl, msec);
+}
+
+static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+{
+ return osal_semaphore_post(mutex_hdl, false);
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+#include "tusb_fifo.h"
+
+// extern to avoid including dcd.h and hcd.h
+#if TUSB_OPT_DEVICE_ENABLED
+extern void dcd_int_disable(uint8_t rhport);
+extern void dcd_int_enable(uint8_t rhport);
+#endif
+
+#if TUSB_OPT_HOST_ENABLED
+extern void hcd_int_disable(uint8_t rhport);
+extern void hcd_int_enable(uint8_t rhport);
+#endif
+
+typedef struct
+{
+ uint8_t role; // device or host
+ tu_fifo_t ff;
+}osal_queue_def_t;
+
+typedef osal_queue_def_t* osal_queue_t;
+
+// role host is used by OS NONE for mutex (disable usb isr) only
+#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+ uint8_t _name##_buf[_depth*sizeof(_type)]; \
+ osal_queue_def_t _name = { \
+ .role = _role, \
+ .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
+ }
+
+// lock queue by disable USB interrupt
+static inline void _osal_q_lock(osal_queue_t qhdl)
+{
+ (void) qhdl;
+
+#if TUSB_OPT_DEVICE_ENABLED
+ if (qhdl->role == OPT_MODE_DEVICE) dcd_int_disable(TUD_OPT_RHPORT);
+#endif
+
+#if TUSB_OPT_HOST_ENABLED
+ if (qhdl->role == OPT_MODE_HOST) hcd_int_disable(TUH_OPT_RHPORT);
+#endif
+}
+
+// unlock queue
+static inline void _osal_q_unlock(osal_queue_t qhdl)
+{
+ (void) qhdl;
+
+#if TUSB_OPT_DEVICE_ENABLED
+ if (qhdl->role == OPT_MODE_DEVICE) dcd_int_enable(TUD_OPT_RHPORT);
+#endif
+
+#if TUSB_OPT_HOST_ENABLED
+ if (qhdl->role == OPT_MODE_HOST) hcd_int_enable(TUH_OPT_RHPORT);
+#endif
+}
+
+static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+{
+ tu_fifo_clear(&qdef->ff);
+ return (osal_queue_t) qdef;
+}
+
+static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+{
+ _osal_q_lock(qhdl);
+ bool success = tu_fifo_read(&qhdl->ff, data);
+ _osal_q_unlock(qhdl);
+
+ return success;
+}
+
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+{
+ if (!in_isr) {
+ _osal_q_lock(qhdl);
+ }
+
+ bool success = tu_fifo_write(&qhdl->ff, data);
+
+ if (!in_isr) {
+ _osal_q_unlock(qhdl);
+ }
+
+ TU_ASSERT(success);
+
+ return success;
+}
+
+static inline bool osal_queue_empty(osal_queue_t qhdl)
+{
+ // Skip queue lock/unlock since this function is primarily called
+ // with interrupt disabled before going into low power mode
+ return tu_fifo_empty(&qhdl->ff);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_OSAL_NONE_H_ */
diff --git a/arkanoid/pico/tinyusb/osal_pico.h b/arkanoid/pico/tinyusb/osal_pico.h
new file mode 100644
index 0000000..7008479
--- /dev/null
+++ b/arkanoid/pico/tinyusb/osal_pico.h
@@ -0,0 +1,187 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_OSAL_PICO_H_
+#define _TUSB_OSAL_PICO_H_
+
+#include "../time.h"
+#include "../sem.h"
+#include "../mutex.h"
+#include "../critical_section.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+static inline void osal_task_delay(uint32_t msec)
+{
+ sleep_ms(msec);
+}
+
+//--------------------------------------------------------------------+
+// Binary Semaphore API
+//--------------------------------------------------------------------+
+typedef struct semaphore osal_semaphore_def_t, *osal_semaphore_t;
+
+static inline osal_semaphore_t osal_semaphore_create(osal_semaphore_def_t* semdef)
+{
+ sem_init(semdef, 0, 255);
+ return semdef;
+}
+
+static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr)
+{
+ (void) in_isr;
+ sem_release(sem_hdl);
+ return true;
+}
+
+static inline bool osal_semaphore_wait (osal_semaphore_t sem_hdl, uint32_t msec)
+{
+ return sem_acquire_timeout_ms(sem_hdl, msec);
+}
+
+static inline void osal_semaphore_reset(osal_semaphore_t sem_hdl)
+{
+ sem_reset(sem_hdl, 0);
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API
+// Within tinyusb, mutex is never used in ISR context
+//--------------------------------------------------------------------+
+typedef struct mutex osal_mutex_def_t, *osal_mutex_t;
+
+static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t* mdef)
+{
+ mutex_init(mdef);
+ return mdef;
+}
+
+static inline bool osal_mutex_lock (osal_mutex_t mutex_hdl, uint32_t msec)
+{
+ return mutex_enter_timeout_ms(mutex_hdl, msec);
+}
+
+static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl)
+{
+ mutex_exit(mutex_hdl);
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+#include "tusb_fifo.h"
+
+#if TUSB_OPT_HOST_ENABLED
+extern void hcd_int_disable(uint8_t rhport);
+extern void hcd_int_enable(uint8_t rhport);
+#endif
+
+typedef struct
+{
+ tu_fifo_t ff;
+ struct critical_section critsec; // osal_queue may be used in IRQs, so need critical section
+} osal_queue_def_t;
+
+typedef osal_queue_def_t* osal_queue_t;
+
+// role host is used by OS NONE for mutex (disable usb isr) only
+#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+ uint8_t _name##_buf[_depth*sizeof(_type)]; \
+ osal_queue_def_t _name = { \
+ .ff = TU_FIFO_INIT(_name##_buf, _depth, _type, false) \
+ }
+
+// lock queue by disable USB interrupt
+static inline void _osal_q_lock(osal_queue_t qhdl)
+{
+ critical_section_enter_blocking(&qhdl->critsec);
+}
+
+// unlock queue
+static inline void _osal_q_unlock(osal_queue_t qhdl)
+{
+ critical_section_exit(&qhdl->critsec);
+}
+
+static inline osal_queue_t osal_queue_create(osal_queue_def_t* qdef)
+{
+ critical_section_init(&qdef->critsec);
+ tu_fifo_clear(&qdef->ff);
+ return (osal_queue_t) qdef;
+}
+
+static inline bool osal_queue_receive(osal_queue_t qhdl, void* data)
+{
+ // TODO: revisit... docs say that mutexes are never used from IRQ context,
+ // however osal_queue_recieve may be. therefore my assumption is that
+ // the fifo mutex is not populated for queues used from an IRQ context
+ //assert(!qhdl->ff.mutex);
+
+ _osal_q_lock(qhdl);
+ bool success = tu_fifo_read(&qhdl->ff, data);
+ _osal_q_unlock(qhdl);
+
+ return success;
+}
+
+static inline bool osal_queue_send(osal_queue_t qhdl, void const * data, bool in_isr)
+{
+ // TODO: revisit... docs say that mutexes are never used from IRQ context,
+ // however osal_queue_recieve may be. therefore my assumption is that
+ // the fifo mutex is not populated for queues used from an IRQ context
+ //assert(!qhdl->ff.mutex);
+ (void) in_isr;
+
+ _osal_q_lock(qhdl);
+ bool success = tu_fifo_write(&qhdl->ff, data);
+ _osal_q_unlock(qhdl);
+
+ TU_ASSERT(success);
+
+ return success;
+}
+
+static inline bool osal_queue_empty(osal_queue_t qhdl)
+{
+ // TODO: revisit; whether this is true or not currently, tu_fifo_empty is a single
+ // volatile read.
+
+ // Skip queue lock/unlock since this function is primarily called
+ // with interrupt disabled before going into low power mode
+ return tu_fifo_empty(&qhdl->ff);
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_OSAL_PICO_H_ */
diff --git a/arkanoid/pico/tinyusb/osal_rtthread.h b/arkanoid/pico/tinyusb/osal_rtthread.h
new file mode 100644
index 0000000..da2ab69
--- /dev/null
+++ b/arkanoid/pico/tinyusb/osal_rtthread.h
@@ -0,0 +1,130 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 tfx2001 (2479727366@qq.com)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_OSAL_RTTHREAD_H_
+#define _TUSB_OSAL_RTTHREAD_H_
+
+// RT-Thread Headers
+#include "rtthread.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TASK API
+//--------------------------------------------------------------------+
+static inline void osal_task_delay(uint32_t msec) {
+ rt_thread_mdelay(msec);
+}
+
+//--------------------------------------------------------------------+
+// Semaphore API
+//--------------------------------------------------------------------+
+typedef struct rt_semaphore osal_semaphore_def_t;
+typedef rt_sem_t osal_semaphore_t;
+
+static inline osal_semaphore_t
+osal_semaphore_create(osal_semaphore_def_t *semdef) {
+ rt_sem_init(semdef, "tusb", 0, RT_IPC_FLAG_FIFO);
+ return semdef;
+}
+
+static inline bool osal_semaphore_post(osal_semaphore_t sem_hdl, bool in_isr) {
+ (void) in_isr;
+ return rt_sem_release(sem_hdl) == RT_EOK;
+}
+
+static inline bool osal_semaphore_wait(osal_semaphore_t sem_hdl, uint32_t msec) {
+ return rt_sem_take(sem_hdl, rt_tick_from_millisecond(msec)) == RT_EOK;
+}
+
+static inline void osal_semaphore_reset(osal_semaphore_t const sem_hdl) {
+ // TODO: implement
+}
+
+//--------------------------------------------------------------------+
+// MUTEX API (priority inheritance)
+//--------------------------------------------------------------------+
+typedef struct rt_mutex osal_mutex_def_t;
+typedef rt_mutex_t osal_mutex_t;
+
+static inline osal_mutex_t osal_mutex_create(osal_mutex_def_t *mdef) {
+ rt_mutex_init(mdef, "tusb", RT_IPC_FLAG_FIFO);
+ return mdef;
+}
+
+static inline bool osal_mutex_lock(osal_mutex_t mutex_hdl, uint32_t msec) {
+ return rt_mutex_take(mutex_hdl, rt_tick_from_millisecond(msec)) == RT_EOK;
+}
+
+static inline bool osal_mutex_unlock(osal_mutex_t mutex_hdl) {
+ return rt_mutex_release(mutex_hdl) == RT_EOK;
+}
+
+//--------------------------------------------------------------------+
+// QUEUE API
+//--------------------------------------------------------------------+
+
+// role host is used by OS NONE for mutex (disable usb isr) only
+#define OSAL_QUEUE_DEF(_role, _name, _depth, _type) \
+ static _type _name##_##buf[_depth]; \
+ osal_queue_def_t _name = { .depth = _depth, .item_sz = sizeof(_type), .buf = _name##_##buf };
+
+typedef struct {
+ uint16_t depth;
+ uint16_t item_sz;
+ void *buf;
+
+ struct rt_messagequeue sq;
+} osal_queue_def_t;
+
+typedef rt_mq_t osal_queue_t;
+
+static inline osal_queue_t osal_queue_create(osal_queue_def_t *qdef) {
+ rt_mq_init(&(qdef->sq), "tusb", qdef->buf, qdef->item_sz,
+ qdef->item_sz * qdef->depth, RT_IPC_FLAG_FIFO);
+ return &(qdef->sq);
+}
+
+static inline bool osal_queue_receive(osal_queue_t qhdl, void *data) {
+ return rt_mq_recv(qhdl, data, qhdl->msg_size, RT_WAITING_FOREVER) == RT_EOK;
+}
+
+static inline bool osal_queue_send(osal_queue_t qhdl, void const *data, bool in_isr) {
+ (void) in_isr;
+ return rt_mq_send(qhdl, (void *)data, qhdl->msg_size) == RT_EOK;
+}
+
+static inline bool osal_queue_empty(osal_queue_t qhdl) {
+ return (qhdl->entry) == 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_OSAL_RTTHREAD_H_ */
diff --git a/arkanoid/pico/tinyusb/rp2040_usb.c b/arkanoid/pico/tinyusb/rp2040_usb.c
new file mode 100644
index 0000000..c9e2f6b
--- /dev/null
+++ b/arkanoid/pico/tinyusb/rp2040_usb.c
@@ -0,0 +1,323 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2021 Ha Thach (tinyusb.org) for Double Buffered
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if CFG_TUSB_MCU == OPT_MCU_RP2040
+
+#include <stdlib.h>
+#include "rp2040_usb.h"
+
+// Direction strings for debug
+const char *ep_dir_string[] = {
+ "out",
+ "in",
+};
+
+static inline void _hw_endpoint_lock_update(__unused struct hw_endpoint * ep, __unused int delta) {
+ // todo add critsec as necessary to prevent issues between worker and IRQ...
+ // note that this is perhaps as simple as disabling IRQs because it would make
+ // sense to have worker and IRQ on same core, however I think using critsec is about equivalent.
+}
+
+static void _hw_endpoint_xfer_sync(struct hw_endpoint *ep);
+static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep);
+
+//--------------------------------------------------------------------+
+//
+//--------------------------------------------------------------------+
+
+void rp2040_usb_init(void)
+{
+ // Reset usb controller
+ reset_block(RESETS_RESET_USBCTRL_BITS);
+ unreset_block_wait(RESETS_RESET_USBCTRL_BITS);
+
+ // Clear any previous state just in case
+ memset(usb_hw, 0, sizeof(*usb_hw));
+ memset(usb_dpram, 0, sizeof(*usb_dpram));
+
+ // Mux the controller to the onboard usb phy
+ usb_hw->muxing = USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS;
+}
+
+void hw_endpoint_reset_transfer(struct hw_endpoint *ep)
+{
+ ep->active = false;
+ ep->remaining_len = 0;
+ ep->xferred_len = 0;
+ ep->user_buf = 0;
+}
+
+void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask) {
+ uint32_t value = 0;
+ if (and_mask) {
+ value = *ep->buffer_control & and_mask;
+ }
+ if (or_mask) {
+ value |= or_mask;
+ if (or_mask & USB_BUF_CTRL_AVAIL) {
+ if (*ep->buffer_control & USB_BUF_CTRL_AVAIL) {
+ panic("ep %d %s was already available", tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+ }
+ *ep->buffer_control = value & ~USB_BUF_CTRL_AVAIL;
+ // 12 cycle delay.. (should be good for 48*12Mhz = 576Mhz)
+ // Don't need delay in host mode as host is in charge
+#if !TUSB_OPT_HOST_ENABLED
+ __asm volatile (
+ "b 1f\n"
+ "1: b 1f\n"
+ "1: b 1f\n"
+ "1: b 1f\n"
+ "1: b 1f\n"
+ "1: b 1f\n"
+ "1:\n"
+ : : : "memory");
+#endif
+ }
+ }
+ *ep->buffer_control = value;
+}
+
+// prepare buffer, return buffer control
+static uint32_t prepare_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
+{
+ uint16_t const buflen = tu_min16(ep->remaining_len, ep->wMaxPacketSize);
+ ep->remaining_len = (uint16_t)(ep->remaining_len - buflen);
+
+ uint32_t buf_ctrl = buflen | USB_BUF_CTRL_AVAIL;
+
+ // PID
+ buf_ctrl |= ep->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
+ ep->next_pid ^= 1u;
+
+ if ( !ep->rx )
+ {
+ // Copy data from user buffer to hw buffer
+ memcpy(ep->hw_data_buf + buf_id*64, ep->user_buf, buflen);
+ ep->user_buf += buflen;
+
+ // Mark as full
+ buf_ctrl |= USB_BUF_CTRL_FULL;
+ }
+
+ // Is this the last buffer? Only really matters for host mode. Will trigger
+ // the trans complete irq but also stop it polling. We only really care about
+ // trans complete for setup packets being sent
+ if (ep->remaining_len == 0)
+ {
+ buf_ctrl |= USB_BUF_CTRL_LAST;
+ }
+
+ if (buf_id) buf_ctrl = buf_ctrl << 16;
+
+ return buf_ctrl;
+}
+
+// Prepare buffer control register value
+static void _hw_endpoint_start_next_buffer(struct hw_endpoint *ep)
+{
+ uint32_t ep_ctrl = *ep->endpoint_control;
+
+ // always compute and start with buffer 0
+ uint32_t buf_ctrl = prepare_ep_buffer(ep, 0) | USB_BUF_CTRL_SEL;
+
+ // For now: skip double buffered for Device mode, OUT endpoint since
+ // host could send < 64 bytes and cause short packet on buffer0
+ // NOTE this could happen to Host mode IN endpoint
+ bool const force_single = !(usb_hw->main_ctrl & USB_MAIN_CTRL_HOST_NDEVICE_BITS) && !tu_edpt_dir(ep->ep_addr);
+
+ if(ep->remaining_len && !force_single)
+ {
+ // Use buffer 1 (double buffered) if there is still data
+ // TODO: Isochronous for buffer1 bit-field is different than CBI (control bulk, interrupt)
+
+ buf_ctrl |= prepare_ep_buffer(ep, 1);
+
+ // Set endpoint control double buffered bit if needed
+ ep_ctrl &= ~EP_CTRL_INTERRUPT_PER_BUFFER;
+ ep_ctrl |= EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER;
+ }else
+ {
+ // Single buffered since 1 is enough
+ ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
+ ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
+ }
+
+ *ep->endpoint_control = ep_ctrl;
+
+ TU_LOG(3, " Prepare BufCtrl: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
+
+ // Finally, write to buffer_control which will trigger the transfer
+ // the next time the controller polls this dpram address
+ _hw_endpoint_buffer_control_set_value32(ep, buf_ctrl);
+}
+
+void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len)
+{
+ _hw_endpoint_lock_update(ep, 1);
+
+ if ( ep->active )
+ {
+ // TODO: Is this acceptable for interrupt packets?
+ TU_LOG(1, "WARN: starting new transfer on already active ep %d %s\n", tu_edpt_number(ep->ep_addr),
+ ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+
+ hw_endpoint_reset_transfer(ep);
+ }
+
+ // Fill in info now that we're kicking off the hw
+ ep->remaining_len = total_len;
+ ep->xferred_len = 0;
+ ep->active = true;
+ ep->user_buf = buffer;
+
+ _hw_endpoint_start_next_buffer(ep);
+ _hw_endpoint_lock_update(ep, -1);
+}
+
+// sync endpoint buffer and return transferred bytes
+static uint16_t sync_ep_buffer(struct hw_endpoint *ep, uint8_t buf_id)
+{
+ uint32_t buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
+ if (buf_id) buf_ctrl = buf_ctrl >> 16;
+
+ uint16_t xferred_bytes = buf_ctrl & USB_BUF_CTRL_LEN_MASK;
+
+ if ( !ep->rx )
+ {
+ // We are continuing a transfer here. If we are TX, we have successfully
+ // sent some data can increase the length we have sent
+ assert(!(buf_ctrl & USB_BUF_CTRL_FULL));
+
+ ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
+ }else
+ {
+ // If we have received some data, so can increase the length
+ // we have received AFTER we have copied it to the user buffer at the appropriate offset
+ assert(buf_ctrl & USB_BUF_CTRL_FULL);
+
+ memcpy(ep->user_buf, ep->hw_data_buf + buf_id*64, xferred_bytes);
+ ep->xferred_len = (uint16_t)(ep->xferred_len + xferred_bytes);
+ ep->user_buf += xferred_bytes;
+ }
+
+ // Short packet
+ if (xferred_bytes < ep->wMaxPacketSize)
+ {
+ pico_trace(" Short packet on buffer %d with %u bytes\n", buf_id, xferred_bytes);
+ // Reduce total length as this is last packet
+ ep->remaining_len = 0;
+ }
+
+ return xferred_bytes;
+}
+
+static void _hw_endpoint_xfer_sync (struct hw_endpoint *ep)
+{
+ // Update hw endpoint struct with info from hardware
+ // after a buff status interrupt
+
+ uint32_t __unused buf_ctrl = _hw_endpoint_buffer_control_get_value32(ep);
+ TU_LOG(3, " Sync BufCtrl: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
+
+ // always sync buffer 0
+ uint16_t buf0_bytes = sync_ep_buffer(ep, 0);
+
+ // sync buffer 1 if double buffered
+ if ( (*ep->endpoint_control) & EP_CTRL_DOUBLE_BUFFERED_BITS )
+ {
+ if (buf0_bytes == ep->wMaxPacketSize)
+ {
+ // sync buffer 1 if not short packet
+ sync_ep_buffer(ep, 1);
+ }else
+ {
+ // short packet on buffer 0
+ // TODO couldn't figure out how to handle this case which happen with net_lwip_webserver example
+ // At this time (currently trigger per 2 buffer), the buffer1 is probably filled with data from
+ // the next transfer (not current one). For now we disable double buffered for device OUT
+ // NOTE this could happen to Host IN
+#if 0
+ uint8_t const ep_num = tu_edpt_number(ep->ep_addr);
+ uint8_t const dir = (uint8_t) tu_edpt_dir(ep->ep_addr);
+ uint8_t const ep_id = 2*ep_num + (dir ? 0 : 1);
+
+ // abort queued transfer on buffer 1
+ usb_hw->abort |= TU_BIT(ep_id);
+
+ while ( !(usb_hw->abort_done & TU_BIT(ep_id)) ) {}
+
+ uint32_t ep_ctrl = *ep->endpoint_control;
+ ep_ctrl &= ~(EP_CTRL_DOUBLE_BUFFERED_BITS | EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER);
+ ep_ctrl |= EP_CTRL_INTERRUPT_PER_BUFFER;
+
+ _hw_endpoint_buffer_control_set_value32(ep, 0);
+
+ usb_hw->abort &= ~TU_BIT(ep_id);
+
+ TU_LOG(3, "----SHORT PACKET buffer0 on EP %02X:\r\n", ep->ep_addr);
+ TU_LOG(3, " BufCtrl: [0] = 0x%04u [1] = 0x%04x\r\n", tu_u32_low16(buf_ctrl), tu_u32_high16(buf_ctrl));
+#endif
+ }
+ }
+}
+
+// Returns true if transfer is complete
+bool hw_endpoint_xfer_continue(struct hw_endpoint *ep)
+{
+ _hw_endpoint_lock_update(ep, 1);
+ // Part way through a transfer
+ if (!ep->active)
+ {
+ panic("Can't continue xfer on inactive ep %d %s", tu_edpt_number(ep->ep_addr), ep_dir_string);
+ }
+
+ // Update EP struct from hardware state
+ _hw_endpoint_xfer_sync(ep);
+
+ // Now we have synced our state with the hardware. Is there more data to transfer?
+ // If we are done then notify tinyusb
+ if (ep->remaining_len == 0)
+ {
+ pico_trace("Completed transfer of %d bytes on ep %d %s\n",
+ ep->xferred_len, tu_edpt_number(ep->ep_addr), ep_dir_string[tu_edpt_dir(ep->ep_addr)]);
+ // Notify caller we are done so it can notify the tinyusb stack
+ _hw_endpoint_lock_update(ep, -1);
+ return true;
+ }
+ else
+ {
+ _hw_endpoint_start_next_buffer(ep);
+ }
+
+ _hw_endpoint_lock_update(ep, -1);
+ // More work to do
+ return false;
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/rp2040_usb.h b/arkanoid/pico/tinyusb/rp2040_usb.h
new file mode 100644
index 0000000..4e7432d
--- /dev/null
+++ b/arkanoid/pico/tinyusb/rp2040_usb.h
@@ -0,0 +1,96 @@
+#ifndef RP2040_COMMON_H_
+#define RP2040_COMMON_H_
+
+#if defined(RP2040_USB_HOST_MODE) && defined(RP2040_USB_DEVICE_MODE)
+#error TinyUSB device and host mode not supported at the same time
+#endif
+
+#include "tusb_common.h"
+
+#include "../pico.h"
+#include "../hardware/structs/usb.h"
+#include "../hardware/irq.h"
+#include "../hardware/resets.h"
+
+#if defined(PICO_RP2040_USB_DEVICE_ENUMERATION_FIX) && !defined(TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX)
+#define TUD_OPT_RP2040_USB_DEVICE_ENUMERATION_FIX PICO_RP2040_USB_DEVICE_ENUMERATION_FIX
+#endif
+
+
+#define pico_info(...) TU_LOG(2, __VA_ARGS__)
+#define pico_trace(...) TU_LOG(3, __VA_ARGS__)
+
+// Hardware information per endpoint
+typedef struct hw_endpoint
+{
+ // Is this a valid struct
+ bool configured;
+
+ // Transfer direction (i.e. IN is rx for host but tx for device)
+ // allows us to common up transfer functions
+ bool rx;
+
+ uint8_t ep_addr;
+ uint8_t next_pid;
+
+ // Endpoint control register
+ io_rw_32 *endpoint_control;
+
+ // Buffer control register
+ io_rw_32 *buffer_control;
+
+ // Buffer pointer in usb dpram
+ uint8_t *hw_data_buf;
+
+ // Current transfer information
+ bool active;
+ uint16_t remaining_len;
+ uint16_t xferred_len;
+
+ // User buffer in main memory
+ uint8_t *user_buf;
+
+ // Data needed from EP descriptor
+ uint16_t wMaxPacketSize;
+
+ // Interrupt, bulk, etc
+ uint8_t transfer_type;
+
+#if TUSB_OPT_HOST_ENABLED
+ // Only needed for host
+ uint8_t dev_addr;
+
+ // If interrupt endpoint
+ uint8_t interrupt_num;
+#endif
+} hw_endpoint_t;
+
+void rp2040_usb_init(void);
+
+void hw_endpoint_xfer_start(struct hw_endpoint *ep, uint8_t *buffer, uint16_t total_len);
+bool hw_endpoint_xfer_continue(struct hw_endpoint *ep);
+void hw_endpoint_reset_transfer(struct hw_endpoint *ep);
+
+void _hw_endpoint_buffer_control_update32(struct hw_endpoint *ep, uint32_t and_mask, uint32_t or_mask);
+static inline uint32_t _hw_endpoint_buffer_control_get_value32(struct hw_endpoint *ep) {
+ return *ep->buffer_control;
+}
+static inline void _hw_endpoint_buffer_control_set_value32(struct hw_endpoint *ep, uint32_t value) {
+ return _hw_endpoint_buffer_control_update32(ep, 0, value);
+}
+static inline void _hw_endpoint_buffer_control_set_mask32(struct hw_endpoint *ep, uint32_t value) {
+ return _hw_endpoint_buffer_control_update32(ep, ~value, value);
+}
+static inline void _hw_endpoint_buffer_control_clear_mask32(struct hw_endpoint *ep, uint32_t value) {
+ return _hw_endpoint_buffer_control_update32(ep, ~value, 0);
+}
+
+static inline uintptr_t hw_data_offset(uint8_t *buf)
+{
+ // Remove usb base from buffer pointer
+ return (uintptr_t)buf ^ (uintptr_t)usb_dpram;
+}
+
+extern const char *ep_dir_string[];
+
+#endif
diff --git a/arkanoid/pico/tinyusb/tusb.c b/arkanoid/pico/tinyusb/tusb.c
new file mode 100644
index 0000000..55ca83b
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb.c
@@ -0,0 +1,246 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_HOST_ENABLED || TUSB_OPT_DEVICE_ENABLED
+
+#include "tusb.h"
+
+// TODO clean up
+#if TUSB_OPT_DEVICE_ENABLED
+#include "usbd_pvt.h"
+#endif
+
+bool tusb_init(void)
+{
+#if TUSB_OPT_DEVICE_ENABLED
+ TU_ASSERT ( tud_init(TUD_OPT_RHPORT) ); // init device stack
+#endif
+
+#if TUSB_OPT_HOST_ENABLED
+ TU_ASSERT( tuh_init(TUH_OPT_RHPORT) ); // init host stack
+#endif
+
+ return true;
+}
+
+bool tusb_inited(void)
+{
+ bool ret = false;
+
+#if TUSB_OPT_DEVICE_ENABLED
+ ret = ret || tud_inited();
+#endif
+
+#if TUSB_OPT_HOST_ENABLED
+ ret = ret || tuh_inited();
+#endif
+
+ return ret;
+}
+
+//--------------------------------------------------------------------+
+// Internal Helper for both Host and Device stack
+//--------------------------------------------------------------------+
+
+bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed)
+{
+ uint16_t const max_packet_size = tu_le16toh(desc_ep->wMaxPacketSize.size);
+ TU_LOG2(" Open EP %02X with Size = %u\r\n", desc_ep->bEndpointAddress, max_packet_size);
+
+ switch (desc_ep->bmAttributes.xfer)
+ {
+ case TUSB_XFER_ISOCHRONOUS:
+ {
+ uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 1023);
+ TU_ASSERT(max_packet_size <= spec_size);
+ }
+ break;
+
+ case TUSB_XFER_BULK:
+ if (speed == TUSB_SPEED_HIGH)
+ {
+ // Bulk highspeed must be EXACTLY 512
+ TU_ASSERT(max_packet_size == 512);
+ }else
+ {
+ // TODO Bulk fullspeed can only be 8, 16, 32, 64
+ TU_ASSERT(max_packet_size <= 64);
+ }
+ break;
+
+ case TUSB_XFER_INTERRUPT:
+ {
+ uint16_t const spec_size = (speed == TUSB_SPEED_HIGH ? 1024 : 64);
+ TU_ASSERT(max_packet_size <= spec_size);
+ }
+ break;
+
+ default: return false;
+ }
+
+ return true;
+}
+
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* desc_itf, uint16_t desc_len, uint8_t driver_id)
+{
+ uint8_t const* p_desc = (uint8_t const*) desc_itf;
+ uint16_t len = 0;
+
+ while( len < desc_len )
+ {
+ if ( TUSB_DESC_ENDPOINT == tu_desc_type(p_desc) )
+ {
+ uint8_t const ep_addr = ((tusb_desc_endpoint_t const*) p_desc)->bEndpointAddress;
+
+ TU_LOG(2, " Bind EP %02x to driver id %u\r\n", ep_addr, driver_id);
+ ep2drv[tu_edpt_number(ep_addr)][tu_edpt_dir(ep_addr)] = driver_id;
+ }
+
+ len += (uint16_t) tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+ }
+}
+
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len)
+{
+ uint8_t const* p_desc = (uint8_t const*) desc_itf;
+ uint16_t len = 0;
+
+ while (itf_count--)
+ {
+ // Next on interface desc
+ len += tu_desc_len(desc_itf);
+ p_desc = tu_desc_next(p_desc);
+
+ while (len < max_len)
+ {
+ // return on IAD regardless of itf count
+ if ( tu_desc_type(p_desc) == TUSB_DESC_INTERFACE_ASSOCIATION ) return len;
+
+ if ( (tu_desc_type(p_desc) == TUSB_DESC_INTERFACE) &&
+ ((tusb_desc_interface_t const*) p_desc)->bAlternateSetting == 0 )
+ {
+ break;
+ }
+
+ len += tu_desc_len(p_desc);
+ p_desc = tu_desc_next(p_desc);
+ }
+ }
+
+ return len;
+}
+
+/*------------------------------------------------------------------*/
+/* Debug
+ *------------------------------------------------------------------*/
+#if CFG_TUSB_DEBUG
+#include <ctype.h>
+
+char const* const tusb_strerr[TUSB_ERROR_COUNT] = { ERROR_TABLE(ERROR_STRING) };
+
+static void dump_str_line(uint8_t const* buf, uint16_t count)
+{
+ tu_printf(" |");
+
+ // each line is 16 bytes
+ for(uint16_t i=0; i<count; i++)
+ {
+ const char ch = buf[i];
+ tu_printf("%c", isprint(ch) ? ch : '.');
+ }
+
+ tu_printf("|\r\n");
+}
+
+/* Print out memory contents
+ * - buf : buffer
+ * - count : number of item
+ * - indent: prefix spaces on every line
+ */
+void tu_print_mem(void const *buf, uint32_t count, uint8_t indent)
+{
+ uint8_t const size = 1; // fixed 1 byte for now
+
+ if ( !buf || !count )
+ {
+ tu_printf("NULL\r\n");
+ return;
+ }
+
+ uint8_t const *buf8 = (uint8_t const *) buf;
+
+ char format[] = "%00X";
+ format[2] += 2*size;
+
+ const uint8_t item_per_line = 16 / size;
+
+ for(unsigned int i=0; i<count; i++)
+ {
+ unsigned int value=0;
+
+ if ( i%item_per_line == 0 )
+ {
+ // Print Ascii
+ if ( i != 0 )
+ {
+ dump_str_line(buf8-16, 16);
+ }
+
+ for(uint8_t s=0; s < indent; s++) tu_printf(" ");
+
+ // print offset or absolute address
+ tu_printf("%04X: ", 16*i/item_per_line);
+ }
+
+ memcpy(&value, buf8, size);
+ buf8 += size;
+
+ tu_printf(" ");
+ tu_printf(format, value);
+ }
+
+ // fill up last row to 16 for printing ascii
+ const uint32_t remain = count%16;
+ uint8_t nback = (remain ? remain : 16);
+
+ if ( remain )
+ {
+ for(uint32_t i=0; i< 16-remain; i++)
+ {
+ tu_printf(" ");
+ for(int j=0; j<2*size; j++) tu_printf(" ");
+ }
+ }
+
+ dump_str_line(buf8-nback, nback);
+}
+
+#endif
+
+#endif // host or device enabled
diff --git a/arkanoid/pico/tinyusb/tusb.h b/arkanoid/pico/tinyusb/tusb.h
new file mode 100644
index 0000000..3befa14
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb.h
@@ -0,0 +1,140 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_H_
+#define _TUSB_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// INCLUDE
+//--------------------------------------------------------------------+
+#include "tusb_common.h"
+#include "osal.h"
+#include "tusb_fifo.h"
+
+//------------- HOST -------------//
+#if TUSB_OPT_HOST_ENABLED
+ #include "host/usbh.h"
+
+ #if CFG_TUH_HID
+ #include "hid/hid_host.h"
+ #endif
+
+ #if CFG_TUH_MSC
+ #include "msc/msc_host.h"
+ #endif
+
+ #if CFG_TUH_CDC
+ #include "cdc/cdc_host.h"
+ #endif
+
+ #if CFG_TUH_VENDOR
+ #include "vendor/vendor_host.h"
+ #endif
+
+#endif
+
+//------------- DEVICE -------------//
+#if TUSB_OPT_DEVICE_ENABLED
+ #include "usbd.h"
+
+ #if CFG_TUD_HID
+ #include "hid/hid_device.h"
+ #endif
+
+ #if CFG_TUD_CDC
+ #include "cdc/cdc_device.h"
+ #endif
+
+ #if CFG_TUD_MSC
+ #include "msc/msc_device.h"
+ #endif
+
+ #if CFG_TUD_AUDIO
+ #include "audio/audio_device.h"
+ #endif
+
+ #if CFG_TUD_VIDEO
+ #include "video/video_device.h"
+ #endif
+
+ #if CFG_TUD_MIDI
+ #include "midi/midi_device.h"
+ #endif
+
+ #if CFG_TUD_VENDOR
+ #include "vendor/vendor_device.h"
+ #endif
+
+ #if CFG_TUD_USBTMC
+ #include "usbtmc/usbtmc_device.h"
+ #endif
+
+ #if CFG_TUD_DFU_RUNTIME
+ #include "dfu/dfu_rt_device.h"
+ #endif
+
+ #if CFG_TUD_DFU
+ #include "dfu/dfu_device.h"
+ #endif
+
+ #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
+ #include "net/net_device.h"
+ #endif
+
+ #if CFG_TUD_BTH
+ #include "bth/bth_device.h"
+ #endif
+#endif
+
+
+//--------------------------------------------------------------------+
+// APPLICATION API
+//--------------------------------------------------------------------+
+/** \ingroup group_application_api
+ * @{ */
+
+// Initialize host stack
+// Note: when using with RTOS, this should be called after scheduler/kernel is started.
+// Otherwise it could cause kernel issue since USB IRQ handler does use RTOS queue API.
+bool tusb_init(void);
+
+// Check if stack is initialized
+bool tusb_inited(void);
+
+// TODO
+// bool tusb_teardown(void);
+
+/** @} */
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_H_ */
diff --git a/arkanoid/pico/tinyusb/tusb_common.h b/arkanoid/pico/tinyusb/tusb_common.h
new file mode 100644
index 0000000..fc4d3bc
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_common.h
@@ -0,0 +1,434 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_COMMON_H_
+#define _TUSB_COMMON_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Macros Helper
+//--------------------------------------------------------------------+
+#define TU_ARRAY_SIZE(_arr) ( sizeof(_arr) / sizeof(_arr[0]) )
+#define TU_MIN(_x, _y) ( ( (_x) < (_y) ) ? (_x) : (_y) )
+#define TU_MAX(_x, _y) ( ( (_x) > (_y) ) ? (_x) : (_y) )
+
+#define TU_U16_HIGH(_u16) ((uint8_t) (((_u16) >> 8) & 0x00ff))
+#define TU_U16_LOW(_u16) ((uint8_t) ((_u16) & 0x00ff))
+#define U16_TO_U8S_BE(_u16) TU_U16_HIGH(_u16), TU_U16_LOW(_u16)
+#define U16_TO_U8S_LE(_u16) TU_U16_LOW(_u16), TU_U16_HIGH(_u16)
+
+#define TU_U32_BYTE3(_u32) ((uint8_t) ((((uint32_t) _u32) >> 24) & 0x000000ff)) // MSB
+#define TU_U32_BYTE2(_u32) ((uint8_t) ((((uint32_t) _u32) >> 16) & 0x000000ff))
+#define TU_U32_BYTE1(_u32) ((uint8_t) ((((uint32_t) _u32) >> 8) & 0x000000ff))
+#define TU_U32_BYTE0(_u32) ((uint8_t) (((uint32_t) _u32) & 0x000000ff)) // LSB
+
+#define U32_TO_U8S_BE(_u32) TU_U32_BYTE3(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE0(_u32)
+#define U32_TO_U8S_LE(_u32) TU_U32_BYTE0(_u32), TU_U32_BYTE1(_u32), TU_U32_BYTE2(_u32), TU_U32_BYTE3(_u32)
+
+#define TU_BIT(n) (1UL << (n))
+
+//--------------------------------------------------------------------+
+// Includes
+//--------------------------------------------------------------------+
+
+// Standard Headers
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdio.h>
+
+// Tinyusb Common Headers
+#include "tusb_option.h"
+#include "tusb_compiler.h"
+#include "tusb_verify.h"
+#include "tusb_types.h"
+
+#include "tusb_error.h" // TODO remove
+#include "tusb_timeout.h" // TODO remove
+
+//--------------------------------------------------------------------+
+// Internal Helper used by Host and Device Stack
+//--------------------------------------------------------------------+
+
+// Check if endpoint descriptor is valid per USB specs
+bool tu_edpt_validate(tusb_desc_endpoint_t const * desc_ep, tusb_speed_t speed);
+
+// Bind all endpoint of a interface descriptor to class driver
+void tu_edpt_bind_driver(uint8_t ep2drv[][2], tusb_desc_interface_t const* p_desc, uint16_t desc_len, uint8_t driver_id);
+
+// Calculate total length of n interfaces (depending on IAD)
+uint16_t tu_desc_get_interface_total_len(tusb_desc_interface_t const* desc_itf, uint8_t itf_count, uint16_t max_len);
+
+//--------------------------------------------------------------------+
+// Internal Inline Functions
+//--------------------------------------------------------------------+
+
+//------------- Mem -------------//
+#define tu_memclr(buffer, size) memset((buffer), 0, (size))
+#define tu_varclr(_var) tu_memclr(_var, sizeof(*(_var)))
+
+//------------- Bytes -------------//
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_u32(uint8_t b3, uint8_t b2, uint8_t b1, uint8_t b0)
+{
+ return ( ((uint32_t) b3) << 24) | ( ((uint32_t) b2) << 16) | ( ((uint32_t) b1) << 8) | b0;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_u16(uint8_t high, uint8_t low)
+{
+ return (uint16_t) ((((uint16_t) high) << 8) | low);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte3(uint32_t ui32) { return TU_U32_BYTE3(ui32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte2(uint32_t ui32) { return TU_U32_BYTE2(ui32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte1(uint32_t ui32) { return TU_U32_BYTE1(ui32); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u32_byte0(uint32_t ui32) { return TU_U32_BYTE0(ui32); }
+
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_high(uint16_t ui16) { return TU_U16_HIGH(ui16); }
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_u16_low (uint16_t ui16) { return TU_U16_LOW(ui16); }
+
+//------------- Bits -------------//
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_set (uint32_t value, uint8_t pos) { return value | TU_BIT(pos); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_bit_clear(uint32_t value, uint8_t pos) { return value & (~TU_BIT(pos)); }
+TU_ATTR_ALWAYS_INLINE static inline bool tu_bit_test (uint32_t value, uint8_t pos) { return (value & TU_BIT(pos)) ? true : false; }
+
+//------------- Min -------------//
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_min8 (uint8_t x, uint8_t y ) { return (x < y) ? x : y; }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_min16 (uint16_t x, uint16_t y) { return (x < y) ? x : y; }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_min32 (uint32_t x, uint32_t y) { return (x < y) ? x : y; }
+
+//------------- Max -------------//
+TU_ATTR_ALWAYS_INLINE static inline uint8_t tu_max8 (uint8_t x, uint8_t y ) { return (x > y) ? x : y; }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_max16 (uint16_t x, uint16_t y) { return (x > y) ? x : y; }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_max32 (uint32_t x, uint32_t y) { return (x > y) ? x : y; }
+
+//------------- Align -------------//
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align(uint32_t value, uint32_t alignment)
+{
+ return value & ((uint32_t) ~(alignment-1));
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align16 (uint32_t value) { return (value & 0xFFFFFFF0UL); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align32 (uint32_t value) { return (value & 0xFFFFFFE0UL); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_align4k (uint32_t value) { return (value & 0xFFFFF000UL); }
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_offset4k(uint32_t value) { return (value & 0xFFFUL); }
+
+//------------- Mathematics -------------//
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_div_ceil(uint32_t v, uint32_t d) { return (v + d -1)/d; }
+
+/// inclusive range checking TODO remove
+TU_ATTR_ALWAYS_INLINE static inline bool tu_within(uint32_t lower, uint32_t value, uint32_t upper)
+{
+ return (lower <= value) && (value <= upper);
+}
+
+// log2 of a value is its MSB's position
+// TODO use clz TODO remove
+static inline uint8_t tu_log2(uint32_t value)
+{
+ uint8_t result = 0;
+ while (value >>= 1) { result++; }
+ return result;
+}
+
+//------------- Unaligned Access -------------//
+#if TUP_ARCH_STRICT_ALIGN
+
+// Rely on compiler to generate correct code for unaligned access
+
+typedef struct { uint16_t val; } TU_ATTR_PACKED tu_unaligned_uint16_t;
+typedef struct { uint32_t val; } TU_ATTR_PACKED tu_unaligned_uint32_t;
+
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void* mem)
+{
+ tu_unaligned_uint32_t const* ua32 = (tu_unaligned_uint32_t const*) mem;
+ return ua32->val;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void* mem, uint32_t value)
+{
+ tu_unaligned_uint32_t* ua32 = (tu_unaligned_uint32_t*) mem;
+ ua32->val = value;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void* mem)
+{
+ tu_unaligned_uint16_t const* ua16 = (tu_unaligned_uint16_t const*) mem;
+ return ua16->val;
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_t value)
+{
+ tu_unaligned_uint16_t* ua16 = (tu_unaligned_uint16_t*) mem;
+ ua16->val = value;
+}
+
+#elif TUP_MCU_STRICT_ALIGN
+
+// MCU such as LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM although it is ARM M4.
+// We have to manually pick up bytes since tu_unaligned_uint32_t will still generate unaligned code
+// NOTE: volatile cast to memory to prevent compiler to optimize and generate unaligned code
+// TODO Big Endian may need minor changes
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32(const void* mem)
+{
+ volatile uint8_t const* buf8 = (uint8_t const*) mem;
+ return tu_u32(buf8[3], buf8[2], buf8[1], buf8[0]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32(void* mem, uint32_t value)
+{
+ volatile uint8_t* buf8 = (uint8_t*) mem;
+ buf8[0] = tu_u32_byte0(value);
+ buf8[1] = tu_u32_byte1(value);
+ buf8[2] = tu_u32_byte2(value);
+ buf8[3] = tu_u32_byte3(value);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16(const void* mem)
+{
+ volatile uint8_t const* buf8 = (uint8_t const*) mem;
+ return tu_u16(buf8[1], buf8[0]);
+}
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16(void* mem, uint16_t value)
+{
+ volatile uint8_t* buf8 = (uint8_t*) mem;
+ buf8[0] = tu_u16_low(value);
+ buf8[1] = tu_u16_high(value);
+}
+
+
+#else
+
+// MCU that could access unaligned memory natively
+TU_ATTR_ALWAYS_INLINE static inline uint32_t tu_unaligned_read32 (const void* mem ) { return *((uint32_t*) mem); }
+TU_ATTR_ALWAYS_INLINE static inline uint16_t tu_unaligned_read16 (const void* mem ) { return *((uint16_t*) mem); }
+
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write32 (void* mem, uint32_t value ) { *((uint32_t*) mem) = value; }
+TU_ATTR_ALWAYS_INLINE static inline void tu_unaligned_write16 (void* mem, uint16_t value ) { *((uint16_t*) mem) = value; }
+
+#endif
+
+/*------------------------------------------------------------------*/
+/* Count number of arguments of __VA_ARGS__
+ * - reference https://groups.google.com/forum/#!topic/comp.std.c/d-6Mj5Lko_s
+ * - _GET_NTH_ARG() takes args >= N (64) but only expand to Nth one (64th)
+ * - _RSEQ_N() is reverse sequential to N to add padding to have
+ * Nth position is the same as the number of arguments
+ * - ##__VA_ARGS__ is used to deal with 0 paramerter (swallows comma)
+ *------------------------------------------------------------------*/
+#ifndef TU_ARGS_NUM
+
+#define TU_ARGS_NUM(...) _TU_NARG(_0, ##__VA_ARGS__,_RSEQ_N())
+
+#define _TU_NARG(...) _GET_NTH_ARG(__VA_ARGS__)
+#define _GET_NTH_ARG( \
+ _1, _2, _3, _4, _5, _6, _7, _8, _9,_10, \
+ _11,_12,_13,_14,_15,_16,_17,_18,_19,_20, \
+ _21,_22,_23,_24,_25,_26,_27,_28,_29,_30, \
+ _31,_32,_33,_34,_35,_36,_37,_38,_39,_40, \
+ _41,_42,_43,_44,_45,_46,_47,_48,_49,_50, \
+ _51,_52,_53,_54,_55,_56,_57,_58,_59,_60, \
+ _61,_62,_63,N,...) N
+#define _RSEQ_N() \
+ 62,61,60, \
+ 59,58,57,56,55,54,53,52,51,50, \
+ 49,48,47,46,45,44,43,42,41,40, \
+ 39,38,37,36,35,34,33,32,31,30, \
+ 29,28,27,26,25,24,23,22,21,20, \
+ 19,18,17,16,15,14,13,12,11,10, \
+ 9,8,7,6,5,4,3,2,1,0
+#endif
+
+// To be removed
+//------------- Binary constant -------------//
+#if defined(__GNUC__) && !defined(__CC_ARM)
+
+#define TU_BIN8(x) ((uint8_t) (0b##x))
+#define TU_BIN16(b1, b2) ((uint16_t) (0b##b1##b2))
+#define TU_BIN32(b1, b2, b3, b4) ((uint32_t) (0b##b1##b2##b3##b4))
+
+#else
+
+// internal macro of B8, B16, B32
+#define _B8__(x) (((x&0x0000000FUL)?1:0) \
+ +((x&0x000000F0UL)?2:0) \
+ +((x&0x00000F00UL)?4:0) \
+ +((x&0x0000F000UL)?8:0) \
+ +((x&0x000F0000UL)?16:0) \
+ +((x&0x00F00000UL)?32:0) \
+ +((x&0x0F000000UL)?64:0) \
+ +((x&0xF0000000UL)?128:0))
+
+#define TU_BIN8(d) ((uint8_t) _B8__(0x##d##UL))
+#define TU_BIN16(dmsb,dlsb) (((uint16_t)TU_BIN8(dmsb)<<8) + TU_BIN8(dlsb))
+#define TU_BIN32(dmsb,db2,db3,dlsb) \
+ (((uint32_t)TU_BIN8(dmsb)<<24) \
+ + ((uint32_t)TU_BIN8(db2)<<16) \
+ + ((uint32_t)TU_BIN8(db3)<<8) \
+ + TU_BIN8(dlsb))
+#endif
+
+//--------------------------------------------------------------------+
+// Debug Function
+//--------------------------------------------------------------------+
+
+// CFG_TUSB_DEBUG for debugging
+// 0 : no debug
+// 1 : print error
+// 2 : print warning
+// 3 : print info
+#if CFG_TUSB_DEBUG
+
+void tu_print_mem(void const *buf, uint32_t count, uint8_t indent);
+
+#ifdef CFG_TUSB_DEBUG_PRINTF
+ extern int CFG_TUSB_DEBUG_PRINTF(const char *format, ...);
+ #define tu_printf CFG_TUSB_DEBUG_PRINTF
+#else
+ #define tu_printf printf
+#endif
+
+static inline
+void tu_print_var(uint8_t const* buf, uint32_t bufsize)
+{
+ for(uint32_t i=0; i<bufsize; i++) tu_printf("%02X ", buf[i]);
+}
+
+// Log with Level
+#define TU_LOG(n, ...) TU_XSTRCAT(TU_LOG, n)(__VA_ARGS__)
+#define TU_LOG_MEM(n, ...) TU_XSTRCAT3(TU_LOG, n, _MEM)(__VA_ARGS__)
+#define TU_LOG_VAR(n, ...) TU_XSTRCAT3(TU_LOG, n, _VAR)(__VA_ARGS__)
+#define TU_LOG_INT(n, ...) TU_XSTRCAT3(TU_LOG, n, _INT)(__VA_ARGS__)
+#define TU_LOG_HEX(n, ...) TU_XSTRCAT3(TU_LOG, n, _HEX)(__VA_ARGS__)
+#define TU_LOG_LOCATION() tu_printf("%s: %d:\r\n", __PRETTY_FUNCTION__, __LINE__)
+#define TU_LOG_FAILED() tu_printf("%s: %d: Failed\r\n", __PRETTY_FUNCTION__, __LINE__)
+
+// Log Level 1: Error
+#define TU_LOG1 tu_printf
+#define TU_LOG1_MEM tu_print_mem
+#define TU_LOG1_VAR(_x) tu_print_var((uint8_t const*)(_x), sizeof(*(_x)))
+#define TU_LOG1_INT(_x) tu_printf(#_x " = %ld\r\n", (uint32_t) (_x) )
+#define TU_LOG1_HEX(_x) tu_printf(#_x " = %lX\r\n", (uint32_t) (_x) )
+
+// Log Level 2: Warn
+#if CFG_TUSB_DEBUG >= 2
+ #define TU_LOG2 TU_LOG1
+ #define TU_LOG2_MEM TU_LOG1_MEM
+ #define TU_LOG2_VAR TU_LOG1_VAR
+ #define TU_LOG2_INT TU_LOG1_INT
+ #define TU_LOG2_HEX TU_LOG1_HEX
+#endif
+
+// Log Level 3: Info
+#if CFG_TUSB_DEBUG >= 3
+ #define TU_LOG3 TU_LOG1
+ #define TU_LOG3_MEM TU_LOG1_MEM
+ #define TU_LOG3_VAR TU_LOG1_VAR
+ #define TU_LOG3_INT TU_LOG1_INT
+ #define TU_LOG3_HEX TU_LOG1_HEX
+#endif
+
+typedef struct
+{
+ uint32_t key;
+ const char* data;
+} tu_lookup_entry_t;
+
+typedef struct
+{
+ uint16_t count;
+ tu_lookup_entry_t const* items;
+} tu_lookup_table_t;
+
+static inline const char* tu_lookup_find(tu_lookup_table_t const* p_table, uint32_t key)
+{
+ static char not_found[11];
+
+ for(uint16_t i=0; i<p_table->count; i++)
+ {
+ if (p_table->items[i].key == key) return p_table->items[i].data;
+ }
+
+ // not found return the key value in hex
+ sprintf(not_found, "0x%08lX", (unsigned long) key);
+
+ return not_found;
+}
+
+#endif // CFG_TUSB_DEBUG
+
+#ifndef TU_LOG
+#define TU_LOG(n, ...)
+#define TU_LOG_MEM(n, ...)
+#define TU_LOG_VAR(n, ...)
+#define TU_LOG_INT(n, ...)
+#define TU_LOG_HEX(n, ...)
+#define TU_LOG_LOCATION()
+#define TU_LOG_FAILED()
+#endif
+
+// TODO replace all TU_LOGn with TU_LOG(n)
+
+#define TU_LOG0(...)
+#define TU_LOG0_MEM(...)
+#define TU_LOG0_VAR(...)
+#define TU_LOG0_INT(...)
+#define TU_LOG0_HEX(...)
+
+
+#ifndef TU_LOG1
+ #define TU_LOG1(...)
+ #define TU_LOG1_MEM(...)
+ #define TU_LOG1_VAR(...)
+ #define TU_LOG1_INT(...)
+ #define TU_LOG1_HEX(...)
+#endif
+
+#ifndef TU_LOG2
+ #define TU_LOG2(...)
+ #define TU_LOG2_MEM(...)
+ #define TU_LOG2_VAR(...)
+ #define TU_LOG2_INT(...)
+ #define TU_LOG2_HEX(...)
+#endif
+
+#ifndef TU_LOG3
+ #define TU_LOG3(...)
+ #define TU_LOG3_MEM(...)
+ #define TU_LOG3_VAR(...)
+ #define TU_LOG3_INT(...)
+ #define TU_LOG3_HEX(...)
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_COMMON_H_ */
diff --git a/arkanoid/pico/tinyusb/tusb_compiler.h b/arkanoid/pico/tinyusb/tusb_compiler.h
new file mode 100644
index 0000000..3e85939
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_compiler.h
@@ -0,0 +1,218 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup Group_Common
+ * \defgroup Group_Compiler Compiler
+ * \brief Group_Compiler brief
+ * @{ */
+
+#ifndef _TUSB_COMPILER_H_
+#define _TUSB_COMPILER_H_
+
+#define TU_TOKEN(x) x
+#define TU_STRING(x) #x ///< stringify without expand
+#define TU_XSTRING(x) TU_STRING(x) ///< expand then stringify
+
+#define TU_STRCAT(a, b) a##b ///< concat without expand
+#define TU_STRCAT3(a, b, c) a##b##c ///< concat without expand
+
+#define TU_XSTRCAT(a, b) TU_STRCAT(a, b) ///< expand then concat
+#define TU_XSTRCAT3(a, b, c) TU_STRCAT3(a, b, c) ///< expand then concat 3 tokens
+
+#define TU_INCLUDE_PATH(_dir,_file) TU_XSTRING( TU_TOKEN(_dir)TU_TOKEN(_file) )
+
+#if defined __COUNTER__ && __COUNTER__ != __COUNTER__
+ #define _TU_COUNTER_ __COUNTER__
+#else
+ #define _TU_COUNTER_ __LINE__
+#endif
+
+// Compile-time Assert
+#if defined (__STDC_VERSION__) && __STDC_VERSION__ >= 201112L
+ #define TU_VERIFY_STATIC _Static_assert
+#elif defined (__cplusplus) && __cplusplus >= 201103L
+ #define TU_VERIFY_STATIC static_assert
+#elif defined(__CCRX__)
+ #define TU_VERIFY_STATIC(const_expr, _mess) typedef char TU_XSTRCAT(Line, __LINE__)[(const_expr) ? 1 : 0];
+#else
+ #define TU_VERIFY_STATIC(const_expr, _mess) enum { TU_XSTRCAT(_verify_static_, _TU_COUNTER_) = 1/(!!(const_expr)) }
+#endif
+
+// for declaration of reserved field, make use of _TU_COUNTER_
+#define TU_RESERVED TU_XSTRCAT(reserved, _TU_COUNTER_)
+
+#define TU_LITTLE_ENDIAN (0x12u)
+#define TU_BIG_ENDIAN (0x21u)
+
+//--------------------------------------------------------------------+
+// Compiler porting with Attribute and Endian
+//--------------------------------------------------------------------+
+
+// TODO refactor since __attribute__ is supported across many compiler
+#if defined(__GNUC__)
+ #define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
+ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name)))
+ #define TU_ATTR_PACKED __attribute__ ((packed))
+ #define TU_ATTR_WEAK __attribute__ ((weak))
+ #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline))
+ #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
+ #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused
+ #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used
+
+ #define TU_ATTR_PACKED_BEGIN
+ #define TU_ATTR_PACKED_END
+ #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
+ #define TU_ATTR_BIT_FIELD_ORDER_END
+
+ // Endian conversion use well-known host to network (big endian) naming
+ #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
+ #else
+ #define TU_BYTE_ORDER TU_BIG_ENDIAN
+ #endif
+
+ #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
+ #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
+
+ // List of obsolete callback function that is renamed and should not be defined.
+ // Put it here since only gcc support this pragma
+ #pragma GCC poison tud_vendor_control_request_cb
+
+#elif defined(__TI_COMPILER_VERSION__)
+ #define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
+ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name)))
+ #define TU_ATTR_PACKED __attribute__ ((packed))
+ #define TU_ATTR_WEAK __attribute__ ((weak))
+ #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline))
+ #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
+ #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused
+ #define TU_ATTR_USED __attribute__ ((used))
+
+ #define TU_ATTR_PACKED_BEGIN
+ #define TU_ATTR_PACKED_END
+ #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
+ #define TU_ATTR_BIT_FIELD_ORDER_END
+
+ // __BYTE_ORDER is defined in the TI ARM compiler, but not MSP430 (which is little endian)
+ #if ((__BYTE_ORDER__) == (__ORDER_LITTLE_ENDIAN__)) || defined(__MSP430__)
+ #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
+ #else
+ #define TU_BYTE_ORDER TU_BIG_ENDIAN
+ #endif
+
+ #define TU_BSWAP16(u16) (__builtin_bswap16(u16))
+ #define TU_BSWAP32(u32) (__builtin_bswap32(u32))
+
+#elif defined(__ICCARM__)
+ #include <intrinsics.h>
+ #define TU_ATTR_ALIGNED(Bytes) __attribute__ ((aligned(Bytes)))
+ #define TU_ATTR_SECTION(sec_name) __attribute__ ((section(#sec_name)))
+ #define TU_ATTR_PACKED __attribute__ ((packed))
+ #define TU_ATTR_WEAK __attribute__ ((weak))
+ #define TU_ATTR_ALWAYS_INLINE __attribute__ ((always_inline))
+ #define TU_ATTR_DEPRECATED(mess) __attribute__ ((deprecated(mess))) // warn if function with this attribute is used
+ #define TU_ATTR_UNUSED __attribute__ ((unused)) // Function/Variable is meant to be possibly unused
+ #define TU_ATTR_USED __attribute__ ((used)) // Function/Variable is meant to be used
+
+ #define TU_ATTR_PACKED_BEGIN
+ #define TU_ATTR_PACKED_END
+ #define TU_ATTR_BIT_FIELD_ORDER_BEGIN
+ #define TU_ATTR_BIT_FIELD_ORDER_END
+
+ // Endian conversion use well-known host to network (big endian) naming
+ #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+ #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
+ #else
+ #define TU_BYTE_ORDER TU_BIG_ENDIAN
+ #endif
+
+ #define TU_BSWAP16(u16) (__iar_builtin_REV16(u16))
+ #define TU_BSWAP32(u32) (__iar_builtin_REV(u32))
+
+#elif defined(__CCRX__)
+ #define TU_ATTR_ALIGNED(Bytes)
+ #define TU_ATTR_SECTION(sec_name)
+ #define TU_ATTR_PACKED
+ #define TU_ATTR_WEAK
+ #define TU_ATTR_ALWAYS_INLINE
+ #define TU_ATTR_DEPRECATED(mess)
+ #define TU_ATTR_UNUSED
+ #define TU_ATTR_USED
+
+ #define TU_ATTR_PACKED_BEGIN _Pragma("pack")
+ #define TU_ATTR_PACKED_END _Pragma("packoption")
+ #define TU_ATTR_BIT_FIELD_ORDER_BEGIN _Pragma("bit_order right")
+ #define TU_ATTR_BIT_FIELD_ORDER_END _Pragma("bit_order")
+
+ // Endian conversion use well-known host to network (big endian) naming
+ #if defined(__LIT)
+ #define TU_BYTE_ORDER TU_LITTLE_ENDIAN
+ #else
+ #define TU_BYTE_ORDER TU_BIG_ENDIAN
+ #endif
+
+ #define TU_BSWAP16(u16) ((unsigned short)_builtin_revw((unsigned long)u16))
+ #define TU_BSWAP32(u32) (_builtin_revl(u32))
+
+#else
+ #error "Compiler attribute porting is required"
+#endif
+
+#if (TU_BYTE_ORDER == TU_LITTLE_ENDIAN)
+
+ #define tu_htons(u16) (TU_BSWAP16(u16))
+ #define tu_ntohs(u16) (TU_BSWAP16(u16))
+
+ #define tu_htonl(u32) (TU_BSWAP32(u32))
+ #define tu_ntohl(u32) (TU_BSWAP32(u32))
+
+ #define tu_htole16(u16) (u16)
+ #define tu_le16toh(u16) (u16)
+
+ #define tu_htole32(u32) (u32)
+ #define tu_le32toh(u32) (u32)
+
+#elif (TU_BYTE_ORDER == TU_BIG_ENDIAN)
+
+ #define tu_htons(u16) (u16)
+ #define tu_ntohs(u16) (u16)
+
+ #define tu_htonl(u32) (u32)
+ #define tu_ntohl(u32) (u32)
+
+ #define tu_htole16(u16) (TU_BSWAP16(u16))
+ #define tu_le16toh(u16) (TU_BSWAP16(u16))
+
+ #define tu_htole32(u32) (TU_BSWAP32(u32))
+ #define tu_le32toh(u32) (TU_BSWAP32(u32))
+
+#else
+ #error Byte order is undefined
+#endif
+
+#endif /* _TUSB_COMPILER_H_ */
+
+/// @}
diff --git a/arkanoid/pico/tinyusb/tusb_config.h b/arkanoid/pico/tinyusb/tusb_config.h
new file mode 100644
index 0000000..3211ef0
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_config.h
@@ -0,0 +1,40 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ * Copyright (c) 2020 Damien P. George
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#ifndef _PICO_STDIO_USB_TUSB_CONFIG_H
+#define _PICO_STDIO_USB_TUSB_CONFIG_H
+
+#include "../stdio_usb.h"
+
+#define CFG_TUSB_RHPORT0_MODE (OPT_MODE_DEVICE)
+
+#define CFG_TUD_CDC (1)
+#define CFG_TUD_CDC_RX_BUFSIZE (256)
+#define CFG_TUD_CDC_TX_BUFSIZE (256)
+
+// We use a vendor specific interface but with our own driver
+#define CFG_TUD_VENDOR (0)
+#endif
diff --git a/arkanoid/pico/tinyusb/tusb_error.h b/arkanoid/pico/tinyusb/tusb_error.h
new file mode 100644
index 0000000..d7ad8c3
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_error.h
@@ -0,0 +1,75 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup Group_Common
+ * \defgroup Group_Error Error Codes
+ * @{ */
+
+#ifndef _TUSB_ERRORS_H_
+#define _TUSB_ERRORS_H_
+
+#include "tusb_option.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#define ERROR_ENUM(x) x,
+#define ERROR_STRING(x) #x,
+
+#define ERROR_TABLE(ENTRY) \
+ ENTRY(TUSB_ERROR_NONE )\
+ ENTRY(TUSB_ERROR_INVALID_PARA )\
+ ENTRY(TUSB_ERROR_DEVICE_NOT_READY )\
+ ENTRY(TUSB_ERROR_INTERFACE_IS_BUSY )\
+ ENTRY(TUSB_ERROR_HCD_OPEN_PIPE_FAILED )\
+ ENTRY(TUSB_ERROR_OSAL_TIMEOUT )\
+ ENTRY(TUSB_ERROR_CDCH_DEVICE_NOT_MOUNTED )\
+ ENTRY(TUSB_ERROR_MSCH_DEVICE_NOT_MOUNTED )\
+ ENTRY(TUSB_ERROR_NOT_SUPPORTED )\
+ ENTRY(TUSB_ERROR_NOT_ENOUGH_MEMORY )\
+ ENTRY(TUSB_ERROR_FAILED )\
+
+/// \brief Error Code returned
+/// TODO obsolete and to be remove
+typedef enum
+{
+ ERROR_TABLE(ERROR_ENUM)
+ TUSB_ERROR_COUNT
+}tusb_error_t;
+
+#if CFG_TUSB_DEBUG
+/// Enum to String for debugging purposes. Only available if \ref CFG_TUSB_DEBUG > 0
+extern char const* const tusb_strerr[TUSB_ERROR_COUNT];
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_ERRORS_H_ */
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/tusb_fifo.c b/arkanoid/pico/tinyusb/tusb_fifo.c
new file mode 100644
index 0000000..174a6fd
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_fifo.c
@@ -0,0 +1,1000 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Reinhard Panhuber - rework to unmasked pointers
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "osal.h"
+#include "tusb_fifo.h"
+
+// Supress IAR warning
+// Warning[Pa082]: undefined behavior: the order of volatile accesses is undefined in this statement
+#if defined(__ICCARM__)
+#pragma diag_suppress = Pa082
+#endif
+
+// implement mutex lock and unlock
+#if CFG_FIFO_MUTEX
+
+static inline void _ff_lock(tu_fifo_mutex_t mutex)
+{
+ if (mutex) osal_mutex_lock(mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+}
+
+static inline void _ff_unlock(tu_fifo_mutex_t mutex)
+{
+ if (mutex) osal_mutex_unlock(mutex);
+}
+
+#else
+
+#define _ff_lock(_mutex)
+#define _ff_unlock(_mutex)
+
+#endif
+
+/** \enum tu_fifo_copy_mode_t
+ * \brief Write modes intended to allow special read and write functions to be able to
+ * copy data to and from USB hardware FIFOs as needed for e.g. STM32s and others
+ */
+typedef enum
+{
+ TU_FIFO_COPY_INC, ///< Copy from/to an increasing source/destination address - default mode
+ TU_FIFO_COPY_CST_FULL_WORDS, ///< Copy from/to a constant source/destination address - required for e.g. STM32 to write into USB hardware FIFO
+} tu_fifo_copy_mode_t;
+
+bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable)
+{
+ if (depth > 0x8000) return false; // Maximum depth is 2^15 items
+
+ _ff_lock(f->mutex_wr);
+ _ff_lock(f->mutex_rd);
+
+ f->buffer = (uint8_t*) buffer;
+ f->depth = depth;
+ f->item_size = item_size;
+ f->overwritable = overwritable;
+
+ // Limit index space to 2*depth - this allows for a fast "modulo" calculation
+ // but limits the maximum depth to 2^16/2 = 2^15 and buffer overflows are detectable
+ // only if overflow happens once (important for unsupervised DMA applications)
+ f->max_pointer_idx = 2*depth - 1;
+ f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
+
+ f->rd_idx = f->wr_idx = 0;
+
+ _ff_unlock(f->mutex_wr);
+ _ff_unlock(f->mutex_rd);
+
+ return true;
+}
+
+// Static functions are intended to work on local variables
+static inline uint16_t _ff_mod(uint16_t idx, uint16_t depth)
+{
+ while ( idx >= depth) idx -= depth;
+ return idx;
+}
+
+// Intended to be used to read from hardware USB FIFO in e.g. STM32 where all data is read from a constant address
+// Code adapted from dcd_synopsis.c
+// TODO generalize with configurable 1 byte or 4 byte each read
+static void _ff_push_const_addr(uint8_t * ff_buf, const void * app_buf, uint16_t len)
+{
+ volatile uint32_t * rx_fifo = (volatile uint32_t *) app_buf;
+
+ // Reading full available 32 bit words from const app address
+ uint16_t full_words = len >> 2;
+ while(full_words--)
+ {
+ tu_unaligned_write32(ff_buf, *rx_fifo);
+ ff_buf += 4;
+ }
+
+ // Read the remaining 1-3 bytes from const app address
+ uint8_t const bytes_rem = len & 0x03;
+ if ( bytes_rem )
+ {
+ uint32_t tmp32 = *rx_fifo;
+ memcpy(ff_buf, &tmp32, bytes_rem);
+ }
+}
+
+// Intended to be used to write to hardware USB FIFO in e.g. STM32
+// where all data is written to a constant address in full word copies
+static void _ff_pull_const_addr(void * app_buf, const uint8_t * ff_buf, uint16_t len)
+{
+ volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf;
+
+ // Pushing full available 32 bit words to const app address
+ uint16_t full_words = len >> 2;
+ while(full_words--)
+ {
+ *tx_fifo = tu_unaligned_read32(ff_buf);
+ ff_buf += 4;
+ }
+
+ // Write the remaining 1-3 bytes into const app address
+ uint8_t const bytes_rem = len & 0x03;
+ if ( bytes_rem )
+ {
+ uint32_t tmp32 = 0;
+ memcpy(&tmp32, ff_buf, bytes_rem);
+
+ *tx_fifo = tmp32;
+ }
+}
+
+// send one item to FIFO WITHOUT updating write pointer
+static inline void _ff_push(tu_fifo_t* f, void const * app_buf, uint16_t rel)
+{
+ memcpy(f->buffer + (rel * f->item_size), app_buf, f->item_size);
+}
+
+// send n items to FIFO WITHOUT updating write pointer
+static void _ff_push_n(tu_fifo_t* f, void const * app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
+{
+ uint16_t const nLin = f->depth - rel;
+ uint16_t const nWrap = n - nLin;
+
+ uint16_t nLin_bytes = nLin * f->item_size;
+ uint16_t nWrap_bytes = nWrap * f->item_size;
+
+ // current buffer of fifo
+ uint8_t* ff_buf = f->buffer + (rel * f->item_size);
+
+ switch (copy_mode)
+ {
+ case TU_FIFO_COPY_INC:
+ if(n <= nLin)
+ {
+ // Linear only
+ memcpy(ff_buf, app_buf, n*f->item_size);
+ }
+ else
+ {
+ // Wrap around
+
+ // Write data to linear part of buffer
+ memcpy(ff_buf, app_buf, nLin_bytes);
+
+ // Write data wrapped around
+ memcpy(f->buffer, ((uint8_t const*) app_buf) + nLin_bytes, nWrap_bytes);
+ }
+ break;
+
+ case TU_FIFO_COPY_CST_FULL_WORDS:
+ // Intended for hardware buffers from which it can be read word by word only
+ if(n <= nLin)
+ {
+ // Linear only
+ _ff_push_const_addr(ff_buf, app_buf, n*f->item_size);
+ }
+ else
+ {
+ // Wrap around case
+
+ // Write full words to linear part of buffer
+ uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC;
+ _ff_push_const_addr(ff_buf, app_buf, nLin_4n_bytes);
+ ff_buf += nLin_4n_bytes;
+
+ // There could be odd 1-3 bytes before the wrap-around boundary
+ volatile uint32_t * rx_fifo = (volatile uint32_t *) app_buf;
+ uint8_t rem = nLin_bytes & 0x03;
+ if (rem > 0)
+ {
+ uint8_t remrem = tu_min16(nWrap_bytes, 4-rem);
+ nWrap_bytes -= remrem;
+
+ uint32_t tmp32 = *rx_fifo;
+ uint8_t * src_u8 = ((uint8_t *) &tmp32);
+
+ // Write 1-3 bytes before wrapped boundary
+ while(rem--) *ff_buf++ = *src_u8++;
+
+ // Read more bytes to beginning to complete a word
+ ff_buf = f->buffer;
+ while(remrem--) *ff_buf++ = *src_u8++;
+ }
+ else
+ {
+ ff_buf = f->buffer; // wrap around to beginning
+ }
+
+ // Write data wrapped part
+ if (nWrap_bytes > 0) _ff_push_const_addr(ff_buf, app_buf, nWrap_bytes);
+ }
+ break;
+ }
+}
+
+// get one item from FIFO WITHOUT updating read pointer
+static inline void _ff_pull(tu_fifo_t* f, void * app_buf, uint16_t rel)
+{
+ memcpy(app_buf, f->buffer + (rel * f->item_size), f->item_size);
+}
+
+// get n items from FIFO WITHOUT updating read pointer
+static void _ff_pull_n(tu_fifo_t* f, void* app_buf, uint16_t n, uint16_t rel, tu_fifo_copy_mode_t copy_mode)
+{
+ uint16_t const nLin = f->depth - rel;
+ uint16_t const nWrap = n - nLin; // only used if wrapped
+
+ uint16_t nLin_bytes = nLin * f->item_size;
+ uint16_t nWrap_bytes = nWrap * f->item_size;
+
+ // current buffer of fifo
+ uint8_t* ff_buf = f->buffer + (rel * f->item_size);
+
+ switch (copy_mode)
+ {
+ case TU_FIFO_COPY_INC:
+ if ( n <= nLin )
+ {
+ // Linear only
+ memcpy(app_buf, ff_buf, n*f->item_size);
+ }
+ else
+ {
+ // Wrap around
+
+ // Read data from linear part of buffer
+ memcpy(app_buf, ff_buf, nLin_bytes);
+
+ // Read data wrapped part
+ memcpy((uint8_t*) app_buf + nLin_bytes, f->buffer, nWrap_bytes);
+ }
+ break;
+
+ case TU_FIFO_COPY_CST_FULL_WORDS:
+ if ( n <= nLin )
+ {
+ // Linear only
+ _ff_pull_const_addr(app_buf, ff_buf, n*f->item_size);
+ }
+ else
+ {
+ // Wrap around case
+
+ // Read full words from linear part of buffer
+ uint16_t nLin_4n_bytes = nLin_bytes & 0xFFFC;
+ _ff_pull_const_addr(app_buf, ff_buf, nLin_4n_bytes);
+ ff_buf += nLin_4n_bytes;
+
+ // There could be odd 1-3 bytes before the wrap-around boundary
+ volatile uint32_t * tx_fifo = (volatile uint32_t *) app_buf;
+ uint8_t rem = nLin_bytes & 0x03;
+ if (rem > 0)
+ {
+ uint8_t remrem = tu_min16(nWrap_bytes, 4-rem);
+ nWrap_bytes -= remrem;
+
+ uint32_t tmp32=0;
+ uint8_t * dst_u8 = (uint8_t *)&tmp32;
+
+ // Read 1-3 bytes before wrapped boundary
+ while(rem--) *dst_u8++ = *ff_buf++;
+
+ // Read more bytes from beginning to complete a word
+ ff_buf = f->buffer;
+ while(remrem--) *dst_u8++ = *ff_buf++;
+
+ *tx_fifo = tmp32;
+ }
+ else
+ {
+ ff_buf = f->buffer; // wrap around to beginning
+ }
+
+ // Read data wrapped part
+ if (nWrap_bytes > 0) _ff_pull_const_addr(app_buf, ff_buf, nWrap_bytes);
+ }
+ break;
+
+ default: break;
+ }
+}
+
+// Advance an absolute pointer
+static uint16_t advance_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
+{
+ // We limit the index space of p such that a correct wrap around happens
+ // Check for a wrap around or if we are in unused index space - This has to be checked first!!
+ // We are exploiting the wrap around to the correct index
+ if ((p > (uint16_t)(p + offset)) || ((uint16_t)(p + offset) > f->max_pointer_idx))
+ {
+ p = (p + offset) + f->non_used_index_space;
+ }
+ else
+ {
+ p += offset;
+ }
+ return p;
+}
+
+// Backward an absolute pointer
+static uint16_t backward_pointer(tu_fifo_t* f, uint16_t p, uint16_t offset)
+{
+ // We limit the index space of p such that a correct wrap around happens
+ // Check for a wrap around or if we are in unused index space - This has to be checked first!!
+ // We are exploiting the wrap around to the correct index
+ if ((p < (uint16_t)(p - offset)) || ((uint16_t)(p - offset) > f->max_pointer_idx))
+ {
+ p = (p - offset) - f->non_used_index_space;
+ }
+ else
+ {
+ p -= offset;
+ }
+ return p;
+}
+
+// get relative from absolute pointer
+static uint16_t get_relative_pointer(tu_fifo_t* f, uint16_t p)
+{
+ return _ff_mod(p, f->depth);
+}
+
+// Works on local copies of w and r - return only the difference and as such can be used to determine an overflow
+static inline uint16_t _tu_fifo_count(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+{
+ uint16_t cnt = wAbs-rAbs;
+
+ // In case we have non-power of two depth we need a further modification
+ if (rAbs > wAbs) cnt -= f->non_used_index_space;
+
+ return cnt;
+}
+
+// Works on local copies of w and r
+static inline bool _tu_fifo_empty(uint16_t wAbs, uint16_t rAbs)
+{
+ return wAbs == rAbs;
+}
+
+// Works on local copies of w and r
+static inline bool _tu_fifo_full(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+{
+ return (_tu_fifo_count(f, wAbs, rAbs) == f->depth);
+}
+
+// Works on local copies of w and r
+// BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS"
+// Only one overflow is allowed for this function to work e.g. if depth = 100, you must not
+// write more than 2*depth-1 items in one rush without updating write pointer. Otherwise
+// write pointer wraps and you pointer states are messed up. This can only happen if you
+// use DMAs, write functions do not allow such an error.
+static inline bool _tu_fifo_overflowed(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+{
+ return (_tu_fifo_count(f, wAbs, rAbs) > f->depth);
+}
+
+// Works on local copies of w
+// For more details see _tu_fifo_overflow()!
+static inline void _tu_fifo_correct_read_pointer(tu_fifo_t* f, uint16_t wAbs)
+{
+ f->rd_idx = backward_pointer(f, wAbs, f->depth);
+}
+
+// Works on local copies of w and r
+// Must be protected by mutexes since in case of an overflow read pointer gets modified
+static bool _tu_fifo_peek(tu_fifo_t* f, void * p_buffer, uint16_t wAbs, uint16_t rAbs)
+{
+ uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs);
+
+ // Check overflow and correct if required
+ if (cnt > f->depth)
+ {
+ _tu_fifo_correct_read_pointer(f, wAbs);
+ cnt = f->depth;
+ }
+
+ // Skip beginning of buffer
+ if (cnt == 0) return false;
+
+ uint16_t rRel = get_relative_pointer(f, rAbs);
+
+ // Peek data
+ _ff_pull(f, p_buffer, rRel);
+
+ return true;
+}
+
+// Works on local copies of w and r
+// Must be protected by mutexes since in case of an overflow read pointer gets modified
+static uint16_t _tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n, uint16_t wAbs, uint16_t rAbs, tu_fifo_copy_mode_t copy_mode)
+{
+ uint16_t cnt = _tu_fifo_count(f, wAbs, rAbs);
+
+ // Check overflow and correct if required
+ if (cnt > f->depth)
+ {
+ _tu_fifo_correct_read_pointer(f, wAbs);
+ rAbs = f->rd_idx;
+ cnt = f->depth;
+ }
+
+ // Skip beginning of buffer
+ if (cnt == 0) return 0;
+
+ // Check if we can read something at and after offset - if too less is available we read what remains
+ if (cnt < n) n = cnt;
+
+ uint16_t rRel = get_relative_pointer(f, rAbs);
+
+ // Peek data
+ _ff_pull_n(f, p_buffer, n, rRel, copy_mode);
+
+ return n;
+}
+
+// Works on local copies of w and r
+static inline uint16_t _tu_fifo_remaining(tu_fifo_t* f, uint16_t wAbs, uint16_t rAbs)
+{
+ return f->depth - _tu_fifo_count(f, wAbs, rAbs);
+}
+
+static uint16_t _tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n, tu_fifo_copy_mode_t copy_mode)
+{
+ if ( n == 0 ) return 0;
+
+ _ff_lock(f->mutex_wr);
+
+ uint16_t w = f->wr_idx, r = f->rd_idx;
+ uint8_t const* buf8 = (uint8_t const*) data;
+
+ if (!f->overwritable)
+ {
+ // Not overwritable limit up to full
+ n = tu_min16(n, _tu_fifo_remaining(f, w, r));
+ }
+ else if (n >= f->depth)
+ {
+ // Only copy last part
+ buf8 = buf8 + (n - f->depth) * f->item_size;
+ n = f->depth;
+
+ // We start writing at the read pointer's position since we fill the complete
+ // buffer and we do not want to modify the read pointer within a write function!
+ // This would end up in a race condition with read functions!
+ w = r;
+ }
+
+ uint16_t wRel = get_relative_pointer(f, w);
+
+ // Write data
+ _ff_push_n(f, buf8, n, wRel, copy_mode);
+
+ // Advance pointer
+ f->wr_idx = advance_pointer(f, w, n);
+
+ _ff_unlock(f->mutex_wr);
+
+ return n;
+}
+
+static uint16_t _tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n, tu_fifo_copy_mode_t copy_mode)
+{
+ _ff_lock(f->mutex_rd);
+
+ // Peek the data
+ // f->rd_idx might get modified in case of an overflow so we can not use a local variable
+ n = _tu_fifo_peek_n(f, buffer, n, f->wr_idx, f->rd_idx, copy_mode);
+
+ // Advance read pointer
+ f->rd_idx = advance_pointer(f, f->rd_idx, n);
+
+ _ff_unlock(f->mutex_rd);
+ return n;
+}
+
+/******************************************************************************/
+/*!
+ @brief Get number of items in FIFO.
+
+ As this function only reads the read and write pointers once, this function is
+ reentrant and thus thread and ISR save without any mutexes. In case an
+ overflow occurred, this function return f.depth at maximum. Overflows are
+ checked and corrected for in the read functions!
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+
+ @returns Number of items in FIFO
+ */
+/******************************************************************************/
+uint16_t tu_fifo_count(tu_fifo_t* f)
+{
+ return tu_min16(_tu_fifo_count(f, f->wr_idx, f->rd_idx), f->depth);
+}
+
+/******************************************************************************/
+/*!
+ @brief Check if FIFO is empty.
+
+ As this function only reads the read and write pointers once, this function is
+ reentrant and thus thread and ISR save without any mutexes.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+
+ @returns Number of items in FIFO
+ */
+/******************************************************************************/
+bool tu_fifo_empty(tu_fifo_t* f)
+{
+ return _tu_fifo_empty(f->wr_idx, f->rd_idx);
+}
+
+/******************************************************************************/
+/*!
+ @brief Check if FIFO is full.
+
+ As this function only reads the read and write pointers once, this function is
+ reentrant and thus thread and ISR save without any mutexes.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+
+ @returns Number of items in FIFO
+ */
+/******************************************************************************/
+bool tu_fifo_full(tu_fifo_t* f)
+{
+ return _tu_fifo_full(f, f->wr_idx, f->rd_idx);
+}
+
+/******************************************************************************/
+/*!
+ @brief Get remaining space in FIFO.
+
+ As this function only reads the read and write pointers once, this function is
+ reentrant and thus thread and ISR save without any mutexes.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+
+ @returns Number of items in FIFO
+ */
+/******************************************************************************/
+uint16_t tu_fifo_remaining(tu_fifo_t* f)
+{
+ return _tu_fifo_remaining(f, f->wr_idx, f->rd_idx);
+}
+
+/******************************************************************************/
+/*!
+ @brief Check if overflow happened.
+
+ BE AWARE - THIS FUNCTION MIGHT NOT GIVE A CORRECT ANSWERE IN CASE WRITE POINTER "OVERFLOWS"
+ Only one overflow is allowed for this function to work e.g. if depth = 100, you must not
+ write more than 2*depth-1 items in one rush without updating write pointer. Otherwise
+ write pointer wraps and your pointer states are messed up. This can only happen if you
+ use DMAs, write functions do not allow such an error. Avoid such nasty things!
+
+ All reading functions (read, peek) check for overflows and correct read pointer on their own such
+ that latest items are read.
+ If required (e.g. for DMA use) you can also correct the read pointer by
+ tu_fifo_correct_read_pointer().
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+
+ @returns True if overflow happened
+ */
+/******************************************************************************/
+bool tu_fifo_overflowed(tu_fifo_t* f)
+{
+ return _tu_fifo_overflowed(f, f->wr_idx, f->rd_idx);
+}
+
+// Only use in case tu_fifo_overflow() returned true!
+void tu_fifo_correct_read_pointer(tu_fifo_t* f)
+{
+ _ff_lock(f->mutex_rd);
+ _tu_fifo_correct_read_pointer(f, f->wr_idx);
+ _ff_unlock(f->mutex_rd);
+}
+
+/******************************************************************************/
+/*!
+ @brief Read one element out of the buffer.
+
+ This function will return the element located at the array index of the
+ read pointer, and then increment the read pointer index.
+ This function checks for an overflow and corrects read pointer if required.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] buffer
+ Pointer to the place holder for data read from the buffer
+
+ @returns TRUE if the queue is not empty
+ */
+/******************************************************************************/
+bool tu_fifo_read(tu_fifo_t* f, void * buffer)
+{
+ _ff_lock(f->mutex_rd);
+
+ // Peek the data
+ // f->rd_idx might get modified in case of an overflow so we can not use a local variable
+ bool ret = _tu_fifo_peek(f, buffer, f->wr_idx, f->rd_idx);
+
+ // Advance pointer
+ f->rd_idx = advance_pointer(f, f->rd_idx, ret);
+
+ _ff_unlock(f->mutex_rd);
+ return ret;
+}
+
+/******************************************************************************/
+/*!
+ @brief This function will read n elements from the array index specified by
+ the read pointer and increment the read index.
+ This function checks for an overflow and corrects read pointer if required.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] buffer
+ The pointer to data location
+ @param[in] n
+ Number of element that buffer can afford
+
+ @returns number of items read from the FIFO
+ */
+/******************************************************************************/
+uint16_t tu_fifo_read_n(tu_fifo_t* f, void * buffer, uint16_t n)
+{
+ return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_INC);
+}
+
+uint16_t tu_fifo_read_n_const_addr_full_words(tu_fifo_t* f, void * buffer, uint16_t n)
+{
+ return _tu_fifo_read_n(f, buffer, n, TU_FIFO_COPY_CST_FULL_WORDS);
+}
+
+/******************************************************************************/
+/*!
+ @brief Read one item without removing it from the FIFO.
+ This function checks for an overflow and corrects read pointer if required.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] offset
+ Position to read from in the FIFO buffer with respect to read pointer
+ @param[in] p_buffer
+ Pointer to the place holder for data read from the buffer
+
+ @returns TRUE if the queue is not empty
+ */
+/******************************************************************************/
+bool tu_fifo_peek(tu_fifo_t* f, void * p_buffer)
+{
+ _ff_lock(f->mutex_rd);
+ bool ret = _tu_fifo_peek(f, p_buffer, f->wr_idx, f->rd_idx);
+ _ff_unlock(f->mutex_rd);
+ return ret;
+}
+
+/******************************************************************************/
+/*!
+ @brief Read n items without removing it from the FIFO
+ This function checks for an overflow and corrects read pointer if required.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] p_buffer
+ Pointer to the place holder for data read from the buffer
+ @param[in] n
+ Number of items to peek
+
+ @returns Number of bytes written to p_buffer
+ */
+/******************************************************************************/
+uint16_t tu_fifo_peek_n(tu_fifo_t* f, void * p_buffer, uint16_t n)
+{
+ _ff_lock(f->mutex_rd);
+ bool ret = _tu_fifo_peek_n(f, p_buffer, n, f->wr_idx, f->rd_idx, TU_FIFO_COPY_INC);
+ _ff_unlock(f->mutex_rd);
+ return ret;
+}
+
+/******************************************************************************/
+/*!
+ @brief Write one element into the buffer.
+
+ This function will write one element into the array index specified by
+ the write pointer and increment the write index.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] data
+ The byte to add to the FIFO
+
+ @returns TRUE if the data was written to the FIFO (overwrittable
+ FIFO will always return TRUE)
+ */
+/******************************************************************************/
+bool tu_fifo_write(tu_fifo_t* f, const void * data)
+{
+ _ff_lock(f->mutex_wr);
+
+ uint16_t w = f->wr_idx;
+
+ if ( _tu_fifo_full(f, w, f->rd_idx) && !f->overwritable ) return false;
+
+ uint16_t wRel = get_relative_pointer(f, w);
+
+ // Write data
+ _ff_push(f, data, wRel);
+
+ // Advance pointer
+ f->wr_idx = advance_pointer(f, w, 1);
+
+ _ff_unlock(f->mutex_wr);
+
+ return true;
+}
+
+/******************************************************************************/
+/*!
+ @brief This function will write n elements into the array index specified by
+ the write pointer and increment the write index.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] data
+ The pointer to data to add to the FIFO
+ @param[in] count
+ Number of element
+ @return Number of written elements
+ */
+/******************************************************************************/
+uint16_t tu_fifo_write_n(tu_fifo_t* f, const void * data, uint16_t n)
+{
+ return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_INC);
+}
+
+/******************************************************************************/
+/*!
+ @brief This function will write n elements into the array index specified by
+ the write pointer and increment the write index. The source address will
+ not be incremented which is useful for reading from registers.
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] data
+ The pointer to data to add to the FIFO
+ @param[in] count
+ Number of element
+ @return Number of written elements
+ */
+/******************************************************************************/
+uint16_t tu_fifo_write_n_const_addr_full_words(tu_fifo_t* f, const void * data, uint16_t n)
+{
+ return _tu_fifo_write_n(f, data, n, TU_FIFO_COPY_CST_FULL_WORDS);
+}
+
+/******************************************************************************/
+/*!
+ @brief Clear the fifo read and write pointers
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ */
+/******************************************************************************/
+bool tu_fifo_clear(tu_fifo_t *f)
+{
+ _ff_lock(f->mutex_wr);
+ _ff_lock(f->mutex_rd);
+
+ f->rd_idx = f->wr_idx = 0;
+ f->max_pointer_idx = 2*f->depth-1;
+ f->non_used_index_space = UINT16_MAX - f->max_pointer_idx;
+
+ _ff_unlock(f->mutex_wr);
+ _ff_unlock(f->mutex_rd);
+ return true;
+}
+
+/******************************************************************************/
+/*!
+ @brief Change the fifo mode to overwritable or not overwritable
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] overwritable
+ Overwritable mode the fifo is set to
+ */
+/******************************************************************************/
+bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable)
+{
+ _ff_lock(f->mutex_wr);
+ _ff_lock(f->mutex_rd);
+
+ f->overwritable = overwritable;
+
+ _ff_unlock(f->mutex_wr);
+ _ff_unlock(f->mutex_rd);
+
+ return true;
+}
+
+/******************************************************************************/
+/*!
+ @brief Advance write pointer - intended to be used in combination with DMA.
+ It is possible to fill the FIFO by use of a DMA in circular mode. Within
+ DMA ISRs you may update the write pointer to be able to read from the FIFO.
+ As long as the DMA is the only process writing into the FIFO this is safe
+ to use.
+
+ USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE!
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] n
+ Number of items the write pointer moves forward
+ */
+/******************************************************************************/
+void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n)
+{
+ f->wr_idx = advance_pointer(f, f->wr_idx, n);
+}
+
+/******************************************************************************/
+/*!
+ @brief Advance read pointer - intended to be used in combination with DMA.
+ It is possible to read from the FIFO by use of a DMA in linear mode. Within
+ DMA ISRs you may update the read pointer to be able to again write into the
+ FIFO. As long as the DMA is the only process reading from the FIFO this is
+ safe to use.
+
+ USE WITH CARE - WE DO NOT CONDUCT SAFTY CHECKS HERE!
+
+ @param[in] f
+ Pointer to the FIFO buffer to manipulate
+ @param[in] n
+ Number of items the read pointer moves forward
+ */
+/******************************************************************************/
+void tu_fifo_advance_read_pointer(tu_fifo_t *f, uint16_t n)
+{
+ f->rd_idx = advance_pointer(f, f->rd_idx, n);
+}
+
+/******************************************************************************/
+/*!
+ @brief Get read info
+
+ Returns the length and pointer from which bytes can be read in a linear manner.
+ This is of major interest for DMA transmissions. If returned length is zero the
+ corresponding pointer is invalid.
+ The read pointer does NOT get advanced, use tu_fifo_advance_read_pointer() to
+ do so!
+ @param[in] f
+ Pointer to FIFO
+ @param[out] *info
+ Pointer to struct which holds the desired infos
+ */
+/******************************************************************************/
+void tu_fifo_get_read_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
+{
+ // Operate on temporary values in case they change in between
+ uint16_t w = f->wr_idx, r = f->rd_idx;
+
+ uint16_t cnt = _tu_fifo_count(f, w, r);
+
+ // Check overflow and correct if required - may happen in case a DMA wrote too fast
+ if (cnt > f->depth)
+ {
+ _ff_lock(f->mutex_rd);
+ _tu_fifo_correct_read_pointer(f, w);
+ _ff_unlock(f->mutex_rd);
+ r = f->rd_idx;
+ cnt = f->depth;
+ }
+
+ // Check if fifo is empty
+ if (cnt == 0)
+ {
+ info->len_lin = 0;
+ info->len_wrap = 0;
+ info->ptr_lin = NULL;
+ info->ptr_wrap = NULL;
+ return;
+ }
+
+ // Get relative pointers
+ w = get_relative_pointer(f, w);
+ r = get_relative_pointer(f, r);
+
+ // Copy pointer to buffer to start reading from
+ info->ptr_lin = &f->buffer[r];
+
+ // Check if there is a wrap around necessary
+ if (w > r) {
+ // Non wrapping case
+ info->len_lin = cnt;
+ info->len_wrap = 0;
+ info->ptr_wrap = NULL;
+ }
+ else
+ {
+ info->len_lin = f->depth - r; // Also the case if FIFO was full
+ info->len_wrap = cnt - info->len_lin;
+ info->ptr_wrap = f->buffer;
+ }
+}
+
+/******************************************************************************/
+/*!
+ @brief Get linear write info
+
+ Returns the length and pointer to which bytes can be written into FIFO in a linear manner.
+ This is of major interest for DMA transmissions not using circular mode. If a returned length is zero the
+ corresponding pointer is invalid. The returned lengths summed up are the currently free space in the FIFO.
+ The write pointer does NOT get advanced, use tu_fifo_advance_write_pointer() to do so!
+ TAKE CARE TO NOT OVERFLOW THE BUFFER MORE THAN TWO TIMES THE FIFO DEPTH - IT CAN NOT RECOVERE OTHERWISE!
+ @param[in] f
+ Pointer to FIFO
+ @param[out] *info
+ Pointer to struct which holds the desired infos
+ */
+/******************************************************************************/
+void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info)
+{
+ uint16_t w = f->wr_idx, r = f->rd_idx;
+ uint16_t free = _tu_fifo_remaining(f, w, r);
+
+ if (free == 0)
+ {
+ info->len_lin = 0;
+ info->len_wrap = 0;
+ info->ptr_lin = NULL;
+ info->ptr_wrap = NULL;
+ return;
+ }
+
+ // Get relative pointers
+ w = get_relative_pointer(f, w);
+ r = get_relative_pointer(f, r);
+
+ // Copy pointer to buffer to start writing to
+ info->ptr_lin = &f->buffer[w];
+
+ if (w < r)
+ {
+ // Non wrapping case
+ info->len_lin = r-w;
+ info->len_wrap = 0;
+ info->ptr_wrap = NULL;
+ }
+ else
+ {
+ info->len_lin = f->depth - w;
+ info->len_wrap = free - info->len_lin; // Remaining length - n already was limited to free or FIFO depth
+ info->ptr_wrap = f->buffer; // Always start of buffer
+ }
+}
diff --git a/arkanoid/pico/tinyusb/tusb_fifo.h b/arkanoid/pico/tinyusb/tusb_fifo.h
new file mode 100644
index 0000000..6f061ae
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_fifo.h
@@ -0,0 +1,151 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ * Copyright (c) 2020 Reinhard Panhuber - rework to unmasked pointers
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_FIFO_H_
+#define _TUSB_FIFO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Due to the use of unmasked pointers, this FIFO does not suffer from loosing
+// one item slice. Furthermore, write and read operations are completely
+// decoupled as write and read functions do not modify a common state. Henceforth,
+// writing or reading from the FIFO within an ISR is safe as long as no other
+// process (thread or ISR) interferes.
+// Also, this FIFO is ready to be used in combination with a DMA as the write and
+// read pointers can be updated from within a DMA ISR. Overflows are detectable
+// within a certain number (see tu_fifo_overflow()).
+
+#include "tusb_common.h"
+
+// mutex is only needed for RTOS
+// for OS None, we don't get preempted
+#define CFG_FIFO_MUTEX (CFG_TUSB_OS != OPT_OS_NONE)
+
+#if CFG_FIFO_MUTEX
+#include "osal.h"
+#define tu_fifo_mutex_t osal_mutex_t
+#endif
+
+typedef struct
+{
+ uint8_t* buffer ; ///< buffer pointer
+ uint16_t depth ; ///< max items
+ uint16_t item_size ; ///< size of each item
+ bool overwritable ;
+
+ uint16_t non_used_index_space ; ///< required for non-power-of-two buffer length
+ uint16_t max_pointer_idx ; ///< maximum absolute pointer index
+
+ volatile uint16_t wr_idx ; ///< write pointer
+ volatile uint16_t rd_idx ; ///< read pointer
+
+#if CFG_FIFO_MUTEX
+ tu_fifo_mutex_t mutex_wr;
+ tu_fifo_mutex_t mutex_rd;
+#endif
+
+} tu_fifo_t;
+
+typedef struct
+{
+ uint16_t len_lin ; ///< linear length in item size
+ uint16_t len_wrap ; ///< wrapped length in item size
+ void * ptr_lin ; ///< linear part start pointer
+ void * ptr_wrap ; ///< wrapped part start pointer
+} tu_fifo_buffer_info_t;
+
+#define TU_FIFO_INIT(_buffer, _depth, _type, _overwritable) \
+{ \
+ .buffer = _buffer, \
+ .depth = _depth, \
+ .item_size = sizeof(_type), \
+ .overwritable = _overwritable, \
+ .non_used_index_space = UINT16_MAX - (2*(_depth)-1), \
+ .max_pointer_idx = 2*(_depth)-1, \
+}
+
+#define TU_FIFO_DEF(_name, _depth, _type, _overwritable) \
+ uint8_t _name##_buf[_depth*sizeof(_type)]; \
+ tu_fifo_t _name = TU_FIFO_INIT(_name##_buf, _depth, _type, _overwritable)
+
+
+bool tu_fifo_set_overwritable(tu_fifo_t *f, bool overwritable);
+bool tu_fifo_clear(tu_fifo_t *f);
+bool tu_fifo_config(tu_fifo_t *f, void* buffer, uint16_t depth, uint16_t item_size, bool overwritable);
+
+#if CFG_FIFO_MUTEX
+TU_ATTR_ALWAYS_INLINE static inline
+void tu_fifo_config_mutex(tu_fifo_t *f, tu_fifo_mutex_t write_mutex_hdl, tu_fifo_mutex_t read_mutex_hdl)
+{
+ f->mutex_wr = write_mutex_hdl;
+ f->mutex_rd = read_mutex_hdl;
+}
+#endif
+
+bool tu_fifo_write (tu_fifo_t* f, void const * p_data);
+uint16_t tu_fifo_write_n (tu_fifo_t* f, void const * p_data, uint16_t n);
+uint16_t tu_fifo_write_n_const_addr_full_words (tu_fifo_t* f, const void * data, uint16_t n);
+
+bool tu_fifo_read (tu_fifo_t* f, void * p_buffer);
+uint16_t tu_fifo_read_n (tu_fifo_t* f, void * p_buffer, uint16_t n);
+uint16_t tu_fifo_read_n_const_addr_full_words (tu_fifo_t* f, void * buffer, uint16_t n);
+
+bool tu_fifo_peek (tu_fifo_t* f, void * p_buffer);
+uint16_t tu_fifo_peek_n (tu_fifo_t* f, void * p_buffer, uint16_t n);
+
+uint16_t tu_fifo_count (tu_fifo_t* f);
+uint16_t tu_fifo_remaining (tu_fifo_t* f);
+bool tu_fifo_empty (tu_fifo_t* f);
+bool tu_fifo_full (tu_fifo_t* f);
+bool tu_fifo_overflowed (tu_fifo_t* f);
+void tu_fifo_correct_read_pointer (tu_fifo_t* f);
+
+TU_ATTR_ALWAYS_INLINE static inline
+uint16_t tu_fifo_depth(tu_fifo_t* f)
+{
+ return f->depth;
+}
+
+// Pointer modifications intended to be used in combinations with DMAs.
+// USE WITH CARE - NO SAFTY CHECKS CONDUCTED HERE! NOT MUTEX PROTECTED!
+void tu_fifo_advance_write_pointer(tu_fifo_t *f, uint16_t n);
+void tu_fifo_advance_read_pointer (tu_fifo_t *f, uint16_t n);
+
+// If you want to read/write from/to the FIFO by use of a DMA, you may need to conduct two copies
+// to handle a possible wrapping part. These functions deliver a pointer to start
+// reading/writing from/to and a valid linear length along which no wrap occurs.
+void tu_fifo_get_read_info (tu_fifo_t *f, tu_fifo_buffer_info_t *info);
+void tu_fifo_get_write_info(tu_fifo_t *f, tu_fifo_buffer_info_t *info);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_FIFO_H_ */
diff --git a/arkanoid/pico/tinyusb/tusb_option.h b/arkanoid/pico/tinyusb/tusb_option.h
new file mode 100644
index 0000000..e49fc01
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_option.h
@@ -0,0 +1,358 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_OPTION_H_
+#define _TUSB_OPTION_H_
+
+#define TUSB_VERSION_MAJOR 0
+#define TUSB_VERSION_MINOR 12
+#define TUSB_VERSION_REVISION 0
+#define TUSB_VERSION_STRING TU_STRING(TUSB_VERSION_MAJOR) "." TU_STRING(TUSB_VERSION_MINOR) "." TU_STRING(TUSB_VERSION_REVISION)
+
+//--------------------------------------------------------------------+
+// Supported MCUs
+// CFG_TUSB_MCU must be defined to one of following value
+//--------------------------------------------------------------------+
+#define TU_CHECK_MCU(_m) (CFG_TUSB_MCU == OPT_MCU_##_m)
+
+#define OPT_MCU_NONE 0
+
+// LPC
+#define OPT_MCU_LPC11UXX 1 ///< NXP LPC11Uxx
+#define OPT_MCU_LPC13XX 2 ///< NXP LPC13xx
+#define OPT_MCU_LPC15XX 3 ///< NXP LPC15xx
+#define OPT_MCU_LPC175X_6X 4 ///< NXP LPC175x, LPC176x
+#define OPT_MCU_LPC177X_8X 5 ///< NXP LPC177x, LPC178x
+#define OPT_MCU_LPC18XX 6 ///< NXP LPC18xx
+#define OPT_MCU_LPC40XX 7 ///< NXP LPC40xx
+#define OPT_MCU_LPC43XX 8 ///< NXP LPC43xx
+#define OPT_MCU_LPC51UXX 9 ///< NXP LPC51U6x
+#define OPT_MCU_LPC54XXX 10 ///< NXP LPC54xxx
+#define OPT_MCU_LPC55XX 11 ///< NXP LPC55xx
+
+// NRF
+#define OPT_MCU_NRF5X 100 ///< Nordic nRF5x series
+
+// SAM
+#define OPT_MCU_SAMD21 200 ///< MicroChip SAMD21
+#define OPT_MCU_SAMD51 201 ///< MicroChip SAMD51
+#define OPT_MCU_SAMG 202 ///< MicroChip SAMDG series
+#define OPT_MCU_SAME5X 203 ///< MicroChip SAM E5x
+#define OPT_MCU_SAMD11 204 ///< MicroChip SAMD11
+#define OPT_MCU_SAML22 205 ///< MicroChip SAML22
+#define OPT_MCU_SAML21 206 ///< MicroChip SAML21
+#define OPT_MCU_SAMX7X 207 ///< MicroChip SAME70, S70, V70, V71 family
+
+// STM32
+#define OPT_MCU_STM32F0 300 ///< ST STM32F0
+#define OPT_MCU_STM32F1 301 ///< ST STM32F1
+#define OPT_MCU_STM32F2 302 ///< ST STM32F2
+#define OPT_MCU_STM32F3 303 ///< ST STM32F3
+#define OPT_MCU_STM32F4 304 ///< ST STM32F4
+#define OPT_MCU_STM32F7 305 ///< ST STM32F7
+#define OPT_MCU_STM32H7 306 ///< ST STM32H7
+#define OPT_MCU_STM32L0 307 ///< ST STM32L0
+#define OPT_MCU_STM32L1 308 ///< ST STM32L1
+#define OPT_MCU_STM32L4 309 ///< ST STM32L4
+
+// Sony
+#define OPT_MCU_CXD56 400 ///< SONY CXD56
+
+// TI MSP430
+#define OPT_MCU_MSP430x5xx 500 ///< TI MSP430x5xx
+
+// ValentyUSB eptri
+#define OPT_MCU_VALENTYUSB_EPTRI 600 ///< Fomu eptri config
+
+// NXP iMX RT
+#define OPT_MCU_MIMXRT10XX 700 ///< NXP iMX RT10xx
+
+// Nuvoton
+#define OPT_MCU_NUC121 800
+#define OPT_MCU_NUC126 801
+#define OPT_MCU_NUC120 802
+#define OPT_MCU_NUC505 803
+
+// Espressif
+#define OPT_MCU_ESP32S2 900 ///< Espressif ESP32-S2
+#define OPT_MCU_ESP32S3 901 ///< Espressif ESP32-S3
+
+// Dialog
+#define OPT_MCU_DA1469X 1000 ///< Dialog Semiconductor DA1469x
+
+// Raspberry Pi
+#define OPT_MCU_RP2040 1100 ///< Raspberry Pi RP2040
+
+// NXP Kinetis
+#define OPT_MCU_MKL25ZXX 1200 ///< NXP MKL25Zxx
+#define OPT_MCU_K32L2BXX 1201 ///< NXP K32L2Bxx
+
+// Silabs
+#define OPT_MCU_EFM32GG 1300 ///< Silabs EFM32GG
+#define OPT_MCU_EFM32GG11 1301 ///< Silabs EFM32GG11
+#define OPT_MCU_EFM32GG12 1302 ///< Silabs EFM32GG12
+
+// Renesas RX
+#define OPT_MCU_RX63X 1400 ///< Renesas RX63N/631
+#define OPT_MCU_RX65X 1401 ///< Renesas RX65N/RX651
+#define OPT_MCU_RX72N 1402 ///< Renesas RX72N
+
+// Mind Motion
+#define OPT_MCU_MM32F327X 1500 ///< Mind Motion MM32F327
+
+// GigaDevice
+#define OPT_MCU_GD32VF103 1600 ///< GigaDevice GD32VF103
+
+//--------------------------------------------------------------------+
+// Supported OS
+//--------------------------------------------------------------------+
+
+#define OPT_OS_NONE 1 ///< No RTOS
+#define OPT_OS_FREERTOS 2 ///< FreeRTOS
+#define OPT_OS_MYNEWT 3 ///< Mynewt OS
+#define OPT_OS_CUSTOM 4 ///< Custom OS is implemented by application
+#define OPT_OS_PICO 5 ///< Raspberry Pi Pico SDK
+#define OPT_OS_RTTHREAD 6 ///< RT-Thread
+
+// Allow to use command line to change the config name/location
+#ifdef CFG_TUSB_CONFIG_FILE
+ #include CFG_TUSB_CONFIG_FILE
+#else
+ #include "tusb_config.h"
+#endif
+
+//--------------------------------------------------------------------
+// RootHub Mode Configuration
+// CFG_TUSB_RHPORTx_MODE contains operation mode and speed for that port
+//--------------------------------------------------------------------
+
+// Lower 4-bit is operational mode
+#define OPT_MODE_NONE 0x00 ///< Disabled
+#define OPT_MODE_DEVICE 0x01 ///< Device Mode
+#define OPT_MODE_HOST 0x02 ///< Host Mode
+
+// Higher 4-bit is max operational speed (corresponding to tusb_speed_t)
+#define OPT_MODE_FULL_SPEED 0x00 ///< Max Full Speed
+#define OPT_MODE_LOW_SPEED 0x10 ///< Max Low Speed
+#define OPT_MODE_HIGH_SPEED 0x20 ///< Max High Speed
+
+
+#ifndef CFG_TUSB_RHPORT0_MODE
+ #define CFG_TUSB_RHPORT0_MODE OPT_MODE_NONE
+#endif
+
+
+#ifndef CFG_TUSB_RHPORT1_MODE
+ #define CFG_TUSB_RHPORT1_MODE OPT_MODE_NONE
+#endif
+
+#if (((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST ) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST )) || \
+ (((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) && ((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE))
+ #error "TinyUSB currently does not support same modes on more than 1 roothub port"
+#endif
+
+// Which roothub port is configured as host
+#define TUH_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HOST) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HOST) ? 1 : -1) )
+#define TUSB_OPT_HOST_ENABLED ( TUH_OPT_RHPORT >= 0 )
+
+// Which roothub port is configured as device
+#define TUD_OPT_RHPORT ( ((CFG_TUSB_RHPORT0_MODE) & OPT_MODE_DEVICE) ? 0 : (((CFG_TUSB_RHPORT1_MODE) & OPT_MODE_DEVICE) ? 1 : -1) )
+
+#if TUD_OPT_RHPORT == 0
+#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT0_MODE) & OPT_MODE_HIGH_SPEED )
+#else
+#define TUD_OPT_HIGH_SPEED ( (CFG_TUSB_RHPORT1_MODE) & OPT_MODE_HIGH_SPEED )
+#endif
+
+#define TUSB_OPT_DEVICE_ENABLED ( TUD_OPT_RHPORT >= 0 )
+
+//--------------------------------------------------------------------+
+// COMMON OPTIONS
+//--------------------------------------------------------------------+
+
+// Debug enable to print out error message
+#ifndef CFG_TUSB_DEBUG
+ #define CFG_TUSB_DEBUG 0
+#endif
+
+// place data in accessible RAM for usb controller
+#ifndef CFG_TUSB_MEM_SECTION
+ #define CFG_TUSB_MEM_SECTION
+#endif
+
+// alignment requirement of buffer used for endpoint transferring
+#ifndef CFG_TUSB_MEM_ALIGN
+ #define CFG_TUSB_MEM_ALIGN TU_ATTR_ALIGNED(4)
+#endif
+
+// OS selection
+#ifndef CFG_TUSB_OS
+ #define CFG_TUSB_OS OPT_OS_NONE
+#endif
+
+#ifndef CFG_TUSB_OS_INC_PATH
+ #define CFG_TUSB_OS_INC_PATH
+#endif
+
+//--------------------------------------------------------------------
+// DEVICE OPTIONS
+//--------------------------------------------------------------------
+
+#ifndef CFG_TUD_ENDPOINT0_SIZE
+ #define CFG_TUD_ENDPOINT0_SIZE 64
+#endif
+
+#ifndef CFG_TUD_CDC
+ #define CFG_TUD_CDC 0
+#endif
+
+#ifndef CFG_TUD_MSC
+ #define CFG_TUD_MSC 0
+#endif
+
+#ifndef CFG_TUD_HID
+ #define CFG_TUD_HID 0
+#endif
+
+#ifndef CFG_TUD_AUDIO
+ #define CFG_TUD_AUDIO 0
+#endif
+
+#ifndef CFG_TUD_VIDEO
+ #define CFG_TUD_VIDEO 0
+#endif
+
+#ifndef CFG_TUD_MIDI
+ #define CFG_TUD_MIDI 0
+#endif
+
+#ifndef CFG_TUD_VENDOR
+ #define CFG_TUD_VENDOR 0
+#endif
+
+#ifndef CFG_TUD_USBTMC
+ #define CFG_TUD_USBTMC 0
+#endif
+
+#ifndef CFG_TUD_DFU_RUNTIME
+ #define CFG_TUD_DFU_RUNTIME 0
+#endif
+
+#ifndef CFG_TUD_DFU
+ #define CFG_TUD_DFU 0
+#endif
+
+#ifndef CFG_TUD_BTH
+ #define CFG_TUD_BTH 0
+#endif
+
+#ifndef CFG_TUD_ECM_RNDIS
+ #ifdef CFG_TUD_NET
+ #warning "CFG_TUD_NET is renamed to CFG_TUD_ECM_RNDIS"
+ #define CFG_TUD_ECM_RNDIS CFG_TUD_NET
+ #else
+ #define CFG_TUD_ECM_RNDIS 0
+ #endif
+#endif
+
+#ifndef CFG_TUD_NCM
+ #define CFG_TUD_NCM 0
+#endif
+
+//--------------------------------------------------------------------
+// HOST OPTIONS
+//--------------------------------------------------------------------
+#if TUSB_OPT_HOST_ENABLED
+ #ifndef CFG_TUH_DEVICE_MAX
+ #define CFG_TUH_DEVICE_MAX 1
+ #endif
+
+ #ifndef CFG_TUH_ENUMERATION_BUFSIZE
+ #define CFG_TUH_ENUMERATION_BUFSIZE 256
+ #endif
+#endif // TUSB_OPT_HOST_ENABLED
+
+//------------- CLASS -------------//
+
+#ifndef CFG_TUH_HUB
+#define CFG_TUH_HUB 0
+#endif
+
+#ifndef CFG_TUH_CDC
+#define CFG_TUH_CDC 0
+#endif
+
+#ifndef CFG_TUH_HID
+#define CFG_TUH_HID 0
+#endif
+
+#ifndef CFG_TUH_MIDI
+#define CFG_TUH_MIDI 0
+#endif
+
+#ifndef CFG_TUH_MSC
+#define CFG_TUH_MSC 0
+#endif
+
+#ifndef CFG_TUH_VENDOR
+#define CFG_TUH_VENDOR 0
+#endif
+
+//--------------------------------------------------------------------+
+// Port Specific
+// TUP stand for TinyUSB Port (can be renamed)
+//--------------------------------------------------------------------+
+
+//------------- Unaligned Memory -------------//
+
+// ARMv7+ (M3-M7, M23-M33) can access unaligned memory
+#if (defined(__ARM_ARCH) && (__ARM_ARCH >= 7))
+ #define TUP_ARCH_STRICT_ALIGN 0
+#else
+ #define TUP_ARCH_STRICT_ALIGN 1
+#endif
+
+// TUP_MCU_STRICT_ALIGN will overwrite TUP_ARCH_STRICT_ALIGN.
+// In case TUP_MCU_STRICT_ALIGN = 1 and TUP_ARCH_STRICT_ALIGN =0, we will not reply on compiler
+// to generate unaligned access code.
+// LPC_IP3511 Highspeed cannot access unaligned memory on USB_RAM
+#if TUD_OPT_HIGH_SPEED && (CFG_TUSB_MCU == OPT_MCU_LPC54XXX || CFG_TUSB_MCU == OPT_MCU_LPC55XX)
+ #define TUP_MCU_STRICT_ALIGN 1
+#else
+ #define TUP_MCU_STRICT_ALIGN 0
+#endif
+
+
+//------------------------------------------------------------------
+// Configuration Validation
+//------------------------------------------------------------------
+#if CFG_TUD_ENDPOINT0_SIZE > 64
+ #error Control Endpoint Max Packet Size cannot be larger than 64
+#endif
+
+#endif /* _TUSB_OPTION_H_ */
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/tusb_timeout.h b/arkanoid/pico/tinyusb/tusb_timeout.h
new file mode 100644
index 0000000..ce53955
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_timeout.h
@@ -0,0 +1,80 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup Group_Common Common Files
+ * \defgroup Group_TimeoutTimer timeout timer
+ * @{ */
+
+#ifndef _TUSB_TIMEOUT_H_
+#define _TUSB_TIMEOUT_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+ uint32_t start;
+ uint32_t interval;
+}tu_timeout_t;
+
+#if 0
+
+extern uint32_t tusb_hal_millis(void);
+
+static inline void tu_timeout_set(tu_timeout_t* tt, uint32_t msec)
+{
+ tt->interval = msec;
+ tt->start = tusb_hal_millis();
+}
+
+static inline bool tu_timeout_expired(tu_timeout_t* tt)
+{
+ return ( tusb_hal_millis() - tt->start ) >= tt->interval;
+}
+
+// For used with periodic event to prevent drift
+static inline void tu_timeout_reset(tu_timeout_t* tt)
+{
+ tt->start += tt->interval;
+}
+
+static inline void tu_timeout_restart(tu_timeout_t* tt)
+{
+ tt->start = tusb_hal_millis();
+}
+
+#endif
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_TIMEOUT_H_ */
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/tusb_types.h b/arkanoid/pico/tinyusb/tusb_types.h
new file mode 100644
index 0000000..897e89b
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_types.h
@@ -0,0 +1,549 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+/** \ingroup group_usb_definitions
+ * \defgroup USBDef_Type USB Types
+ * @{ */
+
+#ifndef _TUSB_TYPES_H_
+#define _TUSB_TYPES_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "tusb_compiler.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/*------------------------------------------------------------------*/
+/* CONSTANTS
+ *------------------------------------------------------------------*/
+
+/// defined base on EHCI specs value for Endpoint Speed
+typedef enum
+{
+ TUSB_SPEED_FULL = 0,
+ TUSB_SPEED_LOW ,
+ TUSB_SPEED_HIGH,
+ TUSB_SPEED_INVALID = 0xff,
+}tusb_speed_t;
+
+/// defined base on USB Specs Endpoint's bmAttributes
+typedef enum
+{
+ TUSB_XFER_CONTROL = 0 ,
+ TUSB_XFER_ISOCHRONOUS ,
+ TUSB_XFER_BULK ,
+ TUSB_XFER_INTERRUPT
+}tusb_xfer_type_t;
+
+typedef enum
+{
+ TUSB_DIR_OUT = 0,
+ TUSB_DIR_IN = 1,
+
+ TUSB_DIR_IN_MASK = 0x80
+}tusb_dir_t;
+
+/// Isochronous End Point Attributes
+typedef enum
+{
+ TUSB_ISO_EP_ATT_NO_SYNC = 0x00,
+ TUSB_ISO_EP_ATT_ASYNCHRONOUS = 0x04,
+ TUSB_ISO_EP_ATT_ADAPTIVE = 0x08,
+ TUSB_ISO_EP_ATT_SYNCHRONOUS = 0x0C,
+ TUSB_ISO_EP_ATT_DATA = 0x00, ///< Data End Point
+ TUSB_ISO_EP_ATT_EXPLICIT_FB = 0x10, ///< Feedback End Point
+ TUSB_ISO_EP_ATT_IMPLICIT_FB = 0x20, ///< Data endpoint that also serves as an implicit feedback
+}tusb_iso_ep_attribute_t;
+
+/// USB Descriptor Types
+typedef enum
+{
+ TUSB_DESC_DEVICE = 0x01,
+ TUSB_DESC_CONFIGURATION = 0x02,
+ TUSB_DESC_STRING = 0x03,
+ TUSB_DESC_INTERFACE = 0x04,
+ TUSB_DESC_ENDPOINT = 0x05,
+ TUSB_DESC_DEVICE_QUALIFIER = 0x06,
+ TUSB_DESC_OTHER_SPEED_CONFIG = 0x07,
+ TUSB_DESC_INTERFACE_POWER = 0x08,
+ TUSB_DESC_OTG = 0x09,
+ TUSB_DESC_DEBUG = 0x0A,
+ TUSB_DESC_INTERFACE_ASSOCIATION = 0x0B,
+
+ TUSB_DESC_BOS = 0x0F,
+ TUSB_DESC_DEVICE_CAPABILITY = 0x10,
+
+ TUSB_DESC_FUNCTIONAL = 0x21,
+
+ // Class Specific Descriptor
+ TUSB_DESC_CS_DEVICE = 0x21,
+ TUSB_DESC_CS_CONFIGURATION = 0x22,
+ TUSB_DESC_CS_STRING = 0x23,
+ TUSB_DESC_CS_INTERFACE = 0x24,
+ TUSB_DESC_CS_ENDPOINT = 0x25,
+
+ TUSB_DESC_SUPERSPEED_ENDPOINT_COMPANION = 0x30,
+ TUSB_DESC_SUPERSPEED_ISO_ENDPOINT_COMPANION = 0x31
+}tusb_desc_type_t;
+
+typedef enum
+{
+ TUSB_REQ_GET_STATUS = 0 ,
+ TUSB_REQ_CLEAR_FEATURE = 1 ,
+ TUSB_REQ_RESERVED = 2 ,
+ TUSB_REQ_SET_FEATURE = 3 ,
+ TUSB_REQ_RESERVED2 = 4 ,
+ TUSB_REQ_SET_ADDRESS = 5 ,
+ TUSB_REQ_GET_DESCRIPTOR = 6 ,
+ TUSB_REQ_SET_DESCRIPTOR = 7 ,
+ TUSB_REQ_GET_CONFIGURATION = 8 ,
+ TUSB_REQ_SET_CONFIGURATION = 9 ,
+ TUSB_REQ_GET_INTERFACE = 10 ,
+ TUSB_REQ_SET_INTERFACE = 11 ,
+ TUSB_REQ_SYNCH_FRAME = 12
+}tusb_request_code_t;
+
+typedef enum
+{
+ TUSB_REQ_FEATURE_EDPT_HALT = 0,
+ TUSB_REQ_FEATURE_REMOTE_WAKEUP = 1,
+ TUSB_REQ_FEATURE_TEST_MODE = 2
+}tusb_request_feature_selector_t;
+
+typedef enum
+{
+ TUSB_REQ_TYPE_STANDARD = 0,
+ TUSB_REQ_TYPE_CLASS,
+ TUSB_REQ_TYPE_VENDOR,
+ TUSB_REQ_TYPE_INVALID
+} tusb_request_type_t;
+
+typedef enum
+{
+ TUSB_REQ_RCPT_DEVICE =0,
+ TUSB_REQ_RCPT_INTERFACE,
+ TUSB_REQ_RCPT_ENDPOINT,
+ TUSB_REQ_RCPT_OTHER
+} tusb_request_recipient_t;
+
+// https://www.usb.org/defined-class-codes
+typedef enum
+{
+ TUSB_CLASS_UNSPECIFIED = 0 ,
+ TUSB_CLASS_AUDIO = 1 ,
+ TUSB_CLASS_CDC = 2 ,
+ TUSB_CLASS_HID = 3 ,
+ TUSB_CLASS_RESERVED_4 = 4 ,
+ TUSB_CLASS_PHYSICAL = 5 ,
+ TUSB_CLASS_IMAGE = 6 ,
+ TUSB_CLASS_PRINTER = 7 ,
+ TUSB_CLASS_MSC = 8 ,
+ TUSB_CLASS_HUB = 9 ,
+ TUSB_CLASS_CDC_DATA = 10 ,
+ TUSB_CLASS_SMART_CARD = 11 ,
+ TUSB_CLASS_RESERVED_12 = 12 ,
+ TUSB_CLASS_CONTENT_SECURITY = 13 ,
+ TUSB_CLASS_VIDEO = 14 ,
+ TUSB_CLASS_PERSONAL_HEALTHCARE = 15 ,
+ TUSB_CLASS_AUDIO_VIDEO = 16 ,
+
+ TUSB_CLASS_DIAGNOSTIC = 0xDC ,
+ TUSB_CLASS_WIRELESS_CONTROLLER = 0xE0 ,
+ TUSB_CLASS_MISC = 0xEF ,
+ TUSB_CLASS_APPLICATION_SPECIFIC = 0xFE ,
+ TUSB_CLASS_VENDOR_SPECIFIC = 0xFF
+}tusb_class_code_t;
+
+typedef enum
+{
+ MISC_SUBCLASS_COMMON = 2
+}misc_subclass_type_t;
+
+typedef enum
+{
+ MISC_PROTOCOL_IAD = 1
+}misc_protocol_type_t;
+
+typedef enum
+{
+ APP_SUBCLASS_USBTMC = 0x03,
+ APP_SUBCLASS_DFU_RUNTIME = 0x01
+} app_subclass_type_t;
+
+typedef enum
+{
+ DEVICE_CAPABILITY_WIRELESS_USB = 0x01,
+ DEVICE_CAPABILITY_USB20_EXTENSION = 0x02,
+ DEVICE_CAPABILITY_SUPERSPEED_USB = 0x03,
+ DEVICE_CAPABILITY_CONTAINER_id = 0x04,
+ DEVICE_CAPABILITY_PLATFORM = 0x05,
+ DEVICE_CAPABILITY_POWER_DELIVERY = 0x06,
+ DEVICE_CAPABILITY_BATTERY_INFO = 0x07,
+ DEVICE_CAPABILITY_PD_CONSUMER_PORT = 0x08,
+ DEVICE_CAPABILITY_PD_PROVIDER_PORT = 0x09,
+ DEVICE_CAPABILITY_SUPERSPEED_PLUS = 0x0A,
+ DEVICE_CAPABILITY_PRECESION_TIME_MEASUREMENT = 0x0B,
+ DEVICE_CAPABILITY_WIRELESS_USB_EXT = 0x0C,
+ DEVICE_CAPABILITY_BILLBOARD = 0x0D,
+ DEVICE_CAPABILITY_AUTHENTICATION = 0x0E,
+ DEVICE_CAPABILITY_BILLBOARD_EX = 0x0F,
+ DEVICE_CAPABILITY_CONFIGURATION_SUMMARY = 0x10
+}device_capability_type_t;
+
+enum {
+ TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP = TU_BIT(5),
+ TUSB_DESC_CONFIG_ATT_SELF_POWERED = TU_BIT(6),
+};
+
+#define TUSB_DESC_CONFIG_POWER_MA(x) ((x)/2)
+
+/// Device State TODO remove
+typedef enum
+{
+ TUSB_DEVICE_STATE_UNPLUG = 0 ,
+ TUSB_DEVICE_STATE_CONFIGURED ,
+ TUSB_DEVICE_STATE_SUSPENDED ,
+}tusb_device_state_t;
+
+typedef enum
+{
+ XFER_RESULT_SUCCESS,
+ XFER_RESULT_FAILED,
+ XFER_RESULT_STALLED,
+}xfer_result_t;
+
+enum // TODO remove
+{
+ DESC_OFFSET_LEN = 0,
+ DESC_OFFSET_TYPE = 1
+};
+
+enum
+{
+ INTERFACE_INVALID_NUMBER = 0xff
+};
+
+
+typedef enum
+{
+ MS_OS_20_SET_HEADER_DESCRIPTOR = 0x00,
+ MS_OS_20_SUBSET_HEADER_CONFIGURATION = 0x01,
+ MS_OS_20_SUBSET_HEADER_FUNCTION = 0x02,
+ MS_OS_20_FEATURE_COMPATBLE_ID = 0x03,
+ MS_OS_20_FEATURE_REG_PROPERTY = 0x04,
+ MS_OS_20_FEATURE_MIN_RESUME_TIME = 0x05,
+ MS_OS_20_FEATURE_MODEL_ID = 0x06,
+ MS_OS_20_FEATURE_CCGP_DEVICE = 0x07,
+ MS_OS_20_FEATURE_VENDOR_REVISION = 0x08
+} microsoft_os_20_type_t;
+
+enum
+{
+ CONTROL_STAGE_SETUP,
+ CONTROL_STAGE_DATA,
+ CONTROL_STAGE_ACK
+};
+
+//--------------------------------------------------------------------+
+// USB Descriptors
+//--------------------------------------------------------------------+
+
+// Start of all packed definitions for compiler without per-type packed
+TU_ATTR_PACKED_BEGIN
+TU_ATTR_BIT_FIELD_ORDER_BEGIN
+
+/// USB Device Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes.
+ uint8_t bDescriptorType ; ///< DEVICE Descriptor Type.
+ uint16_t bcdUSB ; ///< BUSB Specification Release Number in Binary-Coded Decimal (i.e., 2.10 is 210H). This field identifies the release of the USB Specification with which the device and its descriptors are compliant.
+
+ uint8_t bDeviceClass ; ///< Class code (assigned by the USB-IF). \li If this field is reset to zero, each interface within a configuration specifies its own class information and the various interfaces operate independently. \li If this field is set to a value between 1 and FEH, the device supports different class specifications on different interfaces and the interfaces may not operate independently. This value identifies the class definition used for the aggregate interfaces. \li If this field is set to FFH, the device class is vendor-specific.
+ uint8_t bDeviceSubClass ; ///< Subclass code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass field. \li If the bDeviceClass field is reset to zero, this field must also be reset to zero. \li If the bDeviceClass field is not set to FFH, all values are reserved for assignment by the USB-IF.
+ uint8_t bDeviceProtocol ; ///< Protocol code (assigned by the USB-IF). These codes are qualified by the value of the bDeviceClass and the bDeviceSubClass fields. If a device supports class-specific protocols on a device basis as opposed to an interface basis, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use class-specific protocols on a device basis. However, it may use classspecific protocols on an interface basis. \li If this field is set to FFH, the device uses a vendor-specific protocol on a device basis.
+ uint8_t bMaxPacketSize0 ; ///< Maximum packet size for endpoint zero (only 8, 16, 32, or 64 are valid). For HS devices is fixed to 64.
+
+ uint16_t idVendor ; ///< Vendor ID (assigned by the USB-IF).
+ uint16_t idProduct ; ///< Product ID (assigned by the manufacturer).
+ uint16_t bcdDevice ; ///< Device release number in binary-coded decimal.
+ uint8_t iManufacturer ; ///< Index of string descriptor describing manufacturer.
+ uint8_t iProduct ; ///< Index of string descriptor describing product.
+ uint8_t iSerialNumber ; ///< Index of string descriptor describing the device's serial number.
+
+ uint8_t bNumConfigurations ; ///< Number of possible configurations.
+} tusb_desc_device_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_desc_device_t) == 18, "size is not correct");
+
+// USB Binary Device Object Store (BOS) Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes
+ uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type
+ uint16_t wTotalLength ; ///< Total length of data returned for this descriptor
+ uint8_t bNumDeviceCaps ; ///< Number of device capability descriptors in the BOS
+} tusb_desc_bos_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_desc_bos_t) == 5, "size is not correct");
+
+/// USB Configuration Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes
+ uint8_t bDescriptorType ; ///< CONFIGURATION Descriptor Type
+ uint16_t wTotalLength ; ///< Total length of data returned for this configuration. Includes the combined length of all descriptors (configuration, interface, endpoint, and class- or vendor-specific) returned for this configuration.
+
+ uint8_t bNumInterfaces ; ///< Number of interfaces supported by this configuration
+ uint8_t bConfigurationValue ; ///< Value to use as an argument to the SetConfiguration() request to select this configuration.
+ uint8_t iConfiguration ; ///< Index of string descriptor describing this configuration
+ uint8_t bmAttributes ; ///< Configuration characteristics \n D7: Reserved (set to one)\n D6: Self-powered \n D5: Remote Wakeup \n D4...0: Reserved (reset to zero) \n D7 is reserved and must be set to one for historical reasons. \n A device configuration that uses power from the bus and a local source reports a non-zero value in bMaxPower to indicate the amount of bus power required and sets D6. The actual power source at runtime may be determined using the GetStatus(DEVICE) request (see USB 2.0 spec Section 9.4.5). \n If a device configuration supports remote wakeup, D5 is set to one.
+ uint8_t bMaxPower ; ///< Maximum power consumption of the USB device from the bus in this specific configuration when the device is fully operational. Expressed in 2 mA units (i.e., 50 = 100 mA).
+} tusb_desc_configuration_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_desc_configuration_t) == 9, "size is not correct");
+
+/// USB Interface Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes
+ uint8_t bDescriptorType ; ///< INTERFACE Descriptor Type
+
+ uint8_t bInterfaceNumber ; ///< Number of this interface. Zero-based value identifying the index in the array of concurrent interfaces supported by this configuration.
+ uint8_t bAlternateSetting ; ///< Value used to select this alternate setting for the interface identified in the prior field
+ uint8_t bNumEndpoints ; ///< Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the Default Control Pipe.
+ uint8_t bInterfaceClass ; ///< Class code (assigned by the USB-IF). \li A value of zero is reserved for future standardization. \li If this field is set to FFH, the interface class is vendor-specific. \li All other values are reserved for assignment by the USB-IF.
+ uint8_t bInterfaceSubClass ; ///< Subclass code (assigned by the USB-IF). \n These codes are qualified by the value of the bInterfaceClass field. \li If the bInterfaceClass field is reset to zero, this field must also be reset to zero. \li If the bInterfaceClass field is not set to FFH, all values are reserved for assignment by the USB-IF.
+ uint8_t bInterfaceProtocol ; ///< Protocol code (assigned by the USB). \n These codes are qualified by the value of the bInterfaceClass and the bInterfaceSubClass fields. If an interface supports class-specific requests, this code identifies the protocols that the device uses as defined by the specification of the device class. \li If this field is reset to zero, the device does not use a class-specific protocol on this interface. \li If this field is set to FFH, the device uses a vendor-specific protocol for this interface.
+ uint8_t iInterface ; ///< Index of string descriptor describing this interface
+} tusb_desc_interface_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_desc_interface_t) == 9, "size is not correct");
+
+/// USB Endpoint Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes
+ uint8_t bDescriptorType ; ///< ENDPOINT Descriptor Type
+
+ uint8_t bEndpointAddress ; ///< The address of the endpoint on the USB device described by this descriptor. The address is encoded as follows: \n Bit 3...0: The endpoint number \n Bit 6...4: Reserved, reset to zero \n Bit 7: Direction, ignored for control endpoints 0 = OUT endpoint 1 = IN endpoint.
+
+ struct TU_ATTR_PACKED {
+ uint8_t xfer : 2;
+ uint8_t sync : 2;
+ uint8_t usage : 2;
+ uint8_t : 2;
+ } bmAttributes ; ///< This field describes the endpoint's attributes when it is configured using the bConfigurationValue. \n Bits 1..0: Transfer Type \n- 00 = Control \n- 01 = Isochronous \n- 10 = Bulk \n- 11 = Interrupt \n If not an isochronous endpoint, bits 5..2 are reserved and must be set to zero. If isochronous, they are defined as follows: \n Bits 3..2: Synchronization Type \n- 00 = No Synchronization \n- 01 = Asynchronous \n- 10 = Adaptive \n- 11 = Synchronous \n Bits 5..4: Usage Type \n- 00 = Data endpoint \n- 01 = Feedback endpoint \n- 10 = Implicit feedback Data endpoint \n- 11 = Reserved \n Refer to Chapter 5 of USB 2.0 specification for more information. \n All other bits are reserved and must be reset to zero. Reserved bits must be ignored by the host.
+
+ struct TU_ATTR_PACKED {
+#if defined(__CCRX__)
+ //FIXME the original defined bit field has a problem with the CCRX toolchain, so only a size field is defined
+ uint16_t size;
+#else
+ uint16_t size : 11; ///< Maximum packet size this endpoint is capable of sending or receiving when this configuration is selected. \n For isochronous endpoints, this value is used to reserve the bus time in the schedule, required for the per-(micro)frame data payloads. The pipe may, on an ongoing basis, actually use less bandwidth than that reserved. The device reports, if necessary, the actual bandwidth used via its normal, non-USB defined mechanisms. \n For all endpoints, bits 10..0 specify the maximum packet size (in bytes). \n For high-speed isochronous and interrupt endpoints: \n Bits 12..11 specify the number of additional transaction opportunities per microframe: \n- 00 = None (1 transaction per microframe) \n- 01 = 1 additional (2 per microframe) \n- 10 = 2 additional (3 per microframe) \n- 11 = Reserved \n Bits 15..13 are reserved and must be set to zero.
+ uint16_t hs_period_mult : 2;
+ uint16_t TU_RESERVED : 3;
+#endif
+ }wMaxPacketSize;
+
+ uint8_t bInterval ; ///< Interval for polling endpoint for data transfers. Expressed in frames or microframes depending on the device operating speed (i.e., either 1 millisecond or 125 us units). \n- For full-/high-speed isochronous endpoints, this value must be in the range from 1 to 16. The bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$). \n- For full-/low-speed interrupt endpoints, the value of this field may be from 1 to 255. \n- For high-speed interrupt endpoints, the bInterval value is used as the exponent for a \f$ 2^(bInterval-1) \f$ value; e.g., a bInterval of 4 means a period of 8 (\f$ 2^(4-1) \f$) . This value must be from 1 to 16. \n- For high-speed bulk/control OUT endpoints, the bInterval must specify the maximum NAK rate of the endpoint. A value of 0 indicates the endpoint never NAKs. Other values indicate at most 1 NAK each bInterval number of microframes. This value must be in the range from 0 to 255. \n Refer to Chapter 5 of USB 2.0 specification for more information.
+} tusb_desc_endpoint_t;
+
+/// USB Other Speed Configuration Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of descriptor
+ uint8_t bDescriptorType ; ///< Other_speed_Configuration Type
+ uint16_t wTotalLength ; ///< Total length of data returned
+
+ uint8_t bNumInterfaces ; ///< Number of interfaces supported by this speed configuration
+ uint8_t bConfigurationValue ; ///< Value to use to select configuration
+ uint8_t iConfiguration ; ///< Index of string descriptor
+ uint8_t bmAttributes ; ///< Same as Configuration descriptor
+ uint8_t bMaxPower ; ///< Same as Configuration descriptor
+} tusb_desc_other_speed_t;
+
+/// USB Device Qualifier Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of descriptor
+ uint8_t bDescriptorType ; ///< Device Qualifier Type
+ uint16_t bcdUSB ; ///< USB specification version number (e.g., 0200H for V2.00)
+
+ uint8_t bDeviceClass ; ///< Class Code
+ uint8_t bDeviceSubClass ; ///< SubClass Code
+ uint8_t bDeviceProtocol ; ///< Protocol Code
+
+ uint8_t bMaxPacketSize0 ; ///< Maximum packet size for other speed
+ uint8_t bNumConfigurations ; ///< Number of Other-speed Configurations
+ uint8_t bReserved ; ///< Reserved for future use, must be zero
+} tusb_desc_device_qualifier_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_desc_device_qualifier_t) == 10, "size is not correct");
+
+/// USB Interface Association Descriptor (IAD ECN)
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of descriptor
+ uint8_t bDescriptorType ; ///< Other_speed_Configuration Type
+
+ uint8_t bFirstInterface ; ///< Index of the first associated interface.
+ uint8_t bInterfaceCount ; ///< Total number of associated interfaces.
+
+ uint8_t bFunctionClass ; ///< Interface class ID.
+ uint8_t bFunctionSubClass ; ///< Interface subclass ID.
+ uint8_t bFunctionProtocol ; ///< Interface protocol ID.
+
+ uint8_t iFunction ; ///< Index of the string descriptor describing the interface association.
+} tusb_desc_interface_assoc_t;
+
+// USB String Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength ; ///< Size of this descriptor in bytes
+ uint8_t bDescriptorType ; ///< Descriptor Type
+ uint16_t unicode_string[];
+} tusb_desc_string_t;
+
+// USB Binary Device Object Store (BOS)
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType ;
+ uint8_t bDevCapabilityType;
+ uint8_t bReserved;
+ uint8_t PlatformCapabilityUUID[16];
+ uint8_t CapabilityData[];
+} tusb_desc_bos_platform_t;
+
+// USB WebuSB URL Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+ uint8_t bScheme;
+ char url[];
+} tusb_desc_webusb_url_t;
+
+// DFU Functional Descriptor
+typedef struct TU_ATTR_PACKED
+{
+ uint8_t bLength;
+ uint8_t bDescriptorType;
+
+ union {
+ struct TU_ATTR_PACKED {
+ uint8_t bitCanDnload : 1;
+ uint8_t bitCanUpload : 1;
+ uint8_t bitManifestationTolerant : 1;
+ uint8_t bitWillDetach : 1;
+ uint8_t reserved : 4;
+ } bmAttributes;
+
+ uint8_t bAttributes;
+ };
+
+ uint16_t wDetachTimeOut;
+ uint16_t wTransferSize;
+ uint16_t bcdDFUVersion;
+} tusb_desc_dfu_functional_t;
+
+/*------------------------------------------------------------------*/
+/* Types
+ *------------------------------------------------------------------*/
+typedef struct TU_ATTR_PACKED{
+ union {
+ struct TU_ATTR_PACKED {
+ uint8_t recipient : 5; ///< Recipient type tusb_request_recipient_t.
+ uint8_t type : 2; ///< Request type tusb_request_type_t.
+ uint8_t direction : 1; ///< Direction type. tusb_dir_t
+ } bmRequestType_bit;
+
+ uint8_t bmRequestType;
+ };
+
+ uint8_t bRequest;
+ uint16_t wValue;
+ uint16_t wIndex;
+ uint16_t wLength;
+} tusb_control_request_t;
+
+TU_VERIFY_STATIC( sizeof(tusb_control_request_t) == 8, "size is not correct");
+
+
+TU_ATTR_PACKED_END // End of all packed definitions
+TU_ATTR_BIT_FIELD_ORDER_END
+
+//--------------------------------------------------------------------+
+// Endpoint helper
+//--------------------------------------------------------------------+
+
+// Get direction from Endpoint address
+static inline tusb_dir_t tu_edpt_dir(uint8_t addr)
+{
+ return (addr & TUSB_DIR_IN_MASK) ? TUSB_DIR_IN : TUSB_DIR_OUT;
+}
+
+// Get Endpoint number from address
+static inline uint8_t tu_edpt_number(uint8_t addr)
+{
+ return (uint8_t)(addr & (~TUSB_DIR_IN_MASK));
+}
+
+static inline uint8_t tu_edpt_addr(uint8_t num, uint8_t dir)
+{
+ return (uint8_t)(num | (dir ? TUSB_DIR_IN_MASK : 0));
+}
+
+//--------------------------------------------------------------------+
+// Descriptor helper
+//--------------------------------------------------------------------+
+static inline uint8_t const * tu_desc_next(void const* desc)
+{
+ uint8_t const* desc8 = (uint8_t const*) desc;
+ return desc8 + desc8[DESC_OFFSET_LEN];
+}
+
+static inline uint8_t tu_desc_type(void const* desc)
+{
+ return ((uint8_t const*) desc)[DESC_OFFSET_TYPE];
+}
+
+static inline uint8_t tu_desc_len(void const* desc)
+{
+ return ((uint8_t const*) desc)[DESC_OFFSET_LEN];
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _TUSB_TYPES_H_ */
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/tusb_verify.h b/arkanoid/pico/tinyusb/tusb_verify.h
new file mode 100644
index 0000000..56ba8bc
--- /dev/null
+++ b/arkanoid/pico/tinyusb/tusb_verify.h
@@ -0,0 +1,181 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#ifndef TUSB_VERIFY_H_
+#define TUSB_VERIFY_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "tusb_option.h"
+#include "tusb_compiler.h"
+
+/*------------------------------------------------------------------*/
+/* This file use an advanced macro technique to mimic the default parameter
+ * as C++ for the sake of code simplicity. Beware of a headache macro
+ * manipulation that you are told to stay away.
+ *
+ * This contains macros for both VERIFY and ASSERT:
+ *
+ * VERIFY: Used when there is an error condition which is not the
+ * fault of the MCU. For example, bounds checking on data
+ * sent to the micro over USB should use this function.
+ * Another example is checking for buffer overflows, where
+ * returning from the active function causes a NAK.
+ *
+ * ASSERT: Used for error conditions that are caused by MCU firmware
+ * bugs. This is used to discover bugs in the code more
+ * quickly. One example would be adding assertions in library
+ * function calls to confirm a function's (untainted)
+ * parameters are valid.
+ *
+ * The difference in behavior is that ASSERT triggers a breakpoint while
+ * verify does not.
+ *
+ * #define TU_VERIFY(cond) if(cond) return false;
+ * #define TU_VERIFY(cond,ret) if(cond) return ret;
+ *
+ * #define TU_VERIFY_HDLR(cond,handler) if(cond) {handler; return false;}
+ * #define TU_VERIFY_HDLR(cond,ret,handler) if(cond) {handler; return ret;}
+ *
+ * #define TU_ASSERT(cond) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return false;}
+ * #define TU_ASSERT(cond,ret) if(cond) {_MESS_FAILED(); TU_BREAKPOINT(), return ret;}
+ *
+ *------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// TU_VERIFY Helper
+//--------------------------------------------------------------------+
+
+#if CFG_TUSB_DEBUG
+ #include <stdio.h>
+ #define _MESS_ERR(_err) tu_printf("%s %d: failed, error = %s\r\n", __func__, __LINE__, tusb_strerr[_err])
+ #define _MESS_FAILED() tu_printf("%s %d: ASSERT FAILED\r\n", __func__, __LINE__)
+#else
+ #define _MESS_ERR(_err) do {} while (0)
+ #define _MESS_FAILED() do {} while (0)
+#endif
+
+// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7
+#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
+ #define TU_BREAKPOINT() do \
+ { \
+ volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
+ if ( (*ARM_CM_DHCSR) & 1UL ) __asm("BKPT #0\n"); /* Only halt mcu if debugger is attached */ \
+ } while(0)
+
+#elif defined(__riscv)
+ #define TU_BREAKPOINT() do { __asm("ebreak\n"); } while(0)
+
+#else
+ #define TU_BREAKPOINT() do {} while (0)
+#endif
+
+/*------------------------------------------------------------------*/
+/* Macro Generator
+ *------------------------------------------------------------------*/
+
+// Helper to implement optional parameter for TU_VERIFY Macro family
+#define GET_3RD_ARG(arg1, arg2, arg3, ...) arg3
+#define GET_4TH_ARG(arg1, arg2, arg3, arg4, ...) arg4
+
+/*------------- Generator for TU_VERIFY and TU_VERIFY_HDLR -------------*/
+#define TU_VERIFY_DEFINE(_cond, _handler, _ret) do \
+{ \
+ if ( !(_cond) ) { _handler; return _ret; } \
+} while(0)
+
+/*------------------------------------------------------------------*/
+/* TU_VERIFY
+ * - TU_VERIFY_1ARGS : return false if failed
+ * - TU_VERIFY_2ARGS : return provided value if failed
+ *------------------------------------------------------------------*/
+#define TU_VERIFY_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, , false)
+#define TU_VERIFY_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, , _ret)
+
+#define TU_VERIFY(...) GET_3RD_ARG(__VA_ARGS__, TU_VERIFY_2ARGS, TU_VERIFY_1ARGS, UNUSED)(__VA_ARGS__)
+
+
+/*------------------------------------------------------------------*/
+/* TU_VERIFY WITH HANDLER
+ * - TU_VERIFY_HDLR_2ARGS : execute handler, return false if failed
+ * - TU_VERIFY_HDLR_3ARGS : execute handler, return provided error if failed
+ *------------------------------------------------------------------*/
+#define TU_VERIFY_HDLR_2ARGS(_cond, _handler) TU_VERIFY_DEFINE(_cond, _handler, false)
+#define TU_VERIFY_HDLR_3ARGS(_cond, _handler, _ret) TU_VERIFY_DEFINE(_cond, _handler, _ret)
+
+#define TU_VERIFY_HDLR(...) GET_4TH_ARG(__VA_ARGS__, TU_VERIFY_HDLR_3ARGS, TU_VERIFY_HDLR_2ARGS,UNUSED)(__VA_ARGS__)
+
+/*------------------------------------------------------------------*/
+/* ASSERT
+ * basically TU_VERIFY with TU_BREAKPOINT() as handler
+ * - 1 arg : return false if failed
+ * - 2 arg : return error if failed
+ *------------------------------------------------------------------*/
+#define ASSERT_1ARGS(_cond) TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), false)
+#define ASSERT_2ARGS(_cond, _ret) TU_VERIFY_DEFINE(_cond, _MESS_FAILED(); TU_BREAKPOINT(), _ret)
+
+#ifndef TU_ASSERT
+#define TU_ASSERT(...) GET_3RD_ARG(__VA_ARGS__, ASSERT_2ARGS, ASSERT_1ARGS,UNUSED)(__VA_ARGS__)
+#endif
+
+// TODO remove TU_ASSERT_ERR() later
+
+/*------------- Generator for TU_VERIFY_ERR and TU_VERIFY_ERR_HDLR -------------*/
+#define TU_VERIFY_ERR_DEF2(_error, _handler) do \
+{ \
+ uint32_t _err = (uint32_t)(_error); \
+ if ( 0 != _err ) { _MESS_ERR(_err); _handler; return _err; } \
+} while(0)
+
+#define TU_VERIFY_ERR_DEF3(_error, _handler, _ret) do \
+{ \
+ uint32_t _err = (uint32_t)(_error); \
+ if ( 0 != _err ) { _MESS_ERR(_err); _handler; return _ret; } \
+} while(0)
+
+/*------------------------------------------------------------------*/
+/* ASSERT Error
+ * basically TU_VERIFY Error with TU_BREAKPOINT() as handler
+ *------------------------------------------------------------------*/
+#define ASSERT_ERR_1ARGS(_error) TU_VERIFY_ERR_DEF2(_error, TU_BREAKPOINT())
+#define ASSERT_ERR_2ARGS(_error, _ret) TU_VERIFY_ERR_DEF3(_error, TU_BREAKPOINT(), _ret)
+
+#ifndef TU_ASSERT_ERR
+#define TU_ASSERT_ERR(...) GET_3RD_ARG(__VA_ARGS__, ASSERT_ERR_2ARGS, ASSERT_ERR_1ARGS,UNUSED)(__VA_ARGS__)
+#endif
+
+/*------------------------------------------------------------------*/
+/* ASSERT HDLR
+ *------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* TUSB_VERIFY_H_ */
diff --git a/arkanoid/pico/tinyusb/usbd.c b/arkanoid/pico/tinyusb/usbd.c
new file mode 100644
index 0000000..dacaafa
--- /dev/null
+++ b/arkanoid/pico/tinyusb/usbd.c
@@ -0,0 +1,1416 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED
+
+#include "tusb.h"
+#include "usbd.h"
+#include "usbd_pvt.h"
+#include "dcd.h" // TODO was dcd.h
+
+//--------------------------------------------------------------------+
+// USBD Configuration
+//--------------------------------------------------------------------+
+
+// Debug level of USBD
+#define USBD_DBG 2
+
+#ifndef CFG_TUD_TASK_QUEUE_SZ
+ #define CFG_TUD_TASK_QUEUE_SZ 16
+#endif
+
+//--------------------------------------------------------------------+
+// Device Data
+//--------------------------------------------------------------------+
+
+// Invalid driver ID in itf2drv[] ep2drv[][] mapping
+enum { DRVID_INVALID = 0xFFu };
+
+typedef struct
+{
+ struct TU_ATTR_PACKED
+ {
+ volatile uint8_t connected : 1;
+ volatile uint8_t addressed : 1;
+ volatile uint8_t suspended : 1;
+
+ uint8_t remote_wakeup_en : 1; // enable/disable by host
+ uint8_t remote_wakeup_support : 1; // configuration descriptor's attribute
+ uint8_t self_powered : 1; // configuration descriptor's attribute
+ };
+
+ volatile uint8_t cfg_num; // current active configuration (0x00 is not configured)
+ uint8_t speed;
+
+ uint8_t itf2drv[16]; // map interface number to driver (0xff is invalid)
+ uint8_t ep2drv[CFG_TUD_ENDPPOINT_MAX][2]; // map endpoint to driver ( 0xff is invalid )
+
+ struct TU_ATTR_PACKED
+ {
+ volatile bool busy : 1;
+ volatile bool stalled : 1;
+ volatile bool claimed : 1;
+
+ // TODO merge ep2drv here, 4-bit should be sufficient
+ }ep_status[CFG_TUD_ENDPPOINT_MAX][2];
+
+}usbd_device_t;
+
+static usbd_device_t _usbd_dev;
+
+//--------------------------------------------------------------------+
+// Class Driver
+//--------------------------------------------------------------------+
+#if CFG_TUSB_DEBUG >= 2
+ #define DRIVER_NAME(_name) .name = _name,
+#else
+ #define DRIVER_NAME(_name)
+#endif
+
+// Built-in class drivers
+static usbd_class_driver_t const _usbd_driver[] =
+{
+ #if CFG_TUD_CDC
+ {
+ DRIVER_NAME("CDC")
+ .init = cdcd_init,
+ .reset = cdcd_reset,
+ .open = cdcd_open,
+ .control_xfer_cb = cdcd_control_xfer_cb,
+ .xfer_cb = cdcd_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_MSC
+ {
+ DRIVER_NAME("MSC")
+ .init = mscd_init,
+ .reset = mscd_reset,
+ .open = mscd_open,
+ .control_xfer_cb = mscd_control_xfer_cb,
+ .xfer_cb = mscd_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_HID
+ {
+ DRIVER_NAME("HID")
+ .init = hidd_init,
+ .reset = hidd_reset,
+ .open = hidd_open,
+ .control_xfer_cb = hidd_control_xfer_cb,
+ .xfer_cb = hidd_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_AUDIO
+ {
+ DRIVER_NAME("AUDIO")
+ .init = audiod_init,
+ .reset = audiod_reset,
+ .open = audiod_open,
+ .control_xfer_cb = audiod_control_xfer_cb,
+ .xfer_cb = audiod_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_VIDEO
+ {
+ DRIVER_NAME("VIDEO")
+ .init = videod_init,
+ .reset = videod_reset,
+ .open = videod_open,
+ .control_xfer_cb = videod_control_xfer_cb,
+ .xfer_cb = videod_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_MIDI
+ {
+ DRIVER_NAME("MIDI")
+ .init = midid_init,
+ .open = midid_open,
+ .reset = midid_reset,
+ .control_xfer_cb = midid_control_xfer_cb,
+ .xfer_cb = midid_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_VENDOR
+ {
+ DRIVER_NAME("VENDOR")
+ .init = vendord_init,
+ .reset = vendord_reset,
+ .open = vendord_open,
+ .control_xfer_cb = tud_vendor_control_xfer_cb,
+ .xfer_cb = vendord_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_USBTMC
+ {
+ DRIVER_NAME("TMC")
+ .init = usbtmcd_init_cb,
+ .reset = usbtmcd_reset_cb,
+ .open = usbtmcd_open_cb,
+ .control_xfer_cb = usbtmcd_control_xfer_cb,
+ .xfer_cb = usbtmcd_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_DFU_RUNTIME
+ {
+ DRIVER_NAME("DFU-RUNTIME")
+ .init = dfu_rtd_init,
+ .reset = dfu_rtd_reset,
+ .open = dfu_rtd_open,
+ .control_xfer_cb = dfu_rtd_control_xfer_cb,
+ .xfer_cb = NULL,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_DFU
+ {
+ DRIVER_NAME("DFU")
+ .init = dfu_moded_init,
+ .reset = dfu_moded_reset,
+ .open = dfu_moded_open,
+ .control_xfer_cb = dfu_moded_control_xfer_cb,
+ .xfer_cb = NULL,
+ .sof = NULL
+ },
+ #endif
+
+ #if CFG_TUD_ECM_RNDIS || CFG_TUD_NCM
+ {
+ DRIVER_NAME("NET")
+ .init = netd_init,
+ .reset = netd_reset,
+ .open = netd_open,
+ .control_xfer_cb = netd_control_xfer_cb,
+ .xfer_cb = netd_xfer_cb,
+ .sof = NULL,
+ },
+ #endif
+
+ #if CFG_TUD_BTH
+ {
+ DRIVER_NAME("BTH")
+ .init = btd_init,
+ .reset = btd_reset,
+ .open = btd_open,
+ .control_xfer_cb = btd_control_xfer_cb,
+ .xfer_cb = btd_xfer_cb,
+ .sof = NULL
+ },
+ #endif
+};
+
+enum { BUILTIN_DRIVER_COUNT = TU_ARRAY_SIZE(_usbd_driver) };
+
+// Additional class drivers implemented by application
+static usbd_class_driver_t const * _app_driver = NULL;
+static uint8_t _app_driver_count = 0;
+
+// virtually joins built-in and application drivers together.
+// Application is positioned first to allow overwriting built-in ones.
+static inline usbd_class_driver_t const * get_driver(uint8_t drvid)
+{
+ // Application drivers
+ if ( usbd_app_driver_get_cb )
+ {
+ if ( drvid < _app_driver_count ) return &_app_driver[drvid];
+ drvid -= _app_driver_count;
+ }
+
+ // Built-in drivers
+ if (drvid < BUILTIN_DRIVER_COUNT) return &_usbd_driver[drvid];
+
+ return NULL;
+}
+
+#define TOTAL_DRIVER_COUNT (_app_driver_count + BUILTIN_DRIVER_COUNT)
+
+//--------------------------------------------------------------------+
+// DCD Event
+//--------------------------------------------------------------------+
+
+static bool _usbd_initialized = false;
+
+// Event queue
+// OPT_MODE_DEVICE is used by OS NONE for mutex (disable usb isr)
+OSAL_QUEUE_DEF(OPT_MODE_DEVICE, _usbd_qdef, CFG_TUD_TASK_QUEUE_SZ, dcd_event_t);
+static osal_queue_t _usbd_q;
+
+// Mutex for claiming endpoint, only needed when using with preempted RTOS
+#if CFG_TUSB_OS != OPT_OS_NONE
+static osal_mutex_def_t _ubsd_mutexdef;
+static osal_mutex_t _usbd_mutex;
+#endif
+
+
+//--------------------------------------------------------------------+
+// Prototypes
+//--------------------------------------------------------------------+
+static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request);
+static bool process_set_config(uint8_t rhport, uint8_t cfg_num);
+static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const * p_request);
+
+// from usbd_control.c
+void usbd_control_reset(void);
+void usbd_control_set_request(tusb_control_request_t const *request);
+void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
+bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+
+
+//--------------------------------------------------------------------+
+// Debug
+//--------------------------------------------------------------------+
+#if CFG_TUSB_DEBUG >= 2
+static char const* const _usbd_event_str[DCD_EVENT_COUNT] =
+{
+ "Invalid" ,
+ "Bus Reset" ,
+ "Unplugged" ,
+ "SOF" ,
+ "Suspend" ,
+ "Resume" ,
+ "Setup Received" ,
+ "Xfer Complete" ,
+ "Func Call"
+};
+
+static char const* const _tusb_std_request_str[] =
+{
+ "Get Status" ,
+ "Clear Feature" ,
+ "Reserved" ,
+ "Set Feature" ,
+ "Reserved" ,
+ "Set Address" ,
+ "Get Descriptor" ,
+ "Set Descriptor" ,
+ "Get Configuration" ,
+ "Set Configuration" ,
+ "Get Interface" ,
+ "Set Interface" ,
+ "Synch Frame"
+};
+
+static char const* const _tusb_speed_str[] = { "Full", "Low", "High" };
+
+// for usbd_control to print the name of control complete driver
+void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback)
+{
+ for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
+ {
+ usbd_class_driver_t const * driver = get_driver(i);
+ if ( driver->control_xfer_cb == callback )
+ {
+ TU_LOG2(" %s control complete\r\n", driver->name);
+ return;
+ }
+ }
+}
+
+#endif
+
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+tusb_speed_t tud_speed_get(void)
+{
+ return (tusb_speed_t) _usbd_dev.speed;
+}
+
+bool tud_connected(void)
+{
+ return _usbd_dev.connected;
+}
+
+bool tud_mounted(void)
+{
+ return _usbd_dev.cfg_num ? true : false;
+}
+
+bool tud_suspended(void)
+{
+ return _usbd_dev.suspended;
+}
+
+bool tud_remote_wakeup(void)
+{
+ // only wake up host if this feature is supported and enabled and we are suspended
+ TU_VERIFY (_usbd_dev.suspended && _usbd_dev.remote_wakeup_support && _usbd_dev.remote_wakeup_en );
+ dcd_remote_wakeup(TUD_OPT_RHPORT);
+ return true;
+}
+
+bool tud_disconnect(void)
+{
+ TU_VERIFY(dcd_disconnect);
+ dcd_disconnect(TUD_OPT_RHPORT);
+ return true;
+}
+
+bool tud_connect(void)
+{
+ TU_VERIFY(dcd_connect);
+ dcd_connect(TUD_OPT_RHPORT);
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// USBD Task
+//--------------------------------------------------------------------+
+bool tud_inited(void)
+{
+ return _usbd_initialized;
+}
+
+bool tud_init (uint8_t rhport)
+{
+ // skip if already initialized
+ if (_usbd_initialized) return _usbd_initialized;
+
+ TU_LOG2("USBD init\r\n");
+
+ tu_varclr(&_usbd_dev);
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ // Init device mutex
+ _usbd_mutex = osal_mutex_create(&_ubsd_mutexdef);
+ TU_ASSERT(_usbd_mutex);
+#endif
+
+ // Init device queue & task
+ _usbd_q = osal_queue_create(&_usbd_qdef);
+ TU_ASSERT(_usbd_q);
+
+ // Get application driver if available
+ if ( usbd_app_driver_get_cb )
+ {
+ _app_driver = usbd_app_driver_get_cb(&_app_driver_count);
+ }
+
+ // Init class drivers
+ for (uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++)
+ {
+ usbd_class_driver_t const * driver = get_driver(i);
+ TU_LOG2("%s init\r\n", driver->name);
+ driver->init();
+ }
+
+ // Init device controller driver
+ dcd_init(rhport);
+ dcd_int_enable(rhport);
+
+ _usbd_initialized = true;
+
+ return true;
+}
+
+static void configuration_reset(uint8_t rhport)
+{
+ for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
+ {
+ get_driver(i)->reset(rhport);
+ }
+
+ tu_varclr(&_usbd_dev);
+ memset(_usbd_dev.itf2drv, DRVID_INVALID, sizeof(_usbd_dev.itf2drv)); // invalid mapping
+ memset(_usbd_dev.ep2drv , DRVID_INVALID, sizeof(_usbd_dev.ep2drv )); // invalid mapping
+}
+
+static void usbd_reset(uint8_t rhport)
+{
+ configuration_reset(rhport);
+ usbd_control_reset();
+}
+
+bool tud_task_event_ready(void)
+{
+ // Skip if stack is not initialized
+ if ( !tusb_inited() ) return false;
+
+ return !osal_queue_empty(_usbd_q);
+}
+
+/* USB Device Driver task
+ * This top level thread manages all device controller event and delegates events to class-specific drivers.
+ * This should be called periodically within the mainloop or rtos thread.
+ *
+ @code
+ int main(void)
+ {
+ application_init();
+ tusb_init();
+
+ while(1) // the mainloop
+ {
+ application_code();
+ tud_task(); // tinyusb device task
+ }
+ }
+ @endcode
+ */
+void tud_task (void)
+{
+ // Skip if stack is not initialized
+ if ( !tusb_inited() ) return;
+
+ // Loop until there is no more events in the queue
+ while (1)
+ {
+ dcd_event_t event;
+
+ if ( !osal_queue_receive(_usbd_q, &event) ) return;
+
+#if CFG_TUSB_DEBUG >= 2
+ if (event.event_id == DCD_EVENT_SETUP_RECEIVED) TU_LOG2("\r\n"); // extra line for setup
+ TU_LOG2("USBD %s ", event.event_id < DCD_EVENT_COUNT ? _usbd_event_str[event.event_id] : "CORRUPTED");
+#endif
+
+ switch ( event.event_id )
+ {
+ case DCD_EVENT_BUS_RESET:
+ TU_LOG2(": %s Speed\r\n", _tusb_speed_str[event.bus_reset.speed]);
+ usbd_reset(event.rhport);
+ _usbd_dev.speed = event.bus_reset.speed;
+ break;
+
+ case DCD_EVENT_UNPLUGGED:
+ TU_LOG2("\r\n");
+ usbd_reset(event.rhport);
+
+ // invoke callback
+ if (tud_umount_cb) tud_umount_cb();
+ break;
+
+ case DCD_EVENT_SETUP_RECEIVED:
+ TU_LOG2_VAR(&event.setup_received);
+ TU_LOG2("\r\n");
+
+ // Mark as connected after receiving 1st setup packet.
+ // But it is easier to set it every time instead of wasting time to check then set
+ _usbd_dev.connected = 1;
+
+ // mark both in & out control as free
+ _usbd_dev.ep_status[0][TUSB_DIR_OUT].busy = false;
+ _usbd_dev.ep_status[0][TUSB_DIR_OUT].claimed = 0;
+ _usbd_dev.ep_status[0][TUSB_DIR_IN ].busy = false;
+ _usbd_dev.ep_status[0][TUSB_DIR_IN ].claimed = 0;
+
+ // Process control request
+ if ( !process_control_request(event.rhport, &event.setup_received) )
+ {
+ TU_LOG2(" Stall EP0\r\n");
+ // Failed -> stall both control endpoint IN and OUT
+ dcd_edpt_stall(event.rhport, 0);
+ dcd_edpt_stall(event.rhport, 0 | TUSB_DIR_IN_MASK);
+ }
+ break;
+
+ case DCD_EVENT_XFER_COMPLETE:
+ {
+ // Invoke the class callback associated with the endpoint address
+ uint8_t const ep_addr = event.xfer_complete.ep_addr;
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const ep_dir = tu_edpt_dir(ep_addr);
+
+ TU_LOG2("on EP %02X with %u bytes\r\n", ep_addr, (unsigned int) event.xfer_complete.len);
+
+ _usbd_dev.ep_status[epnum][ep_dir].busy = false;
+ _usbd_dev.ep_status[epnum][ep_dir].claimed = 0;
+
+ if ( 0 == epnum )
+ {
+ usbd_control_xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
+ }
+ else
+ {
+ usbd_class_driver_t const * driver = get_driver( _usbd_dev.ep2drv[epnum][ep_dir] );
+ TU_ASSERT(driver, );
+
+ TU_LOG2(" %s xfer callback\r\n", driver->name);
+ driver->xfer_cb(event.rhport, ep_addr, (xfer_result_t)event.xfer_complete.result, event.xfer_complete.len);
+ }
+ }
+ break;
+
+ case DCD_EVENT_SUSPEND:
+ // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
+ // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ), which result in a series of event
+ // e.g suspend -> resume -> unplug/plug. Skip suspend/resume if not connected
+ if ( _usbd_dev.connected )
+ {
+ TU_LOG2(": Remote Wakeup = %u\r\n", _usbd_dev.remote_wakeup_en);
+ if (tud_suspend_cb) tud_suspend_cb(_usbd_dev.remote_wakeup_en);
+ }else
+ {
+ TU_LOG2(" Skipped\r\n");
+ }
+ break;
+
+ case DCD_EVENT_RESUME:
+ if ( _usbd_dev.connected )
+ {
+ TU_LOG2("\r\n");
+ if (tud_resume_cb) tud_resume_cb();
+ }else
+ {
+ TU_LOG2(" Skipped\r\n");
+ }
+ break;
+
+ case DCD_EVENT_SOF:
+ TU_LOG2("\r\n");
+ for ( uint8_t i = 0; i < TOTAL_DRIVER_COUNT; i++ )
+ {
+ usbd_class_driver_t const * driver = get_driver(i);
+ if ( driver->sof ) driver->sof(event.rhport);
+ }
+ break;
+
+ case USBD_EVENT_FUNC_CALL:
+ TU_LOG2("\r\n");
+ if ( event.func_call.func ) event.func_call.func(event.func_call.param);
+ break;
+
+ default:
+ TU_BREAKPOINT();
+ break;
+ }
+ }
+}
+
+//--------------------------------------------------------------------+
+// Control Request Parser & Handling
+//--------------------------------------------------------------------+
+
+// Helper to invoke class driver control request handler
+static bool invoke_class_control(uint8_t rhport, usbd_class_driver_t const * driver, tusb_control_request_t const * request)
+{
+ usbd_control_set_complete_callback(driver->control_xfer_cb);
+ TU_LOG2(" %s control request\r\n", driver->name);
+ return driver->control_xfer_cb(rhport, CONTROL_STAGE_SETUP, request);
+}
+
+// This handles the actual request and its response.
+// return false will cause its caller to stall control endpoint
+static bool process_control_request(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ usbd_control_set_complete_callback(NULL);
+
+ TU_ASSERT(p_request->bmRequestType_bit.type < TUSB_REQ_TYPE_INVALID);
+
+ // Vendor request
+ if ( p_request->bmRequestType_bit.type == TUSB_REQ_TYPE_VENDOR )
+ {
+ TU_VERIFY(tud_vendor_control_xfer_cb);
+
+ usbd_control_set_complete_callback(tud_vendor_control_xfer_cb);
+ return tud_vendor_control_xfer_cb(rhport, CONTROL_STAGE_SETUP, p_request);
+ }
+
+#if CFG_TUSB_DEBUG >= 2
+ if (TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type && p_request->bRequest <= TUSB_REQ_SYNCH_FRAME)
+ {
+ TU_LOG2(" %s", _tusb_std_request_str[p_request->bRequest]);
+ if (TUSB_REQ_GET_DESCRIPTOR != p_request->bRequest) TU_LOG2("\r\n");
+ }
+#endif
+
+ switch ( p_request->bmRequestType_bit.recipient )
+ {
+ //------------- Device Requests e.g in enumeration -------------//
+ case TUSB_REQ_RCPT_DEVICE:
+ if ( TUSB_REQ_TYPE_CLASS == p_request->bmRequestType_bit.type )
+ {
+ uint8_t const itf = tu_u16_low(p_request->wIndex);
+ TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv));
+
+ usbd_class_driver_t const * driver = get_driver(_usbd_dev.itf2drv[itf]);
+ TU_VERIFY(driver);
+
+ // forward to class driver: "non-STD request to Interface"
+ return invoke_class_control(rhport, driver, p_request);
+ }
+
+ if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type )
+ {
+ // Non standard request is not supported
+ TU_BREAKPOINT();
+ return false;
+ }
+
+ switch ( p_request->bRequest )
+ {
+ case TUSB_REQ_SET_ADDRESS:
+ // Depending on mcu, status phase could be sent either before or after changing device address,
+ // or even require stack to not response with status at all
+ // Therefore DCD must take full responsibility to response and include zlp status packet if needed.
+ usbd_control_set_request(p_request); // set request since DCD has no access to tud_control_status() API
+ dcd_set_address(rhport, (uint8_t) p_request->wValue);
+ // skip tud_control_status()
+ _usbd_dev.addressed = 1;
+ break;
+
+ case TUSB_REQ_GET_CONFIGURATION:
+ {
+ uint8_t cfg_num = _usbd_dev.cfg_num;
+ tud_control_xfer(rhport, p_request, &cfg_num, 1);
+ }
+ break;
+
+ case TUSB_REQ_SET_CONFIGURATION:
+ {
+ uint8_t const cfg_num = (uint8_t) p_request->wValue;
+
+ // Only process if new configure is different
+ if (_usbd_dev.cfg_num != cfg_num)
+ {
+ if ( _usbd_dev.cfg_num )
+ {
+ // already configured: need to clear all endpoints and driver first
+ TU_LOG(USBD_DBG, " Clear current Configuration (%u) before switching\r\n", _usbd_dev.cfg_num);
+
+ // close all non-control endpoints, cancel all pending transfers if any
+ dcd_edpt_close_all(rhport);
+
+ // close all drivers and current configured state except bus speed
+ uint8_t const speed = _usbd_dev.speed;
+ configuration_reset(rhport);
+
+ _usbd_dev.speed = speed; // restore speed
+ }
+
+ // switch to new configuration if not zero
+ if ( cfg_num ) TU_ASSERT( process_set_config(rhport, cfg_num) );
+ }
+
+ _usbd_dev.cfg_num = cfg_num;
+ tud_control_status(rhport, p_request);
+ }
+ break;
+
+ case TUSB_REQ_GET_DESCRIPTOR:
+ TU_VERIFY( process_get_descriptor(rhport, p_request) );
+ break;
+
+ case TUSB_REQ_SET_FEATURE:
+ // Only support remote wakeup for device feature
+ TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
+
+ TU_LOG(USBD_DBG, " Enable Remote Wakeup\r\n");
+
+ // Host may enable remote wake up before suspending especially HID device
+ _usbd_dev.remote_wakeup_en = true;
+ tud_control_status(rhport, p_request);
+ break;
+
+ case TUSB_REQ_CLEAR_FEATURE:
+ // Only support remote wakeup for device feature
+ TU_VERIFY(TUSB_REQ_FEATURE_REMOTE_WAKEUP == p_request->wValue);
+
+ TU_LOG(USBD_DBG, " Disable Remote Wakeup\r\n");
+
+ // Host may disable remote wake up after resuming
+ _usbd_dev.remote_wakeup_en = false;
+ tud_control_status(rhport, p_request);
+ break;
+
+ case TUSB_REQ_GET_STATUS:
+ {
+ // Device status bit mask
+ // - Bit 0: Self Powered
+ // - Bit 1: Remote Wakeup enabled
+ uint16_t status = (_usbd_dev.self_powered ? 1 : 0) | (_usbd_dev.remote_wakeup_en ? 2 : 0);
+ tud_control_xfer(rhport, p_request, &status, 2);
+ }
+ break;
+
+ // Unknown/Unsupported request
+ default: TU_BREAKPOINT(); return false;
+ }
+ break;
+
+ //------------- Interface Specific Request -------------//
+ case TUSB_REQ_RCPT_INTERFACE:
+ {
+ uint8_t const itf = tu_u16_low(p_request->wIndex);
+ TU_VERIFY(itf < TU_ARRAY_SIZE(_usbd_dev.itf2drv));
+
+ usbd_class_driver_t const * driver = get_driver(_usbd_dev.itf2drv[itf]);
+ TU_VERIFY(driver);
+
+ // all requests to Interface (STD or Class) is forwarded to class driver.
+ // notable requests are: GET HID REPORT DESCRIPTOR, SET_INTERFACE, GET_INTERFACE
+ if ( !invoke_class_control(rhport, driver, p_request) )
+ {
+ // For GET_INTERFACE and SET_INTERFACE, it is mandatory to respond even if the class
+ // driver doesn't use alternate settings or implement this
+ TU_VERIFY(TUSB_REQ_TYPE_STANDARD == p_request->bmRequestType_bit.type);
+
+ switch(p_request->bRequest)
+ {
+ case TUSB_REQ_GET_INTERFACE:
+ case TUSB_REQ_SET_INTERFACE:
+ // Clear complete callback if driver set since it can also stall the request.
+ usbd_control_set_complete_callback(NULL);
+
+ if (TUSB_REQ_GET_INTERFACE == p_request->bRequest)
+ {
+ uint8_t alternate = 0;
+ tud_control_xfer(rhport, p_request, &alternate, 1);
+ }else
+ {
+ tud_control_status(rhport, p_request);
+ }
+ break;
+
+ default: return false;
+ }
+ }
+ }
+ break;
+
+ //------------- Endpoint Request -------------//
+ case TUSB_REQ_RCPT_ENDPOINT:
+ {
+ uint8_t const ep_addr = tu_u16_low(p_request->wIndex);
+ uint8_t const ep_num = tu_edpt_number(ep_addr);
+ uint8_t const ep_dir = tu_edpt_dir(ep_addr);
+
+ TU_ASSERT(ep_num < TU_ARRAY_SIZE(_usbd_dev.ep2drv) );
+
+ usbd_class_driver_t const * driver = get_driver(_usbd_dev.ep2drv[ep_num][ep_dir]);
+
+ if ( TUSB_REQ_TYPE_STANDARD != p_request->bmRequestType_bit.type )
+ {
+ // Forward class request to its driver
+ TU_VERIFY(driver);
+ return invoke_class_control(rhport, driver, p_request);
+ }
+ else
+ {
+ // Handle STD request to endpoint
+ switch ( p_request->bRequest )
+ {
+ case TUSB_REQ_GET_STATUS:
+ {
+ uint16_t status = usbd_edpt_stalled(rhport, ep_addr) ? 0x0001 : 0x0000;
+ tud_control_xfer(rhport, p_request, &status, 2);
+ }
+ break;
+
+ case TUSB_REQ_CLEAR_FEATURE:
+ case TUSB_REQ_SET_FEATURE:
+ {
+ if ( TUSB_REQ_FEATURE_EDPT_HALT == p_request->wValue )
+ {
+ if ( TUSB_REQ_CLEAR_FEATURE == p_request->bRequest )
+ {
+ usbd_edpt_clear_stall(rhport, ep_addr);
+ }else
+ {
+ usbd_edpt_stall(rhport, ep_addr);
+ }
+ }
+
+ if (driver)
+ {
+ // Some classes such as USBTMC needs to clear/re-init its buffer when receiving CLEAR_FEATURE request
+ // We will also forward std request targeted endpoint to class drivers as well
+
+ // STD request must always be ACKed regardless of driver returned value
+ // Also clear complete callback if driver set since it can also stall the request.
+ (void) invoke_class_control(rhport, driver, p_request);
+ usbd_control_set_complete_callback(NULL);
+
+ // skip ZLP status if driver already did that
+ if ( !_usbd_dev.ep_status[0][TUSB_DIR_IN].busy ) tud_control_status(rhport, p_request);
+ }
+ }
+ break;
+
+ // Unknown/Unsupported request
+ default: TU_BREAKPOINT(); return false;
+ }
+ }
+ }
+ break;
+
+ // Unknown recipient
+ default: TU_BREAKPOINT(); return false;
+ }
+
+ return true;
+}
+
+// Process Set Configure Request
+// This function parse configuration descriptor & open drivers accordingly
+static bool process_set_config(uint8_t rhport, uint8_t cfg_num)
+{
+ // index is cfg_num-1
+ tusb_desc_configuration_t const * desc_cfg = (tusb_desc_configuration_t const *) tud_descriptor_configuration_cb(cfg_num-1);
+ TU_ASSERT(desc_cfg != NULL && desc_cfg->bDescriptorType == TUSB_DESC_CONFIGURATION);
+
+ // Parse configuration descriptor
+ _usbd_dev.remote_wakeup_support = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_REMOTE_WAKEUP) ? 1 : 0;
+ _usbd_dev.self_powered = (desc_cfg->bmAttributes & TUSB_DESC_CONFIG_ATT_SELF_POWERED ) ? 1 : 0;
+
+ // Parse interface descriptor
+ uint8_t const * p_desc = ((uint8_t const*) desc_cfg) + sizeof(tusb_desc_configuration_t);
+ uint8_t const * desc_end = ((uint8_t const*) desc_cfg) + tu_le16toh(desc_cfg->wTotalLength);
+
+ while( p_desc < desc_end )
+ {
+ uint8_t assoc_itf_count = 1;
+
+ // Class will always starts with Interface Association (if any) and then Interface descriptor
+ if ( TUSB_DESC_INTERFACE_ASSOCIATION == tu_desc_type(p_desc) )
+ {
+ tusb_desc_interface_assoc_t const * desc_iad = (tusb_desc_interface_assoc_t const *) p_desc;
+ assoc_itf_count = desc_iad->bInterfaceCount;
+
+ p_desc = tu_desc_next(p_desc); // next to Interface
+
+ // IAD's first interface number and class should match with opened interface
+ //TU_ASSERT(desc_iad->bFirstInterface == desc_itf->bInterfaceNumber &&
+ // desc_iad->bFunctionClass == desc_itf->bInterfaceClass);
+ }
+
+ TU_ASSERT( TUSB_DESC_INTERFACE == tu_desc_type(p_desc) );
+ tusb_desc_interface_t const * desc_itf = (tusb_desc_interface_t const*) p_desc;
+
+ // Find driver for this interface
+ uint16_t const remaining_len = desc_end-p_desc;
+ uint8_t drv_id;
+ for (drv_id = 0; drv_id < TOTAL_DRIVER_COUNT; drv_id++)
+ {
+ usbd_class_driver_t const *driver = get_driver(drv_id);
+ uint16_t const drv_len = driver->open(rhport, desc_itf, remaining_len);
+
+ if ( (sizeof(tusb_desc_interface_t) <= drv_len) && (drv_len <= remaining_len) )
+ {
+ // Open successfully
+ TU_LOG2(" %s opened\r\n", driver->name);
+
+ // Some drivers use 2 or more interfaces but may not have IAD e.g MIDI (always) or
+ // BTH (even CDC) with class in device descriptor (single interface)
+ if ( assoc_itf_count == 1)
+ {
+ #if CFG_TUD_CDC
+ if ( driver->open == cdcd_open ) assoc_itf_count = 2;
+ #endif
+
+ #if CFG_TUD_MIDI
+ if ( driver->open == midid_open ) assoc_itf_count = 2;
+ #endif
+
+ #if CFG_TUD_BTH && CFG_TUD_BTH_ISO_ALT_COUNT
+ if ( driver->open == btd_open ) assoc_itf_count = 2;
+ #endif
+ }
+
+ // bind (associated) interfaces to found driver
+ for(uint8_t i=0; i<assoc_itf_count; i++)
+ {
+ uint8_t const itf_num = desc_itf->bInterfaceNumber+i;
+
+ // Interface number must not be used already
+ TU_ASSERT(DRVID_INVALID == _usbd_dev.itf2drv[itf_num]);
+ _usbd_dev.itf2drv[itf_num] = drv_id;
+ }
+
+ // bind all endpoints to found driver
+ tu_edpt_bind_driver(_usbd_dev.ep2drv, desc_itf, drv_len, drv_id);
+
+ // next Interface
+ p_desc += drv_len;
+
+ break; // exit driver find loop
+ }
+ }
+
+ // Failed if there is no supported drivers
+ TU_ASSERT(drv_id < TOTAL_DRIVER_COUNT);
+ }
+
+ // invoke callback
+ if (tud_mount_cb) tud_mount_cb();
+
+ return true;
+}
+
+// return descriptor's buffer and update desc_len
+static bool process_get_descriptor(uint8_t rhport, tusb_control_request_t const * p_request)
+{
+ tusb_desc_type_t const desc_type = (tusb_desc_type_t) tu_u16_high(p_request->wValue);
+ uint8_t const desc_index = tu_u16_low( p_request->wValue );
+
+ switch(desc_type)
+ {
+ case TUSB_DESC_DEVICE:
+ {
+ TU_LOG2(" Device\r\n");
+
+ uint16_t len = sizeof(tusb_desc_device_t);
+
+ // Only send up to EP0 Packet Size if not addressed and host requested more data
+ // that device descriptor has.
+ // This only happens with the very first get device descriptor and EP0 size = 8 or 16.
+ if ((CFG_TUD_ENDPOINT0_SIZE < sizeof(tusb_desc_device_t)) && !_usbd_dev.addressed &&
+ ((tusb_control_request_t*) p_request)->wLength > sizeof(tusb_desc_device_t))
+ {
+ len = CFG_TUD_ENDPOINT0_SIZE;
+
+ // Hack here: we modify the request length to prevent usbd_control response with zlp
+ ((tusb_control_request_t*) p_request)->wLength = CFG_TUD_ENDPOINT0_SIZE;
+ }
+
+ return tud_control_xfer(rhport, p_request, (void*) tud_descriptor_device_cb(), len);
+ }
+ break;
+
+ case TUSB_DESC_BOS:
+ {
+ TU_LOG2(" BOS\r\n");
+
+ // requested by host if USB > 2.0 ( i.e 2.1 or 3.x )
+ if (!tud_descriptor_bos_cb) return false;
+
+ tusb_desc_bos_t const* desc_bos = (tusb_desc_bos_t const*) tud_descriptor_bos_cb();
+
+ // Use offsetof to avoid pointer to the odd/misaligned address
+ uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_bos + offsetof(tusb_desc_bos_t, wTotalLength)) );
+
+ return tud_control_xfer(rhport, p_request, (void*) desc_bos, total_len);
+ }
+ break;
+
+ case TUSB_DESC_CONFIGURATION:
+ case TUSB_DESC_OTHER_SPEED_CONFIG:
+ {
+ tusb_desc_configuration_t const* desc_config;
+
+ if ( desc_type == TUSB_DESC_CONFIGURATION )
+ {
+ TU_LOG2(" Configuration[%u]\r\n", desc_index);
+ desc_config = (tusb_desc_configuration_t const*) tud_descriptor_configuration_cb(desc_index);
+ }else
+ {
+ // Host only request this after getting Device Qualifier descriptor
+ TU_LOG2(" Other Speed Configuration\r\n");
+ TU_VERIFY( tud_descriptor_other_speed_configuration_cb );
+ desc_config = (tusb_desc_configuration_t const*) tud_descriptor_other_speed_configuration_cb(desc_index);
+ }
+
+ TU_ASSERT(desc_config);
+
+ // Use offsetof to avoid pointer to the odd/misaligned address
+ uint16_t const total_len = tu_le16toh( tu_unaligned_read16((uint8_t*) desc_config + offsetof(tusb_desc_configuration_t, wTotalLength)) );
+
+ return tud_control_xfer(rhport, p_request, (void*) desc_config, total_len);
+ }
+ break;
+
+ case TUSB_DESC_STRING:
+ {
+ TU_LOG2(" String[%u]\r\n", desc_index);
+
+ // String Descriptor always uses the desc set from user
+ uint8_t const* desc_str = (uint8_t const*) tud_descriptor_string_cb(desc_index, p_request->wIndex);
+ TU_VERIFY(desc_str);
+
+ // first byte of descriptor is its size
+ return tud_control_xfer(rhport, p_request, (void*) desc_str, desc_str[0]);
+ }
+ break;
+
+ case TUSB_DESC_DEVICE_QUALIFIER:
+ {
+ TU_LOG2(" Device Qualifier\r\n");
+
+ TU_VERIFY( tud_descriptor_device_qualifier_cb );
+
+ uint8_t const* desc_qualifier = tud_descriptor_device_qualifier_cb();
+ TU_VERIFY(desc_qualifier);
+
+ // first byte of descriptor is its size
+ return tud_control_xfer(rhport, p_request, (void*) desc_qualifier, desc_qualifier[0]);
+ }
+ break;
+
+ default: return false;
+ }
+}
+
+//--------------------------------------------------------------------+
+// DCD Event Handler
+//--------------------------------------------------------------------+
+void dcd_event_handler(dcd_event_t const * event, bool in_isr)
+{
+ switch (event->event_id)
+ {
+ case DCD_EVENT_UNPLUGGED:
+ _usbd_dev.connected = 0;
+ _usbd_dev.addressed = 0;
+ _usbd_dev.cfg_num = 0;
+ _usbd_dev.suspended = 0;
+ osal_queue_send(_usbd_q, event, in_isr);
+ break;
+
+ case DCD_EVENT_SUSPEND:
+ // NOTE: When plugging/unplugging device, the D+/D- state are unstable and
+ // can accidentally meet the SUSPEND condition ( Bus Idle for 3ms ).
+ // In addition, some MCUs such as SAMD or boards that haven no VBUS detection cannot distinguish
+ // suspended vs disconnected. We will skip handling SUSPEND/RESUME event if not currently connected
+ if ( _usbd_dev.connected )
+ {
+ _usbd_dev.suspended = 1;
+ osal_queue_send(_usbd_q, event, in_isr);
+ }
+ break;
+
+ case DCD_EVENT_RESUME:
+ // skip event if not connected (especially required for SAMD)
+ if ( _usbd_dev.connected )
+ {
+ _usbd_dev.suspended = 0;
+ osal_queue_send(_usbd_q, event, in_isr);
+ }
+ break;
+
+ case DCD_EVENT_SOF:
+ // Some MCUs after running dcd_remote_wakeup() does not have way to detect the end of remote wakeup
+ // which last 1-15 ms. DCD can use SOF as a clear indicator that bus is back to operational
+ if ( _usbd_dev.suspended )
+ {
+ _usbd_dev.suspended = 0;
+ dcd_event_t const event_resume = { .rhport = event->rhport, .event_id = DCD_EVENT_RESUME };
+ osal_queue_send(_usbd_q, &event_resume, in_isr);
+ }
+ break;
+
+ default:
+ osal_queue_send(_usbd_q, event, in_isr);
+ break;
+ }
+}
+
+void dcd_event_bus_signal (uint8_t rhport, dcd_eventid_t eid, bool in_isr)
+{
+ dcd_event_t event = { .rhport = rhport, .event_id = eid };
+ dcd_event_handler(&event, in_isr);
+}
+
+void dcd_event_bus_reset (uint8_t rhport, tusb_speed_t speed, bool in_isr)
+{
+ dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_BUS_RESET };
+ event.bus_reset.speed = speed;
+ dcd_event_handler(&event, in_isr);
+}
+
+void dcd_event_setup_received(uint8_t rhport, uint8_t const * setup, bool in_isr)
+{
+ dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_SETUP_RECEIVED };
+ memcpy(&event.setup_received, setup, 8);
+
+ dcd_event_handler(&event, in_isr);
+}
+
+void dcd_event_xfer_complete (uint8_t rhport, uint8_t ep_addr, uint32_t xferred_bytes, uint8_t result, bool in_isr)
+{
+ dcd_event_t event = { .rhport = rhport, .event_id = DCD_EVENT_XFER_COMPLETE };
+
+ event.xfer_complete.ep_addr = ep_addr;
+ event.xfer_complete.len = xferred_bytes;
+ event.xfer_complete.result = result;
+
+ dcd_event_handler(&event, in_isr);
+}
+
+//--------------------------------------------------------------------+
+// USBD API For Class Driver
+//--------------------------------------------------------------------+
+
+// Parse consecutive endpoint descriptors (IN & OUT)
+bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in)
+{
+ for(int i=0; i<ep_count; i++)
+ {
+ tusb_desc_endpoint_t const * desc_ep = (tusb_desc_endpoint_t const *) p_desc;
+
+ TU_ASSERT(TUSB_DESC_ENDPOINT == desc_ep->bDescriptorType && xfer_type == desc_ep->bmAttributes.xfer);
+ TU_ASSERT(usbd_edpt_open(rhport, desc_ep));
+
+ if ( tu_edpt_dir(desc_ep->bEndpointAddress) == TUSB_DIR_IN )
+ {
+ (*ep_in) = desc_ep->bEndpointAddress;
+ }else
+ {
+ (*ep_out) = desc_ep->bEndpointAddress;
+ }
+
+ p_desc = tu_desc_next(p_desc);
+ }
+
+ return true;
+}
+
+// Helper to defer an isr function
+void usbd_defer_func(osal_task_func_t func, void* param, bool in_isr)
+{
+ dcd_event_t event =
+ {
+ .rhport = 0,
+ .event_id = USBD_EVENT_FUNC_CALL,
+ };
+
+ event.func_call.func = func;
+ event.func_call.param = param;
+
+ dcd_event_handler(&event, in_isr);
+}
+
+//--------------------------------------------------------------------+
+// USBD Endpoint API
+//--------------------------------------------------------------------+
+
+bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep)
+{
+ TU_ASSERT(tu_edpt_number(desc_ep->bEndpointAddress) < CFG_TUD_ENDPPOINT_MAX);
+ TU_ASSERT(tu_edpt_validate(desc_ep, (tusb_speed_t) _usbd_dev.speed));
+
+ return dcd_edpt_open(rhport, desc_ep);
+}
+
+bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+
+ // TODO add this check later, also make sure we don't starve an out endpoint while suspending
+ // TU_VERIFY(tud_ready());
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ // pre-check to help reducing mutex lock
+ TU_VERIFY((_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0));
+ osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+ // can only claim the endpoint if it is not busy and not claimed yet.
+ bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 0);
+ if (ret)
+ {
+ _usbd_dev.ep_status[epnum][dir].claimed = 1;
+ }
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ osal_mutex_unlock(_usbd_mutex);
+#endif
+
+ return ret;
+}
+
+bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ osal_mutex_lock(_usbd_mutex, OSAL_TIMEOUT_WAIT_FOREVER);
+#endif
+
+ // can only release the endpoint if it is claimed and not busy
+ bool const ret = (_usbd_dev.ep_status[epnum][dir].busy == 0) && (_usbd_dev.ep_status[epnum][dir].claimed == 1);
+ if (ret)
+ {
+ _usbd_dev.ep_status[epnum][dir].claimed = 0;
+ }
+
+#if CFG_TUSB_OS != OPT_OS_NONE
+ osal_mutex_unlock(_usbd_mutex);
+#endif
+
+ return ret;
+}
+
+bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes)
+{
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ // TODO skip ready() check for now since enumeration also use this API
+ // TU_VERIFY(tud_ready());
+
+ TU_LOG2(" Queue EP %02X with %u bytes ...\r\n", ep_addr, total_bytes);
+
+ // Attempt to transfer on a busy endpoint, sound like an race condition !
+ TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
+
+ // Set busy first since the actual transfer can be complete before dcd_edpt_xfer()
+ // could return and USBD task can preempt and clear the busy
+ _usbd_dev.ep_status[epnum][dir].busy = true;
+
+ if ( dcd_edpt_xfer(rhport, ep_addr, buffer, total_bytes) )
+ {
+ return true;
+ }else
+ {
+ // DCD error, mark endpoint as ready to allow next transfer
+ _usbd_dev.ep_status[epnum][dir].busy = false;
+ _usbd_dev.ep_status[epnum][dir].claimed = 0;
+ TU_LOG2("FAILED\r\n");
+ TU_BREAKPOINT();
+ return false;
+ }
+}
+
+// The number of bytes has to be given explicitly to allow more flexible control of how many
+// bytes should be written and second to keep the return value free to give back a boolean
+// success message. If total_bytes is too big, the FIFO will copy only what is available
+// into the USB buffer!
+bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes)
+{
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ TU_LOG2(" Queue ISO EP %02X with %u bytes ... ", ep_addr, total_bytes);
+
+ // Attempt to transfer on a busy endpoint, sound like an race condition !
+ TU_ASSERT(_usbd_dev.ep_status[epnum][dir].busy == 0);
+
+ // Set busy first since the actual transfer can be complete before dcd_edpt_xfer() could return
+ // and usbd task can preempt and clear the busy
+ _usbd_dev.ep_status[epnum][dir].busy = true;
+
+ if (dcd_edpt_xfer_fifo(rhport, ep_addr, ff, total_bytes))
+ {
+ TU_LOG2("OK\r\n");
+ return true;
+ }else
+ {
+ // DCD error, mark endpoint as ready to allow next transfer
+ _usbd_dev.ep_status[epnum][dir].busy = false;
+ _usbd_dev.ep_status[epnum][dir].claimed = 0;
+ TU_LOG2("failed\r\n");
+ TU_BREAKPOINT();
+ return false;
+ }
+}
+
+bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ return _usbd_dev.ep_status[epnum][dir].busy;
+}
+
+void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr)
+{
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ // only stalled if currently cleared
+ if ( !_usbd_dev.ep_status[epnum][dir].stalled )
+ {
+ TU_LOG(USBD_DBG, " Stall EP %02X\r\n", ep_addr);
+ dcd_edpt_stall(rhport, ep_addr);
+ _usbd_dev.ep_status[epnum][dir].stalled = true;
+ _usbd_dev.ep_status[epnum][dir].busy = true;
+ }
+}
+
+void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr)
+{
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ // only clear if currently stalled
+ if ( _usbd_dev.ep_status[epnum][dir].stalled )
+ {
+ TU_LOG(USBD_DBG, " Clear Stall EP %02X\r\n", ep_addr);
+ dcd_edpt_clear_stall(rhport, ep_addr);
+ _usbd_dev.ep_status[epnum][dir].stalled = false;
+ _usbd_dev.ep_status[epnum][dir].busy = false;
+ }
+}
+
+bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr)
+{
+ (void) rhport;
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ return _usbd_dev.ep_status[epnum][dir].stalled;
+}
+
+/**
+ * usbd_edpt_close will disable an endpoint.
+ *
+ * In progress transfers on this EP may be delivered after this call.
+ *
+ */
+void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr)
+{
+ TU_ASSERT(dcd_edpt_close, /**/);
+ TU_LOG2(" CLOSING Endpoint: 0x%02X\r\n", ep_addr);
+
+ uint8_t const epnum = tu_edpt_number(ep_addr);
+ uint8_t const dir = tu_edpt_dir(ep_addr);
+
+ dcd_edpt_close(rhport, ep_addr);
+ _usbd_dev.ep_status[epnum][dir].stalled = false;
+ _usbd_dev.ep_status[epnum][dir].busy = false;
+ _usbd_dev.ep_status[epnum][dir].claimed = false;
+
+ return;
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/usbd.h b/arkanoid/pico/tinyusb/usbd.h
new file mode 100644
index 0000000..e35a260
--- /dev/null
+++ b/arkanoid/pico/tinyusb/usbd.h
@@ -0,0 +1,851 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#ifndef _TUSB_USBD_H_
+#define _TUSB_USBD_H_
+
+#include "tusb_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
+// Init device stack
+bool tud_init (uint8_t rhport);
+
+// Check if device stack is already initialized
+bool tud_inited(void);
+
+// Task function should be called in main/rtos loop
+void tud_task (void);
+
+// Check if there is pending events need proccessing by tud_task()
+bool tud_task_event_ready(void);
+
+// Interrupt handler, name alias to DCD
+extern void dcd_int_handler(uint8_t rhport);
+#define tud_int_handler dcd_int_handler
+
+// Get current bus speed
+tusb_speed_t tud_speed_get(void);
+
+// Check if device is connected (may not mounted/configured yet)
+// True if just got out of Bus Reset and received the very first data from host
+bool tud_connected(void);
+
+// Check if device is connected and configured
+bool tud_mounted(void);
+
+// Check if device is suspended
+bool tud_suspended(void);
+
+// Check if device is ready to transfer
+TU_ATTR_ALWAYS_INLINE static inline
+bool tud_ready(void)
+{
+ return tud_mounted() && !tud_suspended();
+}
+
+// Remote wake up host, only if suspended and enabled by host
+bool tud_remote_wakeup(void);
+
+// Enable pull-up resistor on D+ D-
+// Return false on unsupported MCUs
+bool tud_disconnect(void);
+
+// Disable pull-up resistor on D+ D-
+// Return false on unsupported MCUs
+bool tud_connect(void);
+
+// Carry out Data and Status stage of control transfer
+// - If len = 0, it is equivalent to sending status only
+// - If len > wLength : it will be truncated
+bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len);
+
+// Send STATUS (zero length) packet
+bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request);
+
+//--------------------------------------------------------------------+
+// Application Callbacks (WEAK is optional)
+//--------------------------------------------------------------------+
+
+// Invoked when received GET DEVICE DESCRIPTOR request
+// Application return pointer to descriptor
+uint8_t const * tud_descriptor_device_cb(void);
+
+// Invoked when received GET CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint8_t const * tud_descriptor_configuration_cb(uint8_t index);
+
+// Invoked when received GET STRING DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+uint16_t const* tud_descriptor_string_cb(uint8_t index, uint16_t langid);
+
+// Invoked when received GET BOS DESCRIPTOR request
+// Application return pointer to descriptor
+TU_ATTR_WEAK uint8_t const * tud_descriptor_bos_cb(void);
+
+// Invoked when received GET DEVICE QUALIFIER DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete.
+// device_qualifier descriptor describes information about a high-speed capable device that would
+// change if the device were operating at the other speed. If not highspeed capable stall this request.
+TU_ATTR_WEAK uint8_t const* tud_descriptor_device_qualifier_cb(void);
+
+// Invoked when received GET OTHER SEED CONFIGURATION DESCRIPTOR request
+// Application return pointer to descriptor, whose contents must exist long enough for transfer to complete
+// Configuration descriptor in the other speed e.g if high speed then this is for full speed and vice versa
+TU_ATTR_WEAK uint8_t const* tud_descriptor_other_speed_configuration_cb(uint8_t index);
+
+// Invoked when device is mounted (configured)
+TU_ATTR_WEAK void tud_mount_cb(void);
+
+// Invoked when device is unmounted
+TU_ATTR_WEAK void tud_umount_cb(void);
+
+// Invoked when usb bus is suspended
+// Within 7ms, device must draw an average of current less than 2.5 mA from bus
+TU_ATTR_WEAK void tud_suspend_cb(bool remote_wakeup_en);
+
+// Invoked when usb bus is resumed
+TU_ATTR_WEAK void tud_resume_cb(void);
+
+// Invoked when received control request with VENDOR TYPE
+TU_ATTR_WEAK bool tud_vendor_control_xfer_cb(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+
+//--------------------------------------------------------------------+
+// Binary Device Object Store (BOS) Descriptor Templates
+//--------------------------------------------------------------------+
+
+#define TUD_BOS_DESC_LEN 5
+
+// total length, number of device caps
+#define TUD_BOS_DESCRIPTOR(_total_len, _caps_num) \
+ 5, TUSB_DESC_BOS, U16_TO_U8S_LE(_total_len), _caps_num
+
+// Device Capability Platform 128-bit UUID + Data
+#define TUD_BOS_PLATFORM_DESCRIPTOR(...) \
+ 4+TU_ARGS_NUM(__VA_ARGS__), TUSB_DESC_DEVICE_CAPABILITY, DEVICE_CAPABILITY_PLATFORM, 0x00, __VA_ARGS__
+
+//------------- WebUSB BOS Platform -------------//
+
+// Descriptor Length
+#define TUD_BOS_WEBUSB_DESC_LEN 24
+
+// Vendor Code, iLandingPage
+#define TUD_BOS_WEBUSB_DESCRIPTOR(_vendor_code, _ipage) \
+ TUD_BOS_PLATFORM_DESCRIPTOR(TUD_BOS_WEBUSB_UUID, U16_TO_U8S_LE(0x0100), _vendor_code, _ipage)
+
+#define TUD_BOS_WEBUSB_UUID \
+ 0x38, 0xB6, 0x08, 0x34, 0xA9, 0x09, 0xA0, 0x47, \
+ 0x8B, 0xFD, 0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65
+
+//------------- Microsoft OS 2.0 Platform -------------//
+#define TUD_BOS_MICROSOFT_OS_DESC_LEN 28
+
+// Total Length of descriptor set, vendor code
+#define TUD_BOS_MS_OS_20_DESCRIPTOR(_desc_set_len, _vendor_code) \
+ TUD_BOS_PLATFORM_DESCRIPTOR(TUD_BOS_MS_OS_20_UUID, U32_TO_U8S_LE(0x06030000), U16_TO_U8S_LE(_desc_set_len), _vendor_code, 0)
+
+#define TUD_BOS_MS_OS_20_UUID \
+ 0xDF, 0x60, 0xDD, 0xD8, 0x89, 0x45, 0xC7, 0x4C, \
+ 0x9C, 0xD2, 0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F
+
+//--------------------------------------------------------------------+
+// Configuration Descriptor Templates
+//--------------------------------------------------------------------+
+
+#define TUD_CONFIG_DESC_LEN (9)
+
+// Config number, interface count, string index, total length, attribute, power in mA
+#define TUD_CONFIG_DESCRIPTOR(config_num, _itfcount, _stridx, _total_len, _attribute, _power_ma) \
+ 9, TUSB_DESC_CONFIGURATION, U16_TO_U8S_LE(_total_len), _itfcount, config_num, _stridx, TU_BIT(7) | _attribute, (_power_ma)/2
+
+//--------------------------------------------------------------------+
+// CDC Descriptor Templates
+//--------------------------------------------------------------------+
+
+// Length of template descriptor: 66 bytes
+#define TUD_CDC_DESC_LEN (8+9+5+5+4+5+7+9+7+7)
+
+// CDC Descriptor Template
+// Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+#define TUD_CDC_DESCRIPTOR(_itfnum, _stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize) \
+ /* Interface Associate */\
+ 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL, CDC_COMM_PROTOCOL_NONE, 0,\
+ /* CDC Control Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL, CDC_COMM_PROTOCOL_NONE, _stridx,\
+ /* CDC Header */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120),\
+ /* CDC Call */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1),\
+ /* CDC ACM: support line request */\
+ 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 2,\
+ /* CDC Union */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
+ /* Endpoint Notification */\
+ 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 16,\
+ /* CDC Data Interface */\
+ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0,\
+ /* Endpoint Out */\
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
+//--------------------------------------------------------------------+
+// MSC Descriptor Templates
+//--------------------------------------------------------------------+
+
+// Length of template descriptor: 23 bytes
+#define TUD_MSC_DESC_LEN (9 + 7 + 7)
+
+// Interface number, string index, EP Out & EP In address, EP size
+#define TUD_MSC_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \
+ /* Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_MSC, MSC_SUBCLASS_SCSI, MSC_PROTOCOL_BOT, _stridx,\
+ /* Endpoint Out */\
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
+
+//--------------------------------------------------------------------+
+// HID Descriptor Templates
+//--------------------------------------------------------------------+
+
+// Length of template descriptor: 25 bytes
+#define TUD_HID_DESC_LEN (9 + 9 + 7)
+
+// HID Input only descriptor
+// Interface number, string index, protocol, report descriptor len, EP In address, size & polling interval
+#define TUD_HID_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epin, _epsize, _ep_interval) \
+ /* Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\
+ /* HID descriptor */\
+ 9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len),\
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval
+
+// Length of template descriptor: 32 bytes
+#define TUD_HID_INOUT_DESC_LEN (9 + 9 + 7 + 7)
+
+// HID Input & Output descriptor
+// Interface number, string index, protocol, report descriptor len, EP OUT & IN address, size & polling interval
+#define TUD_HID_INOUT_DESCRIPTOR(_itfnum, _stridx, _boot_protocol, _report_desc_len, _epout, _epin, _epsize, _ep_interval) \
+ /* Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_HID, (uint8_t)((_boot_protocol) ? (uint8_t)HID_SUBCLASS_BOOT : 0), _boot_protocol, _stridx,\
+ /* HID descriptor */\
+ 9, HID_DESC_TYPE_HID, U16_TO_U8S_LE(0x0111), 0, 1, HID_DESC_TYPE_REPORT, U16_TO_U8S_LE(_report_desc_len),\
+ /* Endpoint Out */\
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval, \
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_epsize), _ep_interval
+
+//--------------------------------------------------------------------+
+// MIDI Descriptor Templates
+// Note: MIDI v1.0 is based on Audio v1.0
+//--------------------------------------------------------------------+
+
+#define TUD_MIDI_DESC_HEAD_LEN (9 + 9 + 9 + 7)
+#define TUD_MIDI_DESC_HEAD(_itfnum, _stridx, _numcables) \
+ /* Audio Control (AC) Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_CONTROL, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, _stridx,\
+ /* AC Header */\
+ 9, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(0x0009), 1, (uint8_t)((_itfnum) + 1),\
+ /* MIDI Streaming (MS) Interface */\
+ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum) + 1), 0, 2, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_MIDI_STREAMING, AUDIO_FUNC_PROTOCOL_CODE_UNDEF, 0,\
+ /* MS Header */\
+ 7, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_HEADER, U16_TO_U8S_LE(0x0100), U16_TO_U8S_LE(7 + (_numcables) * TUD_MIDI_DESC_JACK_LEN)
+
+#define TUD_MIDI_JACKID_IN_EMB(_cablenum) \
+ (uint8_t)(((_cablenum) - 1) * 4 + 1)
+
+#define TUD_MIDI_JACKID_IN_EXT(_cablenum) \
+ (uint8_t)(((_cablenum) - 1) * 4 + 2)
+
+#define TUD_MIDI_JACKID_OUT_EMB(_cablenum) \
+ (uint8_t)(((_cablenum) - 1) * 4 + 3)
+
+#define TUD_MIDI_JACKID_OUT_EXT(_cablenum) \
+ (uint8_t)(((_cablenum) - 1) * 4 + 4)
+
+#define TUD_MIDI_DESC_JACK_LEN (6 + 6 + 9 + 9)
+#define TUD_MIDI_DESC_JACK(_cablenum) \
+ /* MS In Jack (Embedded) */\
+ 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_IN_EMB(_cablenum), 0,\
+ /* MS In Jack (External) */\
+ 6, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_IN_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_IN_EXT(_cablenum), 0,\
+ /* MS Out Jack (Embedded), connected to In Jack External */\
+ 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EMBEDDED, TUD_MIDI_JACKID_OUT_EMB(_cablenum), 1, TUD_MIDI_JACKID_IN_EXT(_cablenum), 1, 0,\
+ /* MS Out Jack (External), connected to In Jack Embedded */\
+ 9, TUSB_DESC_CS_INTERFACE, MIDI_CS_INTERFACE_OUT_JACK, MIDI_JACK_EXTERNAL, TUD_MIDI_JACKID_OUT_EXT(_cablenum), 1, TUD_MIDI_JACKID_IN_EMB(_cablenum), 1, 0
+
+#define TUD_MIDI_DESC_EP_LEN(_numcables) (9 + 4 + (_numcables))
+#define TUD_MIDI_DESC_EP(_epout, _epsize, _numcables) \
+ /* Endpoint: Note Audio v1.0's endpoint has 9 bytes instead of 7 */\
+ 9, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0, 0, 0, \
+ /* MS Endpoint (connected to embedded jack) */\
+ (uint8_t)(4 + (_numcables)), TUSB_DESC_CS_ENDPOINT, MIDI_CS_ENDPOINT_GENERAL, _numcables
+
+// Length of template descriptor (88 bytes)
+#define TUD_MIDI_DESC_LEN (TUD_MIDI_DESC_HEAD_LEN + TUD_MIDI_DESC_JACK_LEN + TUD_MIDI_DESC_EP_LEN(1) * 2)
+
+// MIDI simple descriptor
+// - 1 Embedded Jack In connected to 1 External Jack Out
+// - 1 Embedded Jack out connected to 1 External Jack In
+#define TUD_MIDI_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \
+ TUD_MIDI_DESC_HEAD(_itfnum, _stridx, 1),\
+ TUD_MIDI_DESC_JACK(1),\
+ TUD_MIDI_DESC_EP(_epout, _epsize, 1),\
+ TUD_MIDI_JACKID_IN_EMB(1),\
+ TUD_MIDI_DESC_EP(_epin, _epsize, 1),\
+ TUD_MIDI_JACKID_OUT_EMB(1)
+
+//--------------------------------------------------------------------+
+// Audio v2.0 Descriptor Templates
+//--------------------------------------------------------------------+
+
+/* Standard Interface Association Descriptor (IAD) */
+#define TUD_AUDIO_DESC_IAD_LEN 8
+#define TUD_AUDIO_DESC_IAD(_firstitfs, _nitfs, _stridx) \
+ TUD_AUDIO_DESC_IAD_LEN, TUSB_DESC_INTERFACE_ASSOCIATION, _firstitfs, _nitfs, TUSB_CLASS_AUDIO, AUDIO_FUNCTION_SUBCLASS_UNDEFINED, AUDIO_FUNC_PROTOCOL_CODE_V2, _stridx
+
+/* Standard AC Interface Descriptor(4.7.1) */
+#define TUD_AUDIO_DESC_STD_AC_LEN 9
+#define TUD_AUDIO_DESC_STD_AC(_itfnum, _nEPs, _stridx) /* _nEPs is 0 or 1 */\
+ TUD_AUDIO_DESC_STD_AC_LEN, TUSB_DESC_INTERFACE, _itfnum, /* fixed to zero */ 0x00, _nEPs, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_CONTROL, AUDIO_INT_PROTOCOL_CODE_V2, _stridx
+
+/* Class-Specific AC Interface Header Descriptor(4.7.2) */
+#define TUD_AUDIO_DESC_CS_AC_LEN 9
+#define TUD_AUDIO_DESC_CS_AC(_bcdADC, _category, _totallen, _ctrl) /* _bcdADC : Audio Device Class Specification Release Number in Binary-Coded Decimal, _category : see audio_function_t, _totallen : Total number of bytes returned for the class-specific AudioControl interface i.e. Clock Source, Unit and Terminal descriptors - Do not include TUD_AUDIO_DESC_CS_AC_LEN, we already do this here*/ \
+ TUD_AUDIO_DESC_CS_AC_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_HEADER, U16_TO_U8S_LE(_bcdADC), _category, U16_TO_U8S_LE(_totallen + TUD_AUDIO_DESC_CS_AC_LEN), _ctrl
+
+/* Clock Source Descriptor(4.7.2.1) */
+#define TUD_AUDIO_DESC_CLK_SRC_LEN 8
+#define TUD_AUDIO_DESC_CLK_SRC(_clkid, _attr, _ctrl, _assocTerm, _stridx) \
+ TUD_AUDIO_DESC_CLK_SRC_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_CLOCK_SOURCE, _clkid, _attr, _ctrl, _assocTerm, _stridx
+
+/* Input Terminal Descriptor(4.7.2.4) */
+#define TUD_AUDIO_DESC_INPUT_TERM_LEN 17
+#define TUD_AUDIO_DESC_INPUT_TERM(_termid, _termtype, _assocTerm, _clkid, _nchannelslogical, _channelcfg, _idxchannelnames, _ctrl, _stridx) \
+ TUD_AUDIO_DESC_INPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_INPUT_TERMINAL, _termid, U16_TO_U8S_LE(_termtype), _assocTerm, _clkid, _nchannelslogical, U32_TO_U8S_LE(_channelcfg), _idxchannelnames, U16_TO_U8S_LE(_ctrl), _stridx
+
+/* Output Terminal Descriptor(4.7.2.5) */
+#define TUD_AUDIO_DESC_OUTPUT_TERM_LEN 12
+#define TUD_AUDIO_DESC_OUTPUT_TERM(_termid, _termtype, _assocTerm, _srcid, _clkid, _ctrl, _stridx) \
+ TUD_AUDIO_DESC_OUTPUT_TERM_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_OUTPUT_TERMINAL, _termid, U16_TO_U8S_LE(_termtype), _assocTerm, _srcid, _clkid, U16_TO_U8S_LE(_ctrl), _stridx
+
+/* Feature Unit Descriptor(4.7.2.8) */
+// 1 - Channel
+#define TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN 6+(1+1)*4
+#define TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(_unitid, _srcid, _ctrlch0master, _ctrlch1, _stridx) \
+ TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), _stridx
+
+// 2 - Channels
+#define TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN (6+(2+1)*4)
+#define TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL(_unitid, _srcid, _ctrlch0master, _ctrlch1, _ctrlch2, _stridx) \
+ TUD_AUDIO_DESC_FEATURE_UNIT_TWO_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), U32_TO_U8S_LE(_ctrlch2), _stridx
+// 4 - Channels
+#define TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN (6+(4+1)*4)
+#define TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL(_unitid, _srcid, _ctrlch0master, _ctrlch1, _ctrlch2, _ctrlch3, _ctrlch4, _stridx) \
+ TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AC_INTERFACE_FEATURE_UNIT, _unitid, _srcid, U32_TO_U8S_LE(_ctrlch0master), U32_TO_U8S_LE(_ctrlch1), U32_TO_U8S_LE(_ctrlch2), U32_TO_U8S_LE(_ctrlch3), U32_TO_U8S_LE(_ctrlch4), _stridx
+
+// For more channels, add definitions here
+
+/* Standard AS Interface Descriptor(4.9.1) */
+#define TUD_AUDIO_DESC_STD_AS_INT_LEN 9
+#define TUD_AUDIO_DESC_STD_AS_INT(_itfnum, _altset, _nEPs, _stridx) \
+ TUD_AUDIO_DESC_STD_AS_INT_LEN, TUSB_DESC_INTERFACE, _itfnum, _altset, _nEPs, TUSB_CLASS_AUDIO, AUDIO_SUBCLASS_STREAMING, AUDIO_INT_PROTOCOL_CODE_V2, _stridx
+
+/* Class-Specific AS Interface Descriptor(4.9.2) */
+#define TUD_AUDIO_DESC_CS_AS_INT_LEN 16
+#define TUD_AUDIO_DESC_CS_AS_INT(_termid, _ctrl, _formattype, _formats, _nchannelsphysical, _channelcfg, _stridx) \
+ TUD_AUDIO_DESC_CS_AS_INT_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AS_INTERFACE_AS_GENERAL, _termid, _ctrl, _formattype, U32_TO_U8S_LE(_formats), _nchannelsphysical, U32_TO_U8S_LE(_channelcfg), _stridx
+
+/* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */
+#define TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN 6
+#define TUD_AUDIO_DESC_TYPE_I_FORMAT(_subslotsize, _bitresolution) /* _subslotsize is number of bytes per sample (i.e. subslot) and can be 1,2,3, or 4 */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN, TUSB_DESC_CS_INTERFACE, AUDIO_CS_AS_INTERFACE_FORMAT_TYPE, AUDIO_FORMAT_TYPE_I, _subslotsize, _bitresolution
+
+/* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */
+#define TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN 7
+#define TUD_AUDIO_DESC_STD_AS_ISO_EP(_ep, _attr, _maxEPsize, _interval) \
+ TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN, TUSB_DESC_ENDPOINT, _ep, _attr, U16_TO_U8S_LE(_maxEPsize), _interval
+
+/* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */
+#define TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN 8
+#define TUD_AUDIO_DESC_CS_AS_ISO_EP(_attr, _ctrl, _lockdelayunit, _lockdelay) \
+ TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN, TUSB_DESC_CS_ENDPOINT, AUDIO_CS_EP_SUBTYPE_GENERAL, _attr, _ctrl, _lockdelayunit, U16_TO_U8S_LE(_lockdelay)
+
+/* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */
+#define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN 7
+#define TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(_ep, _interval) \
+ TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN, TUSB_DESC_ENDPOINT, _ep, (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_NO_SYNC | TUSB_ISO_EP_ATT_EXPLICIT_FB), U16_TO_U8S_LE(4), _interval
+
+// AUDIO simple descriptor (UAC2) for 1 microphone input
+// - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source
+
+#define TUD_AUDIO_MIC_ONE_CH_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+ + TUD_AUDIO_DESC_STD_AC_LEN\
+ + TUD_AUDIO_DESC_CS_AC_LEN\
+ + TUD_AUDIO_DESC_CLK_SRC_LEN\
+ + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+#define TUD_AUDIO_MIC_ONE_CH_DESC_N_AS_INT 1 // Number of AS interfaces
+
+#define TUD_AUDIO_MIC_ONE_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \
+ /* Standard Interface Association Descriptor (IAD) */\
+ TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+ /* Standard AC Interface Descriptor(4.7.1) */\
+ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+ TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+ /* Clock Source Descriptor(4.7.2.1) */\
+ TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\
+ /* Input Terminal Descriptor(4.7.2.4) */\
+ TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x03, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00),\
+ /* Output Terminal Descriptor(4.7.2.5) */\
+ TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+ /* Feature Unit Descriptor(4.7.2.8) */\
+ TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x03, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+// AUDIO simple descriptor (UAC2) for 4 microphone input
+// - 1 Input Terminal, 1 Feature Unit (Mute and Volume Control), 1 Output Terminal, 1 Clock Source
+
+#define TUD_AUDIO_MIC_FOUR_CH_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+ + TUD_AUDIO_DESC_STD_AC_LEN\
+ + TUD_AUDIO_DESC_CS_AC_LEN\
+ + TUD_AUDIO_DESC_CLK_SRC_LEN\
+ + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN)
+
+#define TUD_AUDIO_MIC_FOUR_CH_DESC_N_AS_INT 1 // Number of AS interfaces
+
+#define TUD_AUDIO_MIC_FOUR_CH_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epin, _epsize) \
+ /* Standard Interface Association Descriptor (IAD) */\
+ TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+ /* Standard AC Interface Descriptor(4.7.1) */\
+ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+ TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_MICROPHONE, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+ /* Clock Source Descriptor(4.7.2.1) */\
+ TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\
+ /* Input Terminal Descriptor(4.7.2.4) */\
+ TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_IN_GENERIC_MIC, /*_assocTerm*/ 0x03, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x04, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS, /*_stridx*/ 0x00),\
+ /* Output Terminal Descriptor(4.7.2.5) */\
+ TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+ /* Feature Unit Descriptor(4.7.2.8) */\
+ TUD_AUDIO_DESC_FEATURE_UNIT_FOUR_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch1*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch2*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch3*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_ctrlch4*/ AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum)+1), /*_altset*/ 0x01, /*_nEPs*/ 0x01, /*_stridx*/ 0x00),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x03, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x04, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epin, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000)
+
+// AUDIO simple descriptor (UAC2) for mono speaker
+// - 1 Input Terminal, 2 Feature Unit (Mute and Volume Control), 3 Output Terminal, 4 Clock Source
+
+#define TUD_AUDIO_SPEAKER_MONO_FB_DESC_LEN (TUD_AUDIO_DESC_IAD_LEN\
+ + TUD_AUDIO_DESC_STD_AC_LEN\
+ + TUD_AUDIO_DESC_CS_AC_LEN\
+ + TUD_AUDIO_DESC_CLK_SRC_LEN\
+ + TUD_AUDIO_DESC_INPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_OUTPUT_TERM_LEN\
+ + TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_INT_LEN\
+ + TUD_AUDIO_DESC_CS_AS_INT_LEN\
+ + TUD_AUDIO_DESC_TYPE_I_FORMAT_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_CS_AS_ISO_EP_LEN\
+ + TUD_AUDIO_DESC_STD_AS_ISO_FB_EP_LEN)
+
+#define TUD_AUDIO_SPEAKER_MONO_FB_DESCRIPTOR(_itfnum, _stridx, _nBytesPerSample, _nBitsUsedPerSample, _epout, _epsize, _epfb) \
+ /* Standard Interface Association Descriptor (IAD) */\
+ TUD_AUDIO_DESC_IAD(/*_firstitfs*/ _itfnum, /*_nitfs*/ 0x02, /*_stridx*/ 0x00),\
+ /* Standard AC Interface Descriptor(4.7.1) */\
+ TUD_AUDIO_DESC_STD_AC(/*_itfnum*/ _itfnum, /*_nEPs*/ 0x00, /*_stridx*/ _stridx),\
+ /* Class-Specific AC Interface Header Descriptor(4.7.2) */\
+ TUD_AUDIO_DESC_CS_AC(/*_bcdADC*/ 0x0200, /*_category*/ AUDIO_FUNC_DESKTOP_SPEAKER, /*_totallen*/ TUD_AUDIO_DESC_CLK_SRC_LEN+TUD_AUDIO_DESC_INPUT_TERM_LEN+TUD_AUDIO_DESC_OUTPUT_TERM_LEN+TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL_LEN, /*_ctrl*/ AUDIO_CS_AS_INTERFACE_CTRL_LATENCY_POS),\
+ /* Clock Source Descriptor(4.7.2.1) */\
+ TUD_AUDIO_DESC_CLK_SRC(/*_clkid*/ 0x04, /*_attr*/ AUDIO_CLOCK_SOURCE_ATT_INT_FIX_CLK, /*_ctrl*/ (AUDIO_CTRL_R << AUDIO_CLOCK_SOURCE_CTRL_CLK_FRQ_POS), /*_assocTerm*/ 0x01, /*_stridx*/ 0x00),\
+ /* Input Terminal Descriptor(4.7.2.4) */\
+ TUD_AUDIO_DESC_INPUT_TERM(/*_termid*/ 0x01, /*_termtype*/ AUDIO_TERM_TYPE_USB_STREAMING, /*_assocTerm*/ 0x00, /*_clkid*/ 0x04, /*_nchannelslogical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_idxchannelnames*/ 0x00, /*_ctrl*/ 0 * (AUDIO_CTRL_R << AUDIO_IN_TERM_CTRL_CONNECTOR_POS), /*_stridx*/ 0x00),\
+ /* Output Terminal Descriptor(4.7.2.5) */\
+ TUD_AUDIO_DESC_OUTPUT_TERM(/*_termid*/ 0x03, /*_termtype*/ AUDIO_TERM_TYPE_OUT_DESKTOP_SPEAKER, /*_assocTerm*/ 0x01, /*_srcid*/ 0x02, /*_clkid*/ 0x04, /*_ctrl*/ 0x0000, /*_stridx*/ 0x00),\
+ /* Feature Unit Descriptor(4.7.2.8) */\
+ TUD_AUDIO_DESC_FEATURE_UNIT_ONE_CHANNEL(/*_unitid*/ 0x02, /*_srcid*/ 0x01, /*_ctrlch0master*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_ctrlch1*/ 0 * (AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_MUTE_POS | AUDIO_CTRL_RW << AUDIO_FEATURE_UNIT_CTRL_VOLUME_POS), /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 0 - default alternate setting with 0 bandwidth */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x00, /*_nEPs*/ 0x00, /*_stridx*/ 0x00),\
+ /* Standard AS Interface Descriptor(4.9.1) */\
+ /* Interface 1, Alternate 1 - alternate interface for data streaming */\
+ TUD_AUDIO_DESC_STD_AS_INT(/*_itfnum*/ (uint8_t)((_itfnum) + 1), /*_altset*/ 0x01, /*_nEPs*/ 0x02, /*_stridx*/ 0x00),\
+ /* Class-Specific AS Interface Descriptor(4.9.2) */\
+ TUD_AUDIO_DESC_CS_AS_INT(/*_termid*/ 0x01, /*_ctrl*/ AUDIO_CTRL_NONE, /*_formattype*/ AUDIO_FORMAT_TYPE_I, /*_formats*/ AUDIO_DATA_FORMAT_TYPE_I_PCM, /*_nchannelsphysical*/ 0x01, /*_channelcfg*/ AUDIO_CHANNEL_CONFIG_NON_PREDEFINED, /*_stridx*/ 0x00),\
+ /* Type I Format Type Descriptor(2.3.1.6 - Audio Formats) */\
+ TUD_AUDIO_DESC_TYPE_I_FORMAT(_nBytesPerSample, _nBitsUsedPerSample),\
+ /* Standard AS Isochronous Audio Data Endpoint Descriptor(4.10.1.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_EP(/*_ep*/ _epout, /*_attr*/ (TUSB_XFER_ISOCHRONOUS | TUSB_ISO_EP_ATT_ASYNCHRONOUS | TUSB_ISO_EP_ATT_DATA), /*_maxEPsize*/ _epsize, /*_interval*/ (CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 0x04 : 0x01),\
+ /* Class-Specific AS Isochronous Audio Data Endpoint Descriptor(4.10.1.2) */\
+ TUD_AUDIO_DESC_CS_AS_ISO_EP(/*_attr*/ AUDIO_CS_AS_ISO_DATA_EP_ATT_NON_MAX_PACKETS_OK, /*_ctrl*/ AUDIO_CTRL_NONE, /*_lockdelayunit*/ AUDIO_CS_AS_ISO_DATA_EP_LOCK_DELAY_UNIT_UNDEFINED, /*_lockdelay*/ 0x0000),\
+ /* Standard AS Isochronous Feedback Endpoint Descriptor(4.10.2.1) */\
+ TUD_AUDIO_DESC_STD_AS_ISO_FB_EP(/*_ep*/ _epfb, /*_interval*/ 1)\
+
+// Calculate wMaxPacketSize of Endpoints
+#define TUD_AUDIO_EP_SIZE(_maxFrequency, _nBytesPerSample, _nChannels) \
+ ((((_maxFrequency + ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 7999 : 999)) / ((CFG_TUSB_RHPORT0_MODE & OPT_MODE_HIGH_SPEED) ? 8000 : 1000)) + 1) * _nBytesPerSample * _nChannels)
+
+
+//--------------------------------------------------------------------+
+// USBTMC/USB488 Descriptor Templates
+//--------------------------------------------------------------------+
+
+#define TUD_USBTMC_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC)
+#define TUD_USBTMC_APP_SUBCLASS 0x03u
+
+#define TUD_USBTMC_PROTOCOL_STD 0x00u
+#define TUD_USBTMC_PROTOCOL_USB488 0x01u
+
+// Interface number, number of endpoints, EP string index, USB_TMC_PROTOCOL*, bulk-out endpoint ID,
+// bulk-in endpoint ID
+#define TUD_USBTMC_IF_DESCRIPTOR(_itfnum, _bNumEndpoints, _stridx, _itfProtocol) \
+ /* Interface */ \
+ 0x09, TUSB_DESC_INTERFACE, _itfnum, 0x00, _bNumEndpoints, TUD_USBTMC_APP_CLASS, TUD_USBTMC_APP_SUBCLASS, _itfProtocol, _stridx
+
+#define TUD_USBTMC_IF_DESCRIPTOR_LEN 9u
+
+#define TUD_USBTMC_BULK_DESCRIPTORS(_epout, _epin, _bulk_epsize) \
+ /* Endpoint Out */ \
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_bulk_epsize), 0u, \
+ /* Endpoint In */ \
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_bulk_epsize), 0u
+
+#define TUD_USBTMC_BULK_DESCRIPTORS_LEN (7u+7u)
+
+/* optional interrupt endpoint */ \
+// _int_pollingInterval : for LS/FS, expressed in frames (1ms each). 16 may be a good number?
+#define TUD_USBTMC_INT_DESCRIPTOR(_ep_interrupt, _ep_interrupt_size, _int_pollingInterval ) \
+ 7, TUSB_DESC_ENDPOINT, _ep_interrupt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_interrupt_size), 0x16
+
+#define TUD_USBTMC_INT_DESCRIPTOR_LEN (7u)
+
+//--------------------------------------------------------------------+
+// Vendor Descriptor Templates
+//--------------------------------------------------------------------+
+
+#define TUD_VENDOR_DESC_LEN (9+7+7)
+
+// Interface number, string index, EP Out & IN address, EP size
+#define TUD_VENDOR_DESCRIPTOR(_itfnum, _stridx, _epout, _epin, _epsize) \
+ /* Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 2, TUSB_CLASS_VENDOR_SPECIFIC, 0x00, 0x00, _stridx,\
+ /* Endpoint Out */\
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
+//--------------------------------------------------------------------+
+// DFU Runtime Descriptor Templates
+//--------------------------------------------------------------------+
+
+#define TUD_DFU_APP_CLASS (TUSB_CLASS_APPLICATION_SPECIFIC)
+#define TUD_DFU_APP_SUBCLASS (APP_SUBCLASS_DFU_RUNTIME)
+
+// Length of template descriptr: 18 bytes
+#define TUD_DFU_RT_DESC_LEN (9 + 9)
+
+// DFU runtime descriptor
+// Interface number, string index, attributes, detach timeout, transfer size
+#define TUD_DFU_RT_DESCRIPTOR(_itfnum, _stridx, _attr, _timeout, _xfer_size) \
+ /* Interface */ \
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_RT, _stridx, \
+ /* Function */ \
+ 9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
+
+//--------------------------------------------------------------------+
+// DFU Descriptor Templates
+//--------------------------------------------------------------------+
+
+// Length of template descriptor: 9 bytes + number of alternatives * 9
+#define TUD_DFU_DESC_LEN(_alt_count) (9 + (_alt_count) * 9)
+
+// Interface number, Alternate count, starting string index, attributes, detach timeout, transfer size
+// Note: Alternate count must be numberic or macro, string index is increased by one for each Alt interface
+#define TUD_DFU_DESCRIPTOR(_itfnum, _alt_count, _stridx, _attr, _timeout, _xfer_size) \
+ TU_XSTRCAT(_TUD_DFU_ALT_,_alt_count)(_itfnum, 0, _stridx), \
+ /* Function */ \
+ 9, DFU_DESC_FUNCTIONAL, _attr, U16_TO_U8S_LE(_timeout), U16_TO_U8S_LE(_xfer_size), U16_TO_U8S_LE(0x0101)
+
+#define _TUD_DFU_ALT(_itfnum, _alt, _stridx) \
+ /* Interface */ \
+ 9, TUSB_DESC_INTERFACE, _itfnum, _alt, 0, TUD_DFU_APP_CLASS, TUD_DFU_APP_SUBCLASS, DFU_PROTOCOL_DFU, _stridx
+
+#define _TUD_DFU_ALT_1(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx)
+
+#define _TUD_DFU_ALT_2(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \
+ _TUD_DFU_ALT_1(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_3(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \
+ _TUD_DFU_ALT_2(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_4(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \
+ _TUD_DFU_ALT_3(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_5(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \
+ _TUD_DFU_ALT_4(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_6(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \
+ _TUD_DFU_ALT_5(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_7(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \
+ _TUD_DFU_ALT_6(_itfnum, _alt_count+1, _stridx+1)
+
+#define _TUD_DFU_ALT_8(_itfnum, _alt_count, _stridx) \
+ _TUD_DFU_ALT(_itfnum, _alt_count, _stridx), \
+ _TUD_DFU_ALT_7(_itfnum, _alt_count+1, _stridx+1)
+
+//--------------------------------------------------------------------+
+// CDC-ECM Descriptor Templates
+//--------------------------------------------------------------------+
+
+// Length of template descriptor: 71 bytes
+#define TUD_CDC_ECM_DESC_LEN (8+9+5+5+13+7+9+9+7+7)
+
+// CDC-ECM Descriptor Template
+// Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
+#define TUD_CDC_ECM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \
+ /* Interface Association */\
+ 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL, 0, 0,\
+ /* CDC Control Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_ETHERNET_CONTROL_MODEL, 0, _desc_stridx,\
+ /* CDC-ECM Header */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0120),\
+ /* CDC-ECM Union */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
+ /* CDC-ECM Functional Descriptor */\
+ 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0,\
+ /* Endpoint Notification */\
+ 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\
+ /* CDC Data Interface (default inactive) */\
+ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, 0, 0,\
+ /* CDC Data Interface (alternative active) */\
+ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0,\
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+ /* Endpoint Out */\
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
+//--------------------------------------------------------------------+
+// RNDIS Descriptor Templates
+//--------------------------------------------------------------------+
+
+#if 0
+/* Windows XP */
+#define TUD_RNDIS_ITF_CLASS TUSB_CLASS_CDC
+#define TUD_RNDIS_ITF_SUBCLASS CDC_COMM_SUBCLASS_ABSTRACT_CONTROL_MODEL
+#define TUD_RNDIS_ITF_PROTOCOL 0xFF /* CDC_COMM_PROTOCOL_MICROSOFT_RNDIS */
+#else
+/* Windows 7+ */
+#define TUD_RNDIS_ITF_CLASS TUSB_CLASS_WIRELESS_CONTROLLER
+#define TUD_RNDIS_ITF_SUBCLASS 0x01
+#define TUD_RNDIS_ITF_PROTOCOL 0x03
+#endif
+
+// Length of template descriptor: 66 bytes
+#define TUD_RNDIS_DESC_LEN (8+9+5+5+4+5+7+9+7+7)
+
+// RNDIS Descriptor Template
+// Interface number, string index, EP notification address and size, EP data address (out, in) and size.
+#define TUD_RNDIS_DESCRIPTOR(_itfnum, _stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize) \
+ /* Interface Association */\
+ 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUD_RNDIS_ITF_CLASS, TUD_RNDIS_ITF_SUBCLASS, TUD_RNDIS_ITF_PROTOCOL, 0,\
+ /* CDC Control Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUD_RNDIS_ITF_CLASS, TUD_RNDIS_ITF_SUBCLASS, TUD_RNDIS_ITF_PROTOCOL, _stridx,\
+ /* CDC-ACM Header */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\
+ /* CDC Call Management */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_CALL_MANAGEMENT, 0, (uint8_t)((_itfnum) + 1),\
+ /* ACM */\
+ 4, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, 0,\
+ /* CDC Union */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
+ /* Endpoint Notification */\
+ 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 1,\
+ /* CDC Data Interface */\
+ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 2, TUSB_CLASS_CDC_DATA, 0, 0, 0,\
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+ /* Endpoint Out */\
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
+//--------------------------------------------------------------------+
+// Bluetooth Radio Descriptor Templates
+//--------------------------------------------------------------------+
+
+#define TUD_BT_APP_CLASS (TUSB_CLASS_WIRELESS_CONTROLLER)
+#define TUD_BT_APP_SUBCLASS 0x01
+#define TUD_BT_PROTOCOL_PRIMARY_CONTROLLER 0x01
+#define TUD_BT_PROTOCOL_AMP_CONTROLLER 0x02
+
+#ifndef CFG_TUD_BTH_ISO_ALT_COUNT
+#define CFG_TUD_BTH_ISO_ALT_COUNT 0
+#endif
+
+// Length of template descriptor: 30 bytes + number of ISO alternatives * 23
+#define TUD_BTH_DESC_LEN (9 + 7 + 7 + 7 + (CFG_TUD_BTH_ISO_ALT_COUNT) * (9 + 7 + 7))
+
+/* Primary Interface */
+#define TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 3, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, _stridx, \
+ /* Endpoint In for events */ \
+ 7, TUSB_DESC_ENDPOINT, _ep_evt, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_evt_size), _ep_evt_interval, \
+ /* Endpoint In for ACL data */ \
+ 7, TUSB_DESC_ENDPOINT, _ep_in, TUSB_XFER_BULK, U16_TO_U8S_LE(_ep_size), 1, \
+ /* Endpoint Out for ACL data */ \
+ 7, TUSB_DESC_ENDPOINT, _ep_out, TUSB_XFER_BULK, U16_TO_U8S_LE(_ep_size), 1
+
+#define TUD_BTH_ISO_ITF(_itfnum, _alt, _ep_in, _ep_out, _n) ,\
+ /* Interface with 2 endpoints */ \
+ 9, TUSB_DESC_INTERFACE, _itfnum, _alt, 2, TUD_BT_APP_CLASS, TUD_BT_APP_SUBCLASS, TUD_BT_PROTOCOL_PRIMARY_CONTROLLER, 0, \
+ /* Isochronous endpoints */ \
+ 7, TUSB_DESC_ENDPOINT, _ep_in, TUSB_XFER_ISOCHRONOUS, U16_TO_U8S_LE(_n), 1, \
+ 7, TUSB_DESC_ENDPOINT, _ep_out, TUSB_XFER_ISOCHRONOUS, U16_TO_U8S_LE(_n), 1
+
+#define _FIRST(a, ...) a
+#define _REST(a, ...) __VA_ARGS__
+
+#define TUD_BTH_ISO_ITF_0(_itfnum, ...)
+#define TUD_BTH_ISO_ITF_1(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 1, _ep_in, _ep_out, _FIRST(__VA_ARGS__))
+#define TUD_BTH_ISO_ITF_2(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 2, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \
+ TUD_BTH_ISO_ITF_1(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__))
+#define TUD_BTH_ISO_ITF_3(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 3, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \
+ TUD_BTH_ISO_ITF_2(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__))
+#define TUD_BTH_ISO_ITF_4(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 4, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \
+ TUD_BTH_ISO_ITF_3(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__))
+#define TUD_BTH_ISO_ITF_5(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 5, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \
+ TUD_BTH_ISO_ITF_4(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__))
+#define TUD_BTH_ISO_ITF_6(_itfnum, _ep_in, _ep_out, ...) TUD_BTH_ISO_ITF(_itfnum, (CFG_TUD_BTH_ISO_ALT_COUNT) - 6, _ep_in, _ep_out, _FIRST(__VA_ARGS__)) \
+ TUD_BTH_ISO_ITF_5(_itfnum, _ep_in, _ep_out, _REST(__VA_ARGS__))
+
+#define TUD_BTH_ISO_ITFS(_itfnum, _ep_in, _ep_out, ...) \
+ TU_XSTRCAT(TUD_BTH_ISO_ITF_, CFG_TUD_BTH_ISO_ALT_COUNT)(_itfnum, _ep_in, _ep_out, __VA_ARGS__)
+
+// BT Primary controller descriptor
+// Interface number, string index, attributes, event endpoint, event endpoint size, interval, data in, data out, data endpoint size, iso endpoint sizes
+// TODO BTH should also use IAD like CDC for composite device
+#define TUD_BTH_DESCRIPTOR(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size,...) \
+ TUD_BTH_PRI_ITF(_itfnum, _stridx, _ep_evt, _ep_evt_size, _ep_evt_interval, _ep_in, _ep_out, _ep_size) \
+ TUD_BTH_ISO_ITFS(_itfnum + 1, _ep_in + 1, _ep_out + 1, __VA_ARGS__)
+
+//--------------------------------------------------------------------+
+// CDC-NCM Descriptor Templates
+//--------------------------------------------------------------------+
+
+// Length of template descriptor
+#define TUD_CDC_NCM_DESC_LEN (8+9+5+5+13+6+7+9+9+7+7)
+
+// CDC-ECM Descriptor Template
+// Interface number, description string index, MAC address string index, EP notification address and size, EP data address (out, in), and size, max segment size.
+#define TUD_CDC_NCM_DESCRIPTOR(_itfnum, _desc_stridx, _mac_stridx, _ep_notif, _ep_notif_size, _epout, _epin, _epsize, _maxsegmentsize) \
+ /* Interface Association */\
+ 8, TUSB_DESC_INTERFACE_ASSOCIATION, _itfnum, 2, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, 0,\
+ /* CDC Control Interface */\
+ 9, TUSB_DESC_INTERFACE, _itfnum, 0, 1, TUSB_CLASS_CDC, CDC_COMM_SUBCLASS_NETWORK_CONTROL_MODEL, 0, _desc_stridx,\
+ /* CDC-NCM Header */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_HEADER, U16_TO_U8S_LE(0x0110),\
+ /* CDC-NCM Union */\
+ 5, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_UNION, _itfnum, (uint8_t)((_itfnum) + 1),\
+ /* CDC-NCM Functional Descriptor */\
+ 13, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_ETHERNET_NETWORKING, _mac_stridx, 0, 0, 0, 0, U16_TO_U8S_LE(_maxsegmentsize), U16_TO_U8S_LE(0), 0, \
+ /* CDC-NCM Functional Descriptor */\
+ 6, TUSB_DESC_CS_INTERFACE, CDC_FUNC_DESC_NCM, U16_TO_U8S_LE(0x0100), 0, \
+ /* Endpoint Notification */\
+ 7, TUSB_DESC_ENDPOINT, _ep_notif, TUSB_XFER_INTERRUPT, U16_TO_U8S_LE(_ep_notif_size), 50,\
+ /* CDC Data Interface (default inactive) */\
+ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 0, 0, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\
+ /* CDC Data Interface (alternative active) */\
+ 9, TUSB_DESC_INTERFACE, (uint8_t)((_itfnum)+1), 1, 2, TUSB_CLASS_CDC_DATA, 0, NCM_DATA_PROTOCOL_NETWORK_TRANSFER_BLOCK, 0,\
+ /* Endpoint In */\
+ 7, TUSB_DESC_ENDPOINT, _epin, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0,\
+ /* Endpoint Out */\
+ 7, TUSB_DESC_ENDPOINT, _epout, TUSB_XFER_BULK, U16_TO_U8S_LE(_epsize), 0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_USBD_H_ */
+
+/** @} */
diff --git a/arkanoid/pico/tinyusb/usbd_control.c b/arkanoid/pico/tinyusb/usbd_control.c
new file mode 100644
index 0000000..e9e775a
--- /dev/null
+++ b/arkanoid/pico/tinyusb/usbd_control.c
@@ -0,0 +1,233 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+
+#include "tusb_option.h"
+
+#if TUSB_OPT_DEVICE_ENABLED
+
+#include "tusb.h"
+#include "usbd_pvt.h"
+#include "dcd.h" // TODO was dcd.h
+
+#if CFG_TUSB_DEBUG >= 2
+extern void usbd_driver_print_control_complete_name(usbd_control_xfer_cb_t callback);
+#endif
+
+enum
+{
+ EDPT_CTRL_OUT = 0x00,
+ EDPT_CTRL_IN = 0x80
+};
+
+typedef struct
+{
+ tusb_control_request_t request;
+
+ uint8_t* buffer;
+ uint16_t data_len;
+ uint16_t total_xferred;
+
+ usbd_control_xfer_cb_t complete_cb;
+} usbd_control_xfer_t;
+
+static usbd_control_xfer_t _ctrl_xfer;
+
+CFG_TUSB_MEM_SECTION CFG_TUSB_MEM_ALIGN
+static uint8_t _usbd_ctrl_buf[CFG_TUD_ENDPOINT0_SIZE];
+
+//--------------------------------------------------------------------+
+// Application API
+//--------------------------------------------------------------------+
+
+// Queue ZLP status transaction
+static inline bool _status_stage_xact(uint8_t rhport, tusb_control_request_t const * request)
+{
+ // Opposite to endpoint in Data Phase
+ uint8_t const ep_addr = request->bmRequestType_bit.direction ? EDPT_CTRL_OUT : EDPT_CTRL_IN;
+ return usbd_edpt_xfer(rhport, ep_addr, NULL, 0);
+}
+
+// Status phase
+bool tud_control_status(uint8_t rhport, tusb_control_request_t const * request)
+{
+ _ctrl_xfer.request = (*request);
+ _ctrl_xfer.buffer = NULL;
+ _ctrl_xfer.total_xferred = 0;
+ _ctrl_xfer.data_len = 0;
+
+ return _status_stage_xact(rhport, request);
+}
+
+// Queue a transaction in Data Stage
+// Each transaction has up to Endpoint0's max packet size.
+// This function can also transfer an zero-length packet
+static bool _data_stage_xact(uint8_t rhport)
+{
+ uint16_t const xact_len = tu_min16(_ctrl_xfer.data_len - _ctrl_xfer.total_xferred, CFG_TUD_ENDPOINT0_SIZE);
+
+ uint8_t ep_addr = EDPT_CTRL_OUT;
+
+ if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_IN )
+ {
+ ep_addr = EDPT_CTRL_IN;
+ if ( xact_len ) memcpy(_usbd_ctrl_buf, _ctrl_xfer.buffer, xact_len);
+ }
+
+ return usbd_edpt_xfer(rhport, ep_addr, xact_len ? _usbd_ctrl_buf : NULL, xact_len);
+}
+
+// Transmit data to/from the control endpoint.
+// If the request's wLength is zero, a status packet is sent instead.
+bool tud_control_xfer(uint8_t rhport, tusb_control_request_t const * request, void* buffer, uint16_t len)
+{
+ _ctrl_xfer.request = (*request);
+ _ctrl_xfer.buffer = (uint8_t*) buffer;
+ _ctrl_xfer.total_xferred = 0U;
+ _ctrl_xfer.data_len = tu_min16(len, request->wLength);
+
+ if (request->wLength > 0U)
+ {
+ if(_ctrl_xfer.data_len > 0U)
+ {
+ TU_ASSERT(buffer);
+ }
+
+// TU_LOG2(" Control total data length is %u bytes\r\n", _ctrl_xfer.data_len);
+
+ // Data stage
+ TU_ASSERT( _data_stage_xact(rhport) );
+ }
+ else
+ {
+ // Status stage
+ TU_ASSERT( _status_stage_xact(rhport, request) );
+ }
+
+ return true;
+}
+
+//--------------------------------------------------------------------+
+// USBD API
+//--------------------------------------------------------------------+
+
+void usbd_control_reset(void);
+void usbd_control_set_request(tusb_control_request_t const *request);
+void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp );
+bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t event, uint32_t xferred_bytes);
+
+void usbd_control_reset(void)
+{
+ tu_varclr(&_ctrl_xfer);
+}
+
+// Set complete callback
+void usbd_control_set_complete_callback( usbd_control_xfer_cb_t fp )
+{
+ _ctrl_xfer.complete_cb = fp;
+}
+
+// for dcd_set_address where DCD is responsible for status response
+void usbd_control_set_request(tusb_control_request_t const *request)
+{
+ _ctrl_xfer.request = (*request);
+ _ctrl_xfer.buffer = NULL;
+ _ctrl_xfer.total_xferred = 0;
+ _ctrl_xfer.data_len = 0;
+}
+
+// callback when a transaction complete on
+// - DATA stage of control endpoint or
+// - Status stage
+bool usbd_control_xfer_cb (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes)
+{
+ (void) result;
+
+ // Endpoint Address is opposite to direction bit, this is Status Stage complete event
+ if ( tu_edpt_dir(ep_addr) != _ctrl_xfer.request.bmRequestType_bit.direction )
+ {
+ TU_ASSERT(0 == xferred_bytes);
+
+ // invoke optional dcd hook if available
+ if (dcd_edpt0_status_complete) dcd_edpt0_status_complete(rhport, &_ctrl_xfer.request);
+
+ if (_ctrl_xfer.complete_cb)
+ {
+ // TODO refactor with usbd_driver_print_control_complete_name
+ _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_ACK, &_ctrl_xfer.request);
+ }
+
+ return true;
+ }
+
+ if ( _ctrl_xfer.request.bmRequestType_bit.direction == TUSB_DIR_OUT )
+ {
+ TU_VERIFY(_ctrl_xfer.buffer);
+ memcpy(_ctrl_xfer.buffer, _usbd_ctrl_buf, xferred_bytes);
+ TU_LOG_MEM(2, _usbd_ctrl_buf, xferred_bytes, 2);
+ }
+
+ _ctrl_xfer.total_xferred += xferred_bytes;
+ _ctrl_xfer.buffer += xferred_bytes;
+
+ // Data Stage is complete when all request's length are transferred or
+ // a short packet is sent including zero-length packet.
+ if ( (_ctrl_xfer.request.wLength == _ctrl_xfer.total_xferred) || (xferred_bytes < CFG_TUD_ENDPOINT0_SIZE) )
+ {
+ // DATA stage is complete
+ bool is_ok = true;
+
+ // invoke complete callback if set
+ // callback can still stall control in status phase e.g out data does not make sense
+ if ( _ctrl_xfer.complete_cb )
+ {
+ #if CFG_TUSB_DEBUG >= 2
+ usbd_driver_print_control_complete_name(_ctrl_xfer.complete_cb);
+ #endif
+
+ is_ok = _ctrl_xfer.complete_cb(rhport, CONTROL_STAGE_DATA, &_ctrl_xfer.request);
+ }
+
+ if ( is_ok )
+ {
+ // Send status
+ TU_ASSERT( _status_stage_xact(rhport, &_ctrl_xfer.request) );
+ }else
+ {
+ // Stall both IN and OUT control endpoint
+ dcd_edpt_stall(rhport, EDPT_CTRL_OUT);
+ dcd_edpt_stall(rhport, EDPT_CTRL_IN);
+ }
+ }
+ else
+ {
+ // More data to transfer
+ TU_ASSERT( _data_stage_xact(rhport) );
+ }
+
+ return true;
+}
+
+#endif
diff --git a/arkanoid/pico/tinyusb/usbd_pvt.h b/arkanoid/pico/tinyusb/usbd_pvt.h
new file mode 100644
index 0000000..723e4d5
--- /dev/null
+++ b/arkanoid/pico/tinyusb/usbd_pvt.h
@@ -0,0 +1,115 @@
+/*
+ * The MIT License (MIT)
+ *
+ * Copyright (c) 2019 Ha Thach (tinyusb.org)
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ * This file is part of the TinyUSB stack.
+ */
+#ifndef USBD_PVT_H_
+#define USBD_PVT_H_
+
+#include "osal.h"
+#include "tusb_fifo.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// Class Driver API
+//--------------------------------------------------------------------+
+
+typedef struct
+{
+ #if CFG_TUSB_DEBUG >= 2
+ char const* name;
+ #endif
+
+ void (* init ) (void);
+ void (* reset ) (uint8_t rhport);
+ uint16_t (* open ) (uint8_t rhport, tusb_desc_interface_t const * desc_intf, uint16_t max_len);
+ bool (* control_xfer_cb ) (uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+ bool (* xfer_cb ) (uint8_t rhport, uint8_t ep_addr, xfer_result_t result, uint32_t xferred_bytes);
+ void (* sof ) (uint8_t rhport); /* optional */
+} usbd_class_driver_t;
+
+// Invoked when initializing device stack to get additional class drivers.
+// Can optionally implemented by application to extend/overwrite class driver support.
+// Note: The drivers array must be accessible at all time when stack is active
+usbd_class_driver_t const* usbd_app_driver_get_cb(uint8_t* driver_count) TU_ATTR_WEAK;
+
+typedef bool (*usbd_control_xfer_cb_t)(uint8_t rhport, uint8_t stage, tusb_control_request_t const * request);
+
+//--------------------------------------------------------------------+
+// USBD Endpoint API
+//--------------------------------------------------------------------+
+
+// Open an endpoint
+bool usbd_edpt_open(uint8_t rhport, tusb_desc_endpoint_t const * desc_ep);
+
+// Close an endpoint
+void usbd_edpt_close(uint8_t rhport, uint8_t ep_addr);
+
+// Submit a usb transfer
+bool usbd_edpt_xfer(uint8_t rhport, uint8_t ep_addr, uint8_t * buffer, uint16_t total_bytes);
+
+// Submit a usb ISO transfer by use of a FIFO (ring buffer) - all bytes in FIFO get transmitted
+bool usbd_edpt_xfer_fifo(uint8_t rhport, uint8_t ep_addr, tu_fifo_t * ff, uint16_t total_bytes);
+
+// Claim an endpoint before submitting a transfer.
+// If caller does not make any transfer, it must release endpoint for others.
+bool usbd_edpt_claim(uint8_t rhport, uint8_t ep_addr);
+
+// Release an endpoint without submitting a transfer
+bool usbd_edpt_release(uint8_t rhport, uint8_t ep_addr);
+
+// Check if endpoint is busy transferring
+bool usbd_edpt_busy(uint8_t rhport, uint8_t ep_addr);
+
+// Stall endpoint
+void usbd_edpt_stall(uint8_t rhport, uint8_t ep_addr);
+
+// Clear stalled endpoint
+void usbd_edpt_clear_stall(uint8_t rhport, uint8_t ep_addr);
+
+// Check if endpoint is stalled
+bool usbd_edpt_stalled(uint8_t rhport, uint8_t ep_addr);
+
+// Check if endpoint is ready (not busy and not stalled)
+TU_ATTR_ALWAYS_INLINE static inline
+bool usbd_edpt_ready(uint8_t rhport, uint8_t ep_addr)
+{
+ return !usbd_edpt_busy(rhport, ep_addr) && !usbd_edpt_stalled(rhport, ep_addr);
+}
+
+/*------------------------------------------------------------------*/
+/* Helper
+ *------------------------------------------------------------------*/
+
+bool usbd_open_edpt_pair(uint8_t rhport, uint8_t const* p_desc, uint8_t ep_count, uint8_t xfer_type, uint8_t* ep_out, uint8_t* ep_in);
+void usbd_defer_func( osal_task_func_t func, void* param, bool in_isr );
+
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* USBD_PVT_H_ */
diff --git a/arkanoid/pico/unique_id.c b/arkanoid/pico/unique_id.c
new file mode 100644
index 0000000..366a7ee
--- /dev/null
+++ b/arkanoid/pico/unique_id.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "hardware/flash.h"
+#include "unique_id.h"
+
+static_assert(PICO_UNIQUE_BOARD_ID_SIZE_BYTES == FLASH_UNIQUE_ID_SIZE_BYTES, "Board ID size must match flash ID size");
+
+static pico_unique_board_id_t retrieved_id;
+
+static void __attribute__((constructor)) _retrieve_unique_id_on_boot(void) {
+#if PICO_NO_FLASH
+ // The hardware_flash call will panic() if called directly on a NO_FLASH
+ // build. Since this constructor is pre-main it would be annoying to
+ // debug, so just produce something well-defined and obviously wrong.
+ for (int i = 0; i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES; i++)
+ retrieved_id.id[i] = 0xee;
+#else
+ flash_get_unique_id(retrieved_id.id);
+#endif
+}
+
+void pico_get_unique_board_id(pico_unique_board_id_t *id_out) {
+ *id_out = retrieved_id;
+}
+
+void pico_get_unique_board_id_string(char *id_out, uint len) {
+ assert(len > 0);
+ size_t i;
+ // Generate hex one nibble at a time
+ for (i = 0; (i < len - 1) && (i < PICO_UNIQUE_BOARD_ID_SIZE_BYTES * 2); i++) {
+ int nibble = (retrieved_id.id[i/2] >> (4 - 4 * (i&1))) & 0xf;
+ id_out[i] = (char)(nibble < 10 ? nibble + '0' : nibble + 'A' - 10);
+ }
+ id_out[i] = 0;
+}
diff --git a/arkanoid/pico/unique_id.h b/arkanoid/pico/unique_id.h
new file mode 100644
index 0000000..7c9753d
--- /dev/null
+++ b/arkanoid/pico/unique_id.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_UNIQUE_ID_H_
+#define _PICO_UNIQUE_ID_H_
+
+#include "pico.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** \file unique_id.h
+ * \defgroup pico_unique_id pico_unique_id
+ *
+ * Unique device ID access API
+ *
+ * RP2040 does not have an on-board unique identifier (all instances of RP2040
+ * silicon are identical and have no persistent state). However, RP2040 boots
+ * from serial NOR flash devices which have a 64-bit unique ID as a standard
+ * feature, and there is a 1:1 association between RP2040 and flash, so this
+ * is suitable for use as a unique identifier for an RP2040-based board.
+ *
+ * This library injects a call to the flash_get_unique_id function from the
+ * hardware_flash library, to run before main, and stores the result in a
+ * static location which can safely be accessed at any time via
+ * pico_get_unique_id().
+ *
+ * This avoids some pitfalls of the hardware_flash API, which requires any
+ * flash-resident interrupt routines to be disabled when called into.
+ */
+
+#define PICO_UNIQUE_BOARD_ID_SIZE_BYTES 8
+
+/**
+ * \brief Unique board identifier
+ * \ingroup pico_unique_id
+ *
+ * This struct is suitable for holding the unique identifier of a NOR flash
+ * device on an RP2040-based board. It contains an array of
+ * PICO_UNIQUE_BOARD_ID_SIZE_BYTES identifier bytes.
+ */
+typedef struct {
+ uint8_t id[PICO_UNIQUE_BOARD_ID_SIZE_BYTES];
+} pico_unique_board_id_t;
+
+/*! \brief Get unique ID
+ * \ingroup pico_unique_id
+ *
+ * Get the unique 64-bit device identifier which was retrieved from the
+ * external NOR flash device at boot.
+ *
+ * On PICO_NO_FLASH builds the unique identifier is set to all 0xEE.
+ *
+ * \param id_out a pointer to a pico_unique_board_id_t struct, to which the identifier will be written
+ */
+void pico_get_unique_board_id(pico_unique_board_id_t *id_out);
+
+/*! \brief Get unique ID in string format
+ * \ingroup pico_unique_id
+ *
+ * Get the unique 64-bit device identifier which was retrieved from the
+ * external NOR flash device at boot, formatted as an ASCII hex string.
+ * Will always 0-terminate.
+ *
+ * On PICO_NO_FLASH builds the unique identifier is set to all 0xEE.
+ *
+ * \param id_out a pointer to a char buffer of size len, to which the identifier will be written
+ * \param len the size of id_out. For full serial, len >= 2 * PICO_UNIQUE_BOARD_ID_SIZE_BYTES + 1
+ */
+void pico_get_unique_board_id_string(char *id_out, uint len);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/arkanoid/pico/usb_reset_interface.h b/arkanoid/pico/usb_reset_interface.h
new file mode 100644
index 0000000..153acf8
--- /dev/null
+++ b/arkanoid/pico/usb_reset_interface.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _PICO_USB_RESET_INTERFACE_H
+#define _PICO_USB_RESET_INTERFACE_H
+
+/** \file usb_reset_interface.h
+ * \defgroup pico_usb_reset_interface pico_usb_reset_interface
+ *
+ * Definition for the reset interface that may be exposed by the pico_stdio_usb library
+ */
+
+// VENDOR sub-class for the reset interface
+#define RESET_INTERFACE_SUBCLASS 0x00
+// VENDOR protocol for the reset interface
+#define RESET_INTERFACE_PROTOCOL 0x01
+
+// CONTROL requests:
+
+// reset to BOOTSEL
+#define RESET_REQUEST_BOOTSEL 0x01
+// regular flash boot
+#define RESET_REQUEST_FLASH 0x02
+
+#endif
\ No newline at end of file
diff --git a/arkanoid/pico_mountpoint/main.uf2 b/arkanoid/pico_mountpoint/main.uf2
new file mode 100644
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literal 0
HcmV?d00001
diff --git a/arkanoid/utils.c b/arkanoid/utils.c
new file mode 100644
index 0000000..96bbde5
--- /dev/null
+++ b/arkanoid/utils.c
@@ -0,0 +1,23 @@
+#include "utils.h"
+
+uint16_t color32_to_16(uint32_t color) {
+ uint8_t r = (color >> 16) & 0xFF;
+ uint8_t g = (color >> 8) & 0xFF;
+ uint8_t b = color & 0xFF;
+
+ return color_to_rgb(r, g, b);
+}
+
+uint16_t color_to_rgb(uint8_t r, uint8_t g, uint8_t b) {
+ return ((r & 0b11111000) << 8)
+ | ((g & 0b11111100) << 3)
+ | (b >> 3);
+}
+
+uint16_t change_color(uint16_t color, float offset) {
+ uint8_t r = (color >> 8) & 0b11111000;
+ uint8_t g = (color >> 3) & 0b11111100;
+ uint8_t b = (color << 3) & 0b11111000;
+
+ return color_to_rgb(r * offset, g * offset, b * offset);
+}
\ No newline at end of file
diff --git a/arkanoid/utils.h b/arkanoid/utils.h
new file mode 100644
index 0000000..1c46703
--- /dev/null
+++ b/arkanoid/utils.h
@@ -0,0 +1,14 @@
+#ifndef UTILS_H
+#define UTILS_H
+
+#include <stdint.h>
+
+const static int16_t BALL_HIT_NOTHING = -1;
+const static int16_t BALL_HIT_PADDLE = -2;
+const static int16_t BALL_DIED = -3;
+
+uint16_t color32_to_16(uint32_t color);
+uint16_t color_to_rgb(uint8_t r, uint8_t g, uint8_t b);
+uint16_t change_color(uint16_t color, float offset);
+
+#endif
diff --git a/simple-setup.zip b/simple-setup.zip
new file mode 100644
index 0000000000000000000000000000000000000000..f18b6babcde1654a04c69f340ae8d952783d313a
GIT binary patch
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diff --git a/simple-setup/main.c b/simple-setup/main.c
index 3dcd243..d191d41 100644
--- a/simple-setup/main.c
+++ b/simple-setup/main.c
@@ -11,9 +11,9 @@ int main() {
ST7735_Init(); // Initialise the screen
ST7735_FillScreen(ST7735_RED);
- /*char name[21];
- printf("\n\n\n\nyour name? (max 20 chars):\n");
- scanf("%20s", name);
+ //char name[21];
+ //printf("\n\n\n\nyour name? (max 20 chars):\n");
+ //scanf("%20s", name);
//fread(name, 1, 20, stdin); - doesn't seem to work properly
// serial input sends stuff in real time to the pi,
@@ -21,11 +21,11 @@ int main() {
// and since you filled it with characters, the %d scanf's from the while (true)
// loop will halt immediately because there's invalid data on the stdin buffer (???)
- char ch;
+ /*char ch;
do {
ch = getchar();
printf("clearing buffer: %d\n", ch);
- } while (true);
+ } while (true);*/
int opt = 0;
int a = 0;
@@ -33,7 +33,7 @@ int main() {
int c = 0;
while (true) {
- printf("Hi %s!\nWhich variable would you want to change?\n1: a\n2: b\n3: c\n", name);
+ printf("Hi!\nWhich variable would you want to change?\n1: a\n2: b\n3: c\n");
scanf("%d", &opt);
switch (opt) {
@@ -55,5 +55,5 @@ int main() {
printf("\nVariables are now: a=%d, b=%d, c=%d\n", a, b, c);
}
- return 0;*/
+ return 0;
}
--
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